Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 (68762f3d) · Commits · e / devices / android_kernel_xiaomi_nabu

MAINTAINERS

+10 −0

Original line number	Original line	Diff line number	Diff line
	@@ -2228,6 +2228,16 @@ M: philb@gnu.org
	W: http://www.tazenda.demon.co.uk/phil/linux-hp		W: http://www.tazenda.demon.co.uk/phil/linux-hp
	S: Maintained		S: Maintained

			MAC80211
			P: Jiri Benc
			M: jbenc@suse.cz
			P: Michael Wu
			M: flamingice@sourmilk.net
			L: linux-wireless@vger.kernel.org
			W: http://linuxwireless.org/
			T: git kernel.org:/pub/scm/linux/kernel/git/jbenc/mac80211.git
			S: Maintained

	MARVELL YUKON / SYSKONNECT DRIVER		MARVELL YUKON / SYSKONNECT DRIVER
	P: Mirko Lindner		P: Mirko Lindner
	M: mlindner@syskonnect.de		M: mlindner@syskonnect.de

drivers/net/tg3.c

+89 −78

Original line number	Original line	Diff line number	Diff line
	@@ -1300,9 +1300,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
	msleep(1);		msleep(1);
	}		}
	}		}
			if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
	tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE \|		tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE \|
	WOL_DRV_STATE_SHUTDOWN \|		WOL_DRV_STATE_SHUTDOWN \|
	WOL_DRV_WOL \| WOL_SET_MAGIC_PKT);		WOL_DRV_WOL \|
			WOL_SET_MAGIC_PKT);

	pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);		pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);

	@@ -2593,10 +2595,8 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
	{		{
	int current_link_up = 0;		int current_link_up = 0;

	if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {		if (!(mac_status & MAC_STATUS_PCS_SYNCED))
	tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
	goto out;		goto out;
	}

	if (tp->link_config.autoneg == AUTONEG_ENABLE) {		if (tp->link_config.autoneg == AUTONEG_ENABLE) {
	u32 flags;		u32 flags;
	@@ -2614,7 +2614,6 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)

	tg3_setup_flow_control(tp, local_adv, remote_adv);		tg3_setup_flow_control(tp, local_adv, remote_adv);

	tp->tg3_flags \|= TG3_FLAG_GOT_SERDES_FLOWCTL;
	current_link_up = 1;		current_link_up = 1;
	}		}
	for (i = 0; i < 30; i++) {		for (i = 0; i < 30; i++) {
	@@ -2637,7 +2636,6 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
	} else {		} else {
	/* Forcing 1000FD link up. */		/* Forcing 1000FD link up. */
	current_link_up = 1;		current_link_up = 1;
	tp->tg3_flags \|= TG3_FLAG_GOT_SERDES_FLOWCTL;

	tw32_f(MAC_MODE, (tp->mac_mode \| MAC_MODE_SEND_CONFIGS));		tw32_f(MAC_MODE, (tp->mac_mode \| MAC_MODE_SEND_CONFIGS));
	udelay(40);		udelay(40);
	@@ -3895,8 +3893,7 @@ static int tg3_start_xmit(struct sk_buff skb, struct net_device dev)
	entry = tp->tx_prod;		entry = tp->tx_prod;
	base_flags = 0;		base_flags = 0;
	mss = 0;		mss = 0;
	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&		if ((mss = skb_shinfo(skb)->gso_size) != 0) {
	(mss = skb_shinfo(skb)->gso_size) != 0) {
	int tcp_opt_len, ip_tcp_len;		int tcp_opt_len, ip_tcp_len;

	if (skb_header_cloned(skb) &&		if (skb_header_cloned(skb) &&
	@@ -4053,8 +4050,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff skb, struct net_device dev)
	if (skb->ip_summed == CHECKSUM_PARTIAL)		if (skb->ip_summed == CHECKSUM_PARTIAL)
	base_flags \|= TXD_FLAG_TCPUDP_CSUM;		base_flags \|= TXD_FLAG_TCPUDP_CSUM;
	mss = 0;		mss = 0;
	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&		if ((mss = skb_shinfo(skb)->gso_size) != 0) {
	(mss = skb_shinfo(skb)->gso_size) != 0) {
	struct iphdr *iph;		struct iphdr *iph;
	int tcp_opt_len, ip_tcp_len, hdr_len;		int tcp_opt_len, ip_tcp_len, hdr_len;

	@@ -5934,7 +5930,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp)


	/* tp->lock is held. */		/* tp->lock is held. */
	static void __tg3_set_mac_addr(struct tg3 *tp)		static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
	{		{
	u32 addr_high, addr_low;		u32 addr_high, addr_low;
	int i;		int i;
	@@ -5946,6 +5942,8 @@ static void __tg3_set_mac_addr(struct tg3 *tp)
	(tp->dev->dev_addr[4] << 8) \|		(tp->dev->dev_addr[4] << 8) \|
	(tp->dev->dev_addr[5] << 0));		(tp->dev->dev_addr[5] << 0));
	for (i = 0; i < 4; i++) {		for (i = 0; i < 4; i++) {
			if (i == 1 && skip_mac_1)
			continue;
	tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);		tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
	tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);		tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
	}		}
	@@ -5972,7 +5970,7 @@ static int tg3_set_mac_addr(struct net_device dev, void p)
	{		{
	struct tg3 *tp = netdev_priv(dev);		struct tg3 *tp = netdev_priv(dev);
	struct sockaddr *addr = p;		struct sockaddr *addr = p;
	int err = 0;		int err = 0, skip_mac_1 = 0;

	if (!is_valid_ether_addr(addr->sa_data))		if (!is_valid_ether_addr(addr->sa_data))
	return -EINVAL;		return -EINVAL;
	@@ -5983,22 +5981,21 @@ static int tg3_set_mac_addr(struct net_device dev, void p)
	return 0;		return 0;

	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
	/* Reset chip so that ASF can re-init any MAC addresses it		u32 addr0_high, addr0_low, addr1_high, addr1_low;
	* needs.
	*/
	tg3_netif_stop(tp);
	tg3_full_lock(tp, 1);

	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);		addr0_high = tr32(MAC_ADDR_0_HIGH);
	err = tg3_restart_hw(tp, 0);		addr0_low = tr32(MAC_ADDR_0_LOW);
	if (!err)		addr1_high = tr32(MAC_ADDR_1_HIGH);
	tg3_netif_start(tp);		addr1_low = tr32(MAC_ADDR_1_LOW);
	tg3_full_unlock(tp);
	} else {		/* Skip MAC addr 1 if ASF is using it. */
			if ((addr0_high != addr1_high \|\| addr0_low != addr1_low) &&
			!(addr1_high == 0 && addr1_low == 0))
			skip_mac_1 = 1;
			}
	spin_lock_bh(&tp->lock);		spin_lock_bh(&tp->lock);
	__tg3_set_mac_addr(tp);		__tg3_set_mac_addr(tp, skip_mac_1);
	spin_unlock_bh(&tp->lock);		spin_unlock_bh(&tp->lock);
	}

	return err;		return err;
	}		}
	@@ -6315,7 +6312,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
	tp->rx_jumbo_ptr);		tp->rx_jumbo_ptr);

	/* Initialize MAC address and backoff seed. */		/* Initialize MAC address and backoff seed. */
	__tg3_set_mac_addr(tp);		__tg3_set_mac_addr(tp, 0);

	/* MTU + ethernet header + FCS + optional VLAN tag */		/* MTU + ethernet header + FCS + optional VLAN tag */
	tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);		tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
	@@ -6346,8 +6343,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
	tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) \|\|		tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) \|\|
	(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {		(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
	if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
	(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 \|\|		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
	tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
	rdmac_mode \|= RDMAC_MODE_FIFO_SIZE_128;		rdmac_mode \|= RDMAC_MODE_FIFO_SIZE_128;
	} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&		} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
	!(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {		!(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
	@@ -6457,6 +6453,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
	gpio_mask \|= GRC_LCLCTRL_GPIO_UART_SEL;		gpio_mask \|= GRC_LCLCTRL_GPIO_UART_SEL;

			tp->grc_local_ctrl &= ~gpio_mask;
	tp->grc_local_ctrl \|= tr32(GRC_LOCAL_CTRL) & gpio_mask;		tp->grc_local_ctrl \|= tr32(GRC_LOCAL_CTRL) & gpio_mask;

	/* GPIO1 must be driven high for eeprom write protect */		/* GPIO1 must be driven high for eeprom write protect */
	@@ -7036,11 +7033,7 @@ static int tg3_open(struct net_device *dev)
	if (err)		if (err)
	return err;		return err;

	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&		if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
	(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
	(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
	!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
	(tp->pdev_peer == tp->pdev))) {
	/* All MSI supporting chips should support tagged		/* All MSI supporting chips should support tagged
	* status. Assert that this is the case.		* status. Assert that this is the case.
	*/		*/
	@@ -7399,9 +7392,7 @@ static int tg3_close(struct net_device *dev)

	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
	tg3_free_rings(tp);		tg3_free_rings(tp);
	tp->tg3_flags &=		tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
	~(TG3_FLAG_INIT_COMPLETE \|
	TG3_FLAG_GOT_SERDES_FLOWCTL);

	tg3_full_unlock(tp);		tg3_full_unlock(tp);

	@@ -8036,7 +8027,10 @@ static void tg3_get_wol(struct net_device dev, struct ethtool_wolinfo wol)
	{		{
	struct tg3 *tp = netdev_priv(dev);		struct tg3 *tp = netdev_priv(dev);

			if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
	wol->supported = WAKE_MAGIC;		wol->supported = WAKE_MAGIC;
			else
			wol->supported = 0;
	wol->wolopts = 0;		wol->wolopts = 0;
	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)		if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
	wol->wolopts = WAKE_MAGIC;		wol->wolopts = WAKE_MAGIC;
	@@ -8050,8 +8044,7 @@ static int tg3_set_wol(struct net_device dev, struct ethtool_wolinfo wol)
	if (wol->wolopts & ~WAKE_MAGIC)		if (wol->wolopts & ~WAKE_MAGIC)
	return -EINVAL;		return -EINVAL;
	if ((wol->wolopts & WAKE_MAGIC) &&		if ((wol->wolopts & WAKE_MAGIC) &&
	tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&		!(tp->tg3_flags & TG3_FLAG_WOL_CAP))
	!(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
	return -EINVAL;		return -EINVAL;

	spin_lock_bh(&tp->lock);		spin_lock_bh(&tp->lock);
	@@ -9289,7 +9282,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp)
	return;		return;
	}		}
	}		}
	tp->nvram_size = 0x20000;		tp->nvram_size = 0x80000;
	}		}

	static void __devinit tg3_get_nvram_info(struct tg3 *tp)		static void __devinit tg3_get_nvram_info(struct tg3 *tp)
	@@ -9408,33 +9401,31 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)

	static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)		static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
	{		{
	u32 nvcfg1;		u32 nvcfg1, protect = 0;

	nvcfg1 = tr32(NVRAM_CFG1);		nvcfg1 = tr32(NVRAM_CFG1);

	/* NVRAM protection for TPM */		/* NVRAM protection for TPM */
	if (nvcfg1 & (1 << 27))		if (nvcfg1 & (1 << 27)) {
	tp->tg3_flags2 \|= TG3_FLG2_PROTECTED_NVRAM;		tp->tg3_flags2 \|= TG3_FLG2_PROTECTED_NVRAM;
			protect = 1;
			}

	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {		nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
	case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:		switch (nvcfg1) {
	case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
	tp->nvram_jedecnum = JEDEC_ATMEL;
	tp->tg3_flags \|= TG3_FLAG_NVRAM_BUFFERED;
	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;

	nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
	tw32(NVRAM_CFG1, nvcfg1);
	break;
	case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
	case FLASH_5755VENDOR_ATMEL_FLASH_1:		case FLASH_5755VENDOR_ATMEL_FLASH_1:
	case FLASH_5755VENDOR_ATMEL_FLASH_2:		case FLASH_5755VENDOR_ATMEL_FLASH_2:
	case FLASH_5755VENDOR_ATMEL_FLASH_3:		case FLASH_5755VENDOR_ATMEL_FLASH_3:
	case FLASH_5755VENDOR_ATMEL_FLASH_4:
	tp->nvram_jedecnum = JEDEC_ATMEL;		tp->nvram_jedecnum = JEDEC_ATMEL;
	tp->tg3_flags \|= TG3_FLAG_NVRAM_BUFFERED;		tp->tg3_flags \|= TG3_FLAG_NVRAM_BUFFERED;
	tp->tg3_flags2 \|= TG3_FLG2_FLASH;		tp->tg3_flags2 \|= TG3_FLG2_FLASH;
	tp->nvram_pagesize = 264;		tp->nvram_pagesize = 264;
			if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
			tp->nvram_size = (protect ? 0x3e200 : 0x80000);
			else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
			tp->nvram_size = (protect ? 0x1f200 : 0x40000);
			else
			tp->nvram_size = (protect ? 0x1f200 : 0x20000);
	break;		break;
	case FLASH_5752VENDOR_ST_M45PE10:		case FLASH_5752VENDOR_ST_M45PE10:
	case FLASH_5752VENDOR_ST_M45PE20:		case FLASH_5752VENDOR_ST_M45PE20:
	@@ -9443,6 +9434,12 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
	tp->tg3_flags \|= TG3_FLAG_NVRAM_BUFFERED;		tp->tg3_flags \|= TG3_FLAG_NVRAM_BUFFERED;
	tp->tg3_flags2 \|= TG3_FLG2_FLASH;		tp->tg3_flags2 \|= TG3_FLG2_FLASH;
	tp->nvram_pagesize = 256;		tp->nvram_pagesize = 256;
			if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
			tp->nvram_size = (protect ? 0x10000 : 0x20000);
			else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
			tp->nvram_size = (protect ? 0x10000 : 0x40000);
			else
			tp->nvram_size = (protect ? 0x20000 : 0x80000);
	break;		break;
	}		}
	}		}
	@@ -9518,6 +9515,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
	}		}
	tg3_enable_nvram_access(tp);		tg3_enable_nvram_access(tp);

			tp->nvram_size = 0;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
	tg3_get_5752_nvram_info(tp);		tg3_get_5752_nvram_info(tp);
	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
	@@ -9529,6 +9528,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
	else		else
	tg3_get_nvram_info(tp);		tg3_get_nvram_info(tp);

			if (tp->nvram_size == 0)
	tg3_get_nvram_size(tp);		tg3_get_nvram_size(tp);

	tg3_disable_nvram_access(tp);		tg3_disable_nvram_access(tp);
	@@ -9996,8 +9996,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
	tp->phy_id = PHY_ID_INVALID;		tp->phy_id = PHY_ID_INVALID;
	tp->led_ctrl = LED_CTRL_MODE_PHY_1;		tp->led_ctrl = LED_CTRL_MODE_PHY_1;

	/* Assume an onboard device by default. */		/* Assume an onboard device and WOL capable by default. */
	tp->tg3_flags \|= TG3_FLAG_EEPROM_WRITE_PROT;		tp->tg3_flags \|= TG3_FLAG_EEPROM_WRITE_PROT \| TG3_FLAG_WOL_CAP;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
	if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {		if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
	@@ -10120,8 +10120,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
	tp->tg3_flags2 \|= TG3_FLG2_ASF_NEW_HANDSHAKE;		tp->tg3_flags2 \|= TG3_FLG2_ASF_NEW_HANDSHAKE;
	}		}
	if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)		if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
	tp->tg3_flags \|= TG3_FLAG_SERDES_WOL_CAP;		!(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
			tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;

	if (cfg2 & (1 << 17))		if (cfg2 & (1 << 17))
	tp->tg3_flags2 \|= TG3_FLG2_CAPACITIVE_COUPLING;		tp->tg3_flags2 \|= TG3_FLG2_CAPACITIVE_COUPLING;
	@@ -10399,6 +10400,8 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
	}		}
	}		}

			static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);

	static int __devinit tg3_get_invariants(struct tg3 *tp)		static int __devinit tg3_get_invariants(struct tg3 *tp)
	{		{
	static struct pci_device_id write_reorder_chipsets[] = {		static struct pci_device_id write_reorder_chipsets[] = {
	@@ -10554,6 +10557,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;		tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
	tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;		tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;

			if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) \|\|
			(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
			tp->pdev_peer = tg3_find_peer(tp);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 \|\|		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 \|\|
	GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 \|\|		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 \|\|
	GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 \|\|		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 \|\|
	@@ -10567,6 +10574,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	tp->tg3_flags2 \|= TG3_FLG2_5705_PLUS;		tp->tg3_flags2 \|= TG3_FLG2_5705_PLUS;

	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
			tp->tg3_flags \|= TG3_FLAG_SUPPORT_MSI;
			if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX \|\|
			GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX \|\|
			(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
			tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
			tp->pdev_peer == tp->pdev))
			tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 \|\|		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 \|\|
	GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 \|\|		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 \|\|
	GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
	@@ -10668,17 +10683,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)		if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
	tp->tg3_flags \|= TG3_FLAG_TXD_MBOX_HWBUG;		tp->tg3_flags \|= TG3_FLAG_TXD_MBOX_HWBUG;

	/* Back to back register writes can cause problems on this chip,
	* the workaround is to read back all reg writes except those to
	* mailbox regs. See tg3_write_indirect_reg32().
	*
	* PCI Express 5750_A0 rev chips need this workaround too.
	*/
	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 \|\|
	((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
	tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
	tp->tg3_flags \|= TG3_FLAG_5701_REG_WRITE_BUG;

	if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)		if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
	tp->tg3_flags \|= TG3_FLAG_PCI_HIGH_SPEED;		tp->tg3_flags \|= TG3_FLAG_PCI_HIGH_SPEED;
	if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)		if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
	@@ -10702,8 +10706,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
	/* Various workaround register access methods */		/* Various workaround register access methods */
	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)		if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
	tp->write32 = tg3_write_indirect_reg32;		tp->write32 = tg3_write_indirect_reg32;
	else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)		else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 \|\|
			((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
			tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
			/*
			* Back to back register writes can cause problems on these
			* chips, the workaround is to read back all reg writes
			* except those to mailbox regs.
			*
			* See tg3_write_indirect_reg32().
			*/
	tp->write32 = tg3_write_flush_reg32;		tp->write32 = tg3_write_flush_reg32;
			}


	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) \|\|		if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) \|\|
	(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {		(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
	@@ -11892,10 +11907,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
	tp->rx_pending = 63;		tp->rx_pending = 63;
	}		}

	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) \|\|
	(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
	tp->pdev_peer = tg3_find_peer(tp);

	err = tg3_get_device_address(tp);		err = tg3_get_device_address(tp);
	if (err) {		if (err) {
	printk(KERN_ERR PFX "Could not obtain valid ethernet address, "		printk(KERN_ERR PFX "Could not obtain valid ethernet address, "

drivers/net/tg3.h

+3 −3

include/linux/ieee80211.h

0 → 100644

+342 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* IEEE 802.11 defines
			*
			* Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
			* <jkmaline@cc.hut.fi>
			* Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
			* Copyright (c) 2005, Devicescape Software, Inc.
			* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
			*
			* This program is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License version 2 as
			* published by the Free Software Foundation.
			*/

			#ifndef IEEE80211_H
			#define IEEE80211_H

			#include <linux/types.h>

			#define FCS_LEN 4

			#define IEEE80211_FCTL_VERS 0x0003
			#define IEEE80211_FCTL_FTYPE 0x000c
			#define IEEE80211_FCTL_STYPE 0x00f0
			#define IEEE80211_FCTL_TODS 0x0100
			#define IEEE80211_FCTL_FROMDS 0x0200
			#define IEEE80211_FCTL_MOREFRAGS 0x0400
			#define IEEE80211_FCTL_RETRY 0x0800
			#define IEEE80211_FCTL_PM 0x1000
			#define IEEE80211_FCTL_MOREDATA 0x2000
			#define IEEE80211_FCTL_PROTECTED 0x4000
			#define IEEE80211_FCTL_ORDER 0x8000

			#define IEEE80211_SCTL_FRAG 0x000F
			#define IEEE80211_SCTL_SEQ 0xFFF0

			#define IEEE80211_FTYPE_MGMT 0x0000
			#define IEEE80211_FTYPE_CTL 0x0004
			#define IEEE80211_FTYPE_DATA 0x0008

			/* management */
			#define IEEE80211_STYPE_ASSOC_REQ 0x0000
			#define IEEE80211_STYPE_ASSOC_RESP 0x0010
			#define IEEE80211_STYPE_REASSOC_REQ 0x0020
			#define IEEE80211_STYPE_REASSOC_RESP 0x0030
			#define IEEE80211_STYPE_PROBE_REQ 0x0040
			#define IEEE80211_STYPE_PROBE_RESP 0x0050
			#define IEEE80211_STYPE_BEACON 0x0080
			#define IEEE80211_STYPE_ATIM 0x0090
			#define IEEE80211_STYPE_DISASSOC 0x00A0
			#define IEEE80211_STYPE_AUTH 0x00B0
			#define IEEE80211_STYPE_DEAUTH 0x00C0
			#define IEEE80211_STYPE_ACTION 0x00D0

			/* control */
			#define IEEE80211_STYPE_PSPOLL 0x00A0
			#define IEEE80211_STYPE_RTS 0x00B0
			#define IEEE80211_STYPE_CTS 0x00C0
			#define IEEE80211_STYPE_ACK 0x00D0
			#define IEEE80211_STYPE_CFEND 0x00E0
			#define IEEE80211_STYPE_CFENDACK 0x00F0

			/* data */
			#define IEEE80211_STYPE_DATA 0x0000
			#define IEEE80211_STYPE_DATA_CFACK 0x0010
			#define IEEE80211_STYPE_DATA_CFPOLL 0x0020
			#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030
			#define IEEE80211_STYPE_NULLFUNC 0x0040
			#define IEEE80211_STYPE_CFACK 0x0050
			#define IEEE80211_STYPE_CFPOLL 0x0060
			#define IEEE80211_STYPE_CFACKPOLL 0x0070
			#define IEEE80211_STYPE_QOS_DATA 0x0080
			#define IEEE80211_STYPE_QOS_DATA_CFACK 0x0090
			#define IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0
			#define IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0
			#define IEEE80211_STYPE_QOS_NULLFUNC 0x00C0
			#define IEEE80211_STYPE_QOS_CFACK 0x00D0
			#define IEEE80211_STYPE_QOS_CFPOLL 0x00E0
			#define IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0


			/* miscellaneous IEEE 802.11 constants */
			#define IEEE80211_MAX_FRAG_THRESHOLD 2346
			#define IEEE80211_MAX_RTS_THRESHOLD 2347
			#define IEEE80211_MAX_AID 2007
			#define IEEE80211_MAX_TIM_LEN 251
			#define IEEE80211_MAX_DATA_LEN 2304
			/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
			6.2.1.1.2.

			The figure in section 7.1.2 suggests a body size of up to 2312
			bytes is allowed, which is a bit confusing, I suspect this
			represents the 2304 bytes of real data, plus a possible 8 bytes of
			WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */

			#define IEEE80211_MAX_SSID_LEN 32

			struct ieee80211_hdr {
			__le16 frame_control;
			__le16 duration_id;
			u8 addr1[6];
			u8 addr2[6];
			u8 addr3[6];
			__le16 seq_ctrl;
			u8 addr4[6];
			} __attribute__ ((packed));


			struct ieee80211_mgmt {
			__le16 frame_control;
			__le16 duration;
			u8 da[6];
			u8 sa[6];
			u8 bssid[6];
			__le16 seq_ctrl;
			union {
			struct {
			__le16 auth_alg;
			__le16 auth_transaction;
			__le16 status_code;
			/* possibly followed by Challenge text */
			u8 variable[0];
			} __attribute__ ((packed)) auth;
			struct {
			__le16 reason_code;
			} __attribute__ ((packed)) deauth;
			struct {
			__le16 capab_info;
			__le16 listen_interval;
			/* followed by SSID and Supported rates */
			u8 variable[0];
			} __attribute__ ((packed)) assoc_req;
			struct {
			__le16 capab_info;
			__le16 status_code;
			__le16 aid;
			/* followed by Supported rates */
			u8 variable[0];
			} __attribute__ ((packed)) assoc_resp, reassoc_resp;
			struct {
			__le16 capab_info;
			__le16 listen_interval;
			u8 current_ap[6];
			/* followed by SSID and Supported rates */
			u8 variable[0];
			} __attribute__ ((packed)) reassoc_req;
			struct {
			__le16 reason_code;
			} __attribute__ ((packed)) disassoc;
			struct {
			__le64 timestamp;
			__le16 beacon_int;
			__le16 capab_info;
			/* followed by some of SSID, Supported rates,
			* FH Params, DS Params, CF Params, IBSS Params, TIM */
			u8 variable[0];
			} __attribute__ ((packed)) beacon;
			struct {
			/* only variable items: SSID, Supported rates */
			u8 variable[0];
			} __attribute__ ((packed)) probe_req;
			struct {
			__le64 timestamp;
			__le16 beacon_int;
			__le16 capab_info;
			/* followed by some of SSID, Supported rates,
			* FH Params, DS Params, CF Params, IBSS Params */
			u8 variable[0];
			} __attribute__ ((packed)) probe_resp;
			struct {
			u8 category;
			union {
			struct {
			u8 action_code;
			u8 dialog_token;
			u8 status_code;
			u8 variable[0];
			} __attribute__ ((packed)) wme_action;
			struct{
			u8 action_code;
			u8 element_id;
			u8 length;
			u8 switch_mode;
			u8 new_chan;
			u8 switch_count;
			} __attribute__((packed)) chan_switch;
			} u;
			} __attribute__ ((packed)) action;
			} u;
			} __attribute__ ((packed));


			/* Control frames */
			struct ieee80211_rts {
			__le16 frame_control;
			__le16 duration;
			u8 ra[6];
			u8 ta[6];
			} __attribute__ ((packed));

			struct ieee80211_cts {
			__le16 frame_control;
			__le16 duration;
			u8 ra[6];
			} __attribute__ ((packed));


			/* Authentication algorithms */
			#define WLAN_AUTH_OPEN 0
			#define WLAN_AUTH_SHARED_KEY 1
			#define WLAN_AUTH_FAST_BSS_TRANSITION 2
			#define WLAN_AUTH_LEAP 128

			#define WLAN_AUTH_CHALLENGE_LEN 128

			#define WLAN_CAPABILITY_ESS (1<<0)
			#define WLAN_CAPABILITY_IBSS (1<<1)
			#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
			#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
			#define WLAN_CAPABILITY_PRIVACY (1<<4)
			#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
			#define WLAN_CAPABILITY_PBCC (1<<6)
			#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
			/* 802.11h */
			#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8)
			#define WLAN_CAPABILITY_QOS (1<<9)
			#define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10)
			#define WLAN_CAPABILITY_DSSS_OFDM (1<<13)

			/* Status codes */
			enum ieee80211_statuscode {
			WLAN_STATUS_SUCCESS = 0,
			WLAN_STATUS_UNSPECIFIED_FAILURE = 1,
			WLAN_STATUS_CAPS_UNSUPPORTED = 10,
			WLAN_STATUS_REASSOC_NO_ASSOC = 11,
			WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,
			WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,
			WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,
			WLAN_STATUS_CHALLENGE_FAIL = 15,
			WLAN_STATUS_AUTH_TIMEOUT = 16,
			WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,
			WLAN_STATUS_ASSOC_DENIED_RATES = 18,
			/* 802.11b */
			WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,
			WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,
			WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,
			/* 802.11h */
			WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,
			WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,
			WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,
			/* 802.11g */
			WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,
			WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,
			/* 802.11i */
			WLAN_STATUS_INVALID_IE = 40,
			WLAN_STATUS_INVALID_GROUP_CIPHER = 41,
			WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,
			WLAN_STATUS_INVALID_AKMP = 43,
			WLAN_STATUS_UNSUPP_RSN_VERSION = 44,
			WLAN_STATUS_INVALID_RSN_IE_CAP = 45,
			WLAN_STATUS_CIPHER_SUITE_REJECTED = 46,
			};


			/* Reason codes */
			enum ieee80211_reasoncode {
			WLAN_REASON_UNSPECIFIED = 1,
			WLAN_REASON_PREV_AUTH_NOT_VALID = 2,
			WLAN_REASON_DEAUTH_LEAVING = 3,
			WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,
			WLAN_REASON_DISASSOC_AP_BUSY = 5,
			WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,
			WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,
			WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,
			WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,
			/* 802.11h */
			WLAN_REASON_DISASSOC_BAD_POWER = 10,
			WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,
			/* 802.11i */
			WLAN_REASON_INVALID_IE = 13,
			WLAN_REASON_MIC_FAILURE = 14,
			WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,
			WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,
			WLAN_REASON_IE_DIFFERENT = 17,
			WLAN_REASON_INVALID_GROUP_CIPHER = 18,
			WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,
			WLAN_REASON_INVALID_AKMP = 20,
			WLAN_REASON_UNSUPP_RSN_VERSION = 21,
			WLAN_REASON_INVALID_RSN_IE_CAP = 22,
			WLAN_REASON_IEEE8021X_FAILED = 23,
			WLAN_REASON_CIPHER_SUITE_REJECTED = 24,
			};


			/* Information Element IDs */
			enum ieee80211_eid {
			WLAN_EID_SSID = 0,
			WLAN_EID_SUPP_RATES = 1,
			WLAN_EID_FH_PARAMS = 2,
			WLAN_EID_DS_PARAMS = 3,
			WLAN_EID_CF_PARAMS = 4,
			WLAN_EID_TIM = 5,
			WLAN_EID_IBSS_PARAMS = 6,
			WLAN_EID_CHALLENGE = 16,
			/* 802.11d */
			WLAN_EID_COUNTRY = 7,
			WLAN_EID_HP_PARAMS = 8,
			WLAN_EID_HP_TABLE = 9,
			WLAN_EID_REQUEST = 10,
			/* 802.11h */
			WLAN_EID_PWR_CONSTRAINT = 32,
			WLAN_EID_PWR_CAPABILITY = 33,
			WLAN_EID_TPC_REQUEST = 34,
			WLAN_EID_TPC_REPORT = 35,
			WLAN_EID_SUPPORTED_CHANNELS = 36,
			WLAN_EID_CHANNEL_SWITCH = 37,
			WLAN_EID_MEASURE_REQUEST = 38,
			WLAN_EID_MEASURE_REPORT = 39,
			WLAN_EID_QUIET = 40,
			WLAN_EID_IBSS_DFS = 41,
			/* 802.11g */
			WLAN_EID_ERP_INFO = 42,
			WLAN_EID_EXT_SUPP_RATES = 50,
			/* 802.11i */
			WLAN_EID_RSN = 48,
			WLAN_EID_WPA = 221,
			WLAN_EID_GENERIC = 221,
			WLAN_EID_VENDOR_SPECIFIC = 221,
			WLAN_EID_QOS_PARAMETER = 222
			};

			/* cipher suite selectors */
			#define WLAN_CIPHER_SUITE_USE_GROUP 0x000FAC00
			#define WLAN_CIPHER_SUITE_WEP40 0x000FAC01
			#define WLAN_CIPHER_SUITE_TKIP 0x000FAC02
			/* reserved: 0x000FAC03 */
			#define WLAN_CIPHER_SUITE_CCMP 0x000FAC04
			#define WLAN_CIPHER_SUITE_WEP104 0x000FAC05

			#define WLAN_MAX_KEY_LEN 32

			#endif /* IEEE80211_H */

include/linux/netlink.h

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -31,7 +31,7 @@ struct sockaddr_nl
	{		{
	sa_family_t nl_family; /* AF_NETLINK */		sa_family_t nl_family; /* AF_NETLINK */
	unsigned short nl_pad; /* zero */		unsigned short nl_pad; /* zero */
	__u32 nl_pid; /* process pid */		__u32 nl_pid; /* port ID */
	__u32 nl_groups; /* multicast groups mask */		__u32 nl_groups; /* multicast groups mask */
	};		};

	@@ -41,7 +41,7 @@ struct nlmsghdr
	__u16 nlmsg_type; /* Message content */		__u16 nlmsg_type; /* Message content */
	__u16 nlmsg_flags; /* Additional flags */		__u16 nlmsg_flags; /* Additional flags */
	__u32 nlmsg_seq; /* Sequence number */		__u32 nlmsg_seq; /* Sequence number */
	__u32 nlmsg_pid; /* Sending process PID */		__u32 nlmsg_pid; /* Sending process port ID */
	};		};

	/* Flags values */		/* Flags values */

Original line number	Original line	Diff line number	Diff line
	@@ -131,6 +131,7 @@
	#define CHIPREV_ID_5752_A0_HW 0x5000		#define CHIPREV_ID_5752_A0_HW 0x5000
	#define CHIPREV_ID_5752_A0 0x6000		#define CHIPREV_ID_5752_A0 0x6000
	#define CHIPREV_ID_5752_A1 0x6001		#define CHIPREV_ID_5752_A1 0x6001
			#define CHIPREV_ID_5714_A2 0x9002
	#define CHIPREV_ID_5906_A1 0xc001		#define CHIPREV_ID_5906_A1 0xc001
	#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)		#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
	#define ASIC_REV_5700 0x07		#define ASIC_REV_5700 0x07
	@@ -2199,7 +2200,6 @@ struct tg3 {
	#define TG3_FLAG_USE_LINKCHG_REG 0x00000008		#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
	#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010		#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
	#define TG3_FLAG_ENABLE_ASF 0x00000020		#define TG3_FLAG_ENABLE_ASF 0x00000020
	#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
	#define TG3_FLAG_POLL_SERDES 0x00000080		#define TG3_FLAG_POLL_SERDES 0x00000080
	#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100		#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
	#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200		#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
	@@ -2215,14 +2215,14 @@ struct tg3 {
	#define TG3_FLAG_PCI_32BIT 0x00080000		#define TG3_FLAG_PCI_32BIT 0x00080000
	#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000		#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
	#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000		#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
	#define TG3_FLAG_SERDES_WOL_CAP 0x00400000		#define TG3_FLAG_WOL_CAP 0x00400000
	#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000		#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
	#define TG3_FLAG_10_100_ONLY 0x01000000		#define TG3_FLAG_10_100_ONLY 0x01000000
	#define TG3_FLAG_PAUSE_AUTONEG 0x02000000		#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
	#define TG3_FLAG_IN_RESET_TASK 0x04000000		#define TG3_FLAG_IN_RESET_TASK 0x04000000
	#define TG3_FLAG_40BIT_DMA_BUG 0x08000000		#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
	#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000		#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
	#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000		#define TG3_FLAG_SUPPORT_MSI 0x20000000
	#define TG3_FLAG_CHIP_RESETTING 0x40000000		#define TG3_FLAG_CHIP_RESETTING 0x40000000
	#define TG3_FLAG_INIT_COMPLETE 0x80000000		#define TG3_FLAG_INIT_COMPLETE 0x80000000
	u32 tg3_flags2;		u32 tg3_flags2;