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Commit 6875db29 authored by Rishabh Bhatnagar's avatar Rishabh Bhatnagar Committed by Gerrit - the friendly Code Review server
Browse files

pinctrl: Add wakeup gpio register and bit information 



Add wake_reg and wake_bit fields into msm_pingroup structure.
This will be used to configure gpios as wakeup capable.

Change-Id: I19237d16132f014496e9a8a1c718d492e290d5fe
Signed-off-by: default avatarRishabh Bhatnagar <rishabhb@codeaurora.org>
parent 3ef8b8d6

drivers/pinctrl/qcom/pinctrl-atoll.c

+177 −120
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
#define WEST	0x00100000

#define DUMMY	0x0

#define REG_SIZE 0x1000

#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\

#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, wake_off, bit) \

	{						\

		.name = "gpio" #id,			\

		.pins = gpio##id##_pins,		\
@@ -70,6 +70,8 @@ 
		.intr_detection_bit = 2,	\

		.intr_detection_width = 2,	\

		.dir_conn_en_bit = 8,           \

		.wake_reg = base + wake_off,	\

		.wake_bit = bit,		\

	}



#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
@@ -1225,192 +1227,247 @@ static const struct msm_function atoll_functions[] = { 
 */

static const struct msm_pingroup atoll_groups[] = {

	[0] = PINGROUP(0, SOUTH, qup01, cri_trng, NA, phase_flag0, NA, NA, NA,

		       NA, NA),

		       NA, NA, 0x77000, 5),

	[1] = PINGROUP(1, SOUTH, qup01, cri_trng, NA, phase_flag1, NA, NA, NA,

		       NA, NA),

		       NA, NA, 0, -1),

	[2] = PINGROUP(2, SOUTH, qup01, cri_trng, NA, phase_flag3, NA, NA, NA,

		       NA, NA),

		       NA, NA, 0, -1),

	[3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, NA, NA, NA,

		       NA, NA),

	[4] = PINGROUP(4, NORTH, sdc1_tb, NA, qdss_cti, NA, NA, NA, NA, NA, NA),

	[5] = PINGROUP(5, NORTH, sdc2_tb, NA, NA, NA, NA, NA, NA, NA, NA),

	[6] = PINGROUP(6, NORTH, qup11, qup11, NA, NA, NA, NA, NA, NA, NA),

		       NA, NA, 0x77000, 6),

	[4] = PINGROUP(4, NORTH, sdc1_tb, NA, qdss_cti, NA, NA, NA, NA, NA, NA,

			0x77000, 0),

	[5] = PINGROUP(5, NORTH, sdc2_tb, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 1),

	[6] = PINGROUP(6, NORTH, qup11, qup11, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 2),

	[7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, NA, NA, NA, NA, NA,

		       NA),

		       NA, 0, -1),

	[8] = PINGROUP(8, NORTH, GP_PDM1, ddr_bist, NA, phase_flag6, qdss_cti,

		       NA, NA, NA, NA),

		       NA, NA, NA, NA, 0, -1),

	[9] = PINGROUP(9, NORTH, ddr_bist, NA, phase_flag9, qdss_cti, NA, NA,

		       NA, NA, NA),

		       NA, NA, NA, 0x77000, 3),

	[10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 4),

	[11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, NA, phase_flag24,

			ddr_pxi2, NA, NA, NA, NA),

			ddr_pxi2, NA, NA, NA, NA, 0x77000, 5),

	[12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, NA, phase_flag4,

			wlan2_adc0, atest_usb10, ddr_pxi3, NA),

			wlan2_adc0, atest_usb10, ddr_pxi3, NA, 0, -1),

	[13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss_gpio0, NA, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0, -1),

	[14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss_gpio1, NA, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0, -1),

	[15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss_gpio2, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0, -1),

	[16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss_gpio3, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0x77000, 7),

	[17] = PINGROUP(17, SOUTH, cci_i2c, NA, phase_flag20, qdss_gpio4, NA,

			wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),

			wlan1_adc0, atest_usb12, ddr_pxi1, atest_char, 0, -1),

	[18] = PINGROUP(18, SOUTH, cci_i2c, AGERA_PLL, NA, phase_flag18,

			qdss_gpio5, vsense_trigger, ddr_pxi0, atest_char3, NA),

			qdss_gpio5, vsense_trigger, ddr_pxi0, atest_char3, NA,

			0, -1),

	[19] = PINGROUP(19, SOUTH, cci_i2c, NA, phase_flag2, qdss_gpio6,

			atest_char2, NA, NA, NA, NA),

			atest_char2, NA, NA, NA, NA, 0, -1),

	[20] = PINGROUP(20, SOUTH, cci_i2c, NA, phase_flag10, qdss_gpio7,

			atest_char1, NA, NA, NA, NA),

			atest_char1, NA, NA, NA, NA, 0, -1),

	[21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, NA, qdss_gpio6,

			atest_char0, NA, NA, NA, NA),

			atest_char0, NA, NA, NA, NA, 0x77000, 6),

	[22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, NA, qdss_gpio7, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0x77000, 7),

	[23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss_gpio9, NA, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 8),

	[24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss_gpio15, NA, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 9),

	[25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, NA,

			phase_flag23, qdss_gpio11, NA, NA, NA),

			phase_flag23, qdss_gpio11, NA, NA, NA, 0, -1),

	[26] = PINGROUP(26, SOUTH, cci_async, qup05, NA, phase_flag17,

			qdss_gpio12, atest_tsens, atest_usb11, ddr_pxi2, NA),

			qdss_gpio12, atest_tsens, atest_usb11, ddr_pxi2, NA,

			0x77000, 10),

	[27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, NA, phase_flag27,

			qdss_gpio13, ddr_pxi0, NA, NA),

			qdss_gpio13, ddr_pxi0, NA, NA, 0, -1),

	[28] = PINGROUP(28, SOUTH, cci_i2c, qup05, NA, phase_flag31,

			qdss_gpio14, NA, NA, NA, NA),

	[29] = PINGROUP(29, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA),

	[30] = PINGROUP(30, SOUTH, qdss_gpio, NA, NA, NA, NA, NA, NA, NA, NA),

	[31] = PINGROUP(31, NORTH, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA),

			qdss_gpio14, NA, NA, NA, NA, 0x77000, 11),

	[29] = PINGROUP(29, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[30] = PINGROUP(30, SOUTH, qdss_gpio, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 12),

	[31] = PINGROUP(31, NORTH, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 8),

	[32] = PINGROUP(32, NORTH, NA, phase_flag12, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 9),

	[33] = PINGROUP(33, NORTH, sd_write, NA, phase_flag15, qdss_cti, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 10),

	[34] = PINGROUP(34, SOUTH, qup00, NA, phase_flag14, qdss_gpio8, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0x77000, 13),

	[35] = PINGROUP(35, SOUTH, qup00, NA, phase_flag28, qdss_gpio, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0, -1),

	[36] = PINGROUP(36, SOUTH, qup00, NA, phase_flag29, qdss_gpio15, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 14),

	[37] = PINGROUP(37, SOUTH, qup00, GP_PDM0, NA, phase_flag30,

			qdss_gpio10, NA, NA, NA, NA),

			qdss_gpio10, NA, NA, NA, NA, 0x77000, 15),

	[38] = PINGROUP(38, SOUTH, qup03, NA, phase_flag19, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 16),

	[39] = PINGROUP(39, SOUTH, qup03, NA, phase_flag16, atest_tsens2,

			wlan2_adc1, atest_usb1, NA, NA, NA),

	[40] = PINGROUP(40, SOUTH, qup03, NA, NA, NA, NA, NA, NA, NA, NA),

	[41] = PINGROUP(41, SOUTH, qup03, NA, NA, NA, NA, NA, NA, NA, NA),

			wlan2_adc1, atest_usb1, NA, NA, NA, 0x77000, 17),

	[40] = PINGROUP(40, SOUTH, qup03, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[41] = PINGROUP(41, SOUTH, qup03, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 18),

	[42] = PINGROUP(42, NORTH, qup12, NA, phase_flag22, NA, NA, NA, NA, NA,

			NA),

	[43] = PINGROUP(43, NORTH, qup12, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, 0x77000, 11),

	[43] = PINGROUP(43, NORTH, qup12, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 12),

	[44] = PINGROUP(44, NORTH, qup12, NA, phase_flag21, qdss_cti,

			wlan1_adc1, atest_usb13, ddr_pxi1, NA, NA),

	[45] = PINGROUP(45, NORTH, qup12, qdss_cti, NA, NA, NA, NA, NA, NA, NA),

	[46] = PINGROUP(46, NORTH, qup13, qup13, NA, NA, NA, NA, NA, NA, NA),

	[47] = PINGROUP(47, NORTH, qup13, qup13, NA, NA, NA, NA, NA, NA, NA),

	[48] = PINGROUP(48, NORTH, gcc_gp1, NA, NA, NA, NA, NA, NA, NA, NA),

			wlan1_adc1, atest_usb13, ddr_pxi1, NA, NA, 0, -1),

	[45] = PINGROUP(45, NORTH, qup12, qdss_cti, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 13),

	[46] = PINGROUP(46, NORTH, qup13, qup13, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[47] = PINGROUP(47, NORTH, qup13, qup13, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 14),

	[48] = PINGROUP(48, NORTH, gcc_gp1, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 0),

	[50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, GP_PDM1, NA, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0, -1),

	[51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, NA, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0, -1),

	[52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, NA, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 1),

	[53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss_gpio8, atest_usb22, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 2),

	[54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss_gpio9, atest_usb21, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0, -1),

	[55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss_gpio10, atest_usb20, NA,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 3),

	[56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, NA, phase_flag26,

			qdss_gpio13, NA, NA, NA),

			qdss_gpio13, NA, NA, NA, 0x77000, 4),

	[57] = PINGROUP(57, WEST, lpass_ext, audio_ref, JITTER_BIST, GP_PDM2,

			NA, phase_flag25, qdss_gpio11, NA, NA),

			NA, phase_flag25, qdss_gpio11, NA, NA,

			0x77000, 5),

	[58] = PINGROUP(58, WEST, lpass_ext, NA, phase_flag11, NA, NA, NA, NA,

			NA, NA),

	[59] = PINGROUP(59, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA),

	[60] = PINGROUP(60, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA),

	[61] = PINGROUP(61, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA),

	[62] = PINGROUP(62, NORTH, qup10, tgu_ch3, NA, NA, NA, NA, NA, NA, NA),

			NA, NA, 0x77000, 6),

	[59] = PINGROUP(59, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 15),

	[60] = PINGROUP(60, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[61] = PINGROUP(61, NORTH, qup10, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[62] = PINGROUP(62, NORTH, qup10, tgu_ch3, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 16),

	[63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1,

			mdp_vsync2, mdp_vsync3, tgu_ch0, NA, phase_flag8),

			mdp_vsync2, mdp_vsync3, tgu_ch0, NA, phase_flag8,

			0x77000, 17),

	[64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, NA, phase_flag7,

			NA, NA, NA, NA),

			NA, NA, NA, NA, 0x77000, 18),

	[65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, NA, NA,

			NA, NA, NA),

			NA, NA, NA, 0x77000, 19),

	[66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, NA, NA, NA, NA, NA, NA,

			NA),

	[67] = PINGROUP(67, NORTH, qspi_data, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, 0x77000, 20),

	[67] = PINGROUP(67, NORTH, qspi_data, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 21),

	[68] = PINGROUP(68, NORTH, qspi_cs, qup10, GP_PDM0, NA, NA, NA, NA, NA,

			NA),

	[69] = PINGROUP(69, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, 0x77000, 22),

	[69] = PINGROUP(69, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 7),

	[70] = PINGROUP(70, NORTH, NA, NA, mdp_vsync, ldo_en, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 23),

	[71] = PINGROUP(71, NORTH, NA, mdp_vsync, ldo_update, NA, NA, NA, NA,

			NA, NA),

			NA, NA, 0, -1),

	[72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, NA, qdss_cti, NA,

			NA, NA, NA),

	[73] = PINGROUP(73, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[74] = PINGROUP(74, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[75] = PINGROUP(75, WEST, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA),

	[76] = PINGROUP(76, WEST, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA),

	[77] = PINGROUP(77, WEST, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA),

	[78] = PINGROUP(78, WEST, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA),

	[79] = PINGROUP(79, WEST, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA),

	[80] = PINGROUP(80, WEST, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA),

	[81] = PINGROUP(81, WEST, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA),

	[82] = PINGROUP(82, WEST, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, NA, NA, 0x77000, 24),

	[73] = PINGROUP(73, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 8),

	[74] = PINGROUP(74, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 9),

	[75] = PINGROUP(75, WEST, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[76] = PINGROUP(76, WEST, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[77] = PINGROUP(77, WEST, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[78] = PINGROUP(78, WEST, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 10),

	[79] = PINGROUP(79, WEST, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[80] = PINGROUP(80, WEST, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[81] = PINGROUP(81, WEST, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[82] = PINGROUP(82, WEST, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 11),

	[83] = PINGROUP(83, WEST, NA, NAV_GPIO, NAV_PPS_IN, NAV_PPS_OUT,

			GPS_TX, NA, NA, NA, NA),

			GPS_TX, NA, NA, NA, NA, 0, -1),

	[84] = PINGROUP(84, WEST, NA, NAV_GPIO, NAV_PPS_IN, NAV_PPS_OUT,

			GPS_TX, NA, NA, NA, NA),

			GPS_TX, NA, NA, NA, NA, 0x77000, 12),

	[85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, NA, NA, NA, NA,

			NA, NA),

			NA, NA, 0x77000, 13),

	[86] = PINGROUP(86, NORTH, qup14, qdss_gpio0, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 25),

	[87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss_gpio1, NA, NA, NA, NA,

			NA, NA),

			NA, NA, 0x77000, 26),

	[88] = PINGROUP(88, NORTH, qup14, qdss_gpio2, tsense_pwm1, tsense_pwm2,

			NA, NA, NA, NA, NA),

			NA, NA, NA, NA, NA, 0x77000, 27),

	[89] = PINGROUP(89, NORTH, qup14, qdss_gpio3, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 28),

	[90] = PINGROUP(90, NORTH, qup14, qdss_gpio4, NA, NA, NA, NA, NA, NA,

			NA),

			NA, 0x77000, 29),

	[91] = PINGROUP(91, NORTH, qup14, qdss_gpio5, NA, NA, NA, NA, NA, NA,

			NA),

	[92] = PINGROUP(92, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[93] = PINGROUP(93, NORTH, qdss_gpio, NA, NA, NA, NA, NA, NA, NA, NA),

	[94] = PINGROUP(94, SOUTH, qup01, NA, NA, NA, NA, NA, NA, NA, NA),

	[95] = PINGROUP(95, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, 0x77000, 30),

	[92] = PINGROUP(92, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 31),

	[93] = PINGROUP(93, NORTH, qdss_gpio, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 0),

	[94] = PINGROUP(94, SOUTH, qup01, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 19),

	[95] = PINGROUP(95, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 14),

	[96] = PINGROUP(96, WEST, qlink_request, NA, NA, NA, NA, NA, NA, NA,

			NA),

	[97] = PINGROUP(97, WEST, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA),

	[98] = PINGROUP(98, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[99] = PINGROUP(99, WEST, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA),

	[100] = PINGROUP(100, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[101] = PINGROUP(101, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[102] = PINGROUP(102, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[103] = PINGROUP(103, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

			NA, 0x77000, 15),

	[97] = PINGROUP(97, WEST, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[98] = PINGROUP(98, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 16),

	[99] = PINGROUP(99, WEST, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[100] = PINGROUP(100, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[101] = PINGROUP(101, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 1),

	[102] = PINGROUP(102, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[103] = PINGROUP(103, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[104] = PINGROUP(104, WEST, usb_phy, NA, qdss_gpio, NA, NA, NA, NA, NA,

			 NA),

	[105] = PINGROUP(105, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[106] = PINGROUP(106, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

			 NA, 0x77000, 17),

	[105] = PINGROUP(105, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[106] = PINGROUP(106, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 2),

	[107] = PINGROUP(107, WEST, NA, NAV_GPIO, NAV_PPS_IN, NAV_PPS_OUT,

			GPS_TX, NA, NA, NA, NA),

			GPS_TX, NA, NA, NA, NA, 0x77000, 18),

	[108] = PINGROUP(108, SOUTH, mss_lte, NA, phase_flag5, ddr_pxi3, NA,

			 NA, NA, NA, NA),

			 NA, NA, NA, NA, 0, -1),

	[109] = PINGROUP(109, SOUTH, mss_lte, GPS_TX, NA, phase_flag13, NA, NA,

			 NA, NA, NA),

	[110] = PINGROUP(110, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[111] = PINGROUP(111, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[112] = PINGROUP(112, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[113] = PINGROUP(113, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[114] = PINGROUP(114, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),

	[115] = PINGROUP(115, WEST, qup04, qup04, NA, NA, NA, NA, NA, NA, NA),

	[116] = PINGROUP(116, WEST, qup04, qup04, NA, NA, NA, NA, NA, NA, NA),

	[117] = PINGROUP(117, WEST, dp_hot, NA, NA, NA, NA, NA, NA, NA, NA),

	[118] = PINGROUP(118, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),

			 NA, NA, NA, 0x77000, 20),

	[110] = PINGROUP(110, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 3),

	[111] = PINGROUP(111, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[112] = PINGROUP(112, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0, -1),

	[113] = PINGROUP(113, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 4),

	[114] = PINGROUP(114, NORTH, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77004, 5),

	[115] = PINGROUP(115, WEST, qup04, qup04, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 19),

	[116] = PINGROUP(116, WEST, qup04, qup04, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 20),

	[117] = PINGROUP(117, WEST, dp_hot, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 21),

	[118] = PINGROUP(118, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA,

			0x77000, 22),

	[119] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0),

	[120] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6),

	[121] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3),

drivers/pinctrl/qcom/pinctrl-msm.h

+4 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ struct msm_function { 
 * @intr_detection_width: Number of bits used for specifying interrupt type,

 *                        Should be 2 for SoCs that can detect both edges in hardware,

 *                        otherwise 1.

 * @wake_reg:             Offset of the WAKEUP_INT_EN register from base tile

 * @wake_bit:             Bit number for the corresponding gpio

 */

struct msm_pingroup {

	const char *name;
@@ -105,6 +107,8 @@ struct msm_pingroup { 
	unsigned intr_detection_bit:5;

	unsigned intr_detection_width:5;

	unsigned dir_conn_en_bit:8;

	u32 wake_reg;

	unsigned int wake_bit;

};



/**