Merge "clk: qcom: Update freq plan and FMAX corners for few GCC clocks" (678d06d8) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/gcc-sm6150.c

+19 −13

Original line number	Diff line number	Diff line
		@@ -300,7 +300,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
		};

		static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
		F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
		F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
		F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
		F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
		{ }
		@@ -320,8 +320,9 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 50000000,
		[VDD_LOW] = 230400000},
		[VDD_LOWER] = 75000000,
		[VDD_LOW] = 125000000,
		[VDD_NOMINAL] = 250000000},
		},
		};

		@@ -792,6 +793,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
		F(400000, P_BI_TCXO, 12, 1, 4),
		F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
		F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
		F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
		F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
		F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
		F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
		@@ -813,7 +815,9 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 100000000,
		[VDD_LOWER] = 50000000,
		[VDD_LOW] = 100000000,
		[VDD_LOW_L1] = 200000000,
		[VDD_NOMINAL] = 384000000},
		},
		};
		@@ -851,8 +855,9 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
		F(400000, P_BI_TCXO, 12, 1, 4),
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
		F(52000000, P_GPLL8_OUT_MAIN, 8, 0, 0),
		F(208000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
		F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
		F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
		F(202000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
		{ }
		};

		@@ -871,8 +876,9 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 52000000,
		[VDD_LOW] = 208000000},
		[VDD_LOWER] = 50000000,
		[VDD_LOW] = 100000000,
		[VDD_NOMINAL] = 202000000},
		},
		};

		@@ -2555,7 +2561,7 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {

		static struct clk_branch gcc_ufs_card_clkref_clk = {
		.halt_reg = 0x8c004,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x8c004,
		.enable_mask = BIT(0),
		@@ -3496,11 +3502,11 @@ static int gcc_sm6150_probe(struct platform_device *pdev)
		* Disable the GPLL0 active input to MM blocks and GPU
		* via MISC registers.
		*/
		regmap_update_bits(regmap, GCC_DISPLAY_MISC, 0x3, 0x3);
		regmap_update_bits(regmap, GCC_CAMERA_MISC, 0x3, 0x3);
		regmap_update_bits(regmap, GCC_VIDEO_MISC, 0x3, 0x3);
		regmap_update_bits(regmap, GCC_DISPLAY_MISC, 0x1, 0x1);
		regmap_update_bits(regmap, GCC_CAMERA_MISC, 0x1, 0x1);
		regmap_update_bits(regmap, GCC_VIDEO_MISC, 0x1, 0x1);
		regmap_update_bits(regmap, GCC_EMAC_MISC, 0x1, 0x1);
		regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);
		regmap_update_bits(regmap, GCC_EMAC_MISC, 0x3, 0x3);

		ret = qcom_cc_really_probe(pdev, &gcc_sm6150_desc, regmap);
		if (ret) {

drivers/clk/qcom/vdd-level-sm6150.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -25,6 +25,7 @@ enum vdd_mx_levels {
		VDD_MX_LOW_L1, /* SVSL1 */
		VDD_MX_NOMINAL, /* NOM */
		VDD_MX_HIGH, /* TURBO */
		VDD_MX_HIGH_L1, /* TURBO_L1 */
		VDD_MX_NUM,
		};

		@@ -36,6 +37,7 @@ static int vdd_mx_corner[] = {
		RPMH_REGULATOR_LEVEL_SVS_L1, /* VDD_LOW_L1 */
		RPMH_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */
		RPMH_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */
		RPMH_REGULATOR_LEVEL_TURBO_L1, /* VDD_HIGH_L1 */
		};

		enum vdd_levels {
		@@ -47,7 +49,7 @@ enum vdd_levels {
		VDD_NOMINAL, /* NOM */
		VDD_NOMINAL_L1, /* NOM1 */
		VDD_HIGH, /* TURBO */
		VDD_HIGH_L1, /* TURBO1 */
		VDD_HIGH_L1, /* TURBO_L1 */
		VDD_NUM,
		};