Merge tag 'phy-for-4.19' of...

Broadcom Stingray PCIe PHY

Required properties:

- compatible: must be "brcm,sr-pcie-phy"

- reg: base address and length of the PCIe SS register space

- brcm,sr-cdru: phandle to the CDRU syscon node

- brcm,sr-mhb: phandle to the MHB syscon node

- #phy-cells: Must be 1, denotes the PHY index

For PAXB based root complex, one can have a configuration of up to 8 PHYs

PHY index goes from 0 to 7

For the internal PAXC based root complex, PHY index is always 8

Example:

	mhb: syscon@60401000 {

		compatible = "brcm,sr-mhb", "syscon";

		reg = <0 0x60401000 0 0x38c>;

	};

	cdru: syscon@6641d000 {

		compatible = "brcm,sr-cdru", "syscon";

		reg = <0 0x6641d000 0 0x400>;

	};

	pcie_phy: phy@40000000 {

		compatible = "brcm,sr-pcie-phy";

		reg = <0 0x40000000 0 0x800>;

		brcm,sr-cdru = <&cdru>;

		brcm,sr-mhb = <&mhb>;

		#phy-cells = <1>;

	};

	/* users of the PCIe PHY */

	pcie0: pcie@48000000 {

		...

		...

		phys = <&pcie_phy 0>;

		phy-names = "pcie-phy";

	};

			- PHY_TYPE_PCIE

			- PHY_TYPE_SATA

Optional properties (PHY_TYPE_USB2 port (child) node):

- mediatek,eye-src	: u32, the value of slew rate calibrate

- mediatek,eye-vrt	: u32, the selection of VRT reference voltage

- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage

- mediatek,bc12	: bool, enable BC12 of u2phy if support it

Example:

u3phy: usb-phy@11290000 {

	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,

	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.

 - reg: offset and length of register set for PHY's common serdes block.

 - reg:

   - For "qcom,sdm845-qmp-usb3-phy":

     - index 0: address and length of register set for PHY's common serdes

       block.

     - named register "dp_com" (using reg-names): address and length of the

       DP_COM control block.

   - For all others:

     - offset and length of register set for PHY's common serdes block.

 - #clock-cells: must be 1

    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe

Required properties for child node:

 - reg: list of offset and length pairs of register sets for PHY blocks -

	tx, rx and pcs.

	- index 0: tx

	- index 1: rx

	- index 2: pcs

	- index 3: pcs_misc (optional)

 - #phy-cells: must be 0

* Renesas R-Car generation 3 PCIe PHY

This file provides information on what the device node for the R-Car

generation 3 PCIe PHY contains.

Required properties:

- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the

	      R8A77980 SoC.

- reg: offset and length of the register block.

- clocks: clock phandle and specifier pair.

- power-domains: power domain phandle and specifier pair.

- resets: reset phandle and specifier pair.

- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.

Example (R-Car V3H):

	pcie-phy@e65d0000 {

		compatible = "renesas,r8a77980-pcie-phy";

		reg = <0 0xe65d0000 0 0x8000>;

		#phy-cells = <0>;

		clocks = <&cpg CPG_MOD 319>;

		power-domains = <&sysc 32>;

		resets = <&cpg 319>;

	};

	      SoC.

	      "renesas,usb2-phy-r8a77965" if the device is a part of an

	      R8A77965 SoC.

	      "renesas,usb2-phy-r8a77990" if the device is a part of an

	      R8A77990 SoC.

	      "renesas,usb2-phy-r8a77995" if the device is a part of an

	      R8A77995 SoC.

	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.