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Commit 6657959b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: npu: Add NPU driver V2 to support atoll"

parents 3ced73ac 873a9f92
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+162 −0
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/* Copyright (c) 2019, The Linux Foundation.All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	msm_npu: qcom,msm_npu@9800000 {
		compatible = "qcom,msm-npu";
		status = "ok";
		reg = <0x9900000 0x20000>,
			<0x99f0000 0x10000>,
			<0x9980000 0x10000>,
			<0x17c00000 0x10000>;
		reg-names = "tcm", "core", "cc", "apss_shared";
		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
			"general_irq";
		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x1462 0x0>,
			<&apps_smmu 0x1481 0x0>, <&apps_smmu 0x1482 0x0>;

		clocks = <&clock_npucc NPU_CC_XO_CLK>,
			<&clock_npucc NPU_CC_CORE_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_CDC_CLK>,
			<&clock_npucc NPU_CC_NOC_AXI_CLK>,
			<&clock_npucc NPU_CC_NOC_AHB_CLK>,
			<&clock_npucc NPU_CC_NOC_DMA_CLK>,
			<&clock_npucc NPU_CC_RSC_XO_CLK>,
			<&clock_npucc NPU_CC_S2P_CLK>,
			<&clock_npucc NPU_CC_BWMON_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
			<&clock_npucc NPU_CC_BTO_CORE_CLK>,
			<&clock_npucc NPU_DSP_CORE_CLK_SRC>;
		clock-names = "xo_clk",
			"npu_core_clk",
			"cal_hm0_clk",
			"cal_hm0_cdc_clk",
			"axi_clk",
			"ahb_clk",
			"dma_clk",
			"rsc_xo_clk",
			"s2p_clk",
			"bwmon_clk",
			"cal_hm0_perf_cnt_clk",
			"bto_core_clk",
			"dsp_core_clk_src";

		vdd-supply = <&npu_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		#cooling-cells = <2>;
		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;
		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";
		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
		qcom,npu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,npu-pwrlevels";
			initial-pwrlevel = <4>;
			qcom,npu-pwrlevel@0 {
				reg = <0>;
				vreg = <1>;
				clk-freq = <19200000
					100000000
					200000000
					200000000
					120000000
					40000000
					200000000
					19200000
					50000000
					19200000
					200000000
					19200000
					300000000>;
			};

			qcom,npu-pwrlevel@1 {
				reg = <1>;
				vreg = <2>;
				clk-freq = <19200000
					200000000
					400000000
					400000000
					200000000
					40000000
					300000000
					19200000
					50000000
					19200000
					400000000
					19200000
					400000000>;
			};

			qcom,npu-pwrlevel@2 {
				reg = <2>;
				vreg = <3>;
				clk-freq = <19200000
					333000000
					515000000
					515000000
					300000000
					75000000
					400000000
					19200000
					50000000
					19200000
					515000000
					19200000
					500000000>;
			};

			qcom,npu-pwrlevel@3 {
				reg = <3>;
				vreg = <4>;
				clk-freq = <19200000
					428000000
					650000000
					650000000
					403000000
					75000000
					600000000
					19200000
					100000000
					19200000
					515000000
					19200000
					660000000>;
			};

			qcom,npu-pwrlevel@4 {
				reg = <4>;
				vreg = <6>;
				clk-freq = <19200000
					500000000
					800000000
					800000000
					533000000
					75000000
					710000000
					19200000
					100000000
					19200000
					650000000
					19200000
					800000000>;
			};
		};
	};
};
+22 −8
Original line number Diff line number Diff line
@@ -538,16 +538,22 @@
			reg = <0 0x80b00000 0 0x3900000>;
		};

		pil_modem_mem: modem_region@86000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x86000000 0 0x8400000>;
		};

		pil_camera_mem: camera_region@8e400000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8e400000 0 0x500000>;
		};

		pil_modem_mem: modem_region@86000000 {
		pil_npu_mem: pil_npu_region@8e900000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x86000000 0 0x8400000>;
			reg = <0 0x8e900000 0 0x500000>;
		};

		pil_video_mem: pil_video_region@8ee00000 {
@@ -574,12 +580,6 @@
			reg = <0 0x93900000 0 0x200000>;
		};

		npu_mem: npu_region@8e900000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8e900000 0 0x500000>;
		};

		pil_ipa_fw_mem: ipa_fw_region@93b00000 {
			compatible = "removed-dma-pool";
			no-map;
@@ -1197,6 +1197,19 @@
		mbox-names = "mss-pil";
	};

	qcom,npu@9800000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x9800000 0x800000>;

		qcom,pas-id = <23>;
		qcom,firmware-name = "npu";
		memory-region = <&pil_npu_mem>;

		/* Outputs to npu */
		qcom,smem-states = <&npu_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
	};

	qcom,turing@8300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x8300000 0x100000>;
@@ -3300,6 +3313,7 @@
#include "atoll-regulator.dtsi"
#include "atoll-usb.dtsi"
#include "atoll-vidc.dtsi"
#include "atoll-npu.dtsi"

&pm6150_vadc {
	pinctrl-names = "default";
+1 −0
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@@ -60,5 +60,6 @@ endif # MSMB_CAMERA
source "drivers/media/platform/msm/vidc/Kconfig"
source "drivers/media/platform/msm/sde/Kconfig"
source "drivers/media/platform/msm/npu/Kconfig"
source "drivers/media/platform/msm/npu_v2/Kconfig"
source "drivers/media/platform/msm/dvb/Kconfig"
source "drivers/media/platform/msm/broadcast/Kconfig"
+1 −0
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@@ -4,6 +4,7 @@
#
obj-y += sde/
obj-$(CONFIG_MSM_NPU) += npu/
obj-$(CONFIG_MSM_NPU_V2) += npu_v2/
obj-$(CONFIG_MSM_VIDC_V4L2) += vidc/
obj-$(CONFIG_SPECTRA_CAMERA) += camera/
obj-$(CONFIG_MSM_AIS) += ais/
+9 −0
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config MSM_NPU_V2
	tristate "QTI MSM Neural Processing Unit support V2"
	depends on ARCH_QCOM && MSM_NPU=n
	help
	  Enable support for Neural Processing Unit V2.0
	  for specific QTI chipsets.
	  This module serves as the common driver
	  for npu which provides acceleration for neural
	  network processing.
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