Commit 65f1f5a2 authored Oct 01, 2005 by Ralf Baechle

Don't copy SB1 cache error handler to uncached memory.


    
This may have made sense on a paranoid day with pass 1 BCM1250 processors
that were throwing cache error exception left and right for no good
reason.  On modern silicion that hardly makes sense and the code had
gotten just an obscurity ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 5090dfb5

arch/mips/mm/c-sb1.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -503,7 +503,6 @@ void sb1_cache_init(void)

		/* Special cache error handler for SB1 */
		set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
		memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);

		probe_cache_sizes();