Merge "msm: kgsl: Add new debugbus and clusters to a650 snapshot" (6570f77d) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/gpu/msm/adreno.c

+39 −0

Original line number	Diff line number	Diff line
		@@ -1229,6 +1229,24 @@ static void adreno_rscc_probe(struct kgsl_device *device)
		dev_warn(device->dev, "rscc ioremap failed\n");
		}

		static void adreno_isense_probe(struct kgsl_device *device)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		struct resource *res;

		res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,
		"isense_cntl");
		if (res == NULL)
		return;

		adreno_dev->isense_base = res->start - device->reg_phys;
		adreno_dev->isense_len = resource_size(res);
		adreno_dev->isense_virt = devm_ioremap(device->dev, res->start,
		adreno_dev->isense_len);
		if (adreno_dev->isense_virt == NULL)
		dev_warn(device->dev, "isense ioremap failed\n");
		}

		static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)
		{
		unsigned int val;
		@@ -1355,6 +1373,8 @@ static int adreno_probe(struct platform_device *pdev)
		adreno_cx_misc_probe(device);

		adreno_rscc_probe(device);

		adreno_isense_probe(device);
		/*
		* qcom,iommu-secure-id is used to identify MMUs that can handle secure
		* content but that is only part of the story - the GPU also has to be
		@@ -3247,6 +3267,25 @@ void adreno_rscc_regread(struct adreno_device *adreno_dev,
		rmb();
		}

		void adreno_isense_regread(struct adreno_device *adreno_dev,
		unsigned int offsetwords, unsigned int *value)
		{
		unsigned int isense_offset;

		isense_offset = (offsetwords << 2);
		if (!adreno_dev->isense_virt \|\|
		(isense_offset >= adreno_dev->isense_len))
		return;

		*value = __raw_readl(adreno_dev->isense_virt + isense_offset);

		/*
		* ensure this read finishes before the next one.
		* i.e. act like normal readl()
		*/
		rmb();
		}

		void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev,
		unsigned int offsetwords, unsigned int value)
		{

drivers/gpu/msm/adreno.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -445,6 +445,9 @@ enum gpu_coresight_sources {
		* @rscc_base: Base physical address of the RSCC
		* @rscc_len: Length of the RSCC register block
		* @rscc_virt: Pointer where RSCC block is mapped
		* @isense_base: Base physical address of isense block
		* @isense_len: Length of the isense register block
		* @isense_virt: Pointer where isense block is mapped
		* @gpucore: Pointer to the adreno_gpu_core structure
		* @pfp_fw: Buffer which holds the pfp ucode
		* @pfp_fw_size: Size of pfp ucode buffer
		@@ -530,6 +533,9 @@ struct adreno_device {
		unsigned long rscc_base;
		unsigned int rscc_len;
		void __iomem *rscc_virt;
		unsigned long isense_base;
		unsigned int isense_len;
		void __iomem *isense_virt;
		const struct adreno_gpu_core *gpucore;
		struct adreno_firmware fw[2];
		size_t gpmu_cmds_size;
		@@ -1191,6 +1197,8 @@ void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,
		unsigned int mask, unsigned int bits);
		void adreno_rscc_regread(struct adreno_device *adreno_dev,
		unsigned int offsetwords, unsigned int *value);
		void adreno_isense_regread(struct adreno_device *adreno_dev,
		unsigned int offsetwords, unsigned int *value);


		#define ADRENO_TARGET(_name, _id) \

drivers/gpu/msm/adreno_a6xx.h

+2 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/*
		* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef _ADRENO_A6XX_H_
		@@ -14,6 +14,7 @@
		#define CP_CLUSTER_GRAS 0x3
		#define CP_CLUSTER_SP_PS 0x4
		#define CP_CLUSTER_PS 0x5
		#define CP_CLUSTER_VPC_PS 0x6

		/**
		* struct a6xx_cp_preemption_record - CP context record for

drivers/gpu/msm/adreno_a6xx_snapshot.c

+227 −17

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
		*/

		#include <linux/io.h>
		@@ -35,7 +35,7 @@ static const unsigned int a6xx_ps_cluster_rbp[] = {
		0x8C02, 0x8C07, 0x8C11, 0x8C16, 0x8C20, 0x8C25,
		};

		static const unsigned int a6xx_ps_cluster[] = {
		static const unsigned int a6xx_vpc_ps_cluster[] = {
		0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
		};

		@@ -66,6 +66,67 @@ static const unsigned int a6xx_rscc_snapshot_registers[] = {
		0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F,
		};

		static const unsigned int a650_rscc_registers[] = {
		0x38000, 0x38034, 0x38036, 0x38036, 0x38040, 0x38042, 0x38080, 0x38084,
		0x38089, 0x3808C, 0x38091, 0x38094, 0x38099, 0x3809C, 0x380A1, 0x380A4,
		0x380A9, 0x380AC, 0x38100, 0x38102, 0x38104, 0x38107, 0x38114, 0x38119,
		0x38124, 0x3812E, 0x38180, 0x38197, 0x38340, 0x38341, 0x38344, 0x38347,
		0x3834C, 0x3834F, 0x38351, 0x38354, 0x38356, 0x38359, 0x3835B, 0x3835E,
		0x38360, 0x38363, 0x38365, 0x38368, 0x3836A, 0x3836D, 0x3836F, 0x38372,
		0x383EC, 0x383EF, 0x383F4, 0x383F7, 0x383F9, 0x383FC, 0x383FE, 0x38401,
		0x38403, 0x38406, 0x38408, 0x3840B, 0x3840D, 0x38410, 0x38412, 0x38415,
		0x38417, 0x3841A, 0x38494, 0x38497, 0x3849C, 0x3849F, 0x384A1, 0x384A4,
		0x384A6, 0x384A9, 0x384AB, 0x384AE, 0x384B0, 0x384B3, 0x384B5, 0x384B8,
		0x384BA, 0x384BD, 0x384BF, 0x384C2, 0x3853C, 0x3853F, 0x38544, 0x38547,
		0x38549, 0x3854C, 0x3854E, 0x38551, 0x38553, 0x38556, 0x38558, 0x3855B,
		0x3855D, 0x38560, 0x38562, 0x38565, 0x38567, 0x3856A, 0x385E4, 0x385E7,
		0x385EC, 0x385EF, 0x385F1, 0x385F4, 0x385F6, 0x385F9, 0x385FB, 0x385FE,
		0x38600, 0x38603, 0x38605, 0x38608, 0x3860A, 0x3860D, 0x3860F, 0x38612,
		0x3868C, 0x3868F, 0x38694, 0x38697, 0x38699, 0x3869C, 0x3869E, 0x386A1,
		0x386A3, 0x386A6, 0x386A8, 0x386AB, 0x386AD, 0x386B0, 0x386B2, 0x386B5,
		0x386B7, 0x386BA, 0x38734, 0x38737, 0x3873C, 0x3873F, 0x38741, 0x38744,
		0x38746, 0x38749, 0x3874B, 0x3874E, 0x38750, 0x38753, 0x38755, 0x38758,
		0x3875A, 0x3875D, 0x3875F, 0x38762, 0x387DC, 0x387DF, 0x387E4, 0x387E7,
		0x387E9, 0x387EC, 0x387EE, 0x387F1, 0x387F3, 0x387F6, 0x387F8, 0x387FB,
		0x387FD, 0x38800, 0x38802, 0x38805, 0x38807, 0x3880A, 0x38884, 0x38887,
		0x3888C, 0x3888F, 0x38891, 0x38894, 0x38896, 0x38899, 0x3889B, 0x3889E,
		0x388A0, 0x388A3, 0x388A5, 0x388A8, 0x388AA, 0x388AD, 0x388AF, 0x388B2,
		0x3892C, 0x3892F, 0x38934, 0x38937, 0x38939, 0x3893C, 0x3893E, 0x38941,
		0x38943, 0x38946, 0x38948, 0x3894B, 0x3894D, 0x38950, 0x38952, 0x38955,
		0x38957, 0x3895A, 0x38B50, 0x38B51, 0x38B53, 0x38B55, 0x38B5A, 0x38B5A,
		0x38B5F, 0x38B5F, 0x38B64, 0x38B64, 0x38B69, 0x38B69, 0x38B6E, 0x38B6E,
		0x38B73, 0x38B73, 0x38BF8, 0x38BF8, 0x38BFD, 0x38BFD, 0x38C02, 0x38C02,
		0x38C07, 0x38C07, 0x38C0C, 0x38C0C, 0x38C11, 0x38C11, 0x38C16, 0x38C16,
		0x38C1B, 0x38C1B, 0x38CA0, 0x38CA0, 0x38CA5, 0x38CA5, 0x38CAA, 0x38CAA,
		0x38CAF, 0x38CAF, 0x38CB4, 0x38CB4, 0x38CB9, 0x38CB9, 0x38CBE, 0x38CBE,
		0x38CC3, 0x38CC3, 0x38D48, 0x38D48, 0x38D4D, 0x38D4D, 0x38D52, 0x38D52,
		0x38D57, 0x38D57, 0x38D5C, 0x38D5C, 0x38D61, 0x38D61, 0x38D66, 0x38D66,
		0x38D6B, 0x38D6B, 0x38DF0, 0x38DF0, 0x38DF5, 0x38DF5, 0x38DFA, 0x38DFA,
		0x38DFF, 0x38DFF, 0x38E04, 0x38E04, 0x38E09, 0x38E09, 0x38E0E, 0x38E0E,
		0x38E13, 0x38E13, 0x38E98, 0x38E98, 0x38E9D, 0x38E9D, 0x38EA2, 0x38EA2,
		0x38EA7, 0x38EA7, 0x38EAC, 0x38EAC, 0x38EB1, 0x38EB1, 0x38EB6, 0x38EB6,
		0x38EBB, 0x38EBB, 0x38F40, 0x38F40, 0x38F45, 0x38F45, 0x38F4A, 0x38F4A,
		0x38F4F, 0x38F4F, 0x38F54, 0x38F54, 0x38F59, 0x38F59, 0x38F5E, 0x38F5E,
		0x38F63, 0x38F63, 0x38FE8, 0x38FE8, 0x38FED, 0x38FED, 0x38FF2, 0x38FF2,
		0x38FF7, 0x38FF7, 0x38FFC, 0x38FFC, 0x39001, 0x39001, 0x39006, 0x39006,
		0x3900B, 0x3900B, 0x39090, 0x39090, 0x39095, 0x39095, 0x3909A, 0x3909A,
		0x3909F, 0x3909F, 0x390A4, 0x390A4, 0x390A9, 0x390A9, 0x390AE, 0x390AE,
		0x390B3, 0x390B3, 0x39138, 0x39138, 0x3913D, 0x3913D, 0x39142, 0x39142,
		0x39147, 0x39147, 0x3914C, 0x3914C, 0x39151, 0x39151, 0x39156, 0x39156,
		0x3915B, 0x3915B,
		};

		static const unsigned int a650_isense_registers[] = {
		0x22C00, 0x22C19, 0x22C26, 0x22C2D, 0x22C2F, 0x22C36, 0x22C40, 0x22C44,
		0x22C50, 0x22C57, 0x22C60, 0x22C67, 0x22C80, 0x22C87, 0x22D25, 0x22D2A,
		0x22D2C, 0x22D32, 0x22D3E, 0x22D3F, 0x22D4E, 0x22D55, 0x22D58, 0x22D60,
		0x22D64, 0x22D64, 0x22D66, 0x22D66, 0x22D68, 0x22D6B, 0x22D6E, 0x22D76,
		0x22D78, 0x22D78, 0x22D80, 0x22D87, 0x22D90, 0x22D97, 0x22DA0, 0x22DA0,
		0x22DB0, 0x22DB7, 0x22DC0, 0x22DC2, 0x22DC4, 0x22DE3, 0x2301A, 0x2301A,
		0x2301D, 0x2302A, 0x23120, 0x23121, 0x23133, 0x23133, 0x23156, 0x23157,
		0x23165, 0x23165, 0x2316D, 0x2316D, 0x23180, 0x23191,
		};

		static const struct sel_reg {
		unsigned int host_reg;
		unsigned int cd_reg;
		@@ -95,7 +156,7 @@ static struct a6xx_cluster_registers {
		&_a6xx_rb_rac_aperture },
		{ CP_CLUSTER_PS, a6xx_ps_cluster_rbp, ARRAY_SIZE(a6xx_ps_cluster_rbp)/2,
		&_a6xx_rb_rbp_aperture },
		{ CP_CLUSTER_PS, a6xx_ps_cluster, ARRAY_SIZE(a6xx_ps_cluster)/2,
		{ CP_CLUSTER_PS, a6xx_vpc_ps_cluster, ARRAY_SIZE(a6xx_vpc_ps_cluster)/2,
		NULL },
		{ CP_CLUSTER_FE, a6xx_fe_cluster, ARRAY_SIZE(a6xx_fe_cluster)/2,
		NULL },
		@@ -144,7 +205,7 @@ static const unsigned int a6xx_sp_ps_hlsq_2d_cluster[] = {

		static const unsigned int a6xx_sp_ps_sp_cluster[] = {
		0xA980, 0xA9A8, 0xA9B0, 0xA9BC, 0xA9D0, 0xA9D3, 0xA9E0, 0xA9F3,
		0xAA00, 0xAA00, 0xAA30, 0xAA31,
		0xAA00, 0xAA00, 0xAA30, 0xAA31, 0xAAF2, 0xAAF2,
		};

		static const unsigned int a6xx_sp_ps_sp_2d_cluster[] = {
		@@ -354,19 +415,32 @@ enum a6xx_debugbus_id {
		A6XX_DBGBUS_HLSQ_SPTP = 0x1f,
		A6XX_DBGBUS_RB_0 = 0x20,
		A6XX_DBGBUS_RB_1 = 0x21,
		A6XX_DBGBUS_RB_2 = 0x22,
		A6XX_DBGBUS_UCHE_WRAPPER = 0x24,
		A6XX_DBGBUS_CCU_0 = 0x28,
		A6XX_DBGBUS_CCU_1 = 0x29,
		A6XX_DBGBUS_CCU_2 = 0x2a,
		A6XX_DBGBUS_VFD_0 = 0x38,
		A6XX_DBGBUS_VFD_1 = 0x39,
		A6XX_DBGBUS_VFD_2 = 0x3a,
		A6XX_DBGBUS_VFD_3 = 0x3b,
		A6XX_DBGBUS_VFD_4 = 0x3c,
		A6XX_DBGBUS_VFD_5 = 0x3d,
		A6XX_DBGBUS_SP_0 = 0x40,
		A6XX_DBGBUS_SP_1 = 0x41,
		A6XX_DBGBUS_SP_2 = 0x42,
		A6XX_DBGBUS_TPL1_0 = 0x48,
		A6XX_DBGBUS_TPL1_1 = 0x49,
		A6XX_DBGBUS_TPL1_2 = 0x4a,
		A6XX_DBGBUS_TPL1_3 = 0x4b,
		A6XX_DBGBUS_TPL1_4 = 0x4c,
		A6XX_DBGBUS_TPL1_5 = 0x4d,
		A6XX_DBGBUS_SPTP_0 = 0x58,
		A6XX_DBGBUS_SPTP_1 = 0x59,
		A6XX_DBGBUS_SPTP_2 = 0x5a,
		A6XX_DBGBUS_SPTP_3 = 0x5b,
		A6XX_DBGBUS_SPTP_4 = 0x5c,
		A6XX_DBGBUS_SPTP_5 = 0x5d,
		};

		static const struct adreno_debugbus_block a6xx_dbgc_debugbus_blocks[] = {
		@@ -420,6 +494,22 @@ static const struct adreno_debugbus_block a6xx_cx_dbgc_debugbus_blocks[] = {
		{ A6XX_DBGBUS_CX, 0x100, },
		};

		static const struct adreno_debugbus_block a650_dbgc_debugbus_blocks[] = {
		{ A6XX_DBGBUS_RB_2, 0x100, },
		{ A6XX_DBGBUS_CCU_2, 0x100, },
		{ A6XX_DBGBUS_VFD_4, 0x100, },
		{ A6XX_DBGBUS_VFD_5, 0x100, },
		{ A6XX_DBGBUS_SP_2, 0x100, },
		{ A6XX_DBGBUS_TPL1_4, 0x100, },
		{ A6XX_DBGBUS_TPL1_5, 0x100, },
		{ A6XX_DBGBUS_SPTP_0, 0x100, },
		{ A6XX_DBGBUS_SPTP_1, 0x100, },
		{ A6XX_DBGBUS_SPTP_2, 0x100, },
		{ A6XX_DBGBUS_SPTP_3, 0x100, },
		{ A6XX_DBGBUS_SPTP_4, 0x100, },
		{ A6XX_DBGBUS_SPTP_5, 0x100, },
		};

		#define A6XX_NUM_SHADER_BANKS 3
		#define A6XX_SHADER_STATETYPE_SHIFT 8

		@@ -1381,6 +1471,16 @@ static void a6xx_snapshot_debugbus(struct adreno_device *adreno_dev,
		snapshot, a6xx_snapshot_dbgc_debugbus_block,
		(void *) &a6xx_dbgc_debugbus_blocks[i]);
		}

		if (adreno_is_a650(adreno_dev)) {
		for (i = 0; i < ARRAY_SIZE(a650_dbgc_debugbus_blocks); i++) {
		kgsl_snapshot_add_section(device,
		KGSL_SNAPSHOT_SECTION_DEBUGBUS,
		snapshot, a6xx_snapshot_dbgc_debugbus_block,
		(void *) &a650_dbgc_debugbus_blocks[i]);
		}
		}

		/*
		* GBIF has same debugbus as of other GPU blocks hence fall back to
		* default path if GPU uses GBIF.
		@@ -1489,6 +1589,91 @@ static void _a6xx_do_crashdump(struct kgsl_device *device)
		crash_dump_valid = true;
		}

		size_t a6xx_snapshot_rscc_registers(struct kgsl_device device, u8 buf,
		size_t remain, void *priv)
		{
		struct kgsl_snapshot_regs header = (struct kgsl_snapshot_regs )buf;
		struct kgsl_snapshot_registers *regs = priv;
		unsigned int data = (unsigned int )(buf + sizeof(*header));
		int count = 0, j, k;
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

		/* Figure out how many registers we are going to dump */
		for (j = 0; j < regs->count; j++) {
		int start = regs->regs[j * 2];
		int end = regs->regs[j * 2 + 1];

		count += (end - start + 1);
		}

		if (remain < (count * 8) + sizeof(*header)) {
		SNAPSHOT_ERR_NOMEM(device, "RSCC REGISTERS");
		return 0;
		}

		for (j = 0; j < regs->count; j++) {
		unsigned int start = regs->regs[j * 2];
		unsigned int end = regs->regs[j * 2 + 1];

		for (k = start; k <= end; k++) {
		unsigned int val;

		adreno_rscc_regread(adreno_dev,
		k - (adreno_dev->rscc_base >> 2), &val);
		*data++ = k;
		*data++ = val;
		}
		}

		header->count = count;

		/* Return the size of the section */
		return (count * 8) + sizeof(*header);
		}

		size_t a6xx_snapshot_isense_registers(struct kgsl_device device, u8 buf,
		size_t remain, void *priv)
		{
		struct kgsl_snapshot_regs header = (struct kgsl_snapshot_regs )buf;
		struct kgsl_snapshot_registers *regs = priv;
		unsigned int data = (unsigned int )(buf + sizeof(*header));
		int count = 0, j, k;
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

		/* Figure out how many registers we are going to dump */

		for (j = 0; j < regs->count; j++) {
		int start = regs->regs[j * 2];
		int end = regs->regs[j * 2 + 1];

		count += (end - start + 1);
		}

		if (remain < (count * 8) + sizeof(*header)) {
		SNAPSHOT_ERR_NOMEM(device, "ISENSE REGISTERS");
		return 0;
		}

		for (j = 0; j < regs->count; j++) {
		unsigned int start = regs->regs[j * 2];
		unsigned int end = regs->regs[j * 2 + 1];

		for (k = start; k <= end; k++) {
		unsigned int val;

		adreno_isense_regread(adreno_dev,
		k - (adreno_dev->isense_base >> 2), &val);
		*data++ = k;
		*data++ = val;
		}
		}

		header->count = count;

		/* Return the size of the section */
		return (count * 8) + sizeof(*header);
		}

		/*
		* a6xx_snapshot() - A6XX GPU snapshot function
		* @adreno_dev: Device being snapshotted
		@@ -1503,7 +1688,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		bool sptprac_on;
		unsigned int i, roq_size;
		unsigned int i, roq_size, ucode_dbg_size;

		/* GMU TCM data dumped through AHB */
		gmu_core_dev_snapshot(device, snapshot);
		@@ -1517,6 +1702,32 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
		*/
		a6xx_snapshot_debugbus(adreno_dev, snapshot);

		/* RSCC registers are on cx */
		if (adreno_is_a650(adreno_dev)) {
		struct kgsl_snapshot_registers r;

		r.regs = a650_rscc_registers;
		r.count = ARRAY_SIZE(a650_rscc_registers) / 2;

		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,
		snapshot, a6xx_snapshot_rscc_registers, &r);

		r.regs = a650_isense_registers;
		r.count = ARRAY_SIZE(a650_isense_registers) / 2;

		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,
		snapshot, a6xx_snapshot_isense_registers, &r);
		} else if (adreno_is_a615_family(adreno_dev) \|\|
		adreno_is_a630(adreno_dev)) {
		adreno_snapshot_registers(device, snapshot,
		a630_rscc_snapshot_registers,
		ARRAY_SIZE(a630_rscc_snapshot_registers) / 2);
		} else if (adreno_is_a640(adreno_dev) \|\| adreno_is_a680(adreno_dev)) {
		adreno_snapshot_registers(device, snapshot,
		a6xx_rscc_snapshot_registers,
		ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2);
		}

		sptprac_on = gpudev->sptprac_is_on(adreno_dev);

		if (!gmu_core_dev_gx_is_on(device))
		@@ -1545,15 +1756,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
		snapshot, a6xx_snapshot_registers, &a6xx_reg_list[i]);
		}

		if (adreno_is_a615_family(adreno_dev) \|\| adreno_is_a630(adreno_dev))
		adreno_snapshot_registers(device, snapshot,
		a630_rscc_snapshot_registers,
		ARRAY_SIZE(a630_rscc_snapshot_registers) / 2);
		else if (adreno_is_a640(adreno_dev) \|\| adreno_is_a680(adreno_dev))
		adreno_snapshot_registers(device, snapshot,
		a6xx_rscc_snapshot_registers,
		ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2);

		/* CP_SQE indexed registers */
		kgsl_snapshot_indexed_registers(device, snapshot,
		A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33);
		@@ -1563,10 +1765,12 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,
		A6XX_CP_DRAW_STATE_ADDR, A6XX_CP_DRAW_STATE_DATA,
		0, 0x100);

		ucode_dbg_size = adreno_is_a650(adreno_dev) ? 0x7000 : 0x6000;

		/* SQE_UCODE Cache */
		kgsl_snapshot_indexed_registers(device, snapshot,
		A6XX_CP_SQE_UCODE_DBG_ADDR, A6XX_CP_SQE_UCODE_DBG_DATA,
		0, 0x6000);
		0, ucode_dbg_size);

		/*
		* CP ROQ dump units is 4dwords. The number of units is stored
		@@ -1598,7 +1802,8 @@ void a6xx_snapshot(struct adreno_device *adreno_dev,

		}

		static int _a6xx_crashdump_init_mvc(uint64_t ptr, uint64_t offset)
		static int _a6xx_crashdump_init_mvc(struct adreno_device *adreno_dev,
		uint64_t ptr, uint64_t offset)
		{
		int qwords = 0;
		unsigned int i, j, k;
		@@ -1607,6 +1812,11 @@ static int _a6xx_crashdump_init_mvc(uint64_t ptr, uint64_t offset)
		for (i = 0; i < ARRAY_SIZE(a6xx_clusters); i++) {
		struct a6xx_cluster_registers *cluster = &a6xx_clusters[i];

		/* The VPC registers are driven by VPC_PS cluster on a650 */
		if (adreno_is_a650(adreno_dev) &&
		(cluster->regs == a6xx_vpc_ps_cluster))
		cluster->id = CP_CLUSTER_VPC_PS;

		if (cluster->sel) {
		ptr[qwords++] = cluster->sel->val;
		ptr[qwords++] = ((uint64_t)cluster->sel->cd_reg << 44) \|
		@@ -1902,7 +2112,7 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev)
		}

		/* Program the capturescript for the MVC regsiters */
		ptr += _a6xx_crashdump_init_mvc(ptr, &offset);
		ptr += _a6xx_crashdump_init_mvc(adreno_dev, ptr, &offset);

		ptr += _a6xx_crashdump_init_ctx_dbgahb(ptr, &offset);