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Commit 64376269 authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Stephen Warren
Browse files

ARM: tegra: Initialize pll_p_out1 



pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be
initialized to make sure pll_a has a known input clock. Failure to do so
will cause the system to crash early in the bootup.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 8703612b

arch/arm/mach-tegra/common.c

+12 −0
Original line number Diff line number Diff line
@@ -93,6 +93,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { 
};

#endif



#ifdef CONFIG_ARCH_TEGRA_3x_SOC

static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {

	/* name		parent		rate		enabled */

	{ "clk_m",	NULL,		0,		true },

	{ "pll_p",	"clk_m",	408000000,	true },

	{ "pll_p_out1",	"pll_p",	9600000,	true },

	{ NULL,		NULL,		0,		0},

};

#endif





static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)

{

#ifdef CONFIG_CACHE_L2X0
@@ -127,6 +138,7 @@ void __init tegra30_init_early(void) 
{

	tegra_init_fuse();

	tegra30_init_clocks();

	tegra_clk_init_from_table(tegra30_clk_init_table);

	tegra_init_cache(0x441, 0x551);

	tegra_pmc_init();

	tegra_powergate_init();