Merge branch 'pci/vipul-chelsio-reset-v2' into next (63ef4181) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+2 −16

Original line number	Original line	Diff line number	Diff line
	@@ -9935,8 +9935,6 @@ static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)

	static int bnx2x_do_flr(struct bnx2x *bp)		static int bnx2x_do_flr(struct bnx2x *bp)
	{		{
	int i;
	u16 status;
	struct pci_dev *dev = bp->pdev;		struct pci_dev *dev = bp->pdev;

	if (CHIP_IS_E1x(bp)) {		if (CHIP_IS_E1x(bp)) {
	@@ -9951,20 +9949,8 @@ static int bnx2x_do_flr(struct bnx2x *bp)
	return -EINVAL;		return -EINVAL;
	}		}

	/* Wait for Transaction Pending bit clean */		if (!pci_wait_for_pending_transaction(dev))
	for (i = 0; i < 4; i++) {		dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
	if (i)
	msleep((1 << (i - 1)) * 100);

	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
	if (!(status & PCI_EXP_DEVSTA_TRPND))
	goto clear;
	}

	dev_err(&dev->dev,
	"transaction is not cleared; proceeding with reset anyway\n");

	clear:

	BNX2X_DEV_INFO("Initiating FLR\n");		BNX2X_DEV_INFO("Initiating FLR\n");
	bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);		bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);

drivers/pci/pci.c

+25 −13

Original line number	Original line	Diff line number	Diff line
	@@ -3159,19 +3159,17 @@ int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
	}		}
	EXPORT_SYMBOL(pci_set_dma_seg_boundary);		EXPORT_SYMBOL(pci_set_dma_seg_boundary);

	static int pcie_flr(struct pci_dev *dev, int probe)		/**
			* pci_wait_for_pending_transaction - waits for pending transaction
			* @dev: the PCI device to operate on
			*
			* Return 0 if transaction is pending 1 otherwise.
			*/
			int pci_wait_for_pending_transaction(struct pci_dev *dev)
	{		{
	int i;		int i;
	u32 cap;
	u16 status;		u16 status;

	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
	if (!(cap & PCI_EXP_DEVCAP_FLR))
	return -ENOTTY;

	if (probe)
	return 0;

	/* Wait for Transaction Pending bit clean */		/* Wait for Transaction Pending bit clean */
	for (i = 0; i < 4; i++) {		for (i = 0; i < 4; i++) {
	if (i)		if (i)
	@@ -3179,13 +3177,27 @@ static int pcie_flr(struct pci_dev *dev, int probe)

	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);		pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
	if (!(status & PCI_EXP_DEVSTA_TRPND))		if (!(status & PCI_EXP_DEVSTA_TRPND))
	goto clear;		return 1;
	}		}

	dev_err(&dev->dev, "transaction is not cleared; "		return 0;
	"proceeding with reset anyway\n");		}
			EXPORT_SYMBOL(pci_wait_for_pending_transaction);

			static int pcie_flr(struct pci_dev *dev, int probe)
			{
			u32 cap;

			pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
			if (!(cap & PCI_EXP_DEVCAP_FLR))
			return -ENOTTY;

			if (probe)
			return 0;

			if (!pci_wait_for_pending_transaction(dev))
			dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");

	clear:
	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);		pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);

	msleep(100);		msleep(100);

drivers/pci/quirks.c

+81 −16

Original line number	Original line	Diff line number	Diff line
	@@ -3126,9 +3126,6 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)

	static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)		static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
	{		{
	int i;
	u16 status;

	/*		/*
	* http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf		* http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
	*		*
	@@ -3140,20 +3137,9 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
	if (probe)		if (probe)
	return 0;		return 0;

	/* Wait for Transaction Pending bit clean */		if (!pci_wait_for_pending_transaction(dev))
	for (i = 0; i < 4; i++) {		dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
	if (i)
	msleep((1 << (i - 1)) * 100);

	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
	if (!(status & PCI_EXP_DEVSTA_TRPND))
	goto clear;
	}

	dev_err(&dev->dev, "transaction is not cleared; "
	"proceeding with reset anyway\n");

	clear:
	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);		pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);

	msleep(100);		msleep(100);
	@@ -3208,6 +3194,83 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
	return 0;		return 0;
	}		}

			/*
			* Device-specific reset method for Chelsio T4-based adapters.
			*/
			static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
			{
			u16 old_command;
			u16 msix_flags;

			/*
			* If this isn't a Chelsio T4-based device, return -ENOTTY indicating
			* that we have no device-specific reset method.
			*/
			if ((dev->device & 0xf000) != 0x4000)
			return -ENOTTY;

			/*
			* If this is the "probe" phase, return 0 indicating that we can
			* reset this device.
			*/
			if (probe)
			return 0;

			/*
			* T4 can wedge if there are DMAs in flight within the chip and Bus
			* Master has been disabled. We need to have it on till the Function
			* Level Reset completes. (BUS_MASTER is disabled in
			* pci_reset_function()).
			*/
			pci_read_config_word(dev, PCI_COMMAND, &old_command);
			pci_write_config_word(dev, PCI_COMMAND,
			old_command \| PCI_COMMAND_MASTER);

			/*
			* Perform the actual device function reset, saving and restoring
			* configuration information around the reset.
			*/
			pci_save_state(dev);

			/*
			* T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
			* are disabled when an MSI-X interrupt message needs to be delivered.
			* So we briefly re-enable MSI-X interrupts for the duration of the
			* FLR. The pci_restore_state() below will restore the original
			* MSI-X state.
			*/
			pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
			if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
			pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
			msix_flags \|
			PCI_MSIX_FLAGS_ENABLE \|
			PCI_MSIX_FLAGS_MASKALL);

			/*
			* Start of pcie_flr() code sequence. This reset code is a copy of
			* the guts of pcie_flr() because that's not an exported function.
			*/

			if (!pci_wait_for_pending_transaction(dev))
			dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");

			pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
			msleep(100);

			/*
			* End of pcie_flr() code sequence.
			*/

			/*
			* Restore the configuration information (BAR values, etc.) including
			* the original PCI Configuration Space Command word, and return
			* success.
			*/
			pci_restore_state(dev);
			pci_write_config_word(dev, PCI_COMMAND, old_command);
			return 0;
			}

	#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed		#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
	#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156		#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
	#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166		#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
	@@ -3221,6 +3284,8 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
	reset_ivb_igd },		reset_ivb_igd },
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,		{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	reset_intel_generic_dev },		reset_intel_generic_dev },
			{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			reset_chelsio_generic_dev },
	{ 0 }		{ 0 }
	};		};

include/linux/pci.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -914,6 +914,7 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev);
	void pci_msi_off(struct pci_dev *dev);		void pci_msi_off(struct pci_dev *dev);
	int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);		int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
	int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);		int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
			int pci_wait_for_pending_transaction(struct pci_dev *dev);
	int pcix_get_max_mmrbc(struct pci_dev *dev);		int pcix_get_max_mmrbc(struct pci_dev *dev);
	int pcix_get_mmrbc(struct pci_dev *dev);		int pcix_get_mmrbc(struct pci_dev *dev);
	int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);		int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);