staging: r8188eu: Remove ODM_Write1Byte (6348c232) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c

+9 −14

Original line number	Original line	Diff line number	Diff line
	@@ -868,7 +868,7 @@ _PHY_ReloadMACRegisters(

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) {		for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) {
	ODM_Write1Byte(dm_odm, MACReg[i], (u8)MACBackup[i]);		rtw_write8(adapt, MACReg[i], (u8)MACBackup[i]);
	}		}
	ODM_Write4Byte(dm_odm, MACReg[i], MACBackup[i]);		ODM_Write4Byte(dm_odm, MACReg[i], MACBackup[i]);
	}		}
	@@ -912,12 +912,12 @@ _PHY_MACSettingCalibration(

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));

	ODM_Write1Byte(dm_odm, MACReg[i], 0x3F);		rtw_write8(adapt, MACReg[i], 0x3F);

	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) {		for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) {
	ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));		rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
	}		}
	ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));		rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
	}		}

	void		void
	@@ -1223,16 +1223,14 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
	{		{
	u8 tmpreg;		u8 tmpreg;
	u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;		u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
	struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
	struct odm_dm_struct *dm_odm = &pHalData->odmpriv;

	/* Check continuous TX and Packet TX */		/* Check continuous TX and Packet TX */
	tmpreg = rtw_read8(adapt, 0xd03);		tmpreg = rtw_read8(adapt, 0xd03);

	if ((tmpreg&0x70) != 0) /* Deal with contisuous TX case */		if ((tmpreg&0x70) != 0) /* Deal with contisuous TX case */
	ODM_Write1Byte(dm_odm, 0xd03, tmpreg&0x8F); /* disable all continuous TX */		rtw_write8(adapt, 0xd03, tmpreg&0x8F); /* disable all continuous TX */
	else /* Deal with Packet TX case */		else /* Deal with Packet TX case */
	ODM_Write1Byte(dm_odm, REG_TXPAUSE, 0xFF); /* block all queues */		rtw_write8(adapt, REG_TXPAUSE, 0xFF); /* block all queues */

	if ((tmpreg&0x70) != 0) {		if ((tmpreg&0x70) != 0) {
	/* 1. Read original RF mode */		/* 1. Read original RF mode */
	@@ -1264,7 +1262,7 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
	if ((tmpreg&0x70) != 0) {		if ((tmpreg&0x70) != 0) {
	/* Deal with continuous TX case */		/* Deal with continuous TX case */
	/* Path-A */		/* Path-A */
	ODM_Write1Byte(dm_odm, 0xd03, tmpreg);		rtw_write8(adapt, 0xd03, tmpreg);
	PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);		PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);

	/* Path-B */		/* Path-B */
	@@ -1272,7 +1270,7 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
	PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);		PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
	} else {		} else {
	/* Deal with Packet TX case */		/* Deal with Packet TX case */
	ODM_Write1Byte(dm_odm, REG_TXPAUSE, 0x00);		rtw_write8(adapt, REG_TXPAUSE, 0x00);
	}		}
	}		}

	@@ -1468,13 +1466,10 @@ void PHY_LCCalibrate_8188E(struct adapter *adapt)

	static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t)		static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t)
	{		{
	struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
	struct odm_dm_struct *dm_odm = &pHalData->odmpriv;

	if (!adapt->hw_init_completed) {		if (!adapt->hw_init_completed) {
	u8 u1btmp;		u8 u1btmp;
	u1btmp = rtw_read8(adapt, REG_LEDCFG2) \| BIT7;		u1btmp = rtw_read8(adapt, REG_LEDCFG2) \| BIT7;
	ODM_Write1Byte(dm_odm, REG_LEDCFG2, u1btmp);		rtw_write8(adapt, REG_LEDCFG2, u1btmp);
	PHY_SetBBReg(adapt, rFPGA0_XAB_RFParameter, BIT13, 0x01);		PHY_SetBBReg(adapt, rFPGA0_XAB_RFParameter, BIT13, 0x01);
	}		}

drivers/staging/rtl8188eu/hal/odm.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -887,9 +887,10 @@ void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
	void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)		void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
	{		{
	struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;		struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
			struct adapter *adapt = pDM_Odm->Adapter;

	if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */		if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
	ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);		rtw_write8(adapt, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
	pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;		pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
	pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;		pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
	}		}

drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -66,7 +66,9 @@ void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data

	void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)		void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
	{		{
	ODM_Write1Byte(pDM_Odm, Addr, Data);		struct adapter *adapt = pDM_Odm->Adapter;

			rtw_write8(adapt, Addr, Data);
	ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));		ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
	}		}

drivers/staging/rtl8188eu/hal/odm_interface.c

+0 −6

Original line number	Original line	Diff line number	Diff line
	@@ -21,12 +21,6 @@
	#include "odm_precomp.h"		#include "odm_precomp.h"
	/* ODM IO Relative API. */		/* ODM IO Relative API. */

	void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u8 Data)
	{
	struct adapter *Adapter = pDM_Odm->Adapter;
	rtw_write8(Adapter, RegAddr, Data);
	}

	void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data)		void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data)
	{		{
	struct adapter *Adapter = pDM_Odm->Adapter;		struct adapter *Adapter = pDM_Odm->Adapter;

drivers/staging/rtl8188eu/include/odm_interface.h

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -77,8 +77,6 @@ typedef void (RT_WORKITEM_CALL_BACK)(void pContext);

	/* =========== EXtern Function Prototype */		/* =========== EXtern Function Prototype */

	void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u8 Data);

	void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data);		void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data);

	void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 Data);		void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 Data);