Commit 61f6ecb7 authored Aug 12, 2019 by Max Filippov Committed by Greg Kroah-Hartman Aug 25, 2019

xtensa: add missing isync to the cpu_reset TLB code



commit cd8869f4cb257f22b89495ca40f5281e58ba359c upstream.

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 7c001e5a

arch/xtensa/kernel/setup.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -515,6 +515,7 @@ void cpu_reset(void)
		"add %2, %2, %7\n\t"
		"addi %0, %0, -1\n\t"
		"bnez %0, 1b\n\t"
		"isync\n\t"
		/* Jump to identity mapping */
		"jx %3\n"
		"2:\n\t"