drm/msm/sde: remove transfer time factor in pclk calculation

With transfer time factor, pclk clock value is crossing low svs
corner in panels with high porch values resulting in power issues.
For any performance issues,  pclk override tuned clock
can be used.

Change-Id: I323c468f3582598173f059866838570092c5d1ef
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>