drm/gma500: begin pruning dead bits of API (61bedf70) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/gpu/drm/gma500/psb_drm.h

+23 −136

Original line number	Original line	Diff line number	Diff line
	@@ -24,168 +24,41 @@

	#define PSB_NUM_PIPE 3		#define PSB_NUM_PIPE 3

	#define PSB_GPU_ACCESS_READ (1ULL << 32)
	#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
	#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ \| PSB_GPU_ACCESS_WRITE)

	#define PSB_BO_FLAG_COMMAND (1ULL << 52)

	/*		/*
	* Feedback components:		* Manage the LUT for an output
	*/		*/

	struct drm_psb_sizes_arg {
	u32 ta_mem_size;
	u32 mmu_size;
	u32 pds_size;
	u32 rastgeom_size;
	u32 tt_size;
	u32 vram_size;
	};

	struct drm_psb_dpst_lut_arg {		struct drm_psb_dpst_lut_arg {
	uint8_t lut[256];		uint8_t lut[256];
	int output_id;		int output_id;
	};		};

	#define PSB_DC_CRTC_SAVE 0x01		/*
	#define PSB_DC_CRTC_RESTORE 0x02		* Validate modes
	#define PSB_DC_OUTPUT_SAVE 0x04		*/
	#define PSB_DC_OUTPUT_RESTORE 0x08
	#define PSB_DC_CRTC_MASK 0x03
	#define PSB_DC_OUTPUT_MASK 0x0C

	struct drm_psb_dc_state_arg {
	u32 flags;
	u32 obj_id;
	};

	struct drm_psb_mode_operation_arg {		struct drm_psb_mode_operation_arg {
	u32 obj_id;		u32 obj_id;
	u16 operation;		u16 operation;
	struct drm_mode_modeinfo mode;		struct drm_mode_modeinfo mode;
	void *data;		u64 data;
	};		};

			/*
			* Query the stolen memory for smarter management of
			* memory by the server
			*/
	struct drm_psb_stolen_memory_arg {		struct drm_psb_stolen_memory_arg {
	u32 base;		u32 base;
	u32 size;		u32 size;
	};		};

	/Display Register Bits/
	#define REGRWBITS_PFIT_CONTROLS (1 << 0)
	#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
	#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
	#define REGRWBITS_PIPEASRC (1 << 3)
	#define REGRWBITS_PIPEBSRC (1 << 4)
	#define REGRWBITS_VTOTAL_A (1 << 5)
	#define REGRWBITS_VTOTAL_B (1 << 6)
	#define REGRWBITS_DSPACNTR (1 << 8)
	#define REGRWBITS_DSPBCNTR (1 << 9)
	#define REGRWBITS_DSPCCNTR (1 << 10)

	/Overlay Register Bits/
	#define OV_REGRWBITS_OVADD (1 << 0)
	#define OV_REGRWBITS_OGAM_ALL (1 << 1)

	#define OVC_REGRWBITS_OVADD (1 << 2)
	#define OVC_REGRWBITS_OGAM_ALL (1 << 3)

	struct drm_psb_register_rw_arg {
	u32 b_force_hw_on;

	u32 display_read_mask;
	u32 display_write_mask;

	struct {
	u32 pfit_controls;
	u32 pfit_autoscale_ratios;
	u32 pfit_programmed_scale_ratios;
	u32 pipeasrc;
	u32 pipebsrc;
	u32 vtotal_a;
	u32 vtotal_b;
	} display;

	u32 overlay_read_mask;
	u32 overlay_write_mask;

	struct {
	u32 OVADD;
	u32 OGAMC0;
	u32 OGAMC1;
	u32 OGAMC2;
	u32 OGAMC3;
	u32 OGAMC4;
	u32 OGAMC5;
	u32 IEP_ENABLED;
	u32 IEP_BLE_MINMAX;
	u32 IEP_BSSCC_CONTROL;
	u32 b_wait_vblank;
	} overlay;

	u32 sprite_enable_mask;
	u32 sprite_disable_mask;

	struct {
	u32 dspa_control;
	u32 dspa_key_value;
	u32 dspa_key_mask;
	u32 dspc_control;
	u32 dspc_stride;
	u32 dspc_position;
	u32 dspc_linear_offset;
	u32 dspc_size;
	u32 dspc_surface;
	} sprite;

	u32 subpicture_enable_mask;
	u32 subpicture_disable_mask;
	};

	/* Controlling the kernel modesetting buffers */

	#define DRM_PSB_SIZES 0x07
	#define DRM_PSB_FUSE_REG 0x08
	#define DRM_PSB_DC_STATE 0x0A
	#define DRM_PSB_ADB 0x0B
	#define DRM_PSB_MODE_OPERATION 0x0C
	#define DRM_PSB_STOLEN_MEMORY 0x0D
	#define DRM_PSB_REGISTER_RW 0x0E

	/*
	* NOTE: Add new commands here, but increment
	* the values below and increment their
	* corresponding defines where they're
	* defined elsewhere.
	*/

	#define DRM_PSB_GEM_CREATE 0x10
	#define DRM_PSB_2D_OP 0x11 /* Will be merged later */
	#define DRM_PSB_GEM_MMAP 0x12
	#define DRM_PSB_DPST 0x1B
	#define DRM_PSB_GAMMA 0x1C
	#define DRM_PSB_DPST_BL 0x1D
	#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F

	#define PSB_MODE_OPERATION_MODE_VALID 0x01
	#define PSB_MODE_OPERATION_SET_DC_BASE 0x02

	struct drm_psb_get_pipe_from_crtc_id_arg {		struct drm_psb_get_pipe_from_crtc_id_arg {
	/ ID of CRTC being requested /		/ ID of CRTC being requested /
	u32 crtc_id;		u32 crtc_id;

	/ pipe of requested CRTC /		/ pipe of requested CRTC /
	u32 pipe;		u32 pipe;
	};		};

	/* FIXME: move this into a medfield header once we are sure it isn't needed for an
	ioctl */
	struct psb_drm_dpu_rect {
	int x, y;
	int width, height;
	};

	struct drm_psb_gem_create {		struct drm_psb_gem_create {
	__u64 size;		__u64 size;
	__u32 handle;		__u32 handle;
	@@ -204,4 +77,18 @@ struct drm_psb_gem_mmap {
	__u64 offset;		__u64 offset;
	};		};

			/* Controlling the kernel modesetting buffers */

			#define DRM_PSB_GEM_CREATE 0x00 /* Create a GEM object */
			#define DRM_PSB_GEM_MMAP 0x01 /* Map GEM memory */
			#define DRM_PSB_STOLEN_MEMORY 0x02 /* Report stolen memory */
			#define DRM_PSB_2D_OP 0x03 /* Will be merged later */
			#define DRM_PSB_GAMMA 0x04 /* Set gamma table */
			#define DRM_PSB_ADB 0x05 /* Get backlight */
			#define DRM_PSB_DPST_BL 0x06 /* Set backlight */
			#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1 /* CRTC to physical pipe# */
			#define DRM_PSB_MODE_OPERATION 0x07 /* Mode validation/DC set */
			#define PSB_MODE_OPERATION_MODE_VALID 0x01


	#endif		#endif

drivers/gpu/drm/gma500/psb_drv.c

+1 −506

Original line number	Original line	Diff line number	Diff line
	@@ -80,14 +80,6 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
	* Standard IOCTLs.		* Standard IOCTLs.
	*/		*/

	#define DRM_IOCTL_PSB_SIZES \
	DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
	struct drm_psb_sizes_arg)
	#define DRM_IOCTL_PSB_FUSE_REG \
	DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
	#define DRM_IOCTL_PSB_DC_STATE \
	DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
	struct drm_psb_dc_state_arg)
	#define DRM_IOCTL_PSB_ADB \		#define DRM_IOCTL_PSB_ADB \
	DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)		DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
	#define DRM_IOCTL_PSB_MODE_OPERATION \		#define DRM_IOCTL_PSB_MODE_OPERATION \
	@@ -96,12 +88,6 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
	#define DRM_IOCTL_PSB_STOLEN_MEMORY \		#define DRM_IOCTL_PSB_STOLEN_MEMORY \
	DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \		DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
	struct drm_psb_stolen_memory_arg)		struct drm_psb_stolen_memory_arg)
	#define DRM_IOCTL_PSB_REGISTER_RW \
	DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
	struct drm_psb_register_rw_arg)
	#define DRM_IOCTL_PSB_DPST \
	DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
	uint32_t)
	#define DRM_IOCTL_PSB_GAMMA \		#define DRM_IOCTL_PSB_GAMMA \
	DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \		DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
	struct drm_psb_dpst_lut_arg)		struct drm_psb_dpst_lut_arg)
	@@ -118,20 +104,12 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
	DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \		DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \
	struct drm_psb_gem_mmap)		struct drm_psb_gem_mmap)

	static int psb_sizes_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);
	static int psb_dc_state_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);
	static int psb_adb_ioctl(struct drm_device dev, void data,		static int psb_adb_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);		struct drm_file *file_priv);
	static int psb_mode_operation_ioctl(struct drm_device dev, void data,		static int psb_mode_operation_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);		struct drm_file *file_priv);
	static int psb_stolen_memory_ioctl(struct drm_device dev, void data,		static int psb_stolen_memory_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);		struct drm_file *file_priv);
	static int psb_register_rw_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);
	static int psb_dpst_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);
	static int psb_gamma_ioctl(struct drm_device dev, void data,		static int psb_gamma_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv);		struct drm_file *file_priv);
	static int psb_dpst_bl_ioctl(struct drm_device dev, void data,		static int psb_dpst_bl_ioctl(struct drm_device dev, void data,
	@@ -141,16 +119,11 @@ static int psb_dpst_bl_ioctl(struct drm_device dev, void data,
	[DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}		[DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}

	static struct drm_ioctl_desc psb_ioctls[] = {		static struct drm_ioctl_desc psb_ioctls[] = {
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),		PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,		PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
	DRM_AUTH),		DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,		PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
	DRM_AUTH),		DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
	DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),		PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),		PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
	PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,		PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
	@@ -442,75 +415,6 @@ int psb_driver_device_is_agp(struct drm_device *dev)
	return 0;		return 0;
	}		}


	static int psb_sizes_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv)
	{
	struct drm_psb_private *dev_priv = psb_priv(dev);
	struct drm_psb_sizes_arg *arg =
	(struct drm_psb_sizes_arg *) data;

	*arg = dev_priv->sizes;
	return 0;
	}

	static int psb_dc_state_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv)
	{
	uint32_t flags;
	uint32_t obj_id;
	struct drm_mode_object *obj;
	struct drm_connector *connector;
	struct drm_crtc *crtc;
	struct drm_psb_dc_state_arg *arg = data;


	/* Double check MRST case */
	if (IS_MRST(dev) \|\| IS_MFLD(dev))
	return -EOPNOTSUPP;

	flags = arg->flags;
	obj_id = arg->obj_id;

	if (flags & PSB_DC_CRTC_MASK) {
	obj = drm_mode_object_find(dev, obj_id,
	DRM_MODE_OBJECT_CRTC);
	if (!obj) {
	dev_dbg(dev->dev, "Invalid CRTC object.\n");
	return -EINVAL;
	}

	crtc = obj_to_crtc(obj);

	mutex_lock(&dev->mode_config.mutex);
	if (drm_helper_crtc_in_use(crtc)) {
	if (flags & PSB_DC_CRTC_SAVE)
	crtc->funcs->save(crtc);
	else
	crtc->funcs->restore(crtc);
	}
	mutex_unlock(&dev->mode_config.mutex);

	return 0;
	} else if (flags & PSB_DC_OUTPUT_MASK) {
	obj = drm_mode_object_find(dev, obj_id,
	DRM_MODE_OBJECT_CONNECTOR);
	if (!obj) {
	dev_dbg(dev->dev, "Invalid connector id.\n");
	return -EINVAL;
	}

	connector = obj_to_connector(obj);
	if (flags & PSB_DC_OUTPUT_SAVE)
	connector->funcs->save(connector);
	else
	connector->funcs->restore(connector);

	return 0;
	}
	return -EINVAL;
	}

	static inline void get_brightness(struct backlight_device *bd)		static inline void get_brightness(struct backlight_device *bd)
	{		{
	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE		#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	@@ -543,36 +447,6 @@ static int psb_adb_ioctl(struct drm_device dev, void data,
	return 0;		return 0;
	}		}

	/* return the current mode to the dpst module */
	static int psb_dpst_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv)
	{
	struct drm_psb_private *dev_priv = psb_priv(dev);
	uint32_t *arg = data;
	uint32_t x;
	uint32_t y;
	uint32_t reg;

	if (!gma_power_begin(dev, 0))
	return -EIO;

	reg = PSB_RVDC32(PIPEASRC);

	gma_power_end(dev);

	/* horizontal is the left 16 bits */
	x = reg >> 16;
	/* vertical is the right 16 bits */
	y = reg & 0x0000ffff;

	/* the values are the image size minus one */
	x++;
	y++;

	*arg = (x << 16) \| y;

	return 0;
	}
	static int psb_gamma_ioctl(struct drm_device dev, void data,		static int psb_gamma_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv)		struct drm_file *file_priv)
	{		{
	@@ -613,37 +487,15 @@ static int psb_mode_operation_ioctl(struct drm_device dev, void data,
	struct drm_psb_mode_operation_arg *arg;		struct drm_psb_mode_operation_arg *arg;
	struct drm_mode_object *obj;		struct drm_mode_object *obj;
	struct drm_connector *connector;		struct drm_connector *connector;
	struct drm_framebuffer *drm_fb;
	struct psb_framebuffer *psb_fb;
	struct drm_connector_helper_funcs *connector_funcs;		struct drm_connector_helper_funcs *connector_funcs;
	int ret = 0;		int ret = 0;
	int resp = MODE_OK;		int resp = MODE_OK;
	struct drm_psb_private *dev_priv = psb_priv(dev);

	arg = (struct drm_psb_mode_operation_arg *)data;		arg = (struct drm_psb_mode_operation_arg *)data;
	obj_id = arg->obj_id;		obj_id = arg->obj_id;
	op = arg->operation;		op = arg->operation;

	switch (op) {		switch (op) {
	case PSB_MODE_OPERATION_SET_DC_BASE:
	obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
	if (!obj) {
	dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
	return -EINVAL;
	}

	drm_fb = obj_to_fb(obj);
	psb_fb = to_psb_fb(drm_fb);

	if (gma_power_begin(dev, 0)) {
	REG_WRITE(DSPASURF, psb_fb->gtt->offset);
	REG_READ(DSPASURF);
	gma_power_end(dev);
	} else {
	dev_priv->saveDSPASURF = psb_fb->gtt->offset;
	}

	return 0;
	case PSB_MODE_OPERATION_MODE_VALID:		case PSB_MODE_OPERATION_MODE_VALID:
	umode = &arg->mode;		umode = &arg->mode;

	@@ -689,7 +541,7 @@ static int psb_mode_operation_ioctl(struct drm_device dev, void data,

	if (connector_funcs->mode_valid) {		if (connector_funcs->mode_valid) {
	resp = connector_funcs->mode_valid(connector, mode);		resp = connector_funcs->mode_valid(connector, mode);
	arg->data = (void *)resp;		arg->data = resp;
	}		}

	/do some clean up work/		/do some clean up work/
	@@ -719,363 +571,6 @@ static int psb_stolen_memory_ioctl(struct drm_device dev, void data,
	return 0;		return 0;
	}		}

	/* FIXME: needs Medfield changes */
	static int psb_register_rw_ioctl(struct drm_device dev, void data,
	struct drm_file *file_priv)
	{
	struct drm_psb_private *dev_priv = psb_priv(dev);
	struct drm_psb_register_rw_arg *arg = data;
	bool usage = arg->b_force_hw_on ? true : false;

	if (arg->display_write_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
	PSB_WVDC32(arg->display.pfit_controls,
	PFIT_CONTROL);
	if (arg->display_write_mask &
	REGRWBITS_PFIT_AUTOSCALE_RATIOS)
	PSB_WVDC32(arg->display.pfit_autoscale_ratios,
	PFIT_AUTO_RATIOS);
	if (arg->display_write_mask &
	REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
	PSB_WVDC32(
	arg->display.pfit_programmed_scale_ratios,
	PFIT_PGM_RATIOS);
	if (arg->display_write_mask & REGRWBITS_PIPEASRC)
	PSB_WVDC32(arg->display.pipeasrc,
	PIPEASRC);
	if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
	PSB_WVDC32(arg->display.pipebsrc,
	PIPEBSRC);
	if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
	PSB_WVDC32(arg->display.vtotal_a,
	VTOTAL_A);
	if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
	PSB_WVDC32(arg->display.vtotal_b,
	VTOTAL_B);
	gma_power_end(dev);
	} else {
	if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
	dev_priv->savePFIT_CONTROL =
	arg->display.pfit_controls;
	if (arg->display_write_mask &
	REGRWBITS_PFIT_AUTOSCALE_RATIOS)
	dev_priv->savePFIT_AUTO_RATIOS =
	arg->display.pfit_autoscale_ratios;
	if (arg->display_write_mask &
	REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
	dev_priv->savePFIT_PGM_RATIOS =
	arg->display.pfit_programmed_scale_ratios;
	if (arg->display_write_mask & REGRWBITS_PIPEASRC)
	dev_priv->savePIPEASRC = arg->display.pipeasrc;
	if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
	dev_priv->savePIPEBSRC = arg->display.pipebsrc;
	if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
	dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
	if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
	dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
	}
	}

	if (arg->display_read_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	if (arg->display_read_mask &
	REGRWBITS_PFIT_CONTROLS)
	arg->display.pfit_controls =
	PSB_RVDC32(PFIT_CONTROL);
	if (arg->display_read_mask &
	REGRWBITS_PFIT_AUTOSCALE_RATIOS)
	arg->display.pfit_autoscale_ratios =
	PSB_RVDC32(PFIT_AUTO_RATIOS);
	if (arg->display_read_mask &
	REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
	arg->display.pfit_programmed_scale_ratios =
	PSB_RVDC32(PFIT_PGM_RATIOS);
	if (arg->display_read_mask & REGRWBITS_PIPEASRC)
	arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
	if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
	arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
	if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
	arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
	if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
	arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
	gma_power_end(dev);
	} else {
	if (arg->display_read_mask &
	REGRWBITS_PFIT_CONTROLS)
	arg->display.pfit_controls =
	dev_priv->savePFIT_CONTROL;
	if (arg->display_read_mask &
	REGRWBITS_PFIT_AUTOSCALE_RATIOS)
	arg->display.pfit_autoscale_ratios =
	dev_priv->savePFIT_AUTO_RATIOS;
	if (arg->display_read_mask &
	REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
	arg->display.pfit_programmed_scale_ratios =
	dev_priv->savePFIT_PGM_RATIOS;
	if (arg->display_read_mask & REGRWBITS_PIPEASRC)
	arg->display.pipeasrc = dev_priv->savePIPEASRC;
	if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
	arg->display.pipebsrc = dev_priv->savePIPEBSRC;
	if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
	arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
	if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
	arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
	}
	}

	if (arg->overlay_write_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
	PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
	PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
	PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
	PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
	PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
	PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
	}
	if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
	PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
	PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
	PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
	PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
	PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
	PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
	}

	if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
	PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);

	if (arg->overlay.b_wait_vblank) {
	/* Wait for 20ms.*/
	unsigned long vblank_timeout = jiffies
	+ HZ/50;
	uint32_t temp;
	while (time_before_eq(jiffies,
	vblank_timeout)) {
	temp = PSB_RVDC32(OV_DOVASTA);
	if ((temp & (0x1 << 31)) != 0)
	break;
	cpu_relax();
	}
	}
	}
	if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
	PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
	if (arg->overlay.b_wait_vblank) {
	/* Wait for 20ms.*/
	unsigned long vblank_timeout =
	jiffies + HZ/50;
	uint32_t temp;
	while (time_before_eq(jiffies,
	vblank_timeout)) {
	temp = PSB_RVDC32(OVC_DOVCSTA);
	if ((temp & (0x1 << 31)) != 0)
	break;
	cpu_relax();
	}
	}
	}
	gma_power_end(dev);
	} else {
	if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
	dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
	dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
	dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
	dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
	dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
	dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
	}
	if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
	dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
	dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
	dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
	dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
	dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
	dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
	}
	if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
	dev_priv->saveOV_OVADD = arg->overlay.OVADD;
	if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
	dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
	}
	}

	if (arg->overlay_read_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
	arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
	arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
	arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
	arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
	arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
	arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
	}
	if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
	arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
	arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
	arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
	arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
	arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
	arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
	}
	if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
	arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
	if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
	arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
	gma_power_end(dev);
	} else {
	if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
	arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
	arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
	arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
	arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
	arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
	arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
	}
	if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
	arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
	arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
	arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
	arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
	arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
	arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
	}
	if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
	arg->overlay.OVADD = dev_priv->saveOV_OVADD;
	if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
	arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
	}
	}

	if (arg->sprite_enable_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	PSB_WVDC32(0x1F3E, DSPARB);
	PSB_WVDC32(arg->sprite.dspa_control
	\| PSB_RVDC32(DSPACNTR), DSPACNTR);
	PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
	PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
	PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
	PSB_RVDC32(DSPASURF);
	PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
	PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
	PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
	PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
	PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
	PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
	PSB_RVDC32(DSPCSURF);
	gma_power_end(dev);
	}
	}

	if (arg->sprite_disable_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	PSB_WVDC32(0x3F3E, DSPARB);
	PSB_WVDC32(0x0, DSPCCNTR);
	PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
	PSB_RVDC32(DSPCSURF);
	gma_power_end(dev);
	}
	}

	if (arg->subpicture_enable_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	uint32_t temp;
	if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
	temp = PSB_RVDC32(DSPACNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp &= ~DISPPLANE_BOTTOM;
	temp \|= DISPPLANE_32BPP;
	PSB_WVDC32(temp, DSPACNTR);

	temp = PSB_RVDC32(DSPABASE);
	PSB_WVDC32(temp, DSPABASE);
	PSB_RVDC32(DSPABASE);
	temp = PSB_RVDC32(DSPASURF);
	PSB_WVDC32(temp, DSPASURF);
	PSB_RVDC32(DSPASURF);
	}
	if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
	temp = PSB_RVDC32(DSPBCNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp &= ~DISPPLANE_BOTTOM;
	temp \|= DISPPLANE_32BPP;
	PSB_WVDC32(temp, DSPBCNTR);

	temp = PSB_RVDC32(DSPBBASE);
	PSB_WVDC32(temp, DSPBBASE);
	PSB_RVDC32(DSPBBASE);
	temp = PSB_RVDC32(DSPBSURF);
	PSB_WVDC32(temp, DSPBSURF);
	PSB_RVDC32(DSPBSURF);
	}
	if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
	temp = PSB_RVDC32(DSPCCNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp &= ~DISPPLANE_BOTTOM;
	temp \|= DISPPLANE_32BPP;
	PSB_WVDC32(temp, DSPCCNTR);

	temp = PSB_RVDC32(DSPCBASE);
	PSB_WVDC32(temp, DSPCBASE);
	PSB_RVDC32(DSPCBASE);
	temp = PSB_RVDC32(DSPCSURF);
	PSB_WVDC32(temp, DSPCSURF);
	PSB_RVDC32(DSPCSURF);
	}
	gma_power_end(dev);
	}
	}

	if (arg->subpicture_disable_mask != 0) {
	if (gma_power_begin(dev, usage)) {
	uint32_t temp;
	if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
	temp = PSB_RVDC32(DSPACNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp \|= DISPPLANE_32BPP_NO_ALPHA;
	PSB_WVDC32(temp, DSPACNTR);

	temp = PSB_RVDC32(DSPABASE);
	PSB_WVDC32(temp, DSPABASE);
	PSB_RVDC32(DSPABASE);
	temp = PSB_RVDC32(DSPASURF);
	PSB_WVDC32(temp, DSPASURF);
	PSB_RVDC32(DSPASURF);
	}
	if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
	temp = PSB_RVDC32(DSPBCNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp \|= DISPPLANE_32BPP_NO_ALPHA;
	PSB_WVDC32(temp, DSPBCNTR);

	temp = PSB_RVDC32(DSPBBASE);
	PSB_WVDC32(temp, DSPBBASE);
	PSB_RVDC32(DSPBBASE);
	temp = PSB_RVDC32(DSPBSURF);
	PSB_WVDC32(temp, DSPBSURF);
	PSB_RVDC32(DSPBSURF);
	}
	if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
	temp = PSB_RVDC32(DSPCCNTR);
	temp &= ~DISPPLANE_PIXFORMAT_MASK;
	temp \|= DISPPLANE_32BPP_NO_ALPHA;
	PSB_WVDC32(temp, DSPCCNTR);

	temp = PSB_RVDC32(DSPCBASE);
	PSB_WVDC32(temp, DSPCBASE);
	PSB_RVDC32(DSPCBASE);
	temp = PSB_RVDC32(DSPCSURF);
	PSB_WVDC32(temp, DSPCSURF);
	PSB_RVDC32(DSPCSURF);
	}
	gma_power_end(dev);
	}
	}

	return 0;
	}

	static int psb_driver_open(struct drm_device dev, struct drm_file priv)		static int psb_driver_open(struct drm_device dev, struct drm_file priv)
	{		{
	return 0;		return 0;

drivers/gpu/drm/gma500/psb_drv.h

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -324,8 +324,6 @@ struct drm_psb_private {
	* Sizes info		* Sizes info
	*/		*/

	struct drm_psb_sizes_arg sizes;

	u32 fuse_reg_value;		u32 fuse_reg_value;
	u32 video_device_fuse;		u32 video_device_fuse;