clk: qcom: Update CRC register offsets for Atoll



Update the CRC_SID_FSM_CTRL and CRC_MND_CFG register
offsets for enabling CRC in NPU CC.

Change-Id: I52a4ff76c70a0924601a59d60dc33dac7b4a0108
Signed-off-by: Diptanshu Jamgade <djamgade@codeaurora.org>

parent e56ced08

drivers/clk/qcom/npucc-atoll.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -37,9 +37,9 @@

		#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }

		#define CRC_SID_FSM_CTRL 0x100c
		#define CRC_SID_FSM_CTRL 0x11a0
		#define CRC_SID_FSM_CTRL_SETTING 0x800000
		#define CRC_MND_CFG 0x1010
		#define CRC_MND_CFG 0x11a4
		#define CRC_MND_CFG_SETTING 0x15011

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);