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Commit 60f975b9 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: reparent sclk to pll_c_out1 



pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent c8b62ab4

arch/arm/mach-tegra/common.c

+4 −2
Original line number Diff line number Diff line
@@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { 
	{ "pll_p_out2",	"pll_p",	48000000,	true },

	{ "pll_p_out3",	"pll_p",	72000000,	true },

	{ "pll_p_out4",	"pll_p",	108000000,	true },

	{ "sclk",	"pll_p_out4",	108000000,	true },

	{ "hclk",	"sclk",		108000000,	true },

	{ "pll_c",	"clk_m",	600000000,	true },

	{ "pll_c_out1",	"pll_c",	120000000,	true },

	{ "sclk",	"pll_c_out1",	120000000,	true },

	{ "hclk",	"sclk",		120000000,	true },

	{ "pclk",	"hclk",		54000000,	true },

	{ "csite",	NULL,		0,		true },

	{ "emc",	NULL,		0,		true },