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Commit 5ff807a5 authored by Frank Li's avatar Frank Li Committed by Shawn Guo
Browse files

ARM: dts: imx6ul: add qspi support 



enable qspi support

Signed-off-by: default avatarFrank Li <Frank.Li@freescale.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 4e06dfab

arch/arm/boot/dts/imx6ul-14x14-evk.dts

+25 −0
Original line number Diff line number Diff line
@@ -44,6 +44,20 @@ 
	soc-supply = <&reg_soc>;

};



&qspi {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_qspi>;

	status = "okay";



	flash0: n25q256a@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "micron,n25q256a";

		spi-max-frequency = <29000000>;

		reg = <0>;

	};

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;
@@ -206,6 +220,17 @@ 
		>;

	};



	pinctrl_qspi: qspigrp {

		fsl,pins = <

			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK	0x70a1

			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00	0x70a1

			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01	0x70a1

			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02	0x70a1

			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03	0x70a1

			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B	0x70a1

		>;

	};



	pinctrl_pwm1: pwm1grp {

		fsl,pins = <

			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0

arch/arm/boot/dts/imx6ul.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -565,6 +565,19 @@ 
				status = "disabled";

			};



			qspi: qspi@021e0000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";

				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;

				reg-names = "QuadSPI", "QuadSPI-memory";

				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_QSPI>,

					 <&clks IMX6UL_CLK_QSPI>;

				clock-names = "qspi_en", "qspi";

				status = "disabled";

			};



			uart2: serial@021e8000 {

				compatible = "fsl,imx6ul-uart",

					     "fsl,imx6q-uart";