Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5eff503b authored by Maarten Lankhorst's avatar Maarten Lankhorst
Browse files

drm/i915/gen9+: Kill off hw_ddb from intel_crtc. 



dev_priv->hw_ddb is only used by skl_update_crtcs, but the ddb
allocation for each pipe is calculated in crtc_state.

We can rid of the global member by looking at crtc_state.
Do this by saving all active old ddb allocations from the old crtc_state
in an array, and then point them to the new allocation every time we update
a crtc.

This will allow us to keep track of the intermediate ddb allocations,
which is what hw_ddb was previously used for. With hw_ddb gone all
SKL-style watermark values are properly maintained only in crtc_state.

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478609742-13603-5-git-send-email-maarten.lankhorst@linux.intel.com


[mlankhorst: Reword commit message.]
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 512b5527

drivers/gpu/drm/i915/intel_display.c

+12 −3
Original line number Diff line number Diff line
@@ -14304,6 +14304,14 @@ static void skl_update_crtcs(struct drm_atomic_state *state, 
	unsigned int updated = 0;

	bool progress;

	enum pipe pipe;

	int i;



	const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};



	for_each_crtc_in_state(state, crtc, old_crtc_state, i)

		/* ignore allocations for crtc's that have been turned off. */

		if (crtc->state->active)

			entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;



	/*

	 * Whenever the number of active pipes changes, we need to make sure we
@@ -14312,7 +14320,6 @@ static void skl_update_crtcs(struct drm_atomic_state *state, 
	 * cause pipe underruns and other bad stuff.

	 */

	do {

		int i;

		progress = false;



		for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
@@ -14323,12 +14330,14 @@ static void skl_update_crtcs(struct drm_atomic_state *state, 
			cstate = to_intel_crtc_state(crtc->state);

			pipe = intel_crtc->pipe;



			if (updated & cmask || !crtc->state->active)

			if (updated & cmask || !cstate->base.active)

				continue;

			if (skl_ddb_allocation_overlaps(state, intel_crtc))



			if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))

				continue;



			updated |= cmask;

			entries[i] = &cstate->wm.skl.ddb;



			/*

			 * If this is an already active pipe, it's DDB changed,

drivers/gpu/drm/i915/intel_drv.h

+3 −8
Original line number Diff line number Diff line
@@ -727,9 +727,6 @@ struct intel_crtc { 
		bool cxsr_allowed;

	} wm;



	/* gen9+: ddb allocation currently being used */

	struct skl_ddb_entry hw_ddb;



	int scanline_offset;



	struct {
@@ -1739,11 +1736,9 @@ int intel_enable_sagv(struct drm_i915_private *dev_priv); 
int intel_disable_sagv(struct drm_i915_private *dev_priv);

bool skl_wm_level_equals(const struct skl_wm_level *l1,

			 const struct skl_wm_level *l2);

bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,

			       const struct skl_ddb_allocation *new,

			       enum pipe pipe);

bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,

				 struct intel_crtc *intel_crtc);

bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,

				 const struct skl_ddb_entry *ddb,

				 int ignore);

uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);

bool ilk_disable_lp_wm(struct drm_device *dev);

int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);

drivers/gpu/drm/i915/intel_pm.c

+7 −18
Original line number Diff line number Diff line
@@ -3913,25 +3913,16 @@ static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, 
	return a->start < b->end && b->start < a->end;

}



bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,

				 struct intel_crtc *intel_crtc)

{

	struct drm_crtc *other_crtc;

	struct drm_crtc_state *other_cstate;

	struct intel_crtc *other_intel_crtc;

	const struct skl_ddb_entry *ddb =

		&to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;

bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,

				 const struct skl_ddb_entry *ddb,

				 int ignore)

{

	int i;



	for_each_crtc_in_state(state, other_crtc, other_cstate, i) {

		other_intel_crtc = to_intel_crtc(other_crtc);



		if (other_intel_crtc == intel_crtc)

			continue;



		if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))

	for (i = 0; i < I915_MAX_PIPES; i++)

		if (i != ignore && entries[i] &&

		    skl_ddb_entries_overlap(ddb, entries[i]))

			return true;

	}



	return false;

}
@@ -4241,8 +4232,6 @@ static void skl_initial_wm(struct intel_atomic_state *state, 


	skl_copy_wm_for_pipe(hw_vals, results, pipe);



	intel_crtc->hw_ddb = cstate->wm.skl.ddb;



	mutex_unlock(&dev_priv->wm.wm_mutex);

}