Commit 5e2c5c41 authored May 21, 2018 by Shaoqing Liu

ARM: dts: msm: Add cti0 for tmc-etr/etf node for sm8150



TMC(Trace Memory Controller) is designed as a successor
to the coresight embedded trace buffer that enables you
to capture trace using device node: coresight-tmc-etr(ddr mode)
or coresight-tmc-etf(etb mode).
Add cti0 for tmc-etr/etf node for supporting reset and flush
operation in TMC driver.

CRs-Fixed: 2256917
Change-Id: I0530ea4bbe78c4b87c80d68e2179e6452ad8f018
Signed-off-by: Shaoqing Liu <shaoqingliu@codeaurora.org>

parent e579714d

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

+2 −2

Original line number	Diff line number	Diff line
		@@ -325,7 +325,7 @@
		arm,buffer-size = <0x400000>;

		coresight-name = "coresight-tmc-etr";
		coresight-ctis = <&cti0>;
		coresight-ctis = <&cti0 &cti0>;
		coresight-csr = <&csr>;

		clocks = <&clock_aop QDSS_CLK>;
		@@ -350,7 +350,7 @@
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";
		coresight-ctis = <&cti0>;
		coresight-ctis = <&cti0 &cti0>;
		coresight-csr = <&csr>;
		arm,default-sink;