Merge "msm: camera: ppi: Change PPI reset sequence" (5d278ade) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.c

+34 −40

Original line number	Diff line number	Diff line
		@@ -24,8 +24,6 @@ static int cam_csid_ppi_reset(struct cam_csid_ppi_hw *ppi_hw)
		struct cam_hw_soc_info *soc_info;
		const struct cam_csid_ppi_reg_offset *ppi_reg;
		int rc = 0;
		uint32_t val = 0;
		uint32_t clear_mask;
		uint32_t status;

		soc_info = &ppi_hw->hw_info->soc_info;
		@@ -36,36 +34,29 @@ static int cam_csid_ppi_reset(struct cam_csid_ppi_hw *ppi_hw)
		/* Mask all interrupts */
		cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_mask_addr);

		/* clear all interrupts */
		clear_mask = PPI_IRQ_FIFO0_OVERFLOW \| PPI_IRQ_FIFO1_OVERFLOW \|
		PPI_IRQ_FIFO2_OVERFLOW;
		cam_io_w_mb(clear_mask, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_clear_addr);
		cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_cmd_addr);

		/* perform the top PPI HW registers reset */
		cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_set_addr);
		cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_rst_cmd_addr);
		cam_io_w_mb(PPI_IRQ_CMD_SET, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_cmd_addr);

		rc = readl_poll_timeout(soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_status_addr, status,
		(status & 0x1) == 0x1, 1000, 100000);
		(status & 0x1) == 0x1, 1000, 500000);
		CAM_DBG(CAM_ISP, "PPI:%d reset status %d", ppi_hw->hw_intf->hw_idx,
		status);
		if (rc < 0) {
		CAM_ERR(CAM_ISP, "PPI:%d ppi_reset fail rc = %d",
		ppi_hw->hw_intf->hw_idx, rc);
		rc = -ETIMEDOUT;
		CAM_ERR(CAM_ISP, "PPI:%d ppi_reset fail rc = %d status = %d",
		ppi_hw->hw_intf->hw_idx, rc, status);
		return rc;
		}
		CAM_DBG(CAM_ISP, "PPI: reset status %d", status);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_mask_addr);
		if (val != 0)
		CAM_ERR(CAM_ISP, "PPI:%d IRQ value after reset rc = %d",
		ppi_hw->hw_intf->hw_idx, val);
		cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_clear_addr);
		cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_cmd_addr);

		return rc;
		return 0;
		}

		static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
		@@ -75,6 +66,7 @@ static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
		uint64_t val;
		const struct cam_csid_ppi_reg_offset *ppi_reg;
		struct cam_hw_soc_info *soc_info;
		uint32_t err_irq_mask;

		ppi_reg = ppi_hw->ppi_info->ppi_reg;
		soc_info = &ppi_hw->hw_info->soc_info;
		@@ -89,35 +81,34 @@ static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
		goto clk_disable;
		}

		rc = cam_soc_util_irq_enable(soc_info);
		if (rc)
		goto clk_disable;

		/* Reset PPI */
		rc = cam_csid_ppi_reset(ppi_hw);
		if (rc)
		goto irq_disable;
		goto clk_disable;

		err_irq_mask = PPI_IRQ_FIFO0_OVERFLOW \| PPI_IRQ_FIFO1_OVERFLOW \|
		PPI_IRQ_FIFO2_OVERFLOW;
		cam_io_w_mb(err_irq_mask, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_mask_addr);
		rc = cam_soc_util_irq_enable(soc_info);
		if (rc)
		goto clk_disable;
		/* Clear the RST done IRQ */
		cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
		cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_clear_addr);
		cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
		cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_cmd_addr);

		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_hw_version_addr);
		CAM_DBG(CAM_ISP, "PPI:%d PPI HW version: 0x%x",
		ppi_hw->hw_intf->hw_idx, val);

		ppi_hw->device_enabled = 1;

		return 0;
		irq_disable:
		cam_soc_util_irq_disable(soc_info);
		clk_disable:
		for (i--; i >= 0; i--) {
		for (--i; i >= 0; i--)
		cam_soc_util_clk_disable(soc_info->clk[i],
		soc_info->clk_name[i]);
		}
		return rc;
		}

		@@ -234,6 +225,10 @@ static int cam_csid_ppi_init_hw(void hw_priv, void init_args,
		soc_info = &ppi_hw->hw_info->soc_info;
		cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_module_cfg_addr);

		CAM_DBG(CAM_ISP, "ppi cfg 0x%x",
		cam_io_r_mb(soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_module_cfg_addr));
		end:
		return rc;
		}
		@@ -341,7 +336,6 @@ irqreturn_t cam_csid_ppi_irq(int irq_num, void *data)
		}

		ppi_hw = (struct cam_csid_ppi_hw *)data;
		CAM_DBG(CAM_ISP, "PPI %d IRQ Handling", ppi_hw->hw_intf->hw_idx);
		ppi_reg = ppi_hw->ppi_info->ppi_reg;
		soc_info = &ppi_hw->hw_info->soc_info;

		@@ -353,7 +347,7 @@ irqreturn_t cam_csid_ppi_irq(int irq_num, void *data)
		cam_io_w_mb(irq_status, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_clear_addr);

		cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
		cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base +
		ppi_reg->ppi_irq_cmd_addr);

		CAM_DBG(CAM_ISP, "PPI %d irq status 0x%x", ppi_hw->hw_intf->hw_idx,

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -24,7 +24,7 @@
		#define PPI_IRQ_FIFO1_OVERFLOW BIT(2)
		#define PPI_IRQ_FIFO2_OVERFLOW BIT(3)

		#define PPI_IRQ_CMD_SET BIT(0)
		#define PPI_IRQ_CMD_SET BIT(1)

		#define PPI_IRQ_CMD_CLEAR BIT(0)