ARM: dts: msm: Add coresight nodes for sdmshrike (5c7f3c52) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sdmshrike-coresight.dtsi

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		/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		&soc {
		csr: csr@0x6001000 {
		compatible = "qcom,coresight-csr";
		reg = <0x6001000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-csr";
		qcom,usb-bam-support;
		qcom,hwctrl-set-support;
		qcom,set-byte-cntr-support;

		qcom,blk-size = <1>;
		};

		replicator_qdss: replicator@6046000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b909>;

		reg = <0x6046000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator-qdss";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		replicator0_out_tmc_etr: endpoint {
		remote-endpoint=
		<&tmc_etr_in_replicator0>;
		};
		};

		port@2 {
		reg = <0>;
		replicator0_in_tmc_etf: endpoint {
		slave-mode;
		remote-endpoint=
		<&tmc_etf_out_replicator0>;
		};
		};
		};
		};

		tmc_etr: tmc@6048000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6048000 0x1000>,
		<0x6064000 0x15000>;
		reg-names = "tmc-base", "bam-base";

		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x05e0 0>,
		<&apps_smmu 0x04a0 0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		arm,buffer-size = <0x400000>;

		coresight-name = "coresight-tmc-etr";
		coresight-ctis = <&cti0>;
		coresight-csr = <&csr>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";

		port {
		tmc_etr_in_replicator0: endpoint {
		slave-mode;
		remote-endpoint = <&replicator0_out_tmc_etr>;
		};
		};
		};

		tmc_etf: tmc@6047000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6047000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";
		coresight-ctis = <&cti0>;
		coresight-csr = <&csr>;
		arm,default-sink;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tmc_etf_out_replicator0: endpoint {
		remote-endpoint =
		<&replicator0_in_tmc_etf>;
		};
		};

		port@1 {
		reg = <0>;
		tmc_etf_in_funnel_merg: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_merg_out_tmc_etf>;
		};
		};
		};

		};

		funnel_merg: funnel@6045000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6045000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-merg";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_merg_out_tmc_etf: endpoint {
		remote-endpoint =
		<&tmc_etf_in_funnel_merg>;
		};
		};

		port@2 {
		reg = <1>;
		funnel_merg_in_funnel_in1: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_in1_out_funnel_merg>;
		};
		};
		};
		};

		funnel_in1: funnel@0x6042000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_in1_out_funnel_merg: endpoint {
		remote-endpoint =
		<&funnel_merg_in_funnel_in1>;
		};
		};

		port@3 {
		reg = <4>;
		funnel_in1_in_funnel_apss_merg: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_apss_merg_out_funnel_in1>;
		};
		};
		};
		};

		funnel_apss_merg: funnel@7810000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x7810000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss-merg";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_apss_merg_out_funnel_in1: endpoint {
		remote-endpoint =
		<&funnel_in1_in_funnel_apss_merg>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_apss_merg_in_funnel_apss: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_apss_out_funnel_apss_merg>;
		};
		};

		port@2 {
		reg = <2>;
		funnel_apss_merg_in_tpda_olc: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_olc_out_funnel_apss_merg>;
		};
		};

		port@3 {
		reg = <3>;
		funnel_apss_merg_in_tpda_llm_silver: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_llm_silver_out_funnel_apss_merg>;
		};
		};

		port@4 {
		reg = <4>;
		funnel_apss_merg_in_tpda_llm_gold: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_llm_gold_out_funnel_apss_merg>;
		};
		};

		port@5 {
		reg = <5>;
		funnel_apss_merg_in_tpda_apss: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_apss_out_funnel_apss_merg>;
		};
		};
		};
		};

		tpda_olc: tpda@7832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x7832000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-olc";

		qcom,tpda-atid = <69>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tpda_olc_out_funnel_apss_merg: endpoint {
		remote-endpoint =
		<&funnel_apss_merg_in_tpda_olc>;
		};
		};

		port@1 {
		reg = <0>;
		tpda_olc_in_tpdm_olc: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_olc_out_tpda_olc>;
		};
		};
		};
		};

		tpdm_olc: tpdm@7830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x7830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-olc";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
		tpdm_olc_out_tpda_olc: endpoint {
		remote-endpoint = <&tpda_olc_in_tpdm_olc>;
		};
		};
		};

		tpda_apss: tpda@7862000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x7862000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-apss";

		qcom,tpda-atid = <66>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tpda_apss_out_funnel_apss_merg: endpoint {
		remote-endpoint =
		<&funnel_apss_merg_in_tpda_apss>;
		};
		};

		port@1 {
		reg = <0>;
		tpda_apss_in_tpdm_apss: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_apss_out_tpda_apss>;
		};
		};
		};
		};

		tpdm_apss: tpdm@7860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x7860000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-apss";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		tpdm_apss_out_tpda_apss: endpoint {
		remote-endpoint = <&tpda_apss_in_tpdm_apss>;
		};
		};
		};

		tpda_llm_silver: tpda@78c0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x78c0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-silver";

		qcom,tpda-atid = <72>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tpda_llm_silver_out_funnel_apss_merg: endpoint {
		remote-endpoint =
		<&funnel_apss_merg_in_tpda_llm_silver>;
		};
		};

		port@1 {
		reg = <0>;
		tpda_llm_silver_in_tpdm_llm_silver: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_llm_silver_out_tpda_llm_silver>;
		};
		};
		};
		};

		tpdm_llm_silver: tpdm@78a0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x78a0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-silver";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		tpdm_llm_silver_out_tpda_llm_silver: endpoint {
		remote-endpoint =
		<&tpda_llm_silver_in_tpdm_llm_silver>;
		};
		};
		};

		tpda_llm_gold: tpda@78d0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x78d0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-gold";

		qcom,tpda-atid = <73>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		tpda_llm_gold_out_funnel_apss_merg: endpoint {
		remote-endpoint =
		<&funnel_apss_merg_in_tpda_llm_gold>;
		};
		};

		port@1 {
		reg = <0>;
		tpda_llm_gold_in_tpdm_llm_gold: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_llm_gold_out_tpda_llm_gold>;
		};
		};
		};
		};

		tpdm_llm_gold: tpdm@78b0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x78b0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-gold";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		tpdm_llm_gold_out_tpda_llm_gold: endpoint {
		remote-endpoint =
		<&tpda_llm_gold_in_tpdm_llm_gold>;
		};
		};
		};

		funnel_apss: funnel@7800000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x7800000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_apss_out_funnel_apss_merg: endpoint {
		remote-endpoint =
		<&funnel_apss_merg_in_funnel_apss>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_apss_in_etm0: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm0_out_funnel_apss>;
		};
		};

		port@2 {
		reg = <1>;
		funnel_apss_in_etm1: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm1_out_funnel_apss>;
		};
		};

		port@3 {
		reg = <2>;
		funnel_apss_in_etm2: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm2_out_funnel_apss>;
		};
		};

		port@4 {
		reg = <3>;
		funnel_apss_in_etm3: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm3_out_funnel_apss>;
		};
		};

		port@5 {
		reg = <4>;
		funnel_apss_in_etm4: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm4_out_funnel_apss>;
		};
		};

		port@6 {
		reg = <5>;
		funnel_apss_in_etm5: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm5_out_funnel_apss>;
		};
		};

		port@7 {
		reg = <6>;
		funnel_apss_in_etm6: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm6_out_funnel_apss>;
		};
		};

		port@8 {
		reg = <7>;
		funnel_apss_in_etm7: endpoint {
		slave-mode;
		remote-endpoint =
		<&etm7_out_funnel_apss>;
		};
		};
		};
		};

		etm0: etm@7040000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7040000 0x1000>;
		cpu = <&CPU0>;

		coresight-name = "coresight-etm0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		arm,coresight-loses-context-with-cpu;

		port {
		etm0_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm0>;
		};
		};
		};

		etm1: etm@7140000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7140000 0x1000>;
		cpu = <&CPU1>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm1_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm1>;
		};
		};
		};

		etm2: etm@7240000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7240000 0x1000>;
		cpu = <&CPU2>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm2_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm2>;
		};
		};
		};

		etm3: etm@7340000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7340000 0x1000>;
		cpu = <&CPU3>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm3_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm3>;
		};
		};
		};

		etm4: etm@7440000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7440000 0x1000>;
		cpu = <&CPU4>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm4";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm4_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm4>;
		};
		};
		};

		etm5: etm@7540000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7540000 0x1000>;
		cpu = <&CPU5>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm5";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm5_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm5>;
		};
		};
		};

		etm6: etm@7640000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7640000 0x1000>;
		cpu = <&CPU6>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm6_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm6>;
		};
		};
		};

		etm7: etm@7740000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7740000 0x1000>;
		cpu = <&CPU7>;

		qcom,tupwr-disable;
		coresight-name = "coresight-etm7";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
		etm7_out_funnel_apss: endpoint {
		remote-endpoint = <&funnel_apss_in_etm7>;
		};
		};
		};

		cti0_apss: cti@78e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x78e0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti1_apss: cti@78f0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x78f0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti2_apss: cti@7900000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7900000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti0: cti@6010000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti1: cti@6011000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti2: cti@6012000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti3: cti@6013000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti4: cti@6014000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti5: cti@6015000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti6: cti@6016000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti7: cti@6017000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti8: cti@6018000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti9: cti@6019000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti10: cti@601a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti11: cti@601b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti12: cti@601c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti13: cti@601d000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti14: cti@601e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti15: cti@601f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu0: cti@7020000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7020000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";
		cpu = <&CPU0>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu1: cti@7120000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7120000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu1";
		cpu = <&CPU1>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu2: cti@7220000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7220000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu2";
		cpu = <&CPU2>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu3: cti@7320000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7320000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu3";
		cpu = <&CPU3>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu4: cti@7420000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7420000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";
		cpu = <&CPU4>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu5: cti@7520000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7520000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";
		cpu = <&CPU5>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu6: cti@7620000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7620000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";
		cpu = <&CPU6>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};

		cti_cpu7: cti@7720000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7720000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";
		cpu = <&CPU7>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
		};
		};

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -2841,6 +2841,7 @@
		#include "sdmshrike-regulators.dtsi"
		#include "sdmshrike-ion.dtsi"
		#include "sdmshrike-bus.dtsi"
		#include "sdmshrike-coresight.dtsi"
		#include "msm-arm-smmu-sdmshrike.dtsi"
		#include "sdmshrike-usb.dtsi"
		#include "sdmshrike-qupv3.dtsi"