perf vendor events intel: Update IvyTown files to V20 (5b50758c) · Commits · e / devices / android_kernel_xiaomi_nabu

tools/perf/pmu-events/arch/x86/ivytown/cache.json

+456 −0

Original line number	Diff line number	Diff line
		@@ -800,5 +800,461 @@
		"SampleAfterValue": "100003",
		"BriefDescription": "Split locks in SQ",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c0091",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0091",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c0091",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c0091",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0090",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all prefetch data reads that hit the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c0090",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0090",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c0090",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c0090",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c03f7",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c03f7",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c03f7",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c03f7",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c03f7",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10008",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all writebacks from the core to the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0004",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all demand code reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0001",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all demand data reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c0001",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0001",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c0001",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c0001",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0002",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x803c8000",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x23ffc08000",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0040",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0010",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c0010",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0010",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c0010",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c0010",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0200",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x3f803c0080",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x4003c0080",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10003c0080",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x1003c0080",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x2003c0080",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10400",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xB7, 0xBB",
		"MSRValue": "0x10800",
		"Counter": "0,1,2,3",
		"UMask": "0x1",
		"Offcore": "1",
		"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"SampleAfterValue": "100003",
		"BriefDescription": "Counts non-temporal stores",
		"CounterHTOff": "0,1,2,3"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/x86/ivytown/memory.json

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