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Commit 5af35355 authored by Anant Goel's avatar Anant Goel
Browse files

ARM: dts: msm: Update buses configuration for SA8155 VM 



Provide updated bus entries for SE3 SPI and SE13 4-wire
UART. Remove miso sleep for SE3 SPI as it not required on
a VM. Add an active pinctrl set for 4-wire UART to support
active usecases.

Change-Id: Ib63aba5e8f1d73402051b1ca8952fa9e102acbe2
Signed-off-by: default avatarAnant Goel <anantg@codeaurora.org>
parent f4f64c90

arch/arm64/boot/dts/qcom/sa8155-vm-qupv3.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ 
			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se3_spi_active>;

		pinctrl-1 = <&qupv3_se3_spi_sleep &qupv3_se3_spi_miso_sleep>;

		pinctrl-1 = <&qupv3_se3_spi_sleep>;

		interrupts = <GIC_SPI 604 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;
@@ -372,11 +372,13 @@ 
		clocks = <&clock_virt GCC_QUPV3_WRAP2_S3_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,

				<&qupv3_se13_default_tx>;

		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		interrupts = <GIC_SPI 585 0>;

		qcom,wrapper-core = <&qupv3_2>;

		qcom,wakeup-byte = <0xFD>;