Merge "drivers: pinctrl: Add Reset Support for 2nd instance of UFS" (5974d512) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi

+46 −0

Original line number	Diff line number	Diff line
		@@ -67,6 +67,52 @@
		};
		};

		ufs0_dev_reset_assert: ufs0_dev_reset_assert {
		config {
		pins = "ufs0_reset";
		bias-pull-down; /* default: pull down */
		/*
		* UFS_RESET driver strengths are having
		* different values/steps compared to typical
		* GPIO drive strengths.
		*
		* Following table clarifies:
		*
		* HDRV value \| UFS_RESET \| Typical GPIO
		* (dec) \| (mA) \| (mA)
		* 0 \| 0.8 \| 2
		* 1 \| 1.55 \| 4
		* 2 \| 2.35 \| 6
		* 3 \| 3.1 \| 8
		* 4 \| 3.9 \| 10
		* 5 \| 4.65 \| 12
		* 6 \| 5.4 \| 14
		* 7 \| 6.15 \| 16
		*
		* POR value for UFS_RESET HDRV is 3 which means
		* 3.1mA and we want to use that. Hence just
		* specify 8mA to "drive-strength" binding and
		* that should result into writing 3 to HDRV
		* field.
		*/
		drive-strength = <8>; /* default: 3.1 mA */
		output-low; /* active low reset */
		};
		};

		ufs0_dev_reset_deassert: ufs0_dev_reset_deassert {
		config {
		pins = "ufs0_reset";
		bias-pull-down; /* default: pull down */
		/*
		* default: 3.1 mA
		* check comments under ufs_dev_reset_assert
		*/
		drive-strength = <8>;
		output-high; /* active low reset */
		};
		};

		aqt_intr {
		aqt_intr_default: aqt_intr_default {
		mux {

+4 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -321,6 +321,7 @@ static const struct pinctrl_pin_desc sdmshrike_pins[] = {
		PINCTRL_PIN(191, "SDC2_CMD"),
		PINCTRL_PIN(192, "SDC2_DATA"),
		PINCTRL_PIN(193, "UFS_RESET"),
		PINCTRL_PIN(194, "UFS0_RESET"),
		};

		#define DECLARE_MSM_GPIO_PINS(pin) \
		@@ -520,6 +521,7 @@ static const unsigned int sdc2_clk_pins[] = { 190 };
		static const unsigned int sdc2_cmd_pins[] = { 191 };
		static const unsigned int sdc2_data_pins[] = { 192 };
		static const unsigned int ufs_reset_pins[] = { 193 };
		static const unsigned int ufs0_reset_pins[] = { 194 };

		enum sdmshrike_functions {
		msm_mux_GRFC2,
		@@ -2244,6 +2246,7 @@ static const struct msm_pingroup sdmshrike_groups[] = {
		[191] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x9b2000, 11, 3),
		[192] = SDC_QDSD_PINGROUP(sdc2_data, 0x9b2000, 9, 0),
		[193] = UFS_RESET(ufs_reset, 0xdb6004),
		[194] = UFS_RESET(ufs0_reset, 0xdc7004),
		};

		static struct msm_dir_conn sdmshrike_dir_conn[] = {