Loading arch/alpha/kernel/irq_pyxis.c +10 −10 Original line number Diff line number Diff line Loading @@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask) } static inline void pyxis_enable_irq(unsigned int irq) pyxis_enable_irq(struct irq_data *d) { pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); } static void pyxis_disable_irq(unsigned int irq) pyxis_disable_irq(struct irq_data *d) { pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); } static void pyxis_mask_and_ack_irq(unsigned int irq) pyxis_mask_and_ack_irq(struct irq_data *d) { unsigned long bit = 1UL << (irq - 16); unsigned long bit = 1UL << (d->irq - 16); unsigned long mask = cached_irq_mask &= ~bit; /* Disable the interrupt. */ Loading @@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq) static struct irq_chip pyxis_irq_type = { .name = "PYXIS", .mask_ack = pyxis_mask_and_ack_irq, .mask = pyxis_disable_irq, .unmask = pyxis_enable_irq, .irq_mask_ack = pyxis_mask_and_ack_irq, .irq_mask = pyxis_disable_irq, .irq_unmask = pyxis_enable_irq, }; void Loading Loading @@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask) if ((ignore_mask >> i) & 1) continue; set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); irq_to_desc(i)->status |= IRQ_LEVEL; irq_set_status_flags(i, IRQ_LEVEL); } setup_irq(16+7, &isa_cascade_irqaction); Loading Loading
arch/alpha/kernel/irq_pyxis.c +10 −10 Original line number Diff line number Diff line Loading @@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask) } static inline void pyxis_enable_irq(unsigned int irq) pyxis_enable_irq(struct irq_data *d) { pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16)); pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); } static void pyxis_disable_irq(unsigned int irq) pyxis_disable_irq(struct irq_data *d) { pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16))); pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); } static void pyxis_mask_and_ack_irq(unsigned int irq) pyxis_mask_and_ack_irq(struct irq_data *d) { unsigned long bit = 1UL << (irq - 16); unsigned long bit = 1UL << (d->irq - 16); unsigned long mask = cached_irq_mask &= ~bit; /* Disable the interrupt. */ Loading @@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq) static struct irq_chip pyxis_irq_type = { .name = "PYXIS", .mask_ack = pyxis_mask_and_ack_irq, .mask = pyxis_disable_irq, .unmask = pyxis_enable_irq, .irq_mask_ack = pyxis_mask_and_ack_irq, .irq_mask = pyxis_disable_irq, .irq_unmask = pyxis_enable_irq, }; void Loading Loading @@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask) if ((ignore_mask >> i) & 1) continue; set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); irq_to_desc(i)->status |= IRQ_LEVEL; irq_set_status_flags(i, IRQ_LEVEL); } setup_irq(16+7, &isa_cascade_irqaction); Loading