Loading arch/arm64/boot/dts/qcom/sm6150-audio.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -145,3 +145,13 @@ elemental-addr = [ff ff ff fe 17 02]; }; }; &qupv3_se3_i2c { status = "ok"; fsa4480: fsa4480@43 { compatible = "qcom,fsa4480-i2c"; reg = <0x43>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; }; arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi +70 −0 Original line number Diff line number Diff line Loading @@ -632,6 +632,22 @@ }; }; fsa_usbc_ana_en_n@114 { fsa_usbc_ana_en: fsa_usbc_ana_en { mux { pins = "gpio114"; function = "gpio"; }; config { pins = "gpio114"; drive-strength = <2>; bias-disable; output-low; }; }; }; pmx_sde_te { sde_te_active: sde_te_active { mux { Loading Loading @@ -660,6 +676,60 @@ }; }; sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { mux { pins = "gpio104"; function = "gpio"; }; config { pins = "gpio104"; bias-disable; drive-strength = <16>; }; }; sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { mux { pins = "gpio104"; function = "gpio"; }; config { pins = "gpio104"; bias-pull-down; drive-strength = <2>; }; }; sde_dp_switch_active: sde_dp_switch_active { mux { pins = "gpio49"; function = "gpio"; }; config { pins = "gpio49"; bias-pull-up; /* pull up */ drive-strength = <2>; }; }; sde_dp_switch_suspend: sde_dp_switch_suspend { mux { pins = "gpio49"; function = "gpio"; }; config { pins = "gpio49"; bias-pull-down; drive-strength = <2>; }; }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { Loading arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +4 −7 Original line number Diff line number Diff line Loading @@ -155,17 +155,14 @@ label = "wb_display"; }; ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; }; &sde_dp { qcom,dp-usbpd-detection = <&pm6150_pdphy>; }; &mdss_mdp { connectors = <&sde_rscc &sde_wb &sde_dsi>; connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>; }; &dsi_sim_vid { Loading arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi +23 −10 Original line number Diff line number Diff line Loading @@ -39,17 +39,16 @@ }; }; mdss_dp_pll: qcom,mdss_dp_pll@c011000 { status = "disabled"; compatible = "qcom,mdss_dp_pll_7nm"; mdss_dp_pll: qcom,mdss_dp_pll@88e9000 { compatible = "qcom,mdss_dp_pll_14nm"; label = "MDSS DP PLL"; cell-index = <0>; #clock-cells = <1>; reg = <0x088ea000 0x200>, <0x088eaa00 0x200>, <0x088ea200 0x200>, <0x088ea600 0x200>, reg = <0x088e9c00 0x200>, <0x088e9000 0x200>, <0x088e9400 0x200>, <0x088e9800 0x200>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; Loading @@ -57,10 +56,24 @@ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; clock-names = "iface_clk", "ref_clk_src", "gcc_iface", "ref_clk", "pipe_clk"; "ref_clk"; clock-rate = <0>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; }; arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +55 −22 Original line number Diff line number Diff line Loading @@ -10,6 +10,8 @@ * GNU General Public License for more details. */ #include <dt-bindings/clock/mdss-14nm-pll-clk.h> &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; Loading Loading @@ -461,51 +463,82 @@ }; }; ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; }; sde_dp: qcom,dp_display@0{ status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; vdda-1p2-supply = <&pm6150l_l3>; vdda-0p9-supply = <&pm6150_l4>; reg = <0xae90000 0x0dc>, reg = <0xae90000 0x0f4>, <0xae90200 0x0c0>, <0xae90400 0x508>, <0xae90a00 0x094>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xae90400 0x5e0>, <0xae90a00 0x098>, <0x88e9000 0x17c>, <0x88e9400 0x10c>, <0x88e9800 0x10c>, <0xaf02000 0x1a0>, <0x780000 0x621c>, <0x88ea040 0x10>, <0x88e8000 0x20>, <0x0aee1000 0x034>, <0xae91000 0x094>; <0x88e9c30 0x10>, <0xaee1000 0x34>, <0x1fcb200 0x50>; /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1"; "hdcp_physical", "dp_tcsr"; interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; qcom,phy-version = <0x420>; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_AHB2PHY_WEST_CLK>, <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_ahb_clk", "core_usb_sec_ref_clk", "link_clk", "link_iface_clk", "strm0_pixel_clk", "crypto_clk", "pixel_clk_rcg", "pixel_parent"; qcom,phy-version = <0x200>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; qcom,aux-cfg2-settings = [28 24]; qcom,aux-cfg1-settings = [24 13 23 1d]; qcom,aux-cfg2-settings = [28 00]; qcom,aux-cfg3-settings = [2c 00]; qcom,aux-cfg4-settings = [30 0a]; qcom,aux-cfg5-settings = [34 26]; qcom,aux-cfg6-settings = [38 0a]; qcom,aux-cfg7-settings = [3c 03]; qcom,aux-cfg8-settings = [40 b7]; qcom,aux-cfg8-settings = [40 bb]; qcom,aux-cfg9-settings = [44 03]; qcom,max-pclk-frequency-khz = <675000>; qcom,logical2physical-lane-map = [03 02 00 01]; qcom,mst-enable; qcom,max-pclk-frequency-khz = <200000>; qcom,ext-disp = <&ext_disp>; qcom,dp-aux-switch = <&fsa4480>; qcom,mux-sel-gpio = <&tlmm 49 0>; qcom,usbplug-cc-gpio = <&tlmm 104 0>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>; pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>; qcom,ctrl-supply-entries { #address-cells = <1>; Loading @@ -514,8 +547,8 @@ qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-min-voltage = <1232000>; qcom,supply-max-voltage = <1232000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; Loading @@ -529,7 +562,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; qcom,supply-max-voltage = <975000>; qcom,supply-enable-load = <36000>; qcom,supply-disable-load = <0>; }; Loading Loading
arch/arm64/boot/dts/qcom/sm6150-audio.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -145,3 +145,13 @@ elemental-addr = [ff ff ff fe 17 02]; }; }; &qupv3_se3_i2c { status = "ok"; fsa4480: fsa4480@43 { compatible = "qcom,fsa4480-i2c"; reg = <0x43>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; };
arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi +70 −0 Original line number Diff line number Diff line Loading @@ -632,6 +632,22 @@ }; }; fsa_usbc_ana_en_n@114 { fsa_usbc_ana_en: fsa_usbc_ana_en { mux { pins = "gpio114"; function = "gpio"; }; config { pins = "gpio114"; drive-strength = <2>; bias-disable; output-low; }; }; }; pmx_sde_te { sde_te_active: sde_te_active { mux { Loading Loading @@ -660,6 +676,60 @@ }; }; sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { mux { pins = "gpio104"; function = "gpio"; }; config { pins = "gpio104"; bias-disable; drive-strength = <16>; }; }; sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { mux { pins = "gpio104"; function = "gpio"; }; config { pins = "gpio104"; bias-pull-down; drive-strength = <2>; }; }; sde_dp_switch_active: sde_dp_switch_active { mux { pins = "gpio49"; function = "gpio"; }; config { pins = "gpio49"; bias-pull-up; /* pull up */ drive-strength = <2>; }; }; sde_dp_switch_suspend: sde_dp_switch_suspend { mux { pins = "gpio49"; function = "gpio"; }; config { pins = "gpio49"; bias-pull-down; drive-strength = <2>; }; }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { Loading
arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +4 −7 Original line number Diff line number Diff line Loading @@ -155,17 +155,14 @@ label = "wb_display"; }; ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; }; &sde_dp { qcom,dp-usbpd-detection = <&pm6150_pdphy>; }; &mdss_mdp { connectors = <&sde_rscc &sde_wb &sde_dsi>; connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>; }; &dsi_sim_vid { Loading
arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi +23 −10 Original line number Diff line number Diff line Loading @@ -39,17 +39,16 @@ }; }; mdss_dp_pll: qcom,mdss_dp_pll@c011000 { status = "disabled"; compatible = "qcom,mdss_dp_pll_7nm"; mdss_dp_pll: qcom,mdss_dp_pll@88e9000 { compatible = "qcom,mdss_dp_pll_14nm"; label = "MDSS DP PLL"; cell-index = <0>; #clock-cells = <1>; reg = <0x088ea000 0x200>, <0x088eaa00 0x200>, <0x088ea200 0x200>, <0x088ea600 0x200>, reg = <0x088e9c00 0x200>, <0x088e9000 0x200>, <0x088e9400 0x200>, <0x088e9800 0x200>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; Loading @@ -57,10 +56,24 @@ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; clock-names = "iface_clk", "ref_clk_src", "gcc_iface", "ref_clk", "pipe_clk"; "ref_clk"; clock-rate = <0>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; };
arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +55 −22 Original line number Diff line number Diff line Loading @@ -10,6 +10,8 @@ * GNU General Public License for more details. */ #include <dt-bindings/clock/mdss-14nm-pll-clk.h> &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; Loading Loading @@ -461,51 +463,82 @@ }; }; ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; }; sde_dp: qcom,dp_display@0{ status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; vdda-1p2-supply = <&pm6150l_l3>; vdda-0p9-supply = <&pm6150_l4>; reg = <0xae90000 0x0dc>, reg = <0xae90000 0x0f4>, <0xae90200 0x0c0>, <0xae90400 0x508>, <0xae90a00 0x094>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xae90400 0x5e0>, <0xae90a00 0x098>, <0x88e9000 0x17c>, <0x88e9400 0x10c>, <0x88e9800 0x10c>, <0xaf02000 0x1a0>, <0x780000 0x621c>, <0x88ea040 0x10>, <0x88e8000 0x20>, <0x0aee1000 0x034>, <0xae91000 0x094>; <0x88e9c30 0x10>, <0xaee1000 0x34>, <0x1fcb200 0x50>; /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1"; "hdcp_physical", "dp_tcsr"; interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; qcom,phy-version = <0x420>; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_AHB2PHY_WEST_CLK>, <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_ahb_clk", "core_usb_sec_ref_clk", "link_clk", "link_iface_clk", "strm0_pixel_clk", "crypto_clk", "pixel_clk_rcg", "pixel_parent"; qcom,phy-version = <0x200>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; qcom,aux-cfg2-settings = [28 24]; qcom,aux-cfg1-settings = [24 13 23 1d]; qcom,aux-cfg2-settings = [28 00]; qcom,aux-cfg3-settings = [2c 00]; qcom,aux-cfg4-settings = [30 0a]; qcom,aux-cfg5-settings = [34 26]; qcom,aux-cfg6-settings = [38 0a]; qcom,aux-cfg7-settings = [3c 03]; qcom,aux-cfg8-settings = [40 b7]; qcom,aux-cfg8-settings = [40 bb]; qcom,aux-cfg9-settings = [44 03]; qcom,max-pclk-frequency-khz = <675000>; qcom,logical2physical-lane-map = [03 02 00 01]; qcom,mst-enable; qcom,max-pclk-frequency-khz = <200000>; qcom,ext-disp = <&ext_disp>; qcom,dp-aux-switch = <&fsa4480>; qcom,mux-sel-gpio = <&tlmm 49 0>; qcom,usbplug-cc-gpio = <&tlmm 104 0>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>; pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>; qcom,ctrl-supply-entries { #address-cells = <1>; Loading @@ -514,8 +547,8 @@ qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-min-voltage = <1232000>; qcom,supply-max-voltage = <1232000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; Loading @@ -529,7 +562,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <880000>; qcom,supply-max-voltage = <975000>; qcom,supply-enable-load = <36000>; qcom,supply-disable-load = <0>; }; Loading