From 563fff6498fc84eb28b5134c66409b89a1460395 Mon Sep 17 00:00:00 2001 From: Dilip Gudlur Date: Mon, 22 Oct 2018 21:35:46 -0700 Subject: [PATCH 0001/1286] defconfig: sa8155: Enable support for ACM devices Enable ACM device support for USB bus. Change-Id: I6c5badcf76ef1eb7a674446b383c636ff400543d Signed-off-by: Dilip Gudlur --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 1 + arch/arm64/configs/vendor/sa8155_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index 40413a4c7c39..9e59f723f353 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -407,6 +407,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index ddc6887dfbbc..e3cb4de27b6d 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -425,6 +425,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y -- GitLab From 75d1a2077ac97e94a74e671a352cbb42a0b1ca4a Mon Sep 17 00:00:00 2001 From: Kim Zhang Date: Wed, 14 Nov 2018 12:12:01 +0800 Subject: [PATCH 0002/1286] defconfig: Enable qvr external viewer Enable qvr external viewer: Add uvc support Add hid-qvr support CRs-Fixed: 2365637 Change-Id: I34c44c2ca2951a07124c0219b8cc351121042f53 Signed-off-by: Kim Zhang --- arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 3 +++ arch/arm64/configs/vendor/sdmsteppe_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index d7055b6c0cdf..169baddcd81c 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -388,6 +388,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SPECTRA_CAMERA=y CONFIG_MSM_VIDC_V4L2=y @@ -421,6 +423,7 @@ CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_PLANTRONICS=y +CONFIG_HID_QVR=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_XHCI_HCD=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 0fe4f21d3a38..7751ed13f8a3 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -401,6 +401,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SPECTRA_CAMERA=y CONFIG_MSM_VIDC_V4L2=y @@ -436,6 +438,7 @@ CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_PLANTRONICS=y +CONFIG_HID_QVR=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_XHCI_HCD=y -- GitLab From 426477d9f68b56ab71f52a5ce2dd6da0699d89c3 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 1 Nov 2018 13:14:30 +0000 Subject: [PATCH 0003/1286] cifs: don't dereference smb_file_target before null check [ Upstream commit 8c6c9bed8773375b1d54ccca2911ec892c59db5d ] There is a null check on dst_file->private data which suggests it can be potentially null. However, before this check, pointer smb_file_target is derived from dst_file->private and dereferenced in the call to tlink_tcon, hence there is a potential null pointer deference. Fix this by assigning smb_file_target and target_tcon after the null pointer sanity checks. Detected by CoverityScan, CID#1475302 ("Dereference before null check") Fixes: 04b38d601239 ("vfs: pull btrfs clone API to vfs layer") Signed-off-by: Colin Ian King Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/cifs/cifsfs.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 44a7b2dea688..c5fd5abf7206 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -933,8 +933,8 @@ static int cifs_clone_file_range(struct file *src_file, loff_t off, struct inode *src_inode = file_inode(src_file); struct inode *target_inode = file_inode(dst_file); struct cifsFileInfo *smb_file_src = src_file->private_data; - struct cifsFileInfo *smb_file_target = dst_file->private_data; - struct cifs_tcon *target_tcon = tlink_tcon(smb_file_target->tlink); + struct cifsFileInfo *smb_file_target; + struct cifs_tcon *target_tcon; unsigned int xid; int rc; @@ -948,6 +948,9 @@ static int cifs_clone_file_range(struct file *src_file, loff_t off, goto out; } + smb_file_target = dst_file->private_data; + target_tcon = tlink_tcon(smb_file_target->tlink); + /* * Note: cifs case is easier than btrfs since server responsible for * checks for proper open modes and file type and if it wants -- GitLab From bc32d90e4d45b4f544527efdce2ea57d83f77542 Mon Sep 17 00:00:00 2001 From: Ronnie Sahlberg Date: Thu, 25 Oct 2018 15:43:36 +1000 Subject: [PATCH 0004/1286] cifs: fix return value for cifs_listxattr [ Upstream commit 0c5d6cb6643f48ad3775322f3ebab6c7eb67484e ] If the application buffer was too small to fit all the names we would still count the number of bytes and return this for listxattr. This would then trigger a BUG in usercopy.c Fix the computation of the size so that we return -ERANGE correctly when the buffer is too small. This fixes the kernel BUG for xfstest generic/377 Signed-off-by: Ronnie Sahlberg Signed-off-by: Steve French Reviewed-by: Aurelien Aptel Signed-off-by: Sasha Levin --- fs/cifs/smb2ops.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index 4e5b05263e4a..3372eedaa94d 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -441,6 +441,7 @@ move_smb2_ea_to_cifs(char *dst, size_t dst_size, int rc = 0; unsigned int ea_name_len = ea_name ? strlen(ea_name) : 0; char *name, *value; + size_t buf_size = dst_size; size_t name_len, value_len, user_name_len; while (src_size > 0) { @@ -476,9 +477,10 @@ move_smb2_ea_to_cifs(char *dst, size_t dst_size, /* 'user.' plus a terminating null */ user_name_len = 5 + 1 + name_len; - rc += user_name_len; - - if (dst_size >= user_name_len) { + if (buf_size == 0) { + /* skip copy - calc size only */ + rc += user_name_len; + } else if (dst_size >= user_name_len) { dst_size -= user_name_len; memcpy(dst, "user.", 5); dst += 5; @@ -486,8 +488,7 @@ move_smb2_ea_to_cifs(char *dst, size_t dst_size, dst += name_len; *dst = 0; ++dst; - } else if (dst_size == 0) { - /* skip copy - calc size only */ + rc += user_name_len; } else { /* stop before overrun buffer */ rc = -ERANGE; -- GitLab From aa9571b2015d270a3e73a66d3a5b27c37836fd6a Mon Sep 17 00:00:00 2001 From: Anders Roxell Date: Tue, 30 Oct 2018 12:38:50 +0100 Subject: [PATCH 0005/1286] arm64: kprobe: make page to RO mode when allocate it [ Upstream commit 966866892cf89d606544bca22d584ba2ef9ec208 ] Commit 1404d6f13e47 ("arm64: dump: Add checking for writable and exectuable pages") has successfully identified code that leaves a page with W+X permissions. [ 3.245140] arm64/mm: Found insecure W+X mapping at address (____ptrval____)/0xffff000000d90000 [ 3.245771] WARNING: CPU: 0 PID: 1 at ../arch/arm64/mm/dump.c:232 note_page+0x410/0x420 [ 3.246141] Modules linked in: [ 3.246653] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.0-rc5-next-20180928-00001-ge70ae259b853-dirty #62 [ 3.247008] Hardware name: linux,dummy-virt (DT) [ 3.247347] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 3.247623] pc : note_page+0x410/0x420 [ 3.247898] lr : note_page+0x410/0x420 [ 3.248071] sp : ffff00000804bcd0 [ 3.248254] x29: ffff00000804bcd0 x28: ffff000009274000 [ 3.248578] x27: ffff00000921a000 x26: ffff80007dfff000 [ 3.248845] x25: ffff0000093f5000 x24: ffff000009526f6a [ 3.249109] x23: 0000000000000004 x22: ffff000000d91000 [ 3.249396] x21: ffff000000d90000 x20: 0000000000000000 [ 3.249661] x19: ffff00000804bde8 x18: 0000000000000400 [ 3.249924] x17: 0000000000000000 x16: 0000000000000000 [ 3.250271] x15: ffffffffffffffff x14: 295f5f5f5f6c6176 [ 3.250594] x13: 7274705f5f5f5f28 x12: 2073736572646461 [ 3.250941] x11: 20746120676e6970 x10: 70616d20582b5720 [ 3.251252] x9 : 6572756365736e69 x8 : 3039643030303030 [ 3.251519] x7 : 306666666678302f x6 : ffff0000095467b2 [ 3.251802] x5 : 0000000000000000 x4 : 0000000000000000 [ 3.252060] x3 : 0000000000000000 x2 : ffffffffffffffff [ 3.252323] x1 : 4d151327adc50b00 x0 : 0000000000000000 [ 3.252664] Call trace: [ 3.252953] note_page+0x410/0x420 [ 3.253186] walk_pgd+0x12c/0x238 [ 3.253417] ptdump_check_wx+0x68/0xf8 [ 3.253637] mark_rodata_ro+0x68/0x98 [ 3.253847] kernel_init+0x38/0x160 [ 3.254103] ret_from_fork+0x10/0x18 kprobes allocates a writable executable page with module_alloc() in order to store executable code. Reworked to that when allocate a page it sets mode RO. Inspired by commit 63fef14fc98a ("kprobes/x86: Make insn buffer always ROX and use text_poke()"). Suggested-by: Arnd Bergmann Suggested-by: Ard Biesheuvel Acked-by: Will Deacon Acked-by: Masami Hiramatsu Reviewed-by: Laura Abbott Signed-off-by: Anders Roxell [catalin.marinas@arm.com: removed unnecessary casts] Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/kernel/probes/kprobes.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c index 22a5921562c7..0417c929d21a 100644 --- a/arch/arm64/kernel/probes/kprobes.c +++ b/arch/arm64/kernel/probes/kprobes.c @@ -23,7 +23,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -42,10 +44,21 @@ DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); static void __kprobes post_kprobe_handler(struct kprobe_ctlblk *, struct pt_regs *); +static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode) +{ + void *addrs[1]; + u32 insns[1]; + + addrs[0] = addr; + insns[0] = opcode; + + return aarch64_insn_patch_text(addrs, insns, 1); +} + static void __kprobes arch_prepare_ss_slot(struct kprobe *p) { /* prepare insn slot */ - p->ainsn.api.insn[0] = cpu_to_le32(p->opcode); + patch_text(p->ainsn.api.insn, p->opcode); flush_icache_range((uintptr_t) (p->ainsn.api.insn), (uintptr_t) (p->ainsn.api.insn) + @@ -118,15 +131,15 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) return 0; } -static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode) +void *alloc_insn_page(void) { - void *addrs[1]; - u32 insns[1]; + void *page; - addrs[0] = (void *)addr; - insns[0] = (u32)opcode; + page = vmalloc_exec(PAGE_SIZE); + if (page) + set_memory_ro((unsigned long)page, 1); - return aarch64_insn_patch_text(addrs, insns, 1); + return page; } /* arm kprobe: install breakpoint in text */ -- GitLab From f54c21ee5dcede4164e8924a525d801f2fe855fd Mon Sep 17 00:00:00 2001 From: Radoslaw Tyl Date: Mon, 22 Oct 2018 08:44:31 +0200 Subject: [PATCH 0006/1286] ixgbe: fix MAC anti-spoofing filter after VFLR [ Upstream commit 6702185c1ffec3421181b5e24491e3fac920cb61 ] This change resolves a driver bug where the driver is logging a message that says "Spoofed packets detected". This can occur on the PF (host) when a VF has VLAN+MACVLAN enabled and is re-started with a different MAC address. MAC and VLAN anti-spoofing filters are to be enabled together. Signed-off-by: Radoslaw Tyl Tested-by: Andrew Bowers Acked-by: Piotr Skajewski Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 112d24c6c9ce..4904a63b83ef 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -760,8 +760,10 @@ static inline void ixgbe_vf_reset_event(struct ixgbe_adapter *adapter, u32 vf) ixgbe_set_vmvir(adapter, vfinfo->pf_vlan, adapter->default_up, vf); - if (vfinfo->spoofchk_enabled) + if (vfinfo->spoofchk_enabled) { hw->mac.ops.set_vlan_anti_spoofing(hw, true, vf); + hw->mac.ops.set_mac_anti_spoofing(hw, true, vf); + } } /* reset multicast table array for vf */ -- GitLab From 195169e26eaa18da05f0b63cc4b7dbfa50d70752 Mon Sep 17 00:00:00 2001 From: Jann Horn Date: Tue, 30 Oct 2018 15:06:38 -0700 Subject: [PATCH 0007/1286] reiserfs: propagate errors from fill_with_dentries() properly [ Upstream commit b10298d56c9623f9b173f19959732d3184b35f4f ] fill_with_dentries() failed to propagate errors up to reiserfs_for_each_xattr() properly. Plumb them through. Note that reiserfs_for_each_xattr() is only used by reiserfs_delete_xattrs() and reiserfs_chown_xattrs(). The result of reiserfs_delete_xattrs() is discarded anyway, the only difference there is whether a warning is printed to dmesg. The result of reiserfs_chown_xattrs() does matter because it can block chowning of the file to which the xattrs belong; but either way, the resulting state can have misaligned ownership, so my patch doesn't improve things greatly. Credit for making me look at this code goes to Al Viro, who pointed out that the ->actor calling convention is suboptimal and should be changed. Link: http://lkml.kernel.org/r/20180802163335.83312-1-jannh@google.com Signed-off-by: Jann Horn Reviewed-by: Andrew Morton Cc: Jeff Mahoney Cc: Eric Biggers Cc: Al Viro Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/reiserfs/xattr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c index 505f87a8c724..83423192588c 100644 --- a/fs/reiserfs/xattr.c +++ b/fs/reiserfs/xattr.c @@ -185,6 +185,7 @@ struct reiserfs_dentry_buf { struct dir_context ctx; struct dentry *xadir; int count; + int err; struct dentry *dentries[8]; }; @@ -207,6 +208,7 @@ fill_with_dentries(struct dir_context *ctx, const char *name, int namelen, dentry = lookup_one_len(name, dbuf->xadir, namelen); if (IS_ERR(dentry)) { + dbuf->err = PTR_ERR(dentry); return PTR_ERR(dentry); } else if (d_really_is_negative(dentry)) { /* A directory entry exists, but no file? */ @@ -215,6 +217,7 @@ fill_with_dentries(struct dir_context *ctx, const char *name, int namelen, "not found for file %pd.\n", dentry, dbuf->xadir); dput(dentry); + dbuf->err = -EIO; return -EIO; } @@ -262,6 +265,10 @@ static int reiserfs_for_each_xattr(struct inode *inode, err = reiserfs_readdir_inode(d_inode(dir), &buf.ctx); if (err) break; + if (buf.err) { + err = buf.err; + break; + } if (!buf.count) break; for (i = 0; !err && i < buf.count && buf.dentries[i]; i++) { -- GitLab From dc50dd3ac68b092c0bcb05cbd8b604e8d517185a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernesto=20A=2E=20Fern=C3=A1ndez?= Date: Tue, 30 Oct 2018 15:06:07 -0700 Subject: [PATCH 0008/1286] hfs: prevent btree data loss on root split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d057c036672f33d43a5f7344acbb08cf3a8a0c09 ] This bug is triggered whenever hfs_brec_update_parent() needs to split the root node. The height of the btree is not increased, which leaves the new node orphaned and its records lost. It is not possible for this to happen on a valid hfs filesystem because the index nodes have fixed length keys. For reasons I ignore, the hfs module does have support for a number of hfsplus features. A corrupt btree header may report variable length keys and trigger this bug, so it's better to fix it. Link: http://lkml.kernel.org/r/9750b1415685c4adca10766895f6d5ef12babdb0.1535682463.git.ernesto.mnd.fernandez@gmail.com Signed-off-by: Ernesto A. Fernández Cc: Christoph Hellwig Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/hfs/brec.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/hfs/brec.c b/fs/hfs/brec.c index 9a8772465a90..da25c49203cc 100644 --- a/fs/hfs/brec.c +++ b/fs/hfs/brec.c @@ -425,6 +425,10 @@ static int hfs_brec_update_parent(struct hfs_find_data *fd) if (new_node) { __be32 cnid; + if (!new_node->parent) { + hfs_btree_inc_height(tree); + new_node->parent = tree->root; + } fd->bnode = hfs_bnode_find(tree, new_node->parent); /* create index key and entry */ hfs_bnode_read_key(new_node, fd->search_key, 14); -- GitLab From f2e71fed903fa6441188f4ac8b0df6528711cae3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ernesto=20A=2E=20Fern=C3=A1ndez?= Date: Tue, 30 Oct 2018 15:06:00 -0700 Subject: [PATCH 0009/1286] hfsplus: prevent btree data loss on root split MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 0a3021d4f5295aa073c7bf5c5e4de60a2e292578 ] Creating, renaming or deleting a file may cause catalog corruption and data loss. This bug is randomly triggered by xfstests generic/027, but here is a faster reproducer: truncate -s 50M fs.iso mkfs.hfsplus fs.iso mount fs.iso /mnt i=100 while [ $i -le 150 ]; do touch /mnt/$i &>/dev/null ((++i)) done i=100 while [ $i -le 150 ]; do mv /mnt/$i /mnt/$(perl -e "print $i x82") &>/dev/null ((++i)) done umount /mnt fsck.hfsplus -n fs.iso The bug is triggered whenever hfs_brec_update_parent() needs to split the root node. The height of the btree is not increased, which leaves the new node orphaned and its records lost. Link: http://lkml.kernel.org/r/26d882184fc43043a810114258f45277752186c7.1535682461.git.ernesto.mnd.fernandez@gmail.com Signed-off-by: Ernesto A. Fernández Cc: Christoph Hellwig Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/hfsplus/brec.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/hfsplus/brec.c b/fs/hfsplus/brec.c index 808f4d8c859c..d3f36982f685 100644 --- a/fs/hfsplus/brec.c +++ b/fs/hfsplus/brec.c @@ -428,6 +428,10 @@ static int hfs_brec_update_parent(struct hfs_find_data *fd) if (new_node) { __be32 cnid; + if (!new_node->parent) { + hfs_btree_inc_height(tree); + new_node->parent = tree->root; + } fd->bnode = hfs_bnode_find(tree, new_node->parent); /* create index key and entry */ hfs_bnode_read_key(new_node, fd->search_key, 14); -- GitLab From a134b05a43ae2327036e860fb10c74389b5bd971 Mon Sep 17 00:00:00 2001 From: Richard Weinberger Date: Fri, 15 Jun 2018 16:42:56 +0200 Subject: [PATCH 0010/1286] um: Give start_idle_thread() a return code [ Upstream commit 7ff1e34bbdc15acab823b1ee4240e94623d50ee8 ] Fixes: arch/um/os-Linux/skas/process.c:613:1: warning: control reaches end of non-void function [-Wreturn-type] longjmp() never returns but gcc still warns that the end of the function can be reached. Add a return code and debug aid to detect this impossible case. Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- arch/um/os-Linux/skas/process.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/um/os-Linux/skas/process.c b/arch/um/os-Linux/skas/process.c index c94c3bd70ccd..df4a985716eb 100644 --- a/arch/um/os-Linux/skas/process.c +++ b/arch/um/os-Linux/skas/process.c @@ -610,6 +610,11 @@ int start_idle_thread(void *stack, jmp_buf *switch_buf) fatal_sigsegv(); } longjmp(*switch_buf, 1); + + /* unreachable */ + printk(UM_KERN_ERR "impossible long jump!"); + fatal_sigsegv(); + return 0; } void initial_thread_cb_skas(void (*proc)(void *), void *arg) -- GitLab From a3e69ef80467644e7970fdc39452f2247994fc3f Mon Sep 17 00:00:00 2001 From: "Lee, Shawn C" Date: Sun, 28 Oct 2018 22:49:33 -0700 Subject: [PATCH 0011/1286] drm/edid: Add 6 bpc quirk for BOE panel. [ Upstream commit 922dceff8dc1fb4dafc9af78139ba65671408103 ] BOE panel (ID: 0x0771) that reports "DFP 1.x compliant TMDS". But it's 6bpc panel only instead of 8 bpc. Add panel ID to edid quirk list and set 6 bpc as default to work around this issue. Cc: Jani Nikula Cc: Maarten Lankhorst Cc: Gustavo Padovan Cc: Cooper Chiou Signed-off-by: Lee, Shawn C > Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/1540792173-7288-1-git-send-email-shawn.c.lee@intel.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/drm_edid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index d1191ebed072..ed01e3aae0e8 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -120,6 +120,9 @@ static const struct edid_quirk { /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, + /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ + { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, + /* Belinea 10 15 55 */ { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, -- GitLab From b36c78af0c4d210aa99b705c4d777adf6a44d67f Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Sat, 6 Oct 2018 12:21:13 +0530 Subject: [PATCH 0012/1286] platform/x86: intel_telemetry: report debugfs failure [ Upstream commit 8d98b1ef368feeb7720b8b9b6f3bd93f2ad892bc ] On some Goldmont based systems such as ASRock J3455M the BIOS may not enable the IPC1 device that provides access to the PMC and PUNIT. In such scenarios, the IOSS and PSS resources from the platform device can not be obtained and result in a invalid telemetry_plt_config which is an internal data structure that holds platform config and is maintained by the telemetry platform driver. This is also applicable to the platforms where the BIOS supports IPC1 device under debug configurations but IPC1 is disabled by user or the policy. This change allows user to know the reason for not seeing entries under /sys/kernel/debug/telemetry/* when there is no apparent failure at boot. Cc: Matt Turner Cc: Len Brown Cc: Souvik Kumar Chakravarty Cc: Kuppuswamy Sathyanarayanan Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=198779 Acked-by: Matt Turner Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Andy Shevchenko Signed-off-by: Sasha Levin --- drivers/platform/x86/intel_telemetry_debugfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/intel_telemetry_debugfs.c b/drivers/platform/x86/intel_telemetry_debugfs.c index d4fc42b4cbeb..401bdc7a9d94 100644 --- a/drivers/platform/x86/intel_telemetry_debugfs.c +++ b/drivers/platform/x86/intel_telemetry_debugfs.c @@ -968,12 +968,16 @@ static int __init telemetry_debugfs_init(void) debugfs_conf = (struct telemetry_debugfs_conf *)id->driver_data; err = telemetry_pltconfig_valid(); - if (err < 0) + if (err < 0) { + pr_info("Invalid pltconfig, ensure IPC1 device is enabled in BIOS\n"); return -ENODEV; + } err = telemetry_debugfs_check_evts(); - if (err < 0) + if (err < 0) { + pr_info("telemetry_debugfs_check_evts failed\n"); return -EINVAL; + } register_pm_notifier(&pm_notifier); -- GitLab From 0333b8fc793bdb01b454a9c2ad3bf2c63a8cb530 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Thu, 18 Oct 2018 14:54:11 -0500 Subject: [PATCH 0013/1286] clk: fixed-rate: fix of_node_get-put imbalance [ Upstream commit 52091c256bdcad0d01e2852a63f19cd2cce6af96 ] When the fixed rate clock is created by devicetree, of_clk_add_provider is called. Add a call to of_clk_del_provider in the remove function to balance it out. Signed-off-by: Alan Tull Fixes: 435779fe1336 ("clk: fixed-rate: Convert into a module platform driver") Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-fixed-rate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index b5c46b3f8764..6d6475c32ee5 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -200,6 +200,7 @@ static int of_fixed_clk_remove(struct platform_device *pdev) { struct clk *clk = platform_get_drvdata(pdev); + of_clk_del_provider(pdev->dev.of_node); clk_unregister_fixed_rate(clk); return 0; -- GitLab From bff410ea7ec2541a38d353a9e012f7f4622e17c1 Mon Sep 17 00:00:00 2001 From: David Miller Date: Wed, 17 Oct 2018 12:08:59 -0700 Subject: [PATCH 0014/1286] perf symbols: Set PLT entry/header sizes properly on Sparc [ Upstream commit d6afa561e1471ccfdaf7191230c0c59a37e45a5b ] Using the sh_entsize for both values isn't correct. It happens to be correct on x86... For both 32-bit and 64-bit sparc, there are four PLT entries in the PLT section. Signed-off-by: David S. Miller Cc: Alexander Shishkin Cc: Alexis Berlemont Cc: David Tolnay Cc: Hanjun Guo Cc: Hemant Kumar Cc: Li Bin Cc: Masami Hiramatsu Cc: Milian Wolff Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Wang Nan Cc: zhangmengting@huawei.com Fixes: b2f7605076d6 ("perf symbols: Fix plt entry calculation for ARM and AARCH64") Link: http://lkml.kernel.org/r/20181017.120859.2268840244308635255.davem@davemloft.net Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/symbol-elf.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 2de770511e70..8ad4296de98b 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -338,7 +338,17 @@ int dso__synthesize_plt_symbols(struct dso *dso, struct symsrc *ss, struct map * plt_entry_size = 16; break; - default: /* FIXME: s390/alpha/mips/parisc/poperpc/sh/sparc/xtensa need to be checked */ + case EM_SPARC: + plt_header_size = 48; + plt_entry_size = 12; + break; + + case EM_SPARCV9: + plt_header_size = 128; + plt_entry_size = 32; + break; + + default: /* FIXME: s390/alpha/mips/parisc/poperpc/sh/xtensa need to be checked */ plt_header_size = shdr_plt.sh_entsize; plt_entry_size = shdr_plt.sh_entsize; break; -- GitLab From a088fde602b8dc3183fb40fa2e706455243bd900 Mon Sep 17 00:00:00 2001 From: Chengguang Xu Date: Wed, 13 Jun 2018 12:05:13 +0800 Subject: [PATCH 0015/1286] fs/exofs: fix potential memory leak in mount option parsing [ Upstream commit 515f1867addaba49c1c6ac73abfaffbc192c1db4 ] There are some cases can cause memory leak when parsing option 'osdname'. Signed-off-by: Chengguang Xu Signed-off-by: Al Viro Signed-off-by: Sasha Levin --- fs/exofs/super.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/exofs/super.c b/fs/exofs/super.c index 819624cfc8da..c9ec652e2fcd 100644 --- a/fs/exofs/super.c +++ b/fs/exofs/super.c @@ -100,6 +100,7 @@ static int parse_options(char *options, struct exofs_mountopt *opts) token = match_token(p, tokens, args); switch (token) { case Opt_name: + kfree(opts->dev_name); opts->dev_name = match_strdup(&args[0]); if (unlikely(!opts->dev_name)) { EXOFS_ERR("Error allocating dev_name"); @@ -863,8 +864,10 @@ static struct dentry *exofs_mount(struct file_system_type *type, int ret; ret = parse_options(data, &opts); - if (ret) + if (ret) { + kfree(opts.dev_name); return ERR_PTR(ret); + } if (!opts.dev_name) opts.dev_name = dev_name; -- GitLab From e2a11843feaac0a4c7f6047ab433a059f0122603 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 24 Sep 2018 13:01:20 +0200 Subject: [PATCH 0016/1286] clk: samsung: exynos5420: Enable PERIS clocks for suspend [ Upstream commit b33228029d842269e17bba591609e83ed422005d ] Ensure that clocks for core SoC modules (including TZPC0..9 modules) are enabled for suspend/resume cycle. This fixes suspend/resume support on Exynos5422-based Odroid XU3/XU4 boards. Suggested-by: Joonyoung Shim Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki Signed-off-by: Sasha Levin --- drivers/clk/samsung/clk-exynos5420.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 25601967d1cd..500a55415e90 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -280,6 +280,7 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, + { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, }; static int exynos5420_clk_suspend(void) -- GitLab From d0a636aa44f9e7cbac2a90e191bc0ad840b10b9e Mon Sep 17 00:00:00 2001 From: Zubin Mithra Date: Thu, 27 Sep 2018 14:49:17 -0700 Subject: [PATCH 0017/1286] apparmor: Fix uninitialized value in aa_split_fqname [ Upstream commit 250f2da49cb8e582215a65c03f50e8ddf5cd119c ] Syzkaller reported a OOB-read with the stacktrace below. This occurs inside __aa_lookupn_ns as `n` is not initialized. `n` is obtained from aa_splitn_fqname. In cases where `name` is invalid, aa_splitn_fqname returns without initializing `ns_name` and `ns_len`. Fix this by always initializing `ns_name` and `ns_len`. __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x1c4/0x2b4 lib/dump_stack.c:113 print_address_description.cold.8+0x9/0x1ff mm/kasan/report.c:256 kasan_report_error mm/kasan/report.c:354 [inline] kasan_report.cold.9+0x242/0x309 mm/kasan/report.c:412 __asan_report_load1_noabort+0x14/0x20 mm/kasan/report.c:430 memcmp+0xe3/0x160 lib/string.c:861 strnstr+0x4b/0x70 lib/string.c:934 __aa_lookupn_ns+0xc1/0x570 security/apparmor/policy_ns.c:209 aa_lookupn_ns+0x88/0x1e0 security/apparmor/policy_ns.c:240 aa_fqlookupn_profile+0x1b9/0x1010 security/apparmor/policy.c:468 fqlookupn_profile+0x80/0xc0 security/apparmor/label.c:1844 aa_label_strn_parse+0xa3a/0x1230 security/apparmor/label.c:1908 aa_label_parse+0x42/0x50 security/apparmor/label.c:1943 aa_change_profile+0x513/0x3510 security/apparmor/domain.c:1362 apparmor_setprocattr+0xaa4/0x1150 security/apparmor/lsm.c:658 security_setprocattr+0x66/0xc0 security/security.c:1298 proc_pid_attr_write+0x301/0x540 fs/proc/base.c:2555 __vfs_write+0x119/0x9f0 fs/read_write.c:485 vfs_write+0x1fc/0x560 fs/read_write.c:549 ksys_write+0x101/0x260 fs/read_write.c:598 __do_sys_write fs/read_write.c:610 [inline] __se_sys_write fs/read_write.c:607 [inline] __x64_sys_write+0x73/0xb0 fs/read_write.c:607 do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290 entry_SYSCALL_64_after_hwframe+0x49/0xbe Fixes: 3b0aaf5866bf ("apparmor: add lib fn to find the "split" for fqnames") Reported-by: syzbot+61e4b490d9d2da591b50@syzkaller.appspotmail.com Signed-off-by: Zubin Mithra Reviewed-by: Kees Cook Signed-off-by: John Johansen Signed-off-by: Sasha Levin --- security/apparmor/lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/security/apparmor/lib.c b/security/apparmor/lib.c index 08ca26bcca77..451654372a76 100644 --- a/security/apparmor/lib.c +++ b/security/apparmor/lib.c @@ -90,10 +90,12 @@ const char *aa_splitn_fqname(const char *fqname, size_t n, const char **ns_name, const char *end = fqname + n; const char *name = skipn_spaces(fqname, n); - if (!name) - return NULL; *ns_name = NULL; *ns_len = 0; + + if (!name) + return NULL; + if (name[0] == ':') { char *split = strnchr(&name[1], end - &name[1], ':'); *ns_name = skipn_spaces(&name[1], end - &name[1]); -- GitLab From ad2e60ff51a7bbcaf87cf66875e3a28aaefbaedd Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Wed, 3 Oct 2018 00:49:21 +0800 Subject: [PATCH 0018/1286] x86/earlyprintk: Add a force option for pciserial device [ Upstream commit d2266bbfa9e3e32e3b642965088ca461bd24a94f ] The "pciserial" earlyprintk variant helps much on many modern x86 platforms, but unfortunately there are still some platforms with PCI UART devices which have the wrong PCI class code. In that case, the current class code check does not allow for them to be used for logging. Add a sub-option "force" which overrides the class code check and thus the use of such device can be enforced. [ bp: massage formulations. ] Suggested-by: Borislav Petkov Signed-off-by: Feng Tang Signed-off-by: Borislav Petkov Cc: "H. Peter Anvin" Cc: "Stuart R . Anderson" Cc: Bjorn Helgaas Cc: David Rientjes Cc: Feng Tang Cc: Frederic Weisbecker Cc: Greg Kroah-Hartman Cc: H Peter Anvin Cc: Ingo Molnar Cc: Jiri Kosina Cc: Jonathan Corbet Cc: Kai-Heng Feng Cc: Kate Stewart Cc: Konrad Rzeszutek Wilk Cc: Peter Zijlstra Cc: Philippe Ombredanne Cc: Thomas Gleixner Cc: Thymo van Beers Cc: alan@linux.intel.com Cc: linux-doc@vger.kernel.org Link: http://lkml.kernel.org/r/20181002164921.25833-1-feng.tang@intel.com Signed-off-by: Sasha Levin --- .../admin-guide/kernel-parameters.txt | 6 +++- arch/x86/kernel/early_printk.c | 29 ++++++++++++------- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9841bad6f271..99a08722124d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1011,7 +1011,7 @@ earlyprintk=serial[,0x...[,baudrate]] earlyprintk=ttySn[,baudrate] earlyprintk=dbgp[debugController#] - earlyprintk=pciserial,bus:device.function[,baudrate] + earlyprintk=pciserial[,force],bus:device.function[,baudrate] earlyprintk=xdbc[xhciController#] earlyprintk is useful when the kernel crashes before @@ -1043,6 +1043,10 @@ The sclp output can only be used on s390. + The optional "force" to "pciserial" enables use of a + PCI device even when its classcode is not of the + UART class. + edac_report= [HW,EDAC] Control how to report EDAC event Format: {"on" | "off" | "force"} on: enable EDAC to report H/W event. May be overridden diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index 5e801c8c8ce7..374a52fa5296 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -213,8 +213,9 @@ static unsigned int mem32_serial_in(unsigned long addr, int offset) * early_pci_serial_init() * * This function is invoked when the early_printk param starts with "pciserial" - * The rest of the param should be ",B:D.F,baud" where B, D & F describe the - * location of a PCI device that must be a UART device. + * The rest of the param should be "[force],B:D.F,baud", where B, D & F describe + * the location of a PCI device that must be a UART device. "force" is optional + * and overrides the use of an UART device with a wrong PCI class code. */ static __init void early_pci_serial_init(char *s) { @@ -224,17 +225,23 @@ static __init void early_pci_serial_init(char *s) u32 classcode, bar0; u16 cmdreg; char *e; + int force = 0; - - /* - * First, part the param to get the BDF values - */ if (*s == ',') ++s; if (*s == 0) return; + /* Force the use of an UART device with wrong class code */ + if (!strncmp(s, "force,", 6)) { + force = 1; + s += 6; + } + + /* + * Part the param to get the BDF values + */ bus = (u8)simple_strtoul(s, &e, 16); s = e; if (*s != ':') @@ -253,7 +260,7 @@ static __init void early_pci_serial_init(char *s) s++; /* - * Second, find the device from the BDF + * Find the device from the BDF */ cmdreg = read_pci_config(bus, slot, func, PCI_COMMAND); classcode = read_pci_config(bus, slot, func, PCI_CLASS_REVISION); @@ -264,8 +271,10 @@ static __init void early_pci_serial_init(char *s) */ if (((classcode >> 16 != PCI_CLASS_COMMUNICATION_MODEM) && (classcode >> 16 != PCI_CLASS_COMMUNICATION_SERIAL)) || - (((classcode >> 8) & 0xff) != 0x02)) /* 16550 I/F at BAR0 */ - return; + (((classcode >> 8) & 0xff) != 0x02)) /* 16550 I/F at BAR0 */ { + if (!force) + return; + } /* * Determine if it is IO or memory mapped @@ -289,7 +298,7 @@ static __init void early_pci_serial_init(char *s) } /* - * Lastly, initialize the hardware + * Initialize the hardware */ if (*s) { if (strcmp(s, "nocfg") == 0) -- GitLab From 4f9ffc2711d0d6651b67fa68ab75feec7201ecff Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 20 Sep 2018 21:44:19 -0400 Subject: [PATCH 0019/1286] platform/x86: acerhdf: Add BIOS entry for Gateway LT31 v1.3307 [ Upstream commit 684238d79ad85c5e19a71bb5818e77e329912fbc ] To fix: acerhdf: unknown (unsupported) BIOS version Gateway /LT31 /v1.3307 , please report, aborting! As can be seen in the context, the BIOS registers haven't changed in the previous versions, so the assumption is they won't have changed in this last update for this somewhat older platform either. Cc: Peter Feuerer Cc: Darren Hart Cc: Andy Shevchenko Signed-off-by: Paul Gortmaker Signed-off-by: Andy Shevchenko Reviewed-by: Peter Feuerer Signed-off-by: Sasha Levin --- drivers/platform/x86/acerhdf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c index ea22591ee66f..53dfe67807e3 100644 --- a/drivers/platform/x86/acerhdf.c +++ b/drivers/platform/x86/acerhdf.c @@ -233,6 +233,7 @@ static const struct bios_settings bios_tbl[] = { {"Gateway", "LT31", "v1.3201", 0x55, 0x58, {0x9e, 0x00}, 0}, {"Gateway", "LT31", "v1.3302", 0x55, 0x58, {0x9e, 0x00}, 0}, {"Gateway", "LT31", "v1.3303t", 0x55, 0x58, {0x9e, 0x00}, 0}, + {"Gateway", "LT31", "v1.3307", 0x55, 0x58, {0x9e, 0x00}, 0}, /* Packard Bell */ {"Packard Bell", "DOA150", "v0.3104", 0x55, 0x58, {0x21, 0x00}, 0}, {"Packard Bell", "DOA150", "v0.3105", 0x55, 0x58, {0x20, 0x00}, 0}, -- GitLab From 10c51fa85c9879f7d90b184f940e2e16e5e3b330 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 25 Sep 2018 12:44:59 -0700 Subject: [PATCH 0020/1286] arm64: percpu: Initialize ret in the default case [ Upstream commit b5bb425871186303e6936fa2581521bdd1964a58 ] Clang warns that if the default case is taken, ret will be uninitialized. ./arch/arm64/include/asm/percpu.h:196:2: warning: variable 'ret' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ ./arch/arm64/include/asm/percpu.h:200:9: note: uninitialized use occurs here return ret; ^~~ ./arch/arm64/include/asm/percpu.h:157:19: note: initialize the variable 'ret' to silence this warning unsigned long ret, loop; ^ = 0 This warning appears several times while building the erofs filesystem. While it's not strictly wrong, the BUILD_BUG will prevent this from becoming a true problem. Initialize ret to 0 in the default case right before the BUILD_BUG to silence all of these warnings. Reported-by: Prasad Sodagudi Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Dennis Zhou Signed-off-by: Sasha Levin --- arch/arm64/include/asm/percpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h index 43393208229e..d79eaa816f29 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -93,6 +93,7 @@ static inline unsigned long __percpu_##op(void *ptr, \ : [val] "Ir" (val)); \ break; \ default: \ + ret = 0; \ BUILD_BUG(); \ } \ \ @@ -122,6 +123,7 @@ static inline unsigned long __percpu_read(void *ptr, int size) ret = READ_ONCE(*(u64 *)ptr); break; default: + ret = 0; BUILD_BUG(); } @@ -191,6 +193,7 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val, : [val] "r" (val)); break; default: + ret = 0; BUILD_BUG(); } -- GitLab From 221609ce4ce547d2fbad0e7ecd68d66e12f358ec Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Fri, 19 Oct 2018 15:37:01 +0200 Subject: [PATCH 0021/1286] s390/vdso: add missing FORCE to build targets [ Upstream commit b44b136a3773d8a9c7853f8df716bd1483613cbb ] According to Documentation/kbuild/makefiles.txt all build targets using if_changed should use FORCE as well. Add missing FORCE to make sure vdso targets are rebuild properly when not just immediate prerequisites have changed but also when build command differs. Reviewed-by: Philipp Rudo Signed-off-by: Vasily Gorbik Signed-off-by: Martin Schwidefsky Signed-off-by: Sasha Levin --- arch/s390/kernel/vdso32/Makefile | 6 +++--- arch/s390/kernel/vdso64/Makefile | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/s390/kernel/vdso32/Makefile b/arch/s390/kernel/vdso32/Makefile index 308564b9bf68..101cadabfc89 100644 --- a/arch/s390/kernel/vdso32/Makefile +++ b/arch/s390/kernel/vdso32/Makefile @@ -33,7 +33,7 @@ UBSAN_SANITIZE := n $(obj)/vdso32_wrapper.o : $(obj)/vdso32.so # link rule for the .so file, .lds has to be first -$(obj)/vdso32.so.dbg: $(src)/vdso32.lds $(obj-vdso32) +$(obj)/vdso32.so.dbg: $(src)/vdso32.lds $(obj-vdso32) FORCE $(call if_changed,vdso32ld) # strip rule for the .so file @@ -42,12 +42,12 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE $(call if_changed,objcopy) # assembly rules for the .S files -$(obj-vdso32): %.o: %.S +$(obj-vdso32): %.o: %.S FORCE $(call if_changed_dep,vdso32as) # actual build commands quiet_cmd_vdso32ld = VDSO32L $@ - cmd_vdso32ld = $(CC) $(c_flags) -Wl,-T $^ -o $@ + cmd_vdso32ld = $(CC) $(c_flags) -Wl,-T $(filter %.lds %.o,$^) -o $@ quiet_cmd_vdso32as = VDSO32A $@ cmd_vdso32as = $(CC) $(a_flags) -c -o $@ $< diff --git a/arch/s390/kernel/vdso64/Makefile b/arch/s390/kernel/vdso64/Makefile index f81ae7998883..36bbafcf4a77 100644 --- a/arch/s390/kernel/vdso64/Makefile +++ b/arch/s390/kernel/vdso64/Makefile @@ -33,7 +33,7 @@ UBSAN_SANITIZE := n $(obj)/vdso64_wrapper.o : $(obj)/vdso64.so # link rule for the .so file, .lds has to be first -$(obj)/vdso64.so.dbg: $(src)/vdso64.lds $(obj-vdso64) +$(obj)/vdso64.so.dbg: $(src)/vdso64.lds $(obj-vdso64) FORCE $(call if_changed,vdso64ld) # strip rule for the .so file @@ -42,12 +42,12 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE $(call if_changed,objcopy) # assembly rules for the .S files -$(obj-vdso64): %.o: %.S +$(obj-vdso64): %.o: %.S FORCE $(call if_changed_dep,vdso64as) # actual build commands quiet_cmd_vdso64ld = VDSO64L $@ - cmd_vdso64ld = $(CC) $(c_flags) -Wl,-T $^ -o $@ + cmd_vdso64ld = $(CC) $(c_flags) -Wl,-T $(filter %.lds %.o,$^) -o $@ quiet_cmd_vdso64as = VDSO64A $@ cmd_vdso64as = $(CC) $(a_flags) -c -o $@ $< -- GitLab From a1e0ae82cfd5f05973a6459ec17ed61df5cf0f9f Mon Sep 17 00:00:00 2001 From: Stefano Brivio Date: Sat, 14 Jul 2018 21:59:43 +0200 Subject: [PATCH 0022/1286] netfilter: ipset: list:set: Decrease refcount synchronously on deletion and replace [ Upstream commit 439cd39ea136d2c026805264d58a91f36b6b64ca ] Commit 45040978c899 ("netfilter: ipset: Fix set:list type crash when flush/dump set in parallel") postponed decreasing set reference counters to the RCU callback. An 'ipset del' command can terminate before the RCU grace period is elapsed, and if sets are listed before then, the reference counter shown in userspace will be wrong: # ipset create h hash:ip; ipset create l list:set; ipset add l # ipset del l h; ipset list h Name: h Type: hash:ip Revision: 4 Header: family inet hashsize 1024 maxelem 65536 Size in memory: 88 References: 1 Number of entries: 0 Members: # sleep 1; ipset list h Name: h Type: hash:ip Revision: 4 Header: family inet hashsize 1024 maxelem 65536 Size in memory: 88 References: 0 Number of entries: 0 Members: Fix this by making the reference count update synchronous again. As a result, when sets are listed, ip_set_name_byindex() might now fetch a set whose reference count is already zero. Instead of relying on the reference count to protect against concurrent set renaming, grab ip_set_ref_lock as reader and copy the name, while holding the same lock in ip_set_rename() as writer instead. Reported-by: Li Shuang Fixes: 45040978c899 ("netfilter: ipset: Fix set:list type crash when flush/dump set in parallel") Signed-off-by: Stefano Brivio Signed-off-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/linux/netfilter/ipset/ip_set.h | 2 +- net/netfilter/ipset/ip_set_core.c | 23 +++++++++++------------ net/netfilter/ipset/ip_set_list_set.c | 17 +++++++++++------ 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/include/linux/netfilter/ipset/ip_set.h b/include/linux/netfilter/ipset/ip_set.h index 8e42253e5d4d..91a533bd3eb1 100644 --- a/include/linux/netfilter/ipset/ip_set.h +++ b/include/linux/netfilter/ipset/ip_set.h @@ -312,7 +312,7 @@ enum { extern ip_set_id_t ip_set_get_byname(struct net *net, const char *name, struct ip_set **set); extern void ip_set_put_byindex(struct net *net, ip_set_id_t index); -extern const char *ip_set_name_byindex(struct net *net, ip_set_id_t index); +extern void ip_set_name_byindex(struct net *net, ip_set_id_t index, char *name); extern ip_set_id_t ip_set_nfnl_get_byindex(struct net *net, ip_set_id_t index); extern void ip_set_nfnl_put(struct net *net, ip_set_id_t index); diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c index 9d2ce1459cec..a3f1dc7cf538 100644 --- a/net/netfilter/ipset/ip_set_core.c +++ b/net/netfilter/ipset/ip_set_core.c @@ -668,21 +668,20 @@ ip_set_put_byindex(struct net *net, ip_set_id_t index) EXPORT_SYMBOL_GPL(ip_set_put_byindex); /* Get the name of a set behind a set index. - * We assume the set is referenced, so it does exist and - * can't be destroyed. The set cannot be renamed due to - * the referencing either. - * + * Set itself is protected by RCU, but its name isn't: to protect against + * renaming, grab ip_set_ref_lock as reader (see ip_set_rename()) and copy the + * name. */ -const char * -ip_set_name_byindex(struct net *net, ip_set_id_t index) +void +ip_set_name_byindex(struct net *net, ip_set_id_t index, char *name) { - const struct ip_set *set = ip_set_rcu_get(net, index); + struct ip_set *set = ip_set_rcu_get(net, index); BUG_ON(!set); - BUG_ON(set->ref == 0); - /* Referenced, so it's safe */ - return set->name; + read_lock_bh(&ip_set_ref_lock); + strncpy(name, set->name, IPSET_MAXNAMELEN); + read_unlock_bh(&ip_set_ref_lock); } EXPORT_SYMBOL_GPL(ip_set_name_byindex); @@ -1128,7 +1127,7 @@ static int ip_set_rename(struct net *net, struct sock *ctnl, if (!set) return -ENOENT; - read_lock_bh(&ip_set_ref_lock); + write_lock_bh(&ip_set_ref_lock); if (set->ref != 0) { ret = -IPSET_ERR_REFERENCED; goto out; @@ -1145,7 +1144,7 @@ static int ip_set_rename(struct net *net, struct sock *ctnl, strncpy(set->name, name2, IPSET_MAXNAMELEN); out: - read_unlock_bh(&ip_set_ref_lock); + write_unlock_bh(&ip_set_ref_lock); return ret; } diff --git a/net/netfilter/ipset/ip_set_list_set.c b/net/netfilter/ipset/ip_set_list_set.c index 178d4eba013b..75d52aed6fdb 100644 --- a/net/netfilter/ipset/ip_set_list_set.c +++ b/net/netfilter/ipset/ip_set_list_set.c @@ -156,9 +156,7 @@ __list_set_del_rcu(struct rcu_head * rcu) { struct set_elem *e = container_of(rcu, struct set_elem, rcu); struct ip_set *set = e->set; - struct list_set *map = set->data; - ip_set_put_byindex(map->net, e->id); ip_set_ext_destroy(set, e); kfree(e); } @@ -166,15 +164,21 @@ __list_set_del_rcu(struct rcu_head * rcu) static inline void list_set_del(struct ip_set *set, struct set_elem *e) { + struct list_set *map = set->data; + set->elements--; list_del_rcu(&e->list); + ip_set_put_byindex(map->net, e->id); call_rcu(&e->rcu, __list_set_del_rcu); } static inline void -list_set_replace(struct set_elem *e, struct set_elem *old) +list_set_replace(struct ip_set *set, struct set_elem *e, struct set_elem *old) { + struct list_set *map = set->data; + list_replace_rcu(&old->list, &e->list); + ip_set_put_byindex(map->net, old->id); call_rcu(&old->rcu, __list_set_del_rcu); } @@ -306,7 +310,7 @@ list_set_uadd(struct ip_set *set, void *value, const struct ip_set_ext *ext, INIT_LIST_HEAD(&e->list); list_set_init_extensions(set, ext, e); if (n) - list_set_replace(e, n); + list_set_replace(set, e, n); else if (next) list_add_tail_rcu(&e->list, &next->list); else if (prev) @@ -497,6 +501,7 @@ list_set_list(const struct ip_set *set, const struct list_set *map = set->data; struct nlattr *atd, *nested; u32 i = 0, first = cb->args[IPSET_CB_ARG0]; + char name[IPSET_MAXNAMELEN]; struct set_elem *e; int ret = 0; @@ -515,8 +520,8 @@ list_set_list(const struct ip_set *set, nested = ipset_nest_start(skb, IPSET_ATTR_DATA); if (!nested) goto nla_put_failure; - if (nla_put_string(skb, IPSET_ATTR_NAME, - ip_set_name_byindex(map->net, e->id))) + ip_set_name_byindex(map->net, e->id, name); + if (nla_put_string(skb, IPSET_ATTR_NAME, name)) goto nla_put_failure; if (ip_set_put_extensions(skb, set, e, true)) goto nla_put_failure; -- GitLab From 0d5d0b5c41f766355f2b42c47d13ea001f754c7d Mon Sep 17 00:00:00 2001 From: Eric Westbrook Date: Tue, 28 Aug 2018 15:14:42 -0600 Subject: [PATCH 0023/1286] netfilter: ipset: actually allow allowable CIDR 0 in hash:net,port,net [ Upstream commit 886503f34d63e681662057448819edb5b1057a97 ] Allow /0 as advertised for hash:net,port,net sets. For "hash:net,port,net", ipset(8) says that "either subnet is permitted to be a /0 should you wish to match port between all destinations." Make that statement true. Before: # ipset create cidrzero hash:net,port,net # ipset add cidrzero 0.0.0.0/0,12345,0.0.0.0/0 ipset v6.34: The value of the CIDR parameter of the IP address is invalid # ipset create cidrzero6 hash:net,port,net family inet6 # ipset add cidrzero6 ::/0,12345,::/0 ipset v6.34: The value of the CIDR parameter of the IP address is invalid After: # ipset create cidrzero hash:net,port,net # ipset add cidrzero 0.0.0.0/0,12345,0.0.0.0/0 # ipset test cidrzero 192.168.205.129,12345,172.16.205.129 192.168.205.129,tcp:12345,172.16.205.129 is in set cidrzero. # ipset create cidrzero6 hash:net,port,net family inet6 # ipset add cidrzero6 ::/0,12345,::/0 # ipset test cidrzero6 fe80::1,12345,ff00::1 fe80::1,tcp:12345,ff00::1 is in set cidrzero6. See also: https://bugzilla.kernel.org/show_bug.cgi?id=200897 https://github.com/ewestbrook/linux/commit/df7ff6efb0934ab6acc11f003ff1a7580d6c1d9c Signed-off-by: Eric Westbrook Signed-off-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/ipset/ip_set_hash_netportnet.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/net/netfilter/ipset/ip_set_hash_netportnet.c b/net/netfilter/ipset/ip_set_hash_netportnet.c index 8602f2595a1a..0e6e40c6f652 100644 --- a/net/netfilter/ipset/ip_set_hash_netportnet.c +++ b/net/netfilter/ipset/ip_set_hash_netportnet.c @@ -213,13 +213,13 @@ hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[], if (tb[IPSET_ATTR_CIDR]) { e.cidr[0] = nla_get_u8(tb[IPSET_ATTR_CIDR]); - if (!e.cidr[0] || e.cidr[0] > HOST_MASK) + if (e.cidr[0] > HOST_MASK) return -IPSET_ERR_INVALID_CIDR; } if (tb[IPSET_ATTR_CIDR2]) { e.cidr[1] = nla_get_u8(tb[IPSET_ATTR_CIDR2]); - if (!e.cidr[1] || e.cidr[1] > HOST_MASK) + if (e.cidr[1] > HOST_MASK) return -IPSET_ERR_INVALID_CIDR; } @@ -492,13 +492,13 @@ hash_netportnet6_uadt(struct ip_set *set, struct nlattr *tb[], if (tb[IPSET_ATTR_CIDR]) { e.cidr[0] = nla_get_u8(tb[IPSET_ATTR_CIDR]); - if (!e.cidr[0] || e.cidr[0] > HOST_MASK) + if (e.cidr[0] > HOST_MASK) return -IPSET_ERR_INVALID_CIDR; } if (tb[IPSET_ATTR_CIDR2]) { e.cidr[1] = nla_get_u8(tb[IPSET_ATTR_CIDR2]); - if (!e.cidr[1] || e.cidr[1] > HOST_MASK) + if (e.cidr[1] > HOST_MASK) return -IPSET_ERR_INVALID_CIDR; } -- GitLab From 28bd72a7262a2256d4e2fa35b8bba47cb43e8142 Mon Sep 17 00:00:00 2001 From: "Justin M. Forbes" Date: Wed, 31 Oct 2018 13:02:03 -0500 Subject: [PATCH 0024/1286] s390/mm: Fix ERROR: "__node_distance" undefined! [ Upstream commit a541f0ebcc08ed8bc0cc492eec9a86cb280a9f24 ] Fixes: ERROR: "__node_distance" [drivers/nvme/host/nvme-core.ko] undefined! make[1]: *** [scripts/Makefile.modpost:92: __modpost] Error 1 make: *** [Makefile:1275: modules] Error 2 + exit 1 Signed-off-by: Justin M. Forbes Signed-off-by: Heiko Carstens Signed-off-by: Martin Schwidefsky Signed-off-by: Sasha Levin --- arch/s390/numa/numa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/s390/numa/numa.c b/arch/s390/numa/numa.c index 5bd374491f94..6c151b42e65d 100644 --- a/arch/s390/numa/numa.c +++ b/arch/s390/numa/numa.c @@ -54,6 +54,7 @@ int __node_distance(int a, int b) { return mode->distance ? mode->distance(a, b) : 0; } +EXPORT_SYMBOL(__node_distance); int numa_debug_enabled; -- GitLab From 79f2eb5fde82c5264cb51cf52c1c24bd3cef6b47 Mon Sep 17 00:00:00 2001 From: Jozsef Kadlecsik Date: Fri, 19 Oct 2018 19:35:19 +0200 Subject: [PATCH 0025/1286] netfilter: ipset: Correct rcu_dereference() call in ip_set_put_comment() [ Upstream commit 17b8b74c0f8dbf9b9e3301f9ca5b65dd1c079951 ] The function is called when rcu_read_lock() is held and not when rcu_read_lock_bh() is held. Signed-off-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/linux/netfilter/ipset/ip_set_comment.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/netfilter/ipset/ip_set_comment.h b/include/linux/netfilter/ipset/ip_set_comment.h index 8e2bab1e8e90..70877f8de7e9 100644 --- a/include/linux/netfilter/ipset/ip_set_comment.h +++ b/include/linux/netfilter/ipset/ip_set_comment.h @@ -43,11 +43,11 @@ ip_set_init_comment(struct ip_set *set, struct ip_set_comment *comment, rcu_assign_pointer(comment->c, c); } -/* Used only when dumping a set, protected by rcu_read_lock_bh() */ +/* Used only when dumping a set, protected by rcu_read_lock() */ static inline int ip_set_put_comment(struct sk_buff *skb, const struct ip_set_comment *comment) { - struct ip_set_comment_rcu *c = rcu_dereference_bh(comment->c); + struct ip_set_comment_rcu *c = rcu_dereference(comment->c); if (!c) return 0; -- GitLab From fdf4e678ea193ec9c2e099509994a118260f0d8c Mon Sep 17 00:00:00 2001 From: Taehee Yoo Date: Sun, 21 Oct 2018 00:00:08 +0900 Subject: [PATCH 0026/1286] netfilter: xt_IDLETIMER: add sysfs filename checking routine [ Upstream commit 54451f60c8fa061af9051a53be9786393947367c ] When IDLETIMER rule is added, sysfs file is created under /sys/class/xt_idletimer/timers/ But some label name shouldn't be used. ".", "..", "power", "uevent", "subsystem", etc... So that sysfs filename checking routine is needed. test commands: %iptables -I INPUT -j IDLETIMER --timeout 1 --label "power" splat looks like: [95765.423132] sysfs: cannot create duplicate filename '/devices/virtual/xt_idletimer/timers/power' [95765.433418] CPU: 0 PID: 8446 Comm: iptables Not tainted 4.19.0-rc6+ #20 [95765.449755] Call Trace: [95765.449755] dump_stack+0xc9/0x16b [95765.449755] ? show_regs_print_info+0x5/0x5 [95765.449755] sysfs_warn_dup+0x74/0x90 [95765.449755] sysfs_add_file_mode_ns+0x352/0x500 [95765.449755] sysfs_create_file_ns+0x179/0x270 [95765.449755] ? sysfs_add_file_mode_ns+0x500/0x500 [95765.449755] ? idletimer_tg_checkentry+0x3e5/0xb1b [xt_IDLETIMER] [95765.449755] ? rcu_read_lock_sched_held+0x114/0x130 [95765.449755] ? __kmalloc_track_caller+0x211/0x2b0 [95765.449755] ? memcpy+0x34/0x50 [95765.449755] idletimer_tg_checkentry+0x4e2/0xb1b [xt_IDLETIMER] [ ... ] Fixes: 0902b469bd25 ("netfilter: xtables: idletimer target implementation") Signed-off-by: Taehee Yoo Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/xt_IDLETIMER.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/net/netfilter/xt_IDLETIMER.c b/net/netfilter/xt_IDLETIMER.c index 1141f08810b6..3fef8c2e545d 100644 --- a/net/netfilter/xt_IDLETIMER.c +++ b/net/netfilter/xt_IDLETIMER.c @@ -116,6 +116,22 @@ static void idletimer_tg_expired(unsigned long data) schedule_work(&timer->work); } +static int idletimer_check_sysfs_name(const char *name, unsigned int size) +{ + int ret; + + ret = xt_check_proc_name(name, size); + if (ret < 0) + return ret; + + if (!strcmp(name, "power") || + !strcmp(name, "subsystem") || + !strcmp(name, "uevent")) + return -EINVAL; + + return 0; +} + static int idletimer_tg_create(struct idletimer_tg_info *info) { int ret; @@ -126,6 +142,10 @@ static int idletimer_tg_create(struct idletimer_tg_info *info) goto out; } + ret = idletimer_check_sysfs_name(info->label, sizeof(info->label)); + if (ret < 0) + goto out_free_timer; + sysfs_attr_init(&info->timer->attr.attr); info->timer->attr.attr.name = kstrdup(info->label, GFP_KERNEL); if (!info->timer->attr.attr.name) { -- GitLab From 8cab58117e72caa2234323ce399f77037fe4dea2 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Fri, 2 Nov 2018 19:04:09 +0100 Subject: [PATCH 0027/1286] s390/qeth: fix HiperSockets sniffer [ Upstream commit bd74a7f9cc033cf4d405788f80292268987dc0c5 ] Sniffing mode for L3 HiperSockets requires that no IP addresses are registered with the HW. The preferred way to achieve this is for userspace to delete all the IPs on the interface. But qeth is expected to also tolerate a configuration where that is not the case, by skipping the IP registration when in sniffer mode. Since commit 5f78e29ceebf ("qeth: optimize IP handling in rx_mode callback") reworked the IP registration logic in the L3 subdriver, this no longer works. When the qeth device is set online, qeth_l3_recover_ip() now unconditionally registers all unicast addresses from our internal IP table. While we could fix this particular problem by skipping qeth_l3_recover_ip() on a sniffer device, the more future-proof change is to skip the IP address registration at the lowest level. This way we a) catch any future code path that attempts to register an IP address without considering the sniffer scenario, and b) continue to build up our internal IP table, so that if sniffer mode is switched off later we can operate just like normal. Fixes: 5f78e29ceebf ("qeth: optimize IP handling in rx_mode callback") Signed-off-by: Julian Wiedmann Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/s390/net/qeth_l3_main.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index cd73172bff47..a19f2dc69e8a 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -358,9 +358,6 @@ static void qeth_l3_clear_ip_htable(struct qeth_card *card, int recover) QETH_CARD_TEXT(card, 4, "clearip"); - if (recover && card->options.sniffer) - return; - spin_lock_bh(&card->ip_lock); hash_for_each_safe(card->ip_htable, i, tmp, addr, hnode) { @@ -818,6 +815,8 @@ static int qeth_l3_register_addr_entry(struct qeth_card *card, int rc = 0; int cnt = 3; + if (card->options.sniffer) + return 0; if (addr->proto == QETH_PROT_IPV4) { QETH_CARD_TEXT(card, 2, "setaddr4"); @@ -853,6 +852,9 @@ static int qeth_l3_deregister_addr_entry(struct qeth_card *card, { int rc = 0; + if (card->options.sniffer) + return 0; + if (addr->proto == QETH_PROT_IPV4) { QETH_CARD_TEXT(card, 2, "deladdr4"); QETH_CARD_HEX(card, 3, &addr->u.a4.addr, sizeof(int)); -- GitLab From 21eb778e7dd55c4a690b662d988798a2eb988c1d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 28 Oct 2018 18:16:51 +0100 Subject: [PATCH 0028/1286] hwmon: (ibmpowernv) Remove bogus __init annotations [ Upstream commit e3e61f01d755188cb6c2dcf5a244b9c0937c258e ] If gcc decides not to inline make_sensor_label(): WARNING: vmlinux.o(.text+0x4df549c): Section mismatch in reference from the function .create_device_attrs() to the function .init.text:.make_sensor_label() The function .create_device_attrs() references the function __init .make_sensor_label(). This is often because .create_device_attrs lacks a __init annotation or the annotation of .make_sensor_label is wrong. As .probe() can be called after freeing of __init memory, all __init annotiations in the driver are bogus, and should be removed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/ibmpowernv.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/ibmpowernv.c b/drivers/hwmon/ibmpowernv.c index 5ccdd0b52650..b38f4951c94e 100644 --- a/drivers/hwmon/ibmpowernv.c +++ b/drivers/hwmon/ibmpowernv.c @@ -126,7 +126,7 @@ static ssize_t show_label(struct device *dev, struct device_attribute *devattr, return sprintf(buf, "%s\n", sdata->label); } -static int __init get_logical_cpu(int hwcpu) +static int get_logical_cpu(int hwcpu) { int cpu; @@ -137,9 +137,8 @@ static int __init get_logical_cpu(int hwcpu) return -ENOENT; } -static void __init make_sensor_label(struct device_node *np, - struct sensor_data *sdata, - const char *label) +static void make_sensor_label(struct device_node *np, + struct sensor_data *sdata, const char *label) { u32 id; size_t n; -- GitLab From c6b1ef1110ce90b66dbd957b706d58fd1ce4f4b4 Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Fri, 5 Oct 2018 11:50:20 +0900 Subject: [PATCH 0029/1286] Revert "drm/exynos/decon5433: implement frame counter" [ Upstream commit 6ca469e22a30992b4478d2ab88737c70667c1e00 ] This reverts commit 0586feba322e1de05075700eb4b835c8b683e62b This patch makes it to need get_vblank_counter callback in crtc to get frame counter from decon driver. However, drm_dev->max_vblank_count is a member unique to vendor's DRM driver but in case of ARM DRM, some CRTC devices don't provide the frame counter value. As a result, this patch made extension and clone mode not working. Instead of this patch, we may need separated max_vblank_count which belongs to each CRTC device, or need to implement frame counter emulation for them who don't support HW frame counter. Signed-off-by: Inki Dae Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 9 --------- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 11 ----------- drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 - 3 files changed, 21 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index f905c214fdd0..5a5b3535411f 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -160,13 +160,6 @@ static u32 decon_get_frame_count(struct decon_context *ctx, bool end) return frm; } -static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc) -{ - struct decon_context *ctx = crtc->ctx; - - return decon_get_frame_count(ctx, false); -} - static void decon_setup_trigger(struct decon_context *ctx) { if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) @@ -532,7 +525,6 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = { .disable = decon_disable, .enable_vblank = decon_enable_vblank, .disable_vblank = decon_disable_vblank, - .get_vblank_counter = decon_get_vblank_counter, .atomic_begin = decon_atomic_begin, .update_plane = decon_update_plane, .disable_plane = decon_disable_plane, @@ -550,7 +542,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data) int ret; ctx->drm_dev = drm_dev; - drm_dev->max_vblank_count = 0xffffffff; for (win = ctx->first_win; win < WINDOWS_NR; win++) { int tmp = (win == ctx->first_win) ? 0 : win; diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 6ce0821590df..4787560bf93e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -147,16 +147,6 @@ static void exynos_drm_crtc_disable_vblank(struct drm_crtc *crtc) exynos_crtc->ops->disable_vblank(exynos_crtc); } -static u32 exynos_drm_crtc_get_vblank_counter(struct drm_crtc *crtc) -{ - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - - if (exynos_crtc->ops->get_vblank_counter) - return exynos_crtc->ops->get_vblank_counter(exynos_crtc); - - return 0; -} - static const struct drm_crtc_funcs exynos_crtc_funcs = { .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, @@ -166,7 +156,6 @@ static const struct drm_crtc_funcs exynos_crtc_funcs = { .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, .enable_vblank = exynos_drm_crtc_enable_vblank, .disable_vblank = exynos_drm_crtc_disable_vblank, - .get_vblank_counter = exynos_drm_crtc_get_vblank_counter, }; struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index f8bae4cb4823..d228b5148dbc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -133,7 +133,6 @@ struct exynos_drm_crtc_ops { void (*disable)(struct exynos_drm_crtc *crtc); int (*enable_vblank)(struct exynos_drm_crtc *crtc); void (*disable_vblank)(struct exynos_drm_crtc *crtc); - u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc); enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, const struct drm_display_mode *mode); int (*atomic_check)(struct exynos_drm_crtc *crtc, -- GitLab From 35b3e230a2b5dc9068a8779f1b77754b9c3edfde Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Thu, 1 Nov 2018 14:15:49 +0100 Subject: [PATCH 0030/1286] clk: fixed-factor: fix of_node_get-put imbalance [ Upstream commit f98e8a572bddbf27032114127d2fcc78fa5e6a9d ] When the fixed factor clock is created by devicetree, of_clk_add_provider is called. Add a call to of_clk_del_provider in the remove function to balance it out. Reported-by: Alan Tull Fixes: 971451b3b15d ("clk: fixed-factor: Convert into a module platform driver") Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-fixed-factor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 20724abd38bd..7df6b5b1e7ee 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -210,6 +210,7 @@ static int of_fixed_factor_clk_remove(struct platform_device *pdev) { struct clk *clk = platform_get_drvdata(pdev); + of_clk_del_provider(pdev->dev.of_node); clk_unregister_fixed_factor(clk); return 0; -- GitLab From 615a30e8dbc9c60bb35f3687072fb077160ea0b7 Mon Sep 17 00:00:00 2001 From: Jeremy Linton Date: Mon, 5 Nov 2018 18:14:41 -0600 Subject: [PATCH 0031/1286] lib/raid6: Fix arm64 test build [ Upstream commit 313a06e636808387822af24c507cba92703568b1 ] The lib/raid6/test fails to build the neon objects on arm64 because the correct machine type is 'aarch64'. Once this is correctly enabled, the neon recovery objects need to be added to the build. Reviewed-by: Ard Biesheuvel Signed-off-by: Jeremy Linton Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- lib/raid6/test/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index be1010bdc435..565a77220fae 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -27,7 +27,7 @@ ifeq ($(ARCH),arm) CFLAGS += -I../../../arch/arm/include -mfpu=neon HAS_NEON = yes endif -ifeq ($(ARCH),arm64) +ifeq ($(ARCH),aarch64) CFLAGS += -I../../../arch/arm64/include HAS_NEON = yes endif @@ -41,7 +41,7 @@ ifeq ($(IS_X86),yes) gcc -c -x assembler - >&/dev/null && \ rm ./-.o && echo -DCONFIG_AS_AVX512=1) else ifeq ($(HAS_NEON),yes) - OBJS += neon.o neon1.o neon2.o neon4.o neon8.o + OBJS += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o CFLAGS += -DCONFIG_KERNEL_MODE_NEON=1 else HAS_ALTIVEC := $(shell printf '\#include \nvector int a;\n' |\ -- GitLab From 850e4ca7868046e13b66cb0d656398960efc4162 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 29 Oct 2018 08:11:33 +0000 Subject: [PATCH 0032/1286] s390/perf: Change CPUM_CF return code in event init function [ Upstream commit 0bb2ae1b26e1fb7543ec7474cdd374ac4b88c4da ] The function perf_init_event() creates a new event and assignes it to a PMU. This a done in a loop over all existing PMUs. For each listed PMU the event init function is called and if this function does return any other error than -ENOENT, the loop is terminated the creation of the event fails. If the event is invalid, return -ENOENT to try other PMUs. Signed-off-by: Thomas Richter Reviewed-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky Signed-off-by: Sasha Levin --- arch/s390/kernel/perf_cpum_cf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 746d03423333..61e91fee8467 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -376,7 +376,7 @@ static int __hw_perf_event_init(struct perf_event *event) return -ENOENT; if (ev > PERF_CPUM_CF_MAX_CTR) - return -EINVAL; + return -ENOENT; /* Obtain the counter set to which the specified counter belongs */ set = get_counter_set(ev); -- GitLab From ef8d2a5d990af5d658aafd37b41e29782b690bff Mon Sep 17 00:00:00 2001 From: Valentin Schneider Date: Tue, 23 Oct 2018 14:37:31 +0100 Subject: [PATCH 0033/1286] sched/core: Take the hotplug lock in sched_init_smp() [ Upstream commit 40fa3780bac2b654edf23f6b13f4e2dd550aea10 ] When running on linux-next (8c60c36d0b8c ("Add linux-next specific files for 20181019")) + CONFIG_PROVE_LOCKING=y on a big.LITTLE system (e.g. Juno or HiKey960), we get the following report: [ 0.748225] Call trace: [ 0.750685] lockdep_assert_cpus_held+0x30/0x40 [ 0.755236] static_key_enable_cpuslocked+0x20/0xc8 [ 0.760137] build_sched_domains+0x1034/0x1108 [ 0.764601] sched_init_domains+0x68/0x90 [ 0.768628] sched_init_smp+0x30/0x80 [ 0.772309] kernel_init_freeable+0x278/0x51c [ 0.776685] kernel_init+0x10/0x108 [ 0.780190] ret_from_fork+0x10/0x18 The static_key in question is 'sched_asym_cpucapacity' introduced by commit: df054e8445a4 ("sched/topology: Add static_key for asymmetric CPU capacity optimizations") In this particular case, we enable it because smp_prepare_cpus() will end up fetching the capacity-dmips-mhz entry from the devicetree, so we already have some asymmetry detected when entering sched_init_smp(). This didn't get detected in tip/sched/core because we were missing: commit cb538267ea1e ("jump_label/lockdep: Assert we hold the hotplug lock for _cpuslocked() operations") Calls to build_sched_domains() post sched_init_smp() will hold the hotplug lock, it just so happens that this very first call is a special case. As stated by a comment in sched_init_smp(), "There's no userspace yet to cause hotplug operations" so this is a harmless warning. However, to both respect the semantics of underlying callees and make lockdep happy, take the hotplug lock in sched_init_smp(). This also satisfies the comment atop sched_init_domains() that says "Callers must hold the hotplug lock". Reported-by: Sudeep Holla Tested-by: Sudeep Holla Signed-off-by: Valentin Schneider Signed-off-by: Peter Zijlstra (Intel) Cc: Dietmar.Eggemann@arm.com Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: morten.rasmussen@arm.com Cc: quentin.perret@arm.com Link: http://lkml.kernel.org/r/1540301851-3048-1-git-send-email-valentin.schneider@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- kernel/sched/core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 4e89ed8a0fb2..3bc664662081 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5733,14 +5733,17 @@ void __init sched_init_smp(void) /* * There's no userspace yet to cause hotplug operations; hence all the * CPU masks are stable and all blatant races in the below code cannot - * happen. + * happen. The hotplug lock is nevertheless taken to satisfy lockdep, + * but there won't be any contention on it. */ + cpus_read_lock(); mutex_lock(&sched_domains_mutex); sched_init_domains(cpu_active_mask); cpumask_andnot(non_isolated_cpus, cpu_possible_mask, cpu_isolated_map); if (cpumask_empty(non_isolated_cpus)) cpumask_set_cpu(smp_processor_id(), non_isolated_cpus); mutex_unlock(&sched_domains_mutex); + cpus_read_unlock(); /* Move init over to a non-isolated CPU */ if (set_cpus_allowed_ptr(current, non_isolated_cpus) < 0) -- GitLab From fc88b3abe23fe3d4cb2e2b1f3f7036e7f68889fe Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Thu, 1 Nov 2018 20:13:21 -0400 Subject: [PATCH 0034/1286] perf tools: Fix undefined symbol scnprintf in libperf-jvmti.so [ Upstream commit 6ac2226229d931153331a93d90655a3de05b9290 ] Currently jvmti agent can not be used because function scnprintf is not present in the agent libperf-jvmti.so. As a result the JVM when using such agent to record JITed code profiling information will fail on looking up scnprintf: java: symbol lookup error: lib/libperf-jvmti.so: undefined symbol: scnprintf This commit fixes that by reverting to the use of snprintf, that can be looked up, instead of scnprintf, adding a proper check for the returned value in order to print a better error message when the jitdump file pathname is too long. Checking the returned value also helps to comply with some recent gcc versions, like gcc8, which will fail due to truncated writing checks related to the -Werror=format-truncation= flag. Signed-off-by: Gustavo Romero Acked-by: Jiri Olsa LPU-Reference: 1541117601-18937-2-git-send-email-gromero@linux.vnet.ibm.com Link: https://lkml.kernel.org/n/tip-mvpxxxy7wnzaj74cq75muw3f@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/jvmti/jvmti_agent.c | 49 ++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/tools/perf/jvmti/jvmti_agent.c b/tools/perf/jvmti/jvmti_agent.c index c1d20d951434..4ad9948fe594 100644 --- a/tools/perf/jvmti/jvmti_agent.c +++ b/tools/perf/jvmti/jvmti_agent.c @@ -125,7 +125,7 @@ perf_get_timestamp(void) } static int -debug_cache_init(void) +create_jit_cache_dir(void) { char str[32]; char *base, *p; @@ -144,8 +144,13 @@ debug_cache_init(void) strftime(str, sizeof(str), JIT_LANG"-jit-%Y%m%d", &tm); - snprintf(jit_path, PATH_MAX - 1, "%s/.debug/", base); - + ret = snprintf(jit_path, PATH_MAX, "%s/.debug/", base); + if (ret >= PATH_MAX) { + warnx("jvmti: cannot generate jit cache dir because %s/.debug/" + " is too long, please check the cwd, JITDUMPDIR, and" + " HOME variables", base); + return -1; + } ret = mkdir(jit_path, 0755); if (ret == -1) { if (errno != EEXIST) { @@ -154,20 +159,32 @@ debug_cache_init(void) } } - snprintf(jit_path, PATH_MAX - 1, "%s/.debug/jit", base); + ret = snprintf(jit_path, PATH_MAX, "%s/.debug/jit", base); + if (ret >= PATH_MAX) { + warnx("jvmti: cannot generate jit cache dir because" + " %s/.debug/jit is too long, please check the cwd," + " JITDUMPDIR, and HOME variables", base); + return -1; + } ret = mkdir(jit_path, 0755); if (ret == -1) { if (errno != EEXIST) { - warn("cannot create jit cache dir %s", jit_path); + warn("jvmti: cannot create jit cache dir %s", jit_path); return -1; } } - snprintf(jit_path, PATH_MAX - 1, "%s/.debug/jit/%s.XXXXXXXX", base, str); - + ret = snprintf(jit_path, PATH_MAX, "%s/.debug/jit/%s.XXXXXXXX", base, str); + if (ret >= PATH_MAX) { + warnx("jvmti: cannot generate jit cache dir because" + " %s/.debug/jit/%s.XXXXXXXX is too long, please check" + " the cwd, JITDUMPDIR, and HOME variables", + base, str); + return -1; + } p = mkdtemp(jit_path); if (p != jit_path) { - warn("cannot create jit cache dir %s", jit_path); + warn("jvmti: cannot create jit cache dir %s", jit_path); return -1; } @@ -228,7 +245,7 @@ void *jvmti_open(void) { char dump_path[PATH_MAX]; struct jitheader header; - int fd; + int fd, ret; FILE *fp; init_arch_timestamp(); @@ -245,12 +262,22 @@ void *jvmti_open(void) memset(&header, 0, sizeof(header)); - debug_cache_init(); + /* + * jitdump file dir + */ + if (create_jit_cache_dir() < 0) + return NULL; /* * jitdump file name */ - scnprintf(dump_path, PATH_MAX, "%s/jit-%i.dump", jit_path, getpid()); + ret = snprintf(dump_path, PATH_MAX, "%s/jit-%i.dump", jit_path, getpid()); + if (ret >= PATH_MAX) { + warnx("jvmti: cannot generate jitdump file full path because" + " %s/jit-%i.dump is too long, please check the cwd," + " JITDUMPDIR, and HOME variables", jit_path, getpid()); + return NULL; + } fd = open(dump_path, O_CREAT|O_TRUNC|O_RDWR, 0666); if (fd == -1) -- GitLab From eddf9365687f829beeca47a3d0cfcdf6252e46a1 Mon Sep 17 00:00:00 2001 From: Jacob Keller Date: Mon, 29 Oct 2018 10:52:42 -0700 Subject: [PATCH 0035/1286] i40e: restore NETIF_F_GSO_IPXIP[46] to netdev features [ Upstream commit ba766b8b99c30ad3c55ed8cf224d1185ecff1476 ] Since commit bacd75cfac8a ("i40e/i40evf: Add capability exchange for outer checksum", 2017-04-06) the i40e driver has not reported support for IP-in-IP offloads. This likely occurred due to a bad rebase, as the commit extracts hw_enc_features into its own variable. As part of this change, it dropped the NETIF_F_FSO_IPXIP flags from the netdev->hw_enc_features. This was unfortunately not caught during code review. Fix this by adding back the missing feature flags. For reference, NETIF_F_GSO_IPXIP4 was added in commit 7e13318daa4a ("net: define gso types for IPx over IPv4 and IPv6", 2016-05-20), replacing NETIF_F_GSO_IPIP and NETIF_F_GSO_SIT. NETIF_F_GSO_IPXIP6 was added in commit bf2d1df39502 ("intel: Add support for IPv6 IP-in-IP offload", 2016-05-20). Signed-off-by: Jacob Keller Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 04dbf64fb1cb..176c99b8251d 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -9688,6 +9688,8 @@ static int i40e_config_netdev(struct i40e_vsi *vsi) NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_PARTIAL | + NETIF_F_GSO_IPXIP4 | + NETIF_F_GSO_IPXIP6 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | -- GitLab From 484ef227384f88c0b52e9dd43529eccf7c4025da Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Thu, 8 Nov 2018 16:46:08 +0200 Subject: [PATCH 0036/1286] qed: Fix memory/entry leak in qed_init_sp_request() [ Upstream commit 39477551df940ddb1339203817de04f5caaacf7a ] Free the allocated SPQ entry or return the acquired SPQ entry to the free list in error flows. Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- .../net/ethernet/qlogic/qed/qed_sp_commands.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c b/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c index d7c5965328be..b26578464469 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c +++ b/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c @@ -80,7 +80,7 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn, case QED_SPQ_MODE_BLOCK: if (!p_data->p_comp_data) - return -EINVAL; + goto err; p_ent->comp_cb.cookie = p_data->p_comp_data->cookie; break; @@ -95,7 +95,7 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn, default: DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n", p_ent->comp_mode); - return -EINVAL; + goto err; } DP_VERBOSE(p_hwfn, QED_MSG_SPQ, @@ -109,6 +109,18 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn, memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod)); return 0; + +err: + /* qed_spq_get_entry() can either get an entry from the free_pool, + * or, if no entries are left, allocate a new entry and add it to + * the unlimited_pending list. + */ + if (p_ent->queue == &p_hwfn->p_spq->unlimited_pending) + kfree(p_ent); + else + qed_spq_return_entry(p_hwfn, p_ent); + + return -EINVAL; } static enum tunnel_clss qed_tunn_clss_to_fw_clss(u8 type) -- GitLab From 082810cb7f21c52dbe4c15f247e87ad22b88bbb8 Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Thu, 8 Nov 2018 16:46:09 +0200 Subject: [PATCH 0037/1286] qed: Fix blocking/unlimited SPQ entries leak [ Upstream commit 2632f22ebd08da249c2017962a199a0cfb2324bf ] When there are no SPQ entries left in the free_pool, new entries are allocated and are added to the unlimited list. When an entry in the pool is available, the content is copied from the original entry, and the new entry is sent to the device. qed_spq_post() is not aware of that, so the additional entry is stored in the original entry as p_post_ent, which can later be returned to the pool. Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_sp.h | 3 ++ drivers/net/ethernet/qlogic/qed/qed_spq.c | 57 ++++++++++++----------- 2 files changed, 33 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_sp.h b/drivers/net/ethernet/qlogic/qed/qed_sp.h index ab4ad8a1e2a5..01a213d4ee9c 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_sp.h +++ b/drivers/net/ethernet/qlogic/qed/qed_sp.h @@ -167,6 +167,9 @@ struct qed_spq_entry { enum spq_mode comp_mode; struct qed_spq_comp_cb comp_cb; struct qed_spq_comp_done comp_done; /* SPQ_MODE_EBLOCK */ + + /* Posted entry for unlimited list entry in EBLOCK mode */ + struct qed_spq_entry *post_ent; }; struct qed_eq { diff --git a/drivers/net/ethernet/qlogic/qed/qed_spq.c b/drivers/net/ethernet/qlogic/qed/qed_spq.c index be48d9abd001..0313e9c46979 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_spq.c +++ b/drivers/net/ethernet/qlogic/qed/qed_spq.c @@ -687,6 +687,8 @@ static int qed_spq_add_entry(struct qed_hwfn *p_hwfn, /* EBLOCK responsible to free the allocated p_ent */ if (p_ent->comp_mode != QED_SPQ_MODE_EBLOCK) kfree(p_ent); + else + p_ent->post_ent = p_en2; p_ent = p_en2; } @@ -770,6 +772,25 @@ static int qed_spq_pend_post(struct qed_hwfn *p_hwfn) SPQ_HIGH_PRI_RESERVE_DEFAULT); } +/* Avoid overriding of SPQ entries when getting out-of-order completions, by + * marking the completions in a bitmap and increasing the chain consumer only + * for the first successive completed entries. + */ +static void qed_spq_comp_bmap_update(struct qed_hwfn *p_hwfn, __le16 echo) +{ + u16 pos = le16_to_cpu(echo) % SPQ_RING_SIZE; + struct qed_spq *p_spq = p_hwfn->p_spq; + + __set_bit(pos, p_spq->p_comp_bitmap); + while (test_bit(p_spq->comp_bitmap_idx, + p_spq->p_comp_bitmap)) { + __clear_bit(p_spq->comp_bitmap_idx, + p_spq->p_comp_bitmap); + p_spq->comp_bitmap_idx++; + qed_chain_return_produced(&p_spq->chain); + } +} + int qed_spq_post(struct qed_hwfn *p_hwfn, struct qed_spq_entry *p_ent, u8 *fw_return_code) { @@ -821,11 +842,12 @@ int qed_spq_post(struct qed_hwfn *p_hwfn, p_ent->queue == &p_spq->unlimited_pending); if (p_ent->queue == &p_spq->unlimited_pending) { - /* This is an allocated p_ent which does not need to - * return to pool. - */ + struct qed_spq_entry *p_post_ent = p_ent->post_ent; + kfree(p_ent); - return rc; + + /* Return the entry which was actually posted */ + p_ent = p_post_ent; } if (rc) @@ -839,7 +861,7 @@ int qed_spq_post(struct qed_hwfn *p_hwfn, spq_post_fail2: spin_lock_bh(&p_spq->lock); list_del(&p_ent->list); - qed_chain_return_produced(&p_spq->chain); + qed_spq_comp_bmap_update(p_hwfn, p_ent->elem.hdr.echo); spq_post_fail: /* return to the free pool */ @@ -871,25 +893,8 @@ int qed_spq_completion(struct qed_hwfn *p_hwfn, spin_lock_bh(&p_spq->lock); list_for_each_entry_safe(p_ent, tmp, &p_spq->completion_pending, list) { if (p_ent->elem.hdr.echo == echo) { - u16 pos = le16_to_cpu(echo) % SPQ_RING_SIZE; - list_del(&p_ent->list); - - /* Avoid overriding of SPQ entries when getting - * out-of-order completions, by marking the completions - * in a bitmap and increasing the chain consumer only - * for the first successive completed entries. - */ - __set_bit(pos, p_spq->p_comp_bitmap); - - while (test_bit(p_spq->comp_bitmap_idx, - p_spq->p_comp_bitmap)) { - __clear_bit(p_spq->comp_bitmap_idx, - p_spq->p_comp_bitmap); - p_spq->comp_bitmap_idx++; - qed_chain_return_produced(&p_spq->chain); - } - + qed_spq_comp_bmap_update(p_hwfn, echo); p_spq->comp_count++; found = p_ent; break; @@ -928,11 +933,9 @@ int qed_spq_completion(struct qed_hwfn *p_hwfn, QED_MSG_SPQ, "Got a completion without a callback function\n"); - if ((found->comp_mode != QED_SPQ_MODE_EBLOCK) || - (found->queue == &p_spq->unlimited_pending)) + if (found->comp_mode != QED_SPQ_MODE_EBLOCK) /* EBLOCK is responsible for returning its own entry into the - * free list, unless it originally added the entry into the - * unlimited pending list. + * free list. */ qed_spq_return_entry(p_hwfn, found); -- GitLab From fe2c4df2692de3c724ac8720d4479cbe16d89814 Mon Sep 17 00:00:00 2001 From: Sagiv Ozeri Date: Thu, 8 Nov 2018 16:46:11 +0200 Subject: [PATCH 0038/1286] qed: Fix potential memory corruption [ Upstream commit fa5c448d98f0df660bfcad3dd5facc027ef84cd3 ] A stuck ramrod should be deleted from the completion_pending list, otherwise it will be added again in the future and corrupt the list. Return error value to inform that ramrod is stuck and should be deleted. Signed-off-by: Sagiv Ozeri Signed-off-by: Denis Bolotin Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_spq.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_spq.c b/drivers/net/ethernet/qlogic/qed/qed_spq.c index 0313e9c46979..467755b6dd0b 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_spq.c +++ b/drivers/net/ethernet/qlogic/qed/qed_spq.c @@ -144,6 +144,7 @@ static int qed_spq_block(struct qed_hwfn *p_hwfn, DP_INFO(p_hwfn, "Ramrod is stuck, requesting MCP drain\n"); rc = qed_mcp_drain(p_hwfn, p_ptt); + qed_ptt_release(p_hwfn, p_ptt); if (rc) { DP_NOTICE(p_hwfn, "MCP drain failed\n"); goto err; @@ -152,18 +153,15 @@ static int qed_spq_block(struct qed_hwfn *p_hwfn, /* Retry after drain */ rc = __qed_spq_block(p_hwfn, p_ent, p_fw_ret, true); if (!rc) - goto out; + return 0; comp_done = (struct qed_spq_comp_done *)p_ent->comp_cb.cookie; - if (comp_done->done == 1) + if (comp_done->done == 1) { if (p_fw_ret) *p_fw_ret = comp_done->fw_return_code; -out: - qed_ptt_release(p_hwfn, p_ptt); - return 0; - + return 0; + } err: - qed_ptt_release(p_hwfn, p_ptt); DP_NOTICE(p_hwfn, "Ramrod is stuck [CID %08x cmd %02x protocol %02x echo %04x]\n", le32_to_cpu(p_ent->elem.hdr.cid), -- GitLab From 47ff76ee9c9c938531ec97b7b4a74804a10f04fc Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 8 Nov 2018 11:42:14 -0600 Subject: [PATCH 0039/1286] net: stmmac: Fix RX packet size > 8191 [ Upstream commit 8137b6ef0ce469154e5cf19f8e7fe04d9a72ac5e ] Ping problems with packets > 8191 as shown: PING 192.168.1.99 (192.168.1.99) 8150(8178) bytes of data. 8158 bytes from 192.168.1.99: icmp_seq=1 ttl=64 time=0.669 ms wrong data byte 8144 should be 0xd0 but was 0x0 16 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f %< ---------------snip-------------------------------------- 8112 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf 8144 0 0 0 0 d0 d1 ^^^^^^^ Notice the 4 bytes of 0 before the expected byte of d0. Databook notes that the RX buffer must be a multiple of 4/8/16 bytes [1]. Update the DMA Buffer size define to 8188 instead of 8192. Remove the -1 from the RX buffer size allocations and use the new DMA Buffer size directly. [1] Synopsys DesignWare Cores Ethernet MAC Universal v3.70a [section 8.4.2 - Table 8-24] Tested on SoCFPGA Stratix10 with ping sweep from 100 to 8300 byte packets. Fixes: 286a83721720 ("stmmac: add CHAINED descriptor mode support (V4)") Suggested-by: Jose Abreu Signed-off-by: Thor Thayer Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/common.h | 3 ++- drivers/net/ethernet/stmicro/stmmac/descs_com.h | 2 +- drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 2 +- drivers/net/ethernet/stmicro/stmmac/ring_mode.c | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 627fec210e2f..8e2a19616bc9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -340,7 +340,8 @@ struct dma_features { /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ #define BUF_SIZE_16KiB 16384 -#define BUF_SIZE_8KiB 8192 +/* RX Buffer size must be < 8191 and multiple of 4/8/16 bytes */ +#define BUF_SIZE_8KiB 8188 #define BUF_SIZE_4KiB 4096 #define BUF_SIZE_2KiB 2048 diff --git a/drivers/net/ethernet/stmicro/stmmac/descs_com.h b/drivers/net/ethernet/stmicro/stmmac/descs_com.h index ca9d7e48034c..40d6356a7e73 100644 --- a/drivers/net/ethernet/stmicro/stmmac/descs_com.h +++ b/drivers/net/ethernet/stmicro/stmmac/descs_com.h @@ -31,7 +31,7 @@ /* Enhanced descriptors */ static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end) { - p->des1 |= cpu_to_le32(((BUF_SIZE_8KiB - 1) + p->des1 |= cpu_to_le32((BUF_SIZE_8KiB << ERDES1_BUFFER2_SIZE_SHIFT) & ERDES1_BUFFER2_SIZE_MASK); diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c index 2a828a312814..acd65a4f94d4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c @@ -262,7 +262,7 @@ static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode, int end) { p->des0 |= cpu_to_le32(RDES0_OWN); - p->des1 |= cpu_to_le32((BUF_SIZE_8KiB - 1) & ERDES1_BUFFER1_SIZE_MASK); + p->des1 |= cpu_to_le32(BUF_SIZE_8KiB & ERDES1_BUFFER1_SIZE_MASK); if (mode == STMMAC_CHAIN_MODE) ehn_desc_rx_set_on_chain(p); diff --git a/drivers/net/ethernet/stmicro/stmmac/ring_mode.c b/drivers/net/ethernet/stmicro/stmmac/ring_mode.c index 28e4b5d50ce6..1af7b078b94d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/ring_mode.c +++ b/drivers/net/ethernet/stmicro/stmmac/ring_mode.c @@ -143,7 +143,7 @@ static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p) static int stmmac_set_16kib_bfsize(int mtu) { int ret = 0; - if (unlikely(mtu >= BUF_SIZE_8KiB)) + if (unlikely(mtu > BUF_SIZE_8KiB)) ret = BUF_SIZE_16KiB; return ret; } -- GitLab From c887029c11d0c2bc14da9eb02704669cebab89a9 Mon Sep 17 00:00:00 2001 From: Minchan Kim Date: Fri, 23 Nov 2018 15:25:50 +0900 Subject: [PATCH 0040/1286] zram: close udev startup race condition as default groups commit fef912bf860e upstream. commit 98af4d4df889 upstream. I got a report from Howard Chen that he saw zram and sysfs race(ie, zram block device file is created but sysfs for it isn't yet) when he tried to create new zram devices via hotadd knob. v4.20 kernel fixes it by [1, 2] but it's too large size to merge into -stable so this patch fixes the problem by registering defualt group by Greg KH's approach[3]. This patch should be applied to every stable tree [3.16+] currently existing from kernel.org because the problem was introduced at 2.6.37 by [4]. [1] fef912bf860e, block: genhd: add 'groups' argument to device_add_disk [2] 98af4d4df889, zram: register default groups with device_add_disk() [3] http://kroah.com/log/blog/2013/06/26/how-to-create-a-sysfs-file-correctly/ [4] 33863c21e69e9, Staging: zram: Replace ioctls with sysfs interface Cc: Sergey Senozhatsky Cc: Hannes Reinecke Tested-by: Howard Chen Signed-off-by: Minchan Kim Signed-off-by: Sasha Levin --- drivers/block/zram/zram_drv.c | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 1e2648e4c286..27b202c64c84 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -1491,6 +1491,11 @@ static const struct attribute_group zram_disk_attr_group = { .attrs = zram_disk_attrs, }; +static const struct attribute_group *zram_disk_attr_groups[] = { + &zram_disk_attr_group, + NULL, +}; + /* * Allocate and initialize new zram device. the function returns * '>= 0' device_id upon success, and negative value otherwise. @@ -1568,23 +1573,14 @@ static int zram_add(void) if (ZRAM_LOGICAL_BLOCK_SIZE == PAGE_SIZE) blk_queue_max_write_zeroes_sectors(zram->disk->queue, UINT_MAX); + disk_to_dev(zram->disk)->groups = zram_disk_attr_groups; add_disk(zram->disk); - ret = sysfs_create_group(&disk_to_dev(zram->disk)->kobj, - &zram_disk_attr_group); - if (ret < 0) { - pr_err("Error creating sysfs group for device %d\n", - device_id); - goto out_free_disk; - } strlcpy(zram->compressor, default_compressor, sizeof(zram->compressor)); pr_info("Added device: %s\n", zram->disk->disk_name); return device_id; -out_free_disk: - del_gendisk(zram->disk); - put_disk(zram->disk); out_free_queue: blk_cleanup_queue(queue); out_free_idr: @@ -1612,16 +1608,6 @@ static int zram_remove(struct zram *zram) zram->claim = true; mutex_unlock(&bdev->bd_mutex); - /* - * Remove sysfs first, so no one will perform a disksize - * store while we destroy the devices. This also helps during - * hot_remove -- zram_reset_device() is the last holder of - * ->init_lock, no later/concurrent disksize_store() or any - * other sysfs handlers are possible. - */ - sysfs_remove_group(&disk_to_dev(zram->disk)->kobj, - &zram_disk_attr_group); - /* Make sure all the pending I/O are finished */ fsync_bdev(bdev); zram_reset_device(zram); -- GitLab From 26eff850549b52e43d0bc61f4682952fe2da293d Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Thu, 8 Nov 2018 02:04:57 +0000 Subject: [PATCH 0041/1286] SUNRPC: drop pointless static qualifier in xdr_get_next_encode_buffer() [ Upstream commit 025911a5f4e36955498ed50806ad1b02f0f76288 ] There is no need to have the '__be32 *p' variable static since new value always be assigned before use it. Signed-off-by: YueHaibing Cc: stable@vger.kernel.org Signed-off-by: J. Bruce Fields Signed-off-by: Sasha Levin --- net/sunrpc/xdr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/sunrpc/xdr.c b/net/sunrpc/xdr.c index 13695ba8fc54..4f382805eb9c 100644 --- a/net/sunrpc/xdr.c +++ b/net/sunrpc/xdr.c @@ -512,7 +512,7 @@ EXPORT_SYMBOL_GPL(xdr_commit_encode); static __be32 *xdr_get_next_encode_buffer(struct xdr_stream *xdr, size_t nbytes) { - static __be32 *p; + __be32 *p; int space_left; int frag1bytes, frag2bytes; -- GitLab From 8c209c38d8fa633bfd519476f6b616ee1bc8eb06 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 22 May 2018 14:16:50 +0300 Subject: [PATCH 0042/1286] ACPI / watchdog: Prefer iTCO_wdt always when WDAT table uses RTC SRAM [ Upstream commit 5a802a7a285c8877ca872e44eeb0f06afcb5212f ] After we added quirk for Lenovo Z50-70 it turns out there are at least two more systems where WDAT table includes instructions accessing RTC SRAM. Instead of quirking each system separately, look for such instructions in the table and automatically prefer iTCO_wdt if found. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199033 Reported-by: Arnold Guy Reported-by: Alois Nespor Reported-by: Yury Pakin Reported-by: Ihor Chyhin Signed-off-by: Mika Westerberg Acked-by: Guenter Roeck Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpi_watchdog.c | 72 ++++++++++++++++++++++-------------- 1 file changed, 45 insertions(+), 27 deletions(-) diff --git a/drivers/acpi/acpi_watchdog.c b/drivers/acpi/acpi_watchdog.c index 4bde16fb97d8..95600309ce42 100644 --- a/drivers/acpi/acpi_watchdog.c +++ b/drivers/acpi/acpi_watchdog.c @@ -12,35 +12,51 @@ #define pr_fmt(fmt) "ACPI: watchdog: " fmt #include -#include #include #include #include "internal.h" -static const struct dmi_system_id acpi_watchdog_skip[] = { - { - /* - * On Lenovo Z50-70 there are two issues with the WDAT - * table. First some of the instructions use RTC SRAM - * to store persistent information. This does not work well - * with Linux RTC driver. Second, more important thing is - * that the instructions do not actually reset the system. - * - * On this particular system iTCO_wdt seems to work just - * fine so we prefer that over WDAT for now. - * - * See also https://bugzilla.kernel.org/show_bug.cgi?id=199033. - */ - .ident = "Lenovo Z50-70", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_NAME, "20354"), - DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Z50-70"), - }, - }, - {} -}; +#ifdef CONFIG_RTC_MC146818_LIB +#include + +/* + * There are several systems where the WDAT table is accessing RTC SRAM to + * store persistent information. This does not work well with the Linux RTC + * driver so on those systems we skip WDAT driver and prefer iTCO_wdt + * instead. + * + * See also https://bugzilla.kernel.org/show_bug.cgi?id=199033. + */ +static bool acpi_watchdog_uses_rtc(const struct acpi_table_wdat *wdat) +{ + const struct acpi_wdat_entry *entries; + int i; + + entries = (struct acpi_wdat_entry *)(wdat + 1); + for (i = 0; i < wdat->entries; i++) { + const struct acpi_generic_address *gas; + + gas = &entries[i].register_region; + if (gas->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + switch (gas->address) { + case RTC_PORT(0): + case RTC_PORT(1): + case RTC_PORT(2): + case RTC_PORT(3): + return true; + } + } + } + + return false; +} +#else +static bool acpi_watchdog_uses_rtc(const struct acpi_table_wdat *wdat) +{ + return false; +} +#endif static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void) { @@ -50,9 +66,6 @@ static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void) if (acpi_disabled) return NULL; - if (dmi_check_system(acpi_watchdog_skip)) - return NULL; - status = acpi_get_table(ACPI_SIG_WDAT, 0, (struct acpi_table_header **)&wdat); if (ACPI_FAILURE(status)) { @@ -60,6 +73,11 @@ static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void) return NULL; } + if (acpi_watchdog_uses_rtc(wdat)) { + pr_info("Skipping WDAT on this system because it uses RTC SRAM\n"); + return NULL; + } + return wdat; } -- GitLab From e404a6294a31b2b68cecdd2e89d61cc6ed87dddd Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 21 Nov 2018 15:52:43 +0200 Subject: [PATCH 0043/1286] perf machine: Add machine__is() to identify machine arch commit dbbd34a666ee117d0e39e71a47f38f02c4a5c698 upstream. Add a function to identify the machine architecture. Signed-off-by: Adrian Hunter Tested-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andy Lutomirski Cc: Dave Hansen Cc: H. Peter Anvin Cc: Joerg Roedel Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: x86@kernel.org Link: http://lkml.kernel.org/r/1526548928-20790-6-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/env.c | 19 +++++++++++++++++++ tools/perf/util/env.h | 3 +++ tools/perf/util/machine.c | 9 +++++++++ tools/perf/util/machine.h | 2 ++ 4 files changed, 33 insertions(+) diff --git a/tools/perf/util/env.c b/tools/perf/util/env.c index 6276b340f893..49f58921a968 100644 --- a/tools/perf/util/env.c +++ b/tools/perf/util/env.c @@ -3,6 +3,7 @@ #include "env.h" #include "util.h" #include +#include struct perf_env perf_env; @@ -87,6 +88,24 @@ int perf_env__read_cpu_topology_map(struct perf_env *env) return 0; } +static int perf_env__read_arch(struct perf_env *env) +{ + struct utsname uts; + + if (env->arch) + return 0; + + if (!uname(&uts)) + env->arch = strdup(uts.machine); + + return env->arch ? 0 : -ENOMEM; +} + +const char *perf_env__raw_arch(struct perf_env *env) +{ + return env && !perf_env__read_arch(env) ? env->arch : "unknown"; +} + void cpu_cache_level__free(struct cpu_cache_level *cache) { free(cache->type); diff --git a/tools/perf/util/env.h b/tools/perf/util/env.h index 1eb35b190b34..bd3869913907 100644 --- a/tools/perf/util/env.h +++ b/tools/perf/util/env.h @@ -65,4 +65,7 @@ int perf_env__set_cmdline(struct perf_env *env, int argc, const char *argv[]); int perf_env__read_cpu_topology_map(struct perf_env *env); void cpu_cache_level__free(struct cpu_cache_level *cache); + +const char *perf_env__raw_arch(struct perf_env *env); + #endif /* __PERF_ENV_H */ diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index bd5d5b5e2218..2af879693fbe 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -2238,6 +2238,15 @@ int machine__set_current_tid(struct machine *machine, int cpu, pid_t pid, return 0; } +/* + * Compares the raw arch string. N.B. see instead perf_env__arch() if a + * normalized arch is needed. + */ +bool machine__is(struct machine *machine, const char *arch) +{ + return machine && !strcmp(perf_env__raw_arch(machine->env), arch); +} + int machine__get_kernel_start(struct machine *machine) { struct map *map = machine__kernel_map(machine); diff --git a/tools/perf/util/machine.h b/tools/perf/util/machine.h index d551aa80a59b..fbc5133fb27c 100644 --- a/tools/perf/util/machine.h +++ b/tools/perf/util/machine.h @@ -169,6 +169,8 @@ static inline bool machine__is_host(struct machine *machine) return machine ? machine->pid == HOST_KERNEL_ID : false; } +bool machine__is(struct machine *machine, const char *arch); + struct thread *__machine__findnew_thread(struct machine *machine, pid_t pid, pid_t tid); struct thread *machine__findnew_thread(struct machine *machine, pid_t pid, pid_t tid); -- GitLab From 4edc059bac38f8cb59a8e539fb36fe0b8d19c55e Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 21 Nov 2018 15:52:44 +0200 Subject: [PATCH 0044/1286] perf tools: Fix kernel_start for PTI on x86 commit 19422a9f2a3be7f3a046285ffae4cbb571aa853a upstream. On x86_64, PTI entry trampolines are less than the start of kernel text, but still above 2^63. So leave kernel_start = 1ULL << 63 for x86_64. Signed-off-by: Adrian Hunter Tested-by: Jiri Olsa Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andy Lutomirski Cc: Dave Hansen Cc: H. Peter Anvin Cc: Joerg Roedel Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: x86@kernel.org Link: http://lkml.kernel.org/r/1526548928-20790-7-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/machine.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 2af879693fbe..af18c3d55642 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -2263,7 +2263,12 @@ int machine__get_kernel_start(struct machine *machine) machine->kernel_start = 1ULL << 63; if (map) { err = map__load(map); - if (!err) + /* + * On x86_64, PTI entry trampolines are less than the + * start of kernel text, but still above 2^63. So leave + * kernel_start = 1ULL << 63 for x86_64. + */ + if (!err && !machine__is(machine, "x86_64")) machine->kernel_start = map->start; } return err; -- GitLab From 5d390059eab4bc9b3bfcba01a214ab873514f578 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 21 Nov 2018 15:52:45 +0200 Subject: [PATCH 0045/1286] perf machine: Add nr_cpus_avail() commit 9cecca325ea879c84fcd31a5e609a514c1a1dbd1 upstream. Add a function to return the number of the machine's available CPUs. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andy Lutomirski Cc: Dave Hansen Cc: H. Peter Anvin Cc: Jiri Olsa Cc: Joerg Roedel Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: x86@kernel.org Link: http://lkml.kernel.org/r/1526986485-6562-5-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/env.c | 13 +++++++++++++ tools/perf/util/env.h | 1 + tools/perf/util/machine.c | 5 +++++ tools/perf/util/machine.h | 1 + 4 files changed, 20 insertions(+) diff --git a/tools/perf/util/env.c b/tools/perf/util/env.c index 49f58921a968..b492cb974aa0 100644 --- a/tools/perf/util/env.c +++ b/tools/perf/util/env.c @@ -101,11 +101,24 @@ static int perf_env__read_arch(struct perf_env *env) return env->arch ? 0 : -ENOMEM; } +static int perf_env__read_nr_cpus_avail(struct perf_env *env) +{ + if (env->nr_cpus_avail == 0) + env->nr_cpus_avail = cpu__max_present_cpu(); + + return env->nr_cpus_avail ? 0 : -ENOENT; +} + const char *perf_env__raw_arch(struct perf_env *env) { return env && !perf_env__read_arch(env) ? env->arch : "unknown"; } +int perf_env__nr_cpus_avail(struct perf_env *env) +{ + return env && !perf_env__read_nr_cpus_avail(env) ? env->nr_cpus_avail : 0; +} + void cpu_cache_level__free(struct cpu_cache_level *cache) { free(cache->type); diff --git a/tools/perf/util/env.h b/tools/perf/util/env.h index bd3869913907..9aace8452751 100644 --- a/tools/perf/util/env.h +++ b/tools/perf/util/env.h @@ -67,5 +67,6 @@ int perf_env__read_cpu_topology_map(struct perf_env *env); void cpu_cache_level__free(struct cpu_cache_level *cache); const char *perf_env__raw_arch(struct perf_env *env); +int perf_env__nr_cpus_avail(struct perf_env *env); #endif /* __PERF_ENV_H */ diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index af18c3d55642..78aa1c5f19ca 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -2247,6 +2247,11 @@ bool machine__is(struct machine *machine, const char *arch) return machine && !strcmp(perf_env__raw_arch(machine->env), arch); } +int machine__nr_cpus_avail(struct machine *machine) +{ + return machine ? perf_env__nr_cpus_avail(machine->env) : 0; +} + int machine__get_kernel_start(struct machine *machine) { struct map *map = machine__kernel_map(machine); diff --git a/tools/perf/util/machine.h b/tools/perf/util/machine.h index fbc5133fb27c..245743d9ce63 100644 --- a/tools/perf/util/machine.h +++ b/tools/perf/util/machine.h @@ -170,6 +170,7 @@ static inline bool machine__is_host(struct machine *machine) } bool machine__is(struct machine *machine, const char *arch); +int machine__nr_cpus_avail(struct machine *machine); struct thread *__machine__findnew_thread(struct machine *machine, pid_t pid, pid_t tid); struct thread *machine__findnew_thread(struct machine *machine, pid_t pid, pid_t tid); -- GitLab From ce41e5fc90d4039907046e10b8d8dd7206ec36a4 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 21 Nov 2018 15:52:46 +0200 Subject: [PATCH 0046/1286] perf machine: Workaround missing maps for x86 PTI entry trampolines commit 4d99e4136580d178e3523281a820be17bf814bf8 upstream. On x86_64 the PTI entry trampolines are not in the kernel map created by perf tools. That results in the addresses having no symbols and prevents annotation. It also causes Intel PT to have decoding errors at the trampoline addresses. Workaround that by creating maps for the trampolines. At present the kernel does not export information revealing where the trampolines are. Until that happens, the addresses are hardcoded. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andy Lutomirski Cc: Dave Hansen Cc: H. Peter Anvin Cc: Jiri Olsa Cc: Joerg Roedel Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: x86@kernel.org Link: http://lkml.kernel.org/r/1526986485-6562-6-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/machine.c | 96 +++++++++++++++++++++++++++++++++++++++ tools/perf/util/machine.h | 3 ++ tools/perf/util/symbol.c | 12 +++-- 3 files changed, 106 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 78aa1c5f19ca..968fd0454e6b 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -818,6 +818,102 @@ static int machine__get_running_kernel_start(struct machine *machine, return 0; } +/* Kernel-space maps for symbols that are outside the main kernel map and module maps */ +struct extra_kernel_map { + u64 start; + u64 end; + u64 pgoff; +}; + +static int machine__create_extra_kernel_map(struct machine *machine, + struct dso *kernel, + struct extra_kernel_map *xm) +{ + struct kmap *kmap; + struct map *map; + + map = map__new2(xm->start, kernel, MAP__FUNCTION); + if (!map) + return -1; + + map->end = xm->end; + map->pgoff = xm->pgoff; + + kmap = map__kmap(map); + + kmap->kmaps = &machine->kmaps; + + map_groups__insert(&machine->kmaps, map); + + pr_debug2("Added extra kernel map %" PRIx64 "-%" PRIx64 "\n", + map->start, map->end); + + map__put(map); + + return 0; +} + +static u64 find_entry_trampoline(struct dso *dso) +{ + /* Duplicates are removed so lookup all aliases */ + const char *syms[] = { + "_entry_trampoline", + "__entry_trampoline_start", + "entry_SYSCALL_64_trampoline", + }; + struct symbol *sym = dso__first_symbol(dso, MAP__FUNCTION); + unsigned int i; + + for (; sym; sym = dso__next_symbol(sym)) { + if (sym->binding != STB_GLOBAL) + continue; + for (i = 0; i < ARRAY_SIZE(syms); i++) { + if (!strcmp(sym->name, syms[i])) + return sym->start; + } + } + + return 0; +} + +/* + * These values can be used for kernels that do not have symbols for the entry + * trampolines in kallsyms. + */ +#define X86_64_CPU_ENTRY_AREA_PER_CPU 0xfffffe0000000000ULL +#define X86_64_CPU_ENTRY_AREA_SIZE 0x2c000 +#define X86_64_ENTRY_TRAMPOLINE 0x6000 + +/* Map x86_64 PTI entry trampolines */ +int machine__map_x86_64_entry_trampolines(struct machine *machine, + struct dso *kernel) +{ + u64 pgoff = find_entry_trampoline(kernel); + int nr_cpus_avail, cpu; + + if (!pgoff) + return 0; + + nr_cpus_avail = machine__nr_cpus_avail(machine); + + /* Add a 1 page map for each CPU's entry trampoline */ + for (cpu = 0; cpu < nr_cpus_avail; cpu++) { + u64 va = X86_64_CPU_ENTRY_AREA_PER_CPU + + cpu * X86_64_CPU_ENTRY_AREA_SIZE + + X86_64_ENTRY_TRAMPOLINE; + struct extra_kernel_map xm = { + .start = va, + .end = va + page_size, + .pgoff = pgoff, + }; + + if (machine__create_extra_kernel_map(machine, kernel, &xm) < 0) + return -1; + } + + return 0; +} + int __machine__create_kernel_maps(struct machine *machine, struct dso *kernel) { int type; diff --git a/tools/perf/util/machine.h b/tools/perf/util/machine.h index 245743d9ce63..13041b036a5b 100644 --- a/tools/perf/util/machine.h +++ b/tools/perf/util/machine.h @@ -266,4 +266,7 @@ int machine__set_current_tid(struct machine *machine, int cpu, pid_t pid, */ char *machine__resolve_kernel_addr(void *vmachine, unsigned long long *addrp, char **modp); +int machine__map_x86_64_entry_trampolines(struct machine *machine, + struct dso *kernel); + #endif /* __PERF_MACHINE_H */ diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index ec40e47aa198..3936f69f385c 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -1513,20 +1513,22 @@ int dso__load(struct dso *dso, struct map *map) goto out; } + if (map->groups && map->groups->machine) + machine = map->groups->machine; + else + machine = NULL; + if (dso->kernel) { if (dso->kernel == DSO_TYPE_KERNEL) ret = dso__load_kernel_sym(dso, map); else if (dso->kernel == DSO_TYPE_GUEST_KERNEL) ret = dso__load_guest_kernel_sym(dso, map); + if (machine__is(machine, "x86_64")) + machine__map_x86_64_entry_trampolines(machine, dso); goto out; } - if (map->groups && map->groups->machine) - machine = map->groups->machine; - else - machine = NULL; - dso->adjust_symbols = 0; if (perfmap) { -- GitLab From 09917457494163dec35a74745ff04184385c8d32 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 21 Nov 2018 15:52:47 +0200 Subject: [PATCH 0047/1286] perf test code-reading: Fix perf_env setup for PTI entry trampolines commit f6c66d73bb8192d357bb5fb8cd5826920f811d8c upstream. The "Object code reading" test will not create maps for the PTI entry trampolines unless the machine environment exists to show that the arch is x86_64. Signed-off-by: Adrian Hunter Reported-by: Arnaldo Carvalho de Melo Tested-by: Arnaldo Carvalho de Melo Cc: Jiri Olsa Link: http://lkml.kernel.org/r/1528183800-21577-1-git-send-email-adrian.hunter@intel.com [ split from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/tests/code-reading.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index fcc8984bc329..acad8ba06d77 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -527,6 +527,7 @@ static int do_test_code_reading(bool try_kcore) pid = getpid(); machine = machine__new_host(); + machine->env = &perf_env; ret = machine__create_kernel_maps(machine); if (ret < 0) { -- GitLab From d412ab7cfc0de3c01befb5d32746eaf512929bde Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Fri, 26 Oct 2018 15:28:54 +0300 Subject: [PATCH 0048/1286] x86/mm: Move LDT remap out of KASLR region on 5-level paging commit d52888aa2753e3063a9d3a0c9f72f94aa9809c15 upstream On 5-level paging the LDT remap area is placed in the middle of the KASLR randomization region and it can overlap with the direct mapping, the vmalloc or the vmap area. The LDT mapping is per mm, so it cannot be moved into the P4D page table next to the CPU_ENTRY_AREA without complicating PGD table allocation for 5-level paging. The 4 PGD slot gap just before the direct mapping is reserved for hypervisors, so it cannot be used. Move the direct mapping one slot deeper and use the resulting gap for the LDT remap area. The resulting layout is the same for 4 and 5 level paging. [ tglx: Massaged changelog ] Fixes: f55f0501cbf6 ("x86/pti: Put the LDT in its own PGD if PTI is on") Signed-off-by: Kirill A. Shutemov Signed-off-by: Thomas Gleixner Reviewed-by: Andy Lutomirski Cc: bp@alien8.de Cc: hpa@zytor.com Cc: dave.hansen@linux.intel.com Cc: peterz@infradead.org Cc: boris.ostrovsky@oracle.com Cc: jgross@suse.com Cc: bhe@redhat.com Cc: willy@infradead.org Cc: linux-mm@kvack.org Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181026122856.66224-2-kirill.shutemov@linux.intel.com Signed-off-by: Sasha Levin --- Documentation/x86/x86_64/mm.txt | 10 ++++++---- arch/x86/include/asm/page_64_types.h | 12 +++++++----- arch/x86/include/asm/pgtable_64_types.h | 7 +++---- arch/x86/xen/mmu_pv.c | 6 +++--- 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt index ea91cb61a602..43f066cde67d 100644 --- a/Documentation/x86/x86_64/mm.txt +++ b/Documentation/x86/x86_64/mm.txt @@ -4,8 +4,9 @@ Virtual memory map with 4 level page tables: 0000000000000000 - 00007fffffffffff (=47 bits) user space, different per mm hole caused by [47:63] sign extension ffff800000000000 - ffff87ffffffffff (=43 bits) guard hole, reserved for hypervisor -ffff880000000000 - ffffc7ffffffffff (=64 TB) direct mapping of all phys. memory -ffffc80000000000 - ffffc8ffffffffff (=40 bits) hole +ffff880000000000 - ffff887fffffffff (=39 bits) LDT remap for PTI +ffff888000000000 - ffffc87fffffffff (=64 TB) direct mapping of all phys. memory +ffffc88000000000 - ffffc8ffffffffff (=39 bits) hole ffffc90000000000 - ffffe8ffffffffff (=45 bits) vmalloc/ioremap space ffffe90000000000 - ffffe9ffffffffff (=40 bits) hole ffffea0000000000 - ffffeaffffffffff (=40 bits) virtual memory map (1TB) @@ -30,8 +31,9 @@ Virtual memory map with 5 level page tables: 0000000000000000 - 00ffffffffffffff (=56 bits) user space, different per mm hole caused by [56:63] sign extension ff00000000000000 - ff0fffffffffffff (=52 bits) guard hole, reserved for hypervisor -ff10000000000000 - ff8fffffffffffff (=55 bits) direct mapping of all phys. memory -ff90000000000000 - ff9fffffffffffff (=52 bits) LDT remap for PTI +ff10000000000000 - ff10ffffffffffff (=48 bits) LDT remap for PTI +ff11000000000000 - ff90ffffffffffff (=55 bits) direct mapping of all phys. memory +ff91000000000000 - ff9fffffffffffff (=3840 TB) hole ffa0000000000000 - ffd1ffffffffffff (=54 bits) vmalloc/ioremap space (12800 TB) ffd2000000000000 - ffd3ffffffffffff (=49 bits) hole ffd4000000000000 - ffd5ffffffffffff (=49 bits) virtual memory map (512TB) diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h index e1407312c412..74d531f6d518 100644 --- a/arch/x86/include/asm/page_64_types.h +++ b/arch/x86/include/asm/page_64_types.h @@ -33,14 +33,16 @@ /* * Set __PAGE_OFFSET to the most negative possible address + - * PGDIR_SIZE*16 (pgd slot 272). The gap is to allow a space for a - * hypervisor to fit. Choosing 16 slots here is arbitrary, but it's - * what Xen requires. + * PGDIR_SIZE*17 (pgd slot 273). + * + * The gap is to allow a space for LDT remap for PTI (1 pgd slot) and space for + * a hypervisor (16 slots). Choosing 16 slots for a hypervisor is arbitrary, + * but it's what Xen requires. */ #ifdef CONFIG_X86_5LEVEL -#define __PAGE_OFFSET_BASE _AC(0xff10000000000000, UL) +#define __PAGE_OFFSET_BASE _AC(0xff11000000000000, UL) #else -#define __PAGE_OFFSET_BASE _AC(0xffff880000000000, UL) +#define __PAGE_OFFSET_BASE _AC(0xffff888000000000, UL) #endif #ifdef CONFIG_RANDOMIZE_MEMORY diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 6b8f73dcbc2c..7764617b8f9c 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -88,16 +88,15 @@ typedef struct { pteval_t pte; } pte_t; # define VMALLOC_SIZE_TB _AC(12800, UL) # define __VMALLOC_BASE _AC(0xffa0000000000000, UL) # define __VMEMMAP_BASE _AC(0xffd4000000000000, UL) -# define LDT_PGD_ENTRY _AC(-112, UL) -# define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT) #else # define VMALLOC_SIZE_TB _AC(32, UL) # define __VMALLOC_BASE _AC(0xffffc90000000000, UL) # define __VMEMMAP_BASE _AC(0xffffea0000000000, UL) -# define LDT_PGD_ENTRY _AC(-3, UL) -# define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT) #endif +#define LDT_PGD_ENTRY -240UL +#define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT) + #ifdef CONFIG_RANDOMIZE_MEMORY # define VMALLOC_START vmalloc_base # define VMEMMAP_START vmemmap_base diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 8ed11a5b1a9d..b33fa127a613 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -1869,7 +1869,7 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn) init_top_pgt[0] = __pgd(0); /* Pre-constructed entries are in pfn, so convert to mfn */ - /* L4[272] -> level3_ident_pgt */ + /* L4[273] -> level3_ident_pgt */ /* L4[511] -> level3_kernel_pgt */ convert_pfn_mfn(init_top_pgt); @@ -1889,8 +1889,8 @@ void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn) addr[0] = (unsigned long)pgd; addr[1] = (unsigned long)l3; addr[2] = (unsigned long)l2; - /* Graft it onto L4[272][0]. Note that we creating an aliasing problem: - * Both L4[272][0] and L4[511][510] have entries that point to the same + /* Graft it onto L4[273][0]. Note that we creating an aliasing problem: + * Both L4[273][0] and L4[511][510] have entries that point to the same * L2 (PMD) tables. Meaning that if you modify it in __va space * it will be also modified in the __ka space! (But if you just * modify the PMD table to point to other PTE's or none, then you -- GitLab From a17989cb9bb03c75bb57dddc0f044100fd4d856e Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Fri, 26 Oct 2018 15:28:55 +0300 Subject: [PATCH 0049/1286] x86/ldt: Unmap PTEs for the slot before freeing LDT pages commit a0e6e0831c516860fc7f9be1db6c081fe902ebcf upstream modify_ldt(2) leaves the old LDT mapped after switching over to the new one. The old LDT gets freed and the pages can be re-used. Leaving the mapping in place can have security implications. The mapping is present in the userspace page tables and Meltdown-like attacks can read these freed and possibly reused pages. It's relatively simple to fix: unmap the old LDT and flush TLB before freeing the old LDT memory. This further allows to avoid flushing the TLB in map_ldt_struct() as the slot is unmapped and flushed by unmap_ldt_struct() or has never been mapped at all. [ tglx: Massaged changelog and removed the needless line breaks ] Fixes: f55f0501cbf6 ("x86/pti: Put the LDT in its own PGD if PTI is on") Signed-off-by: Kirill A. Shutemov Signed-off-by: Thomas Gleixner Cc: bp@alien8.de Cc: hpa@zytor.com Cc: dave.hansen@linux.intel.com Cc: luto@kernel.org Cc: peterz@infradead.org Cc: boris.ostrovsky@oracle.com Cc: jgross@suse.com Cc: bhe@redhat.com Cc: willy@infradead.org Cc: linux-mm@kvack.org Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181026122856.66224-3-kirill.shutemov@linux.intel.com Signed-off-by: Sasha Levin --- arch/x86/kernel/ldt.c | 49 +++++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c index 26d713ecad34..65df298d4e9e 100644 --- a/arch/x86/kernel/ldt.c +++ b/arch/x86/kernel/ldt.c @@ -103,14 +103,6 @@ static struct ldt_struct *alloc_ldt_struct(unsigned int num_entries) /* * If PTI is enabled, this maps the LDT into the kernelmode and * usermode tables for the given mm. - * - * There is no corresponding unmap function. Even if the LDT is freed, we - * leave the PTEs around until the slot is reused or the mm is destroyed. - * This is harmless: the LDT is always in ordinary memory, and no one will - * access the freed slot. - * - * If we wanted to unmap freed LDTs, we'd also need to do a flush to make - * it useful, and the flush would slow down modify_ldt(). */ static int map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot) @@ -119,8 +111,8 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot) bool is_vmalloc, had_top_level_entry; unsigned long va; spinlock_t *ptl; + int i, nr_pages; pgd_t *pgd; - int i; if (!static_cpu_has(X86_FEATURE_PTI)) return 0; @@ -141,7 +133,9 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot) is_vmalloc = is_vmalloc_addr(ldt->entries); - for (i = 0; i * PAGE_SIZE < ldt->nr_entries * LDT_ENTRY_SIZE; i++) { + nr_pages = DIV_ROUND_UP(ldt->nr_entries * LDT_ENTRY_SIZE, PAGE_SIZE); + + for (i = 0; i < nr_pages; i++) { unsigned long offset = i << PAGE_SHIFT; const void *src = (char *)ldt->entries + offset; unsigned long pfn; @@ -189,14 +183,42 @@ map_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt, int slot) } } - va = (unsigned long)ldt_slot_va(slot); - flush_tlb_mm_range(mm, va, va + LDT_SLOT_STRIDE, 0); - ldt->slot = slot; #endif return 0; } +static void unmap_ldt_struct(struct mm_struct *mm, struct ldt_struct *ldt) +{ +#ifdef CONFIG_PAGE_TABLE_ISOLATION + unsigned long va; + int i, nr_pages; + + if (!ldt) + return; + + /* LDT map/unmap is only required for PTI */ + if (!static_cpu_has(X86_FEATURE_PTI)) + return; + + nr_pages = DIV_ROUND_UP(ldt->nr_entries * LDT_ENTRY_SIZE, PAGE_SIZE); + + for (i = 0; i < nr_pages; i++) { + unsigned long offset = i << PAGE_SHIFT; + spinlock_t *ptl; + pte_t *ptep; + + va = (unsigned long)ldt_slot_va(ldt->slot) + offset; + ptep = get_locked_pte(mm, va, &ptl); + pte_clear(mm, va, ptep); + pte_unmap_unlock(ptep, ptl); + } + + va = (unsigned long)ldt_slot_va(ldt->slot); + flush_tlb_mm_range(mm, va, va + nr_pages * PAGE_SIZE, 0); +#endif /* CONFIG_PAGE_TABLE_ISOLATION */ +} + static void free_ldt_pgtables(struct mm_struct *mm) { #ifdef CONFIG_PAGE_TABLE_ISOLATION @@ -433,6 +455,7 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode) } install_ldt(mm, new_ldt); + unmap_ldt_struct(mm, old_ldt); free_ldt_struct(old_ldt); error = 0; -- GitLab From 817266cb8d45b74a695fb8a27e12b17cf087d7b1 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 5 Nov 2018 09:35:44 -0500 Subject: [PATCH 0050/1286] media: v4l: event: Add subscription to list before calling "add" operation commit 92539d3eda2c090b382699bbb896d4b54e9bdece upstream. Patch ad608fbcf166 changed how events were subscribed to address an issue elsewhere. As a side effect of that change, the "add" callback was called before the event subscription was added to the list of subscribed events, causing the first event queued by the add callback (and possibly other events arriving soon afterwards) to be lost. Fix this by adding the subscription to the list before calling the "add" callback, and clean up afterwards if that fails. Fixes: ad608fbcf166 ("media: v4l: event: Prevent freeing event subscriptions while accessed") Reported-by: Dave Stevenson Signed-off-by: Sakari Ailus Tested-by: Dave Stevenson Reviewed-by: Hans Verkuil Tested-by: Hans Verkuil Cc: stable@vger.kernel.org (for 4.14 and up) Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Greg Kroah-Hartman --- drivers/media/v4l2-core/v4l2-event.c | 43 ++++++++++++++++------------ 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-event.c b/drivers/media/v4l2-core/v4l2-event.c index 568dd4affb33..011907eff660 100644 --- a/drivers/media/v4l2-core/v4l2-event.c +++ b/drivers/media/v4l2-core/v4l2-event.c @@ -193,6 +193,22 @@ int v4l2_event_pending(struct v4l2_fh *fh) } EXPORT_SYMBOL_GPL(v4l2_event_pending); +static void __v4l2_event_unsubscribe(struct v4l2_subscribed_event *sev) +{ + struct v4l2_fh *fh = sev->fh; + unsigned int i; + + lockdep_assert_held(&fh->subscribe_lock); + assert_spin_locked(&fh->vdev->fh_lock); + + /* Remove any pending events for this subscription */ + for (i = 0; i < sev->in_use; i++) { + list_del(&sev->events[sev_pos(sev, i)].list); + fh->navailable--; + } + list_del(&sev->list); +} + int v4l2_event_subscribe(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub, unsigned elems, const struct v4l2_subscribed_event_ops *ops) @@ -225,27 +241,23 @@ int v4l2_event_subscribe(struct v4l2_fh *fh, spin_lock_irqsave(&fh->vdev->fh_lock, flags); found_ev = v4l2_event_subscribed(fh, sub->type, sub->id); + if (!found_ev) + list_add(&sev->list, &fh->subscribed); spin_unlock_irqrestore(&fh->vdev->fh_lock, flags); if (found_ev) { /* Already listening */ kvfree(sev); - goto out_unlock; - } - - if (sev->ops && sev->ops->add) { + } else if (sev->ops && sev->ops->add) { ret = sev->ops->add(sev, elems); if (ret) { + spin_lock_irqsave(&fh->vdev->fh_lock, flags); + __v4l2_event_unsubscribe(sev); + spin_unlock_irqrestore(&fh->vdev->fh_lock, flags); kvfree(sev); - goto out_unlock; } } - spin_lock_irqsave(&fh->vdev->fh_lock, flags); - list_add(&sev->list, &fh->subscribed); - spin_unlock_irqrestore(&fh->vdev->fh_lock, flags); - -out_unlock: mutex_unlock(&fh->subscribe_lock); return ret; @@ -280,7 +292,6 @@ int v4l2_event_unsubscribe(struct v4l2_fh *fh, { struct v4l2_subscribed_event *sev; unsigned long flags; - int i; if (sub->type == V4L2_EVENT_ALL) { v4l2_event_unsubscribe_all(fh); @@ -292,14 +303,8 @@ int v4l2_event_unsubscribe(struct v4l2_fh *fh, spin_lock_irqsave(&fh->vdev->fh_lock, flags); sev = v4l2_event_subscribed(fh, sub->type, sub->id); - if (sev != NULL) { - /* Remove any pending events for this subscription */ - for (i = 0; i < sev->in_use; i++) { - list_del(&sev->events[sev_pos(sev, i)].list); - fh->navailable--; - } - list_del(&sev->list); - } + if (sev != NULL) + __v4l2_event_unsubscribe(sev); spin_unlock_irqrestore(&fh->vdev->fh_lock, flags); -- GitLab From 2fc77700daa9f2faf7e61f46c1d784fd85867dfc Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 11 Nov 2018 00:06:12 +0200 Subject: [PATCH 0051/1286] MIPS: OCTEON: cavium_octeon_defconfig: re-enable OCTEON USB driver commit 82fba2df7f7c019627f24c5036dc99f41731d770 upstream. Re-enable OCTEON USB driver which is needed on older hardware (e.g. EdgeRouter Lite) for mass storage etc. This got accidentally deleted when config options were changed for OCTEON2/3 USB. Signed-off-by: Aaro Koskinen Signed-off-by: Paul Burton Fixes: f922bc0ad08b ("MIPS: Octeon: cavium_octeon_defconfig: Enable more drivers") Patchwork: https://patchwork.linux-mips.org/patch/21077/ Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # 4.14+ Signed-off-by: Greg Kroah-Hartman --- arch/mips/configs/cavium_octeon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 490b12af103c..c52d0efacd14 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -140,6 +140,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_STAGING=y CONFIG_OCTEON_ETHERNET=y +CONFIG_OCTEON_USB=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_RAS=y CONFIG_EXT4_FS=y -- GitLab From f6a6ae4e0f345aa481535bfe2046cd33f4dc37b8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 26 Oct 2018 10:19:51 +0300 Subject: [PATCH 0052/1286] uio: Fix an Oops on load commit 432798195bbce1f8cd33d1c0284d0538835e25fb upstream. I was trying to solve a double free but I introduced a more serious NULL dereference bug. The problem is that if there is an IRQ which triggers immediately, then we need "info->uio_dev" but it's not set yet. This patch puts the original initialization back to how it was and just sets info->uio_dev to NULL on the error path so it should solve both the Oops and the double free. Fixes: f019f07ecf6a ("uio: potential double frees if __uio_register_device() fails") Reported-by: Mathias Thore Signed-off-by: Dan Carpenter Cc: stable Tested-by: Mathias Thore Signed-off-by: Greg Kroah-Hartman --- drivers/uio/uio.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index 0a730136646d..654579bc1e54 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c @@ -850,6 +850,8 @@ int __uio_register_device(struct module *owner, if (ret) goto err_uio_dev_add_attributes; + info->uio_dev = idev; + if (info->irq && (info->irq != UIO_IRQ_CUSTOM)) { /* * Note that we deliberately don't use devm_request_irq @@ -861,11 +863,12 @@ int __uio_register_device(struct module *owner, */ ret = request_irq(info->irq, uio_interrupt, info->irq_flags, info->name, idev); - if (ret) + if (ret) { + info->uio_dev = NULL; goto err_request_irq; + } } - info->uio_dev = idev; return 0; err_request_irq: -- GitLab From 578f05a757bf76e828fe244994436947187bcfe3 Mon Sep 17 00:00:00 2001 From: Maarten Jacobs Date: Mon, 19 Nov 2018 23:18:49 +0000 Subject: [PATCH 0053/1286] usb: cdc-acm: add entry for Hiro (Conexant) modem commit 63529eaa6164ef7ab4b907b25ac3648177e5e78f upstream. The cdc-acm kernel module currently does not support the Hiro (Conexant) H05228 USB modem. The patch below adds the device specific information: idVendor 0x0572 idProduct 0x1349 Signed-off-by: Maarten Jacobs Acked-by: Oliver Neukum Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/class/cdc-acm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index e41d00bc7e97..5a8ef83a5c5c 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -1724,6 +1724,9 @@ static const struct usb_device_id acm_ids[] = { { USB_DEVICE(0x0572, 0x1328), /* Shiro / Aztech USB MODEM UM-3100 */ .driver_info = NO_UNION_NORMAL, /* has no union descriptor */ }, + { USB_DEVICE(0x0572, 0x1349), /* Hiro (Conexant) USB MODEM H50228 */ + .driver_info = NO_UNION_NORMAL, /* has no union descriptor */ + }, { USB_DEVICE(0x20df, 0x0001), /* Simtec Electronics Entropy Key */ .driver_info = QUIRK_CONTROL_LINE_STATE, }, { USB_DEVICE(0x2184, 0x001c) }, /* GW Instek AFG-2225 */ -- GitLab From d7385bcf1887642ac0f0c7c6b82efc0d3c3c5f45 Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Fri, 26 Oct 2018 13:33:15 +0800 Subject: [PATCH 0054/1286] USB: quirks: Add no-lpm quirk for Raydium touchscreens commit deefd24228a172d1b27d4a9adbfd2cdacd60ae64 upstream. Raydium USB touchscreen fails to set config if LPM is enabled: [ 2.030658] usb 1-8: New USB device found, idVendor=2386, idProduct=3119 [ 2.030659] usb 1-8: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 2.030660] usb 1-8: Product: Raydium Touch System [ 2.030661] usb 1-8: Manufacturer: Raydium Corporation [ 7.132209] usb 1-8: can't set config #1, error -110 Same behavior can be observed on 2386:3114. Raydium claims the touchscreen supports LPM under Windows, so I used Microsoft USB Test Tools (MUTT) [1] to check its LPM status. MUTT shows that the LPM doesn't work under Windows, either. So let's just disable LPM for Raydium touchscreens. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-test-tools Signed-off-by: Kai-Heng Feng Cc: stable Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 37a5e07b3488..dc753a8b2418 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -263,6 +263,11 @@ static const struct usb_device_id usb_quirk_list[] = { { USB_DEVICE(0x2040, 0x7200), .driver_info = USB_QUIRK_CONFIG_INTF_STRINGS }, + /* Raydium Touchscreen */ + { USB_DEVICE(0x2386, 0x3114), .driver_info = USB_QUIRK_NO_LPM }, + + { USB_DEVICE(0x2386, 0x3119), .driver_info = USB_QUIRK_NO_LPM }, + /* DJI CineSSD */ { USB_DEVICE(0x2ca3, 0x0031), .driver_info = USB_QUIRK_NO_LPM }, -- GitLab From 041fa1f61997142e52331eee0eba84ffdbf85bd2 Mon Sep 17 00:00:00 2001 From: Emmanuel Pescosta Date: Fri, 26 Oct 2018 14:48:09 +0200 Subject: [PATCH 0055/1286] usb: quirks: Add delay-init quirk for Corsair K70 LUX RGB commit a77112577667cbda7c6292c52d909636aef31fd9 upstream. Following on from this patch: https://lkml.org/lkml/2017/11/3/516, Corsair K70 LUX RGB keyboards also require the DELAY_INIT quirk to start correctly at boot. Dmesg output: usb 1-6: string descriptor 0 read error: -110 usb 1-6: New USB device found, idVendor=1b1c, idProduct=1b33 usb 1-6: New USB device strings: Mfr=1, Product=2, SerialNumber=3 usb 1-6: can't set config #1, error -110 Signed-off-by: Emmanuel Pescosta Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index dc753a8b2418..1e8f68960014 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -243,6 +243,9 @@ static const struct usb_device_id usb_quirk_list[] = { { USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT | USB_QUIRK_DELAY_CTRL_MSG }, + /* Corsair K70 LUX RGB */ + { USB_DEVICE(0x1b1c, 0x1b33), .driver_info = USB_QUIRK_DELAY_INIT }, + /* Corsair K70 LUX */ { USB_DEVICE(0x1b1c, 0x1b36), .driver_info = USB_QUIRK_DELAY_INIT }, -- GitLab From 939936e6015d007f6ef2e344f5e2ec809074c987 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 17 Oct 2018 10:09:02 -0700 Subject: [PATCH 0056/1286] misc: atmel-ssc: Fix section annotation on atmel_ssc_get_driver_data commit 7c97301285b62a41d6bceded7d964085fc8cc50f upstream. After building the kernel with Clang, the following section mismatch warning appears: WARNING: vmlinux.o(.text+0x3bf19a6): Section mismatch in reference from the function ssc_probe() to the function .init.text:atmel_ssc_get_driver_data() The function ssc_probe() references the function __init atmel_ssc_get_driver_data(). This is often because ssc_probe lacks a __init annotation or the annotation of atmel_ssc_get_driver_data is wrong. Remove __init from atmel_ssc_get_driver_data to get rid of the mismatch. Signed-off-by: Nathan Chancellor Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/misc/atmel-ssc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c index b2a0340f277e..d8e3cc2dc747 100644 --- a/drivers/misc/atmel-ssc.c +++ b/drivers/misc/atmel-ssc.c @@ -132,7 +132,7 @@ static const struct of_device_id atmel_ssc_dt_ids[] = { MODULE_DEVICE_TABLE(of, atmel_ssc_dt_ids); #endif -static inline const struct atmel_ssc_platform_data * __init +static inline const struct atmel_ssc_platform_data * atmel_ssc_get_driver_data(struct platform_device *pdev) { if (pdev->dev.of_node) { -- GitLab From fb37c765e28d778f53c66c7727254f8ac2f047ea Mon Sep 17 00:00:00 2001 From: Mattias Jacobsson <2pi@mok.nu> Date: Sun, 21 Oct 2018 11:25:37 +0200 Subject: [PATCH 0057/1286] USB: misc: appledisplay: add 20" Apple Cinema Display commit f6501f49199097b99e4e263644d88c90d1ec1060 upstream. Add another Apple Cinema Display to the list of supported displays Signed-off-by: Mattias Jacobsson <2pi@mok.nu> Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/misc/appledisplay.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/misc/appledisplay.c b/drivers/usb/misc/appledisplay.c index 8efdc500e790..288fe3e69d52 100644 --- a/drivers/usb/misc/appledisplay.c +++ b/drivers/usb/misc/appledisplay.c @@ -63,6 +63,7 @@ static const struct usb_device_id appledisplay_table[] = { { APPLEDISPLAY_DEVICE(0x9219) }, { APPLEDISPLAY_DEVICE(0x921c) }, { APPLEDISPLAY_DEVICE(0x921d) }, + { APPLEDISPLAY_DEVICE(0x9222) }, { APPLEDISPLAY_DEVICE(0x9236) }, /* Terminating entry */ -- GitLab From 16c233b9b6c8758207f0079737bf36bda9cd9094 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Tue, 16 Oct 2018 12:59:44 +0200 Subject: [PATCH 0058/1286] drivers/misc/sgi-gru: fix Spectre v1 vulnerability commit fee05f455ceb5c670cbe48e2f9454ebc4a388554 upstream. req.gid can be indirectly controlled by user-space, hence leading to a potential exploitation of the Spectre variant 1 vulnerability. This issue was detected with the help of Smatch: vers/misc/sgi-gru/grukdump.c:200 gru_dump_chiplet_request() warn: potential spectre issue 'gru_base' [w] Fix this by sanitizing req.gid before calling macro GID_TO_GRU, which uses it to index gru_base. Notice that given that speculation windows are large, the policy is to kill the speculation on the first load and not worry if it can be completed with a dependent load/store [1]. [1] https://marc.info/?l=linux-kernel&m=152449131114778&w=2 Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva Signed-off-by: Greg Kroah-Hartman --- drivers/misc/sgi-gru/grukdump.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/sgi-gru/grukdump.c b/drivers/misc/sgi-gru/grukdump.c index 313da3150262..1540a7785e14 100644 --- a/drivers/misc/sgi-gru/grukdump.c +++ b/drivers/misc/sgi-gru/grukdump.c @@ -27,6 +27,9 @@ #include #include #include + +#include + #include "gru.h" #include "grutables.h" #include "gruhandles.h" @@ -196,6 +199,7 @@ int gru_dump_chiplet_request(unsigned long arg) /* Currently, only dump by gid is implemented */ if (req.gid >= gru_max_gids) return -EINVAL; + req.gid = array_index_nospec(req.gid, gru_max_gids); gru = GID_TO_GRU(req.gid); ubuf = req.buf; -- GitLab From 3cf1a2b4e0b3eae21abd25d535142e7b6ac3209c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 19 Nov 2018 19:06:01 +0100 Subject: [PATCH 0059/1286] ACPI / platform: Add SMB0001 HID to forbidden_id_list commit 2bbb5fa37475d7aa5fa62f34db1623f3da2dfdfa upstream. Many HP AMD based laptops contain an SMB0001 device like this: Device (SMBD) { Name (_HID, "SMB0001") // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0B20, // Range Minimum 0x0B20, // Range Maximum 0x20, // Alignment 0x20, // Length ) IRQ (Level, ActiveLow, Shared, ) {7} }) } The legacy style IRQ resource here causes acpi_dev_get_irqresource() to be called with legacy=true and this message to show in dmesg: ACPI: IRQ 7 override to edge, high This causes issues when later on the AMD0030 GPIO device gets enumerated: Device (GPIO) { Name (_HID, "AMDI0030") // _HID: Hardware ID Name (_CID, "AMDI0030") // _CID: Compatible ID Name (_UID, Zero) // _UID: Unique ID Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (RBUF, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { 0x00000007, } Memory32Fixed (ReadWrite, 0xFED81500, // Address Base 0x00000400, // Address Length ) }) Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */ } } Now acpi_dev_get_irqresource() gets called with legacy=false, but because of the earlier override of the trigger-type acpi_register_gsi() returns -EBUSY (because we try to register the same interrupt with a different trigger-type) and we end up setting IORESOURCE_DISABLED in the flags. The setting of IORESOURCE_DISABLED causes platform_get_irq() to call acpi_irq_get() which is not implemented on x86 and returns -EINVAL. resulting in the following in dmesg: amd_gpio AMDI0030:00: Failed to get gpio IRQ: -22 amd_gpio: probe of AMDI0030:00 failed with error -22 The SMB0001 is a "virtual" device in the sense that the only way the OS interacts with it is through calling a couple of methods to do SMBus transfers. As such it is weird that it has IO and IRQ resources at all, because the driver for it is not expected to ever access the hardware directly. The Linux driver for the SMB0001 device directly binds to the acpi_device through the acpi_bus, so we do not need to instantiate a platform_device for this ACPI device. This commit adds the SMB0001 HID to the forbidden_id_list, avoiding the instantiating of a platform_device for it. Not instantiating a platform_device means we will no longer call acpi_dev_get_irqresource() for the legacy IRQ resource fixing the probe of the AMDI0030 device failing. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1644013 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=198715 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199523 Reported-by: Lukas Kahnert Tested-by: Marc Cc: All applicable Signed-off-by: Hans de Goede Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/acpi/acpi_platform.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_platform.c b/drivers/acpi/acpi_platform.c index 88cd949003f3..ecd84d910ed2 100644 --- a/drivers/acpi/acpi_platform.c +++ b/drivers/acpi/acpi_platform.c @@ -30,6 +30,7 @@ static const struct acpi_device_id forbidden_id_list[] = { {"PNP0200", 0}, /* AT DMA Controller */ {"ACPI0009", 0}, /* IOxAPIC */ {"ACPI000A", 0}, /* IOAPIC */ + {"SMB0001", 0}, /* ACPI SMBUS virtual device */ {"", 0}, }; -- GitLab From 540f89376ba2949f53ed6f057fea321be848cd43 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Wed, 14 Nov 2018 13:55:09 -0800 Subject: [PATCH 0060/1286] HID: uhid: forbid UHID_CREATE under KERNEL_DS or elevated privileges commit 8c01db7619f07c85c5cd81ec5eb83608b56c88f5 upstream. When a UHID_CREATE command is written to the uhid char device, a copy_from_user() is done from a user pointer embedded in the command. When the address limit is KERNEL_DS, e.g. as is the case during sys_sendfile(), this can read from kernel memory. Alternatively, information can be leaked from a setuid binary that is tricked to write to the file descriptor. Therefore, forbid UHID_CREATE in these cases. No other commands in uhid_char_write() are affected by this bug and UHID_CREATE is marked as "obsolete", so apply the restriction to UHID_CREATE only rather than to uhid_char_write() entirely. Thanks to Dmitry Vyukov for adding uhid definitions to syzkaller and to Jann Horn for commit 9da3f2b740544 ("x86/fault: BUG() when uaccess helpers fault on kernel addresses"), allowing this bug to be found. Reported-by: syzbot+72473edc9bf4eb1c6556@syzkaller.appspotmail.com Fixes: d365c6cfd337 ("HID: uhid: add UHID_CREATE and UHID_DESTROY events") Cc: # v3.6+ Cc: Jann Horn Cc: Andy Lutomirski Signed-off-by: Eric Biggers Reviewed-by: Jann Horn Signed-off-by: Jiri Kosina Signed-off-by: Greg Kroah-Hartman --- drivers/hid/uhid.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c index 6f819f144cb4..6f67d73b184e 100644 --- a/drivers/hid/uhid.c +++ b/drivers/hid/uhid.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -722,6 +723,17 @@ static ssize_t uhid_char_write(struct file *file, const char __user *buffer, switch (uhid->input_buf.type) { case UHID_CREATE: + /* + * 'struct uhid_create_req' contains a __user pointer which is + * copied from, so it's unsafe to allow this with elevated + * privileges (e.g. from a setuid binary) or via kernel_write(). + */ + if (file->f_cred != current_cred() || uaccess_kernel()) { + pr_err_once("UHID_CREATE from different security context by process %d (%s), this is not allowed.\n", + task_tgid_vnr(current), current->comm); + ret = -EACCES; + goto unlock; + } ret = uhid_dev_create(uhid, &uhid->input_buf); break; case UHID_CREATE2: -- GitLab From 3c7f1671af5f1bef6fac4e9ad7416e7a5a4ed295 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Thu, 8 Nov 2018 15:55:37 +0100 Subject: [PATCH 0061/1286] libceph: fall back to sendmsg for slab pages commit 7e241f647dc7087a0401418a187f3f5b527cc690 upstream. skb_can_coalesce() allows coalescing neighboring slab objects into a single frag: return page == skb_frag_page(frag) && off == frag->page_offset + skb_frag_size(frag); ceph_tcp_sendpage() can be handed slab pages. One example of this is XFS: it passes down sector sized slab objects for its metadata I/O. If the kernel client is co-located on the OSD node, the skb may go through loopback and pop on the receive side with the exact same set of frags. When tcp_recvmsg() attempts to copy out such a frag, hardened usercopy complains because the size exceeds the object's allocated size: usercopy: kernel memory exposure attempt detected from ffff9ba917f20a00 (kmalloc-512) (1024 bytes) Although skb_can_coalesce() could be taught to return false if the resulting frag would cross a slab object boundary, we already have a fallback for non-refcounted pages. Utilize it for slab pages too. Cc: stable@vger.kernel.org # 4.8+ Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- net/ceph/messenger.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 5c4e85296cf6..5281da82371a 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -594,9 +594,15 @@ static int ceph_tcp_sendpage(struct socket *sock, struct page *page, struct bio_vec bvec; int ret; - /* sendpage cannot properly handle pages with page_count == 0, - * we need to fallback to sendmsg if that's the case */ - if (page_count(page) >= 1) + /* + * sendpage cannot properly handle pages with page_count == 0, + * we need to fall back to sendmsg if that's the case. + * + * Same goes for slab pages: skb_can_coalesce() allows + * coalescing neighboring slab objects into a single frag which + * triggers one of hardened usercopy checks. + */ + if (page_count(page) >= 1 && !PageSlab(page)) return __ceph_tcp_sendpage(sock, page, offset, size, more); bvec.bv_page = page; -- GitLab From 4201a586f1fa63de5a965a1ebc3b99e0e1a4912c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 27 Nov 2018 16:10:52 +0100 Subject: [PATCH 0062/1286] Linux 4.14.84 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0f42814095a4..874d72a3e6a7 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 83 +SUBLEVEL = 84 EXTRAVERSION = NAME = Petit Gorille -- GitLab From dca7c1aaa67e49cf7ae1a4a8afb81212e68ebc40 Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Wed, 28 Nov 2018 17:56:13 -0800 Subject: [PATCH 0063/1286] defconfig: sdxprairie: Enable Lazy mapping for sdxprairie Enable Lazy mapping to support reference counted iommu-mapping support for ION buffers. Change-Id: I8960960785192855182d4436656a5ec96b172cc4 Signed-off-by: Swathi Sridhar --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 8966e61074f7..307e5341b5ec 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -287,6 +287,7 @@ CONFIG_QCOM_APCS_IPC=y CONFIG_MSM_QMP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 888546219c2e..a4554ebe4e6b 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -277,6 +277,7 @@ CONFIG_QCOM_APCS_IPC=y CONFIG_MSM_QMP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y -- GitLab From 20df7a2eb6c8241775518f032c49139835ce07f1 Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Wed, 21 Nov 2018 15:10:20 -0800 Subject: [PATCH 0064/1286] defconfig: sdxprairie: enable CONFIG_QCOM_SECURE_BUFFER Enable CONFIG_QCOM_SECURE_BUFFER for sdxprairie to enable secure ION allocations. Change-Id: I9226472d495543760b5bd147ff0a2f2378604d8d Signed-off-by: Swathi Sridhar --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 307e5341b5ec..424fd1a6e1a9 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -305,6 +305,7 @@ CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y +CONFIG_QCOM_SECURE_BUFFER=y CONFIG_QCOM_BUS_SCALING=y CONFIG_QCOM_BUS_CONFIG_RPMH=y CONFIG_QCOM_COMMAND_DB=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index a4554ebe4e6b..d5aaf2d1ec06 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -296,6 +296,7 @@ CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_SECURE_BUFFER=y CONFIG_QCOM_BUS_SCALING=y CONFIG_QCOM_BUS_CONFIG_RPMH=y CONFIG_QCOM_COMMAND_DB=y -- GitLab From 7625cb31bf3e177f04d73bcd99d99e6a1e36b75d Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Thu, 29 Mar 2018 17:34:28 +0800 Subject: [PATCH 0065/1286] pinctrl: qcom: Add syscore system suspend/resume Add syscore system suspend and resume handlers, to print gpio interrupts status during device resume. Change-Id: I7c574d2e44a7e318ac9ef89063d2081bf63c09b6 Signed-off-by: Prasad Sodagudi Signed-off-by: Maria Yu Signed-off-by: Tengfei Fan --- drivers/pinctrl/qcom/pinctrl-msm.c | 49 ++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 6 ++++ 2 files changed, 55 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index b25503a13c6e..475f2646ec8b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -1771,6 +1772,52 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) } } +#ifdef CONFIG_PM +static int msm_pinctrl_suspend(void) +{ + return 0; +} + +static void msm_pinctrl_resume(void) +{ + int i, irq; + u32 val; + unsigned long flags; + struct irq_desc *desc; + const struct msm_pingroup *g; + const char *name = "null"; + struct msm_pinctrl *pctrl = msm_pinctrl_data; + + if (!msm_show_resume_irq_mask) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = readl_relaxed(pctrl->regs + g->intr_status_reg); + if (val & BIT(g->intr_status_bit)) { + irq = irq_find_mapping(pctrl->chip.irqdomain, i); + desc = irq_to_desc(irq); + if (desc == NULL) + name = "stray irq"; + else if (desc->action && desc->action->name) + name = desc->action->name; + + pr_warn("%s: %d triggered %s\n", __func__, irq, name); + } + } + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} +#else +#define msm_pinctrl_suspend NULL +#define msm_pinctrl_resume NULL +#endif + +static struct syscore_ops msm_pinctrl_pm_ops = { + .suspend = msm_pinctrl_suspend, + .resume = msm_pinctrl_resume, +}; + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { @@ -1846,6 +1893,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, platform_set_drvdata(pdev, pctrl); + register_syscore_ops(&msm_pinctrl_pm_ops); dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); return 0; @@ -1859,6 +1907,7 @@ int msm_pinctrl_remove(struct platform_device *pdev) gpiochip_remove(&pctrl->chip); unregister_restart_handler(&pctrl->restart_nb); + unregister_syscore_ops(&msm_pinctrl_pm_ops); return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index fefd9a9b18f0..4602e450c82c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -190,4 +190,10 @@ int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); +#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ +extern int msm_show_resume_irq_mask; +#else +#define msm_show_resume_irq_mask 0 +#endif + #endif -- GitLab From ed482390c8dbf51484bfe69d0f4952cf29a4dc6b Mon Sep 17 00:00:00 2001 From: Alistair Strachan Date: Tue, 27 Nov 2018 15:33:17 -0800 Subject: [PATCH 0066/1286] efi/libstub: arm: support building with clang (commit 41f1c48420709470c51ee0e54b6fb28b956bb4e0 upstream) When building with CONFIG_EFI and CONFIG_EFI_STUB on ARM, the libstub Makefile would use -mno-single-pic-base without checking it was supported by the compiler. As the ARM (32-bit) clang backend does not support this flag, the build would fail. This changes the Makefile to check the compiler's support for -mno-single-pic-base before using it, similar to c1c386681bd7 ("ARM: 8767/1: add support for building ARM kernel with clang"). Signed-off-by: Alistair Strachan Reviewed-by: Stefan Agner Signed-off-by: Ard Biesheuvel [ND: adjusted due to missing commit ce279d374ff3 ("efi/libstub: Only disable stackleak plugin for arm64")] Signed-off-by: Nick Desaulniers Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/efi/libstub/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index adaa4a964f0c..678bc910e080 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -13,7 +13,8 @@ cflags-$(CONFIG_X86) += -m$(BITS) -D__KERNEL__ -O2 \ cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS)) -fpie cflags-$(CONFIG_ARM) := $(subst -pg,,$(KBUILD_CFLAGS)) \ - -fno-builtin -fpic -mno-single-pic-base + -fno-builtin -fpic \ + $(call cc-option,-mno-single-pic-base) cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt -- GitLab From f1222c5f7f6036cbab74abefdbce0bffe85d3eea Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 8 May 2018 22:49:49 +0100 Subject: [PATCH 0067/1286] ARM: 8766/1: drop no-thumb-interwork in EABI mode (commit 22905a24306c8c312c2d66da9f90d09af0414f81 upstream) According to GCC documentation -m(no-)thumb-interwork is meaningless in AAPCS configurations. Also clang does not support the flag: clang-5.0: error: unknown argument: '-mno-thumb-interwork' Just drop -mno-thumb-interwork in AEABI configuration. Signed-off-by: Stefan Agner Signed-off-by: Russell King Signed-off-by: Nick Desaulniers Signed-off-by: Greg Kroah-Hartman --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 36ae4454554c..17e80f483281 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -106,7 +106,7 @@ tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) tune-y := $(tune-y) ifeq ($(CONFIG_AEABI),y) -CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp +CFLAGS_ABI :=-mabi=aapcs-linux -mfpu=vfp else CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) endif -- GitLab From 764ecc201217f676fdc7f0878e74ca034716d9ee Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 8 May 2018 22:50:38 +0100 Subject: [PATCH 0068/1286] ARM: 8767/1: add support for building ARM kernel with clang (commit c1c386681bd73c4fc28eb5cc91cf8b7be9b409ba upstream) Use cc-options call for compiler options which are not available in clang. With this patch an ARMv7 multi platform kernel can be successfully build using clang (tested with version 5.0.1). Based-on-patches-by: Behan Webster Signed-off-by: Stefan Agner Signed-off-by: Russell King Signed-off-by: Nick Desaulniers Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/compressed/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index a5889238fc9f..746c8c575f98 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -113,7 +113,7 @@ CFLAGS_fdt_ro.o := $(nossp_flags) CFLAGS_fdt_rw.o := $(nossp_flags) CFLAGS_fdt_wip.o := $(nossp_flags) -ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) +ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin -I$(obj) asflags-y := -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. -- GitLab From 8d7925ad96c682dd1a0b15943a5d545c5191107e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 8 May 2018 16:27:26 +0200 Subject: [PATCH 0069/1286] bus: arm-cci: remove unnecessary unreachable() (commit 10d8713429d345867fc8998d6193b233c0cab28c upstream) Mixing asm and C code is not recommended in a naked function by gcc and leads to an error when using clang: drivers/bus/arm-cci.c:2107:2: error: non-ASM statement in naked function is not supported unreachable(); ^ While the function is marked __naked it actually properly return in asm. There is no need for the unreachable() call. GCC 7.2 generates identical object files before and after, other than (for obvious reasons) the line numbers generated by WANT_WARN_ON_SLOWPATH for all the WARN()s appearing later in the file. Suggested-by: Russell King Signed-off-by: Stefan Agner Acked-by: Nicolas Pitre Reviewed-by: Robin Murphy Signed-off-by: Olof Johansson Signed-off-by: Nick Desaulniers Signed-off-by: Greg Kroah-Hartman --- drivers/bus/arm-cci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 5426c04fe24b..fc2da3a617ac 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -2103,8 +2103,6 @@ asmlinkage void __naked cci_enable_port_for_self(void) [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)), [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)), [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) ); - - unreachable(); } /** -- GitLab From 5d47e129a7107d6f35ac4ce7f32ff9376b555bfe Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 25 Mar 2018 20:09:56 +0200 Subject: [PATCH 0070/1286] ARM: trusted_foundations: do not use naked function (commit 4ea7bdc6b5b33427bbd3f41c333e21c1825462a3 upstream) As documented in GCC naked functions should only use basic ASM syntax. The extended ASM or mixture of basic ASM and "C" code is not guaranteed. Currently this works because it was hard coded to follow and check GCC behavior for arguments and register placement. Furthermore with clang using parameters in Extended asm in a naked function is not supported: arch/arm/firmware/trusted_foundations.c:47:10: error: parameter references not allowed in naked functions : "r" (type), "r" (arg1), "r" (arg2) ^ Use a regular function to be more portable. This aligns also with the other SMC call implementations e.g. in qcom_scm-32.c and bcm_kona_smc.c. Cc: Dmitry Osipenko Cc: Stephen Warren Cc: Thierry Reding Signed-off-by: Stefan Agner Signed-off-by: Thierry Reding Signed-off-by: Nick Desaulniers Signed-off-by: Greg Kroah-Hartman --- arch/arm/firmware/trusted_foundations.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..689e6565abfc 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -31,21 +31,25 @@ static unsigned long cpu_boot_addr; -static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) +static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) { + register u32 r0 asm("r0") = type; + register u32 r1 asm("r1") = arg1; + register u32 r2 asm("r2") = arg2; + asm volatile( ".arch_extension sec\n\t" - "stmfd sp!, {r4 - r11, lr}\n\t" + "stmfd sp!, {r4 - r11}\n\t" __asmeq("%0", "r0") __asmeq("%1", "r1") __asmeq("%2", "r2") "mov r3, #0\n\t" "mov r4, #0\n\t" "smc #0\n\t" - "ldmfd sp!, {r4 - r11, pc}" + "ldmfd sp!, {r4 - r11}\n\t" : - : "r" (type), "r" (arg1), "r" (arg2) - : "memory"); + : "r" (r0), "r" (r1), "r" (r2) + : "memory", "r3", "r12", "lr"); } static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) -- GitLab From 427d4e4c27442ed2329a9672f65af49cd5a56389 Mon Sep 17 00:00:00 2001 From: Dennis Wassenberg Date: Tue, 13 Nov 2018 14:40:34 +0100 Subject: [PATCH 0071/1286] usb: core: Fix hub port connection events lost commit 22454b79e6de05fa61a2a72d00d2eed798abbb75 upstream. This will clear the USB_PORT_FEAT_C_CONNECTION bit in case of a hub port reset only if a device is was attached to the hub port before resetting the hub port. Using a Lenovo T480s attached to the ultra dock it was not possible to detect some usb-c devices at the dock usb-c ports because the hub_port_reset code will clear the USB_PORT_FEAT_C_CONNECTION bit after the actual hub port reset. Using this device combo the USB_PORT_FEAT_C_CONNECTION bit was set between the actual hub port reset and the clear of the USB_PORT_FEAT_C_CONNECTION bit. This ends up with clearing the USB_PORT_FEAT_C_CONNECTION bit after the new device was attached such that it was not detected. This patch will not clear the USB_PORT_FEAT_C_CONNECTION bit if there is currently no device attached to the port before the hub port reset. This will avoid clearing the connection bit for new attached devices. Signed-off-by: Dennis Wassenberg Acked-by: Mathias Nyman Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hub.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index a9db0887edca..638dc6f66d70 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -2815,7 +2815,9 @@ static int hub_port_reset(struct usb_hub *hub, int port1, USB_PORT_FEAT_C_BH_PORT_RESET); usb_clear_port_feature(hub->hdev, port1, USB_PORT_FEAT_C_PORT_LINK_STATE); - usb_clear_port_feature(hub->hdev, port1, + + if (udev) + usb_clear_port_feature(hub->hdev, port1, USB_PORT_FEAT_C_CONNECTION); /* -- GitLab From 47631d837acccf5532a32b47943621ce62a3a477 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 1 Aug 2018 09:37:34 +0300 Subject: [PATCH 0072/1286] usb: dwc3: gadget: fix ISOC TRB type on unaligned transfers commit 2fc6d4be35fb1e262f209758e25bfe2b7a113a7f upstream. When chaining ISOC TRBs together, only the first ISOC TRB should be of type ISOC_FIRST, all others should be of type ISOC. This patch fixes that. Fixes: c6267a51639b ("usb: dwc3: gadget: align transfers to wMaxPacketSize") Cc: # v4.11+ Signed-off-by: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/gadget.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index d7fae66a0681..e28d2904e3a3 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1088,7 +1088,7 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, /* Now prepare one extra TRB to align transfer size */ trb = &dep->trb_pool[dep->trb_enqueue]; __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, - maxp - rem, false, 0, + maxp - rem, false, 1, req->request.stream_id, req->request.short_not_ok, req->request.no_interrupt); @@ -1120,7 +1120,7 @@ static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, /* Now prepare one extra TRB to align transfer size */ trb = &dep->trb_pool[dep->trb_enqueue]; __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, - false, 0, req->request.stream_id, + false, 1, req->request.stream_id, req->request.short_not_ok, req->request.no_interrupt); } else if (req->request.zero && req->request.length && @@ -1136,7 +1136,7 @@ static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, /* Now prepare one extra TRB to handle ZLP */ trb = &dep->trb_pool[dep->trb_enqueue]; __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, - false, 0, req->request.stream_id, + false, 1, req->request.stream_id, req->request.short_not_ok, req->request.no_interrupt); } else { -- GitLab From 474e39f53816ef70224cdb6fae27893d679fb65f Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Thu, 2 Aug 2018 20:17:16 -0700 Subject: [PATCH 0073/1286] usb: dwc3: gadget: Properly check last unaligned/zero chain TRB commit ba3a51ac32ebcf8d0a54b37f1af268ad8a31c52f upstream. Current check for the last extra TRB for zero and unaligned transfers does not account for isoc OUT. The last TRB of the Buffer Descriptor for isoc OUT transfers will be retired with HWO=0. As a result, we won't return early. The req->remaining will be updated to include the BUFSIZ count of the extra TRB, and the actual number of transferred bytes calculation will be wrong. To fix this, check whether it's a short or zero packet and the last TRB chain bit to return early. Fixes: c6267a51639b ("usb: dwc3: gadget: align transfers to wMaxPacketSize") Cc: Signed-off-by: Thinh Nguyen Signed-off-by: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/gadget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index e28d2904e3a3..ac8d619ff887 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2249,7 +2249,7 @@ static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, * with one TRB pending in the ring. We need to manually clear HWO bit * from that TRB. */ - if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) { + if ((req->zero || req->unaligned) && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { trb->ctrl &= ~DWC3_TRB_CTRL_HWO; return 1; } -- GitLab From 2c3e97edbb19a4a47e1aa47101b1e2553e3bdad0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 27 Aug 2018 18:30:16 +0300 Subject: [PATCH 0074/1286] usb: dwc3: core: Clean up ULPI device commit 08fd9a82fda86529bb2f2af3c2f7cb657b4d3066 upstream. If dwc3_core_init_mode() fails with deferred probe, next probe fails on sysfs with sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:11.0/dwc3.0.auto/dwc3.0.auto.ulpi' To avoid this failure, clean up ULPI device. Cc: Signed-off-by: Andy Shevchenko Signed-off-by: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8b323a360e03..783d16a53466 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1276,6 +1276,7 @@ static int dwc3_probe(struct platform_device *pdev) err5: dwc3_event_buffers_cleanup(dwc); + dwc3_ulpi_exit(dwc); err4: dwc3_free_scratch_buffers(dwc); -- GitLab From 0902c4e7d6dbdeaa73fa6fc635391624de6e9a5f Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Fri, 9 Nov 2018 17:21:19 +0200 Subject: [PATCH 0075/1286] xhci: Add check for invalid byte size error when UAS devices are connected. commit d9193efba84fe4c4aa22a569fade5e6ca971f8af upstream. Observed "TRB completion code (27)" error which corresponds to Stopped - Length Invalid error(xhci spec section 4.17.4) while connecting USB to SATA bridge. Looks like this case was not considered when the following patch[1] was committed. Hence adding this new check which can prevent the invalid byte size error. [1] ade2e3a xhci: handle transfer events without TRB pointer Cc: Signed-off-by: Sandeep Singh cc: Nehal Shah cc: Shyam Sundar S K Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-ring.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 6996235e34a9..2d64cb024d00 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -2335,6 +2335,7 @@ static int handle_tx_event(struct xhci_hcd *xhci, goto cleanup; case COMP_RING_UNDERRUN: case COMP_RING_OVERRUN: + case COMP_STOPPED_LENGTH_INVALID: goto cleanup; default: xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", -- GitLab From 494427532654fc2b3c6791bdd997587643717684 Mon Sep 17 00:00:00 2001 From: Aaron Ma Date: Fri, 9 Nov 2018 17:21:21 +0200 Subject: [PATCH 0076/1286] usb: xhci: fix timeout for transition from RExit to U0 commit a5baeaeabcca3244782a9b6382ebab6f8a58f583 upstream. This definition is used by msecs_to_jiffies in milliseconds. According to the comments, max rexit timeout should be 20ms. Align with the comments to properly calculate the delay. Verified on Sunrise Point-LP and Cannon Lake. Cc: stable@vger.kernel.org Signed-off-by: Aaron Ma Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-hub.c | 4 ++-- drivers/usb/host/xhci.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index d2a9767a8e9c..4f612b5d0f94 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -941,7 +941,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd, time_left = wait_for_completion_timeout( &bus_state->rexit_done[wIndex], msecs_to_jiffies( - XHCI_MAX_REXIT_TIMEOUT)); + XHCI_MAX_REXIT_TIMEOUT_MS)); spin_lock_irqsave(&xhci->lock, flags); if (time_left) { @@ -955,7 +955,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd, } else { int port_status = readl(port_array[wIndex]); xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", - XHCI_MAX_REXIT_TIMEOUT, + XHCI_MAX_REXIT_TIMEOUT_MS, port_status); status |= USB_PORT_STAT_SUSPEND; clear_bit(wIndex, &bus_state->rexit_ports); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 11232e62b898..29dc6160c9eb 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1684,7 +1684,7 @@ struct xhci_bus_state { * It can take up to 20 ms to transition from RExit to U0 on the * Intel Lynx Point LP xHCI host. */ -#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) +#define XHCI_MAX_REXIT_TIMEOUT_MS 20 static inline unsigned int hcd_index(struct usb_hcd *hcd) { -- GitLab From 1129534f73336addfcea53a65c7847d1aa1d2175 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 9 Nov 2018 11:59:45 +0100 Subject: [PATCH 0077/1286] ALSA: oss: Use kvzalloc() for local buffer allocations commit 65766ee0bf7fe8b3be80e2e1c3ef54ad59b29476 upstream. PCM OSS layer may allocate a few temporary buffers, one for the core read/write and another for the conversions via plugins. Currently both are allocated via vmalloc(). But as the allocation size is equivalent with the PCM period size, the required size might be quite small, depending on the application. This patch replaces these vmalloc() calls with kvzalloc() for covering small period sizes better. Also, we use "z"-alloc variant here for addressing the possible uninitialized access reported by syzkaller. Reported-by: syzbot+1cb36954e127c98dd037@syzkaller.appspotmail.com Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/oss/pcm_oss.c | 6 +++--- sound/core/oss/pcm_plugin.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/sound/core/oss/pcm_oss.c b/sound/core/oss/pcm_oss.c index b4f954e6d2db..df358e838b5b 100644 --- a/sound/core/oss/pcm_oss.c +++ b/sound/core/oss/pcm_oss.c @@ -1062,8 +1062,8 @@ static int snd_pcm_oss_change_params_locked(struct snd_pcm_substream *substream) runtime->oss.channels = params_channels(params); runtime->oss.rate = params_rate(params); - vfree(runtime->oss.buffer); - runtime->oss.buffer = vmalloc(runtime->oss.period_bytes); + kvfree(runtime->oss.buffer); + runtime->oss.buffer = kvzalloc(runtime->oss.period_bytes, GFP_KERNEL); if (!runtime->oss.buffer) { err = -ENOMEM; goto failure; @@ -2328,7 +2328,7 @@ static void snd_pcm_oss_release_substream(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime; runtime = substream->runtime; - vfree(runtime->oss.buffer); + kvfree(runtime->oss.buffer); runtime->oss.buffer = NULL; #ifdef CONFIG_SND_PCM_OSS_PLUGINS snd_pcm_oss_plugin_clear(substream); diff --git a/sound/core/oss/pcm_plugin.c b/sound/core/oss/pcm_plugin.c index 85a56af104bd..617845d4a811 100644 --- a/sound/core/oss/pcm_plugin.c +++ b/sound/core/oss/pcm_plugin.c @@ -66,8 +66,8 @@ static int snd_pcm_plugin_alloc(struct snd_pcm_plugin *plugin, snd_pcm_uframes_t return -ENXIO; size /= 8; if (plugin->buf_frames < frames) { - vfree(plugin->buf); - plugin->buf = vmalloc(size); + kvfree(plugin->buf); + plugin->buf = kvzalloc(size, GFP_KERNEL); plugin->buf_frames = frames; } if (!plugin->buf) { @@ -191,7 +191,7 @@ int snd_pcm_plugin_free(struct snd_pcm_plugin *plugin) if (plugin->private_free) plugin->private_free(plugin); kfree(plugin->buf_channels); - vfree(plugin->buf); + kvfree(plugin->buf); kfree(plugin); return 0; } -- GitLab From d34af066f084defffd77f33778217fef8889e063 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 15 Nov 2018 15:03:24 -0800 Subject: [PATCH 0078/1286] MAINTAINERS: Add Sasha as a stable branch maintainer commit cb5d21946d2a2f4687c482ab4604af1d29dac35a upstream. Sasha has somehow been convinced into helping me with the stable kernel maintenance. Codify this slip in good judgement before he realizes what he really signed up for :) Signed-off-by: Greg Kroah-Hartman Acked-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 546beb6b0176..6cb70b853323 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12662,6 +12662,7 @@ F: arch/alpha/kernel/srm_env.c STABLE BRANCH M: Greg Kroah-Hartman +M: Sasha Levin L: stable@vger.kernel.org S: Supported F: Documentation/process/stable-kernel-rules.rst -- GitLab From 7c9f55c5a58a8a7131e1f5a82a7f85bf06c62a63 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Mon, 29 Oct 2018 15:17:01 -0700 Subject: [PATCH 0079/1286] mmc: sdhci-pci: Try "cd" for card-detect lookup before using NULL commit cdcefe6bd9df754f528ffc339d3cc143cea4ddf6 upstream. Problem: The card detect IRQ does not work with modern BIOS (that want to use _DSD to provide the card detect GPIO to the driver). Details: The mmc core provides the mmc_gpiod_request_cd() API to let host drivers request the gpio descriptor for the "card detect" pin. This pin is specified in the ACPI for the SDHC device: * Either as a resource using _CRS. This is a method used by legacy BIOS. (The driver needs to tell which resource index). * Or as a named property ("cd-gpios"/"cd-gpio") in _DSD (which internally points to an entry in _CRS). This way, the driver can lookup using a string. This is what modern BIOS prefer to use. This API finally results in a call to the following code: struct gpio_desc *acpi_find_gpio(..., const char *con_id,...) { ... /* Lookup gpio (using "-gpio") in the _DSD */ ... if (!acpi_can_fallback_to_crs(adev, con_id)) return ERR_PTR(-ENOENT); ... /* Falling back to _CRS is allowed, Lookup gpio in the _CRS */ ... } Note that this means that if the ACPI has _DSD properties, the kernel will never use _CRS for the lookup (Because acpi_can_fallback_to_crs() will always be false for any device hat has _DSD entries). The SDHCI driver is thus currently broken on a modern BIOS, even if BIOS provides both _CRS (for index based lookup) and _DSD entries (for string based lookup). Ironically, none of these will be used for the lookup currently because: * Since the con_id is NULL, acpi_find_gpio() does not find a matching entry in DSDT. (The _DSDT entry has the property name = "cd-gpios") * Because ACPI contains DSDT entries, thus acpi_can_fallback_to_crs() returns false (because device properties have been populated from _DSD), thus the _CRS is never used for the lookup. Fix: Try "cd" for lookup in the _DSD before falling back to using NULL so as to try looking up in the _CRS. I've tested this patch successfully with both Legacy BIOS (that provide only _CRS method) as well as modern BIOS (that provide both _CRS and _DSD). Also the use of "cd" appears to be fairly consistent across other users of this API (other MMC host controller drivers). Link: https://lkml.org/lkml/2018/9/25/1113 Signed-off-by: Rajat Jain Acked-by: Adrian Hunter Fixes: f10e4bf6632b ("gpio: acpi: Even more tighten up ACPI GPIO lookups") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/sdhci-pci-core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 44da037b13ba..0e386f5cc836 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1607,8 +1607,13 @@ static struct sdhci_pci_slot *sdhci_pci_probe_slot( host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; if (slot->cd_idx >= 0) { - ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, + ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, slot->cd_override_level, 0, NULL); + if (ret && ret != -EPROBE_DEFER) + ret = mmc_gpiod_request_cd(host->mmc, NULL, + slot->cd_idx, + slot->cd_override_level, + 0, NULL); if (ret == -EPROBE_DEFER) goto remove; -- GitLab From 6a5f25e30045bb2c3622136807d76be3bd4fb0ba Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 2 Nov 2018 15:39:43 +0200 Subject: [PATCH 0080/1286] gpio: don't free unallocated ida on gpiochip_add_data_with_key() error path commit a05a14049999598a3bb6fab12db6b768a0215522 upstream. The change corrects the error path in gpiochip_add_data_with_key() by avoiding to call ida_simple_remove(), if ida_simple_get() returns an error. Note that ida_simple_remove()/ida_free() throws a BUG(), if id argument is negative, it allows to easily check the correctness of the fix by fuzzing the return value from ida_simple_get(). Fixes: ff2b13592299 ("gpio: make the gpiochip a real device") Cc: stable@vger.kernel.org # v4.6+ Signed-off-by: Vladimir Zapolskiy Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/gpio/gpiolib.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 7d5de4ef4f22..21062cb6b85f 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1166,7 +1166,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) gdev->descs = kcalloc(chip->ngpio, sizeof(gdev->descs[0]), GFP_KERNEL); if (!gdev->descs) { status = -ENOMEM; - goto err_free_gdev; + goto err_free_ida; } if (chip->ngpio == 0) { @@ -1298,8 +1298,9 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) kfree(gdev->label); err_free_descs: kfree(gdev->descs); -err_free_gdev: +err_free_ida: ida_simple_remove(&gpio_ida, gdev->id); +err_free_gdev: /* failures here can mean systems won't boot... */ pr_err("%s: GPIOs %d..%d (%s) failed to register\n", __func__, gdev->base, gdev->base + gdev->ngpio - 1, -- GitLab From bc176d7a68bef23e1db1b0ec6e4ad4d75aa63958 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Thu, 16 Aug 2018 13:25:48 +0300 Subject: [PATCH 0081/1286] iwlwifi: mvm: support sta_statistics() even on older firmware commit ec484d03ef0df8d34086b95710e355a259cbe1f2 upstream. The oldest firmware supported by iwlmvm do support getting the average beacon RSSI. Enable the sta_statistics() call from mac80211 even on older firmware versions. Fixes: 33cef9256342 ("iwlwifi: mvm: support beacon statistics for BSS client") Cc: stable@vger.kernel.org # 4.2+ Signed-off-by: Emmanuel Grumbach Signed-off-by: Luca Coelho Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c index 80a653950e86..f161fa55d202 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c @@ -4189,10 +4189,6 @@ static void iwl_mvm_mac_sta_statistics(struct ieee80211_hw *hw, sinfo->filled |= BIT(NL80211_STA_INFO_SIGNAL_AVG); } - if (!fw_has_capa(&mvm->fw->ucode_capa, - IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS)) - return; - /* if beacon filtering isn't on mac80211 does it anyway */ if (!(vif->driver_flags & IEEE80211_VIF_BEACON_FILTER)) return; -- GitLab From b58f0659f7c6c9957a528aa15cb0189055570672 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Wed, 3 Oct 2018 11:16:54 +0300 Subject: [PATCH 0082/1286] iwlwifi: mvm: fix regulatory domain update when the firmware starts commit 82715ac71e6b94a2c2136e31f3a8e6748e33aa8c upstream. When the firmware starts, it doesn't have any regulatory information, hence it uses the world wide limitations. The driver can feed the firmware with previous knowledge that was kept in the driver, but the firmware may still not update its internal tables. This happens when we start a BSS interface, and then the firmware can change the regulatory tables based on our location and it'll use more lenient, location specific rules. Then, if the firmware is shut down (when the interface is brought down), and then an AP interface is created, the firmware will forget the country specific rules. The host will think that we are in a certain country that may allow channels and will try to teach the firmware about our location, but the firmware may still not allow to drop the world wide limitations and apply country specific rules because it was just re-started. In this case, the firmware will reply with MCC_RESP_ILLEGAL to the MCC_UPDATE_CMD. In that case, iwlwifi needs to let the upper layers (cfg80211 / hostapd) know that the channel list they know about has been updated. This fixes https://bugzilla.kernel.org/show_bug.cgi?id=201105 Cc: stable@vger.kernel.org Signed-off-by: Emmanuel Grumbach Signed-off-by: Luca Coelho Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c | 8 ++++++-- drivers/net/wireless/intel/iwlwifi/mvm/nvm.c | 5 ++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c index f161fa55d202..77ed6ecf5ee5 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c @@ -328,8 +328,12 @@ struct ieee80211_regdomain *iwl_mvm_get_regdomain(struct wiphy *wiphy, goto out; } - if (changed) - *changed = (resp->status == MCC_RESP_NEW_CHAN_PROFILE); + if (changed) { + u32 status = le32_to_cpu(resp->status); + + *changed = (status == MCC_RESP_NEW_CHAN_PROFILE || + status == MCC_RESP_ILLEGAL); + } regd = iwl_parse_nvm_mcc_info(mvm->trans->dev, mvm->cfg, __le32_to_cpu(resp->n_channels), diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c index fb25b6f29323..ca2d66ce8424 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/nvm.c @@ -732,9 +732,8 @@ iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2, } IWL_DEBUG_LAR(mvm, - "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n", - status, mcc, mcc >> 8, mcc & 0xff, - !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels); + "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') n_chans: %d\n", + status, mcc, mcc >> 8, mcc & 0xff, n_channels); exit: iwl_free_resp(&cmd); -- GitLab From bf02eaf57a328b7213520396f4920902286e8cd8 Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Wed, 17 Oct 2018 08:35:15 +0300 Subject: [PATCH 0083/1286] iwlwifi: mvm: don't use SAR Geo if basic SAR is not used commit 5d041c46ccb9b48acc110e214beff5e2789311df upstream. We can't use SAR Geo if basic SAR is not enabled, since the SAR Geo tables define offsets in relation to the basic SAR table in use. To fix this, make iwl_mvm_sar_init() return one in case WRDS is not available, so we can skip reading WGDS entirely. Fixes: a6bff3cb19b7 ("iwlwifi: mvm: add GEO_TX_POWER_LIMIT cmd for geographic tx power table") Cc: stable@vger.kernel.org # 4.12+ Signed-off-by: Luca Coelho Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/intel/iwlwifi/mvm/fw.c | 36 ++++++++++++++++----- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c index b71a9d11a50f..11319675f2d9 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c @@ -997,6 +997,11 @@ static int iwl_mvm_sar_get_ewrd_table(struct iwl_mvm *mvm) return -ENOENT; } +static int iwl_mvm_sar_get_wgds_table(struct iwl_mvm *mvm) +{ + return -ENOENT; +} + static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) { return 0; @@ -1023,8 +1028,11 @@ static int iwl_mvm_sar_init(struct iwl_mvm *mvm) IWL_DEBUG_RADIO(mvm, "WRDS SAR BIOS table invalid or unavailable. (%d)\n", ret); - /* if not available, don't fail and don't bother with EWRD */ - return 0; + /* + * If not available, don't fail and don't bother with EWRD. + * Return 1 to tell that we can't use WGDS either. + */ + return 1; } ret = iwl_mvm_sar_get_ewrd_table(mvm); @@ -1037,9 +1045,13 @@ static int iwl_mvm_sar_init(struct iwl_mvm *mvm) /* choose profile 1 (WRDS) as default for both chains */ ret = iwl_mvm_sar_select_profile(mvm, 1, 1); - /* if we don't have profile 0 from BIOS, just skip it */ + /* + * If we don't have profile 0 from BIOS, just skip it. This + * means that SAR Geo will not be enabled either, even if we + * have other valid profiles. + */ if (ret == -ENOENT) - return 0; + return 1; return ret; } @@ -1229,11 +1241,19 @@ int iwl_mvm_up(struct iwl_mvm *mvm) iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN); ret = iwl_mvm_sar_init(mvm); - if (ret) - goto error; + if (ret == 0) { + ret = iwl_mvm_sar_geo_init(mvm); + } else if (ret > 0 && !iwl_mvm_sar_get_wgds_table(mvm)) { + /* + * If basic SAR is not available, we check for WGDS, + * which should *not* be available either. If it is + * available, issue an error, because we can't use SAR + * Geo without basic SAR. + */ + IWL_ERR(mvm, "BIOS contains WGDS but no WRDS\n"); + } - ret = iwl_mvm_sar_geo_init(mvm); - if (ret) + if (ret < 0) goto error; iwl_mvm_leds_sync(mvm); -- GitLab From a0b9ddf4906e6340c4ce920c9450de05021e73ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 8 Nov 2018 16:08:29 +0100 Subject: [PATCH 0084/1286] brcmfmac: fix reporting support for 160 MHz channels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit d1fe6ad6f6bd61c84788d3a7b11e459a439c6169 upstream. Driver can report IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ so it's important to provide valid & complete info about supported bands for each channel. By default no support for 160 MHz should be assumed unless firmware reports it for a given channel later. This fixes info passed to the userspace. Without that change userspace could try to use invalid channel and fail to start an interface. Signed-off-by: Rafał Miłecki Cc: stable@vger.kernel.org Signed-off-by: Kalle Valo Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index 083e5ce7eac7..cd6c5ece9a5d 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -6098,7 +6098,8 @@ static int brcmf_construct_chaninfo(struct brcmf_cfg80211_info *cfg, * for subsequent chanspecs. */ channel->flags = IEEE80211_CHAN_NO_HT40 | - IEEE80211_CHAN_NO_80MHZ; + IEEE80211_CHAN_NO_80MHZ | + IEEE80211_CHAN_NO_160MHZ; ch.bw = BRCMU_CHAN_BW_20; cfg->d11inf.encchspec(&ch); chaninfo = ch.chspec; -- GitLab From 3b99dcd4026a08fc9d1fd5cc0a9fc50529803fca Mon Sep 17 00:00:00 2001 From: Konstantin Khlebnikov Date: Tue, 16 Oct 2018 11:56:26 +0300 Subject: [PATCH 0085/1286] tools/power/cpupower: fix compilation with STATIC=true commit 9de9aa45e9bd67232e000cca42ceb134b8ae51b6 upstream. Rename duplicate sysfs_read_file into cpupower_read_sysfs and fix linking. Signed-off-by: Konstantin Khlebnikov Acked-by: Thomas Renninger Cc: Signed-off-by: Shuah Khan (Samsung OSG) Signed-off-by: Greg Kroah-Hartman --- tools/power/cpupower/bench/Makefile | 2 +- tools/power/cpupower/lib/cpufreq.c | 2 +- tools/power/cpupower/lib/cpuidle.c | 2 +- tools/power/cpupower/lib/cpupower.c | 4 ++-- tools/power/cpupower/lib/cpupower_intern.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/power/cpupower/bench/Makefile b/tools/power/cpupower/bench/Makefile index d79ab161cc75..f68b4bc55273 100644 --- a/tools/power/cpupower/bench/Makefile +++ b/tools/power/cpupower/bench/Makefile @@ -9,7 +9,7 @@ endif ifeq ($(strip $(STATIC)),true) LIBS = -L../ -L$(OUTPUT) -lm OBJS = $(OUTPUT)main.o $(OUTPUT)parse.o $(OUTPUT)system.o $(OUTPUT)benchmark.o \ - $(OUTPUT)../lib/cpufreq.o $(OUTPUT)../lib/sysfs.o + $(OUTPUT)../lib/cpufreq.o $(OUTPUT)../lib/cpupower.o else LIBS = -L../ -L$(OUTPUT) -lm -lcpupower OBJS = $(OUTPUT)main.o $(OUTPUT)parse.o $(OUTPUT)system.o $(OUTPUT)benchmark.o diff --git a/tools/power/cpupower/lib/cpufreq.c b/tools/power/cpupower/lib/cpufreq.c index 1b993fe1ce23..0c0f3e3f0d80 100644 --- a/tools/power/cpupower/lib/cpufreq.c +++ b/tools/power/cpupower/lib/cpufreq.c @@ -28,7 +28,7 @@ static unsigned int sysfs_cpufreq_read_file(unsigned int cpu, const char *fname, snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u/cpufreq/%s", cpu, fname); - return sysfs_read_file(path, buf, buflen); + return cpupower_read_sysfs(path, buf, buflen); } /* helper function to write a new value to a /sys file */ diff --git a/tools/power/cpupower/lib/cpuidle.c b/tools/power/cpupower/lib/cpuidle.c index 9bd4c7655fdb..852d25462388 100644 --- a/tools/power/cpupower/lib/cpuidle.c +++ b/tools/power/cpupower/lib/cpuidle.c @@ -319,7 +319,7 @@ static unsigned int sysfs_cpuidle_read_file(const char *fname, char *buf, snprintf(path, sizeof(path), PATH_TO_CPU "cpuidle/%s", fname); - return sysfs_read_file(path, buf, buflen); + return cpupower_read_sysfs(path, buf, buflen); } diff --git a/tools/power/cpupower/lib/cpupower.c b/tools/power/cpupower/lib/cpupower.c index 9c395ec924de..9711d628b0f4 100644 --- a/tools/power/cpupower/lib/cpupower.c +++ b/tools/power/cpupower/lib/cpupower.c @@ -15,7 +15,7 @@ #include "cpupower.h" #include "cpupower_intern.h" -unsigned int sysfs_read_file(const char *path, char *buf, size_t buflen) +unsigned int cpupower_read_sysfs(const char *path, char *buf, size_t buflen) { int fd; ssize_t numread; @@ -95,7 +95,7 @@ static int sysfs_topology_read_file(unsigned int cpu, const char *fname, int *re snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u/topology/%s", cpu, fname); - if (sysfs_read_file(path, linebuf, MAX_LINE_LEN) == 0) + if (cpupower_read_sysfs(path, linebuf, MAX_LINE_LEN) == 0) return -1; *result = strtol(linebuf, &endp, 0); if (endp == linebuf || errno == ERANGE) diff --git a/tools/power/cpupower/lib/cpupower_intern.h b/tools/power/cpupower/lib/cpupower_intern.h index 92affdfbe417..4887c76d23f8 100644 --- a/tools/power/cpupower/lib/cpupower_intern.h +++ b/tools/power/cpupower/lib/cpupower_intern.h @@ -3,4 +3,4 @@ #define MAX_LINE_LEN 4096 #define SYSFS_PATH_MAX 255 -unsigned int sysfs_read_file(const char *path, char *buf, size_t buflen); +unsigned int cpupower_read_sysfs(const char *path, char *buf, size_t buflen); -- GitLab From 335f31342699f9015f0ab5a8d41d6c911085f033 Mon Sep 17 00:00:00 2001 From: Dominique Martinet Date: Mon, 27 Aug 2018 15:12:05 +0900 Subject: [PATCH 0086/1286] v9fs_dir_readdir: fix double-free on p9stat_read error commit 81c99089bce693b94b775b6eb888115d2d540086 upstream. p9stat_read will call p9stat_free on error, we should only free the struct content on success. There also is no need to "p9stat_init" st as the read function will zero the whole struct for us anyway, so clean up the code a bit while we are here. Link: http://lkml.kernel.org/r/1535410108-20650-1-git-send-email-asmadeus@codewreck.org Signed-off-by: Dominique Martinet Reported-by: syzbot+d4252148d198410b864f@syzkaller.appspotmail.com Signed-off-by: Greg Kroah-Hartman --- fs/9p/vfs_dir.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/fs/9p/vfs_dir.c b/fs/9p/vfs_dir.c index b0405d6aac85..48db9a9f13f9 100644 --- a/fs/9p/vfs_dir.c +++ b/fs/9p/vfs_dir.c @@ -76,15 +76,6 @@ static inline int dt_type(struct p9_wstat *mistat) return rettype; } -static void p9stat_init(struct p9_wstat *stbuf) -{ - stbuf->name = NULL; - stbuf->uid = NULL; - stbuf->gid = NULL; - stbuf->muid = NULL; - stbuf->extension = NULL; -} - /** * v9fs_alloc_rdir_buf - Allocate buffer used for read and readdir * @filp: opened file structure @@ -145,12 +136,10 @@ static int v9fs_dir_readdir(struct file *file, struct dir_context *ctx) rdir->tail = n; } while (rdir->head < rdir->tail) { - p9stat_init(&st); err = p9stat_read(fid->clnt, rdir->buf + rdir->head, rdir->tail - rdir->head, &st); if (err) { p9_debug(P9_DEBUG_VFS, "returned %d\n", err); - p9stat_free(&st); return -EIO; } reclen = st.size+2; -- GitLab From 9520db16756e24873677d867a6a0f9cab3b6726d Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Sat, 8 Sep 2018 01:42:58 +0900 Subject: [PATCH 0087/1286] selinux: Add __GFP_NOWARN to allocation at str_read() commit 4458bba09788e70e8fb39ad003f087cd9dfbd6ac upstream. syzbot is hitting warning at str_read() [1] because len parameter can become larger than KMALLOC_MAX_SIZE. We don't need to emit warning for this case. [1] https://syzkaller.appspot.com/bug?id=7f2f5aad79ea8663c296a2eedb81978401a908f0 Signed-off-by: Tetsuo Handa Reported-by: syzbot Signed-off-by: Paul Moore Signed-off-by: Greg Kroah-Hartman --- security/selinux/ss/policydb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c index 6e8c8056d7ad..6688ac5b991e 100644 --- a/security/selinux/ss/policydb.c +++ b/security/selinux/ss/policydb.c @@ -1099,7 +1099,7 @@ static int str_read(char **strp, gfp_t flags, void *fp, u32 len) if ((len == 0) || (len == (u32)-1)) return -EINVAL; - str = kmalloc(len + 1, flags); + str = kmalloc(len + 1, flags | __GFP_NOWARN); if (!str) return -ENOMEM; -- GitLab From 922fad66a961a34d970f9d0d0e961813489c556c Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 16 Oct 2018 17:07:35 -0700 Subject: [PATCH 0088/1286] Input: synaptics - avoid using uninitialized variable when probing commit f39f8688888ae74fa8deae2d01289b69b4727394 upstream. synaptics_detect() does not check whether sending commands to the device succeeds and instead relies on getting unique data from the device. Let's make sure we seed entire buffer with zeroes to make sure we will not use garbage on stack that just happen to be 0x47. Reported-by: syzbot+13cb3b01d0784e4ffc3f@syzkaller.appspotmail.com Reviewed-by: Benjamin Tissoires Reviewed-by: Peter Hutterer Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/synaptics.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index 6c4bbd38700e..6f36e2d01e2e 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -99,9 +99,7 @@ static int synaptics_mode_cmd(struct psmouse *psmouse, u8 mode) int synaptics_detect(struct psmouse *psmouse, bool set_properties) { struct ps2dev *ps2dev = &psmouse->ps2dev; - u8 param[4]; - - param[0] = 0; + u8 param[4] = { 0 }; ps2_command(ps2dev, param, PSMOUSE_CMD_SETRES); ps2_command(ps2dev, param, PSMOUSE_CMD_SETRES); -- GitLab From bc94cd6d869ea0ac78936b14321d37bdea657ba4 Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Fri, 2 Nov 2018 15:48:42 -0700 Subject: [PATCH 0089/1286] bfs: add sanity check at bfs_fill_super() commit 9f2df09a33aa2c76ce6385d382693f98d7f2f07e upstream. syzbot is reporting too large memory allocation at bfs_fill_super() [1]. Since file system image is corrupted such that bfs_sb->s_start == 0, bfs_fill_super() is trying to allocate 8MB of continuous memory. Fix this by adding a sanity check on bfs_sb->s_start, __GFP_NOWARN and printf(). [1] https://syzkaller.appspot.com/bug?id=16a87c236b951351374a84c8a32f40edbc034e96 Link: http://lkml.kernel.org/r/1525862104-3407-1-git-send-email-penguin-kernel@I-love.SAKURA.ne.jp Signed-off-by: Tetsuo Handa Reported-by: syzbot Reviewed-by: Andrew Morton Cc: Tigran Aivazian Cc: Matthew Wilcox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- fs/bfs/inode.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/fs/bfs/inode.c b/fs/bfs/inode.c index 9a69392f1fb3..d81c148682e7 100644 --- a/fs/bfs/inode.c +++ b/fs/bfs/inode.c @@ -350,7 +350,8 @@ static int bfs_fill_super(struct super_block *s, void *data, int silent) s->s_magic = BFS_MAGIC; - if (le32_to_cpu(bfs_sb->s_start) > le32_to_cpu(bfs_sb->s_end)) { + if (le32_to_cpu(bfs_sb->s_start) > le32_to_cpu(bfs_sb->s_end) || + le32_to_cpu(bfs_sb->s_start) < BFS_BSIZE) { printf("Superblock is corrupted\n"); goto out1; } @@ -359,9 +360,11 @@ static int bfs_fill_super(struct super_block *s, void *data, int silent) sizeof(struct bfs_inode) + BFS_ROOT_INO - 1; imap_len = (info->si_lasti / 8) + 1; - info->si_imap = kzalloc(imap_len, GFP_KERNEL); - if (!info->si_imap) + info->si_imap = kzalloc(imap_len, GFP_KERNEL | __GFP_NOWARN); + if (!info->si_imap) { + printf("Cannot allocate %u bytes\n", imap_len); goto out1; + } for (i = 0; i < BFS_ROOT_INO; i++) set_bit(i, info->si_imap); -- GitLab From 8376fdc999be008f0e9918db52f1ed8c08f5a1c9 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Mon, 29 Oct 2018 23:10:29 +0800 Subject: [PATCH 0090/1286] sctp: clear the transport of some out_chunk_list chunks in sctp_assoc_rm_peer commit df132eff463873e14e019a07f387b4d577d6d1f9 upstream. If a transport is removed by asconf but there still are some chunks with this transport queuing on out_chunk_list, later an use-after-free issue will be caused when accessing this transport from these chunks in sctp_outq_flush(). This is an old bug, we fix it by clearing the transport of these chunks in out_chunk_list when removing a transport in sctp_assoc_rm_peer(). Reported-by: syzbot+56a40ceee5fb35932f4d@syzkaller.appspotmail.com Signed-off-by: Xin Long Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/sctp/associola.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/net/sctp/associola.c b/net/sctp/associola.c index 58f7d8cfd748..4982b31fec8e 100644 --- a/net/sctp/associola.c +++ b/net/sctp/associola.c @@ -497,8 +497,9 @@ void sctp_assoc_set_primary(struct sctp_association *asoc, void sctp_assoc_rm_peer(struct sctp_association *asoc, struct sctp_transport *peer) { - struct list_head *pos; - struct sctp_transport *transport; + struct sctp_transport *transport; + struct list_head *pos; + struct sctp_chunk *ch; pr_debug("%s: association:%p addr:%pISpc\n", __func__, asoc, &peer->ipaddr.sa); @@ -562,7 +563,6 @@ void sctp_assoc_rm_peer(struct sctp_association *asoc, */ if (!list_empty(&peer->transmitted)) { struct sctp_transport *active = asoc->peer.active_path; - struct sctp_chunk *ch; /* Reset the transport of each chunk on this list */ list_for_each_entry(ch, &peer->transmitted, @@ -584,6 +584,10 @@ void sctp_assoc_rm_peer(struct sctp_association *asoc, sctp_transport_hold(active); } + list_for_each_entry(ch, &asoc->outqueue.out_chunk_list, list) + if (ch->transport == peer) + ch->transport = NULL; + asoc->peer.transport_count--; sctp_transport_free(peer); -- GitLab From 49ee6220be1b9c2dfd00a4a7adc55c2d7ffc7faf Mon Sep 17 00:00:00 2001 From: Andrew Price Date: Mon, 8 Oct 2018 07:52:43 -0500 Subject: [PATCH 0091/1286] gfs2: Don't leave s_fs_info pointing to freed memory in init_sbd commit 4c62bd9cea7bcf10292f7e4c57a2bca332942697 upstream. When alloc_percpu() fails, sdp gets freed but sb->s_fs_info still points to the same address. Move the assignment after that error check so that s_fs_info can only point to a valid sdp or NULL, which is checked for later in the error path, in gfs2_kill_super(). Reported-by: syzbot+dcb8b3587445007f5808@syzkaller.appspotmail.com Signed-off-by: Andrew Price Signed-off-by: Bob Peterson Signed-off-by: Greg Kroah-Hartman --- fs/gfs2/ops_fstype.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/gfs2/ops_fstype.c b/fs/gfs2/ops_fstype.c index 28d6c65c8bb3..057be88eb1b4 100644 --- a/fs/gfs2/ops_fstype.c +++ b/fs/gfs2/ops_fstype.c @@ -72,13 +72,13 @@ static struct gfs2_sbd *init_sbd(struct super_block *sb) if (!sdp) return NULL; - sb->s_fs_info = sdp; sdp->sd_vfs = sb; sdp->sd_lkstats = alloc_percpu(struct gfs2_pcpu_lkstats); if (!sdp->sd_lkstats) { kfree(sdp); return NULL; } + sb->s_fs_info = sdp; set_bit(SDF_NOJOURNALID, &sdp->sd_flags); gfs2_tune_init(&sdp->sd_tune); -- GitLab From 8a37895d1e35884c160fbdd2bb90aeab8daafd87 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 22 Oct 2018 09:24:27 -0700 Subject: [PATCH 0092/1286] llc: do not use sk_eat_skb() commit 604d415e2bd642b7e02c80e719e0396b9d4a77a6 upstream. syzkaller triggered a use-after-free [1], caused by a combination of skb_get() in llc_conn_state_process() and usage of sk_eat_skb() sk_eat_skb() is assuming the skb about to be freed is only used by the current thread. TCP/DCCP stacks enforce this because current thread holds the socket lock. llc_conn_state_process() wants to make sure skb does not disappear, and holds a reference on the skb it manipulates. But as soon as this skb is added to socket receive queue, another thread can consume it. This means that llc must use regular skb_unlink() and kfree_skb() so that both producer and consumer can safely work on the same skb. [1] BUG: KASAN: use-after-free in atomic_read include/asm-generic/atomic-instrumented.h:21 [inline] BUG: KASAN: use-after-free in refcount_read include/linux/refcount.h:43 [inline] BUG: KASAN: use-after-free in skb_unref include/linux/skbuff.h:967 [inline] BUG: KASAN: use-after-free in kfree_skb+0xb7/0x580 net/core/skbuff.c:655 Read of size 4 at addr ffff8801d1f6fba4 by task ksoftirqd/1/18 CPU: 1 PID: 18 Comm: ksoftirqd/1 Not tainted 4.19.0-rc8+ #295 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x1c4/0x2b6 lib/dump_stack.c:113 print_address_description.cold.8+0x9/0x1ff mm/kasan/report.c:256 kasan_report_error mm/kasan/report.c:354 [inline] kasan_report.cold.9+0x242/0x309 mm/kasan/report.c:412 check_memory_region_inline mm/kasan/kasan.c:260 [inline] check_memory_region+0x13e/0x1b0 mm/kasan/kasan.c:267 kasan_check_read+0x11/0x20 mm/kasan/kasan.c:272 atomic_read include/asm-generic/atomic-instrumented.h:21 [inline] refcount_read include/linux/refcount.h:43 [inline] skb_unref include/linux/skbuff.h:967 [inline] kfree_skb+0xb7/0x580 net/core/skbuff.c:655 llc_sap_state_process+0x9b/0x550 net/llc/llc_sap.c:224 llc_sap_rcv+0x156/0x1f0 net/llc/llc_sap.c:297 llc_sap_handler+0x65e/0xf80 net/llc/llc_sap.c:438 llc_rcv+0x79e/0xe20 net/llc/llc_input.c:208 __netif_receive_skb_one_core+0x14d/0x200 net/core/dev.c:4913 __netif_receive_skb+0x2c/0x1e0 net/core/dev.c:5023 process_backlog+0x218/0x6f0 net/core/dev.c:5829 napi_poll net/core/dev.c:6249 [inline] net_rx_action+0x7c5/0x1950 net/core/dev.c:6315 __do_softirq+0x30c/0xb03 kernel/softirq.c:292 run_ksoftirqd+0x94/0x100 kernel/softirq.c:653 smpboot_thread_fn+0x68b/0xa00 kernel/smpboot.c:164 kthread+0x35a/0x420 kernel/kthread.c:246 ret_from_fork+0x3a/0x50 arch/x86/entry/entry_64.S:413 Allocated by task 18: save_stack+0x43/0xd0 mm/kasan/kasan.c:448 set_track mm/kasan/kasan.c:460 [inline] kasan_kmalloc+0xc7/0xe0 mm/kasan/kasan.c:553 kasan_slab_alloc+0x12/0x20 mm/kasan/kasan.c:490 kmem_cache_alloc_node+0x144/0x730 mm/slab.c:3644 __alloc_skb+0x119/0x770 net/core/skbuff.c:193 alloc_skb include/linux/skbuff.h:995 [inline] llc_alloc_frame+0xbc/0x370 net/llc/llc_sap.c:54 llc_station_ac_send_xid_r net/llc/llc_station.c:52 [inline] llc_station_rcv+0x1dc/0x1420 net/llc/llc_station.c:111 llc_rcv+0xc32/0xe20 net/llc/llc_input.c:220 __netif_receive_skb_one_core+0x14d/0x200 net/core/dev.c:4913 __netif_receive_skb+0x2c/0x1e0 net/core/dev.c:5023 process_backlog+0x218/0x6f0 net/core/dev.c:5829 napi_poll net/core/dev.c:6249 [inline] net_rx_action+0x7c5/0x1950 net/core/dev.c:6315 __do_softirq+0x30c/0xb03 kernel/softirq.c:292 Freed by task 16383: save_stack+0x43/0xd0 mm/kasan/kasan.c:448 set_track mm/kasan/kasan.c:460 [inline] __kasan_slab_free+0x102/0x150 mm/kasan/kasan.c:521 kasan_slab_free+0xe/0x10 mm/kasan/kasan.c:528 __cache_free mm/slab.c:3498 [inline] kmem_cache_free+0x83/0x290 mm/slab.c:3756 kfree_skbmem+0x154/0x230 net/core/skbuff.c:582 __kfree_skb+0x1d/0x20 net/core/skbuff.c:642 sk_eat_skb include/net/sock.h:2366 [inline] llc_ui_recvmsg+0xec2/0x1610 net/llc/af_llc.c:882 sock_recvmsg_nosec net/socket.c:794 [inline] sock_recvmsg+0xd0/0x110 net/socket.c:801 ___sys_recvmsg+0x2b6/0x680 net/socket.c:2278 __sys_recvmmsg+0x303/0xb90 net/socket.c:2390 do_sys_recvmmsg+0x181/0x1a0 net/socket.c:2466 __do_sys_recvmmsg net/socket.c:2484 [inline] __se_sys_recvmmsg net/socket.c:2480 [inline] __x64_sys_recvmmsg+0xbe/0x150 net/socket.c:2480 do_syscall_64+0x1b9/0x820 arch/x86/entry/common.c:290 entry_SYSCALL_64_after_hwframe+0x49/0xbe The buggy address belongs to the object at ffff8801d1f6fac0 which belongs to the cache skbuff_head_cache of size 232 The buggy address is located 228 bytes inside of 232-byte region [ffff8801d1f6fac0, ffff8801d1f6fba8) The buggy address belongs to the page: page:ffffea000747dbc0 count:1 mapcount:0 mapping:ffff8801d9be7680 index:0xffff8801d1f6fe80 flags: 0x2fffc0000000100(slab) raw: 02fffc0000000100 ffffea0007346e88 ffffea000705b108 ffff8801d9be7680 raw: ffff8801d1f6fe80 ffff8801d1f6f0c0 000000010000000b 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff8801d1f6fa80: fc fc fc fc fc fc fc fc fb fb fb fb fb fb fb fb ffff8801d1f6fb00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff8801d1f6fb80: fb fb fb fb fb fc fc fc fc fc fc fc fc fc fc fc ^ ffff8801d1f6fc00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff8801d1f6fc80: fb fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Eric Dumazet Reported-by: syzbot Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/llc/af_llc.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/net/llc/af_llc.c b/net/llc/af_llc.c index b49f5afab405..2e472d5c3ea4 100644 --- a/net/llc/af_llc.c +++ b/net/llc/af_llc.c @@ -730,7 +730,6 @@ static int llc_ui_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, struct sk_buff *skb = NULL; struct sock *sk = sock->sk; struct llc_sock *llc = llc_sk(sk); - unsigned long cpu_flags; size_t copied = 0; u32 peek_seq = 0; u32 *seq, skb_len; @@ -855,9 +854,8 @@ static int llc_ui_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, goto copy_uaddr; if (!(flags & MSG_PEEK)) { - spin_lock_irqsave(&sk->sk_receive_queue.lock, cpu_flags); - sk_eat_skb(sk, skb); - spin_unlock_irqrestore(&sk->sk_receive_queue.lock, cpu_flags); + skb_unlink(skb, &sk->sk_receive_queue); + kfree_skb(skb); *seq = 0; } @@ -878,9 +876,8 @@ static int llc_ui_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, llc_cmsg_rcv(msg, skb); if (!(flags & MSG_PEEK)) { - spin_lock_irqsave(&sk->sk_receive_queue.lock, cpu_flags); - sk_eat_skb(sk, skb); - spin_unlock_irqrestore(&sk->sk_receive_queue.lock, cpu_flags); + skb_unlink(skb, &sk->sk_receive_queue); + kfree_skb(skb); *seq = 0; } -- GitLab From 97764043885cd2aa6017891948a6705e4f1086e8 Mon Sep 17 00:00:00 2001 From: Dmitry Vyukov Date: Fri, 26 Oct 2018 15:03:12 -0700 Subject: [PATCH 0093/1286] mm: don't warn about large allocations for slab commit 61448479a9f2c954cde0cfe778cb6bec5d0a748d upstream. Slub does not call kmalloc_slab() for sizes > KMALLOC_MAX_CACHE_SIZE, instead it falls back to kmalloc_large(). For slab KMALLOC_MAX_CACHE_SIZE == KMALLOC_MAX_SIZE and it calls kmalloc_slab() for all allocations relying on NULL return value for over-sized allocations. This inconsistency leads to unwanted warnings from kmalloc_slab() for over-sized allocations for slab. Returning NULL for failed allocations is the expected behavior. Make slub and slab code consistent by checking size > KMALLOC_MAX_CACHE_SIZE in slab before calling kmalloc_slab(). While we are here also fix the check in kmalloc_slab(). We should check against KMALLOC_MAX_CACHE_SIZE rather than KMALLOC_MAX_SIZE. It all kinda worked because for slab the constants are the same, and slub always checks the size against KMALLOC_MAX_CACHE_SIZE before kmalloc_slab(). But if we get there with size > KMALLOC_MAX_CACHE_SIZE anyhow bad things will happen. For example, in case of a newly introduced bug in slub code. Also move the check in kmalloc_slab() from function entry to the size > 192 case. This partially compensates for the additional check in slab code and makes slub code a bit faster (at least theoretically). Also drop __GFP_NOWARN in the warning check. This warning means a bug in slab code itself, user-passed flags have nothing to do with it. Nothing of this affects slob. Link: http://lkml.kernel.org/r/20180927171502.226522-1-dvyukov@gmail.com Signed-off-by: Dmitry Vyukov Reported-by: syzbot+87829a10073277282ad1@syzkaller.appspotmail.com Reported-by: syzbot+ef4e8fc3a06e9019bb40@syzkaller.appspotmail.com Reported-by: syzbot+6e438f4036df52cbb863@syzkaller.appspotmail.com Reported-by: syzbot+8574471d8734457d98aa@syzkaller.appspotmail.com Reported-by: syzbot+af1504df0807a083dbd9@syzkaller.appspotmail.com Acked-by: Christoph Lameter Acked-by: Vlastimil Babka Cc: Pekka Enberg Cc: David Rientjes Cc: Joonsoo Kim Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/slab.c | 4 ++++ mm/slab_common.c | 12 ++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/mm/slab.c b/mm/slab.c index 198c1e2c5358..68ab88e2920e 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -3670,6 +3670,8 @@ __do_kmalloc_node(size_t size, gfp_t flags, int node, unsigned long caller) struct kmem_cache *cachep; void *ret; + if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) + return NULL; cachep = kmalloc_slab(size, flags); if (unlikely(ZERO_OR_NULL_PTR(cachep))) return cachep; @@ -3705,6 +3707,8 @@ static __always_inline void *__do_kmalloc(size_t size, gfp_t flags, struct kmem_cache *cachep; void *ret; + if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) + return NULL; cachep = kmalloc_slab(size, flags); if (unlikely(ZERO_OR_NULL_PTR(cachep))) return cachep; diff --git a/mm/slab_common.c b/mm/slab_common.c index 91d271b90600..f6764cf162b8 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -971,18 +971,18 @@ struct kmem_cache *kmalloc_slab(size_t size, gfp_t flags) { int index; - if (unlikely(size > KMALLOC_MAX_SIZE)) { - WARN_ON_ONCE(!(flags & __GFP_NOWARN)); - return NULL; - } - if (size <= 192) { if (!size) return ZERO_SIZE_PTR; index = size_index[size_index_elem(size)]; - } else + } else { + if (unlikely(size > KMALLOC_MAX_CACHE_SIZE)) { + WARN_ON(1); + return NULL; + } index = fls(size - 1); + } #ifdef CONFIG_ZONE_DMA if (unlikely((flags & GFP_DMA))) -- GitLab From 6b43a9978a6b000cf05d19f8765eba0434817f94 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Fri, 26 Oct 2018 15:09:01 -0700 Subject: [PATCH 0094/1286] mm/memory.c: recheck page table entry with page table lock held commit ff09d7ec9786be4ad7589aa987d7dc66e2dd9160 upstream. We clear the pte temporarily during read/modify/write update of the pte. If we take a page fault while the pte is cleared, the application can get SIGBUS. One such case is with remap_pfn_range without a backing vm_ops->fault callback. do_fault will return SIGBUS in that case. cpu 0 cpu1 mprotect() ptep_modify_prot_start()/pte cleared. . . page fault. . . prep_modify_prot_commit() Fix this by taking page table lock and rechecking for pte_none. [aneesh.kumar@linux.ibm.com: fix crash observed with syzkaller run] Link: http://lkml.kernel.org/r/87va6bwlfg.fsf@linux.ibm.com Link: http://lkml.kernel.org/r/20180926031858.9692-1-aneesh.kumar@linux.ibm.com Signed-off-by: Aneesh Kumar K.V Acked-by: Kirill A. Shutemov Cc: Willem de Bruijn Cc: Eric Dumazet Cc: Ido Schimmel Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/memory.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/mm/memory.c b/mm/memory.c index 93d5d324904b..b6cfe0cf0ead 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3697,10 +3697,36 @@ static int do_fault(struct vm_fault *vmf) struct vm_area_struct *vma = vmf->vma; int ret; - /* The VMA was not fully populated on mmap() or missing VM_DONTEXPAND */ - if (!vma->vm_ops->fault) - ret = VM_FAULT_SIGBUS; - else if (!(vmf->flags & FAULT_FLAG_WRITE)) + /* + * The VMA was not fully populated on mmap() or missing VM_DONTEXPAND + */ + if (!vma->vm_ops->fault) { + /* + * If we find a migration pmd entry or a none pmd entry, which + * should never happen, return SIGBUS + */ + if (unlikely(!pmd_present(*vmf->pmd))) + ret = VM_FAULT_SIGBUS; + else { + vmf->pte = pte_offset_map_lock(vmf->vma->vm_mm, + vmf->pmd, + vmf->address, + &vmf->ptl); + /* + * Make sure this is not a temporary clearing of pte + * by holding ptl and checking again. A R/M/W update + * of pte involves: take ptl, clearing the pte so that + * we don't have concurrent modification by hardware + * followed by an update. + */ + if (unlikely(pte_none(*vmf->pte))) + ret = VM_FAULT_SIGBUS; + else + ret = VM_FAULT_NOPAGE; + + pte_unmap_unlock(vmf->pte, vmf->ptl); + } + } else if (!(vmf->flags & FAULT_FLAG_WRITE)) ret = do_read_fault(vmf); else if (!(vma->vm_flags & VM_SHARED)) ret = do_cow_fault(vmf); -- GitLab From e6ddc2c3d89c8ed3266d83254a0c11798f33502e Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 1 Oct 2018 23:24:26 -0700 Subject: [PATCH 0095/1286] tcp: do not release socket ownership in tcp_close() commit 8873c064d1de579ea23412a6d3eee972593f142b upstream. syzkaller was able to hit the WARN_ON(sock_owned_by_user(sk)); in tcp_close() While a socket is being closed, it is very possible other threads find it in rtnetlink dump. tcp_get_info() will acquire the socket lock for a short amount of time (slow = lock_sock_fast(sk)/unlock_sock_fast(sk, slow);), enough to trigger the warning. Fixes: 67db3e4bfbc9 ("tcp: no longer hold ehash lock while calling tcp_get_info()") Signed-off-by: Eric Dumazet Reported-by: syzbot Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- include/net/sock.h | 1 + net/core/sock.c | 2 +- net/ipv4/tcp.c | 11 +++-------- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 9bd5d68076d9..64a330544dad 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1452,6 +1452,7 @@ static inline void lock_sock(struct sock *sk) lock_sock_nested(sk, 0); } +void __release_sock(struct sock *sk); void release_sock(struct sock *sk); /* BH context may only use the following locking interface. */ diff --git a/net/core/sock.c b/net/core/sock.c index 68d08ed5521e..36f19458e2fe 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -2242,7 +2242,7 @@ static void __lock_sock(struct sock *sk) finish_wait(&sk->sk_lock.wq, &wait); } -static void __release_sock(struct sock *sk) +void __release_sock(struct sock *sk) __releases(&sk->sk_lock.slock) __acquires(&sk->sk_lock.slock) { diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index f9c985460faa..8109985e78a1 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2217,16 +2217,10 @@ void tcp_close(struct sock *sk, long timeout) sock_hold(sk); sock_orphan(sk); - /* It is the last release_sock in its life. It will remove backlog. */ - release_sock(sk); - - - /* Now socket is owned by kernel and we acquire BH lock - * to finish close. No need to check for user refs. - */ local_bh_disable(); bh_lock_sock(sk); - WARN_ON(sock_owned_by_user(sk)); + /* remove backlog if any, without releasing ownership. */ + __release_sock(sk); percpu_counter_inc(sk->sk_prot->orphan_count); @@ -2295,6 +2289,7 @@ void tcp_close(struct sock *sk, long timeout) out: bh_unlock_sock(sk); local_bh_enable(); + release_sock(sk); sock_put(sk); } EXPORT_SYMBOL(tcp_close); -- GitLab From c271b660b798998c926d2d62b47d0cd4d97d8d2e Mon Sep 17 00:00:00 2001 From: Parav Pandit Date: Tue, 9 Jan 2018 15:24:50 +0200 Subject: [PATCH 0096/1286] IB/core: Perform modify QP on real one commit b2bedfb39541a7e14798d066b6f8685d84c8fcf5 upstream. Currently qp->port stores the port number whenever IB_QP_PORT QP attribute mask is set (during QP state transition to INIT state). This port number should be stored for the real QP when XRC target QP is used. Follow the ib_modify_qp() implementation and hide the access to ->real_qp. Fixes: a512c2fbef9c ("IB/core: Introduce modify QP operation with udata") Signed-off-by: Parav Pandit Reviewed-by: Daniel Jurgens Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/core/verbs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c index feb80dbb5948..6d59af07d338 100644 --- a/drivers/infiniband/core/verbs.c +++ b/drivers/infiniband/core/verbs.c @@ -1285,7 +1285,7 @@ EXPORT_SYMBOL(ib_resolve_eth_dmac); /** * ib_modify_qp_with_udata - Modifies the attributes for the specified QP. - * @qp: The QP to modify. + * @ib_qp: The QP to modify. * @attr: On input, specifies the QP attributes to modify. On output, * the current values of selected QP attributes are returned. * @attr_mask: A bit-mask used to specify which attributes of the QP @@ -1294,9 +1294,10 @@ EXPORT_SYMBOL(ib_resolve_eth_dmac); * are being modified. * It returns 0 on success and returns appropriate error code on error. */ -int ib_modify_qp_with_udata(struct ib_qp *qp, struct ib_qp_attr *attr, +int ib_modify_qp_with_udata(struct ib_qp *ib_qp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata) { + struct ib_qp *qp = ib_qp->real_qp; int ret; if (attr_mask & IB_QP_AV) { -- GitLab From d84bb18ed7a29a3a571feed8ed36ee2c3e58d1bc Mon Sep 17 00:00:00 2001 From: Mathias Nyman Date: Thu, 15 Nov 2018 11:38:41 +0200 Subject: [PATCH 0097/1286] usb: xhci: Prevent bus suspend if a port connect change or polling state is detected commit 2f31a67f01a8beb22cae754c53522cb61a005750 upstream. USB3 roothub might autosuspend before a plugged USB3 device is detected, causing USB3 device enumeration failure. USB3 devices don't show up as connected and enabled until USB3 link trainig completes. On a fast booting platform with a slow USB3 link training the link might reach the connected enabled state just as the bus is suspending. If this device is discovered first time by the xhci_bus_suspend() routine it will be put to U3 suspended state like the other ports which failed to suspend earlier. The hub thread will notice the connect change and resume the bus, moving the port back to U0 This U0 -> U3 -> U0 transition right after being connected seems to be too much for some devices, causing them to first go to SS.Inactive state, and finally end up stuck in a polling state with reset asserted Fix this by failing the bus suspend if a port has a connect change or is in a polling state in xhci_bus_suspend(). Don't do any port changes until all ports are checked, buffer all port changes and only write them in the end if suspend can proceed Cc: stable@vger.kernel.org Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-hub.c | 60 ++++++++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 14 deletions(-) diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index 4f612b5d0f94..a2e350d28c05 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -1481,13 +1481,16 @@ int xhci_bus_suspend(struct usb_hcd *hcd) __le32 __iomem **port_array; struct xhci_bus_state *bus_state; unsigned long flags; + u32 portsc_buf[USB_MAXCHILDREN]; + bool wake_enabled; max_ports = xhci_get_ports(hcd, &port_array); bus_state = &xhci->bus_state[hcd_index(hcd)]; + wake_enabled = hcd->self.root_hub->do_remote_wakeup; spin_lock_irqsave(&xhci->lock, flags); - if (hcd->self.root_hub->do_remote_wakeup) { + if (wake_enabled) { if (bus_state->resuming_ports || /* USB2 */ bus_state->port_remote_wakeup) { /* USB3 */ spin_unlock_irqrestore(&xhci->lock, flags); @@ -1495,26 +1498,36 @@ int xhci_bus_suspend(struct usb_hcd *hcd) return -EBUSY; } } - - port_index = max_ports; + /* + * Prepare ports for suspend, but don't write anything before all ports + * are checked and we know bus suspend can proceed + */ bus_state->bus_suspended = 0; + port_index = max_ports; while (port_index--) { - /* suspend the port if the port is not suspended */ u32 t1, t2; - int slot_id; t1 = readl(port_array[port_index]); t2 = xhci_port_state_to_neutral(t1); + portsc_buf[port_index] = 0; - if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { - xhci_dbg(xhci, "port %d not suspended\n", port_index); - slot_id = xhci_find_slot_id_by_port(hcd, xhci, - port_index + 1); - if (slot_id) { + /* Bail out if a USB3 port has a new device in link training */ + if ((t1 & PORT_PLS_MASK) == XDEV_POLLING) { + bus_state->bus_suspended = 0; + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_dbg(xhci, "Bus suspend bailout, port in polling\n"); + return -EBUSY; + } + + /* suspend ports in U0, or bail out for new connect changes */ + if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { + if ((t1 & PORT_CSC) && wake_enabled) { + bus_state->bus_suspended = 0; spin_unlock_irqrestore(&xhci->lock, flags); - xhci_stop_device(xhci, slot_id, 1); - spin_lock_irqsave(&xhci->lock, flags); + xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); + return -EBUSY; } + xhci_dbg(xhci, "port %d not suspended\n", port_index); t2 &= ~PORT_PLS_MASK; t2 |= PORT_LINK_STROBE | XDEV_U3; set_bit(port_index, &bus_state->bus_suspended); @@ -1523,7 +1536,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd) * including the USB 3.0 roothub, but only if CONFIG_PM * is enabled, so also enable remote wake here. */ - if (hcd->self.root_hub->do_remote_wakeup) { + if (wake_enabled) { if (t1 & PORT_CONNECT) { t2 |= PORT_WKOC_E | PORT_WKDISC_E; t2 &= ~PORT_WKCONN_E; @@ -1543,7 +1556,26 @@ int xhci_bus_suspend(struct usb_hcd *hcd) t1 = xhci_port_state_to_neutral(t1); if (t1 != t2) - writel(t2, port_array[port_index]); + portsc_buf[port_index] = t2; + } + + /* write port settings, stopping and suspending ports if needed */ + port_index = max_ports; + while (port_index--) { + if (!portsc_buf[port_index]) + continue; + if (test_bit(port_index, &bus_state->bus_suspended)) { + int slot_id; + + slot_id = xhci_find_slot_id_by_port(hcd, xhci, + port_index + 1); + if (slot_id) { + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_stop_device(xhci, slot_id, 1); + spin_lock_irqsave(&xhci->lock, flags); + } + } + writel(portsc_buf[port_index], port_array[port_index]); } hcd->state = HC_STATE_SUSPENDED; bus_state->next_statechange = jiffies + msecs_to_jiffies(10); -- GitLab From e51b0b1c1f015c72315a2706e043cd9665af73cc Mon Sep 17 00:00:00 2001 From: "Y.C. Chen" Date: Wed, 3 Oct 2018 14:57:47 +0800 Subject: [PATCH 0098/1286] drm/ast: change resolution may cause screen blurred commit 1a37bd823891568f8721989aed0615835632d81a upstream. The value of pitches is not correct while calling mode_set. The issue we found so far on following system: - Debian8 with XFCE Desktop - Ubuntu with KDE Desktop - SUSE15 with KDE Desktop Signed-off-by: Y.C. Chen Cc: Tested-by: Jean Delvare Reviewed-by: Jean Delvare Signed-off-by: Dave Airlie Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/ast/ast_mode.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index e9f1e6fe7b94..604ff42121f8 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -568,6 +568,7 @@ static int ast_crtc_do_set_base(struct drm_crtc *crtc, } ast_bo_unreserve(bo); + ast_set_offset_reg(crtc); ast_set_start_address_crt1(crtc, (u32)gpu_addr); return 0; -- GitLab From ffc3c0ffbb93be9b1b75f0a71ba38501039f5180 Mon Sep 17 00:00:00 2001 From: "Y.C. Chen" Date: Tue, 30 Oct 2018 11:34:46 +0800 Subject: [PATCH 0099/1286] drm/ast: fixed cursor may disappear sometimes commit 7989b9ee8bafe5cc625381dd0c3c4586de27ca26 upstream. Signed-off-by: Y.C. Chen Cc: Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/ast/ast_mode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 604ff42121f8..fae1176b2472 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -1255,7 +1255,7 @@ static int ast_cursor_move(struct drm_crtc *crtc, ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07)); /* dummy write to fire HWC */ - ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00); + ast_show_cursor(crtc); return 0; } -- GitLab From dca24b512763930963408ea5c78a2f223a73a2a8 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 15 Nov 2018 11:42:16 +0100 Subject: [PATCH 0100/1286] drm/ast: Remove existing framebuffers before loading driver commit 5478ad10e7850ce3d8b7056db05ddfa3c9ddad9a upstream. If vesafb attaches to the AST device, it configures the framebuffer memory for uncached access by default. When ast.ko later tries to attach itself to the device, it wants to use write-combining on the framebuffer memory, but vesefb's existing configuration for uncached access takes precedence. This results in reduced performance. Removing the framebuffer's configuration before loding the AST driver fixes the problem. Other DRM drivers already contain equivalent code. Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1112963 Signed-off-by: Thomas Zimmermann Cc: Tested-by: Y.C. Chen Reviewed-by: Jean Delvare Tested-by: Jean Delvare Signed-off-by: Dave Airlie Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/ast/ast_drv.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index 69dab82a3771..bf589c53b908 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -60,8 +60,29 @@ static const struct pci_device_id pciidlist[] = { MODULE_DEVICE_TABLE(pci, pciidlist); +static void ast_kick_out_firmware_fb(struct pci_dev *pdev) +{ + struct apertures_struct *ap; + bool primary = false; + + ap = alloc_apertures(1); + if (!ap) + return; + + ap->ranges[0].base = pci_resource_start(pdev, 0); + ap->ranges[0].size = pci_resource_len(pdev, 0); + +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; +#endif + drm_fb_helper_remove_conflicting_framebuffers(ap, "astdrmfb", primary); + kfree(ap); +} + static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { + ast_kick_out_firmware_fb(pdev); + return drm_get_pci_dev(pdev, ent, &driver); } -- GitLab From b3f1f493529e060fd3e9d4fe5b406f8379b24d71 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 31 Oct 2018 10:37:46 +0100 Subject: [PATCH 0101/1286] can: dev: can_get_echo_skb(): factor out non sending code to __can_get_echo_skb() commit a4310fa2f24687888ce80fdb0e88583561a23700 upstream. This patch factors out all non sending parts of can_get_echo_skb() into a seperate function __can_get_echo_skb(), so that it can be re-used in an upcoming patch. Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/dev.c | 36 +++++++++++++++++++++++++----------- include/linux/can/dev.h | 1 + 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index b6a681bce400..ae08bc6e7267 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c @@ -476,14 +476,7 @@ void can_put_echo_skb(struct sk_buff *skb, struct net_device *dev, } EXPORT_SYMBOL_GPL(can_put_echo_skb); -/* - * Get the skb from the stack and loop it back locally - * - * The function is typically called when the TX done interrupt - * is handled in the device driver. The driver must protect - * access to priv->echo_skb, if necessary. - */ -unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx) +struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 *len_ptr) { struct can_priv *priv = netdev_priv(dev); @@ -494,13 +487,34 @@ unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx) struct can_frame *cf = (struct can_frame *)skb->data; u8 dlc = cf->can_dlc; - netif_rx(priv->echo_skb[idx]); + *len_ptr = dlc; priv->echo_skb[idx] = NULL; - return dlc; + return skb; } - return 0; + return NULL; +} + +/* + * Get the skb from the stack and loop it back locally + * + * The function is typically called when the TX done interrupt + * is handled in the device driver. The driver must protect + * access to priv->echo_skb, if necessary. + */ +unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx) +{ + struct sk_buff *skb; + u8 len; + + skb = __can_get_echo_skb(dev, idx, &len); + if (!skb) + return 0; + + netif_rx(skb); + + return len; } EXPORT_SYMBOL_GPL(can_get_echo_skb); diff --git a/include/linux/can/dev.h b/include/linux/can/dev.h index 61f1cf2d9f44..c0c0b992210e 100644 --- a/include/linux/can/dev.h +++ b/include/linux/can/dev.h @@ -163,6 +163,7 @@ void can_change_state(struct net_device *dev, struct can_frame *cf, void can_put_echo_skb(struct sk_buff *skb, struct net_device *dev, unsigned int idx); +struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 *len_ptr); unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx); void can_free_echo_skb(struct net_device *dev, unsigned int idx); -- GitLab From 3f6b2bbbee20a5aa52eed1aaea65cdab98aed8c6 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 31 Oct 2018 11:08:21 +0100 Subject: [PATCH 0102/1286] can: dev: __can_get_echo_skb(): replace struct can_frame by canfd_frame to access frame length commit 200f5c49f7a2cd694436bfc6cb0662b794c96736 upstream. This patch replaces the use of "struct can_frame::can_dlc" by "struct canfd_frame::len" to access the frame's length. As it is ensured that both structures have a compatible memory layout for this member this is no functional change. Futher, this compatibility is documented in a comment. Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/dev.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index ae08bc6e7267..7900d5a39989 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c @@ -483,11 +483,14 @@ struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 BUG_ON(idx >= priv->echo_skb_max); if (priv->echo_skb[idx]) { + /* Using "struct canfd_frame::len" for the frame + * length is supported on both CAN and CANFD frames. + */ struct sk_buff *skb = priv->echo_skb[idx]; - struct can_frame *cf = (struct can_frame *)skb->data; - u8 dlc = cf->can_dlc; + struct canfd_frame *cf = (struct canfd_frame *)skb->data; + u8 len = cf->len; - *len_ptr = dlc; + *len_ptr = len; priv->echo_skb[idx] = NULL; return skb; -- GitLab From bf991335b02d62e067e09471b15cf2216d54d5cf Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 31 Oct 2018 14:05:26 +0100 Subject: [PATCH 0103/1286] can: dev: __can_get_echo_skb(): Don't crash the kernel if can_priv::echo_skb is accessed out of bounds commit e7a6994d043a1e31d5b17706a22ce33d2a3e4cdc upstream. If the "struct can_priv::echo_skb" is accessed out of bounds would lead to a kernel crash. Better print a sensible warning message instead and try to recover. Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/dev.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index 7900d5a39989..7d61d8801220 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c @@ -480,7 +480,11 @@ struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 { struct can_priv *priv = netdev_priv(dev); - BUG_ON(idx >= priv->echo_skb_max); + if (idx >= priv->echo_skb_max) { + netdev_err(dev, "%s: BUG! Trying to access can_priv::echo_skb out of bounds (%u/max %u)\n", + __func__, idx, priv->echo_skb_max); + return NULL; + } if (priv->echo_skb[idx]) { /* Using "struct canfd_frame::len" for the frame -- GitLab From 906ed1bdf850851b3433e4f5521b406651643b27 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 31 Oct 2018 14:15:13 +0100 Subject: [PATCH 0104/1286] can: dev: __can_get_echo_skb(): print error message, if trying to echo non existing skb commit 7da11ba5c5066dadc2e96835a6233d56d7b7764a upstream. Prior to echoing a successfully transmitted CAN frame (by calling can_get_echo_skb()), CAN drivers have to put the CAN frame (by calling can_put_echo_skb() in the transmit function). These put and get function take an index as parameter, which is used to identify the CAN frame. A driver calling can_get_echo_skb() with a index not pointing to a skb is a BUG, so add an appropriate error message. Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/dev.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index 7d61d8801220..035daca63168 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c @@ -479,6 +479,8 @@ EXPORT_SYMBOL_GPL(can_put_echo_skb); struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 *len_ptr) { struct can_priv *priv = netdev_priv(dev); + struct sk_buff *skb = priv->echo_skb[idx]; + struct canfd_frame *cf; if (idx >= priv->echo_skb_max) { netdev_err(dev, "%s: BUG! Trying to access can_priv::echo_skb out of bounds (%u/max %u)\n", @@ -486,21 +488,20 @@ struct sk_buff *__can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 return NULL; } - if (priv->echo_skb[idx]) { - /* Using "struct canfd_frame::len" for the frame - * length is supported on both CAN and CANFD frames. - */ - struct sk_buff *skb = priv->echo_skb[idx]; - struct canfd_frame *cf = (struct canfd_frame *)skb->data; - u8 len = cf->len; - - *len_ptr = len; - priv->echo_skb[idx] = NULL; - - return skb; + if (!skb) { + netdev_err(dev, "%s: BUG! Trying to echo non existing skb: can_priv::echo_skb[%u]\n", + __func__, idx); + return NULL; } - return NULL; + /* Using "struct canfd_frame::len" for the frame + * length is supported on both CAN and CANFD frames. + */ + cf = (struct canfd_frame *)skb->data; + *len_ptr = cf->len; + priv->echo_skb[idx] = NULL; + + return skb; } /* -- GitLab From bb8813be5cc7a0134e5bd8584005b189223f237c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 Sep 2018 11:40:38 +0200 Subject: [PATCH 0105/1286] can: rx-offload: introduce can_rx_offload_get_echo_skb() and can_rx_offload_queue_sorted() functions commit 55059f2b7f868cd43b3ad30e28e18347e1b46ace upstream. Current CAN framework can't guarantee proper/chronological order of RX and TX-ECHO messages. To make this possible, drivers should use this functions instead of can_get_echo_skb(). Signed-off-by: Oleksij Rempel Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/rx-offload.c | 46 ++++++++++++++++++++++++++++++++++ include/linux/can/rx-offload.h | 4 +++ 2 files changed, 50 insertions(+) diff --git a/drivers/net/can/rx-offload.c b/drivers/net/can/rx-offload.c index f394f77d7528..61b30bfffacc 100644 --- a/drivers/net/can/rx-offload.c +++ b/drivers/net/can/rx-offload.c @@ -209,6 +209,52 @@ int can_rx_offload_irq_offload_fifo(struct can_rx_offload *offload) } EXPORT_SYMBOL_GPL(can_rx_offload_irq_offload_fifo); +int can_rx_offload_queue_sorted(struct can_rx_offload *offload, + struct sk_buff *skb, u32 timestamp) +{ + struct can_rx_offload_cb *cb; + unsigned long flags; + + if (skb_queue_len(&offload->skb_queue) > + offload->skb_queue_len_max) + return -ENOMEM; + + cb = can_rx_offload_get_cb(skb); + cb->timestamp = timestamp; + + spin_lock_irqsave(&offload->skb_queue.lock, flags); + __skb_queue_add_sort(&offload->skb_queue, skb, can_rx_offload_compare); + spin_unlock_irqrestore(&offload->skb_queue.lock, flags); + + can_rx_offload_schedule(offload); + + return 0; +} +EXPORT_SYMBOL_GPL(can_rx_offload_queue_sorted); + +unsigned int can_rx_offload_get_echo_skb(struct can_rx_offload *offload, + unsigned int idx, u32 timestamp) +{ + struct net_device *dev = offload->dev; + struct net_device_stats *stats = &dev->stats; + struct sk_buff *skb; + u8 len; + int err; + + skb = __can_get_echo_skb(dev, idx, &len); + if (!skb) + return 0; + + err = can_rx_offload_queue_sorted(offload, skb, timestamp); + if (err) { + stats->rx_errors++; + stats->tx_fifo_errors++; + } + + return len; +} +EXPORT_SYMBOL_GPL(can_rx_offload_get_echo_skb); + int can_rx_offload_irq_queue_err_skb(struct can_rx_offload *offload, struct sk_buff *skb) { if (skb_queue_len(&offload->skb_queue) > diff --git a/include/linux/can/rx-offload.h b/include/linux/can/rx-offload.h index cb31683bbe15..01a7c9e5d8d8 100644 --- a/include/linux/can/rx-offload.h +++ b/include/linux/can/rx-offload.h @@ -41,6 +41,10 @@ int can_rx_offload_add_timestamp(struct net_device *dev, struct can_rx_offload * int can_rx_offload_add_fifo(struct net_device *dev, struct can_rx_offload *offload, unsigned int weight); int can_rx_offload_irq_offload_timestamp(struct can_rx_offload *offload, u64 reg); int can_rx_offload_irq_offload_fifo(struct can_rx_offload *offload); +int can_rx_offload_queue_sorted(struct can_rx_offload *offload, + struct sk_buff *skb, u32 timestamp); +unsigned int can_rx_offload_get_echo_skb(struct can_rx_offload *offload, + unsigned int idx, u32 timestamp); int can_rx_offload_irq_queue_err_skb(struct can_rx_offload *offload, struct sk_buff *skb); void can_rx_offload_reset(struct can_rx_offload *offload); void can_rx_offload_del(struct can_rx_offload *offload); -- GitLab From 30b996ac6e61e9a39d6bec70ec4e39daeeeff8b6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 Sep 2018 11:40:40 +0200 Subject: [PATCH 0106/1286] can: rx-offload: rename can_rx_offload_irq_queue_err_skb() to can_rx_offload_queue_tail() commit 4530ec36bb1e0d24f41c33229694adacda3d5d89 upstream. This function has nothing todo with error. Signed-off-by: Oleksij Rempel Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/flexcan.c | 4 ++-- drivers/net/can/rx-offload.c | 5 +++-- include/linux/can/rx-offload.h | 3 ++- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index ed8a2a7ce500..9ef501fd153f 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -599,7 +599,7 @@ static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr) if (tx_errors) dev->stats.tx_errors++; - can_rx_offload_irq_queue_err_skb(&priv->offload, skb); + can_rx_offload_queue_tail(&priv->offload, skb); } static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) @@ -639,7 +639,7 @@ static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) if (unlikely(new_state == CAN_STATE_BUS_OFF)) can_bus_off(dev); - can_rx_offload_irq_queue_err_skb(&priv->offload, skb); + can_rx_offload_queue_tail(&priv->offload, skb); } static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) diff --git a/drivers/net/can/rx-offload.c b/drivers/net/can/rx-offload.c index 61b30bfffacc..d227db45fec9 100644 --- a/drivers/net/can/rx-offload.c +++ b/drivers/net/can/rx-offload.c @@ -255,7 +255,8 @@ unsigned int can_rx_offload_get_echo_skb(struct can_rx_offload *offload, } EXPORT_SYMBOL_GPL(can_rx_offload_get_echo_skb); -int can_rx_offload_irq_queue_err_skb(struct can_rx_offload *offload, struct sk_buff *skb) +int can_rx_offload_queue_tail(struct can_rx_offload *offload, + struct sk_buff *skb) { if (skb_queue_len(&offload->skb_queue) > offload->skb_queue_len_max) @@ -266,7 +267,7 @@ int can_rx_offload_irq_queue_err_skb(struct can_rx_offload *offload, struct sk_b return 0; } -EXPORT_SYMBOL_GPL(can_rx_offload_irq_queue_err_skb); +EXPORT_SYMBOL_GPL(can_rx_offload_queue_tail); static int can_rx_offload_init_queue(struct net_device *dev, struct can_rx_offload *offload, unsigned int weight) { diff --git a/include/linux/can/rx-offload.h b/include/linux/can/rx-offload.h index 01a7c9e5d8d8..8268811a697e 100644 --- a/include/linux/can/rx-offload.h +++ b/include/linux/can/rx-offload.h @@ -45,7 +45,8 @@ int can_rx_offload_queue_sorted(struct can_rx_offload *offload, struct sk_buff *skb, u32 timestamp); unsigned int can_rx_offload_get_echo_skb(struct can_rx_offload *offload, unsigned int idx, u32 timestamp); -int can_rx_offload_irq_queue_err_skb(struct can_rx_offload *offload, struct sk_buff *skb); +int can_rx_offload_queue_tail(struct can_rx_offload *offload, + struct sk_buff *skb); void can_rx_offload_reset(struct can_rx_offload *offload); void can_rx_offload_del(struct can_rx_offload *offload); void can_rx_offload_enable(struct can_rx_offload *offload); -- GitLab From 9af977aeef27001698133948fd44fa7e59a5901d Mon Sep 17 00:00:00 2001 From: Oliver Hartkopp Date: Wed, 24 Oct 2018 10:27:12 +0200 Subject: [PATCH 0107/1286] can: raw: check for CAN FD capable netdev in raw_sendmsg() commit a43608fa77213ad5ac5f75994254b9f65d57cfa0 upstream. When the socket is CAN FD enabled it can handle CAN FD frame transmissions. Add an additional check in raw_sendmsg() as a CAN2.0 CAN driver (non CAN FD) should never see a CAN FD frame. Due to the commonly used can_dropped_invalid_skb() function the CAN 2.0 driver would drop that CAN FD frame anyway - but with this patch the user gets a proper -EINVAL return code. Signed-off-by: Oliver Hartkopp Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- net/can/raw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/net/can/raw.c b/net/can/raw.c index 864c80dbdb72..e1f26441b49a 100644 --- a/net/can/raw.c +++ b/net/can/raw.c @@ -745,18 +745,19 @@ static int raw_sendmsg(struct socket *sock, struct msghdr *msg, size_t size) } else ifindex = ro->ifindex; - if (ro->fd_frames) { + dev = dev_get_by_index(sock_net(sk), ifindex); + if (!dev) + return -ENXIO; + + err = -EINVAL; + if (ro->fd_frames && dev->mtu == CANFD_MTU) { if (unlikely(size != CANFD_MTU && size != CAN_MTU)) - return -EINVAL; + goto put_dev; } else { if (unlikely(size != CAN_MTU)) - return -EINVAL; + goto put_dev; } - dev = dev_get_by_index(sock_net(sk), ifindex); - if (!dev) - return -ENXIO; - skb = sock_alloc_send_skb(sk, size + sizeof(struct can_skb_priv), msg->msg_flags & MSG_DONTWAIT, &err); if (!skb) -- GitLab From 7d0724cecb0ebfcf161277fc4c44616a2f9d1e0c Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 27 Oct 2018 10:36:54 +0200 Subject: [PATCH 0108/1286] can: hi311x: Use level-triggered interrupt commit f164d0204b1156a7e0d8d1622c1a8d25752befec upstream. If the hi3110 shares the SPI bus with another traffic-intensive device and packets are received in high volume (by a separate machine sending with "cangen -g 0 -i -x"), reception stops after a few minutes and the counter in /proc/interrupts stops incrementing. Bus state is "active". Bringing the interface down and back up reconvenes the reception. The issue is not observed when the hi3110 is the sole device on the SPI bus. Using a level-triggered interrupt makes the issue go away and lets the hi3110 successfully receive 2 GByte over the course of 5 days while a ks8851 Ethernet chip on the same SPI bus handles 6 GByte of traffic. Unfortunately the hi3110 datasheet is mum on the trigger type. The pin description on page 3 only specifies the polarity (active high): http://www.holtic.com/documents/371-hi-3110_v-rev-kpdf.do Cc: Mathias Duckeck Cc: Akshay Bhat Cc: Casey Fitzpatrick Signed-off-by: Lukas Wunner Cc: linux-stable Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/net/can/holt_hi311x.txt | 2 +- drivers/net/can/spi/hi311x.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/holt_hi311x.txt b/Documentation/devicetree/bindings/net/can/holt_hi311x.txt index 23aa94eab207..4e0ec14f7abf 100644 --- a/Documentation/devicetree/bindings/net/can/holt_hi311x.txt +++ b/Documentation/devicetree/bindings/net/can/holt_hi311x.txt @@ -18,7 +18,7 @@ Example: reg = <1>; clocks = <&clk32m>; interrupt-parent = <&gpio4>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; vdd-supply = <®5v0>; xceiver-supply = <®5v0>; }; diff --git a/drivers/net/can/spi/hi311x.c b/drivers/net/can/spi/hi311x.c index 53e320c92a8b..ddaf46239e39 100644 --- a/drivers/net/can/spi/hi311x.c +++ b/drivers/net/can/spi/hi311x.c @@ -760,7 +760,7 @@ static int hi3110_open(struct net_device *net) { struct hi3110_priv *priv = netdev_priv(net); struct spi_device *spi = priv->spi; - unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_RISING; + unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; int ret; ret = open_candev(net); -- GitLab From 240ec6ca4b9a2f05bf1190e37c637820fcfbeecd Mon Sep 17 00:00:00 2001 From: "Michael J. Ruhl" Date: Mon, 10 Sep 2018 09:39:03 -0700 Subject: [PATCH 0109/1286] IB/hfi1: Eliminate races in the SDMA send error path commit a0e0cb82804a6a21d9067022c2dfdf80d11da429 upstream. pq_update() can only be called in two places: from the completion function when the complete (npkts) sequence of packets has been submitted and processed, or from setup function if a subset of the packets were submitted (i.e. the error path). Currently both paths can call pq_update() if an error occurrs. This race will cause the n_req value to go negative, hanging file_close(), or cause a crash by freeing the txlist more than once. Several variables are used to determine SDMA send state. Most of these are unnecessary, and have code inspectible races between the setup function and the completion function, in both the send path and the error path. The request 'status' value can be set by the setup or by the completion function. This is code inspectibly racy. Since the status is not needed in the completion code or by the caller it has been removed. The request 'done' value races between usage by the setup and the completion function. The completion function does not need this. When the number of processed packets matches npkts, it is done. The 'has_error' value races between usage of the setup and the completion function. This can cause incorrect error handling and leave the n_req in an incorrect value (i.e. negative). Simplify the code by removing all of the unneeded state checks and variables. Clean up iovs node when it is freed. Eliminate race conditions in the error path: If all packets are submitted, the completion handler will set the completion status correctly (ok or aborted). If all packets are not submitted, the caller must wait until the submitted packets have completed, and then set the completion status. These two change eliminate the race condition in the error path. Reviewed-by: Mitko Haralanov Reviewed-by: Mike Marciniszyn Signed-off-by: Michael J. Ruhl Signed-off-by: Dennis Dalessandro Signed-off-by: Jason Gunthorpe Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/hfi1/user_sdma.c | 87 ++++++++++++-------------- drivers/infiniband/hw/hfi1/user_sdma.h | 3 - 2 files changed, 39 insertions(+), 51 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c index 8c954a0ae3b6..c14ec04f2a89 100644 --- a/drivers/infiniband/hw/hfi1/user_sdma.c +++ b/drivers/infiniband/hw/hfi1/user_sdma.c @@ -328,7 +328,6 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, u8 opcode, sc, vl; u16 pkey; u32 slid; - int req_queued = 0; u16 dlid; u32 selector; @@ -392,7 +391,6 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, req->data_len = 0; req->pq = pq; req->cq = cq; - req->status = -1; req->ahg_idx = -1; req->iov_idx = 0; req->sent = 0; @@ -400,12 +398,14 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, req->seqcomp = 0; req->seqsubmitted = 0; req->tids = NULL; - req->done = 0; req->has_error = 0; INIT_LIST_HEAD(&req->txps); memcpy(&req->info, &info, sizeof(info)); + /* The request is initialized, count it */ + atomic_inc(&pq->n_reqs); + if (req_opcode(info.ctrl) == EXPECTED) { /* expected must have a TID info and at least one data vector */ if (req->data_iovs < 2) { @@ -500,7 +500,6 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, ret = pin_vector_pages(req, &req->iovs[i]); if (ret) { req->data_iovs = i; - req->status = ret; goto free_req; } req->data_len += req->iovs[i].iov.iov_len; @@ -561,14 +560,10 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, req->ahg_idx = sdma_ahg_alloc(req->sde); set_comp_state(pq, cq, info.comp_idx, QUEUED, 0); - atomic_inc(&pq->n_reqs); - req_queued = 1; /* Send the first N packets in the request to buy us some time */ ret = user_sdma_send_pkts(req, pcount); - if (unlikely(ret < 0 && ret != -EBUSY)) { - req->status = ret; + if (unlikely(ret < 0 && ret != -EBUSY)) goto free_req; - } /* * It is possible that the SDMA engine would have processed all the @@ -588,14 +583,8 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, while (req->seqsubmitted != req->info.npkts) { ret = user_sdma_send_pkts(req, pcount); if (ret < 0) { - if (ret != -EBUSY) { - req->status = ret; - WRITE_ONCE(req->has_error, 1); - if (ACCESS_ONCE(req->seqcomp) == - req->seqsubmitted - 1) - goto free_req; - return ret; - } + if (ret != -EBUSY) + goto free_req; wait_event_interruptible_timeout( pq->busy.wait_dma, (pq->state == SDMA_PKT_Q_ACTIVE), @@ -606,10 +595,19 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, *count += idx; return 0; free_req: - user_sdma_free_request(req, true); - if (req_queued) + /* + * If the submitted seqsubmitted == npkts, the completion routine + * controls the final state. If sequbmitted < npkts, wait for any + * outstanding packets to finish before cleaning up. + */ + if (req->seqsubmitted < req->info.npkts) { + if (req->seqsubmitted) + wait_event(pq->busy.wait_dma, + (req->seqcomp == req->seqsubmitted - 1)); + user_sdma_free_request(req, true); pq_update(pq); - set_comp_state(pq, cq, info.comp_idx, ERROR, req->status); + set_comp_state(pq, cq, info.comp_idx, ERROR, ret); + } return ret; } @@ -917,7 +915,6 @@ static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts) ret = sdma_send_txlist(req->sde, &pq->busy, &req->txps, &count); req->seqsubmitted += count; if (req->seqsubmitted == req->info.npkts) { - WRITE_ONCE(req->done, 1); /* * The txreq has already been submitted to the HW queue * so we can free the AHG entry now. Corruption will not @@ -1347,11 +1344,15 @@ static int set_txreq_header_ahg(struct user_sdma_request *req, return diff; } -/* - * SDMA tx request completion callback. Called when the SDMA progress - * state machine gets notification that the SDMA descriptors for this - * tx request have been processed by the DMA engine. Called in - * interrupt context. +/** + * user_sdma_txreq_cb() - SDMA tx request completion callback. + * @txreq: valid sdma tx request + * @status: success/failure of request + * + * Called when the SDMA progress state machine gets notification that + * the SDMA descriptors for this tx request have been processed by the + * DMA engine. Called in interrupt context. + * Only do work on completed sequences. */ static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status) { @@ -1360,7 +1361,7 @@ static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status) struct user_sdma_request *req; struct hfi1_user_sdma_pkt_q *pq; struct hfi1_user_sdma_comp_q *cq; - u16 idx; + enum hfi1_sdma_comp_state state = COMPLETE; if (!tx->req) return; @@ -1373,31 +1374,19 @@ static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status) SDMA_DBG(req, "SDMA completion with error %d", status); WRITE_ONCE(req->has_error, 1); + state = ERROR; } req->seqcomp = tx->seqnum; kmem_cache_free(pq->txreq_cache, tx); - tx = NULL; - - idx = req->info.comp_idx; - if (req->status == -1 && status == SDMA_TXREQ_S_OK) { - if (req->seqcomp == req->info.npkts - 1) { - req->status = 0; - user_sdma_free_request(req, false); - pq_update(pq); - set_comp_state(pq, cq, idx, COMPLETE, 0); - } - } else { - if (status != SDMA_TXREQ_S_OK) - req->status = status; - if (req->seqcomp == (ACCESS_ONCE(req->seqsubmitted) - 1) && - (READ_ONCE(req->done) || - READ_ONCE(req->has_error))) { - user_sdma_free_request(req, false); - pq_update(pq); - set_comp_state(pq, cq, idx, ERROR, req->status); - } - } + + /* sequence isn't complete? We are done */ + if (req->seqcomp != req->info.npkts - 1) + return; + + user_sdma_free_request(req, false); + set_comp_state(pq, cq, req->info.comp_idx, state, status); + pq_update(pq); } static inline void pq_update(struct hfi1_user_sdma_pkt_q *pq) @@ -1430,6 +1419,8 @@ static void user_sdma_free_request(struct user_sdma_request *req, bool unpin) if (!node) continue; + req->iovs[i].node = NULL; + if (unpin) hfi1_mmu_rb_remove(req->pq->handler, &node->rb); diff --git a/drivers/infiniband/hw/hfi1/user_sdma.h b/drivers/infiniband/hw/hfi1/user_sdma.h index 9b8bb5634c0d..5af52334b7dc 100644 --- a/drivers/infiniband/hw/hfi1/user_sdma.h +++ b/drivers/infiniband/hw/hfi1/user_sdma.h @@ -196,8 +196,6 @@ struct user_sdma_request { /* Writeable fields shared with interrupt */ u64 seqcomp ____cacheline_aligned_in_smp; u64 seqsubmitted; - /* status of the last txreq completed */ - int status; /* Send side fields */ struct list_head txps ____cacheline_aligned_in_smp; @@ -219,7 +217,6 @@ struct user_sdma_request { u16 tididx; /* progress index moving along the iovs array */ u8 iov_idx; - u8 done; u8 has_error; struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ]; -- GitLab From 6dce186b48bbf6abbe207a9f18deaaa6b6363d22 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 23 Oct 2018 18:03:19 +0200 Subject: [PATCH 0110/1286] pinctrl: meson: fix pinconf bias disable [ Upstream commit e39f9dd8206ad66992ac0e6218ef1ba746f2cce9 ] If a bias is enabled on a pin of an Amlogic SoC, calling .pin_config_set() with PIN_CONFIG_BIAS_DISABLE will not disable the bias. Instead it will force a pull-down bias on the pin. Instead of the pull type register bank, the driver should access the pull enable register bank. Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs") Signed-off-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/meson/pinctrl-meson.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 66ed70c12733..6c43322dbb97 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -273,7 +273,7 @@ static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, dev_dbg(pc->dev, "pin %u: disable bias\n", pin); meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(pc->reg_pull, reg, + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); if (ret) return ret; -- GitLab From 6af32ab13852790718ed3fb63cd09fc4d3e8afa3 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 6 Nov 2018 19:49:34 -0600 Subject: [PATCH 0111/1286] KVM: PPC: Move and undef TRACE_INCLUDE_PATH/FILE [ Upstream commit 28c5bcf74fa07c25d5bd118d1271920f51ce2a98 ] TRACE_INCLUDE_PATH and TRACE_INCLUDE_FILE are used by , so like that #include, they should be outside #ifdef protection. They also need to be #undefed before defining, in case multiple trace headers are included by the same C file. This became the case on book3e after commit cf4a6085151a ("powerpc/mm: Add missing tracepoint for tlbie"), leading to the following build error: CC arch/powerpc/kvm/powerpc.o In file included from arch/powerpc/kvm/powerpc.c:51:0: arch/powerpc/kvm/trace.h:9:0: error: "TRACE_INCLUDE_PATH" redefined [-Werror] #define TRACE_INCLUDE_PATH . ^ In file included from arch/powerpc/kvm/../mm/mmu_decl.h:25:0, from arch/powerpc/kvm/powerpc.c:48: ./arch/powerpc/include/asm/trace.h:224:0: note: this is the location of the previous definition #define TRACE_INCLUDE_PATH asm ^ cc1: all warnings being treated as errors Reported-by: Christian Zigotzky Signed-off-by: Scott Wood Signed-off-by: Michael Ellerman Signed-off-by: Sasha Levin --- arch/powerpc/kvm/trace.h | 8 ++++++-- arch/powerpc/kvm/trace_booke.h | 9 +++++++-- arch/powerpc/kvm/trace_hv.h | 9 +++++++-- arch/powerpc/kvm/trace_pr.h | 9 +++++++-- 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h index 491b0f715d6b..ea1d7c808319 100644 --- a/arch/powerpc/kvm/trace.h +++ b/arch/powerpc/kvm/trace.h @@ -6,8 +6,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE trace /* * Tracepoint for guest mode entry. @@ -120,4 +118,10 @@ TRACE_EVENT(kvm_check_requests, #endif /* _TRACE_KVM_H */ /* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE + +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace + #include diff --git a/arch/powerpc/kvm/trace_booke.h b/arch/powerpc/kvm/trace_booke.h index ac640e81fdc5..3837842986aa 100644 --- a/arch/powerpc/kvm/trace_booke.h +++ b/arch/powerpc/kvm/trace_booke.h @@ -6,8 +6,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm_booke -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE trace_booke #define kvm_trace_symbol_exit \ {0, "CRITICAL"}, \ @@ -218,4 +216,11 @@ TRACE_EVENT(kvm_booke_queue_irqprio, #endif /* This part must be outside protection */ + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE + +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace_booke + #include diff --git a/arch/powerpc/kvm/trace_hv.h b/arch/powerpc/kvm/trace_hv.h index bcfe8a987f6a..8a1e3b0047f1 100644 --- a/arch/powerpc/kvm/trace_hv.h +++ b/arch/powerpc/kvm/trace_hv.h @@ -9,8 +9,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm_hv -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE trace_hv #define kvm_trace_symbol_hcall \ {H_REMOVE, "H_REMOVE"}, \ @@ -497,4 +495,11 @@ TRACE_EVENT(kvmppc_run_vcpu_exit, #endif /* _TRACE_KVM_HV_H */ /* This part must be outside protection */ + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE + +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace_hv + #include diff --git a/arch/powerpc/kvm/trace_pr.h b/arch/powerpc/kvm/trace_pr.h index 85785a370c0e..256530eb1354 100644 --- a/arch/powerpc/kvm/trace_pr.h +++ b/arch/powerpc/kvm/trace_pr.h @@ -8,8 +8,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM kvm_pr -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE trace_pr TRACE_EVENT(kvm_book3s_reenter, TP_PROTO(int r, struct kvm_vcpu *vcpu), @@ -272,4 +270,11 @@ TRACE_EVENT(kvm_unmap_hva, #endif /* _TRACE_KVM_H */ /* This part must be outside protection */ + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE + +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace_pr + #include -- GitLab From abaf1eb8132120f80071137cf5421a1c1eb7d720 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 5 Nov 2018 00:59:28 +0000 Subject: [PATCH 0112/1286] cpufreq: imx6q: add return value check for voltage scale [ Upstream commit 6ef28a04d1ccf718eee069b72132ce4aa1e52ab9 ] Add return value check for voltage scale when ARM clock rate change fail. Signed-off-by: Anson Huang Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/cpufreq/imx6q-cpufreq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 14466a9b01c0..63d28323a29c 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -135,8 +135,13 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) /* Ensure the arm clock divider is what we expect */ ret = clk_set_rate(arm_clk, new_freq * 1000); if (ret) { + int ret1; + dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); - regulator_set_voltage_tol(arm_reg, volt_old, 0); + ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); + if (ret1) + dev_warn(cpu_dev, + "failed to restore vddarm voltage: %d\n", ret1); return ret; } -- GitLab From 6e4fbdc7a308957c98d4599255a7a700ec92ca1c Mon Sep 17 00:00:00 2001 From: Xulin Sun Date: Tue, 6 Nov 2018 16:42:19 +0800 Subject: [PATCH 0113/1286] rtc: pcf2127: fix a kmemleak caused in pcf2127_i2c_gather_write [ Upstream commit 9bde0afb7a906f1dabdba37162551565740b862d ] pcf2127_i2c_gather_write() allocates memory as local variable for i2c_master_send(), after finishing the master transfer, the allocated memory should be freed. The kmemleak is reported: unreferenced object 0xffff80231e7dba80 (size 64): comm "hwclock", pid 27762, jiffies 4296880075 (age 356.944s) hex dump (first 32 bytes): 03 00 12 03 19 02 11 13 00 80 98 18 00 00 ff ff ................ 00 50 00 00 00 00 00 00 02 00 00 00 00 00 00 00 .P.............. backtrace: [] create_object+0xf8/0x278 [] kmemleak_alloc+0x74/0xa0 [] __kmalloc+0x1ac/0x348 [] pcf2127_i2c_gather_write+0x54/0xf8 [] _regmap_raw_write+0x464/0x850 [] regmap_bulk_write+0x1a4/0x348 [] pcf2127_rtc_set_time+0xac/0xe8 [] rtc_set_time+0x80/0x138 [] rtc_dev_ioctl+0x398/0x610 [] do_vfs_ioctl+0xb0/0x848 [] SyS_ioctl+0x8c/0xa8 [] el0_svc_naked+0x34/0x38 [] 0xffffffffffffffff Signed-off-by: Xulin Sun Signed-off-by: Alexandre Belloni Signed-off-by: Sasha Levin --- drivers/rtc/rtc-pcf2127.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index f33447c5db85..9f1b14bf91ae 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -248,6 +248,9 @@ static int pcf2127_i2c_gather_write(void *context, memcpy(buf + 1, val, val_size); ret = i2c_master_send(client, buf, val_size + 1); + + kfree(buf); + if (ret != val_size + 1) return ret < 0 ? ret : -EIO; -- GitLab From 66da887d8732b75b9dccc92b75d3972381fe62c7 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 8 Nov 2018 23:55:16 +0100 Subject: [PATCH 0114/1286] crypto: simd - correctly take reqsize of wrapped skcipher into account [ Upstream commit 508a1c4df085a547187eed346f1bfe5e381797f1 ] The simd wrapper's skcipher request context structure consists of a single subrequest whose size is taken from the subordinate skcipher. However, in simd_skcipher_init(), the reqsize that is retrieved is not from the subordinate skcipher but from the cryptd request structure, whose size is completely unrelated to the actual wrapped skcipher. Reported-by: Qian Cai Signed-off-by: Ard Biesheuvel Tested-by: Qian Cai Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- crypto/simd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/crypto/simd.c b/crypto/simd.c index 88203370a62f..894c62944106 100644 --- a/crypto/simd.c +++ b/crypto/simd.c @@ -126,8 +126,9 @@ static int simd_skcipher_init(struct crypto_skcipher *tfm) ctx->cryptd_tfm = cryptd_tfm; - reqsize = sizeof(struct skcipher_request); - reqsize += crypto_skcipher_reqsize(&cryptd_tfm->base); + reqsize = crypto_skcipher_reqsize(cryptd_skcipher_child(cryptd_tfm)); + reqsize = max(reqsize, crypto_skcipher_reqsize(&cryptd_tfm->base)); + reqsize += sizeof(struct skcipher_request); crypto_skcipher_set_reqsize(tfm, reqsize); -- GitLab From 5565c30a0bc770764cd085db881bc7a9f5e9d63c Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Fri, 9 Nov 2018 15:58:40 -0700 Subject: [PATCH 0115/1286] floppy: fix race condition in __floppy_read_block_0() [ Upstream commit de7b75d82f70c5469675b99ad632983c50b6f7e7 ] LKP recently reported a hang at bootup in the floppy code: [ 245.678853] INFO: task mount:580 blocked for more than 120 seconds. [ 245.679906] Tainted: G T 4.19.0-rc6-00172-ga9f38e1 #1 [ 245.680959] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 245.682181] mount D 6372 580 1 0x00000004 [ 245.683023] Call Trace: [ 245.683425] __schedule+0x2df/0x570 [ 245.683975] schedule+0x2d/0x80 [ 245.684476] schedule_timeout+0x19d/0x330 [ 245.685090] ? wait_for_common+0xa5/0x170 [ 245.685735] wait_for_common+0xac/0x170 [ 245.686339] ? do_sched_yield+0x90/0x90 [ 245.686935] wait_for_completion+0x12/0x20 [ 245.687571] __floppy_read_block_0+0xfb/0x150 [ 245.688244] ? floppy_resume+0x40/0x40 [ 245.688844] floppy_revalidate+0x20f/0x240 [ 245.689486] check_disk_change+0x43/0x60 [ 245.690087] floppy_open+0x1ea/0x360 [ 245.690653] __blkdev_get+0xb4/0x4d0 [ 245.691212] ? blkdev_get+0x1db/0x370 [ 245.691777] blkdev_get+0x1f3/0x370 [ 245.692351] ? path_put+0x15/0x20 [ 245.692871] ? lookup_bdev+0x4b/0x90 [ 245.693539] blkdev_get_by_path+0x3d/0x80 [ 245.694165] mount_bdev+0x2a/0x190 [ 245.694695] squashfs_mount+0x10/0x20 [ 245.695271] ? squashfs_alloc_inode+0x30/0x30 [ 245.695960] mount_fs+0xf/0x90 [ 245.696451] vfs_kern_mount+0x43/0x130 [ 245.697036] do_mount+0x187/0xc40 [ 245.697563] ? memdup_user+0x28/0x50 [ 245.698124] ksys_mount+0x60/0xc0 [ 245.698639] sys_mount+0x19/0x20 [ 245.699167] do_int80_syscall_32+0x61/0x130 [ 245.699813] entry_INT80_32+0xc7/0xc7 showing that we never complete that read request. The reason is that the completion setup is racy - it initializes the completion event AFTER submitting the IO, which means that the IO could complete before/during the init. If it does, we are passing garbage to complete() and we may sleep forever waiting for the event to occur. Fixes: 7b7b68bba5ef ("floppy: bail out in open() if drive is not responding to block0 read") Reviewed-by: Omar Sandoval Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/block/floppy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 3d0287e212fe..a7f212ea17bf 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -4146,10 +4146,11 @@ static int __floppy_read_block_0(struct block_device *bdev, int drive) bio.bi_end_io = floppy_rb0_cb; bio_set_op_attrs(&bio, REQ_OP_READ, 0); + init_completion(&cbdata.complete); + submit_bio(&bio); process_fd_request(); - init_completion(&cbdata.complete); wait_for_completion(&cbdata.complete); __free_page(page); -- GitLab From d5e236ba5bcdd95751980558b7af5519d05e19d1 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 6 Nov 2018 23:37:58 +1100 Subject: [PATCH 0116/1286] powerpc/io: Fix the IO workarounds code to work with Radix [ Upstream commit 43c6494fa1499912c8177e71450c0279041152a6 ] Back in 2006 Ben added some workarounds for a misbehaviour in the Spider IO bridge used on early Cell machines, see commit 014da7ff47b5 ("[POWERPC] Cell "Spider" MMIO workarounds"). Later these were made to be generic, ie. not tied specifically to Spider. The code stashes a token in the high bits (59-48) of virtual addresses used for IO (eg. returned from ioremap()). This works fine when using the Hash MMU, but when we're using the Radix MMU the bits used for the token overlap with some of the bits of the virtual address. This is because the maximum virtual address is larger with Radix, up to c00fffffffffffff, and in fact we use that high part of the address range for ioremap(), see RADIX_KERN_IO_START. As it happens the bits that are used overlap with the bits that differentiate an IO address vs a linear map address. If the resulting address lies outside the linear mapping we will crash (see below), if not we just corrupt memory. virtio-pci 0000:00:00.0: Using 64-bit direct DMA at offset 800000000000000 Unable to handle kernel paging request for data at address 0xc000000080000014 ... CFAR: c000000000626b98 DAR: c000000080000014 DSISR: 42000000 IRQMASK: 0 GPR00: c0000000006c54fc c00000003e523378 c0000000016de600 0000000000000000 GPR04: c00c000080000014 0000000000000007 0fffffff000affff 0000000000000030 ^^^^ ... NIP [c000000000626c5c] .iowrite8+0xec/0x100 LR [c0000000006c992c] .vp_reset+0x2c/0x90 Call Trace: .pci_bus_read_config_dword+0xc4/0x120 (unreliable) .register_virtio_device+0x13c/0x1c0 .virtio_pci_probe+0x148/0x1f0 .local_pci_probe+0x68/0x140 .pci_device_probe+0x164/0x220 .really_probe+0x274/0x3b0 .driver_probe_device+0x80/0x170 .__driver_attach+0x14c/0x150 .bus_for_each_dev+0xb8/0x130 .driver_attach+0x34/0x50 .bus_add_driver+0x178/0x2f0 .driver_register+0x90/0x1a0 .__pci_register_driver+0x6c/0x90 .virtio_pci_driver_init+0x2c/0x40 .do_one_initcall+0x64/0x280 .kernel_init_freeable+0x36c/0x474 .kernel_init+0x24/0x160 .ret_from_kernel_thread+0x58/0x7c This hasn't been a problem because CONFIG_PPC_IO_WORKAROUNDS which enables this code is usually not enabled. It is only enabled when it's selected by PPC_CELL_NATIVE which is only selected by PPC_IBM_CELL_BLADE and that in turn depends on BIG_ENDIAN. So in order to hit the bug you need to build a big endian kernel, with IBM Cell Blade support enabled, as well as Radix MMU support, and then boot that on Power9 using Radix MMU. Still we can fix the bug, so let's do that. We simply use fewer bits for the token, taking the union of the restrictions on the address from both Hash and Radix, we end up with 8 bits we can use for the token. The only user of the token is iowa_mem_find_bus() which only supports 8 token values, so 8 bits is plenty for that. Fixes: 566ca99af026 ("powerpc/mm/radix: Add dummy radix_enabled()") Signed-off-by: Michael Ellerman Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/io.h | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 422f99cf9924..e6d33eed8202 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -287,19 +287,13 @@ extern void _memcpy_toio(volatile void __iomem *dest, const void *src, * their hooks, a bitfield is reserved for use by the platform near the * top of MMIO addresses (not PIO, those have to cope the hard way). * - * This bit field is 12 bits and is at the top of the IO virtual - * addresses PCI_IO_INDIRECT_TOKEN_MASK. + * The highest address in the kernel virtual space are: * - * The kernel virtual space is thus: + * d0003fffffffffff # with Hash MMU + * c00fffffffffffff # with Radix MMU * - * 0xD000000000000000 : vmalloc - * 0xD000080000000000 : PCI PHB IO space - * 0xD000080080000000 : ioremap - * 0xD0000fffffffffff : end of ioremap region - * - * Since the top 4 bits are reserved as the region ID, we use thus - * the next 12 bits and keep 4 bits available for the future if the - * virtual address space is ever to be extended. + * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits + * that can be used for the field. * * The direct IO mapping operations will then mask off those bits * before doing the actual access, though that only happen when @@ -311,8 +305,8 @@ extern void _memcpy_toio(volatile void __iomem *dest, const void *src, */ #ifdef CONFIG_PPC_INDIRECT_MMIO -#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul -#define PCI_IO_IND_TOKEN_SHIFT 48 +#define PCI_IO_IND_TOKEN_SHIFT 52 +#define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT) #define PCI_FIX_ADDR(addr) \ ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) #define PCI_GET_ADDR_TOKEN(addr) \ -- GitLab From e1f0f55f27883820021a6cbc69deba0576098d0d Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Fri, 19 Oct 2018 10:04:18 -0700 Subject: [PATCH 0117/1286] perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake CPUs [ Upstream commit c10a8de0d32e95b0b8c7c17b6dc09baea5a5a899 ] KabyLake and CoffeeLake CPUs have the same client uncore events as SkyLake. Add the PCI IDs for the KabyLake Y, U, S processor lines and CoffeeLake U, H, S processor lines. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/20181019170419.378-1-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- arch/x86/events/intel/uncore_snb.c | 115 ++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c index aee5e8496be4..aa4e6f4e6a01 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -15,6 +15,25 @@ #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f +#define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c +#define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904 +#define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f +#define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f +#define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc +#define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0 +#define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10 +#define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f +#define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f +#define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18 +#define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6 +#define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31 +#define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33 +#define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca +#define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32 /* SNB event control */ #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff @@ -632,7 +651,82 @@ static const struct pci_device_id skl_uncore_pci_ids[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC), .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), }, - + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, { /* end: all zeroes */ }, }; @@ -681,6 +775,25 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = { IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */ IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */ IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */ + IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */ + IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */ + IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */ + IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */ + IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */ + IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */ + IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */ + IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */ + IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */ + IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */ + IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */ + IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */ + IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */ + IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */ + IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */ + IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */ + IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */ + IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */ + IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */ { /* end marker */ } }; -- GitLab From 677805a95934eb37bcc2482766d6160e6d216d98 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Mon, 12 Nov 2018 16:06:51 -0500 Subject: [PATCH 0118/1286] SUNRPC: Fix a bogus get/put in generic_key_to_expire() [ Upstream commit e3d5e573a54dabdc0f9f3cb039d799323372b251 ] Signed-off-by: Trond Myklebust Signed-off-by: Sasha Levin --- net/sunrpc/auth_generic.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/net/sunrpc/auth_generic.c b/net/sunrpc/auth_generic.c index f1df9837f1ac..1ac08dcbf85d 100644 --- a/net/sunrpc/auth_generic.c +++ b/net/sunrpc/auth_generic.c @@ -281,13 +281,7 @@ static bool generic_key_to_expire(struct rpc_cred *cred) { struct auth_cred *acred = &container_of(cred, struct generic_cred, gc_base)->acred; - bool ret; - - get_rpccred(cred); - ret = test_bit(RPC_CRED_KEY_EXPIRE_SOON, &acred->ac_flags); - put_rpccred(cred); - - return ret; + return test_bit(RPC_CRED_KEY_EXPIRE_SOON, &acred->ac_flags); } static const struct rpc_credops generic_credops = { -- GitLab From 281a4f41c6be4f6c09859f1877ab7a8b294ead62 Mon Sep 17 00:00:00 2001 From: Prarit Bhargava Date: Thu, 20 Sep 2018 08:59:14 -0400 Subject: [PATCH 0119/1286] kdb: Use strscpy with destination buffer size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit c2b94c72d93d0929f48157eef128c4f9d2e603ce ] gcc 8.1.0 warns with: kernel/debug/kdb/kdb_support.c: In function ‘kallsyms_symbol_next’: kernel/debug/kdb/kdb_support.c:239:4: warning: ‘strncpy’ specified bound depends on the length of the source argument [-Wstringop-overflow=] strncpy(prefix_name, name, strlen(name)+1); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/debug/kdb/kdb_support.c:239:31: note: length computed here Use strscpy() with the destination buffer size, and use ellipses when displaying truncated symbols. v2: Use strscpy() Signed-off-by: Prarit Bhargava Cc: Jonathan Toppins Cc: Jason Wessel Cc: Daniel Thompson Cc: kgdb-bugreport@lists.sourceforge.net Reviewed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Sasha Levin --- kernel/debug/kdb/kdb_io.c | 15 +++++++++------ kernel/debug/kdb/kdb_private.h | 2 +- kernel/debug/kdb/kdb_support.c | 10 +++++----- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/kernel/debug/kdb/kdb_io.c b/kernel/debug/kdb/kdb_io.c index ed5d34925ad0..6a4b41484afe 100644 --- a/kernel/debug/kdb/kdb_io.c +++ b/kernel/debug/kdb/kdb_io.c @@ -216,7 +216,7 @@ static char *kdb_read(char *buffer, size_t bufsize) int count; int i; int diag, dtab_count; - int key; + int key, buf_size, ret; diag = kdbgetintenv("DTABCOUNT", &dtab_count); @@ -336,9 +336,8 @@ static char *kdb_read(char *buffer, size_t bufsize) else p_tmp = tmpbuffer; len = strlen(p_tmp); - count = kallsyms_symbol_complete(p_tmp, - sizeof(tmpbuffer) - - (p_tmp - tmpbuffer)); + buf_size = sizeof(tmpbuffer) - (p_tmp - tmpbuffer); + count = kallsyms_symbol_complete(p_tmp, buf_size); if (tab == 2 && count > 0) { kdb_printf("\n%d symbols are found.", count); if (count > dtab_count) { @@ -350,9 +349,13 @@ static char *kdb_read(char *buffer, size_t bufsize) } kdb_printf("\n"); for (i = 0; i < count; i++) { - if (WARN_ON(!kallsyms_symbol_next(p_tmp, i))) + ret = kallsyms_symbol_next(p_tmp, i, buf_size); + if (WARN_ON(!ret)) break; - kdb_printf("%s ", p_tmp); + if (ret != -E2BIG) + kdb_printf("%s ", p_tmp); + else + kdb_printf("%s... ", p_tmp); *(p_tmp + len) = '\0'; } if (i >= dtab_count) diff --git a/kernel/debug/kdb/kdb_private.h b/kernel/debug/kdb/kdb_private.h index fc224fbcf954..f2158e463a0f 100644 --- a/kernel/debug/kdb/kdb_private.h +++ b/kernel/debug/kdb/kdb_private.h @@ -83,7 +83,7 @@ typedef struct __ksymtab { unsigned long sym_start; unsigned long sym_end; } kdb_symtab_t; -extern int kallsyms_symbol_next(char *prefix_name, int flag); +extern int kallsyms_symbol_next(char *prefix_name, int flag, int buf_size); extern int kallsyms_symbol_complete(char *prefix_name, int max_len); /* Exported Symbols for kernel loadable modules to use. */ diff --git a/kernel/debug/kdb/kdb_support.c b/kernel/debug/kdb/kdb_support.c index 84422d2b95c0..014f6fbb3832 100644 --- a/kernel/debug/kdb/kdb_support.c +++ b/kernel/debug/kdb/kdb_support.c @@ -221,11 +221,13 @@ int kallsyms_symbol_complete(char *prefix_name, int max_len) * Parameters: * prefix_name prefix of a symbol name to lookup * flag 0 means search from the head, 1 means continue search. + * buf_size maximum length that can be written to prefix_name + * buffer * Returns: * 1 if a symbol matches the given prefix. * 0 if no string found */ -int kallsyms_symbol_next(char *prefix_name, int flag) +int kallsyms_symbol_next(char *prefix_name, int flag, int buf_size) { int prefix_len = strlen(prefix_name); static loff_t pos; @@ -235,10 +237,8 @@ int kallsyms_symbol_next(char *prefix_name, int flag) pos = 0; while ((name = kdb_walk_kallsyms(&pos))) { - if (strncmp(name, prefix_name, prefix_len) == 0) { - strncpy(prefix_name, name, strlen(name)+1); - return 1; - } + if (!strncmp(name, prefix_name, prefix_len)) + return strscpy(prefix_name, name, buf_size); } return 0; } -- GitLab From 2a968a024116dc75b9488744a4711b0166ac3172 Mon Sep 17 00:00:00 2001 From: Satheesh Rajendran Date: Thu, 8 Nov 2018 10:47:56 +0530 Subject: [PATCH 0120/1286] powerpc/numa: Suppress "VPHN is not supported" messages [ Upstream commit 437ccdc8ce629470babdda1a7086e2f477048cbd ] When VPHN function is not supported and during cpu hotplug event, kernel prints message 'VPHN function not supported. Disabling polling...'. Currently it prints on every hotplug event, it floods dmesg when a KVM guest tries to hotplug huge number of vcpus, let's just print once and suppress further kernel prints. Signed-off-by: Satheesh Rajendran Signed-off-by: Michael Ellerman Signed-off-by: Sasha Levin --- arch/powerpc/mm/numa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 9fead0796364..40fb9a8835fe 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -1261,7 +1261,7 @@ static long vphn_get_associativity(unsigned long cpu, switch (rc) { case H_FUNCTION: - printk(KERN_INFO + printk_once(KERN_INFO "VPHN is not supported. Disabling polling...\n"); stop_topology_update(); break; -- GitLab From d6bfb89267efe3ae5eef1fc11984fae3dcd95137 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 14 Nov 2018 09:55:41 -0800 Subject: [PATCH 0121/1286] efi/arm: Revert deferred unmap of early memmap mapping [ Upstream commit 33412b8673135b18ea42beb7f5117ed0091798b6 ] Commit: 3ea86495aef2 ("efi/arm: preserve early mapping of UEFI memory map longer for BGRT") deferred the unmap of the early mapping of the UEFI memory map to accommodate the ACPI BGRT code, which looks up the memory type that backs the BGRT table to validate it against the requirements of the UEFI spec. Unfortunately, this causes problems on ARM, which does not permit early mappings to persist after paging_init() is called, resulting in a WARN() splat. Since we don't support the BGRT table on ARM anway, let's revert ARM to the old behaviour, which is to take down the early mapping at the end of efi_init(). Signed-off-by: Ard Biesheuvel Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Fixes: 3ea86495aef2 ("efi/arm: preserve early mapping of UEFI memory ...") Link: http://lkml.kernel.org/r/20181114175544.12860-3-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- drivers/firmware/efi/arm-init.c | 4 ++++ drivers/firmware/efi/arm-runtime.c | 2 +- drivers/firmware/efi/memmap.c | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/efi/arm-init.c b/drivers/firmware/efi/arm-init.c index a7c522eac640..312f9f32e168 100644 --- a/drivers/firmware/efi/arm-init.c +++ b/drivers/firmware/efi/arm-init.c @@ -265,6 +265,10 @@ void __init efi_init(void) (params.mmap & ~PAGE_MASK))); init_screen_info(); + + /* ARM does not permit early mappings to persist across paging_init() */ + if (IS_ENABLED(CONFIG_ARM)) + efi_memmap_unmap(); } static int __init register_gop_device(void) diff --git a/drivers/firmware/efi/arm-runtime.c b/drivers/firmware/efi/arm-runtime.c index 8995a48bd067..ad1530aff633 100644 --- a/drivers/firmware/efi/arm-runtime.c +++ b/drivers/firmware/efi/arm-runtime.c @@ -122,7 +122,7 @@ static int __init arm_enable_runtime_services(void) { u64 mapsize; - if (!efi_enabled(EFI_BOOT) || !efi_enabled(EFI_MEMMAP)) { + if (!efi_enabled(EFI_BOOT)) { pr_info("EFI services will not be available.\n"); return 0; } diff --git a/drivers/firmware/efi/memmap.c b/drivers/firmware/efi/memmap.c index 5fc70520e04c..1907db2b38d8 100644 --- a/drivers/firmware/efi/memmap.c +++ b/drivers/firmware/efi/memmap.c @@ -118,6 +118,9 @@ int __init efi_memmap_init_early(struct efi_memory_map_data *data) void __init efi_memmap_unmap(void) { + if (!efi_enabled(EFI_MEMMAP)) + return; + if (!efi.memmap.late) { unsigned long size; -- GitLab From e28ae7aaa9920570820c1af795663df317946ad7 Mon Sep 17 00:00:00 2001 From: Vitaly Wool Date: Fri, 16 Nov 2018 15:07:56 -0800 Subject: [PATCH 0122/1286] z3fold: fix possible reclaim races [ Upstream commit ca0246bb97c23da9d267c2107c07fb77e38205c9 ] Reclaim and free can race on an object which is basically fine but in order for reclaim to be able to map "freed" object we need to encode object length in the handle. handle_to_chunks() is then introduced to extract object length from a handle and use it during mapping. Moreover, to avoid racing on a z3fold "headless" page release, we should not try to free that page in z3fold_free() if the reclaim bit is set. Also, in the unlikely case of trying to reclaim a page being freed, we should not proceed with that page. While at it, fix the page accounting in reclaim function. This patch supersedes "[PATCH] z3fold: fix reclaim lock-ups". Link: http://lkml.kernel.org/r/20181105162225.74e8837d03583a9b707cf559@gmail.com Signed-off-by: Vitaly Wool Signed-off-by: Jongseok Kim Reported-by-by: Jongseok Kim Reviewed-by: Snild Dolkow Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/z3fold.c | 101 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 39 deletions(-) diff --git a/mm/z3fold.c b/mm/z3fold.c index f33403d718ac..2813cdfa46b9 100644 --- a/mm/z3fold.c +++ b/mm/z3fold.c @@ -99,6 +99,7 @@ struct z3fold_header { #define NCHUNKS ((PAGE_SIZE - ZHDR_SIZE_ALIGNED) >> CHUNK_SHIFT) #define BUDDY_MASK (0x3) +#define BUDDY_SHIFT 2 /** * struct z3fold_pool - stores metadata for each z3fold pool @@ -145,7 +146,7 @@ enum z3fold_page_flags { MIDDLE_CHUNK_MAPPED, NEEDS_COMPACTING, PAGE_STALE, - UNDER_RECLAIM + PAGE_CLAIMED, /* by either reclaim or free */ }; /***************** @@ -174,7 +175,7 @@ static struct z3fold_header *init_z3fold_page(struct page *page, clear_bit(MIDDLE_CHUNK_MAPPED, &page->private); clear_bit(NEEDS_COMPACTING, &page->private); clear_bit(PAGE_STALE, &page->private); - clear_bit(UNDER_RECLAIM, &page->private); + clear_bit(PAGE_CLAIMED, &page->private); spin_lock_init(&zhdr->page_lock); kref_init(&zhdr->refcount); @@ -223,8 +224,11 @@ static unsigned long encode_handle(struct z3fold_header *zhdr, enum buddy bud) unsigned long handle; handle = (unsigned long)zhdr; - if (bud != HEADLESS) - handle += (bud + zhdr->first_num) & BUDDY_MASK; + if (bud != HEADLESS) { + handle |= (bud + zhdr->first_num) & BUDDY_MASK; + if (bud == LAST) + handle |= (zhdr->last_chunks << BUDDY_SHIFT); + } return handle; } @@ -234,6 +238,12 @@ static struct z3fold_header *handle_to_z3fold_header(unsigned long handle) return (struct z3fold_header *)(handle & PAGE_MASK); } +/* only for LAST bud, returns zero otherwise */ +static unsigned short handle_to_chunks(unsigned long handle) +{ + return (handle & ~PAGE_MASK) >> BUDDY_SHIFT; +} + /* * (handle & BUDDY_MASK) < zhdr->first_num is possible in encode_handle * but that doesn't matter. because the masking will result in the @@ -717,37 +727,39 @@ static void z3fold_free(struct z3fold_pool *pool, unsigned long handle) page = virt_to_page(zhdr); if (test_bit(PAGE_HEADLESS, &page->private)) { - /* HEADLESS page stored */ - bud = HEADLESS; - } else { - z3fold_page_lock(zhdr); - bud = handle_to_buddy(handle); - - switch (bud) { - case FIRST: - zhdr->first_chunks = 0; - break; - case MIDDLE: - zhdr->middle_chunks = 0; - zhdr->start_middle = 0; - break; - case LAST: - zhdr->last_chunks = 0; - break; - default: - pr_err("%s: unknown bud %d\n", __func__, bud); - WARN_ON(1); - z3fold_page_unlock(zhdr); - return; + /* if a headless page is under reclaim, just leave. + * NB: we use test_and_set_bit for a reason: if the bit + * has not been set before, we release this page + * immediately so we don't care about its value any more. + */ + if (!test_and_set_bit(PAGE_CLAIMED, &page->private)) { + spin_lock(&pool->lock); + list_del(&page->lru); + spin_unlock(&pool->lock); + free_z3fold_page(page); + atomic64_dec(&pool->pages_nr); } + return; } - if (bud == HEADLESS) { - spin_lock(&pool->lock); - list_del(&page->lru); - spin_unlock(&pool->lock); - free_z3fold_page(page); - atomic64_dec(&pool->pages_nr); + /* Non-headless case */ + z3fold_page_lock(zhdr); + bud = handle_to_buddy(handle); + + switch (bud) { + case FIRST: + zhdr->first_chunks = 0; + break; + case MIDDLE: + zhdr->middle_chunks = 0; + break; + case LAST: + zhdr->last_chunks = 0; + break; + default: + pr_err("%s: unknown bud %d\n", __func__, bud); + WARN_ON(1); + z3fold_page_unlock(zhdr); return; } @@ -755,7 +767,7 @@ static void z3fold_free(struct z3fold_pool *pool, unsigned long handle) atomic64_dec(&pool->pages_nr); return; } - if (test_bit(UNDER_RECLAIM, &page->private)) { + if (test_bit(PAGE_CLAIMED, &page->private)) { z3fold_page_unlock(zhdr); return; } @@ -833,20 +845,30 @@ static int z3fold_reclaim_page(struct z3fold_pool *pool, unsigned int retries) } list_for_each_prev(pos, &pool->lru) { page = list_entry(pos, struct page, lru); + + /* this bit could have been set by free, in which case + * we pass over to the next page in the pool. + */ + if (test_and_set_bit(PAGE_CLAIMED, &page->private)) + continue; + + zhdr = page_address(page); if (test_bit(PAGE_HEADLESS, &page->private)) - /* candidate found */ break; - zhdr = page_address(page); - if (!z3fold_page_trylock(zhdr)) + if (!z3fold_page_trylock(zhdr)) { + zhdr = NULL; continue; /* can't evict at this point */ + } kref_get(&zhdr->refcount); list_del_init(&zhdr->buddy); zhdr->cpu = -1; - set_bit(UNDER_RECLAIM, &page->private); break; } + if (!zhdr) + break; + list_del_init(&page->lru); spin_unlock(&pool->lock); @@ -895,6 +917,7 @@ static int z3fold_reclaim_page(struct z3fold_pool *pool, unsigned int retries) if (test_bit(PAGE_HEADLESS, &page->private)) { if (ret == 0) { free_z3fold_page(page); + atomic64_dec(&pool->pages_nr); return 0; } spin_lock(&pool->lock); @@ -902,7 +925,7 @@ static int z3fold_reclaim_page(struct z3fold_pool *pool, unsigned int retries) spin_unlock(&pool->lock); } else { z3fold_page_lock(zhdr); - clear_bit(UNDER_RECLAIM, &page->private); + clear_bit(PAGE_CLAIMED, &page->private); if (kref_put(&zhdr->refcount, release_z3fold_page_locked)) { atomic64_dec(&pool->pages_nr); @@ -961,7 +984,7 @@ static void *z3fold_map(struct z3fold_pool *pool, unsigned long handle) set_bit(MIDDLE_CHUNK_MAPPED, &page->private); break; case LAST: - addr += PAGE_SIZE - (zhdr->last_chunks << CHUNK_SHIFT); + addr += PAGE_SIZE - (handle_to_chunks(handle) << CHUNK_SHIFT); break; default: pr_err("unknown buddy id %d\n", buddy); -- GitLab From a84c872c8b306e11c95c4912f4bed7f567e901b4 Mon Sep 17 00:00:00 2001 From: Yufen Yu Date: Fri, 16 Nov 2018 15:08:39 -0800 Subject: [PATCH 0123/1286] tmpfs: make lseek(SEEK_DATA/SEK_HOLE) return ENXIO with a negative offset [ Upstream commit 1a413646931cb14442065cfc17561e50f5b5bb44 ] Other filesystems such as ext4, f2fs and ubifs all return ENXIO when lseek (SEEK_DATA or SEEK_HOLE) requests a negative offset. man 2 lseek says : EINVAL whence is not valid. Or: the resulting file offset would be : negative, or beyond the end of a seekable device. : : ENXIO whence is SEEK_DATA or SEEK_HOLE, and the file offset is beyond : the end of the file. Make tmpfs return ENXIO under these circumstances as well. After this, tmpfs also passes xfstests's generic/448. [akpm@linux-foundation.org: rewrite changelog] Link: http://lkml.kernel.org/r/1540434176-14349-1-git-send-email-yuyufen@huawei.com Signed-off-by: Yufen Yu Reviewed-by: Andrew Morton Cc: Al Viro Cc: Hugh Dickins Cc: William Kucharski Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/shmem.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/mm/shmem.c b/mm/shmem.c index ea786a504e1b..fa08f56fd5e5 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2590,9 +2590,7 @@ static loff_t shmem_file_llseek(struct file *file, loff_t offset, int whence) inode_lock(inode); /* We're holding i_mutex so we can access i_size directly */ - if (offset < 0) - offset = -EINVAL; - else if (offset >= inode->i_size) + if (offset < 0 || offset >= inode->i_size) offset = -ENXIO; else { start = offset >> PAGE_SHIFT; -- GitLab From c6a4b3c3b81b818dc0138c813fd7656aeb78aa11 Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Fri, 16 Nov 2018 15:08:53 -0800 Subject: [PATCH 0124/1286] mm, page_alloc: check for max order in hot path [ Upstream commit c63ae43ba53bc432b414fd73dd5f4b01fcb1ab43 ] Konstantin has noticed that kvmalloc might trigger the following warning: WARNING: CPU: 0 PID: 6676 at mm/vmstat.c:986 __fragmentation_index+0x54/0x60 [...] Call Trace: fragmentation_index+0x76/0x90 compaction_suitable+0x4f/0xf0 shrink_node+0x295/0x310 node_reclaim+0x205/0x250 get_page_from_freelist+0x649/0xad0 __alloc_pages_nodemask+0x12a/0x2a0 kmalloc_large_node+0x47/0x90 __kmalloc_node+0x22b/0x2e0 kvmalloc_node+0x3e/0x70 xt_alloc_table_info+0x3a/0x80 [x_tables] do_ip6t_set_ctl+0xcd/0x1c0 [ip6_tables] nf_setsockopt+0x44/0x60 SyS_setsockopt+0x6f/0xc0 do_syscall_64+0x67/0x120 entry_SYSCALL_64_after_hwframe+0x3d/0xa2 the problem is that we only check for an out of bound order in the slow path and the node reclaim might happen from the fast path already. This is fixable by making sure that kvmalloc doesn't ever use kmalloc for requests that are larger than KMALLOC_MAX_SIZE but this also shows that the code is rather fragile. A recent UBSAN report just underlines that by the following report UBSAN: Undefined behaviour in mm/page_alloc.c:3117:19 shift exponent 51 is too large for 32-bit type 'int' CPU: 0 PID: 6520 Comm: syz-executor1 Not tainted 4.19.0-rc2 #1 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0xd2/0x148 lib/dump_stack.c:113 ubsan_epilogue+0x12/0x94 lib/ubsan.c:159 __ubsan_handle_shift_out_of_bounds+0x2b6/0x30b lib/ubsan.c:425 __zone_watermark_ok+0x2c7/0x400 mm/page_alloc.c:3117 zone_watermark_fast mm/page_alloc.c:3216 [inline] get_page_from_freelist+0xc49/0x44c0 mm/page_alloc.c:3300 __alloc_pages_nodemask+0x21e/0x640 mm/page_alloc.c:4370 alloc_pages_current+0xcc/0x210 mm/mempolicy.c:2093 alloc_pages include/linux/gfp.h:509 [inline] __get_free_pages+0x12/0x60 mm/page_alloc.c:4414 dma_mem_alloc+0x36/0x50 arch/x86/include/asm/floppy.h:156 raw_cmd_copyin drivers/block/floppy.c:3159 [inline] raw_cmd_ioctl drivers/block/floppy.c:3206 [inline] fd_locked_ioctl+0xa00/0x2c10 drivers/block/floppy.c:3544 fd_ioctl+0x40/0x60 drivers/block/floppy.c:3571 __blkdev_driver_ioctl block/ioctl.c:303 [inline] blkdev_ioctl+0xb3c/0x1a30 block/ioctl.c:601 block_ioctl+0x105/0x150 fs/block_dev.c:1883 vfs_ioctl fs/ioctl.c:46 [inline] do_vfs_ioctl+0x1c0/0x1150 fs/ioctl.c:687 ksys_ioctl+0x9e/0xb0 fs/ioctl.c:702 __do_sys_ioctl fs/ioctl.c:709 [inline] __se_sys_ioctl fs/ioctl.c:707 [inline] __x64_sys_ioctl+0x7e/0xc0 fs/ioctl.c:707 do_syscall_64+0xc4/0x510 arch/x86/entry/common.c:290 entry_SYSCALL_64_after_hwframe+0x49/0xbe Note that this is not a kvmalloc path. It is just that the fast path really depends on having sanitzed order as well. Therefore move the order check to the fast path. Link: http://lkml.kernel.org/r/20181113094305.GM15120@dhcp22.suse.cz Signed-off-by: Michal Hocko Reported-by: Konstantin Khlebnikov Reported-by: Kyungtae Kim Acked-by: Vlastimil Babka Cc: Balbir Singh Cc: Mel Gorman Cc: Pavel Tatashin Cc: Oscar Salvador Cc: Mike Rapoport Cc: Aaron Lu Cc: Joonsoo Kim Cc: Byoungyoung Lee Cc: "Dae R. Jeong" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/page_alloc.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index a604b5da6755..2074f424dabf 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -3867,17 +3867,6 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int order, unsigned int cpuset_mems_cookie; int reserve_flags; - /* - * In the slowpath, we sanity check order to avoid ever trying to - * reclaim >= MAX_ORDER areas which will never succeed. Callers may - * be using allocators in order of preference for an area that is - * too large. - */ - if (order >= MAX_ORDER) { - WARN_ON_ONCE(!(gfp_mask & __GFP_NOWARN)); - return NULL; - } - /* * We also sanity check to catch abuse of atomic reserves being used by * callers that are not in atomic context. @@ -4179,6 +4168,15 @@ __alloc_pages_nodemask(gfp_t gfp_mask, unsigned int order, int preferred_nid, gfp_t alloc_mask; /* The gfp_t that was actually used for allocation */ struct alloc_context ac = { }; + /* + * There are several places where we assume that the order value is sane + * so bail out early if the request is out of bound. + */ + if (unlikely(order >= MAX_ORDER)) { + WARN_ON_ONCE(!(gfp_mask & __GFP_NOWARN)); + return NULL; + } + gfp_mask &= gfp_allowed_mask; alloc_mask = gfp_mask; if (!prepare_alloc_pages(gfp_mask, order, preferred_nid, nodemask, &ac, &alloc_mask, &alloc_flags)) -- GitLab From c1ede7043d74de0022872921b453d106341fcf93 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:45 +0200 Subject: [PATCH 0125/1286] of: add helper to lookup compatible child node [ Upstream commit 36156f9241cb0f9e37d998052873ca7501ad4b36 ] Add of_get_compatible_child() helper that can be used to lookup compatible child nodes. Several drivers currently use of_find_compatible_node() to lookup child nodes while failing to notice that the of_find_ functions search the entire tree depth-first (from a given start node) and therefore can match unrelated nodes. The fact that these functions also drop a reference to the node they start searching from (e.g. the parent node) is typically also overlooked, something which can lead to use-after-free bugs. Signed-off-by: Johan Hovold Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/of/base.c | 25 +++++++++++++++++++++++++ include/linux/of.h | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/of/base.c b/drivers/of/base.c index 63897531cd75..ce8a6e0c9b6a 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -737,6 +737,31 @@ struct device_node *of_get_next_available_child(const struct device_node *node, } EXPORT_SYMBOL(of_get_next_available_child); +/** + * of_get_compatible_child - Find compatible child node + * @parent: parent node + * @compatible: compatible string + * + * Lookup child node whose compatible property contains the given compatible + * string. + * + * Returns a node pointer with refcount incremented, use of_node_put() on it + * when done; or NULL if not found. + */ +struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible) +{ + struct device_node *child; + + for_each_child_of_node(parent, child) { + if (of_device_is_compatible(child, compatible)) + break; + } + + return child; +} +EXPORT_SYMBOL(of_get_compatible_child); + /** * of_get_child_by_name - Find the child node by name for a given parent * @node: parent node diff --git a/include/linux/of.h b/include/linux/of.h index b240ed69dc96..70b7dacf9238 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -288,6 +288,8 @@ extern struct device_node *of_get_next_child(const struct device_node *node, extern struct device_node *of_get_next_available_child( const struct device_node *node, struct device_node *prev); +extern struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible); extern struct device_node *of_get_child_by_name(const struct device_node *node, const char *name); @@ -625,6 +627,12 @@ static inline bool of_have_populated_dt(void) return false; } +static inline struct device_node *of_get_compatible_child(const struct device_node *parent, + const char *compatible) +{ + return NULL; +} + static inline struct device_node *of_get_child_by_name( const struct device_node *node, const char *name) -- GitLab From 2ae0ac647a773fc3db57770a202b1c62a66fe3db Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:52 +0200 Subject: [PATCH 0126/1286] NFC: nfcmrvl_uart: fix OF child-node lookup [ Upstream commit 5bf59773aaf36dd62117dc83d50e1bbf9ef432da ] Use the new of_get_compatible_child() helper to lookup the nfc child node instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (i.e. non-child) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the parent node). Fixes: e097dc624f78 ("NFC: nfcmrvl: add UART driver") Fixes: d8e018c0b321 ("NFC: nfcmrvl: update device tree bindings for Marvell NFC") Cc: stable # 4.2 Cc: Vincent Cuissard Cc: Samuel Ortiz Signed-off-by: Johan Hovold Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/nfc/nfcmrvl/uart.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/nfc/nfcmrvl/uart.c b/drivers/nfc/nfcmrvl/uart.c index 91162f8e0366..9a22056e8d9e 100644 --- a/drivers/nfc/nfcmrvl/uart.c +++ b/drivers/nfc/nfcmrvl/uart.c @@ -73,10 +73,9 @@ static int nfcmrvl_uart_parse_dt(struct device_node *node, struct device_node *matched_node; int ret; - matched_node = of_find_compatible_node(node, NULL, "marvell,nfc-uart"); + matched_node = of_get_compatible_child(node, "marvell,nfc-uart"); if (!matched_node) { - matched_node = of_find_compatible_node(node, NULL, - "mrvl,nfc-uart"); + matched_node = of_get_compatible_child(node, "mrvl,nfc-uart"); if (!matched_node) return -ENODEV; } -- GitLab From 6f95f0734968025278b6d8b4d0c589b7afeb9c96 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:50 +0200 Subject: [PATCH 0127/1286] net: bcmgenet: fix OF child-node lookup [ Upstream commit d397dbe606120a1ea1b11b0020c3f7a3852da5ac ] Use the new of_get_compatible_child() helper to lookup the mdio child node instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (i.e. non-child) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the node of the device being probed). Fixes: aa09677cba42 ("net: bcmgenet: add MDIO routines") Cc: stable # 3.15 Cc: David S. Miller Reviewed-by: Florian Fainelli Signed-off-by: Johan Hovold Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/genet/bcmmii.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c index abbd2894f870..c421e2753c8c 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c @@ -360,7 +360,7 @@ static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) if (!compat) return NULL; - priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); + priv->mdio_dn = of_get_compatible_child(dn, compat); kfree(compat); if (!priv->mdio_dn) { dev_err(kdev, "unable to find MDIO bus node\n"); -- GitLab From 279eb9ce4cbc20ae82f73fd3b2d05184f8f40d53 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:46 +0200 Subject: [PATCH 0128/1286] drm/mediatek: fix OF sibling-node lookup [ Upstream commit ceff2f4dcd44abf35864d9a99f85ac619e89a01d ] Use the new of_get_compatible_child() helper to lookup the sibling instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (i.e. non-sibling) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the parent device node). While at it, also fix the related cec-node reference leak. Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") Cc: stable # 4.8 Cc: Junzhi Zhao Cc: Philipp Zabel Cc: CK Hu Cc: David Airlie Signed-off-by: Johan Hovold Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 690c67507cbc..aba27ea9cea5 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1446,8 +1446,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } /* The CEC module handles HDMI hotplug detection */ - cec_np = of_find_compatible_node(np->parent, NULL, - "mediatek,mt8173-cec"); + cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); if (!cec_np) { dev_err(dev, "Failed to find CEC node\n"); return -EINVAL; @@ -1457,8 +1456,10 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, if (!cec_pdev) { dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np); + of_node_put(cec_np); return -EPROBE_DEFER; } + of_node_put(cec_np); hdmi->cec_dev = &cec_pdev->dev; /* -- GitLab From 5f2b2c591fc8fd84c70fd591aa13d903e32c2df7 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:53 +0200 Subject: [PATCH 0129/1286] power: supply: twl4030-charger: fix OF sibling-node lookup [ Upstream commit 9844fb2e351311210e6660a9a1c62d17424a6145 ] Use the new of_get_compatible_child() helper to lookup the usb sibling node instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (non-sibling) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the parent device node). While at it, also fix the related phy-node reference leak. Fixes: f5e4edb8c888 ("power: twl4030_charger: find associated phy by more reliable means.") Cc: stable # 4.2 Cc: NeilBrown Cc: Felipe Balbi Cc: Sebastian Reichel Reviewed-by: Sebastian Reichel Signed-off-by: Johan Hovold Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/power/supply/twl4030_charger.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/twl4030_charger.c b/drivers/power/supply/twl4030_charger.c index a5915f498eea..0cc12bfe7b02 100644 --- a/drivers/power/supply/twl4030_charger.c +++ b/drivers/power/supply/twl4030_charger.c @@ -996,12 +996,13 @@ static int twl4030_bci_probe(struct platform_device *pdev) if (bci->dev->of_node) { struct device_node *phynode; - phynode = of_find_compatible_node(bci->dev->of_node->parent, - NULL, "ti,twl4030-usb"); + phynode = of_get_compatible_child(bci->dev->of_node->parent, + "ti,twl4030-usb"); if (phynode) { bci->usb_nb.notifier_call = twl4030_bci_usb_ncb; bci->transceiver = devm_usb_get_phy_by_node( bci->dev, phynode, &bci->usb_nb); + of_node_put(phynode); if (IS_ERR(bci->transceiver)) { ret = PTR_ERR(bci->transceiver); if (ret == -EPROBE_DEFER) -- GitLab From 38f94eca31d47db6429edb1ba6a560db1f34d298 Mon Sep 17 00:00:00 2001 From: Greg Hackmann Date: Tue, 27 Nov 2018 11:15:20 -0800 Subject: [PATCH 0130/1286] arm64: remove no-op -p linker flag (commit 1a381d4a0a9a0f999a13faaba22bf6b3fc80dcb9 upstream) Linking the ARM64 defconfig kernel with LLVM lld fails with the error: ld.lld: error: unknown argument: -p Makefile:1015: recipe for target 'vmlinux' failed Without this flag, the ARM64 defconfig kernel successfully links with lld and boots on Dragonboard 410c. After digging through binutils source and changelogs, it turns out that -p is only relevant to ancient binutils installations targeting 32-bit ARM. binutils accepts -p for AArch64 too, but it's always been undocumented and silently ignored. A comment in ld/emultempl/aarch64elf.em explains that it's "Only here for backwards compatibility". Since this flag is a no-op on ARM64, we can safely drop it. Acked-by: Will Deacon Reviewed-by: Nick Desaulniers Signed-off-by: Greg Hackmann Signed-off-by: Catalin Marinas Signed-off-by: Nick Desaulniers Signed-off-by: Sasha Levin --- arch/arm64/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 7318165cfc90..48f2b3657507 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -10,7 +10,7 @@ # # Copyright (C) 1995-2001 by Russell King -LDFLAGS_vmlinux :=-p --no-undefined -X +LDFLAGS_vmlinux :=--no-undefined -X CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) GZFLAGS :=-9 -- GitLab From cd4f18da5ecaf08fbbb61e74434468b63519ecf3 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 23 May 2018 18:41:36 +0100 Subject: [PATCH 0131/1286] xhci: Allow more than 32 quirks commit 36b6857932f380fcb55c31ac75857e3e81dd583a upstream. We now have 32 different quirks, and the field that holds them is full. Let's bump it up to the next stage so that we can handle some more... The type is now an unsigned long long, which is 64bit on most architectures. We take this opportunity to change the quirks from using (1 << x) to BIT_ULL(x). Tested-by: Domenico Andreoli Signed-off-by: Marc Zyngier Tested-by: Faiz Abbas Tested-by: Domenico Andreoli Acked-by: Mathias Nyman Cc: "Cherian, George" Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci.c | 6 ++-- drivers/usb/host/xhci.h | 64 +++++++++++++++++++++-------------------- 2 files changed, 36 insertions(+), 34 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 64ddba3f79a9..faf048682194 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -43,8 +43,8 @@ static int link_quirk; module_param(link_quirk, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); -static unsigned int quirks; -module_param(quirks, uint, S_IRUGO); +static unsigned long long quirks; +module_param(quirks, ullong, S_IRUGO); MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring) @@ -4956,7 +4956,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) return retval; xhci_dbg(xhci, "Called HCD init\n"); - xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n", + xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n", xhci->hcc_params, xhci->hci_version, xhci->quirks); return 0; diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 29dc6160c9eb..ef7f171d6e97 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1794,12 +1794,12 @@ struct xhci_hcd { #define XHCI_STATE_DYING (1 << 0) #define XHCI_STATE_HALTED (1 << 1) #define XHCI_STATE_REMOVING (1 << 2) - unsigned int quirks; -#define XHCI_LINK_TRB_QUIRK (1 << 0) -#define XHCI_RESET_EP_QUIRK (1 << 1) -#define XHCI_NEC_HOST (1 << 2) -#define XHCI_AMD_PLL_FIX (1 << 3) -#define XHCI_SPURIOUS_SUCCESS (1 << 4) + unsigned long long quirks; +#define XHCI_LINK_TRB_QUIRK BIT_ULL(0) +#define XHCI_RESET_EP_QUIRK BIT_ULL(1) +#define XHCI_NEC_HOST BIT_ULL(2) +#define XHCI_AMD_PLL_FIX BIT_ULL(3) +#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) /* * Certain Intel host controllers have a limit to the number of endpoint * contexts they can handle. Ideally, they would signal that they can't handle @@ -1809,33 +1809,35 @@ struct xhci_hcd { * commands, reset device commands, disable slot commands, and address device * commands. */ -#define XHCI_EP_LIMIT_QUIRK (1 << 5) -#define XHCI_BROKEN_MSI (1 << 6) -#define XHCI_RESET_ON_RESUME (1 << 7) -#define XHCI_SW_BW_CHECKING (1 << 8) -#define XHCI_AMD_0x96_HOST (1 << 9) -#define XHCI_TRUST_TX_LENGTH (1 << 10) -#define XHCI_LPM_SUPPORT (1 << 11) -#define XHCI_INTEL_HOST (1 << 12) -#define XHCI_SPURIOUS_REBOOT (1 << 13) -#define XHCI_COMP_MODE_QUIRK (1 << 14) -#define XHCI_AVOID_BEI (1 << 15) -#define XHCI_PLAT (1 << 16) -#define XHCI_SLOW_SUSPEND (1 << 17) -#define XHCI_SPURIOUS_WAKEUP (1 << 18) +#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) +#define XHCI_BROKEN_MSI BIT_ULL(6) +#define XHCI_RESET_ON_RESUME BIT_ULL(7) +#define XHCI_SW_BW_CHECKING BIT_ULL(8) +#define XHCI_AMD_0x96_HOST BIT_ULL(9) +#define XHCI_TRUST_TX_LENGTH BIT_ULL(10) +#define XHCI_LPM_SUPPORT BIT_ULL(11) +#define XHCI_INTEL_HOST BIT_ULL(12) +#define XHCI_SPURIOUS_REBOOT BIT_ULL(13) +#define XHCI_COMP_MODE_QUIRK BIT_ULL(14) +#define XHCI_AVOID_BEI BIT_ULL(15) +#define XHCI_PLAT BIT_ULL(16) +#define XHCI_SLOW_SUSPEND BIT_ULL(17) +#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) /* For controllers with a broken beyond repair streams implementation */ -#define XHCI_BROKEN_STREAMS (1 << 19) -#define XHCI_PME_STUCK_QUIRK (1 << 20) -#define XHCI_MTK_HOST (1 << 21) -#define XHCI_SSIC_PORT_UNUSED (1 << 22) -#define XHCI_NO_64BIT_SUPPORT (1 << 23) -#define XHCI_MISSING_CAS (1 << 24) +#define XHCI_BROKEN_STREAMS BIT_ULL(19) +#define XHCI_PME_STUCK_QUIRK BIT_ULL(20) +#define XHCI_MTK_HOST BIT_ULL(21) +#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) +#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) +#define XHCI_MISSING_CAS BIT_ULL(24) /* For controller with a broken Port Disable implementation */ -#define XHCI_BROKEN_PORT_PED (1 << 25) -#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) -#define XHCI_U2_DISABLE_WAKE (1 << 27) -#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) -#define XHCI_SUSPEND_DELAY (1 << 30) +#define XHCI_BROKEN_PORT_PED BIT_ULL(25) +#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) +#define XHCI_U2_DISABLE_WAKE BIT_ULL(27) +#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) +#define XHCI_HW_LPM_DISABLE BIT_ULL(29) +#define XHCI_SUSPEND_DELAY BIT_ULL(30) +#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) unsigned int num_active_eps; unsigned int limit_active_eps; -- GitLab From 649594a678c2aa9bea0693a22753034c35ab42c6 Mon Sep 17 00:00:00 2001 From: "Cherian, George" Date: Fri, 9 Nov 2018 17:21:22 +0200 Subject: [PATCH 0132/1286] xhci: Add quirk to workaround the errata seen on Cavium Thunder-X2 Soc commit 11644a7659529730eaf2f166efaabe7c3dc7af8c upstream. Implement workaround for ThunderX2 Errata-129 (documented in CN99XX Known Issues" available at Cavium support site). As per ThunderX2errata-129, USB 2 device may come up as USB 1 if a connection to a USB 1 device is followed by another connection to a USB 2 device, the link will come up as USB 1 for the USB 2 device. Resolution: Reset the PHY after the USB 1 device is disconnected. The PHY reset sequence is done using private registers in XHCI register space. After the PHY is reset we check for the PLL lock status and retry the operation if it fails. From our tests, retrying 4 times is sufficient. Add a new quirk flag XHCI_RESET_PLL_ON_DISCONNECT to invoke the workaround in handle_xhci_port_status(). Cc: stable@vger.kernel.org Signed-off-by: George Cherian Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-pci.c | 5 +++++ drivers/usb/host/xhci-ring.c | 35 ++++++++++++++++++++++++++++++++++- drivers/usb/host/xhci.h | 1 + 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 9218f506f8e3..4b07b6859b4c 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -236,6 +236,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; + if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || + pdev->vendor == PCI_VENDOR_ID_CAVIUM) && + pdev->device == 0x9026) + xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; + if (xhci->quirks & XHCI_RESET_ON_RESUME) xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, "QUIRK: Resetting on resume"); diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 2d64cb024d00..998f61d82689 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -1568,6 +1568,35 @@ static void handle_device_notification(struct xhci_hcd *xhci, usb_wakeup_notification(udev->parent, udev->portnum); } +/* + * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI + * Controller. + * As per ThunderX2errata-129 USB 2 device may come up as USB 1 + * If a connection to a USB 1 device is followed by another connection + * to a USB 2 device. + * + * Reset the PHY after the USB device is disconnected if device speed + * is less than HCD_USB3. + * Retry the reset sequence max of 4 times checking the PLL lock status. + * + */ +static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) +{ + struct usb_hcd *hcd = xhci_to_hcd(xhci); + u32 pll_lock_check; + u32 retry_count = 4; + + do { + /* Assert PHY reset */ + writel(0x6F, hcd->regs + 0x1048); + udelay(10); + /* De-assert the PHY reset */ + writel(0x7F, hcd->regs + 0x1048); + udelay(200); + pll_lock_check = readl(hcd->regs + 0x1070); + } while (!(pll_lock_check & 0x1) && --retry_count); +} + static void handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event) { @@ -1725,9 +1754,13 @@ static void handle_port_status(struct xhci_hcd *xhci, goto cleanup; } - if (hcd->speed < HCD_USB3) + if (hcd->speed < HCD_USB3) { xhci_test_and_clear_bit(xhci, port_array, faked_port_index, PORT_PLC); + if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && + (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) + xhci_cavium_reset_phy_quirk(xhci); + } cleanup: /* Update event ring dequeue pointer before dropping the lock */ diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index ef7f171d6e97..74ba20556020 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1838,6 +1838,7 @@ struct xhci_hcd { #define XHCI_HW_LPM_DISABLE BIT_ULL(29) #define XHCI_SUSPEND_DELAY BIT_ULL(30) #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) +#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) unsigned int num_active_eps; unsigned int limit_active_eps; -- GitLab From 0aa6b111cc44f9aef0be1715e2d8ac8c2e9023cb Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:49 +0200 Subject: [PATCH 0133/1286] mtd: rawnand: atmel: fix OF child-node lookup commit 5d1e9c2212ea6b4dd735e4fc3dd6279a365d5d10 upstream. Use the new of_get_compatible_child() helper to lookup the nfc child node instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (i.e. non-child) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the node of the device being probed). While at it, also fix a related nfc-node reference leak. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Cc: stable # 4.11 Cc: Nicolas Ferre Cc: Josh Wu Cc: Boris Brezillon Signed-off-by: Johan Hovold Signed-off-by: Boris Brezillon Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/atmel/nand-controller.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c index 32a2f947a454..0b93f152d993 100644 --- a/drivers/mtd/nand/atmel/nand-controller.c +++ b/drivers/mtd/nand/atmel/nand-controller.c @@ -2077,8 +2077,7 @@ atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc) int ret; nand_np = dev->of_node; - nfc_np = of_find_compatible_node(dev->of_node, NULL, - "atmel,sama5d3-nfc"); + nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); if (!nfc_np) { dev_err(dev, "Could not find device node for sama5d3-nfc\n"); return -ENODEV; @@ -2492,15 +2491,19 @@ static int atmel_nand_controller_probe(struct platform_device *pdev) } if (caps->legacy_of_bindings) { + struct device_node *nfc_node; u32 ale_offs = 21; /* * If we are parsing legacy DT props and the DT contains a * valid NFC node, forward the request to the sama5 logic. */ - if (of_find_compatible_node(pdev->dev.of_node, NULL, - "atmel,sama5d3-nfc")) + nfc_node = of_get_compatible_child(pdev->dev.of_node, + "atmel,sama5d3-nfc"); + if (nfc_node) { caps = &atmel_sama5_nand_caps; + of_node_put(nfc_node); + } /* * Even if the compatible says we are dealing with an -- GitLab From da141471e77ba27b9c50f858ff866b4958d9e04c Mon Sep 17 00:00:00 2001 From: Richard Weinberger Date: Mon, 28 May 2018 22:04:33 +0200 Subject: [PATCH 0134/1286] ubi: fastmap: Check each mapping only once commit 34653fd8c46e771585fce5975e4243f8fd401914 upstream. Maintain a bitmap to keep track of which LEB->PEB mapping was checked already. That way we have to read back VID headers only once. Fixes: a23cf10d9abb ("ubi: fastmap: Correctly handle interrupted erasures in EBA") Signed-off-by: Richard Weinberger Signed-off-by: Martin Kepplinger --- drivers/mtd/ubi/build.c | 1 + drivers/mtd/ubi/eba.c | 4 ++++ drivers/mtd/ubi/fastmap.c | 20 ++++++++++++++++++++ drivers/mtd/ubi/ubi.h | 11 +++++++++++ drivers/mtd/ubi/vmt.c | 1 + drivers/mtd/ubi/vtbl.c | 16 +++++++++++++++- 6 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 18a72da759a0..6445c693d935 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -526,6 +526,7 @@ void ubi_free_internal_volumes(struct ubi_device *ubi) for (i = ubi->vtbl_slots; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { ubi_eba_replace_table(ubi->volumes[i], NULL); + ubi_fastmap_destroy_checkmap(ubi->volumes[i]); kfree(ubi->volumes[i]); } } diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index d0884bd9d955..c4d4b8f07630 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -517,6 +517,9 @@ static int check_mapping(struct ubi_device *ubi, struct ubi_volume *vol, int lnu if (!ubi->fast_attach) return 0; + if (!vol->checkmap || test_bit(lnum, vol->checkmap)) + return 0; + vidb = ubi_alloc_vid_buf(ubi, GFP_NOFS); if (!vidb) return -ENOMEM; @@ -551,6 +554,7 @@ static int check_mapping(struct ubi_device *ubi, struct ubi_volume *vol, int lnu goto out_free; } + set_bit(lnum, vol->checkmap); err = 0; out_free: diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c index 5a832bc79b1b..63e8527f7b65 100644 --- a/drivers/mtd/ubi/fastmap.c +++ b/drivers/mtd/ubi/fastmap.c @@ -1101,6 +1101,26 @@ int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai, goto out; } +int ubi_fastmap_init_checkmap(struct ubi_volume *vol, int leb_count) +{ + struct ubi_device *ubi = vol->ubi; + + if (!ubi->fast_attach) + return 0; + + vol->checkmap = kcalloc(BITS_TO_LONGS(leb_count), sizeof(unsigned long), + GFP_KERNEL); + if (!vol->checkmap) + return -ENOMEM; + + return 0; +} + +void ubi_fastmap_destroy_checkmap(struct ubi_volume *vol) +{ + kfree(vol->checkmap); +} + /** * ubi_write_fastmap - writes a fastmap. * @ubi: UBI device object diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 5fe62653995e..f5ba97c46160 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -334,6 +334,9 @@ struct ubi_eba_leb_desc { * @changing_leb: %1 if the atomic LEB change ioctl command is in progress * @direct_writes: %1 if direct writes are enabled for this volume * + * @checkmap: bitmap to remember which PEB->LEB mappings got checked, + * protected by UBI LEB lock tree. + * * The @corrupted field indicates that the volume's contents is corrupted. * Since UBI protects only static volumes, this field is not relevant to * dynamic volumes - it is user's responsibility to assure their data @@ -377,6 +380,10 @@ struct ubi_volume { unsigned int updating:1; unsigned int changing_leb:1; unsigned int direct_writes:1; + +#ifdef CONFIG_MTD_UBI_FASTMAP + unsigned long *checkmap; +#endif }; /** @@ -965,8 +972,12 @@ size_t ubi_calc_fm_size(struct ubi_device *ubi); int ubi_update_fastmap(struct ubi_device *ubi); int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai, struct ubi_attach_info *scan_ai); +int ubi_fastmap_init_checkmap(struct ubi_volume *vol, int leb_count); +void ubi_fastmap_destroy_checkmap(struct ubi_volume *vol); #else static inline int ubi_update_fastmap(struct ubi_device *ubi) { return 0; } +int static inline ubi_fastmap_init_checkmap(struct ubi_volume *vol, int leb_count) { return 0; } +static inline void ubi_fastmap_destroy_checkmap(struct ubi_volume *vol) {} #endif /* block.c */ diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 3fd8d7ff7a02..0be516780e92 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -139,6 +139,7 @@ static void vol_release(struct device *dev) struct ubi_volume *vol = container_of(dev, struct ubi_volume, dev); ubi_eba_replace_table(vol, NULL); + ubi_fastmap_destroy_checkmap(vol); kfree(vol); } diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index 263743e7b741..94d7a865b135 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -534,7 +534,7 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_attach_info *ai, const struct ubi_vtbl_record *vtbl) { - int i, reserved_pebs = 0; + int i, err, reserved_pebs = 0; struct ubi_ainf_volume *av; struct ubi_volume *vol; @@ -620,6 +620,16 @@ static int init_volumes(struct ubi_device *ubi, (long long)(vol->used_ebs - 1) * vol->usable_leb_size; vol->used_bytes += av->last_data_size; vol->last_eb_bytes = av->last_data_size; + + /* + * We use ubi->peb_count and not vol->reserved_pebs because + * we want to keep the code simple. Otherwise we'd have to + * resize/check the bitmap upon volume resize too. + * Allocating a few bytes more does not hurt. + */ + err = ubi_fastmap_init_checkmap(vol, ubi->peb_count); + if (err) + return err; } /* And add the layout volume */ @@ -645,6 +655,9 @@ static int init_volumes(struct ubi_device *ubi, reserved_pebs += vol->reserved_pebs; ubi->vol_count += 1; vol->ubi = ubi; + err = ubi_fastmap_init_checkmap(vol, UBI_LAYOUT_VOLUME_EBS); + if (err) + return err; if (reserved_pebs > ubi->avail_pebs) { ubi_err(ubi, "not enough PEBs, required %d, available %d", @@ -849,6 +862,7 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_attach_info *ai) out_free: vfree(ubi->vtbl); for (i = 0; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) { + ubi_fastmap_destroy_checkmap(ubi->volumes[i]); kfree(ubi->volumes[i]); ubi->volumes[i] = NULL; } -- GitLab From f299ecb085117412b313094d075e573994c704a0 Mon Sep 17 00:00:00 2001 From: Francis Therien Date: Mon, 26 Mar 2018 15:59:00 -0700 Subject: [PATCH 0135/1286] Input: xpad - add PDP device id 0x02a4 [ Upstream commit c6c848572f4da0e34ffe0a35364b4db871e13e42 ] Adds support for a PDP Xbox One controller with device ID (0x06ef:0x02a4). The Product string for this device is "PDP Wired Controller for Xbox One - Stealth Series | Phantom Black". Signed-off-by: Francis Therien Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/joystick/xpad.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 53f775c41cd1..d2a1857fdae5 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -231,6 +231,7 @@ static const struct xpad_device { { 0x0e6f, 0x021f, "Rock Candy Gamepad for Xbox 360", 0, XTYPE_XBOX360 }, { 0x0e6f, 0x0246, "Rock Candy Gamepad for Xbox One 2015", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x02ab, "PDP Controller for Xbox One", 0, XTYPE_XBOXONE }, + { 0x0e6f, 0x02a4, "PDP Wired Controller for Xbox One - Stealth Series", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x0301, "Logic3 Controller", 0, XTYPE_XBOX360 }, { 0x0e6f, 0x0346, "Rock Candy Gamepad for Xbox One 2016", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x0401, "Logic3 Controller", 0, XTYPE_XBOX360 }, @@ -480,7 +481,8 @@ static const u8 xboxone_hori_init[] = { /* * This packet is required for some of the PDP pads to start - * sending input reports. One of those pads is (0x0e6f:0x02ab). + * sending input reports. These pads include: (0x0e6f:0x02ab), + * (0x0e6f:0x02a4). */ static const u8 xboxone_pdp_init1[] = { 0x0a, 0x20, 0x00, 0x03, 0x00, 0x01, 0x14 @@ -488,7 +490,8 @@ static const u8 xboxone_pdp_init1[] = { /* * This packet is required for some of the PDP pads to start - * sending input reports. One of those pads is (0x0e6f:0x02ab). + * sending input reports. These pads include: (0x0e6f:0x02ab), + * (0x0e6f:0x02a4). */ static const u8 xboxone_pdp_init2[] = { 0x06, 0x20, 0x00, 0x02, 0x01, 0x00 @@ -526,6 +529,8 @@ static const struct xboxone_init_packet xboxone_init_packets[] = { XBOXONE_INIT_PKT(0x0000, 0x0000, xboxone_fw2015_init), XBOXONE_INIT_PKT(0x0e6f, 0x02ab, xboxone_pdp_init1), XBOXONE_INIT_PKT(0x0e6f, 0x02ab, xboxone_pdp_init2), + XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init1), + XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init2), XBOXONE_INIT_PKT(0x24c6, 0x541a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x542a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x543a, xboxone_rumblebegin_init), -- GitLab From 5d3bf6348692bb664da58a07510cd21c1439394e Mon Sep 17 00:00:00 2001 From: Leo Sperling Date: Wed, 3 Aug 2016 17:31:09 -0700 Subject: [PATCH 0136/1286] Input: xpad - fix some coding style issues [ Upstream commit 68c78d0155e37992268664e134996d2b140ddf38 ] Fix some coding style issues reported by checkpatch.pl. Mostly brackets in macros, spacing and comment style. Signed-off-by: Leo Sperling Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/joystick/xpad.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index d2a1857fdae5..7e812a8877bc 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -89,8 +89,10 @@ #define XPAD_PKT_LEN 64 -/* xbox d-pads should map to buttons, as is required for DDR pads - but we map them to axes when possible to simplify things */ +/* + * xbox d-pads should map to buttons, as is required for DDR pads + * but we map them to axes when possible to simplify things + */ #define MAP_DPAD_TO_BUTTONS (1 << 0) #define MAP_TRIGGERS_TO_BUTTONS (1 << 1) #define MAP_STICKS_TO_NULL (1 << 2) @@ -391,15 +393,15 @@ static const signed short xpad_abs_triggers[] = { * match against vendor id as well. Wired Xbox 360 devices have protocol 1, * wireless controllers have protocol 129. */ -#define XPAD_XBOX360_VENDOR_PROTOCOL(vend,pr) \ +#define XPAD_XBOX360_VENDOR_PROTOCOL(vend, pr) \ .match_flags = USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_INT_INFO, \ .idVendor = (vend), \ .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ .bInterfaceSubClass = 93, \ .bInterfaceProtocol = (pr) #define XPAD_XBOX360_VENDOR(vend) \ - { XPAD_XBOX360_VENDOR_PROTOCOL(vend,1) }, \ - { XPAD_XBOX360_VENDOR_PROTOCOL(vend,129) } + { XPAD_XBOX360_VENDOR_PROTOCOL((vend), 1) }, \ + { XPAD_XBOX360_VENDOR_PROTOCOL((vend), 129) } /* The Xbox One controller uses subclass 71 and protocol 208. */ #define XPAD_XBOXONE_VENDOR_PROTOCOL(vend, pr) \ @@ -409,7 +411,7 @@ static const signed short xpad_abs_triggers[] = { .bInterfaceSubClass = 71, \ .bInterfaceProtocol = (pr) #define XPAD_XBOXONE_VENDOR(vend) \ - { XPAD_XBOXONE_VENDOR_PROTOCOL(vend, 208) } + { XPAD_XBOXONE_VENDOR_PROTOCOL((vend), 208) } static const struct usb_device_id xpad_table[] = { { USB_INTERFACE_INFO('X', 'B', 0) }, /* X-Box USB-IF not approved class */ @@ -1578,6 +1580,7 @@ static void xpad_close(struct input_dev *dev) static void xpad_set_up_abs(struct input_dev *input_dev, signed short abs) { struct usb_xpad *xpad = input_get_drvdata(input_dev); + set_bit(abs, input_dev->absbit); switch (abs) { -- GitLab From 8d6a81009de5a184da9da76de27961d4abd62092 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Tue, 8 May 2018 15:17:07 -0700 Subject: [PATCH 0137/1286] Input: xpad - avoid using __set_bit() for capabilities [ Upstream commit a01308031c2647ed5f1c845104b73a8820a958a9 ] input_set_capability() and input_set_abs_param() will do it for you. Signed-off-by: Marcus Folkesson Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/joystick/xpad.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 7e812a8877bc..69b44aebaf01 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -1581,8 +1581,6 @@ static void xpad_set_up_abs(struct input_dev *input_dev, signed short abs) { struct usb_xpad *xpad = input_get_drvdata(input_dev); - set_bit(abs, input_dev->absbit); - switch (abs) { case ABS_X: case ABS_Y: @@ -1601,6 +1599,9 @@ static void xpad_set_up_abs(struct input_dev *input_dev, signed short abs) case ABS_HAT0Y: /* the d-pad (only if dpad is mapped to axes */ input_set_abs_params(input_dev, abs, -1, 1, 0, 0); break; + default: + input_set_abs_params(input_dev, abs, 0, 0, 0, 0); + break; } } @@ -1641,10 +1642,7 @@ static int xpad_init_input(struct usb_xpad *xpad) input_dev->close = xpad_close; } - __set_bit(EV_KEY, input_dev->evbit); - if (!(xpad->mapping & MAP_STICKS_TO_NULL)) { - __set_bit(EV_ABS, input_dev->evbit); /* set up axes */ for (i = 0; xpad_abs[i] >= 0; i++) xpad_set_up_abs(input_dev, xpad_abs[i]); @@ -1652,21 +1650,22 @@ static int xpad_init_input(struct usb_xpad *xpad) /* set up standard buttons */ for (i = 0; xpad_common_btn[i] >= 0; i++) - __set_bit(xpad_common_btn[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, xpad_common_btn[i]); /* set up model-specific ones */ if (xpad->xtype == XTYPE_XBOX360 || xpad->xtype == XTYPE_XBOX360W || xpad->xtype == XTYPE_XBOXONE) { for (i = 0; xpad360_btn[i] >= 0; i++) - __set_bit(xpad360_btn[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, xpad360_btn[i]); } else { for (i = 0; xpad_btn[i] >= 0; i++) - __set_bit(xpad_btn[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, xpad_btn[i]); } if (xpad->mapping & MAP_DPAD_TO_BUTTONS) { for (i = 0; xpad_btn_pad[i] >= 0; i++) - __set_bit(xpad_btn_pad[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, + xpad_btn_pad[i]); } /* @@ -1683,7 +1682,8 @@ static int xpad_init_input(struct usb_xpad *xpad) if (xpad->mapping & MAP_TRIGGERS_TO_BUTTONS) { for (i = 0; xpad_btn_triggers[i] >= 0; i++) - __set_bit(xpad_btn_triggers[i], input_dev->keybit); + input_set_capability(input_dev, EV_KEY, + xpad_btn_triggers[i]); } else { for (i = 0; xpad_abs_triggers[i] >= 0; i++) xpad_set_up_abs(input_dev, xpad_abs_triggers[i]); -- GitLab From eb4b4647003688e3b3a4e20fef6ca33a029a1e58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ramses=20Ram=C3=ADrez?= Date: Fri, 28 Sep 2018 16:59:26 -0700 Subject: [PATCH 0138/1286] Input: xpad - add support for Xbox1 PDP Camo series gamepad MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9735082a7cbae572c2eabdc45acecc8c9fa0759b ] The "Xbox One PDP Wired Controller - Camo series" has a different product-id than the regular PDP controller and the PDP stealth series, but it uses the same initialization sequence. This patch adds the product-id of the camo series to the structures that handle the other PDP Xbox One controllers. Signed-off-by: Ramses Ramírez Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/joystick/xpad.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 69b44aebaf01..2e52015634f9 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -234,6 +234,7 @@ static const struct xpad_device { { 0x0e6f, 0x0246, "Rock Candy Gamepad for Xbox One 2015", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x02ab, "PDP Controller for Xbox One", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x02a4, "PDP Wired Controller for Xbox One - Stealth Series", 0, XTYPE_XBOXONE }, + { 0x0e6f, 0x02a6, "PDP Wired Controller for Xbox One - Camo Series", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x0301, "Logic3 Controller", 0, XTYPE_XBOX360 }, { 0x0e6f, 0x0346, "Rock Candy Gamepad for Xbox One 2016", 0, XTYPE_XBOXONE }, { 0x0e6f, 0x0401, "Logic3 Controller", 0, XTYPE_XBOX360 }, @@ -533,6 +534,8 @@ static const struct xboxone_init_packet xboxone_init_packets[] = { XBOXONE_INIT_PKT(0x0e6f, 0x02ab, xboxone_pdp_init2), XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init1), XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init2), + XBOXONE_INIT_PKT(0x0e6f, 0x02a6, xboxone_pdp_init1), + XBOXONE_INIT_PKT(0x0e6f, 0x02a6, xboxone_pdp_init2), XBOXONE_INIT_PKT(0x24c6, 0x541a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x542a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x543a, xboxone_rumblebegin_init), -- GitLab From 1fe2316fc23aa6a23721bf97a4cdd8a88e8213f4 Mon Sep 17 00:00:00 2001 From: Matt Chen Date: Fri, 3 Aug 2018 14:29:20 +0800 Subject: [PATCH 0139/1286] iwlwifi: fix wrong WGDS_WIFI_DATA_SIZE commit 66e839030fd698586734e017fd55c4f2a89dba0b upstream. From coreboot/BIOS: Name ("WGDS", Package() { Revision, Package() { DomainType, // 0x7:WiFi ==> We miss this one. WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset } }) When read the ACPI data to find out the WGDS, the DATA_SIZE is never matched. From the above format, it gives 19 numbers, but our driver is hardcode as 18. Fix it to pass then can parse the data into our wgds table. Then we will see: iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init Sending GEO_TX_POWER_LIMIT iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[0] Band[0]: chain A = 68 chain B = 69 max_tx_power = 54 iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[0] Band[1]: chain A = 48 chain B = 49 max_tx_power = 70 iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[1] Band[0]: chain A = 51 chain B = 67 max_tx_power = 50 iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[1] Band[1]: chain A = 69 chain B = 70 max_tx_power = 68 iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[2] Band[0]: chain A = 49 chain B = 50 max_tx_power = 48 iwlwifi 0000:01:00.0: U iwl_mvm_sar_geo_init SAR geographic profile[2] Band[1]: chain A = 52 chain B = 53 max_tx_power = 51 Cc: stable@vger.kernel.org # 4.12+ Fixes: a6bff3cb19b7 ("iwlwifi: mvm: add GEO_TX_POWER_LIMIT cmd for geographic tx power table") Signed-off-by: Matt Chen Signed-off-by: Luca Coelho Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/intel/iwlwifi/mvm/fw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c index 11319675f2d9..cebf0ce76d27 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c @@ -590,7 +590,7 @@ static int iwl_mvm_config_ltr(struct iwl_mvm *mvm) #define ACPI_WRDS_WIFI_DATA_SIZE (IWL_MVM_SAR_TABLE_SIZE + 2) #define ACPI_EWRD_WIFI_DATA_SIZE ((IWL_MVM_SAR_PROFILE_NUM - 1) * \ IWL_MVM_SAR_TABLE_SIZE + 3) -#define ACPI_WGDS_WIFI_DATA_SIZE 18 +#define ACPI_WGDS_WIFI_DATA_SIZE 19 #define ACPI_WGDS_NUM_BANDS 2 #define ACPI_WGDS_TABLE_SIZE 3 @@ -964,7 +964,7 @@ static int iwl_mvm_sar_geo_init(struct iwl_mvm *mvm) IWL_DEBUG_RADIO(mvm, "Sending GEO_TX_POWER_LIMIT\n"); BUILD_BUG_ON(IWL_NUM_GEO_PROFILES * ACPI_WGDS_NUM_BANDS * - ACPI_WGDS_TABLE_SIZE != ACPI_WGDS_WIFI_DATA_SIZE); + ACPI_WGDS_TABLE_SIZE + 1 != ACPI_WGDS_WIFI_DATA_SIZE); for (i = 0; i < IWL_NUM_GEO_PROFILES; i++) { struct iwl_per_chain_offset *chain = -- GitLab From 9d844b0e66929e3c3099fe428fe06543bc18b99a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 17 Sep 2018 19:31:57 -0700 Subject: [PATCH 0140/1286] kbuild: allow to use GCC toolchain not in Clang search path commit ef8c4ed9db80261f397f0c0bf723684601ae3b52 upstream. When using a GCC cross toolchain which is not in a compiled in Clang search path, Clang reverts to the system assembler and linker. This leads to assembler or linker errors, depending on which tool is first used for a given architecture. It seems that Clang is not searching $PATH for a matching assembler or linker. Make sure that Clang picks up the correct assembler or linker by passing the cross compilers bin directory as search path. This allows to use Clang provided by distributions with GCC toolchains not in /usr/bin. Link: https://github.com/ClangBuiltLinux/linux/issues/78 Signed-off-by: Stefan Agner Reviewed-and-tested-by: Nick Desaulniers Signed-off-by: Masahiro Yamada [nc: Adjust context] Signed-off-by: Nathan Chancellor Signed-off-by: Greg Kroah-Hartman --- Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 874d72a3e6a7..cb131e135c42 100644 --- a/Makefile +++ b/Makefile @@ -480,13 +480,15 @@ endif ifeq ($(cc-name),clang) ifneq ($(CROSS_COMPILE),) CLANG_TARGET := --target=$(notdir $(CROSS_COMPILE:%-=%)) -GCC_TOOLCHAIN := $(realpath $(dir $(shell which $(LD)))/..) +GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD))) +CLANG_PREFIX := --prefix=$(GCC_TOOLCHAIN_DIR) +GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) endif ifneq ($(GCC_TOOLCHAIN),) CLANG_GCC_TC := --gcc-toolchain=$(GCC_TOOLCHAIN) endif -KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) -KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) +KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) $(CLANG_PREFIX) +KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) $(CLANG_PREFIX) KBUILD_CFLAGS += $(call cc-option, -no-integrated-as) KBUILD_AFLAGS += $(call cc-option, -no-integrated-as) endif -- GitLab From 7aaa554d09606185650cd1aa422887736b9e1056 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 14 Dec 2017 14:01:45 +0100 Subject: [PATCH 0141/1286] PCI: endpoint: Populate func_no before calling pci_epc_add_epf() commit 0c47cd7a9b6c9c36c08113e594e9ad017fb17865 upstream. func_no is a member of struct pci_epf. Since struct pci_epf is used as an argument to pci_epc_add_epf() (to bind an endpoint function to a controller), struct pci_epf.func_no should be populated before calling pci_epc_add_epf(). Initialize the struct pci_epf.func_no member before calling pci_epc_add_epf(), to fix the endpoint function binding to an endpoint controller. Fixes: d74679911610 ("PCI: endpoint: Introduce configfs entry for configuring EP functions") Signed-off-by: Niklas Cassel [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: Lorenzo Pieralisi Suggested-by: Kishon Vijay Abraham I Acked-by: Kishon Vijay Abraham I Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/pci/endpoint/pci-ep-cfs.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index 16cec66b1d0b..8fdb9d07c50a 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -97,16 +97,10 @@ static int pci_epc_epf_link(struct config_item *epc_item, { int ret; u32 func_no = 0; - struct pci_epc *epc; - struct pci_epf *epf; struct pci_epf_group *epf_group = to_pci_epf_group(epf_item); struct pci_epc_group *epc_group = to_pci_epc_group(epc_item); - - epc = epc_group->epc; - epf = epf_group->epf; - ret = pci_epc_add_epf(epc, epf); - if (ret) - goto err_add_epf; + struct pci_epc *epc = epc_group->epc; + struct pci_epf *epf = epf_group->epf; func_no = find_first_zero_bit(&epc_group->function_num_map, BITS_PER_LONG); @@ -116,6 +110,10 @@ static int pci_epc_epf_link(struct config_item *epc_item, set_bit(func_no, &epc_group->function_num_map); epf->func_no = func_no; + ret = pci_epc_add_epf(epc, epf); + if (ret) + goto err_add_epf; + ret = pci_epf_bind(epf); if (ret) goto err_epf_bind; -- GitLab From 9d9cd2bcfc5298109bd90c52f239011337147812 Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Wed, 13 Dec 2017 18:12:10 +0200 Subject: [PATCH 0142/1286] net/mlx4_core: Fix wrong calculation of free counters commit 0bb9fc4f5429ac970181c073aa32e521e20f7b73 upstream. The field res_free indicates the total number of counters which are available for allocation (reserved and unreserved). Fixed a bug where the reserved counters were subtracted from res_free before any allocation was performed. Before this fix, free counters which were not reserved could not be allocated. Fixes: 9de92c60beaa ("net/mlx4_core: Adjust counter grant policy in the resource tracker") Signed-off-by: Eran Ben Elisha Reviewed-by: Jack Morgenstein Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/mellanox/mlx4/resource_tracker.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c index b26da0952a4d..a5381b091710 100644 --- a/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c +++ b/drivers/net/ethernet/mellanox/mlx4/resource_tracker.c @@ -611,7 +611,6 @@ int mlx4_init_resource_tracker(struct mlx4_dev *dev) MLX4_MAX_PORTS; else res_alloc->guaranteed[t] = 0; - res_alloc->res_free -= res_alloc->guaranteed[t]; break; default: break; -- GitLab From 31a673709a853cf28ca4a1bb88e15bf4c0bf099f Mon Sep 17 00:00:00 2001 From: Mustafa Ismail Date: Mon, 7 May 2018 12:52:17 -0500 Subject: [PATCH 0143/1286] i40iw: Fix memory leak in error path of create QP commit 5a7189d529cd146cd5838af97b32fcac4122b471 upstream. If i40iw_allocate_dma_mem fails when creating a QP, the memory allocated for the QP structure using kzalloc is not freed because iwqp->allocated_buffer is used to free the memory and it is not setup until later. Fix this by setting iwqp->allocated_buffer before allocating the dma memory. Fixes: d37498417947 ("i40iw: add files for iwarp interface") Signed-off-by: Mustafa Ismail Signed-off-by: Shiraz Saleem Signed-off-by: Doug Ledford Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/i40iw/i40iw_verbs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw_verbs.c b/drivers/infiniband/hw/i40iw/i40iw_verbs.c index 39398dd074d6..c1021b4afb41 100644 --- a/drivers/infiniband/hw/i40iw/i40iw_verbs.c +++ b/drivers/infiniband/hw/i40iw/i40iw_verbs.c @@ -631,6 +631,7 @@ static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd, return ERR_PTR(-ENOMEM); iwqp = (struct i40iw_qp *)mem; + iwqp->allocated_buffer = mem; qp = &iwqp->sc_qp; qp->back_qp = (void *)iwqp; qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX; @@ -659,7 +660,6 @@ static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd, goto error; } - iwqp->allocated_buffer = mem; iwqp->iwdev = iwdev; iwqp->iwpd = iwpd; iwqp->ibqp.qp_num = qp_num; -- GitLab From 7eebc934f302922de7c7399db4752956c19f7147 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 13 Oct 2017 00:06:44 +0200 Subject: [PATCH 0144/1286] rtc: omap: fix error path when pinctrl_register fails commit 26e480f7bb7840fc0daa9c3af7c4501b2cf5902f upstream. If pinctrl_register() fails probe will return with an error without locking the RTC and disabling pm_runtime. Set ret and jump to err instead. Fixes: 97ea1906b3c2 ("rtc: omap: Support ext_wakeup configuration") Signed-off-by: Alexandre Belloni Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/rtc/rtc-omap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c index ac6e6a6a194c..ae6506a8b4f5 100644 --- a/drivers/rtc/rtc-omap.c +++ b/drivers/rtc/rtc-omap.c @@ -823,7 +823,8 @@ static int omap_rtc_probe(struct platform_device *pdev) rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc); if (IS_ERR(rtc->pctldev)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(rtc->pctldev); + ret = PTR_ERR(rtc->pctldev); + goto err; } if (rtc->is_pmic_controller) { -- GitLab From dc32281ec0281ffe2ea57d3157eaae6eb74aef8a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 13 Mar 2018 11:46:12 +0100 Subject: [PATCH 0145/1286] clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices commit 5b23fceec1ff94305c5d1accde018cae27448005 upstream. FIMC LITE SYSMMU devices are defined in exynos5250.dtsi, but clocks for them are not instantiated by Exynos5250 clock provider driver. Add needed definitions for those clocks to fix IOMMU probe failure: ERROR: could not get clock /soc/sysmmu@13c40000:sysmmu(0) exynos-sysmmu 13c40000.sysmmu: Failed to get device clock(s)! exynos-sysmmu: probe of 13c40000.sysmmu failed with error -38 ERROR: could not get clock /soc/sysmmu@13c50000:sysmmu(0) exynos-sysmmu 13c50000.sysmmu: Failed to get device clock(s)! exynos-sysmmu: probe of 13c50000.sysmmu failed with error -38 Signed-off-by: Marek Szyprowski Fixes: bfed1074f213 ("clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks") Acked-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/clk/samsung/clk-exynos5250.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 6a0cb8a515e8..b609219c802b 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -560,6 +560,8 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { 0), GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 0), + GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 4, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", @@ -570,6 +572,10 @@ static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { GATE_IP_GSCL, 9, 0, 0), GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 10, 0, 0), + GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 11, 0, 0), + GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub", + GATE_IP_GSCL, 12, 0, 0), GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 0), -- GitLab From a46ca4c8f1c64723ce0a9f66638a1343a71bbe3f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 Apr 2018 20:26:41 +0200 Subject: [PATCH 0146/1286] ARM: dts: exynos: Fix invalid node referenced by i2c20 alias in Peach Pit and Pi commit 70c3250ac1374688d7963e562fe58b23f70bcba9 upstream. After moving all nodes under "soc" node in commit 5d99cc59a3c6 ("ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc"), the i2c20 alias in Peach Pit and Peach Pi stopped pointing to proper node: arch/arm/boot/dts/exynos5420-peach-pit.dtb: Warning (alias_paths): /aliases:i2c20: aliases property is not a valid node (/spi@12d40000/cros-ec@0/i2c-tunnel) arch/arm/boot/dts/exynos5800-peach-pi.dtb: Warning (alias_paths): /aliases:i2c20: aliases property is not a valid node (/spi@12d40000/cros-ec@0/i2c-tunnel) Fixes: 5d99cc59a3c6 ("ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++-- arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 683a4cfb4a23..c91eff8475a8 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -31,7 +31,7 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + i2c20 = &i2c_tunnel; }; backlight: backlight { @@ -952,7 +952,7 @@ samsung,spi-feedback-delay = <1>; }; - i2c-tunnel { + i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index b2b95ff205e8..daad5d425cf5 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -29,7 +29,7 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + i2c20 = &i2c_tunnel; }; backlight: backlight { @@ -921,7 +921,7 @@ samsung,spi-feedback-delay = <1>; }; - i2c-tunnel { + i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; #address-cells = <1>; #size-cells = <0>; -- GitLab From c8692d9f5ceff240792df5b42ca1639ace77204b Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Fri, 20 Oct 2017 20:01:01 +0800 Subject: [PATCH 0147/1286] driver core: Move device_links_purge() after bus_remove_device() commit 2ec16150179888b81717d1d3ce84e634f4736af2 upstream. The current ordering of code in device_del() triggers a WARN_ON() in device_links_purge(), because of an unexpected link status. The device_links_unbind_consumers() call in device_release_driver() has to take place before device_links_purge() for the status of all links to be correct, so move the device_links_purge() call in device_del() after the invocation of bus_remove_device() which calls device_release_driver(). Fixes: 9ed9895370ae (driver core: Functional dependencies tracking support) Signed-off-by: Jeffy Chen Reviewed-by: Rafael J. Wysocki Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- drivers/base/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/core.c b/drivers/base/core.c index eb066cc827ef..3f463a61f8cf 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -1973,7 +1973,6 @@ void device_del(struct device *dev) blocking_notifier_call_chain(&dev->bus->p->bus_notifier, BUS_NOTIFY_DEL_DEVICE, dev); - device_links_purge(dev); dpm_sysfs_remove(dev); if (parent) klist_del(&dev->p->knode_parent); @@ -2001,6 +2000,7 @@ void device_del(struct device *dev) device_pm_remove(dev); driver_deferred_probe_del(dev); device_remove_properties(dev); + device_links_purge(dev); /* Notify the platform of the removal, in case they * need to do anything... -- GitLab From a956132ac00bd5a4b2909707f00f8d5366931648 Mon Sep 17 00:00:00 2001 From: Sebastien Boisvert Date: Fri, 26 Oct 2018 15:02:23 -0700 Subject: [PATCH 0148/1286] include/linux/pfn_t.h: force '~' to be parsed as an unary operator commit 4d54954a197175c0dcb3c82af0c0740d0c5f827a upstream. Tracing the event "fs_dax:dax_pmd_insert_mapping" with perf produces this warning: [fs_dax:dax_pmd_insert_mapping] unknown op '~' It is printed in process_op (tools/lib/traceevent/event-parse.c) because '~' is parsed as a binary operator. perf reads the format of fs_dax:dax_pmd_insert_mapping ("print fmt") from /sys/kernel/debug/tracing/events/fs_dax/dax_pmd_insert_mapping/format . The format contains: ~(((u64) ~(~(((1UL) << 12)-1))) ^ \ interpreted as a binary operator by process_op(). This part is generated in the declaration of the event class dax_pmd_insert_mapping_class in include/trace/events/fs_dax.h : __print_flags_u64(__entry->pfn_val & PFN_FLAGS_MASK, "|", PFN_FLAGS_TRACE), This patch adds a pair of parentheses in the declaration of PFN_FLAGS_MASK to make sure that '~' is parsed as a unary operator by perf. The part of the format that was problematic is now: ~(((u64) (~(~(((1UL) << 12)-1)))) Now, all the '~' are parsed as unary operators. Link: http://lkml.kernel.org/r/20181021145939.8760-1-sebhtml@videotron.qc.ca Signed-off-by: Sebastien Boisvert Acked-by: Dan Williams Cc: "Steven Rostedt (VMware)" Cc: Arnaldo Carvalho de Melo Cc: "Tzvetomir Stoyanov (VMware)" Cc: Namhyung Kim Cc: Ross Zwisler Cc: Elenie Godzaridis Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- include/linux/pfn_t.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/pfn_t.h b/include/linux/pfn_t.h index 43b1d7648e82..a8aef18c6244 100644 --- a/include/linux/pfn_t.h +++ b/include/linux/pfn_t.h @@ -10,7 +10,7 @@ * PFN_DEV - pfn is not covered by system memmap by default * PFN_MAP - pfn has a dynamic page mapping established by a device driver */ -#define PFN_FLAGS_MASK (((u64) ~PAGE_MASK) << (BITS_PER_LONG_LONG - PAGE_SHIFT)) +#define PFN_FLAGS_MASK (((u64) (~PAGE_MASK)) << (BITS_PER_LONG_LONG - PAGE_SHIFT)) #define PFN_SG_CHAIN (1ULL << (BITS_PER_LONG_LONG - 1)) #define PFN_SG_LAST (1ULL << (BITS_PER_LONG_LONG - 2)) #define PFN_DEV (1ULL << (BITS_PER_LONG_LONG - 3)) -- GitLab From 5e063b64163be65e2f04588808760e790a889e3c Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 4 Oct 2018 11:06:13 -0700 Subject: [PATCH 0149/1286] tty: wipe buffer. commit c9a8e5fce009e3c601a43c49ea9dbcb25d1ffac5 upstream. After we are done with the tty buffer, zero it out. Reported-by: aszlig Tested-by: Milan Broz Tested-by: Daniel Zatovic Tested-by: aszlig Cc: Willy Tarreau Signed-off-by: Greg Kroah-Hartman --- drivers/tty/tty_buffer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/tty_buffer.c b/drivers/tty/tty_buffer.c index 677fa99b7747..217114227f8d 100644 --- a/drivers/tty/tty_buffer.c +++ b/drivers/tty/tty_buffer.c @@ -467,11 +467,15 @@ receive_buf(struct tty_port *port, struct tty_buffer *head, int count) { unsigned char *p = char_buf_ptr(head, head->read); char *f = NULL; + int n; if (~head->flags & TTYB_NORMAL) f = flag_buf_ptr(head, head->read); - return port->client_ops->receive_buf(port, p, f, count); + n = port->client_ops->receive_buf(port, p, f, count); + if (n > 0) + memset(p, 0, n); + return n; } /** -- GitLab From b008f3b25588868a89e9e4562b4dc641d1032553 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 4 Oct 2018 11:06:14 -0700 Subject: [PATCH 0150/1286] tty: wipe buffer if not echoing data commit b97b3d9fb57860a60592859e332de7759fd54c2e upstream. If we are not echoing the data to userspace or the console is in icanon mode, then perhaps it is a "secret" so we should wipe it once we are done with it. This mirrors the logic that the audit code has. Reported-by: aszlig Tested-by: Milan Broz Tested-by: Daniel Zatovic Tested-by: aszlig Cc: Willy Tarreau Signed-off-by: Greg Kroah-Hartman --- drivers/tty/n_tty.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c index 0475f9685a41..904fc9c37fde 100644 --- a/drivers/tty/n_tty.c +++ b/drivers/tty/n_tty.c @@ -154,17 +154,28 @@ static inline unsigned char *echo_buf_addr(struct n_tty_data *ldata, size_t i) return &ldata->echo_buf[i & (N_TTY_BUF_SIZE - 1)]; } +/* If we are not echoing the data, perhaps this is a secret so erase it */ +static void zero_buffer(struct tty_struct *tty, u8 *buffer, int size) +{ + bool icanon = !!L_ICANON(tty); + bool no_echo = !L_ECHO(tty); + + if (icanon && no_echo) + memset(buffer, 0x00, size); +} + static int tty_copy_to_user(struct tty_struct *tty, void __user *to, size_t tail, size_t n) { struct n_tty_data *ldata = tty->disc_data; size_t size = N_TTY_BUF_SIZE - tail; - const void *from = read_buf_addr(ldata, tail); + void *from = read_buf_addr(ldata, tail); int uncopied; if (n > size) { tty_audit_add_data(tty, from, size); uncopied = copy_to_user(to, from, size); + zero_buffer(tty, from, size - uncopied); if (uncopied) return uncopied; to += size; @@ -173,7 +184,9 @@ static int tty_copy_to_user(struct tty_struct *tty, void __user *to, } tty_audit_add_data(tty, from, n); - return copy_to_user(to, from, n); + uncopied = copy_to_user(to, from, n); + zero_buffer(tty, from, n - uncopied); + return uncopied; } /** @@ -1962,11 +1975,12 @@ static int copy_from_read_buf(struct tty_struct *tty, n = min(head - ldata->read_tail, N_TTY_BUF_SIZE - tail); n = min(*nr, n); if (n) { - const unsigned char *from = read_buf_addr(ldata, tail); + unsigned char *from = read_buf_addr(ldata, tail); retval = copy_to_user(*b, from, n); n -= retval; is_eof = n == 1 && *from == EOF_CHAR(tty); tty_audit_add_data(tty, from, n); + zero_buffer(tty, from, n); smp_store_release(&ldata->read_tail, ldata->read_tail + n); /* Turn single EOF into zero-length read */ if (L_EXTPROC(tty) && ldata->icanon && is_eof && -- GitLab From 2ecab0857ab03cd74bfeeb8946323cf737b12280 Mon Sep 17 00:00:00 2001 From: Aaron Ma Date: Fri, 9 Nov 2018 17:21:20 +0200 Subject: [PATCH 0151/1286] usb: xhci: fix uninitialized completion when USB3 port got wrong status commit 958c0bd86075d4ef1c936998deefe1947e539240 upstream. Realtek USB3.0 Card Reader [0bda:0328] reports wrong port status on Cannon lake PCH USB3.1 xHCI [8086:a36d] after resume from S3, after clear port reset it works fine. Since this device is registered on USB3 roothub at boot, when port status reports not superspeed, xhci_get_port_status will call an uninitialized completion in bus_state[0]. Kernel will hang because of NULL pointer. Restrict the USB2 resume status check in USB2 roothub to fix hang issue. Cc: stable@vger.kernel.org Signed-off-by: Aaron Ma Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-hub.c | 2 +- drivers/usb/host/xhci-ring.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index a2e350d28c05..6b2f6c41e2a9 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -895,7 +895,7 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd, status |= USB_PORT_STAT_SUSPEND; } if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && - !DEV_SUPERSPEED_ANY(raw_port_status)) { + !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) { if ((raw_port_status & PORT_RESET) || !(raw_port_status & PORT_PE)) return 0xffffffff; diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 998f61d82689..aa230706b875 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -1746,7 +1746,7 @@ static void handle_port_status(struct xhci_hcd *xhci, * RExit to a disconnect state). If so, let the the driver know it's * out of the RExit state. */ - if (!DEV_SUPERSPEED_ANY(portsc) && + if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 && test_and_clear_bit(faked_port_index, &bus_state->rexit_ports)) { complete(&bus_state->rexit_done[faked_port_index]); -- GitLab From 7bcfd8f985f2c7bf7be6a08333dfaf31ed58ccd4 Mon Sep 17 00:00:00 2001 From: Salvatore Mesoraca Date: Thu, 23 Aug 2018 17:00:35 -0700 Subject: [PATCH 0152/1286] namei: allow restricted O_CREAT of FIFOs and regular files commit 30aba6656f61ed44cba445a3c0d38b296fa9e8f5 upstream. Disallows open of FIFOs or regular files not owned by the user in world writable sticky directories, unless the owner is the same as that of the directory or the file is opened without the O_CREAT flag. The purpose is to make data spoofing attacks harder. This protection can be turned on and off separately for FIFOs and regular files via sysctl, just like the symlinks/hardlinks protection. This patch is based on Openwall's "HARDEN_FIFO" feature by Solar Designer. This is a brief list of old vulnerabilities that could have been prevented by this feature, some of them even allow for privilege escalation: CVE-2000-1134 CVE-2007-3852 CVE-2008-0525 CVE-2009-0416 CVE-2011-4834 CVE-2015-1838 CVE-2015-7442 CVE-2016-7489 This list is not meant to be complete. It's difficult to track down all vulnerabilities of this kind because they were often reported without any mention of this particular attack vector. In fact, before hardlinks/symlinks restrictions, fifos/regular files weren't the favorite vehicle to exploit them. [s.mesoraca16@gmail.com: fix bug reported by Dan Carpenter] Link: https://lkml.kernel.org/r/20180426081456.GA7060@mwanda Link: http://lkml.kernel.org/r/1524829819-11275-1-git-send-email-s.mesoraca16@gmail.com [keescook@chromium.org: drop pr_warn_ratelimited() in favor of audit changes in the future] [keescook@chromium.org: adjust commit subjet] Link: http://lkml.kernel.org/r/20180416175918.GA13494@beast Signed-off-by: Salvatore Mesoraca Signed-off-by: Kees Cook Suggested-by: Solar Designer Suggested-by: Kees Cook Cc: Al Viro Cc: Dan Carpenter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Cc: Loic Signed-off-by: Greg Kroah-Hartman --- Documentation/sysctl/fs.txt | 36 +++++++++++++++++++++++++ fs/namei.c | 53 ++++++++++++++++++++++++++++++++++--- include/linux/fs.h | 2 ++ kernel/sysctl.c | 18 +++++++++++++ 4 files changed, 106 insertions(+), 3 deletions(-) diff --git a/Documentation/sysctl/fs.txt b/Documentation/sysctl/fs.txt index 35e17f748ca7..af5859b2d0f9 100644 --- a/Documentation/sysctl/fs.txt +++ b/Documentation/sysctl/fs.txt @@ -34,7 +34,9 @@ Currently, these files are in /proc/sys/fs: - overflowgid - pipe-user-pages-hard - pipe-user-pages-soft +- protected_fifos - protected_hardlinks +- protected_regular - protected_symlinks - suid_dumpable - super-max @@ -182,6 +184,24 @@ applied. ============================================================== +protected_fifos: + +The intent of this protection is to avoid unintentional writes to +an attacker-controlled FIFO, where a program expected to create a regular +file. + +When set to "0", writing to FIFOs is unrestricted. + +When set to "1" don't allow O_CREAT open on FIFOs that we don't own +in world writable sticky directories, unless they are owned by the +owner of the directory. + +When set to "2" it also applies to group writable sticky directories. + +This protection is based on the restrictions in Openwall. + +============================================================== + protected_hardlinks: A long-standing class of security issues is the hardlink-based @@ -202,6 +222,22 @@ This protection is based on the restrictions in Openwall and grsecurity. ============================================================== +protected_regular: + +This protection is similar to protected_fifos, but it +avoids writes to an attacker-controlled regular file, where a program +expected to create one. + +When set to "0", writing to regular files is unrestricted. + +When set to "1" don't allow O_CREAT open on regular files that we +don't own in world writable sticky directories, unless they are +owned by the owner of the directory. + +When set to "2" it also applies to group writable sticky directories. + +============================================================== + protected_symlinks: A long-standing class of security issues is the symlink-based diff --git a/fs/namei.c b/fs/namei.c index 0b46b858cd42..d1e467b7b9de 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -904,6 +904,8 @@ static inline void put_link(struct nameidata *nd) int sysctl_protected_symlinks __read_mostly = 0; int sysctl_protected_hardlinks __read_mostly = 0; +int sysctl_protected_fifos __read_mostly; +int sysctl_protected_regular __read_mostly; /** * may_follow_link - Check symlink following for unsafe situations @@ -1017,6 +1019,45 @@ static int may_linkat(struct path *link) return -EPERM; } +/** + * may_create_in_sticky - Check whether an O_CREAT open in a sticky directory + * should be allowed, or not, on files that already + * exist. + * @dir: the sticky parent directory + * @inode: the inode of the file to open + * + * Block an O_CREAT open of a FIFO (or a regular file) when: + * - sysctl_protected_fifos (or sysctl_protected_regular) is enabled + * - the file already exists + * - we are in a sticky directory + * - we don't own the file + * - the owner of the directory doesn't own the file + * - the directory is world writable + * If the sysctl_protected_fifos (or sysctl_protected_regular) is set to 2 + * the directory doesn't have to be world writable: being group writable will + * be enough. + * + * Returns 0 if the open is allowed, -ve on error. + */ +static int may_create_in_sticky(struct dentry * const dir, + struct inode * const inode) +{ + if ((!sysctl_protected_fifos && S_ISFIFO(inode->i_mode)) || + (!sysctl_protected_regular && S_ISREG(inode->i_mode)) || + likely(!(dir->d_inode->i_mode & S_ISVTX)) || + uid_eq(inode->i_uid, dir->d_inode->i_uid) || + uid_eq(current_fsuid(), inode->i_uid)) + return 0; + + if (likely(dir->d_inode->i_mode & 0002) || + (dir->d_inode->i_mode & 0020 && + ((sysctl_protected_fifos >= 2 && S_ISFIFO(inode->i_mode)) || + (sysctl_protected_regular >= 2 && S_ISREG(inode->i_mode))))) { + return -EACCES; + } + return 0; +} + static __always_inline const char *get_link(struct nameidata *nd) { @@ -3355,9 +3396,15 @@ static int do_last(struct nameidata *nd, if (error) return error; audit_inode(nd->name, nd->path.dentry, 0); - error = -EISDIR; - if ((open_flag & O_CREAT) && d_is_dir(nd->path.dentry)) - goto out; + if (open_flag & O_CREAT) { + error = -EISDIR; + if (d_is_dir(nd->path.dentry)) + goto out; + error = may_create_in_sticky(dir, + d_backing_inode(nd->path.dentry)); + if (unlikely(error)) + goto out; + } error = -ENOTDIR; if ((nd->flags & LOOKUP_DIRECTORY) && !d_can_lookup(nd->path.dentry)) goto out; diff --git a/include/linux/fs.h b/include/linux/fs.h index 7374639f0aa0..f6a577edec67 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -72,6 +72,8 @@ extern struct inodes_stat_t inodes_stat; extern int leases_enable, lease_break_time; extern int sysctl_protected_symlinks; extern int sysctl_protected_hardlinks; +extern int sysctl_protected_fifos; +extern int sysctl_protected_regular; typedef __kernel_rwf_t rwf_t; diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 069550540a39..d330b1ce3b94 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -1793,6 +1793,24 @@ static struct ctl_table fs_table[] = { .extra1 = &zero, .extra2 = &one, }, + { + .procname = "protected_fifos", + .data = &sysctl_protected_fifos, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &two, + }, + { + .procname = "protected_regular", + .data = &sysctl_protected_regular, + .maxlen = sizeof(int), + .mode = 0600, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &two, + }, { .procname = "suid_dumpable", .data = &suid_dumpable, -- GitLab From a4977f3e8a3a668878543828ceaf40d69b5bfc32 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 19 Apr 2018 17:59:38 +0100 Subject: [PATCH 0153/1286] lan78xx: Read MAC address from DT if present commit 760db29bdc97b73ff60b091315ad787b1deb5cf5 upstream. There is a standard mechanism for locating and using a MAC address from the Device Tree. Use this facility in the lan78xx driver to support applications without programmed EEPROM or OTP. At the same time, regularise the handling of the different address sources. Signed-off-by: Phil Elwell Signed-off-by: David S. Miller Tested-by: Paolo Pisati Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/lan78xx.c | 42 +++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index 50e2e10a9050..e069b310d6a6 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "lan78xx.h" #define DRIVER_AUTHOR "WOOJUNG HUH " @@ -1645,34 +1646,31 @@ static void lan78xx_init_mac_address(struct lan78xx_net *dev) addr[5] = (addr_hi >> 8) & 0xFF; if (!is_valid_ether_addr(addr)) { - /* reading mac address from EEPROM or OTP */ - if ((lan78xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, - addr) == 0) || - (lan78xx_read_otp(dev, EEPROM_MAC_OFFSET, ETH_ALEN, - addr) == 0)) { - if (is_valid_ether_addr(addr)) { - /* eeprom values are valid so use them */ - netif_dbg(dev, ifup, dev->net, - "MAC address read from EEPROM"); - } else { - /* generate random MAC */ - random_ether_addr(addr); - netif_dbg(dev, ifup, dev->net, - "MAC address set to random addr"); - } - - addr_lo = addr[0] | (addr[1] << 8) | - (addr[2] << 16) | (addr[3] << 24); - addr_hi = addr[4] | (addr[5] << 8); - - ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo); - ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi); + if (!eth_platform_get_mac_address(&dev->udev->dev, addr)) { + /* valid address present in Device Tree */ + netif_dbg(dev, ifup, dev->net, + "MAC address read from Device Tree"); + } else if (((lan78xx_read_eeprom(dev, EEPROM_MAC_OFFSET, + ETH_ALEN, addr) == 0) || + (lan78xx_read_otp(dev, EEPROM_MAC_OFFSET, + ETH_ALEN, addr) == 0)) && + is_valid_ether_addr(addr)) { + /* eeprom values are valid so use them */ + netif_dbg(dev, ifup, dev->net, + "MAC address read from EEPROM"); } else { /* generate random MAC */ random_ether_addr(addr); netif_dbg(dev, ifup, dev->net, "MAC address set to random addr"); } + + addr_lo = addr[0] | (addr[1] << 8) | + (addr[2] << 16) | (addr[3] << 24); + addr_hi = addr[4] | (addr[5] << 8); + + ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo); + ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi); } ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo); -- GitLab From aef9f7db7e8cf0cd5357e5b449669af1e7cdccad Mon Sep 17 00:00:00 2001 From: Janosch Frank Date: Thu, 16 Aug 2018 09:02:31 +0100 Subject: [PATCH 0154/1286] s390/mm: Check for valid vma before zapping in gmap_discard commit 1843abd03250115af6cec0892683e70cf2297c25 upstream. Userspace could have munmapped the area before doing unmapping from the gmap. This would leave us with a valid vmaddr, but an invalid vma from which we would try to zap memory. Let's check before using the vma. Fixes: 1e133ab296f3 ("s390/mm: split arch/s390/mm/pgtable.c") Signed-off-by: Janosch Frank Reviewed-by: David Hildenbrand Reported-by: Dan Carpenter Message-Id: <20180816082432.78828-1-frankja@linux.ibm.com> Signed-off-by: Janosch Frank Signed-off-by: Greg Kroah-Hartman --- arch/s390/mm/gmap.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/s390/mm/gmap.c b/arch/s390/mm/gmap.c index 2f66290c9b92..ec9292917d3f 100644 --- a/arch/s390/mm/gmap.c +++ b/arch/s390/mm/gmap.c @@ -689,6 +689,8 @@ void gmap_discard(struct gmap *gmap, unsigned long from, unsigned long to) vmaddr |= gaddr & ~PMD_MASK; /* Find vma in the parent mm */ vma = find_vma(gmap->mm, vmaddr); + if (!vma) + continue; size = min(to - gaddr, PMD_SIZE - (gaddr & ~PMD_MASK)); zap_page_range(vma, vmaddr, size); } -- GitLab From 077506972ba23772b752e08b1ab7052cf5f04511 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 9 Jul 2018 13:47:30 -0700 Subject: [PATCH 0155/1286] rcu: Make need_resched() respond to urgent RCU-QS needs commit 92aa39e9dc77481b90cbef25e547d66cab901496 upstream. The per-CPU rcu_dynticks.rcu_urgent_qs variable communicates an urgent need for an RCU quiescent state from the force-quiescent-state processing within the grace-period kthread to context switches and to cond_resched(). Unfortunately, such urgent needs are not communicated to need_resched(), which is sometimes used to decide when to invoke cond_resched(), for but one example, within the KVM vcpu_run() function. As of v4.15, this can result in synchronize_sched() being delayed by up to ten seconds, which can be problematic, to say nothing of annoying. This commit therefore checks rcu_dynticks.rcu_urgent_qs from within rcu_check_callbacks(), which is invoked from the scheduling-clock interrupt handler. If the current task is not an idle task and is not executing in usermode, a context switch is forced, and either way, the rcu_dynticks.rcu_urgent_qs variable is set to false. If the current task is an idle task, then RCU's dyntick-idle code will detect the quiescent state, so no further action is required. Similarly, if the task is executing in usermode, other code in rcu_check_callbacks() and its called functions will report the corresponding quiescent state. Reported-by: Marius Hillenbrand Reported-by: David Woodhouse Suggested-by: Peter Zijlstra Signed-off-by: Paul E. McKenney [ paulmck: Backported to make patch apply cleanly on older versions. ] Tested-by: Marius Hillenbrand Cc: # 4.12.x - 4.19.x Signed-off-by: Greg Kroah-Hartman --- kernel/rcu/tree.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 3e3650e94ae6..710ce1d6b982 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -2772,6 +2772,15 @@ void rcu_check_callbacks(int user) rcu_bh_qs(); } rcu_preempt_check_callbacks(); + /* The load-acquire pairs with the store-release setting to true. */ + if (smp_load_acquire(this_cpu_ptr(&rcu_dynticks.rcu_urgent_qs))) { + /* Idle and userspace execution already are quiescent states. */ + if (!rcu_is_cpu_rrupt_from_idle() && !user) { + set_tsk_need_resched(current); + set_preempt_need_resched(); + } + __this_cpu_write(rcu_dynticks.rcu_urgent_qs, false); + } if (rcu_pending()) invoke_rcu_core(); if (user) -- GitLab From 57ccd1fc8ebbd656594354ab0213754fcda03bde Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Fri, 20 Apr 2018 14:54:13 -0400 Subject: [PATCH 0156/1286] net: ieee802154: 6lowpan: fix frag reassembly commit f18fa5de5ba7f1d6650951502bb96a6e4715a948 upstream. This patch initialize stack variables which are used in frag_lowpan_compare_key to zero. In my case there are padding bytes in the structures ieee802154_addr as well in frag_lowpan_compare_key. Otherwise the key variable contains random bytes. The result is that a compare of two keys by memcmp works incorrect. Fixes: 648700f76b03 ("inet: frags: use rhashtables for reassembly units") Signed-off-by: Alexander Aring Reported-by: Stefan Schmidt Signed-off-by: Stefan Schmidt Signed-off-by: Greg Kroah-Hartman --- net/ieee802154/6lowpan/6lowpan_i.h | 4 ++-- net/ieee802154/6lowpan/reassembly.c | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/net/ieee802154/6lowpan/6lowpan_i.h b/net/ieee802154/6lowpan/6lowpan_i.h index b8d95cb71c25..44a7e16bf3b5 100644 --- a/net/ieee802154/6lowpan/6lowpan_i.h +++ b/net/ieee802154/6lowpan/6lowpan_i.h @@ -20,8 +20,8 @@ typedef unsigned __bitwise lowpan_rx_result; struct frag_lowpan_compare_key { u16 tag; u16 d_size; - const struct ieee802154_addr src; - const struct ieee802154_addr dst; + struct ieee802154_addr src; + struct ieee802154_addr dst; }; /* Equivalent of ipv4 struct ipq diff --git a/net/ieee802154/6lowpan/reassembly.c b/net/ieee802154/6lowpan/reassembly.c index 1790b65944b3..2cc224106b69 100644 --- a/net/ieee802154/6lowpan/reassembly.c +++ b/net/ieee802154/6lowpan/reassembly.c @@ -75,14 +75,14 @@ fq_find(struct net *net, const struct lowpan_802154_cb *cb, { struct netns_ieee802154_lowpan *ieee802154_lowpan = net_ieee802154_lowpan(net); - struct frag_lowpan_compare_key key = { - .tag = cb->d_tag, - .d_size = cb->d_size, - .src = *src, - .dst = *dst, - }; + struct frag_lowpan_compare_key key = {}; struct inet_frag_queue *q; + key.tag = cb->d_tag; + key.d_size = cb->d_size; + key.src = *src; + key.dst = *dst; + q = inet_frag_find(&ieee802154_lowpan->frags, &key); if (!q) return NULL; @@ -372,7 +372,7 @@ int lowpan_frag_rcv(struct sk_buff *skb, u8 frag_type) struct lowpan_frag_queue *fq; struct net *net = dev_net(skb->dev); struct lowpan_802154_cb *cb = lowpan_802154_cb(skb); - struct ieee802154_hdr hdr; + struct ieee802154_hdr hdr = {}; int err; if (ieee802154_hdr_peek_addrs(skb, &hdr) < 0) -- GitLab From de72a0f9ad28895b57b9403ae29aa5a6a579f31d Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Sat, 17 Jun 2017 23:56:23 -0400 Subject: [PATCH 0157/1286] ima: always measure and audit files in policy commit f3cc6b25dcc5616f0d5c720009b2ac66f97df2ff upstream. All files matching a "measure" rule must be included in the IMA measurement list, even when the file hash cannot be calculated. Similarly, all files matching an "audit" rule must be audited, even when the file hash can not be calculated. The file data hash field contained in the IMA measurement list template data will contain 0's instead of the actual file hash digest. Note: In general, adding, deleting or in anyway changing which files are included in the IMA measurement list is not a good idea, as it might result in not being able to unseal trusted keys sealed to a specific TPM PCR value. This patch not only adds file measurements that were not previously measured, but specifies that the file hash value for these files will be 0's. As the IMA measurement list ordering is not consistent from one boot to the next, it is unlikely that anyone is sealing keys based on the IMA measurement list. Remote attestation servers should be able to process these new measurement records, but might complain about these unknown records. Signed-off-by: Mimi Zohar Reviewed-by: Dmitry Kasatkin Cc: Aditya Kali Signed-off-by: Greg Kroah-Hartman --- security/integrity/ima/ima_api.c | 67 ++++++++++++++++++----------- security/integrity/ima/ima_crypto.c | 10 +++++ security/integrity/ima/ima_main.c | 9 ++-- 3 files changed, 56 insertions(+), 30 deletions(-) diff --git a/security/integrity/ima/ima_api.c b/security/integrity/ima/ima_api.c index c2edba8de35e..c7e8db0ea4c0 100644 --- a/security/integrity/ima/ima_api.c +++ b/security/integrity/ima/ima_api.c @@ -199,42 +199,59 @@ int ima_collect_measurement(struct integrity_iint_cache *iint, struct inode *inode = file_inode(file); const char *filename = file->f_path.dentry->d_name.name; int result = 0; + int length; + void *tmpbuf; + u64 i_version; struct { struct ima_digest_data hdr; char digest[IMA_MAX_DIGEST_SIZE]; } hash; - if (!(iint->flags & IMA_COLLECTED)) { - u64 i_version = file_inode(file)->i_version; + if (iint->flags & IMA_COLLECTED) + goto out; - if (file->f_flags & O_DIRECT) { - audit_cause = "failed(directio)"; - result = -EACCES; - goto out; - } + /* + * Dectecting file change is based on i_version. On filesystems + * which do not support i_version, support is limited to an initial + * measurement/appraisal/audit. + */ + i_version = file_inode(file)->i_version; + hash.hdr.algo = algo; - hash.hdr.algo = algo; - - result = (!buf) ? ima_calc_file_hash(file, &hash.hdr) : - ima_calc_buffer_hash(buf, size, &hash.hdr); - if (!result) { - int length = sizeof(hash.hdr) + hash.hdr.length; - void *tmpbuf = krealloc(iint->ima_hash, length, - GFP_NOFS); - if (tmpbuf) { - iint->ima_hash = tmpbuf; - memcpy(iint->ima_hash, &hash, length); - iint->version = i_version; - iint->flags |= IMA_COLLECTED; - } else - result = -ENOMEM; - } + /* Initialize hash digest to 0's in case of failure */ + memset(&hash.digest, 0, sizeof(hash.digest)); + + if (buf) + result = ima_calc_buffer_hash(buf, size, &hash.hdr); + else + result = ima_calc_file_hash(file, &hash.hdr); + + if (result && result != -EBADF && result != -EINVAL) + goto out; + + length = sizeof(hash.hdr) + hash.hdr.length; + tmpbuf = krealloc(iint->ima_hash, length, GFP_NOFS); + if (!tmpbuf) { + result = -ENOMEM; + goto out; } + + iint->ima_hash = tmpbuf; + memcpy(iint->ima_hash, &hash, length); + iint->version = i_version; + + /* Possibly temporary failure due to type of read (eg. O_DIRECT) */ + if (!result) + iint->flags |= IMA_COLLECTED; out: - if (result) + if (result) { + if (file->f_flags & O_DIRECT) + audit_cause = "failed(directio)"; + integrity_audit_msg(AUDIT_INTEGRITY_DATA, inode, filename, "collect_data", audit_cause, result, 0); + } return result; } @@ -278,7 +295,7 @@ void ima_store_measurement(struct integrity_iint_cache *iint, } result = ima_store_template(entry, violation, inode, filename, pcr); - if (!result || result == -EEXIST) { + if ((!result || result == -EEXIST) && !(file->f_flags & O_DIRECT)) { iint->flags |= IMA_MEASURED; iint->measured_pcrs |= (0x1 << pcr); } diff --git a/security/integrity/ima/ima_crypto.c b/security/integrity/ima/ima_crypto.c index 90453aa1c813..cb041af9eddb 100644 --- a/security/integrity/ima/ima_crypto.c +++ b/security/integrity/ima/ima_crypto.c @@ -443,6 +443,16 @@ int ima_calc_file_hash(struct file *file, struct ima_digest_data *hash) loff_t i_size; int rc; + /* + * For consistency, fail file's opened with the O_DIRECT flag on + * filesystems mounted with/without DAX option. + */ + if (file->f_flags & O_DIRECT) { + hash->length = hash_digest_size[ima_hash_algo]; + hash->algo = ima_hash_algo; + return -EINVAL; + } + i_size = i_size_read(file_inode(file)); if (ima_ahash_minsize && i_size >= ima_ahash_minsize) { diff --git a/security/integrity/ima/ima_main.c b/security/integrity/ima/ima_main.c index f8553179bdd7..06c4cf125f2a 100644 --- a/security/integrity/ima/ima_main.c +++ b/security/integrity/ima/ima_main.c @@ -242,11 +242,8 @@ static int process_measurement(struct file *file, char *buf, loff_t size, hash_algo = ima_get_hash_algo(xattr_value, xattr_len); rc = ima_collect_measurement(iint, file, buf, size, hash_algo); - if (rc != 0) { - if (file->f_flags & O_DIRECT) - rc = (iint->flags & IMA_PERMIT_DIRECTIO) ? 0 : -EACCES; + if (rc != 0 && rc != -EBADF && rc != -EINVAL) goto out_digsig; - } if (!pathbuf) /* ima_rdwr_violation possibly pre-fetched */ pathname = ima_d_path(&file->f_path, &pathbuf, filename); @@ -254,12 +251,14 @@ static int process_measurement(struct file *file, char *buf, loff_t size, if (action & IMA_MEASURE) ima_store_measurement(iint, file, pathname, xattr_value, xattr_len, pcr); - if (action & IMA_APPRAISE_SUBMASK) + if (rc == 0 && (action & IMA_APPRAISE_SUBMASK)) rc = ima_appraise_measurement(func, iint, file, pathname, xattr_value, xattr_len, opened); if (action & IMA_AUDIT) ima_audit_measurement(iint, pathname); + if ((file->f_flags & O_DIRECT) && (iint->flags & IMA_PERMIT_DIRECTIO)) + rc = 0; out_digsig: if ((mask & MAY_WRITE) && (iint->flags & IMA_DIGSIG) && !(iint->flags & IMA_NEW_FILE)) -- GitLab From e099863340d86741c0957217971c29becf24b881 Mon Sep 17 00:00:00 2001 From: Matthew Garrett Date: Tue, 7 Nov 2017 07:17:42 -0800 Subject: [PATCH 0158/1286] EVM: Add support for portable signature format commit 50b977481fce90aa5fbda55e330b9d722733e358 upstream. The EVM signature includes the inode number and (optionally) the filesystem UUID, making it impractical to ship EVM signatures in packages. This patch adds a new portable format intended to allow distributions to include EVM signatures. It is identical to the existing format but hardcodes the inode and generation numbers to 0 and does not include the filesystem UUID even if the kernel is configured to do so. Removing the inode means that the metadata and signature from one file could be copied to another file without invalidating it. This is avoided by ensuring that an IMA xattr is present during EVM validation. Portable signatures are intended to be immutable - ie, they will never be transformed into HMACs. Based on earlier work by Dmitry Kasatkin and Mikhail Kurinnoi. Signed-off-by: Matthew Garrett Cc: Dmitry Kasatkin Cc: Mikhail Kurinnoi Signed-off-by: Mimi Zohar Cc: Aditya Kali Signed-off-by: Greg Kroah-Hartman --- include/linux/integrity.h | 1 + security/integrity/evm/evm.h | 2 +- security/integrity/evm/evm_crypto.c | 75 +++++++++++++++++++++++---- security/integrity/evm/evm_main.c | 29 +++++++---- security/integrity/ima/ima_appraise.c | 4 +- security/integrity/integrity.h | 2 + 6 files changed, 92 insertions(+), 21 deletions(-) diff --git a/include/linux/integrity.h b/include/linux/integrity.h index c2d6082a1a4c..858d3f4a2241 100644 --- a/include/linux/integrity.h +++ b/include/linux/integrity.h @@ -14,6 +14,7 @@ enum integrity_status { INTEGRITY_PASS = 0, + INTEGRITY_PASS_IMMUTABLE, INTEGRITY_FAIL, INTEGRITY_NOLABEL, INTEGRITY_NOXATTRS, diff --git a/security/integrity/evm/evm.h b/security/integrity/evm/evm.h index f5f12727771a..2ff02459fcfd 100644 --- a/security/integrity/evm/evm.h +++ b/security/integrity/evm/evm.h @@ -48,7 +48,7 @@ int evm_calc_hmac(struct dentry *dentry, const char *req_xattr_name, size_t req_xattr_value_len, char *digest); int evm_calc_hash(struct dentry *dentry, const char *req_xattr_name, const char *req_xattr_value, - size_t req_xattr_value_len, char *digest); + size_t req_xattr_value_len, char type, char *digest); int evm_init_hmac(struct inode *inode, const struct xattr *xattr, char *hmac_val); int evm_init_secfs(void); diff --git a/security/integrity/evm/evm_crypto.c b/security/integrity/evm/evm_crypto.c index ee9c3de5065a..f1f030ae363b 100644 --- a/security/integrity/evm/evm_crypto.c +++ b/security/integrity/evm/evm_crypto.c @@ -139,7 +139,7 @@ static struct shash_desc *init_desc(char type) * protection.) */ static void hmac_add_misc(struct shash_desc *desc, struct inode *inode, - char *digest) + char type, char *digest) { struct h_misc { unsigned long ino; @@ -150,8 +150,13 @@ static void hmac_add_misc(struct shash_desc *desc, struct inode *inode, } hmac_misc; memset(&hmac_misc, 0, sizeof(hmac_misc)); - hmac_misc.ino = inode->i_ino; - hmac_misc.generation = inode->i_generation; + /* Don't include the inode or generation number in portable + * signatures + */ + if (type != EVM_XATTR_PORTABLE_DIGSIG) { + hmac_misc.ino = inode->i_ino; + hmac_misc.generation = inode->i_generation; + } /* The hmac uid and gid must be encoded in the initial user * namespace (not the filesystems user namespace) as encoding * them in the filesystems user namespace allows an attack @@ -164,7 +169,8 @@ static void hmac_add_misc(struct shash_desc *desc, struct inode *inode, hmac_misc.gid = from_kgid(&init_user_ns, inode->i_gid); hmac_misc.mode = inode->i_mode; crypto_shash_update(desc, (const u8 *)&hmac_misc, sizeof(hmac_misc)); - if (evm_hmac_attrs & EVM_ATTR_FSUUID) + if ((evm_hmac_attrs & EVM_ATTR_FSUUID) && + type != EVM_XATTR_PORTABLE_DIGSIG) crypto_shash_update(desc, &inode->i_sb->s_uuid.b[0], sizeof(inode->i_sb->s_uuid)); crypto_shash_final(desc, digest); @@ -190,6 +196,7 @@ static int evm_calc_hmac_or_hash(struct dentry *dentry, char *xattr_value = NULL; int error; int size; + bool ima_present = false; if (!(inode->i_opflags & IOP_XATTR)) return -EOPNOTSUPP; @@ -200,11 +207,18 @@ static int evm_calc_hmac_or_hash(struct dentry *dentry, error = -ENODATA; for (xattrname = evm_config_xattrnames; *xattrname != NULL; xattrname++) { + bool is_ima = false; + + if (strcmp(*xattrname, XATTR_NAME_IMA) == 0) + is_ima = true; + if ((req_xattr_name && req_xattr_value) && !strcmp(*xattrname, req_xattr_name)) { error = 0; crypto_shash_update(desc, (const u8 *)req_xattr_value, req_xattr_value_len); + if (is_ima) + ima_present = true; continue; } size = vfs_getxattr_alloc(dentry, *xattrname, @@ -219,9 +233,14 @@ static int evm_calc_hmac_or_hash(struct dentry *dentry, error = 0; xattr_size = size; crypto_shash_update(desc, (const u8 *)xattr_value, xattr_size); + if (is_ima) + ima_present = true; } - hmac_add_misc(desc, inode, digest); + hmac_add_misc(desc, inode, type, digest); + /* Portable EVM signatures must include an IMA hash */ + if (type == EVM_XATTR_PORTABLE_DIGSIG && !ima_present) + return -EPERM; out: kfree(xattr_value); kfree(desc); @@ -233,17 +252,45 @@ int evm_calc_hmac(struct dentry *dentry, const char *req_xattr_name, char *digest) { return evm_calc_hmac_or_hash(dentry, req_xattr_name, req_xattr_value, - req_xattr_value_len, EVM_XATTR_HMAC, digest); + req_xattr_value_len, EVM_XATTR_HMAC, digest); } int evm_calc_hash(struct dentry *dentry, const char *req_xattr_name, const char *req_xattr_value, size_t req_xattr_value_len, - char *digest) + char type, char *digest) { return evm_calc_hmac_or_hash(dentry, req_xattr_name, req_xattr_value, - req_xattr_value_len, IMA_XATTR_DIGEST, digest); + req_xattr_value_len, type, digest); +} + +static int evm_is_immutable(struct dentry *dentry, struct inode *inode) +{ + const struct evm_ima_xattr_data *xattr_data = NULL; + struct integrity_iint_cache *iint; + int rc = 0; + + iint = integrity_iint_find(inode); + if (iint && (iint->flags & EVM_IMMUTABLE_DIGSIG)) + return 1; + + /* Do this the hard way */ + rc = vfs_getxattr_alloc(dentry, XATTR_NAME_EVM, (char **)&xattr_data, 0, + GFP_NOFS); + if (rc <= 0) { + if (rc == -ENODATA) + return 0; + return rc; + } + if (xattr_data->type == EVM_XATTR_PORTABLE_DIGSIG) + rc = 1; + else + rc = 0; + + kfree(xattr_data); + return rc; } + /* * Calculate the hmac and update security.evm xattr * @@ -256,6 +303,16 @@ int evm_update_evmxattr(struct dentry *dentry, const char *xattr_name, struct evm_ima_xattr_data xattr_data; int rc = 0; + /* + * Don't permit any transformation of the EVM xattr if the signature + * is of an immutable type + */ + rc = evm_is_immutable(dentry, inode); + if (rc < 0) + return rc; + if (rc) + return -EPERM; + rc = evm_calc_hmac(dentry, xattr_name, xattr_value, xattr_value_len, xattr_data.digest); if (rc == 0) { @@ -281,7 +338,7 @@ int evm_init_hmac(struct inode *inode, const struct xattr *lsm_xattr, } crypto_shash_update(desc, lsm_xattr->value, lsm_xattr->value_len); - hmac_add_misc(desc, inode, hmac_val); + hmac_add_misc(desc, inode, EVM_XATTR_HMAC, hmac_val); kfree(desc); return 0; } diff --git a/security/integrity/evm/evm_main.c b/security/integrity/evm/evm_main.c index 063d38aef64e..1d1a7053144b 100644 --- a/security/integrity/evm/evm_main.c +++ b/security/integrity/evm/evm_main.c @@ -31,7 +31,7 @@ int evm_initialized; static char *integrity_status_msg[] = { - "pass", "fail", "no_label", "no_xattrs", "unknown" + "pass", "pass_immutable", "fail", "no_label", "no_xattrs", "unknown" }; char *evm_hmac = "hmac(sha1)"; char *evm_hash = "sha1"; @@ -120,7 +120,8 @@ static enum integrity_status evm_verify_hmac(struct dentry *dentry, enum integrity_status evm_status = INTEGRITY_PASS; int rc, xattr_len; - if (iint && iint->evm_status == INTEGRITY_PASS) + if (iint && (iint->evm_status == INTEGRITY_PASS || + iint->evm_status == INTEGRITY_PASS_IMMUTABLE)) return iint->evm_status; /* if status is not PASS, try to check again - against -ENOMEM */ @@ -161,22 +162,26 @@ static enum integrity_status evm_verify_hmac(struct dentry *dentry, rc = -EINVAL; break; case EVM_IMA_XATTR_DIGSIG: + case EVM_XATTR_PORTABLE_DIGSIG: rc = evm_calc_hash(dentry, xattr_name, xattr_value, - xattr_value_len, calc.digest); + xattr_value_len, xattr_data->type, + calc.digest); if (rc) break; rc = integrity_digsig_verify(INTEGRITY_KEYRING_EVM, (const char *)xattr_data, xattr_len, calc.digest, sizeof(calc.digest)); if (!rc) { - /* Replace RSA with HMAC if not mounted readonly and - * not immutable - */ - if (!IS_RDONLY(d_backing_inode(dentry)) && - !IS_IMMUTABLE(d_backing_inode(dentry))) + if (xattr_data->type == EVM_XATTR_PORTABLE_DIGSIG) { + if (iint) + iint->flags |= EVM_IMMUTABLE_DIGSIG; + evm_status = INTEGRITY_PASS_IMMUTABLE; + } else if (!IS_RDONLY(d_backing_inode(dentry)) && + !IS_IMMUTABLE(d_backing_inode(dentry))) { evm_update_evmxattr(dentry, xattr_name, xattr_value, xattr_value_len); + } } break; default: @@ -277,7 +282,7 @@ static enum integrity_status evm_verify_current_integrity(struct dentry *dentry) * affect security.evm. An interesting side affect of writing posix xattr * acls is their modifying of the i_mode, which is included in security.evm. * For posix xattr acls only, permit security.evm, even if it currently - * doesn't exist, to be updated. + * doesn't exist, to be updated unless the EVM signature is immutable. */ static int evm_protect_xattr(struct dentry *dentry, const char *xattr_name, const void *xattr_value, size_t xattr_value_len) @@ -345,7 +350,8 @@ int evm_inode_setxattr(struct dentry *dentry, const char *xattr_name, if (strcmp(xattr_name, XATTR_NAME_EVM) == 0) { if (!xattr_value_len) return -EINVAL; - if (xattr_data->type != EVM_IMA_XATTR_DIGSIG) + if (xattr_data->type != EVM_IMA_XATTR_DIGSIG && + xattr_data->type != EVM_XATTR_PORTABLE_DIGSIG) return -EPERM; } return evm_protect_xattr(dentry, xattr_name, xattr_value, @@ -422,6 +428,9 @@ void evm_inode_post_removexattr(struct dentry *dentry, const char *xattr_name) /** * evm_inode_setattr - prevent updating an invalid EVM extended attribute * @dentry: pointer to the affected dentry + * + * Permit update of file attributes when files have a valid EVM signature, + * except in the case of them having an immutable portable signature. */ int evm_inode_setattr(struct dentry *dentry, struct iattr *attr) { diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c index 348db9b78681..e91d28cc05cc 100644 --- a/security/integrity/ima/ima_appraise.c +++ b/security/integrity/ima/ima_appraise.c @@ -230,7 +230,9 @@ int ima_appraise_measurement(enum ima_hooks func, } status = evm_verifyxattr(dentry, XATTR_NAME_IMA, xattr_value, rc, iint); - if ((status != INTEGRITY_PASS) && (status != INTEGRITY_UNKNOWN)) { + if ((status != INTEGRITY_PASS) && + (status != INTEGRITY_PASS_IMMUTABLE) && + (status != INTEGRITY_UNKNOWN)) { if ((status == INTEGRITY_NOLABEL) || (status == INTEGRITY_NOXATTRS)) cause = "missing-HMAC"; diff --git a/security/integrity/integrity.h b/security/integrity/integrity.h index a53e7e4ab06c..cbc7de33fac7 100644 --- a/security/integrity/integrity.h +++ b/security/integrity/integrity.h @@ -33,6 +33,7 @@ #define IMA_DIGSIG_REQUIRED 0x02000000 #define IMA_PERMIT_DIRECTIO 0x04000000 #define IMA_NEW_FILE 0x08000000 +#define EVM_IMMUTABLE_DIGSIG 0x10000000 #define IMA_DO_MASK (IMA_MEASURE | IMA_APPRAISE | IMA_AUDIT | \ IMA_APPRAISE_SUBMASK) @@ -58,6 +59,7 @@ enum evm_ima_xattr_type { EVM_XATTR_HMAC, EVM_IMA_XATTR_DIGSIG, IMA_XATTR_DIGEST_NG, + EVM_XATTR_PORTABLE_DIGSIG, IMA_XATTR_LAST }; -- GitLab From 281c07f30f71b4982cb535b633e5286bf0c7d056 Mon Sep 17 00:00:00 2001 From: Dmitry Kasatkin Date: Tue, 5 Dec 2017 21:06:34 +0200 Subject: [PATCH 0159/1286] ima: re-introduce own integrity cache lock commit 0d73a55208e94fc9fb6deaeea61438cd3280d4c0 upstream. Before IMA appraisal was introduced, IMA was using own integrity cache lock along with i_mutex. process_measurement and ima_file_free took the iint->mutex first and then the i_mutex, while setxattr, chmod and chown took the locks in reverse order. To resolve the potential deadlock, i_mutex was moved to protect entire IMA functionality and the redundant iint->mutex was eliminated. Solution was based on the assumption that filesystem code does not take i_mutex further. But when file is opened with O_DIRECT flag, direct-io implementation takes i_mutex and produces deadlock. Furthermore, certain other filesystem operations, such as llseek, also take i_mutex. More recently some filesystems have replaced their filesystem specific lock with the global i_rwsem to read a file. As a result, when IMA attempts to calculate the file hash, reading the file attempts to take the i_rwsem again. To resolve O_DIRECT related deadlock problem, this patch re-introduces iint->mutex. But to eliminate the original chmod() related deadlock problem, this patch eliminates the requirement for chmod hooks to take the iint->mutex by introducing additional atomic iint->attr_flags to indicate calling of the hooks. The allowed locking order is to take the iint->mutex first and then the i_rwsem. Original flags were cleared in chmod(), setxattr() or removwxattr() hooks and tested when file was closed or opened again. New atomic flags are set or cleared in those hooks and tested to clear iint->flags on close or on open. Atomic flags are following: * IMA_CHANGE_ATTR - indicates that chATTR() was called (chmod, chown, chgrp) and file attributes have changed. On file open, it causes IMA to clear iint->flags to re-evaluate policy and perform IMA functions again. * IMA_CHANGE_XATTR - indicates that setxattr or removexattr was called and extended attributes have changed. On file open, it causes IMA to clear iint->flags IMA_DONE_MASK to re-appraise. * IMA_UPDATE_XATTR - indicates that security.ima needs to be updated. It is cleared if file policy changes and no update is needed. * IMA_DIGSIG - indicates that file security.ima has signature and file security.ima must not update to file has on file close. * IMA_MUST_MEASURE - indicates the file is in the measurement policy. Fixes: Commit 6552321831dc ("xfs: remove i_iolock and use i_rwsem in the VFS inode instead") Signed-off-by: Dmitry Kasatkin Signed-off-by: Mimi Zohar Cc: Aditya Kali Signed-off-by: Greg Kroah-Hartman --- security/integrity/iint.c | 2 + security/integrity/ima/ima_appraise.c | 27 ++++++----- security/integrity/ima/ima_main.c | 70 ++++++++++++++++++--------- security/integrity/integrity.h | 18 +++++-- 4 files changed, 77 insertions(+), 40 deletions(-) diff --git a/security/integrity/iint.c b/security/integrity/iint.c index 6fc888ca468e..2db461c38795 100644 --- a/security/integrity/iint.c +++ b/security/integrity/iint.c @@ -155,12 +155,14 @@ static void init_once(void *foo) memset(iint, 0, sizeof(*iint)); iint->version = 0; iint->flags = 0UL; + iint->atomic_flags = 0; iint->ima_file_status = INTEGRITY_UNKNOWN; iint->ima_mmap_status = INTEGRITY_UNKNOWN; iint->ima_bprm_status = INTEGRITY_UNKNOWN; iint->ima_read_status = INTEGRITY_UNKNOWN; iint->evm_status = INTEGRITY_UNKNOWN; iint->measured_pcrs = 0; + mutex_init(&iint->mutex); } static int __init integrity_iintcache_init(void) diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c index e91d28cc05cc..84eb6cc956bf 100644 --- a/security/integrity/ima/ima_appraise.c +++ b/security/integrity/ima/ima_appraise.c @@ -251,6 +251,7 @@ int ima_appraise_measurement(enum ima_hooks func, status = INTEGRITY_FAIL; break; } + clear_bit(IMA_DIGSIG, &iint->atomic_flags); if (xattr_len - sizeof(xattr_value->type) - hash_start >= iint->ima_hash->length) /* xattr length may be longer. md5 hash in previous @@ -269,7 +270,7 @@ int ima_appraise_measurement(enum ima_hooks func, status = INTEGRITY_PASS; break; case EVM_IMA_XATTR_DIGSIG: - iint->flags |= IMA_DIGSIG; + set_bit(IMA_DIGSIG, &iint->atomic_flags); rc = integrity_digsig_verify(INTEGRITY_KEYRING_IMA, (const char *)xattr_value, rc, iint->ima_hash->digest, @@ -320,7 +321,7 @@ void ima_update_xattr(struct integrity_iint_cache *iint, struct file *file) int rc = 0; /* do not collect and update hash for digital signatures */ - if (iint->flags & IMA_DIGSIG) + if (test_bit(IMA_DIGSIG, &iint->atomic_flags)) return; if (iint->ima_file_status != INTEGRITY_PASS) @@ -330,7 +331,9 @@ void ima_update_xattr(struct integrity_iint_cache *iint, struct file *file) if (rc < 0) return; + inode_lock(file_inode(file)); ima_fix_xattr(dentry, iint); + inode_unlock(file_inode(file)); } /** @@ -353,16 +356,14 @@ void ima_inode_post_setattr(struct dentry *dentry) return; must_appraise = ima_must_appraise(inode, MAY_ACCESS, POST_SETATTR); + if (!must_appraise) + __vfs_removexattr(dentry, XATTR_NAME_IMA); iint = integrity_iint_find(inode); if (iint) { - iint->flags &= ~(IMA_APPRAISE | IMA_APPRAISED | - IMA_APPRAISE_SUBMASK | IMA_APPRAISED_SUBMASK | - IMA_ACTION_RULE_FLAGS); - if (must_appraise) - iint->flags |= IMA_APPRAISE; + set_bit(IMA_CHANGE_ATTR, &iint->atomic_flags); + if (!must_appraise) + clear_bit(IMA_UPDATE_XATTR, &iint->atomic_flags); } - if (!must_appraise) - __vfs_removexattr(dentry, XATTR_NAME_IMA); } /* @@ -391,12 +392,12 @@ static void ima_reset_appraise_flags(struct inode *inode, int digsig) iint = integrity_iint_find(inode); if (!iint) return; - - iint->flags &= ~IMA_DONE_MASK; iint->measured_pcrs = 0; + set_bit(IMA_CHANGE_XATTR, &iint->atomic_flags); if (digsig) - iint->flags |= IMA_DIGSIG; - return; + set_bit(IMA_DIGSIG, &iint->atomic_flags); + else + clear_bit(IMA_DIGSIG, &iint->atomic_flags); } int ima_inode_setxattr(struct dentry *dentry, const char *xattr_name, diff --git a/security/integrity/ima/ima_main.c b/security/integrity/ima/ima_main.c index 06c4cf125f2a..92d0ca7309f9 100644 --- a/security/integrity/ima/ima_main.c +++ b/security/integrity/ima/ima_main.c @@ -99,10 +99,13 @@ static void ima_rdwr_violation_check(struct file *file, if (!iint) iint = integrity_iint_find(inode); /* IMA_MEASURE is set from reader side */ - if (iint && (iint->flags & IMA_MEASURE)) + if (iint && test_bit(IMA_MUST_MEASURE, + &iint->atomic_flags)) send_tomtou = true; } } else { + if (must_measure) + set_bit(IMA_MUST_MEASURE, &iint->atomic_flags); if ((atomic_read(&inode->i_writecount) > 0) && must_measure) send_writers = true; } @@ -124,21 +127,24 @@ static void ima_check_last_writer(struct integrity_iint_cache *iint, struct inode *inode, struct file *file) { fmode_t mode = file->f_mode; + bool update; if (!(mode & FMODE_WRITE)) return; - inode_lock(inode); + mutex_lock(&iint->mutex); if (atomic_read(&inode->i_writecount) == 1) { + update = test_and_clear_bit(IMA_UPDATE_XATTR, + &iint->atomic_flags); if ((iint->version != inode->i_version) || (iint->flags & IMA_NEW_FILE)) { iint->flags &= ~(IMA_DONE_MASK | IMA_NEW_FILE); iint->measured_pcrs = 0; - if (iint->flags & IMA_APPRAISE) + if (update) ima_update_xattr(iint, file); } } - inode_unlock(inode); + mutex_unlock(&iint->mutex); } /** @@ -171,7 +177,7 @@ static int process_measurement(struct file *file, char *buf, loff_t size, char *pathbuf = NULL; char filename[NAME_MAX]; const char *pathname = NULL; - int rc = -ENOMEM, action, must_appraise; + int rc = 0, action, must_appraise = 0; int pcr = CONFIG_IMA_MEASURE_PCR_IDX; struct evm_ima_xattr_data *xattr_value = NULL; int xattr_len = 0; @@ -202,17 +208,31 @@ static int process_measurement(struct file *file, char *buf, loff_t size, if (action) { iint = integrity_inode_get(inode); if (!iint) - goto out; + rc = -ENOMEM; } - if (violation_check) { + if (!rc && violation_check) ima_rdwr_violation_check(file, iint, action & IMA_MEASURE, &pathbuf, &pathname); - if (!action) { - rc = 0; - goto out_free; - } - } + + inode_unlock(inode); + + if (rc) + goto out; + if (!action) + goto out; + + mutex_lock(&iint->mutex); + + if (test_and_clear_bit(IMA_CHANGE_ATTR, &iint->atomic_flags)) + /* reset appraisal flags if ima_inode_post_setattr was called */ + iint->flags &= ~(IMA_APPRAISE | IMA_APPRAISED | + IMA_APPRAISE_SUBMASK | IMA_APPRAISED_SUBMASK | + IMA_ACTION_FLAGS); + + if (test_and_clear_bit(IMA_CHANGE_XATTR, &iint->atomic_flags)) + /* reset all flags if ima_inode_setxattr was called */ + iint->flags &= ~IMA_DONE_MASK; /* Determine if already appraised/measured based on bitmask * (IMA_MEASURE, IMA_MEASURED, IMA_XXXX_APPRAISE, IMA_XXXX_APPRAISED, @@ -230,7 +250,7 @@ static int process_measurement(struct file *file, char *buf, loff_t size, if (!action) { if (must_appraise) rc = ima_get_cache_status(iint, func); - goto out_digsig; + goto out_locked; } template_desc = ima_template_desc_current(); @@ -243,7 +263,7 @@ static int process_measurement(struct file *file, char *buf, loff_t size, rc = ima_collect_measurement(iint, file, buf, size, hash_algo); if (rc != 0 && rc != -EBADF && rc != -EINVAL) - goto out_digsig; + goto out_locked; if (!pathbuf) /* ima_rdwr_violation possibly pre-fetched */ pathname = ima_d_path(&file->f_path, &pathbuf, filename); @@ -251,26 +271,32 @@ static int process_measurement(struct file *file, char *buf, loff_t size, if (action & IMA_MEASURE) ima_store_measurement(iint, file, pathname, xattr_value, xattr_len, pcr); - if (rc == 0 && (action & IMA_APPRAISE_SUBMASK)) + if (rc == 0 && (action & IMA_APPRAISE_SUBMASK)) { + inode_lock(inode); rc = ima_appraise_measurement(func, iint, file, pathname, xattr_value, xattr_len, opened); + inode_unlock(inode); + } if (action & IMA_AUDIT) ima_audit_measurement(iint, pathname); if ((file->f_flags & O_DIRECT) && (iint->flags & IMA_PERMIT_DIRECTIO)) rc = 0; -out_digsig: - if ((mask & MAY_WRITE) && (iint->flags & IMA_DIGSIG) && +out_locked: + if ((mask & MAY_WRITE) && test_bit(IMA_DIGSIG, &iint->atomic_flags) && !(iint->flags & IMA_NEW_FILE)) rc = -EACCES; + mutex_unlock(&iint->mutex); kfree(xattr_value); -out_free: +out: if (pathbuf) __putname(pathbuf); -out: - inode_unlock(inode); - if ((rc && must_appraise) && (ima_appraise & IMA_APPRAISE_ENFORCE)) - return -EACCES; + if (must_appraise) { + if (rc && (ima_appraise & IMA_APPRAISE_ENFORCE)) + return -EACCES; + if (file->f_mode & FMODE_WRITE) + set_bit(IMA_UPDATE_XATTR, &iint->atomic_flags); + } return 0; } diff --git a/security/integrity/integrity.h b/security/integrity/integrity.h index cbc7de33fac7..f43ac351c172 100644 --- a/security/integrity/integrity.h +++ b/security/integrity/integrity.h @@ -29,11 +29,10 @@ /* iint cache flags */ #define IMA_ACTION_FLAGS 0xff000000 #define IMA_ACTION_RULE_FLAGS 0x06000000 -#define IMA_DIGSIG 0x01000000 -#define IMA_DIGSIG_REQUIRED 0x02000000 -#define IMA_PERMIT_DIRECTIO 0x04000000 -#define IMA_NEW_FILE 0x08000000 -#define EVM_IMMUTABLE_DIGSIG 0x10000000 +#define IMA_DIGSIG_REQUIRED 0x01000000 +#define IMA_PERMIT_DIRECTIO 0x02000000 +#define IMA_NEW_FILE 0x04000000 +#define EVM_IMMUTABLE_DIGSIG 0x08000000 #define IMA_DO_MASK (IMA_MEASURE | IMA_APPRAISE | IMA_AUDIT | \ IMA_APPRAISE_SUBMASK) @@ -54,6 +53,13 @@ #define IMA_APPRAISED_SUBMASK (IMA_FILE_APPRAISED | IMA_MMAP_APPRAISED | \ IMA_BPRM_APPRAISED | IMA_READ_APPRAISED) +/* iint cache atomic_flags */ +#define IMA_CHANGE_XATTR 0 +#define IMA_UPDATE_XATTR 1 +#define IMA_CHANGE_ATTR 2 +#define IMA_DIGSIG 3 +#define IMA_MUST_MEASURE 4 + enum evm_ima_xattr_type { IMA_XATTR_DIGEST = 0x01, EVM_XATTR_HMAC, @@ -102,10 +108,12 @@ struct signature_v2_hdr { /* integrity data associated with an inode */ struct integrity_iint_cache { struct rb_node rb_node; /* rooted in integrity_iint_tree */ + struct mutex mutex; /* protects: version, flags, digest */ struct inode *inode; /* back pointer to inode in question */ u64 version; /* track inode changes */ unsigned long flags; unsigned long measured_pcrs; + unsigned long atomic_flags; enum integrity_status ima_file_status:4; enum integrity_status ima_mmap_status:4; enum integrity_status ima_bprm_status:4; -- GitLab From d467320fdaf328fd6f98fc686b3a3fdd226dbaef Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Tue, 23 Jan 2018 10:00:41 -0500 Subject: [PATCH 0160/1286] ima: re-initialize iint->atomic_flags commit e2598077dc6a26c9644393e5c21f22a90dbdccdb upstream. Intermittently security.ima is not being written for new files. This patch re-initializes the new slab iint->atomic_flags field before freeing it. Fixes: commit 0d73a55208e9 ("ima: re-introduce own integrity cache lock") Signed-off-by: Mimi Zohar Signed-off-by: James Morris Cc: Aditya Kali Signed-off-by: Greg Kroah-Hartman --- security/integrity/iint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/security/integrity/iint.c b/security/integrity/iint.c index 2db461c38795..f4a40fb84b1e 100644 --- a/security/integrity/iint.c +++ b/security/integrity/iint.c @@ -74,6 +74,7 @@ static void iint_free(struct integrity_iint_cache *iint) iint->ima_hash = NULL; iint->version = 0; iint->flags = 0UL; + iint->atomic_flags = 0UL; iint->ima_file_status = INTEGRITY_UNKNOWN; iint->ima_mmap_status = INTEGRITY_UNKNOWN; iint->ima_bprm_status = INTEGRITY_UNKNOWN; -- GitLab From 5ff1ad556aad473952c1caca6092aac4517ac1ae Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 1 Dec 2018 09:43:00 +0100 Subject: [PATCH 0161/1286] Linux 4.14.85 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index cb131e135c42..58a248264090 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 84 +SUBLEVEL = 85 EXTRAVERSION = NAME = Petit Gorille -- GitLab From e12b67d81b08a79994ee9b1484a7e0c4601bfdad Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:13 -0800 Subject: [PATCH 0162/1286] mm/huge_memory: rename freeze_page() to unmap_page() commit 906f9cdfc2a0800f13683f9e4ebdfd08c12ee81b upstream. The term "freeze" is used in several ways in the kernel, and in mm it has the particular meaning of forcing page refcount temporarily to 0. freeze_page() is just too confusing a name for a function that unmaps a page: rename it unmap_page(), and rename unfreeze_page() remap_page(). Went to change the mention of freeze_page() added later in mm/rmap.c, but found it to be incorrect: ordinary page reclaim reaches there too; but the substance of the comment still seems correct, so edit it down. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261514080.2275@eggly.anvils Fixes: e9b61f19858a5 ("thp: reintroduce split_huge_page()") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/huge_memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/mm/huge_memory.c b/mm/huge_memory.c index adacfe66cf3d..09d7e9c4de89 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -2280,7 +2280,7 @@ void vma_adjust_trans_huge(struct vm_area_struct *vma, } } -static void freeze_page(struct page *page) +static void unmap_page(struct page *page) { enum ttu_flags ttu_flags = TTU_IGNORE_MLOCK | TTU_IGNORE_ACCESS | TTU_RMAP_LOCKED | TTU_SPLIT_HUGE_PMD; @@ -2295,7 +2295,7 @@ static void freeze_page(struct page *page) VM_BUG_ON_PAGE(!unmap_success, page); } -static void unfreeze_page(struct page *page) +static void remap_page(struct page *page) { int i; if (PageTransHuge(page)) { @@ -2412,7 +2412,7 @@ static void __split_huge_page(struct page *page, struct list_head *list, spin_unlock_irqrestore(zone_lru_lock(page_zone(head)), flags); - unfreeze_page(head); + remap_page(head); for (i = 0; i < HPAGE_PMD_NR; i++) { struct page *subpage = head + i; @@ -2593,7 +2593,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) } /* - * Racy check if we can split the page, before freeze_page() will + * Racy check if we can split the page, before unmap_page() will * split PMDs */ if (!can_split_huge_page(head, &extra_pins)) { @@ -2602,7 +2602,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) } mlocked = PageMlocked(page); - freeze_page(head); + unmap_page(head); VM_BUG_ON_PAGE(compound_mapcount(head), head); /* Make sure the page is not on per-CPU pagevec as it takes pin */ @@ -2659,7 +2659,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) fail: if (mapping) spin_unlock(&mapping->tree_lock); spin_unlock_irqrestore(zone_lru_lock(page_zone(head)), flags); - unfreeze_page(head); + remap_page(head); ret = -EBUSY; } -- GitLab From 30241d721f90ea1cd783b79049024379d4a5b4f0 Mon Sep 17 00:00:00 2001 From: Konstantin Khlebnikov Date: Thu, 5 Apr 2018 16:23:28 -0700 Subject: [PATCH 0163/1286] mm/huge_memory.c: reorder operations in __split_huge_page_tail() commit 605ca5ede7643a01f4c4a15913f9714ac297f8a6 upstream. THP split makes non-atomic change of tail page flags. This is almost ok because tail pages are locked and isolated but this breaks recent changes in page locking: non-atomic operation could clear bit PG_waiters. As a result concurrent sequence get_page_unless_zero() -> lock_page() might block forever. Especially if this page was truncated later. Fix is trivial: clone flags before unfreezing page reference counter. This race exists since commit 62906027091f ("mm: add PageWaiters indicating tasks are waiting for a page bit") while unsave unfreeze itself was added in commit 8df651c7059e ("thp: cleanup split_huge_page()"). clear_compound_head() also must be called before unfreezing page reference because after successful get_page_unless_zero() might follow put_page() which needs correct compound_head(). And replace page_ref_inc()/page_ref_add() with page_ref_unfreeze() which is made especially for that and has semantic of smp_store_release(). Link: http://lkml.kernel.org/r/151844393341.210639.13162088407980624477.stgit@buzz Signed-off-by: Konstantin Khlebnikov Acked-by: Kirill A. Shutemov Cc: Michal Hocko Cc: Nicholas Piggin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/huge_memory.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/mm/huge_memory.c b/mm/huge_memory.c index 09d7e9c4de89..8969f5cf3174 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -2312,26 +2312,13 @@ static void __split_huge_page_tail(struct page *head, int tail, struct page *page_tail = head + tail; VM_BUG_ON_PAGE(atomic_read(&page_tail->_mapcount) != -1, page_tail); - VM_BUG_ON_PAGE(page_ref_count(page_tail) != 0, page_tail); /* - * tail_page->_refcount is zero and not changing from under us. But - * get_page_unless_zero() may be running from under us on the - * tail_page. If we used atomic_set() below instead of atomic_inc() or - * atomic_add(), we would then run atomic_set() concurrently with - * get_page_unless_zero(), and atomic_set() is implemented in C not - * using locked ops. spin_unlock on x86 sometime uses locked ops - * because of PPro errata 66, 92, so unless somebody can guarantee - * atomic_set() here would be safe on all archs (and not only on x86), - * it's safer to use atomic_inc()/atomic_add(). + * Clone page flags before unfreezing refcount. + * + * After successful get_page_unless_zero() might follow flags change, + * for exmaple lock_page() which set PG_waiters. */ - if (PageAnon(head) && !PageSwapCache(head)) { - page_ref_inc(page_tail); - } else { - /* Additional pin to radix tree */ - page_ref_add(page_tail, 2); - } - page_tail->flags &= ~PAGE_FLAGS_CHECK_AT_PREP; page_tail->flags |= (head->flags & ((1L << PG_referenced) | @@ -2344,14 +2331,21 @@ static void __split_huge_page_tail(struct page *head, int tail, (1L << PG_unevictable) | (1L << PG_dirty))); - /* - * After clearing PageTail the gup refcount can be released. - * Page flags also must be visible before we make the page non-compound. - */ + /* Page flags must be visible before we make the page non-compound. */ smp_wmb(); + /* + * Clear PageTail before unfreezing page refcount. + * + * After successful get_page_unless_zero() might follow put_page() + * which needs correct compound_head(). + */ clear_compound_head(page_tail); + /* Finally unfreeze refcount. Additional reference from page cache. */ + page_ref_unfreeze(page_tail, 1 + (!PageAnon(head) || + PageSwapCache(head))); + if (page_is_young(head)) set_page_young(page_tail); if (page_is_idle(head)) -- GitLab From 16d07443b27746fc819600fbe79742335a471d47 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:16 -0800 Subject: [PATCH 0164/1286] mm/huge_memory: splitting set mapping+index before unfreeze commit 173d9d9fd3ddae84c110fea8aedf1f26af6be9ec upstream. Huge tmpfs stress testing has occasionally hit shmem_undo_range()'s VM_BUG_ON_PAGE(page_to_pgoff(page) != index, page). Move the setting of mapping and index up before the page_ref_unfreeze() in __split_huge_page_tail() to fix this: so that a page cache lookup cannot get a reference while the tail's mapping and index are unstable. In fact, might as well move them up before the smp_wmb(): I don't see an actual need for that, but if I'm missing something, this way round is safer than the other, and no less efficient. You might argue that VM_BUG_ON_PAGE(page_to_pgoff(page) != index, page) is misplaced, and should be left until after the trylock_page(); but left as is has not crashed since, and gives more stringent assurance. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261516380.2275@eggly.anvils Fixes: e9b61f19858a5 ("thp: reintroduce split_huge_page()") Requires: 605ca5ede764 ("mm/huge_memory.c: reorder operations in __split_huge_page_tail()") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Konstantin Khlebnikov Cc: Jerome Glisse Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/huge_memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/mm/huge_memory.c b/mm/huge_memory.c index 8969f5cf3174..69ffeb439b0f 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -2331,6 +2331,12 @@ static void __split_huge_page_tail(struct page *head, int tail, (1L << PG_unevictable) | (1L << PG_dirty))); + /* ->mapping in first tail page is compound_mapcount */ + VM_BUG_ON_PAGE(tail > 2 && page_tail->mapping != TAIL_MAPPING, + page_tail); + page_tail->mapping = head->mapping; + page_tail->index = head->index + tail; + /* Page flags must be visible before we make the page non-compound. */ smp_wmb(); @@ -2351,12 +2357,6 @@ static void __split_huge_page_tail(struct page *head, int tail, if (page_is_idle(head)) set_page_idle(page_tail); - /* ->mapping in first tail page is compound_mapcount */ - VM_BUG_ON_PAGE(tail > 2 && page_tail->mapping != TAIL_MAPPING, - page_tail); - page_tail->mapping = head->mapping; - - page_tail->index = head->index + tail; page_cpupid_xchg_last(page_tail, page_cpupid_last(head)); lru_add_page_tail(head, page_tail, lruvec, list); } -- GitLab From 6f75a09833839caef7450275cc227dcef1679493 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:21 -0800 Subject: [PATCH 0165/1286] mm/huge_memory: fix lockdep complaint on 32-bit i_size_read() commit 006d3ff27e884f80bd7d306b041afc415f63598f upstream. Huge tmpfs testing, on 32-bit kernel with lockdep enabled, showed that __split_huge_page() was using i_size_read() while holding the irq-safe lru_lock and page tree lock, but the 32-bit i_size_read() uses an irq-unsafe seqlock which should not be nested inside them. Instead, read the i_size earlier in split_huge_page_to_list(), and pass the end offset down to __split_huge_page(): all while holding head page lock, which is enough to prevent truncation of that extent before the page tree lock has been taken. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261520070.2275@eggly.anvils Fixes: baa355fd33142 ("thp: file pages support for split_huge_page()") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/huge_memory.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/mm/huge_memory.c b/mm/huge_memory.c index 69ffeb439b0f..930f2aa3bb4d 100644 --- a/mm/huge_memory.c +++ b/mm/huge_memory.c @@ -2362,12 +2362,11 @@ static void __split_huge_page_tail(struct page *head, int tail, } static void __split_huge_page(struct page *page, struct list_head *list, - unsigned long flags) + pgoff_t end, unsigned long flags) { struct page *head = compound_head(page); struct zone *zone = page_zone(head); struct lruvec *lruvec; - pgoff_t end = -1; int i; lruvec = mem_cgroup_page_lruvec(head, zone->zone_pgdat); @@ -2375,9 +2374,6 @@ static void __split_huge_page(struct page *page, struct list_head *list, /* complete memcg works before add pages to LRU */ mem_cgroup_split_huge_fixup(head); - if (!PageAnon(page)) - end = DIV_ROUND_UP(i_size_read(head->mapping->host), PAGE_SIZE); - for (i = HPAGE_PMD_NR - 1; i >= 1; i--) { __split_huge_page_tail(head, i, lruvec, list); /* Some pages can be beyond i_size: drop them from page cache */ @@ -2549,6 +2545,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) int count, mapcount, extra_pins, ret; bool mlocked; unsigned long flags; + pgoff_t end; VM_BUG_ON_PAGE(is_huge_zero_page(page), page); VM_BUG_ON_PAGE(!PageLocked(page), page); @@ -2571,6 +2568,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) ret = -EBUSY; goto out; } + end = -1; mapping = NULL; anon_vma_lock_write(anon_vma); } else { @@ -2584,6 +2582,15 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) anon_vma = NULL; i_mmap_lock_read(mapping); + + /* + *__split_huge_page() may need to trim off pages beyond EOF: + * but on 32-bit, i_size_read() takes an irq-unsafe seqlock, + * which cannot be nested inside the page tree lock. So note + * end now: i_size itself may be changed at any moment, but + * head page lock is good enough to serialize the trimming. + */ + end = DIV_ROUND_UP(i_size_read(mapping->host), PAGE_SIZE); } /* @@ -2633,7 +2640,7 @@ int split_huge_page_to_list(struct page *page, struct list_head *list) if (mapping) __dec_node_page_state(page, NR_SHMEM_THPS); spin_unlock(&pgdata->split_queue_lock); - __split_huge_page(page, list, flags); + __split_huge_page(page, list, end, flags); if (PageSwapCache(head)) { swp_entry_t entry = { .val = page_private(head) }; -- GitLab From 81d2848c99cc4951eb3f7c3ce4313e830b07cc2b Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:25 -0800 Subject: [PATCH 0166/1286] mm/khugepaged: collapse_shmem() stop if punched or truncated commit 701270fa193aadf00bdcf607738f64997275d4c7 upstream. Huge tmpfs testing showed that although collapse_shmem() recognizes a concurrently truncated or hole-punched page correctly, its handling of holes was liable to refill an emptied extent. Add check to stop that. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261522040.2275@eggly.anvils Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Reviewed-by: Matthew Wilcox Cc: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index 0a5bb3e8a8a3..d4a06afbeda4 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1352,6 +1352,16 @@ static void collapse_shmem(struct mm_struct *mm, radix_tree_for_each_slot(slot, &mapping->page_tree, &iter, start) { int n = min(iter.index, end) - index; + /* + * Stop if extent has been hole-punched, and is now completely + * empty (the more obvious i_size_read() check would take an + * irq-unsafe seqlock on 32-bit). + */ + if (n >= HPAGE_PMD_NR) { + result = SCAN_TRUNCATED; + goto tree_locked; + } + /* * Handle holes in the radix tree: charge it from shmem and * insert relevant subpage of new_page into the radix-tree. @@ -1463,6 +1473,11 @@ static void collapse_shmem(struct mm_struct *mm, if (result == SCAN_SUCCEED && index < end) { int n = end - index; + /* Stop if extent has been truncated, and is now empty */ + if (n >= HPAGE_PMD_NR) { + result = SCAN_TRUNCATED; + goto tree_locked; + } if (!shmem_charge(mapping->host, n)) { result = SCAN_FAIL; goto tree_locked; -- GitLab From 98f1ae169c2e7264b198c3df08612f1bcd0fcfac Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:29 -0800 Subject: [PATCH 0167/1286] mm/khugepaged: fix crashes due to misaccounted holes commit aaa52e340073b7f4593b3c4ddafcafa70cf838b5 upstream. Huge tmpfs testing on a shortish file mapped into a pmd-rounded extent hit shmem_evict_inode()'s WARN_ON(inode->i_blocks) followed by clear_inode()'s BUG_ON(inode->i_data.nrpages) when the file was later closed and unlinked. khugepaged's collapse_shmem() was forgetting to update mapping->nrpages on the rollback path, after it had added but then needs to undo some holes. There is indeed an irritating asymmetry between shmem_charge(), whose callers want it to increment nrpages after successfully accounting blocks, and shmem_uncharge(), when __delete_from_page_cache() already decremented nrpages itself: oh well, just add a comment on that to them both. And shmem_recalc_inode() is supposed to be called when the accounting is expected to be in balance (so it can deduce from imbalance that reclaim discarded some pages): so change shmem_charge() to update nrpages earlier (though it's rare for the difference to matter at all). Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261523450.2275@eggly.anvils Fixes: 800d8c63b2e98 ("shmem: add huge pages support") Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 4 +++- mm/shmem.c | 6 +++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index d4a06afbeda4..be7b0863e33c 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1539,8 +1539,10 @@ static void collapse_shmem(struct mm_struct *mm, *hpage = NULL; } else { /* Something went wrong: rollback changes to the radix-tree */ - shmem_uncharge(mapping->host, nr_none); spin_lock_irq(&mapping->tree_lock); + mapping->nrpages -= nr_none; + shmem_uncharge(mapping->host, nr_none); + radix_tree_for_each_slot(slot, &mapping->page_tree, &iter, start) { if (iter.index >= end) diff --git a/mm/shmem.c b/mm/shmem.c index fa08f56fd5e5..177fef62cbbd 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -296,12 +296,14 @@ bool shmem_charge(struct inode *inode, long pages) if (!shmem_inode_acct_block(inode, pages)) return false; + /* nrpages adjustment first, then shmem_recalc_inode() when balanced */ + inode->i_mapping->nrpages += pages; + spin_lock_irqsave(&info->lock, flags); info->alloced += pages; inode->i_blocks += pages * BLOCKS_PER_PAGE; shmem_recalc_inode(inode); spin_unlock_irqrestore(&info->lock, flags); - inode->i_mapping->nrpages += pages; return true; } @@ -311,6 +313,8 @@ void shmem_uncharge(struct inode *inode, long pages) struct shmem_inode_info *info = SHMEM_I(inode); unsigned long flags; + /* nrpages adjustment done by __delete_from_page_cache() or caller */ + spin_lock_irqsave(&info->lock, flags); info->alloced -= pages; inode->i_blocks -= pages * BLOCKS_PER_PAGE; -- GitLab From 5021918a515cd86fb8715ec0f24ae66f15f5aba5 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:35 -0800 Subject: [PATCH 0168/1286] mm/khugepaged: collapse_shmem() remember to clear holes commit 2af8ff291848cc4b1cce24b6c943394eb2c761e8 upstream. Huge tmpfs testing reminds us that there is no __GFP_ZERO in the gfp flags khugepaged uses to allocate a huge page - in all common cases it would just be a waste of effort - so collapse_shmem() must remember to clear out any holes that it instantiates. The obvious place to do so, where they are put into the page cache tree, is not a good choice: because interrupts are disabled there. Leave it until further down, once success is assured, where the other pages are copied (before setting PageUptodate). Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261525080.2275@eggly.anvils Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index be7b0863e33c..f535dbe3f9f5 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1502,7 +1502,12 @@ static void collapse_shmem(struct mm_struct *mm, * Replacing old pages with new one has succeed, now we need to * copy the content and free old pages. */ + index = start; list_for_each_entry_safe(page, tmp, &pagelist, lru) { + while (index < page->index) { + clear_highpage(new_page + (index % HPAGE_PMD_NR)); + index++; + } copy_highpage(new_page + (page->index % HPAGE_PMD_NR), page); list_del(&page->lru); @@ -1512,6 +1517,11 @@ static void collapse_shmem(struct mm_struct *mm, ClearPageActive(page); ClearPageUnevictable(page); put_page(page); + index++; + } + while (index < end) { + clear_highpage(new_page + (index % HPAGE_PMD_NR)); + index++; } local_irq_save(flags); -- GitLab From b447a6adf423cd80862a5944e4e9d9c91afff05a Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:39 -0800 Subject: [PATCH 0169/1286] mm/khugepaged: minor reorderings in collapse_shmem() commit 042a30824871fa3149b0127009074b75cc25863c upstream. Several cleanups in collapse_shmem(): most of which probably do not really matter, beyond doing things in a more familiar and reassuring order. Simplify the failure gotos in the main loop, and on success update stats while interrupts still disabled from the last iteration. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261526400.2275@eggly.anvils Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 73 ++++++++++++++++++++----------------------------- 1 file changed, 30 insertions(+), 43 deletions(-) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index f535dbe3f9f5..0eac4344477a 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1333,13 +1333,12 @@ static void collapse_shmem(struct mm_struct *mm, goto out; } + __SetPageLocked(new_page); + __SetPageSwapBacked(new_page); new_page->index = start; new_page->mapping = mapping; - __SetPageSwapBacked(new_page); - __SetPageLocked(new_page); BUG_ON(!page_ref_freeze(new_page, 1)); - /* * At this point the new_page is 'frozen' (page_count() is zero), locked * and not up-to-date. It's safe to insert it into radix tree, because @@ -1368,13 +1367,13 @@ static void collapse_shmem(struct mm_struct *mm, */ if (n && !shmem_charge(mapping->host, n)) { result = SCAN_FAIL; - break; + goto tree_locked; } - nr_none += n; for (; index < min(iter.index, end); index++) { radix_tree_insert(&mapping->page_tree, index, new_page + (index % HPAGE_PMD_NR)); } + nr_none += n; /* We are done. */ if (index >= end) @@ -1390,12 +1389,12 @@ static void collapse_shmem(struct mm_struct *mm, result = SCAN_FAIL; goto tree_unlocked; } - spin_lock_irq(&mapping->tree_lock); } else if (trylock_page(page)) { get_page(page); + spin_unlock_irq(&mapping->tree_lock); } else { result = SCAN_PAGE_LOCK; - break; + goto tree_locked; } /* @@ -1410,11 +1409,10 @@ static void collapse_shmem(struct mm_struct *mm, result = SCAN_TRUNCATED; goto out_unlock; } - spin_unlock_irq(&mapping->tree_lock); if (isolate_lru_page(page)) { result = SCAN_DEL_PAGE_LRU; - goto out_isolate_failed; + goto out_unlock; } if (page_mapped(page)) @@ -1436,7 +1434,9 @@ static void collapse_shmem(struct mm_struct *mm, */ if (!page_ref_freeze(page, 3)) { result = SCAN_PAGE_COUNT; - goto out_lru; + spin_unlock_irq(&mapping->tree_lock); + putback_lru_page(page); + goto out_unlock; } /* @@ -1452,17 +1452,10 @@ static void collapse_shmem(struct mm_struct *mm, slot = radix_tree_iter_resume(slot, &iter); index++; continue; -out_lru: - spin_unlock_irq(&mapping->tree_lock); - putback_lru_page(page); -out_isolate_failed: - unlock_page(page); - put_page(page); - goto tree_unlocked; out_unlock: unlock_page(page); put_page(page); - break; + goto tree_unlocked; } /* @@ -1470,7 +1463,7 @@ static void collapse_shmem(struct mm_struct *mm, * This code only triggers if there's nothing in radix tree * beyond 'end'. */ - if (result == SCAN_SUCCEED && index < end) { + if (index < end) { int n = end - index; /* Stop if extent has been truncated, and is now empty */ @@ -1482,7 +1475,6 @@ static void collapse_shmem(struct mm_struct *mm, result = SCAN_FAIL; goto tree_locked; } - for (; index < end; index++) { radix_tree_insert(&mapping->page_tree, index, new_page + (index % HPAGE_PMD_NR)); @@ -1490,14 +1482,19 @@ static void collapse_shmem(struct mm_struct *mm, nr_none += n; } + __inc_node_page_state(new_page, NR_SHMEM_THPS); + if (nr_none) { + struct zone *zone = page_zone(new_page); + + __mod_node_page_state(zone->zone_pgdat, NR_FILE_PAGES, nr_none); + __mod_node_page_state(zone->zone_pgdat, NR_SHMEM, nr_none); + } + tree_locked: spin_unlock_irq(&mapping->tree_lock); tree_unlocked: if (result == SCAN_SUCCEED) { - unsigned long flags; - struct zone *zone = page_zone(new_page); - /* * Replacing old pages with new one has succeed, now we need to * copy the content and free old pages. @@ -1511,11 +1508,11 @@ static void collapse_shmem(struct mm_struct *mm, copy_highpage(new_page + (page->index % HPAGE_PMD_NR), page); list_del(&page->lru); - unlock_page(page); - page_ref_unfreeze(page, 1); page->mapping = NULL; + page_ref_unfreeze(page, 1); ClearPageActive(page); ClearPageUnevictable(page); + unlock_page(page); put_page(page); index++; } @@ -1524,28 +1521,17 @@ static void collapse_shmem(struct mm_struct *mm, index++; } - local_irq_save(flags); - __inc_node_page_state(new_page, NR_SHMEM_THPS); - if (nr_none) { - __mod_node_page_state(zone->zone_pgdat, NR_FILE_PAGES, nr_none); - __mod_node_page_state(zone->zone_pgdat, NR_SHMEM, nr_none); - } - local_irq_restore(flags); - - /* - * Remove pte page tables, so we can re-faulti - * the page as huge. - */ - retract_page_tables(mapping, start); - /* Everything is ready, let's unfreeze the new_page */ - set_page_dirty(new_page); SetPageUptodate(new_page); page_ref_unfreeze(new_page, HPAGE_PMD_NR); + set_page_dirty(new_page); mem_cgroup_commit_charge(new_page, memcg, false, true); lru_cache_add_anon(new_page); - unlock_page(new_page); + /* + * Remove pte page tables, so we can re-fault the page as huge. + */ + retract_page_tables(mapping, start); *hpage = NULL; } else { /* Something went wrong: rollback changes to the radix-tree */ @@ -1578,8 +1564,8 @@ static void collapse_shmem(struct mm_struct *mm, slot, page); slot = radix_tree_iter_resume(slot, &iter); spin_unlock_irq(&mapping->tree_lock); - putback_lru_page(page); unlock_page(page); + putback_lru_page(page); spin_lock_irq(&mapping->tree_lock); } VM_BUG_ON(nr_none); @@ -1588,9 +1574,10 @@ static void collapse_shmem(struct mm_struct *mm, /* Unfreeze new_page, caller would take care about freeing it */ page_ref_unfreeze(new_page, 1); mem_cgroup_cancel_charge(new_page, memcg, true); - unlock_page(new_page); new_page->mapping = NULL; } + + unlock_page(new_page); out: VM_BUG_ON(!list_empty(&pagelist)); /* TODO: tracepoints */ -- GitLab From 84c55f8d40102855f3b86ffdfad6b5e4da517858 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:43 -0800 Subject: [PATCH 0170/1286] mm/khugepaged: collapse_shmem() without freezing new_page commit 87c460a0bded56195b5eb497d44709777ef7b415 upstream. khugepaged's collapse_shmem() does almost all of its work, to assemble the huge new_page from 512 scattered old pages, with the new_page's refcount frozen to 0 (and refcounts of all old pages so far also frozen to 0). Including shmem_getpage() to read in any which were out on swap, memory reclaim if necessary to allocate their intermediate pages, and copying over all the data from old to new. Imagine the frozen refcount as a spinlock held, but without any lock debugging to highlight the abuse: it's not good, and under serious load heads into lockups - speculative getters of the page are not expecting to spin while khugepaged is rescheduled. One can get a little further under load by hacking around elsewhere; but fortunately, freezing the new_page turns out to have been entirely unnecessary, with no hacks needed elsewhere. The huge new_page lock is already held throughout, and guards all its subpages as they are brought one by one into the page cache tree; and anything reading the data in that page, without the lock, before it has been marked PageUptodate, would already be in the wrong. So simply eliminate the freezing of the new_page. Each of the old pages remains frozen with refcount 0 after it has been replaced by a new_page subpage in the page cache tree, until they are all unfrozen on success or failure: just as before. They could be unfrozen sooner, but cause no problem once no longer visible to find_get_entry(), filemap_map_pages() and other speculative lookups. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261527570.2275@eggly.anvils Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Acked-by: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index 0eac4344477a..45bf0e5775f7 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1288,7 +1288,7 @@ static void retract_page_tables(struct address_space *mapping, pgoff_t pgoff) * collapse_shmem - collapse small tmpfs/shmem pages into huge one. * * Basic scheme is simple, details are more complex: - * - allocate and freeze a new huge page; + * - allocate and lock a new huge page; * - scan over radix tree replacing old pages the new one * + swap in pages if necessary; * + fill in gaps; @@ -1296,11 +1296,11 @@ static void retract_page_tables(struct address_space *mapping, pgoff_t pgoff) * - if replacing succeed: * + copy data over; * + free old pages; - * + unfreeze huge page; + * + unlock huge page; * - if replacing failed; * + put all pages back and unfreeze them; * + restore gaps in the radix-tree; - * + free huge page; + * + unlock and free huge page; */ static void collapse_shmem(struct mm_struct *mm, struct address_space *mapping, pgoff_t start, @@ -1337,13 +1337,11 @@ static void collapse_shmem(struct mm_struct *mm, __SetPageSwapBacked(new_page); new_page->index = start; new_page->mapping = mapping; - BUG_ON(!page_ref_freeze(new_page, 1)); /* - * At this point the new_page is 'frozen' (page_count() is zero), locked - * and not up-to-date. It's safe to insert it into radix tree, because - * nobody would be able to map it or use it in other way until we - * unfreeze it. + * At this point the new_page is locked and not up-to-date. + * It's safe to insert it into the page cache, because nobody would + * be able to map it or use it in another way until we unlock it. */ index = start; @@ -1521,9 +1519,8 @@ static void collapse_shmem(struct mm_struct *mm, index++; } - /* Everything is ready, let's unfreeze the new_page */ SetPageUptodate(new_page); - page_ref_unfreeze(new_page, HPAGE_PMD_NR); + page_ref_add(new_page, HPAGE_PMD_NR - 1); set_page_dirty(new_page); mem_cgroup_commit_charge(new_page, memcg, false, true); lru_cache_add_anon(new_page); @@ -1571,8 +1568,6 @@ static void collapse_shmem(struct mm_struct *mm, VM_BUG_ON(nr_none); spin_unlock_irq(&mapping->tree_lock); - /* Unfreeze new_page, caller would take care about freeing it */ - page_ref_unfreeze(new_page, 1); mem_cgroup_cancel_charge(new_page, memcg, true); new_page->mapping = NULL; } -- GitLab From 8f85b74fb1c0a7fa267f828a90b582e27fdf56e7 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Fri, 30 Nov 2018 14:10:47 -0800 Subject: [PATCH 0171/1286] mm/khugepaged: collapse_shmem() do not crash on Compound commit 06a5e1268a5fb9c2b346a3da6b97e85f2eba0f07 upstream. collapse_shmem()'s VM_BUG_ON_PAGE(PageTransCompound) was unsafe: before it holds page lock of the first page, racing truncation then extension might conceivably have inserted a hugepage there already. Fail with the SCAN_PAGE_COMPOUND result, instead of crashing (CONFIG_DEBUG_VM=y) or otherwise mishandling the unexpected hugepage - though later we might code up a more constructive way of handling it, with SCAN_SUCCESS. Link: http://lkml.kernel.org/r/alpine.LSU.2.11.1811261529310.2275@eggly.anvils Fixes: f3f0e1d2150b2 ("khugepaged: add support of collapse for tmpfs/shmem pages") Signed-off-by: Hugh Dickins Cc: Kirill A. Shutemov Cc: Jerome Glisse Cc: Konstantin Khlebnikov Cc: Matthew Wilcox Cc: [4.8+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/khugepaged.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index 45bf0e5775f7..d27a73737f1a 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1401,7 +1401,15 @@ static void collapse_shmem(struct mm_struct *mm, */ VM_BUG_ON_PAGE(!PageLocked(page), page); VM_BUG_ON_PAGE(!PageUptodate(page), page); - VM_BUG_ON_PAGE(PageTransCompound(page), page); + + /* + * If file was truncated then extended, or hole-punched, before + * we locked the first page, then a THP might be there already. + */ + if (PageTransCompound(page)) { + result = SCAN_PAGE_COMPOUND; + goto out_unlock; + } if (page_mapping(page) != mapping) { result = SCAN_TRUNCATED; -- GitLab From 30cdc0c3bac950bebd3ba59f5ff980cdd3710e0f Mon Sep 17 00:00:00 2001 From: Matthias Schwarzott Date: Mon, 30 Oct 2017 06:07:29 -0400 Subject: [PATCH 0172/1286] media: em28xx: Fix use-after-free when disconnecting [ Upstream commit 910b0797fa9e8af09c44a3fa36cb310ba7a7218d ] Fix bug by moving the i2c_unregister_device calls after deregistration of dvb frontend. The new style i2c drivers already destroys the frontend object at i2c_unregister_device time. When the dvb frontend is unregistered afterwards it leads to this oops: [ 6058.866459] BUG: unable to handle kernel NULL pointer dereference at 00000000000001f8 [ 6058.866578] IP: dvb_frontend_stop+0x30/0xd0 [dvb_core] [ 6058.866644] PGD 0 [ 6058.866646] P4D 0 [ 6058.866726] Oops: 0000 [#1] SMP [ 6058.866768] Modules linked in: rc_pinnacle_pctv_hd(O) em28xx_rc(O) si2157(O) si2168(O) em28xx_dvb(O) em28xx(O) si2165(O) a8293(O) tda10071(O) tea5767(O) tuner(O) cx23885(O) tda18271(O) videobuf2_dvb(O) videobuf2_dma_sg(O) m88ds3103(O) tveeprom(O) cx2341x(O) v4l2_common(O) dvb_core(O) rc_core(O) videobuf2_memops(O) videobuf2_v4l2(O) videobuf2_core(O) videodev(O) media(O) bluetooth ecdh_generic ums_realtek uas rtl8192cu rtl_usb rtl8192c_common rtlwifi usb_storage snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic i2c_mux snd_hda_intel snd_hda_codec snd_hwdep x86_pkg_temp_thermal snd_hda_core kvm_intel kvm irqbypass [last unloaded: videobuf2_memops] [ 6058.867497] CPU: 2 PID: 7349 Comm: kworker/2:0 Tainted: G W O 4.13.9-gentoo #1 [ 6058.867595] Hardware name: MEDION E2050 2391/H81H3-EM2, BIOS H81EM2W08.308 08/25/2014 [ 6058.867692] Workqueue: usb_hub_wq hub_event [ 6058.867746] task: ffff88011a15e040 task.stack: ffffc90003074000 [ 6058.867825] RIP: 0010:dvb_frontend_stop+0x30/0xd0 [dvb_core] [ 6058.867896] RSP: 0018:ffffc90003077b58 EFLAGS: 00010293 [ 6058.867964] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 000000010040001f [ 6058.868056] RDX: ffff88011a15e040 RSI: ffffea000464e400 RDI: ffff88001cbe3028 [ 6058.868150] RBP: ffffc90003077b68 R08: ffff880119390380 R09: 000000010040001f [ 6058.868241] R10: ffffc90003077b18 R11: 000000000001e200 R12: ffff88001cbe3028 [ 6058.868330] R13: ffff88001cbe68d0 R14: ffff8800cf734000 R15: ffff8800cf734098 [ 6058.868419] FS: 0000000000000000(0000) GS:ffff88011fb00000(0000) knlGS:0000000000000000 [ 6058.868511] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6058.868578] CR2: 00000000000001f8 CR3: 00000001113c5000 CR4: 00000000001406e0 [ 6058.868662] Call Trace: [ 6058.868705] dvb_unregister_frontend+0x2a/0x80 [dvb_core] [ 6058.868774] em28xx_dvb_fini+0x132/0x220 [em28xx_dvb] [ 6058.868840] em28xx_close_extension+0x34/0x90 [em28xx] [ 6058.868902] em28xx_usb_disconnect+0x4e/0x70 [em28xx] [ 6058.868968] usb_unbind_interface+0x6d/0x260 [ 6058.869025] device_release_driver_internal+0x150/0x210 [ 6058.869094] device_release_driver+0xd/0x10 [ 6058.869150] bus_remove_device+0xe4/0x160 [ 6058.869204] device_del+0x1ce/0x2f0 [ 6058.869253] usb_disable_device+0x99/0x270 [ 6058.869306] usb_disconnect+0x8d/0x260 [ 6058.869359] hub_event+0x93d/0x1520 [ 6058.869408] ? dequeue_task_fair+0xae5/0xd20 [ 6058.869467] process_one_work+0x1d9/0x3e0 [ 6058.869522] worker_thread+0x43/0x3e0 [ 6058.869576] kthread+0x104/0x140 [ 6058.869602] ? trace_event_raw_event_workqueue_work+0x80/0x80 [ 6058.869640] ? kthread_create_on_node+0x40/0x40 [ 6058.869673] ret_from_fork+0x22/0x30 [ 6058.869698] Code: 54 49 89 fc 53 48 8b 9f 18 03 00 00 0f 1f 44 00 00 41 83 bc 24 04 05 00 00 02 74 0c 41 c7 84 24 04 05 00 00 01 00 00 00 0f ae f0 <48> 8b bb f8 01 00 00 48 85 ff 74 5c e8 df 40 f0 e0 48 8b 93 f8 [ 6058.869850] RIP: dvb_frontend_stop+0x30/0xd0 [dvb_core] RSP: ffffc90003077b58 [ 6058.869894] CR2: 00000000000001f8 [ 6058.875880] ---[ end trace 717eecf7193b3fc6 ]--- Signed-off-by: Matthias Schwarzott Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/em28xx/em28xx-dvb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index 4a7db623fe29..29cdaaf1ed90 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -2105,6 +2105,8 @@ static int em28xx_dvb_fini(struct em28xx *dev) } } + em28xx_unregister_dvb(dvb); + /* remove I2C SEC */ client = dvb->i2c_client_sec; if (client) { @@ -2126,7 +2128,6 @@ static int em28xx_dvb_fini(struct em28xx *dev) i2c_unregister_device(client); } - em28xx_unregister_dvb(dvb); kfree(dvb); dev->dvb = NULL; kref_put(&dev->ref, em28xx_free_device); -- GitLab From ba9606d0121b644019d0699b5973926cc1a91c10 Mon Sep 17 00:00:00 2001 From: Richard Weinberger Date: Tue, 12 Jun 2018 09:33:16 +0200 Subject: [PATCH 0173/1286] ubi: Initialize Fastmap checkmapping correctly commit 25677478474a91fa1b46f19a4a591a9848bca6fb upstream We cannot do it last, otherwithse it will be skipped for dynamic volumes. Reported-by: Lachmann, Juergen Fixes: 34653fd8c46e ("ubi: fastmap: Check each mapping only once") Signed-off-by: Richard Weinberger Signed-off-by: Sudip Mukherjee Signed-off-by: Sasha Levin --- drivers/mtd/ubi/vtbl.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index 94d7a865b135..7504f430c011 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -578,6 +578,16 @@ static int init_volumes(struct ubi_device *ubi, vol->ubi = ubi; reserved_pebs += vol->reserved_pebs; + /* + * We use ubi->peb_count and not vol->reserved_pebs because + * we want to keep the code simple. Otherwise we'd have to + * resize/check the bitmap upon volume resize too. + * Allocating a few bytes more does not hurt. + */ + err = ubi_fastmap_init_checkmap(vol, ubi->peb_count); + if (err) + return err; + /* * In case of dynamic volume UBI knows nothing about how many * data is stored there. So assume the whole volume is used. @@ -620,16 +630,6 @@ static int init_volumes(struct ubi_device *ubi, (long long)(vol->used_ebs - 1) * vol->usable_leb_size; vol->used_bytes += av->last_data_size; vol->last_eb_bytes = av->last_data_size; - - /* - * We use ubi->peb_count and not vol->reserved_pebs because - * we want to keep the code simple. Otherwise we'd have to - * resize/check the bitmap upon volume resize too. - * Allocating a few bytes more does not hurt. - */ - err = ubi_fastmap_init_checkmap(vol, ubi->peb_count); - if (err) - return err; } /* And add the layout volume */ -- GitLab From 2fd0d0f9bb59ec5b628622e30f22158cb564c4ea Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Thu, 26 Jul 2018 15:17:46 +0200 Subject: [PATCH 0174/1286] libceph: store ceph_auth_handshake pointer in ceph_connection commit 262614c4294d33b1f19e0d18c0091d9c329b544a upstream. We already copy authorizer_reply_buf and authorizer_reply_buf_len into ceph_connection. Factoring out __prepare_write_connect() requires two more: authorizer_buf and authorizer_buf_len. Store the pointer to the handshake in con->auth rather than piling on. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- include/linux/ceph/messenger.h | 3 +- net/ceph/messenger.c | 54 ++++++++++++++++------------------ 2 files changed, 27 insertions(+), 30 deletions(-) diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h index ead9d85f1c11..9056077c023f 100644 --- a/include/linux/ceph/messenger.h +++ b/include/linux/ceph/messenger.h @@ -203,9 +203,8 @@ struct ceph_connection { attempt for this connection, client */ u32 peer_global_seq; /* peer's global seq for this connection */ + struct ceph_auth_handshake *auth; int auth_retry; /* true if we need a newer authorizer */ - void *auth_reply_buf; /* where to put the authorizer reply */ - int auth_reply_buf_len; struct mutex mutex; diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 5281da82371a..3a82e6d2864b 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -1411,24 +1411,26 @@ static void prepare_write_keepalive(struct ceph_connection *con) * Connection negotiation. */ -static struct ceph_auth_handshake *get_connect_authorizer(struct ceph_connection *con, - int *auth_proto) +static int get_connect_authorizer(struct ceph_connection *con) { struct ceph_auth_handshake *auth; + int auth_proto; if (!con->ops->get_authorizer) { + con->auth = NULL; con->out_connect.authorizer_protocol = CEPH_AUTH_UNKNOWN; con->out_connect.authorizer_len = 0; - return NULL; + return 0; } - auth = con->ops->get_authorizer(con, auth_proto, con->auth_retry); + auth = con->ops->get_authorizer(con, &auth_proto, con->auth_retry); if (IS_ERR(auth)) - return auth; + return PTR_ERR(auth); - con->auth_reply_buf = auth->authorizer_reply_buf; - con->auth_reply_buf_len = auth->authorizer_reply_buf_len; - return auth; + con->auth = auth; + con->out_connect.authorizer_protocol = cpu_to_le32(auth_proto); + con->out_connect.authorizer_len = cpu_to_le32(auth->authorizer_buf_len); + return 0; } /* @@ -1448,8 +1450,7 @@ static int prepare_write_connect(struct ceph_connection *con) { unsigned int global_seq = get_global_seq(con->msgr, 0); int proto; - int auth_proto; - struct ceph_auth_handshake *auth; + int ret; switch (con->peer_name.type) { case CEPH_ENTITY_TYPE_MON: @@ -1476,20 +1477,15 @@ static int prepare_write_connect(struct ceph_connection *con) con->out_connect.protocol_version = cpu_to_le32(proto); con->out_connect.flags = 0; - auth_proto = CEPH_AUTH_UNKNOWN; - auth = get_connect_authorizer(con, &auth_proto); - if (IS_ERR(auth)) - return PTR_ERR(auth); - - con->out_connect.authorizer_protocol = cpu_to_le32(auth_proto); - con->out_connect.authorizer_len = auth ? - cpu_to_le32(auth->authorizer_buf_len) : 0; + ret = get_connect_authorizer(con); + if (ret) + return ret; con_out_kvec_add(con, sizeof (con->out_connect), &con->out_connect); - if (auth && auth->authorizer_buf_len) - con_out_kvec_add(con, auth->authorizer_buf_len, - auth->authorizer_buf); + if (con->auth) + con_out_kvec_add(con, con->auth->authorizer_buf_len, + con->auth->authorizer_buf); con->out_more = 0; con_flag_set(con, CON_FLAG_WRITE_PENDING); @@ -1753,11 +1749,14 @@ static int read_partial_connect(struct ceph_connection *con) if (ret <= 0) goto out; - size = le32_to_cpu(con->in_reply.authorizer_len); - end += size; - ret = read_partial(con, end, size, con->auth_reply_buf); - if (ret <= 0) - goto out; + if (con->auth) { + size = le32_to_cpu(con->in_reply.authorizer_len); + end += size; + ret = read_partial(con, end, size, + con->auth->authorizer_reply_buf); + if (ret <= 0) + goto out; + } dout("read_partial_connect %p tag %d, con_seq = %u, g_seq = %u\n", con, (int)con->in_reply.tag, @@ -1765,7 +1764,6 @@ static int read_partial_connect(struct ceph_connection *con) le32_to_cpu(con->in_reply.global_seq)); out: return ret; - } /* @@ -2048,7 +2046,7 @@ static int process_connect(struct ceph_connection *con) dout("process_connect on %p tag %d\n", con, (int)con->in_tag); - if (con->auth_reply_buf) { + if (con->auth) { /* * Any connection that defines ->get_authorizer() * should also define ->verify_authorizer_reply(). -- GitLab From 66abd96062b627f0ee20a684ebba48cec80233d7 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Thu, 26 Jul 2018 17:43:47 +0200 Subject: [PATCH 0175/1286] libceph: factor out __prepare_write_connect() commit c0f56b483aa09c99bfe97409a43ad786f33b8a5a upstream. Will be used for sending ceph_msg_connect with an updated authorizer, after the server challenges the initial authorizer. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/ceph/messenger.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 3a82e6d2864b..0b121327d32f 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -1446,6 +1446,17 @@ static void prepare_write_banner(struct ceph_connection *con) con_flag_set(con, CON_FLAG_WRITE_PENDING); } +static void __prepare_write_connect(struct ceph_connection *con) +{ + con_out_kvec_add(con, sizeof(con->out_connect), &con->out_connect); + if (con->auth) + con_out_kvec_add(con, con->auth->authorizer_buf_len, + con->auth->authorizer_buf); + + con->out_more = 0; + con_flag_set(con, CON_FLAG_WRITE_PENDING); +} + static int prepare_write_connect(struct ceph_connection *con) { unsigned int global_seq = get_global_seq(con->msgr, 0); @@ -1481,15 +1492,7 @@ static int prepare_write_connect(struct ceph_connection *con) if (ret) return ret; - con_out_kvec_add(con, sizeof (con->out_connect), - &con->out_connect); - if (con->auth) - con_out_kvec_add(con, con->auth->authorizer_buf_len, - con->auth->authorizer_buf); - - con->out_more = 0; - con_flag_set(con, CON_FLAG_WRITE_PENDING); - + __prepare_write_connect(con); return 0; } -- GitLab From 0858417b5c2e7bcc0b9e52c4b76e2af3d69e138b Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Thu, 26 Jul 2018 18:05:43 +0200 Subject: [PATCH 0176/1286] libceph: factor out __ceph_x_decrypt() commit c571fe24d243bfe7017f0e67fe800b3cc2a1d1f7 upstream. Will be used for decrypting the server challenge which is only preceded by ceph_x_encrypt_header. Drop struct_v check to allow for extending ceph_x_encrypt_header in the future. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/ceph/auth_x.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index 2f4a1baf5f52..9cac05239346 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -70,25 +70,40 @@ static int ceph_x_encrypt(struct ceph_crypto_key *secret, void *buf, return sizeof(u32) + ciphertext_len; } +static int __ceph_x_decrypt(struct ceph_crypto_key *secret, void *p, + int ciphertext_len) +{ + struct ceph_x_encrypt_header *hdr = p; + int plaintext_len; + int ret; + + ret = ceph_crypt(secret, false, p, ciphertext_len, ciphertext_len, + &plaintext_len); + if (ret) + return ret; + + if (le64_to_cpu(hdr->magic) != CEPHX_ENC_MAGIC) { + pr_err("%s bad magic\n", __func__); + return -EINVAL; + } + + return plaintext_len - sizeof(*hdr); +} + static int ceph_x_decrypt(struct ceph_crypto_key *secret, void **p, void *end) { - struct ceph_x_encrypt_header *hdr = *p + sizeof(u32); - int ciphertext_len, plaintext_len; + int ciphertext_len; int ret; ceph_decode_32_safe(p, end, ciphertext_len, e_inval); ceph_decode_need(p, end, ciphertext_len, e_inval); - ret = ceph_crypt(secret, false, *p, end - *p, ciphertext_len, - &plaintext_len); - if (ret) + ret = __ceph_x_decrypt(secret, *p, ciphertext_len); + if (ret < 0) return ret; - if (hdr->struct_v != 1 || le64_to_cpu(hdr->magic) != CEPHX_ENC_MAGIC) - return -EPERM; - *p += ciphertext_len; - return plaintext_len - sizeof(struct ceph_x_encrypt_header); + return ret; e_inval: return -EINVAL; -- GitLab From a55056e1523990e1ef9d70531ffaf27fd1ddff55 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 27 Jul 2018 16:37:54 +0200 Subject: [PATCH 0177/1286] libceph: factor out encrypt_authorizer() commit 149cac4a50b0b4081b38b2f38de6ef71c27eaa85 upstream. Will be used for encrypting both the initial and updated authorizers. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/ceph/auth_x.c | 49 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index 9cac05239346..722791f45b2a 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -290,6 +290,38 @@ static int ceph_x_proc_ticket_reply(struct ceph_auth_client *ac, return -EINVAL; } +/* + * Encode and encrypt the second part (ceph_x_authorize_b) of the + * authorizer. The first part (ceph_x_authorize_a) should already be + * encoded. + */ +static int encrypt_authorizer(struct ceph_x_authorizer *au) +{ + struct ceph_x_authorize_a *msg_a; + struct ceph_x_authorize_b *msg_b; + void *p, *end; + int ret; + + msg_a = au->buf->vec.iov_base; + WARN_ON(msg_a->ticket_blob.secret_id != cpu_to_le64(au->secret_id)); + p = (void *)(msg_a + 1) + le32_to_cpu(msg_a->ticket_blob.blob_len); + end = au->buf->vec.iov_base + au->buf->vec.iov_len; + + msg_b = p + ceph_x_encrypt_offset(); + msg_b->struct_v = 1; + msg_b->nonce = cpu_to_le64(au->nonce); + + ret = ceph_x_encrypt(&au->session_key, p, end - p, sizeof(*msg_b)); + if (ret < 0) + return ret; + + p += ret; + WARN_ON(p > end); + au->buf->vec.iov_len = p - au->buf->vec.iov_base; + + return 0; +} + static void ceph_x_authorizer_cleanup(struct ceph_x_authorizer *au) { ceph_crypto_key_destroy(&au->session_key); @@ -306,7 +338,6 @@ static int ceph_x_build_authorizer(struct ceph_auth_client *ac, int maxlen; struct ceph_x_authorize_a *msg_a; struct ceph_x_authorize_b *msg_b; - void *p, *end; int ret; int ticket_blob_len = (th->ticket_blob ? th->ticket_blob->vec.iov_len : 0); @@ -350,21 +381,13 @@ static int ceph_x_build_authorizer(struct ceph_auth_client *ac, dout(" th %p secret_id %lld %lld\n", th, th->secret_id, le64_to_cpu(msg_a->ticket_blob.secret_id)); - p = msg_a + 1; - p += ticket_blob_len; - end = au->buf->vec.iov_base + au->buf->vec.iov_len; - - msg_b = p + ceph_x_encrypt_offset(); - msg_b->struct_v = 1; get_random_bytes(&au->nonce, sizeof(au->nonce)); - msg_b->nonce = cpu_to_le64(au->nonce); - ret = ceph_x_encrypt(&au->session_key, p, end - p, sizeof(*msg_b)); - if (ret < 0) + ret = encrypt_authorizer(au); + if (ret) { + pr_err("failed to encrypt authorizer: %d", ret); goto out_au; + } - p += ret; - WARN_ON(p > end); - au->buf->vec.iov_len = p - au->buf->vec.iov_base; dout(" built authorizer nonce %llx len %d\n", au->nonce, (int)au->buf->vec.iov_len); return 0; -- GitLab From 3fd73c8a71f299e30359a63add1f33e3fd834831 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 27 Jul 2018 19:18:34 +0200 Subject: [PATCH 0178/1286] libceph: add authorizer challenge commit 6daca13d2e72bedaaacfc08f873114c9307d5aea upstream. When a client authenticates with a service, an authorizer is sent with a nonce to the service (ceph_x_authorize_[ab]) and the service responds with a mutation of that nonce (ceph_x_authorize_reply). This lets the client verify the service is who it says it is but it doesn't protect against a replay: someone can trivially capture the exchange and reuse the same authorizer to authenticate themselves. Allow the service to reject an initial authorizer with a random challenge (ceph_x_authorize_challenge). The client then has to respond with an updated authorizer proving they are able to decrypt the service's challenge and that the new authorizer was produced for this specific connection instance. The accepting side requires this challenge and response unconditionally if the client side advertises they have CEPHX_V2 feature bit. This addresses CVE-2018-1128. Link: http://tracker.ceph.com/issues/24836 Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/ceph/mds_client.c | 11 ++++++ include/linux/ceph/auth.h | 8 ++++ include/linux/ceph/messenger.h | 3 ++ include/linux/ceph/msgr.h | 2 +- net/ceph/auth.c | 16 ++++++++ net/ceph/auth_x.c | 72 +++++++++++++++++++++++++++++++--- net/ceph/auth_x_protocol.h | 7 ++++ net/ceph/messenger.c | 17 +++++++- net/ceph/osd_client.c | 11 ++++++ 9 files changed, 140 insertions(+), 7 deletions(-) diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c index bf378ddca4db..a48984dd6426 100644 --- a/fs/ceph/mds_client.c +++ b/fs/ceph/mds_client.c @@ -4079,6 +4079,16 @@ static struct ceph_auth_handshake *get_authorizer(struct ceph_connection *con, return auth; } +static int add_authorizer_challenge(struct ceph_connection *con, + void *challenge_buf, int challenge_buf_len) +{ + struct ceph_mds_session *s = con->private; + struct ceph_mds_client *mdsc = s->s_mdsc; + struct ceph_auth_client *ac = mdsc->fsc->client->monc.auth; + + return ceph_auth_add_authorizer_challenge(ac, s->s_auth.authorizer, + challenge_buf, challenge_buf_len); +} static int verify_authorizer_reply(struct ceph_connection *con) { @@ -4142,6 +4152,7 @@ static const struct ceph_connection_operations mds_con_ops = { .put = con_put, .dispatch = dispatch, .get_authorizer = get_authorizer, + .add_authorizer_challenge = add_authorizer_challenge, .verify_authorizer_reply = verify_authorizer_reply, .invalidate_authorizer = invalidate_authorizer, .peer_reset = peer_reset, diff --git a/include/linux/ceph/auth.h b/include/linux/ceph/auth.h index e931da8424a4..6728c2ee0205 100644 --- a/include/linux/ceph/auth.h +++ b/include/linux/ceph/auth.h @@ -64,6 +64,10 @@ struct ceph_auth_client_ops { /* ensure that an existing authorizer is up to date */ int (*update_authorizer)(struct ceph_auth_client *ac, int peer_type, struct ceph_auth_handshake *auth); + int (*add_authorizer_challenge)(struct ceph_auth_client *ac, + struct ceph_authorizer *a, + void *challenge_buf, + int challenge_buf_len); int (*verify_authorizer_reply)(struct ceph_auth_client *ac, struct ceph_authorizer *a); void (*invalidate_authorizer)(struct ceph_auth_client *ac, @@ -118,6 +122,10 @@ void ceph_auth_destroy_authorizer(struct ceph_authorizer *a); extern int ceph_auth_update_authorizer(struct ceph_auth_client *ac, int peer_type, struct ceph_auth_handshake *a); +int ceph_auth_add_authorizer_challenge(struct ceph_auth_client *ac, + struct ceph_authorizer *a, + void *challenge_buf, + int challenge_buf_len); extern int ceph_auth_verify_authorizer_reply(struct ceph_auth_client *ac, struct ceph_authorizer *a); extern void ceph_auth_invalidate_authorizer(struct ceph_auth_client *ac, diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h index 9056077c023f..18fbe910ed55 100644 --- a/include/linux/ceph/messenger.h +++ b/include/linux/ceph/messenger.h @@ -31,6 +31,9 @@ struct ceph_connection_operations { struct ceph_auth_handshake *(*get_authorizer) ( struct ceph_connection *con, int *proto, int force_new); + int (*add_authorizer_challenge)(struct ceph_connection *con, + void *challenge_buf, + int challenge_buf_len); int (*verify_authorizer_reply) (struct ceph_connection *con); int (*invalidate_authorizer)(struct ceph_connection *con); diff --git a/include/linux/ceph/msgr.h b/include/linux/ceph/msgr.h index 73ae2a926548..9e50aede46c8 100644 --- a/include/linux/ceph/msgr.h +++ b/include/linux/ceph/msgr.h @@ -91,7 +91,7 @@ struct ceph_entity_inst { #define CEPH_MSGR_TAG_SEQ 13 /* 64-bit int follows with seen seq number */ #define CEPH_MSGR_TAG_KEEPALIVE2 14 /* keepalive2 byte + ceph_timespec */ #define CEPH_MSGR_TAG_KEEPALIVE2_ACK 15 /* keepalive2 reply */ - +#define CEPH_MSGR_TAG_CHALLENGE_AUTHORIZER 16 /* cephx v2 doing server challenge */ /* * connection negotiation diff --git a/net/ceph/auth.c b/net/ceph/auth.c index dbde2b3c3c15..fbeee068ea14 100644 --- a/net/ceph/auth.c +++ b/net/ceph/auth.c @@ -315,6 +315,22 @@ int ceph_auth_update_authorizer(struct ceph_auth_client *ac, } EXPORT_SYMBOL(ceph_auth_update_authorizer); +int ceph_auth_add_authorizer_challenge(struct ceph_auth_client *ac, + struct ceph_authorizer *a, + void *challenge_buf, + int challenge_buf_len) +{ + int ret = 0; + + mutex_lock(&ac->mutex); + if (ac->ops && ac->ops->add_authorizer_challenge) + ret = ac->ops->add_authorizer_challenge(ac, a, challenge_buf, + challenge_buf_len); + mutex_unlock(&ac->mutex); + return ret; +} +EXPORT_SYMBOL(ceph_auth_add_authorizer_challenge); + int ceph_auth_verify_authorizer_reply(struct ceph_auth_client *ac, struct ceph_authorizer *a) { diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index 722791f45b2a..ce28bb07d8fd 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -295,7 +295,8 @@ static int ceph_x_proc_ticket_reply(struct ceph_auth_client *ac, * authorizer. The first part (ceph_x_authorize_a) should already be * encoded. */ -static int encrypt_authorizer(struct ceph_x_authorizer *au) +static int encrypt_authorizer(struct ceph_x_authorizer *au, + u64 *server_challenge) { struct ceph_x_authorize_a *msg_a; struct ceph_x_authorize_b *msg_b; @@ -308,16 +309,28 @@ static int encrypt_authorizer(struct ceph_x_authorizer *au) end = au->buf->vec.iov_base + au->buf->vec.iov_len; msg_b = p + ceph_x_encrypt_offset(); - msg_b->struct_v = 1; + msg_b->struct_v = 2; msg_b->nonce = cpu_to_le64(au->nonce); + if (server_challenge) { + msg_b->have_challenge = 1; + msg_b->server_challenge_plus_one = + cpu_to_le64(*server_challenge + 1); + } else { + msg_b->have_challenge = 0; + msg_b->server_challenge_plus_one = 0; + } ret = ceph_x_encrypt(&au->session_key, p, end - p, sizeof(*msg_b)); if (ret < 0) return ret; p += ret; - WARN_ON(p > end); - au->buf->vec.iov_len = p - au->buf->vec.iov_base; + if (server_challenge) { + WARN_ON(p != end); + } else { + WARN_ON(p > end); + au->buf->vec.iov_len = p - au->buf->vec.iov_base; + } return 0; } @@ -382,7 +395,7 @@ static int ceph_x_build_authorizer(struct ceph_auth_client *ac, le64_to_cpu(msg_a->ticket_blob.secret_id)); get_random_bytes(&au->nonce, sizeof(au->nonce)); - ret = encrypt_authorizer(au); + ret = encrypt_authorizer(au, NULL); if (ret) { pr_err("failed to encrypt authorizer: %d", ret); goto out_au; @@ -664,6 +677,54 @@ static int ceph_x_update_authorizer( return 0; } +static int decrypt_authorize_challenge(struct ceph_x_authorizer *au, + void *challenge_buf, + int challenge_buf_len, + u64 *server_challenge) +{ + struct ceph_x_authorize_challenge *ch = + challenge_buf + sizeof(struct ceph_x_encrypt_header); + int ret; + + /* no leading len */ + ret = __ceph_x_decrypt(&au->session_key, challenge_buf, + challenge_buf_len); + if (ret < 0) + return ret; + if (ret < sizeof(*ch)) { + pr_err("bad size %d for ceph_x_authorize_challenge\n", ret); + return -EINVAL; + } + + *server_challenge = le64_to_cpu(ch->server_challenge); + return 0; +} + +static int ceph_x_add_authorizer_challenge(struct ceph_auth_client *ac, + struct ceph_authorizer *a, + void *challenge_buf, + int challenge_buf_len) +{ + struct ceph_x_authorizer *au = (void *)a; + u64 server_challenge; + int ret; + + ret = decrypt_authorize_challenge(au, challenge_buf, challenge_buf_len, + &server_challenge); + if (ret) { + pr_err("failed to decrypt authorize challenge: %d", ret); + return ret; + } + + ret = encrypt_authorizer(au, &server_challenge); + if (ret) { + pr_err("failed to encrypt authorizer w/ challenge: %d", ret); + return ret; + } + + return 0; +} + static int ceph_x_verify_authorizer_reply(struct ceph_auth_client *ac, struct ceph_authorizer *a) { @@ -816,6 +877,7 @@ static const struct ceph_auth_client_ops ceph_x_ops = { .handle_reply = ceph_x_handle_reply, .create_authorizer = ceph_x_create_authorizer, .update_authorizer = ceph_x_update_authorizer, + .add_authorizer_challenge = ceph_x_add_authorizer_challenge, .verify_authorizer_reply = ceph_x_verify_authorizer_reply, .invalidate_authorizer = ceph_x_invalidate_authorizer, .reset = ceph_x_reset, diff --git a/net/ceph/auth_x_protocol.h b/net/ceph/auth_x_protocol.h index 32c13d763b9a..24b0b74564d0 100644 --- a/net/ceph/auth_x_protocol.h +++ b/net/ceph/auth_x_protocol.h @@ -70,6 +70,13 @@ struct ceph_x_authorize_a { struct ceph_x_authorize_b { __u8 struct_v; __le64 nonce; + __u8 have_challenge; + __le64 server_challenge_plus_one; +} __attribute__ ((packed)); + +struct ceph_x_authorize_challenge { + __u8 struct_v; + __le64 server_challenge; } __attribute__ ((packed)); struct ceph_x_authorize_reply { diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 0b121327d32f..ad33baa2008d 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -2052,9 +2052,24 @@ static int process_connect(struct ceph_connection *con) if (con->auth) { /* * Any connection that defines ->get_authorizer() - * should also define ->verify_authorizer_reply(). + * should also define ->add_authorizer_challenge() and + * ->verify_authorizer_reply(). + * * See get_connect_authorizer(). */ + if (con->in_reply.tag == CEPH_MSGR_TAG_CHALLENGE_AUTHORIZER) { + ret = con->ops->add_authorizer_challenge( + con, con->auth->authorizer_reply_buf, + le32_to_cpu(con->in_reply.authorizer_len)); + if (ret < 0) + return ret; + + con_out_kvec_reset(con); + __prepare_write_connect(con); + prepare_read_connect(con); + return 0; + } + ret = con->ops->verify_authorizer_reply(con); if (ret < 0) { con->error_msg = "bad authorize reply"; diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 2814dba5902d..53ea2d48896c 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -5292,6 +5292,16 @@ static struct ceph_auth_handshake *get_authorizer(struct ceph_connection *con, return auth; } +static int add_authorizer_challenge(struct ceph_connection *con, + void *challenge_buf, int challenge_buf_len) +{ + struct ceph_osd *o = con->private; + struct ceph_osd_client *osdc = o->o_osdc; + struct ceph_auth_client *ac = osdc->client->monc.auth; + + return ceph_auth_add_authorizer_challenge(ac, o->o_auth.authorizer, + challenge_buf, challenge_buf_len); +} static int verify_authorizer_reply(struct ceph_connection *con) { @@ -5341,6 +5351,7 @@ static const struct ceph_connection_operations osd_con_ops = { .put = put_osd_con, .dispatch = dispatch, .get_authorizer = get_authorizer, + .add_authorizer_challenge = add_authorizer_challenge, .verify_authorizer_reply = verify_authorizer_reply, .invalidate_authorizer = invalidate_authorizer, .alloc_msg = alloc_msg, -- GitLab From b16d0c5d32468a0624505a7b6b211e20488295e9 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 27 Jul 2018 19:25:32 +0200 Subject: [PATCH 0179/1286] libceph: implement CEPHX_V2 calculation mode commit cc255c76c70f7a87d97939621eae04b600d9f4a1 upstream. Derive the signature from the entire buffer (both AES cipher blocks) instead of using just the first half of the first block, leaving out data_crc entirely. This addresses CVE-2018-1129. Link: http://tracker.ceph.com/issues/24837 Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- include/linux/ceph/ceph_features.h | 7 +-- net/ceph/auth_x.c | 73 +++++++++++++++++++++++------- 2 files changed, 60 insertions(+), 20 deletions(-) diff --git a/include/linux/ceph/ceph_features.h b/include/linux/ceph/ceph_features.h index 59042d5ac520..70f42eef813b 100644 --- a/include/linux/ceph/ceph_features.h +++ b/include/linux/ceph/ceph_features.h @@ -165,9 +165,9 @@ DEFINE_CEPH_FEATURE(58, 1, FS_FILE_LAYOUT_V2) // overlap DEFINE_CEPH_FEATURE(59, 1, FS_BTIME) DEFINE_CEPH_FEATURE(59, 1, FS_CHANGE_ATTR) // overlap DEFINE_CEPH_FEATURE(59, 1, MSG_ADDR2) // overlap -DEFINE_CEPH_FEATURE(60, 1, BLKIN_TRACING) // *do not share this bit* +DEFINE_CEPH_FEATURE(60, 1, OSD_RECOVERY_DELETES) // *do not share this bit* +DEFINE_CEPH_FEATURE(61, 1, CEPHX_V2) // *do not share this bit* -DEFINE_CEPH_FEATURE(61, 1, RESERVED2) // unused, but slow down! DEFINE_CEPH_FEATURE(62, 1, RESERVED) // do not use; used as a sentinal DEFINE_CEPH_FEATURE_DEPRECATED(63, 1, RESERVED_BROKEN, LUMINOUS) // client-facing @@ -209,7 +209,8 @@ DEFINE_CEPH_FEATURE_DEPRECATED(63, 1, RESERVED_BROKEN, LUMINOUS) // client-facin CEPH_FEATURE_SERVER_JEWEL | \ CEPH_FEATURE_MON_STATEFUL_SUB | \ CEPH_FEATURE_CRUSH_TUNABLES5 | \ - CEPH_FEATURE_NEW_OSDOPREPLY_ENCODING) + CEPH_FEATURE_NEW_OSDOPREPLY_ENCODING | \ + CEPH_FEATURE_CEPHX_V2) #define CEPH_FEATURES_REQUIRED_DEFAULT \ (CEPH_FEATURE_NOSRCADDR | \ diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index ce28bb07d8fd..10eb759bbcb4 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -803,26 +804,64 @@ static int calc_signature(struct ceph_x_authorizer *au, struct ceph_msg *msg, __le64 *psig) { void *enc_buf = au->enc_buf; - struct { - __le32 len; - __le32 header_crc; - __le32 front_crc; - __le32 middle_crc; - __le32 data_crc; - } __packed *sigblock = enc_buf + ceph_x_encrypt_offset(); int ret; - sigblock->len = cpu_to_le32(4*sizeof(u32)); - sigblock->header_crc = msg->hdr.crc; - sigblock->front_crc = msg->footer.front_crc; - sigblock->middle_crc = msg->footer.middle_crc; - sigblock->data_crc = msg->footer.data_crc; - ret = ceph_x_encrypt(&au->session_key, enc_buf, CEPHX_AU_ENC_BUF_LEN, - sizeof(*sigblock)); - if (ret < 0) - return ret; + if (!CEPH_HAVE_FEATURE(msg->con->peer_features, CEPHX_V2)) { + struct { + __le32 len; + __le32 header_crc; + __le32 front_crc; + __le32 middle_crc; + __le32 data_crc; + } __packed *sigblock = enc_buf + ceph_x_encrypt_offset(); + + sigblock->len = cpu_to_le32(4*sizeof(u32)); + sigblock->header_crc = msg->hdr.crc; + sigblock->front_crc = msg->footer.front_crc; + sigblock->middle_crc = msg->footer.middle_crc; + sigblock->data_crc = msg->footer.data_crc; + + ret = ceph_x_encrypt(&au->session_key, enc_buf, + CEPHX_AU_ENC_BUF_LEN, sizeof(*sigblock)); + if (ret < 0) + return ret; + + *psig = *(__le64 *)(enc_buf + sizeof(u32)); + } else { + struct { + __le32 header_crc; + __le32 front_crc; + __le32 front_len; + __le32 middle_crc; + __le32 middle_len; + __le32 data_crc; + __le32 data_len; + __le32 seq_lower_word; + } __packed *sigblock = enc_buf; + struct { + __le64 a, b, c, d; + } __packed *penc = enc_buf; + int ciphertext_len; + + sigblock->header_crc = msg->hdr.crc; + sigblock->front_crc = msg->footer.front_crc; + sigblock->front_len = msg->hdr.front_len; + sigblock->middle_crc = msg->footer.middle_crc; + sigblock->middle_len = msg->hdr.middle_len; + sigblock->data_crc = msg->footer.data_crc; + sigblock->data_len = msg->hdr.data_len; + sigblock->seq_lower_word = *(__le32 *)&msg->hdr.seq; + + /* no leading len, no ceph_x_encrypt_header */ + ret = ceph_crypt(&au->session_key, true, enc_buf, + CEPHX_AU_ENC_BUF_LEN, sizeof(*sigblock), + &ciphertext_len); + if (ret) + return ret; + + *psig = penc->a ^ penc->b ^ penc->c ^ penc->d; + } - *psig = *(__le64 *)(enc_buf + sizeof(u32)); return 0; } -- GitLab From 83b570c004da47b51d7417ac18d8491d9fc91420 Mon Sep 17 00:00:00 2001 From: Alexei Starovoitov Date: Tue, 15 May 2018 09:27:05 -0700 Subject: [PATCH 0180/1286] bpf: Prevent memory disambiguation attack commit af86ca4e3088fe5eacf2f7e58c01fa68ca067672 upstream. Detect code patterns where malicious 'speculative store bypass' can be used and sanitize such patterns. 39: (bf) r3 = r10 40: (07) r3 += -216 41: (79) r8 = *(u64 *)(r7 +0) // slow read 42: (7a) *(u64 *)(r10 -72) = 0 // verifier inserts this instruction 43: (7b) *(u64 *)(r8 +0) = r3 // this store becomes slow due to r8 44: (79) r1 = *(u64 *)(r6 +0) // cpu speculatively executes this load 45: (71) r2 = *(u8 *)(r1 +0) // speculatively arbitrary 'load byte' // is now sanitized Above code after x86 JIT becomes: e5: mov %rbp,%rdx e8: add $0xffffffffffffff28,%rdx ef: mov 0x0(%r13),%r14 f3: movq $0x0,-0x48(%rbp) fb: mov %rdx,0x0(%r14) ff: mov 0x0(%rbx),%rdi 103: movzbq 0x0(%rdi),%rsi Signed-off-by: Alexei Starovoitov Signed-off-by: Thomas Gleixner [bwh: Backported to 4.14: - Add bpf_verifier_env parameter to check_stack_write() - Look up stack slot_types with state->stack_slot_type[] rather than state->stack[].slot_type[] - Drop bpf_verifier_env argument to verbose() - Adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- include/linux/bpf_verifier.h | 1 + kernel/bpf/verifier.c | 62 +++++++++++++++++++++++++++++++++--- 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h index a3333004fd2b..8458cc5fbce5 100644 --- a/include/linux/bpf_verifier.h +++ b/include/linux/bpf_verifier.h @@ -113,6 +113,7 @@ struct bpf_insn_aux_data { struct bpf_map *map_ptr; /* pointer for call insn into lookup_elem */ }; int ctx_field_size; /* the ctx field size for load insn, maybe 0 */ + int sanitize_stack_off; /* stack slot to be cleared */ bool seen; /* this insn was processed by the verifier */ }; diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 013b0cd1958e..f6755fd5bae2 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -717,8 +717,9 @@ static bool is_spillable_regtype(enum bpf_reg_type type) /* check_stack_read/write functions track spill/fill of registers, * stack boundary and alignment are checked in check_mem_access() */ -static int check_stack_write(struct bpf_verifier_state *state, int off, - int size, int value_regno) +static int check_stack_write(struct bpf_verifier_env *env, + struct bpf_verifier_state *state, int off, + int size, int value_regno, int insn_idx) { int i, spi = (MAX_BPF_STACK + off) / BPF_REG_SIZE; /* caller checked that off % size == 0 and -MAX_BPF_STACK <= off < 0, @@ -738,8 +739,32 @@ static int check_stack_write(struct bpf_verifier_state *state, int off, state->spilled_regs[spi] = state->regs[value_regno]; state->spilled_regs[spi].live |= REG_LIVE_WRITTEN; - for (i = 0; i < BPF_REG_SIZE; i++) + for (i = 0; i < BPF_REG_SIZE; i++) { + if (state->stack_slot_type[MAX_BPF_STACK + off + i] == STACK_MISC && + !env->allow_ptr_leaks) { + int *poff = &env->insn_aux_data[insn_idx].sanitize_stack_off; + int soff = (-spi - 1) * BPF_REG_SIZE; + + /* detected reuse of integer stack slot with a pointer + * which means either llvm is reusing stack slot or + * an attacker is trying to exploit CVE-2018-3639 + * (speculative store bypass) + * Have to sanitize that slot with preemptive + * store of zero. + */ + if (*poff && *poff != soff) { + /* disallow programs where single insn stores + * into two different stack slots, since verifier + * cannot sanitize them + */ + verbose("insn %d cannot access two stack slots fp%d and fp%d", + insn_idx, *poff, soff); + return -EINVAL; + } + *poff = soff; + } state->stack_slot_type[MAX_BPF_STACK + off + i] = STACK_SPILL; + } } else { /* regular write of data into stack */ state->spilled_regs[spi] = (struct bpf_reg_state) {}; @@ -1216,7 +1241,8 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn verbose("attempt to corrupt spilled pointer on stack\n"); return -EACCES; } - err = check_stack_write(state, off, size, value_regno); + err = check_stack_write(env, state, off, size, + value_regno, insn_idx); } else { err = check_stack_read(state, off, size, value_regno); } @@ -4270,6 +4296,34 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env) else continue; + if (type == BPF_WRITE && + env->insn_aux_data[i + delta].sanitize_stack_off) { + struct bpf_insn patch[] = { + /* Sanitize suspicious stack slot with zero. + * There are no memory dependencies for this store, + * since it's only using frame pointer and immediate + * constant of zero + */ + BPF_ST_MEM(BPF_DW, BPF_REG_FP, + env->insn_aux_data[i + delta].sanitize_stack_off, + 0), + /* the original STX instruction will immediately + * overwrite the same stack slot with appropriate value + */ + *insn, + }; + + cnt = ARRAY_SIZE(patch); + new_prog = bpf_patch_insn_data(env, i + delta, patch, cnt); + if (!new_prog) + return -ENOMEM; + + delta += cnt - 1; + env->prog = new_prog; + insn = new_prog->insnsi + i + delta; + continue; + } + if (env->insn_aux_data[i + delta].ptr_type != PTR_TO_CTX) continue; -- GitLab From 25f03991a5210f31491e1e2fccec7cf0d080772e Mon Sep 17 00:00:00 2001 From: Ilya Lesokhin Date: Mon, 13 Nov 2017 10:22:45 +0200 Subject: [PATCH 0181/1286] tls: Add function to update the TLS socket configuration commit 6d88207fcfddc002afe3e2e4a455e5201089d5d9 upstream. The tx configuration is now stored in ctx->tx_conf. And sk->sk_prot is updated trough a function This will simplify things when we add rx and support for different possible tx and rx cross configurations. Signed-off-by: Ilya Lesokhin Signed-off-by: David S. Miller Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- include/net/tls.h | 2 ++ net/tls/tls_main.c | 46 ++++++++++++++++++++++++++++++++-------------- 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/include/net/tls.h b/include/net/tls.h index 86ed3dd80fe7..0c3ab2af74d3 100644 --- a/include/net/tls.h +++ b/include/net/tls.h @@ -89,6 +89,8 @@ struct tls_context { void *priv_ctx; + u8 tx_conf:2; + u16 prepend_size; u16 tag_size; u16 overhead_size; diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index 4f2971f528db..191a8adee3ea 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -46,8 +46,18 @@ MODULE_DESCRIPTION("Transport Layer Security Support"); MODULE_LICENSE("Dual BSD/GPL"); MODULE_ALIAS_TCP_ULP("tls"); -static struct proto tls_base_prot; -static struct proto tls_sw_prot; +enum { + TLS_BASE_TX, + TLS_SW_TX, + TLS_NUM_CONFIG, +}; + +static struct proto tls_prots[TLS_NUM_CONFIG]; + +static inline void update_sk_prot(struct sock *sk, struct tls_context *ctx) +{ + sk->sk_prot = &tls_prots[ctx->tx_conf]; +} int wait_on_pending_writer(struct sock *sk, long *timeo) { @@ -364,8 +374,8 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, { struct tls_crypto_info *crypto_info, tmp_crypto_info; struct tls_context *ctx = tls_get_ctx(sk); - struct proto *prot = NULL; int rc = 0; + int tx_conf; if (!optval || (optlen < sizeof(*crypto_info))) { rc = -EINVAL; @@ -422,11 +432,12 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, /* currently SW is default, we will have ethtool in future */ rc = tls_set_sw_offload(sk, ctx); - prot = &tls_sw_prot; + tx_conf = TLS_SW_TX; if (rc) goto err_crypto_info; - sk->sk_prot = prot; + ctx->tx_conf = tx_conf; + update_sk_prot(sk, ctx); goto out; err_crypto_info: @@ -488,7 +499,9 @@ static int tls_init(struct sock *sk) icsk->icsk_ulp_data = ctx; ctx->setsockopt = sk->sk_prot->setsockopt; ctx->getsockopt = sk->sk_prot->getsockopt; - sk->sk_prot = &tls_base_prot; + + ctx->tx_conf = TLS_BASE_TX; + update_sk_prot(sk, ctx); out: return rc; } @@ -499,16 +512,21 @@ static struct tcp_ulp_ops tcp_tls_ulp_ops __read_mostly = { .init = tls_init, }; +static void build_protos(struct proto *prot, struct proto *base) +{ + prot[TLS_BASE_TX] = *base; + prot[TLS_BASE_TX].setsockopt = tls_setsockopt; + prot[TLS_BASE_TX].getsockopt = tls_getsockopt; + + prot[TLS_SW_TX] = prot[TLS_BASE_TX]; + prot[TLS_SW_TX].close = tls_sk_proto_close; + prot[TLS_SW_TX].sendmsg = tls_sw_sendmsg; + prot[TLS_SW_TX].sendpage = tls_sw_sendpage; +} + static int __init tls_register(void) { - tls_base_prot = tcp_prot; - tls_base_prot.setsockopt = tls_setsockopt; - tls_base_prot.getsockopt = tls_getsockopt; - - tls_sw_prot = tls_base_prot; - tls_sw_prot.sendmsg = tls_sw_sendmsg; - tls_sw_prot.sendpage = tls_sw_sendpage; - tls_sw_prot.close = tls_sk_proto_close; + build_protos(tls_prots, &tcp_prot); tcp_register_ulp(&tcp_tls_ulp_ops); -- GitLab From 797b8bb47fb27ee49a3b59ad110e5264585415aa Mon Sep 17 00:00:00 2001 From: Ilya Lesokhin Date: Mon, 13 Nov 2017 10:22:46 +0200 Subject: [PATCH 0182/1286] tls: Fix TLS ulp context leak, when TLS_TX setsockopt is not used. commit ff45d820a2df163957ad8ab459b6eb6976144c18 upstream. Previously the TLS ulp context would leak if we attached a TLS ulp to a socket but did not use the TLS_TX setsockopt, or did use it but it failed. This patch solves the issue by overriding prot[TLS_BASE_TX].close and fixing tls_sk_proto_close to work properly when its called with ctx->tx_conf == TLS_BASE_TX. This patch also removes ctx->free_resources as we can use ctx->tx_conf to obtain the relevant information. Fixes: 3c4d7559159b ('tls: kernel TLS support') Signed-off-by: Ilya Lesokhin Signed-off-by: David S. Miller [bwh: Backported to 4.14: Keep using tls_ctx_free() as introduced by the earlier backport of "tls: zero the crypto information from tls_context before freeing"] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- include/net/tls.h | 2 +- net/tls/tls_main.c | 24 ++++++++++++++++-------- net/tls/tls_sw.c | 3 +-- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/include/net/tls.h b/include/net/tls.h index 0c3ab2af74d3..604fd982da19 100644 --- a/include/net/tls.h +++ b/include/net/tls.h @@ -106,7 +106,6 @@ struct tls_context { u16 pending_open_record_frags; int (*push_pending_record)(struct sock *sk, int flags); - void (*free_resources)(struct sock *sk); void (*sk_write_space)(struct sock *sk); void (*sk_proto_close)(struct sock *sk, long timeout); @@ -131,6 +130,7 @@ int tls_sw_sendmsg(struct sock *sk, struct msghdr *msg, size_t size); int tls_sw_sendpage(struct sock *sk, struct page *page, int offset, size_t size, int flags); void tls_sw_close(struct sock *sk, long timeout); +void tls_sw_free_tx_resources(struct sock *sk); void tls_sk_destruct(struct sock *sk, struct tls_context *ctx); void tls_icsk_clean_acked(struct sock *sk); diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index 191a8adee3ea..b5f9c578bcf0 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -249,6 +249,12 @@ static void tls_sk_proto_close(struct sock *sk, long timeout) void (*sk_proto_close)(struct sock *sk, long timeout); lock_sock(sk); + sk_proto_close = ctx->sk_proto_close; + + if (ctx->tx_conf == TLS_BASE_TX) { + tls_ctx_free(ctx); + goto skip_tx_cleanup; + } if (!tls_complete_pending_work(sk, ctx, 0, &timeo)) tls_handle_open_record(sk, 0); @@ -265,13 +271,16 @@ static void tls_sk_proto_close(struct sock *sk, long timeout) sg++; } } - ctx->free_resources(sk); + kfree(ctx->rec_seq); kfree(ctx->iv); - sk_proto_close = ctx->sk_proto_close; - tls_ctx_free(ctx); + if (ctx->tx_conf == TLS_SW_TX) { + tls_sw_free_tx_resources(sk); + tls_ctx_free(ctx); + } +skip_tx_cleanup: release_sock(sk); sk_proto_close(sk, timeout); } @@ -428,8 +437,6 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, ctx->sk_write_space = sk->sk_write_space; sk->sk_write_space = tls_write_space; - ctx->sk_proto_close = sk->sk_prot->close; - /* currently SW is default, we will have ethtool in future */ rc = tls_set_sw_offload(sk, ctx); tx_conf = TLS_SW_TX; @@ -499,6 +506,7 @@ static int tls_init(struct sock *sk) icsk->icsk_ulp_data = ctx; ctx->setsockopt = sk->sk_prot->setsockopt; ctx->getsockopt = sk->sk_prot->getsockopt; + ctx->sk_proto_close = sk->sk_prot->close; ctx->tx_conf = TLS_BASE_TX; update_sk_prot(sk, ctx); @@ -515,11 +523,11 @@ static struct tcp_ulp_ops tcp_tls_ulp_ops __read_mostly = { static void build_protos(struct proto *prot, struct proto *base) { prot[TLS_BASE_TX] = *base; - prot[TLS_BASE_TX].setsockopt = tls_setsockopt; - prot[TLS_BASE_TX].getsockopt = tls_getsockopt; + prot[TLS_BASE_TX].setsockopt = tls_setsockopt; + prot[TLS_BASE_TX].getsockopt = tls_getsockopt; + prot[TLS_BASE_TX].close = tls_sk_proto_close; prot[TLS_SW_TX] = prot[TLS_BASE_TX]; - prot[TLS_SW_TX].close = tls_sk_proto_close; prot[TLS_SW_TX].sendmsg = tls_sw_sendmsg; prot[TLS_SW_TX].sendpage = tls_sw_sendpage; } diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index 6ae9ca567d6c..5996fb5756e1 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -646,7 +646,7 @@ int tls_sw_sendpage(struct sock *sk, struct page *page, return ret; } -static void tls_sw_free_resources(struct sock *sk) +void tls_sw_free_tx_resources(struct sock *sk) { struct tls_context *tls_ctx = tls_get_ctx(sk); struct tls_sw_context *ctx = tls_sw_ctx(tls_ctx); @@ -685,7 +685,6 @@ int tls_set_sw_offload(struct sock *sk, struct tls_context *ctx) } ctx->priv_ctx = (struct tls_offload_context *)sw_ctx; - ctx->free_resources = tls_sw_free_resources; crypto_info = &ctx->crypto_send.info; switch (crypto_info->cipher_type) { -- GitLab From 93f16446c8ddacbf26ae8408ecd9c9c397b8d5b4 Mon Sep 17 00:00:00 2001 From: Ilya Lesokhin Date: Mon, 13 Nov 2017 10:22:48 +0200 Subject: [PATCH 0183/1286] tls: Avoid copying crypto_info again after cipher_type check. commit 196c31b4b54474b31dee3c30352c45c2a93e9226 upstream. Avoid copying crypto_info again after cipher_type check to avoid a TOCTOU exploits. The temporary array on the stack is removed as we don't really need it Fixes: 3c4d7559159b ('tls: kernel TLS support') Signed-off-by: Ilya Lesokhin Signed-off-by: David S. Miller [bwh: Backported to 4.14: Preserve changes made by earlier backports of "tls: return -EBUSY if crypto_info is already set" and "tls: zero the crypto information from tls_context before freeing"] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/tls/tls_main.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index b5f9c578bcf0..f88df514ad5f 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -381,7 +381,7 @@ static int tls_getsockopt(struct sock *sk, int level, int optname, static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, unsigned int optlen) { - struct tls_crypto_info *crypto_info, tmp_crypto_info; + struct tls_crypto_info *crypto_info; struct tls_context *ctx = tls_get_ctx(sk); int rc = 0; int tx_conf; @@ -391,38 +391,33 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, goto out; } - rc = copy_from_user(&tmp_crypto_info, optval, sizeof(*crypto_info)); + crypto_info = &ctx->crypto_send.info; + /* Currently we don't support set crypto info more than one time */ + if (TLS_CRYPTO_INFO_READY(crypto_info)) { + rc = -EBUSY; + goto out; + } + + rc = copy_from_user(crypto_info, optval, sizeof(*crypto_info)); if (rc) { rc = -EFAULT; goto out; } /* check version */ - if (tmp_crypto_info.version != TLS_1_2_VERSION) { + if (crypto_info->version != TLS_1_2_VERSION) { rc = -ENOTSUPP; - goto out; - } - - /* get user crypto info */ - crypto_info = &ctx->crypto_send.info; - - /* Currently we don't support set crypto info more than one time */ - if (TLS_CRYPTO_INFO_READY(crypto_info)) { - rc = -EBUSY; - goto out; + goto err_crypto_info; } - switch (tmp_crypto_info.cipher_type) { + switch (crypto_info->cipher_type) { case TLS_CIPHER_AES_GCM_128: { if (optlen != sizeof(struct tls12_crypto_info_aes_gcm_128)) { rc = -EINVAL; goto err_crypto_info; } - rc = copy_from_user( - crypto_info, - optval, - sizeof(struct tls12_crypto_info_aes_gcm_128)); - + rc = copy_from_user(crypto_info + 1, optval + sizeof(*crypto_info), + optlen - sizeof(*crypto_info)); if (rc) { rc = -EFAULT; goto err_crypto_info; -- GitLab From 2b8b2e76222f1241cec381eb0ec599ee33e9cd00 Mon Sep 17 00:00:00 2001 From: Ilya Lesokhin Date: Mon, 13 Nov 2017 10:22:49 +0200 Subject: [PATCH 0184/1286] tls: don't override sk_write_space if tls_set_sw_offload fails. commit ee181e5201e640a4b92b217e9eab2531dab57d2c upstream. If we fail to enable tls in the kernel we shouldn't override the sk_write_space callback Fixes: 3c4d7559159b ('tls: kernel TLS support') Signed-off-by: Ilya Lesokhin Signed-off-by: David S. Miller Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/tls/tls_main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index f88df514ad5f..33187e34599b 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -429,9 +429,6 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, goto err_crypto_info; } - ctx->sk_write_space = sk->sk_write_space; - sk->sk_write_space = tls_write_space; - /* currently SW is default, we will have ethtool in future */ rc = tls_set_sw_offload(sk, ctx); tx_conf = TLS_SW_TX; @@ -440,6 +437,8 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval, ctx->tx_conf = tx_conf; update_sk_prot(sk, ctx); + ctx->sk_write_space = sk->sk_write_space; + sk->sk_write_space = tls_write_space; goto out; err_crypto_info: -- GitLab From 2a0f5919e1e6a1c0423d895ab75eb15f94a67c69 Mon Sep 17 00:00:00 2001 From: Boris Pismenny Date: Tue, 27 Feb 2018 14:18:39 +0200 Subject: [PATCH 0185/1286] tls: Use correct sk->sk_prot for IPV6 commit c113187d38ff85dc302a1bb55864b203ebb2ba10 upstream. The tls ulp overrides sk->prot with a new tls specific proto structs. The tls specific structs were previously based on the ipv4 specific tcp_prot sturct. As a result, attaching the tls ulp to an ipv6 tcp socket replaced some ipv6 callback with the ipv4 equivalents. This patch adds ipv6 tls proto structs and uses them when attached to ipv6 sockets. Fixes: 3c4d7559159b ('tls: kernel TLS support') Signed-off-by: Boris Pismenny Signed-off-by: Ilya Lesokhin Signed-off-by: David S. Miller Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/tls/tls_main.c | 52 +++++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index 33187e34599b..e903bdd39b9f 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -46,17 +46,27 @@ MODULE_DESCRIPTION("Transport Layer Security Support"); MODULE_LICENSE("Dual BSD/GPL"); MODULE_ALIAS_TCP_ULP("tls"); +enum { + TLSV4, + TLSV6, + TLS_NUM_PROTS, +}; + enum { TLS_BASE_TX, TLS_SW_TX, TLS_NUM_CONFIG, }; -static struct proto tls_prots[TLS_NUM_CONFIG]; +static struct proto *saved_tcpv6_prot; +static DEFINE_MUTEX(tcpv6_prot_mutex); +static struct proto tls_prots[TLS_NUM_PROTS][TLS_NUM_CONFIG]; static inline void update_sk_prot(struct sock *sk, struct tls_context *ctx) { - sk->sk_prot = &tls_prots[ctx->tx_conf]; + int ip_ver = sk->sk_family == AF_INET6 ? TLSV6 : TLSV4; + + sk->sk_prot = &tls_prots[ip_ver][ctx->tx_conf]; } int wait_on_pending_writer(struct sock *sk, long *timeo) @@ -476,8 +486,21 @@ static int tls_setsockopt(struct sock *sk, int level, int optname, return do_tls_setsockopt(sk, optname, optval, optlen); } +static void build_protos(struct proto *prot, struct proto *base) +{ + prot[TLS_BASE_TX] = *base; + prot[TLS_BASE_TX].setsockopt = tls_setsockopt; + prot[TLS_BASE_TX].getsockopt = tls_getsockopt; + prot[TLS_BASE_TX].close = tls_sk_proto_close; + + prot[TLS_SW_TX] = prot[TLS_BASE_TX]; + prot[TLS_SW_TX].sendmsg = tls_sw_sendmsg; + prot[TLS_SW_TX].sendpage = tls_sw_sendpage; +} + static int tls_init(struct sock *sk) { + int ip_ver = sk->sk_family == AF_INET6 ? TLSV6 : TLSV4; struct inet_connection_sock *icsk = inet_csk(sk); struct tls_context *ctx; int rc = 0; @@ -502,6 +525,17 @@ static int tls_init(struct sock *sk) ctx->getsockopt = sk->sk_prot->getsockopt; ctx->sk_proto_close = sk->sk_prot->close; + /* Build IPv6 TLS whenever the address of tcpv6_prot changes */ + if (ip_ver == TLSV6 && + unlikely(sk->sk_prot != smp_load_acquire(&saved_tcpv6_prot))) { + mutex_lock(&tcpv6_prot_mutex); + if (likely(sk->sk_prot != saved_tcpv6_prot)) { + build_protos(tls_prots[TLSV6], sk->sk_prot); + smp_store_release(&saved_tcpv6_prot, sk->sk_prot); + } + mutex_unlock(&tcpv6_prot_mutex); + } + ctx->tx_conf = TLS_BASE_TX; update_sk_prot(sk, ctx); out: @@ -514,21 +548,9 @@ static struct tcp_ulp_ops tcp_tls_ulp_ops __read_mostly = { .init = tls_init, }; -static void build_protos(struct proto *prot, struct proto *base) -{ - prot[TLS_BASE_TX] = *base; - prot[TLS_BASE_TX].setsockopt = tls_setsockopt; - prot[TLS_BASE_TX].getsockopt = tls_getsockopt; - prot[TLS_BASE_TX].close = tls_sk_proto_close; - - prot[TLS_SW_TX] = prot[TLS_BASE_TX]; - prot[TLS_SW_TX].sendmsg = tls_sw_sendmsg; - prot[TLS_SW_TX].sendpage = tls_sw_sendpage; -} - static int __init tls_register(void) { - build_protos(tls_prots, &tcp_prot); + build_protos(tls_prots[TLSV4], &tcp_prot); tcp_register_ulp(&tcp_tls_ulp_ops); -- GitLab From 39d9e1c62e3f8b5569a0d9bf4d47a3d5d8ae02e2 Mon Sep 17 00:00:00 2001 From: Vakul Garg Date: Mon, 10 Sep 2018 22:53:46 +0530 Subject: [PATCH 0186/1286] net/tls: Fixed return value when tls_complete_pending_work() fails commit 150085791afb8054e11d2e080d4b9cd755dd7f69 upstream. In tls_sw_sendmsg() and tls_sw_sendpage(), the variable 'ret' has been set to return value of tls_complete_pending_work(). This allows return of proper error code if tls_complete_pending_work() fails. Fixes: 3c4d7559159b ("tls: kernel TLS support") Signed-off-by: Vakul Garg Signed-off-by: David S. Miller [bwh: Backported to 4.14: adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- net/tls/tls_sw.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index 5996fb5756e1..d18d4a478e4f 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -388,7 +388,7 @@ int tls_sw_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) { struct tls_context *tls_ctx = tls_get_ctx(sk); struct tls_sw_context *ctx = tls_sw_ctx(tls_ctx); - int ret = 0; + int ret; int required_size; long timeo = sock_sndtimeo(sk, msg->msg_flags & MSG_DONTWAIT); bool eor = !(msg->msg_flags & MSG_MORE); @@ -403,7 +403,8 @@ int tls_sw_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) lock_sock(sk); - if (tls_complete_pending_work(sk, tls_ctx, msg->msg_flags, &timeo)) + ret = tls_complete_pending_work(sk, tls_ctx, msg->msg_flags, &timeo); + if (ret) goto send_end; if (unlikely(msg->msg_controllen)) { @@ -539,7 +540,7 @@ int tls_sw_sendpage(struct sock *sk, struct page *page, { struct tls_context *tls_ctx = tls_get_ctx(sk); struct tls_sw_context *ctx = tls_sw_ctx(tls_ctx); - int ret = 0; + int ret; long timeo = sock_sndtimeo(sk, flags & MSG_DONTWAIT); bool eor; size_t orig_size = size; @@ -559,7 +560,8 @@ int tls_sw_sendpage(struct sock *sk, struct page *page, sk_clear_bit(SOCKWQ_ASYNC_NOSPACE, sk); - if (tls_complete_pending_work(sk, tls_ctx, flags, &timeo)) + ret = tls_complete_pending_work(sk, tls_ctx, flags, &timeo); + if (ret) goto sendpage_end; /* Call the sk_stream functions to manage the sndbuf mem. */ -- GitLab From 107b02c81a8761f1f7efc1e8b54d435324ccd13e Mon Sep 17 00:00:00 2001 From: Lior David Date: Tue, 14 Nov 2017 15:25:39 +0200 Subject: [PATCH 0187/1286] wil6210: missing length check in wmi_set_ie commit b5a8ffcae4103a9d823ea3aa3a761f65779fbe2a upstream. Add a length check in wmi_set_ie to detect unsigned integer overflow. Signed-off-by: Lior David Signed-off-by: Maya Erez Signed-off-by: Kalle Valo Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/wil6210/wmi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c index ffdd2fa401b1..d63d7c326801 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c @@ -1380,8 +1380,14 @@ int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie) }; int rc; u16 len = sizeof(struct wmi_set_appie_cmd) + ie_len; - struct wmi_set_appie_cmd *cmd = kzalloc(len, GFP_KERNEL); + struct wmi_set_appie_cmd *cmd; + if (len < ie_len) { + rc = -EINVAL; + goto out; + } + + cmd = kzalloc(len, GFP_KERNEL); if (!cmd) { rc = -ENOMEM; goto out; -- GitLab From f7eef132ccc95c9af50b647c5da0511d2b8492f8 Mon Sep 17 00:00:00 2001 From: Gu Jinxiang Date: Wed, 4 Jul 2018 18:16:39 +0800 Subject: [PATCH 0188/1286] btrfs: validate type when reading a chunk commit 315409b0098fb2651d86553f0436b70502b29bb2 upstream. Reported in https://bugzilla.kernel.org/show_bug.cgi?id=199839, with an image that has an invalid chunk type but does not return an error. Add chunk type check in btrfs_check_chunk_valid, to detect the wrong type combinations. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199839 Reported-by: Xu Wen Reviewed-by: Qu Wenruo Signed-off-by: Gu Jinxiang Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/volumes.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index a0947f4a3e87..cfd5728e7519 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -6353,6 +6353,8 @@ static int btrfs_check_chunk_valid(struct btrfs_fs_info *fs_info, u16 num_stripes; u16 sub_stripes; u64 type; + u64 features; + bool mixed = false; length = btrfs_chunk_length(leaf, chunk); stripe_len = btrfs_chunk_stripe_len(leaf, chunk); @@ -6391,6 +6393,32 @@ static int btrfs_check_chunk_valid(struct btrfs_fs_info *fs_info, btrfs_chunk_type(leaf, chunk)); return -EIO; } + + if ((type & BTRFS_BLOCK_GROUP_TYPE_MASK) == 0) { + btrfs_err(fs_info, "missing chunk type flag: 0x%llx", type); + return -EIO; + } + + if ((type & BTRFS_BLOCK_GROUP_SYSTEM) && + (type & (BTRFS_BLOCK_GROUP_METADATA | BTRFS_BLOCK_GROUP_DATA))) { + btrfs_err(fs_info, + "system chunk with data or metadata type: 0x%llx", type); + return -EIO; + } + + features = btrfs_super_incompat_flags(fs_info->super_copy); + if (features & BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS) + mixed = true; + + if (!mixed) { + if ((type & BTRFS_BLOCK_GROUP_METADATA) && + (type & BTRFS_BLOCK_GROUP_DATA)) { + btrfs_err(fs_info, + "mixed chunk type in non-mixed mode: 0x%llx", type); + return -EIO; + } + } + if ((type & BTRFS_BLOCK_GROUP_RAID10 && sub_stripes != 2) || (type & BTRFS_BLOCK_GROUP_RAID1 && num_stripes < 1) || (type & BTRFS_BLOCK_GROUP_RAID5 && num_stripes < 2) || -- GitLab From 895586ecb7a4528336d41f81d0ce3985e8abbed6 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 1 Aug 2018 10:37:17 +0800 Subject: [PATCH 0189/1286] btrfs: Verify that every chunk has corresponding block group at mount time commit 7ef49515fa6727cb4b6f2f5b0ffbc5fc20a9f8c6 upstream. If a crafted image has missing block group items, it could cause unexpected behavior and breaks the assumption of 1:1 chunk<->block group mapping. Although we have the block group -> chunk mapping check, we still need chunk -> block group mapping check. This patch will do extra check to ensure each chunk has its corresponding block group. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199847 Reported-by: Xu Wen Signed-off-by: Qu Wenruo Reviewed-by: Gu Jinxiang Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/extent-tree.c | 58 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index 2cb3569ac548..fdc42eddccc2 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -10092,6 +10092,62 @@ btrfs_create_block_group_cache(struct btrfs_fs_info *fs_info, return cache; } + +/* + * Iterate all chunks and verify that each of them has the corresponding block + * group + */ +static int check_chunk_block_group_mappings(struct btrfs_fs_info *fs_info) +{ + struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree; + struct extent_map *em; + struct btrfs_block_group_cache *bg; + u64 start = 0; + int ret = 0; + + while (1) { + read_lock(&map_tree->map_tree.lock); + /* + * lookup_extent_mapping will return the first extent map + * intersecting the range, so setting @len to 1 is enough to + * get the first chunk. + */ + em = lookup_extent_mapping(&map_tree->map_tree, start, 1); + read_unlock(&map_tree->map_tree.lock); + if (!em) + break; + + bg = btrfs_lookup_block_group(fs_info, em->start); + if (!bg) { + btrfs_err(fs_info, + "chunk start=%llu len=%llu doesn't have corresponding block group", + em->start, em->len); + ret = -EUCLEAN; + free_extent_map(em); + break; + } + if (bg->key.objectid != em->start || + bg->key.offset != em->len || + (bg->flags & BTRFS_BLOCK_GROUP_TYPE_MASK) != + (em->map_lookup->type & BTRFS_BLOCK_GROUP_TYPE_MASK)) { + btrfs_err(fs_info, +"chunk start=%llu len=%llu flags=0x%llx doesn't match block group start=%llu len=%llu flags=0x%llx", + em->start, em->len, + em->map_lookup->type & BTRFS_BLOCK_GROUP_TYPE_MASK, + bg->key.objectid, bg->key.offset, + bg->flags & BTRFS_BLOCK_GROUP_TYPE_MASK); + ret = -EUCLEAN; + free_extent_map(em); + btrfs_put_block_group(bg); + break; + } + start = em->start + em->len; + free_extent_map(em); + btrfs_put_block_group(bg); + } + return ret; +} + int btrfs_read_block_groups(struct btrfs_fs_info *info) { struct btrfs_path *path; @@ -10264,7 +10320,7 @@ int btrfs_read_block_groups(struct btrfs_fs_info *info) } init_global_block_rsv(info); - ret = 0; + ret = check_chunk_block_group_mappings(info); error: btrfs_free_path(path); return ret; -- GitLab From a5cc85fe139c181e53cc557230c5ea4001a90c80 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 23 Aug 2017 16:57:56 +0900 Subject: [PATCH 0190/1286] btrfs: Refactor check_leaf function for later expansion commit c3267bbaa9cae09b62960eafe33ad19196803285 upstream. Current check_leaf() function does a good job checking key order and item offset/size. However it only checks from slot 0 to the last but one slot, this is good but makes later expansion hard. So this refactoring iterates from slot 0 to the last slot. For key comparison, it uses a key with all 0 as initial key, so all valid keys should be larger than that. And for item size/offset checks, it compares current item end with previous item offset. For slot 0, use leaf end as a special case. This makes later item/key offset checks and item size checks easier to be implemented. Also, makes check_leaf() to return -EUCLEAN other than -EIO to indicate error. Signed-off-by: Qu Wenruo Reviewed-by: Nikolay Borisov Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/disk-io.c | 50 +++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 0e67cee73c53..4a1e63df1183 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -554,8 +554,9 @@ static noinline int check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) { struct btrfs_fs_info *fs_info = root->fs_info; + /* No valid key type is 0, so all key should be larger than this key */ + struct btrfs_key prev_key = {0, 0, 0}; struct btrfs_key key; - struct btrfs_key leaf_key; u32 nritems = btrfs_header_nritems(leaf); int slot; @@ -588,7 +589,7 @@ static noinline int check_leaf(struct btrfs_root *root, CORRUPT("non-root leaf's nritems is 0", leaf, check_root, 0); free_extent_buffer(eb); - return -EIO; + return -EUCLEAN; } free_extent_buffer(eb); } @@ -598,28 +599,23 @@ static noinline int check_leaf(struct btrfs_root *root, if (nritems == 0) return 0; - /* Check the 0 item */ - if (btrfs_item_offset_nr(leaf, 0) + btrfs_item_size_nr(leaf, 0) != - BTRFS_LEAF_DATA_SIZE(fs_info)) { - CORRUPT("invalid item offset size pair", leaf, root, 0); - return -EIO; - } - /* - * Check to make sure each items keys are in the correct order and their - * offsets make sense. We only have to loop through nritems-1 because - * we check the current slot against the next slot, which verifies the - * next slot's offset+size makes sense and that the current's slot - * offset is correct. + * Check the following things to make sure this is a good leaf, and + * leaf users won't need to bother with similar sanity checks: + * + * 1) key order + * 2) item offset and size + * No overlap, no hole, all inside the leaf. */ - for (slot = 0; slot < nritems - 1; slot++) { - btrfs_item_key_to_cpu(leaf, &leaf_key, slot); - btrfs_item_key_to_cpu(leaf, &key, slot + 1); + for (slot = 0; slot < nritems; slot++) { + u32 item_end_expected; + + btrfs_item_key_to_cpu(leaf, &key, slot); /* Make sure the keys are in the right order */ - if (btrfs_comp_cpu_keys(&leaf_key, &key) >= 0) { + if (btrfs_comp_cpu_keys(&prev_key, &key) >= 0) { CORRUPT("bad key order", leaf, root, slot); - return -EIO; + return -EUCLEAN; } /* @@ -627,10 +623,14 @@ static noinline int check_leaf(struct btrfs_root *root, * item data starts at the end of the leaf and grows towards the * front. */ - if (btrfs_item_offset_nr(leaf, slot) != - btrfs_item_end_nr(leaf, slot + 1)) { + if (slot == 0) + item_end_expected = BTRFS_LEAF_DATA_SIZE(fs_info); + else + item_end_expected = btrfs_item_offset_nr(leaf, + slot - 1); + if (btrfs_item_end_nr(leaf, slot) != item_end_expected) { CORRUPT("slot offset bad", leaf, root, slot); - return -EIO; + return -EUCLEAN; } /* @@ -641,8 +641,12 @@ static noinline int check_leaf(struct btrfs_root *root, if (btrfs_item_end_nr(leaf, slot) > BTRFS_LEAF_DATA_SIZE(fs_info)) { CORRUPT("slot end outside of leaf", leaf, root, slot); - return -EIO; + return -EUCLEAN; } + + prev_key.objectid = key.objectid; + prev_key.type = key.type; + prev_key.offset = key.offset; } return 0; -- GitLab From ac6ea50bb6306ed056222a5967b2bad3c3a9e2dd Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 23 Aug 2017 16:57:57 +0900 Subject: [PATCH 0191/1286] btrfs: Check if item pointer overlaps with the item itself commit 7f43d4affb2a254d421ab20b0cf65ac2569909fb upstream. Function check_leaf() checks if any item pointer points outside of the leaf, but it doesn't check if the pointer overlaps with the item itself. Normally only the last item may be the victim, but adding such check is never a bad idea anyway. Signed-off-by: Qu Wenruo Reviewed-by: Nikolay Borisov Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/disk-io.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 4a1e63df1183..da7b2039e4cb 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -644,6 +644,13 @@ static noinline int check_leaf(struct btrfs_root *root, return -EUCLEAN; } + /* Also check if the item pointer overlaps with btrfs item. */ + if (btrfs_item_nr_offset(slot) + sizeof(struct btrfs_item) > + btrfs_item_ptr_offset(leaf, slot)) { + CORRUPT("slot overlap with its data", leaf, root, slot); + return -EUCLEAN; + } + prev_key.objectid = key.objectid; prev_key.type = key.type; prev_key.offset = key.offset; -- GitLab From fa5d29e6d7cbfac45e3b7bdb7bb3d48f124bbe55 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 23 Aug 2017 16:57:58 +0900 Subject: [PATCH 0192/1286] btrfs: Add sanity check for EXTENT_DATA when reading out leaf commit 40c3c40947324d9f40bf47830c92c59a9bbadf4a upstream. Add extra checks for item with EXTENT_DATA type. This checks the following thing: 0) Key offset All key offsets must be aligned to sectorsize. Inline extent must have 0 for key offset. 1) Item size Uncompressed inline file extent size must match item size. (Compressed inline file extent has no information about its on-disk size.) Regular/preallocated file extent size must be a fixed value. 2) Every member of regular file extent item Including alignment for bytenr and offset, possible value for compression/encryption/type. 3) Type/compression/encode must be one of the valid values. This should be the most comprehensive and strict check in the context of btrfs_item for EXTENT_DATA. Signed-off-by: Qu Wenruo Reviewed-by: Nikolay Borisov Reviewed-by: David Sterba [ switch to BTRFS_FILE_EXTENT_TYPES, similar to what BTRFS_COMPRESS_TYPES does ] Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/disk-io.c | 103 ++++++++++++++++++++++++++++++++ include/uapi/linux/btrfs_tree.h | 1 + 2 files changed, 104 insertions(+) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index da7b2039e4cb..ab8925b2efd1 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -550,6 +550,100 @@ static int check_tree_block_fsid(struct btrfs_fs_info *fs_info, btrfs_header_level(eb) == 0 ? "leaf" : "node", \ reason, btrfs_header_bytenr(eb), root->objectid, slot) +static int check_extent_data_item(struct btrfs_root *root, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + struct btrfs_file_extent_item *fi; + u32 sectorsize = root->fs_info->sectorsize; + u32 item_size = btrfs_item_size_nr(leaf, slot); + + if (!IS_ALIGNED(key->offset, sectorsize)) { + CORRUPT("unaligned key offset for file extent", + leaf, root, slot); + return -EUCLEAN; + } + + fi = btrfs_item_ptr(leaf, slot, struct btrfs_file_extent_item); + + if (btrfs_file_extent_type(leaf, fi) > BTRFS_FILE_EXTENT_TYPES) { + CORRUPT("invalid file extent type", leaf, root, slot); + return -EUCLEAN; + } + + /* + * Support for new compression/encrption must introduce incompat flag, + * and must be caught in open_ctree(). + */ + if (btrfs_file_extent_compression(leaf, fi) > BTRFS_COMPRESS_TYPES) { + CORRUPT("invalid file extent compression", leaf, root, slot); + return -EUCLEAN; + } + if (btrfs_file_extent_encryption(leaf, fi)) { + CORRUPT("invalid file extent encryption", leaf, root, slot); + return -EUCLEAN; + } + if (btrfs_file_extent_type(leaf, fi) == BTRFS_FILE_EXTENT_INLINE) { + /* Inline extent must have 0 as key offset */ + if (key->offset) { + CORRUPT("inline extent has non-zero key offset", + leaf, root, slot); + return -EUCLEAN; + } + + /* Compressed inline extent has no on-disk size, skip it */ + if (btrfs_file_extent_compression(leaf, fi) != + BTRFS_COMPRESS_NONE) + return 0; + + /* Uncompressed inline extent size must match item size */ + if (item_size != BTRFS_FILE_EXTENT_INLINE_DATA_START + + btrfs_file_extent_ram_bytes(leaf, fi)) { + CORRUPT("plaintext inline extent has invalid size", + leaf, root, slot); + return -EUCLEAN; + } + return 0; + } + + /* Regular or preallocated extent has fixed item size */ + if (item_size != sizeof(*fi)) { + CORRUPT( + "regluar or preallocated extent data item size is invalid", + leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(btrfs_file_extent_ram_bytes(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_disk_bytenr(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_disk_num_bytes(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_offset(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_num_bytes(leaf, fi), sectorsize)) { + CORRUPT( + "regular or preallocated extent data item has unaligned value", + leaf, root, slot); + return -EUCLEAN; + } + + return 0; +} + +/* + * Common point to switch the item-specific validation. + */ +static int check_leaf_item(struct btrfs_root *root, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + int ret = 0; + + switch (key->type) { + case BTRFS_EXTENT_DATA_KEY: + ret = check_extent_data_item(root, leaf, key, slot); + break; + } + return ret; +} + static noinline int check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) { @@ -606,9 +700,13 @@ static noinline int check_leaf(struct btrfs_root *root, * 1) key order * 2) item offset and size * No overlap, no hole, all inside the leaf. + * 3) item content + * If possible, do comprehensive sanity check. + * NOTE: All checks must only rely on the item data itself. */ for (slot = 0; slot < nritems; slot++) { u32 item_end_expected; + int ret; btrfs_item_key_to_cpu(leaf, &key, slot); @@ -651,6 +749,11 @@ static noinline int check_leaf(struct btrfs_root *root, return -EUCLEAN; } + /* Check if the item size and content meet other criteria */ + ret = check_leaf_item(root, leaf, &key, slot); + if (ret < 0) + return ret; + prev_key.objectid = key.objectid; prev_key.type = key.type; prev_key.offset = key.offset; diff --git a/include/uapi/linux/btrfs_tree.h b/include/uapi/linux/btrfs_tree.h index 7115838fbf2a..38ab0e06259a 100644 --- a/include/uapi/linux/btrfs_tree.h +++ b/include/uapi/linux/btrfs_tree.h @@ -734,6 +734,7 @@ struct btrfs_balance_item { #define BTRFS_FILE_EXTENT_INLINE 0 #define BTRFS_FILE_EXTENT_REG 1 #define BTRFS_FILE_EXTENT_PREALLOC 2 +#define BTRFS_FILE_EXTENT_TYPES 2 struct btrfs_file_extent_item { /* -- GitLab From 64948fd63f662180c00f0fe70b623eab51108a89 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 23 Aug 2017 16:57:59 +0900 Subject: [PATCH 0193/1286] btrfs: Add checker for EXTENT_CSUM commit 4b865cab96fe2a30ed512cf667b354bd291b3b0a upstream. EXTENT_CSUM checker is a relatively easy one, only needs to check: 1) Objectid Fixed to BTRFS_EXTENT_CSUM_OBJECTID 2) Key offset alignment Must be aligned to sectorsize 3) Item size alignedment Must be aligned to csum size Signed-off-by: Qu Wenruo Reviewed-by: Nikolay Borisov Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/disk-io.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index ab8925b2efd1..53841d773a40 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -627,6 +627,27 @@ static int check_extent_data_item(struct btrfs_root *root, return 0; } +static int check_csum_item(struct btrfs_root *root, struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + u32 sectorsize = root->fs_info->sectorsize; + u32 csumsize = btrfs_super_csum_size(root->fs_info->super_copy); + + if (key->objectid != BTRFS_EXTENT_CSUM_OBJECTID) { + CORRUPT("invalid objectid for csum item", leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(key->offset, sectorsize)) { + CORRUPT("unaligned key offset for csum item", leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(btrfs_item_size_nr(leaf, slot), csumsize)) { + CORRUPT("unaligned csum item size", leaf, root, slot); + return -EUCLEAN; + } + return 0; +} + /* * Common point to switch the item-specific validation. */ @@ -640,6 +661,9 @@ static int check_leaf_item(struct btrfs_root *root, case BTRFS_EXTENT_DATA_KEY: ret = check_extent_data_item(root, leaf, key, slot); break; + case BTRFS_EXTENT_CSUM_KEY: + ret = check_csum_item(root, leaf, key, slot); + break; } return ret; } -- GitLab From eb3493e2476c5ce60c6a376a6b50d465f2864968 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Mon, 9 Oct 2017 01:51:02 +0000 Subject: [PATCH 0194/1286] btrfs: Move leaf and node validation checker to tree-checker.c commit 557ea5dd003d371536f6b4e8f7c8209a2b6fd4e3 upstream. It's no doubt the comprehensive tree block checker will become larger, so moving them into their own files is quite reasonable. Signed-off-by: Qu Wenruo [ wording adjustments ] Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/Makefile | 2 +- fs/btrfs/disk-io.c | 285 +----------------------------------- fs/btrfs/tree-checker.c | 309 ++++++++++++++++++++++++++++++++++++++++ fs/btrfs/tree-checker.h | 26 ++++ 4 files changed, 340 insertions(+), 282 deletions(-) create mode 100644 fs/btrfs/tree-checker.c create mode 100644 fs/btrfs/tree-checker.h diff --git a/fs/btrfs/Makefile b/fs/btrfs/Makefile index f2cd9dedb037..195229df5ba0 100644 --- a/fs/btrfs/Makefile +++ b/fs/btrfs/Makefile @@ -10,7 +10,7 @@ btrfs-y += super.o ctree.o extent-tree.o print-tree.o root-tree.o dir-item.o \ export.o tree-log.o free-space-cache.o zlib.o lzo.o zstd.o \ compression.o delayed-ref.o relocation.o delayed-inode.o scrub.o \ reada.o backref.o ulist.o qgroup.o send.o dev-replace.o raid56.o \ - uuid-tree.o props.o hash.o free-space-tree.o + uuid-tree.o props.o hash.o free-space-tree.o tree-checker.o btrfs-$(CONFIG_BTRFS_FS_POSIX_ACL) += acl.o btrfs-$(CONFIG_BTRFS_FS_CHECK_INTEGRITY) += check-integrity.o diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 53841d773a40..2df5e906db08 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -50,6 +50,7 @@ #include "sysfs.h" #include "qgroup.h" #include "compression.h" +#include "tree-checker.h" #ifdef CONFIG_X86 #include @@ -544,284 +545,6 @@ static int check_tree_block_fsid(struct btrfs_fs_info *fs_info, return ret; } -#define CORRUPT(reason, eb, root, slot) \ - btrfs_crit(root->fs_info, \ - "corrupt %s, %s: block=%llu, root=%llu, slot=%d", \ - btrfs_header_level(eb) == 0 ? "leaf" : "node", \ - reason, btrfs_header_bytenr(eb), root->objectid, slot) - -static int check_extent_data_item(struct btrfs_root *root, - struct extent_buffer *leaf, - struct btrfs_key *key, int slot) -{ - struct btrfs_file_extent_item *fi; - u32 sectorsize = root->fs_info->sectorsize; - u32 item_size = btrfs_item_size_nr(leaf, slot); - - if (!IS_ALIGNED(key->offset, sectorsize)) { - CORRUPT("unaligned key offset for file extent", - leaf, root, slot); - return -EUCLEAN; - } - - fi = btrfs_item_ptr(leaf, slot, struct btrfs_file_extent_item); - - if (btrfs_file_extent_type(leaf, fi) > BTRFS_FILE_EXTENT_TYPES) { - CORRUPT("invalid file extent type", leaf, root, slot); - return -EUCLEAN; - } - - /* - * Support for new compression/encrption must introduce incompat flag, - * and must be caught in open_ctree(). - */ - if (btrfs_file_extent_compression(leaf, fi) > BTRFS_COMPRESS_TYPES) { - CORRUPT("invalid file extent compression", leaf, root, slot); - return -EUCLEAN; - } - if (btrfs_file_extent_encryption(leaf, fi)) { - CORRUPT("invalid file extent encryption", leaf, root, slot); - return -EUCLEAN; - } - if (btrfs_file_extent_type(leaf, fi) == BTRFS_FILE_EXTENT_INLINE) { - /* Inline extent must have 0 as key offset */ - if (key->offset) { - CORRUPT("inline extent has non-zero key offset", - leaf, root, slot); - return -EUCLEAN; - } - - /* Compressed inline extent has no on-disk size, skip it */ - if (btrfs_file_extent_compression(leaf, fi) != - BTRFS_COMPRESS_NONE) - return 0; - - /* Uncompressed inline extent size must match item size */ - if (item_size != BTRFS_FILE_EXTENT_INLINE_DATA_START + - btrfs_file_extent_ram_bytes(leaf, fi)) { - CORRUPT("plaintext inline extent has invalid size", - leaf, root, slot); - return -EUCLEAN; - } - return 0; - } - - /* Regular or preallocated extent has fixed item size */ - if (item_size != sizeof(*fi)) { - CORRUPT( - "regluar or preallocated extent data item size is invalid", - leaf, root, slot); - return -EUCLEAN; - } - if (!IS_ALIGNED(btrfs_file_extent_ram_bytes(leaf, fi), sectorsize) || - !IS_ALIGNED(btrfs_file_extent_disk_bytenr(leaf, fi), sectorsize) || - !IS_ALIGNED(btrfs_file_extent_disk_num_bytes(leaf, fi), sectorsize) || - !IS_ALIGNED(btrfs_file_extent_offset(leaf, fi), sectorsize) || - !IS_ALIGNED(btrfs_file_extent_num_bytes(leaf, fi), sectorsize)) { - CORRUPT( - "regular or preallocated extent data item has unaligned value", - leaf, root, slot); - return -EUCLEAN; - } - - return 0; -} - -static int check_csum_item(struct btrfs_root *root, struct extent_buffer *leaf, - struct btrfs_key *key, int slot) -{ - u32 sectorsize = root->fs_info->sectorsize; - u32 csumsize = btrfs_super_csum_size(root->fs_info->super_copy); - - if (key->objectid != BTRFS_EXTENT_CSUM_OBJECTID) { - CORRUPT("invalid objectid for csum item", leaf, root, slot); - return -EUCLEAN; - } - if (!IS_ALIGNED(key->offset, sectorsize)) { - CORRUPT("unaligned key offset for csum item", leaf, root, slot); - return -EUCLEAN; - } - if (!IS_ALIGNED(btrfs_item_size_nr(leaf, slot), csumsize)) { - CORRUPT("unaligned csum item size", leaf, root, slot); - return -EUCLEAN; - } - return 0; -} - -/* - * Common point to switch the item-specific validation. - */ -static int check_leaf_item(struct btrfs_root *root, - struct extent_buffer *leaf, - struct btrfs_key *key, int slot) -{ - int ret = 0; - - switch (key->type) { - case BTRFS_EXTENT_DATA_KEY: - ret = check_extent_data_item(root, leaf, key, slot); - break; - case BTRFS_EXTENT_CSUM_KEY: - ret = check_csum_item(root, leaf, key, slot); - break; - } - return ret; -} - -static noinline int check_leaf(struct btrfs_root *root, - struct extent_buffer *leaf) -{ - struct btrfs_fs_info *fs_info = root->fs_info; - /* No valid key type is 0, so all key should be larger than this key */ - struct btrfs_key prev_key = {0, 0, 0}; - struct btrfs_key key; - u32 nritems = btrfs_header_nritems(leaf); - int slot; - - /* - * Extent buffers from a relocation tree have a owner field that - * corresponds to the subvolume tree they are based on. So just from an - * extent buffer alone we can not find out what is the id of the - * corresponding subvolume tree, so we can not figure out if the extent - * buffer corresponds to the root of the relocation tree or not. So skip - * this check for relocation trees. - */ - if (nritems == 0 && !btrfs_header_flag(leaf, BTRFS_HEADER_FLAG_RELOC)) { - struct btrfs_root *check_root; - - key.objectid = btrfs_header_owner(leaf); - key.type = BTRFS_ROOT_ITEM_KEY; - key.offset = (u64)-1; - - check_root = btrfs_get_fs_root(fs_info, &key, false); - /* - * The only reason we also check NULL here is that during - * open_ctree() some roots has not yet been set up. - */ - if (!IS_ERR_OR_NULL(check_root)) { - struct extent_buffer *eb; - - eb = btrfs_root_node(check_root); - /* if leaf is the root, then it's fine */ - if (leaf != eb) { - CORRUPT("non-root leaf's nritems is 0", - leaf, check_root, 0); - free_extent_buffer(eb); - return -EUCLEAN; - } - free_extent_buffer(eb); - } - return 0; - } - - if (nritems == 0) - return 0; - - /* - * Check the following things to make sure this is a good leaf, and - * leaf users won't need to bother with similar sanity checks: - * - * 1) key order - * 2) item offset and size - * No overlap, no hole, all inside the leaf. - * 3) item content - * If possible, do comprehensive sanity check. - * NOTE: All checks must only rely on the item data itself. - */ - for (slot = 0; slot < nritems; slot++) { - u32 item_end_expected; - int ret; - - btrfs_item_key_to_cpu(leaf, &key, slot); - - /* Make sure the keys are in the right order */ - if (btrfs_comp_cpu_keys(&prev_key, &key) >= 0) { - CORRUPT("bad key order", leaf, root, slot); - return -EUCLEAN; - } - - /* - * Make sure the offset and ends are right, remember that the - * item data starts at the end of the leaf and grows towards the - * front. - */ - if (slot == 0) - item_end_expected = BTRFS_LEAF_DATA_SIZE(fs_info); - else - item_end_expected = btrfs_item_offset_nr(leaf, - slot - 1); - if (btrfs_item_end_nr(leaf, slot) != item_end_expected) { - CORRUPT("slot offset bad", leaf, root, slot); - return -EUCLEAN; - } - - /* - * Check to make sure that we don't point outside of the leaf, - * just in case all the items are consistent to each other, but - * all point outside of the leaf. - */ - if (btrfs_item_end_nr(leaf, slot) > - BTRFS_LEAF_DATA_SIZE(fs_info)) { - CORRUPT("slot end outside of leaf", leaf, root, slot); - return -EUCLEAN; - } - - /* Also check if the item pointer overlaps with btrfs item. */ - if (btrfs_item_nr_offset(slot) + sizeof(struct btrfs_item) > - btrfs_item_ptr_offset(leaf, slot)) { - CORRUPT("slot overlap with its data", leaf, root, slot); - return -EUCLEAN; - } - - /* Check if the item size and content meet other criteria */ - ret = check_leaf_item(root, leaf, &key, slot); - if (ret < 0) - return ret; - - prev_key.objectid = key.objectid; - prev_key.type = key.type; - prev_key.offset = key.offset; - } - - return 0; -} - -static int check_node(struct btrfs_root *root, struct extent_buffer *node) -{ - unsigned long nr = btrfs_header_nritems(node); - struct btrfs_key key, next_key; - int slot; - u64 bytenr; - int ret = 0; - - if (nr == 0 || nr > BTRFS_NODEPTRS_PER_BLOCK(root->fs_info)) { - btrfs_crit(root->fs_info, - "corrupt node: block %llu root %llu nritems %lu", - node->start, root->objectid, nr); - return -EIO; - } - - for (slot = 0; slot < nr - 1; slot++) { - bytenr = btrfs_node_blockptr(node, slot); - btrfs_node_key_to_cpu(node, &key, slot); - btrfs_node_key_to_cpu(node, &next_key, slot + 1); - - if (!bytenr) { - CORRUPT("invalid item slot", node, root, slot); - ret = -EIO; - goto out; - } - - if (btrfs_comp_cpu_keys(&key, &next_key) >= 0) { - CORRUPT("bad key order", node, root, slot); - ret = -EIO; - goto out; - } - } -out: - return ret; -} - static int btree_readpage_end_io_hook(struct btrfs_io_bio *io_bio, u64 phy_offset, struct page *page, u64 start, u64 end, int mirror) @@ -887,12 +610,12 @@ static int btree_readpage_end_io_hook(struct btrfs_io_bio *io_bio, * that we don't try and read the other copies of this block, just * return -EIO. */ - if (found_level == 0 && check_leaf(root, eb)) { + if (found_level == 0 && btrfs_check_leaf(root, eb)) { set_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags); ret = -EIO; } - if (found_level > 0 && check_node(root, eb)) + if (found_level > 0 && btrfs_check_node(root, eb)) ret = -EIO; if (!ret) @@ -4147,7 +3870,7 @@ void btrfs_mark_buffer_dirty(struct extent_buffer *buf) buf->len, fs_info->dirty_metadata_batch); #ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY - if (btrfs_header_level(buf) == 0 && check_leaf(root, buf)) { + if (btrfs_header_level(buf) == 0 && btrfs_check_leaf(root, buf)) { btrfs_print_leaf(buf); ASSERT(0); } diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c new file mode 100644 index 000000000000..56e25a630103 --- /dev/null +++ b/fs/btrfs/tree-checker.c @@ -0,0 +1,309 @@ +/* + * Copyright (C) Qu Wenruo 2017. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public + * License v2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program. + */ + +/* + * The module is used to catch unexpected/corrupted tree block data. + * Such behavior can be caused either by a fuzzed image or bugs. + * + * The objective is to do leaf/node validation checks when tree block is read + * from disk, and check *every* possible member, so other code won't + * need to checking them again. + * + * Due to the potential and unwanted damage, every checker needs to be + * carefully reviewed otherwise so it does not prevent mount of valid images. + */ + +#include "ctree.h" +#include "tree-checker.h" +#include "disk-io.h" +#include "compression.h" + +#define CORRUPT(reason, eb, root, slot) \ + btrfs_crit(root->fs_info, \ + "corrupt %s, %s: block=%llu, root=%llu, slot=%d", \ + btrfs_header_level(eb) == 0 ? "leaf" : "node", \ + reason, btrfs_header_bytenr(eb), root->objectid, slot) + +static int check_extent_data_item(struct btrfs_root *root, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + struct btrfs_file_extent_item *fi; + u32 sectorsize = root->fs_info->sectorsize; + u32 item_size = btrfs_item_size_nr(leaf, slot); + + if (!IS_ALIGNED(key->offset, sectorsize)) { + CORRUPT("unaligned key offset for file extent", + leaf, root, slot); + return -EUCLEAN; + } + + fi = btrfs_item_ptr(leaf, slot, struct btrfs_file_extent_item); + + if (btrfs_file_extent_type(leaf, fi) > BTRFS_FILE_EXTENT_TYPES) { + CORRUPT("invalid file extent type", leaf, root, slot); + return -EUCLEAN; + } + + /* + * Support for new compression/encrption must introduce incompat flag, + * and must be caught in open_ctree(). + */ + if (btrfs_file_extent_compression(leaf, fi) > BTRFS_COMPRESS_TYPES) { + CORRUPT("invalid file extent compression", leaf, root, slot); + return -EUCLEAN; + } + if (btrfs_file_extent_encryption(leaf, fi)) { + CORRUPT("invalid file extent encryption", leaf, root, slot); + return -EUCLEAN; + } + if (btrfs_file_extent_type(leaf, fi) == BTRFS_FILE_EXTENT_INLINE) { + /* Inline extent must have 0 as key offset */ + if (key->offset) { + CORRUPT("inline extent has non-zero key offset", + leaf, root, slot); + return -EUCLEAN; + } + + /* Compressed inline extent has no on-disk size, skip it */ + if (btrfs_file_extent_compression(leaf, fi) != + BTRFS_COMPRESS_NONE) + return 0; + + /* Uncompressed inline extent size must match item size */ + if (item_size != BTRFS_FILE_EXTENT_INLINE_DATA_START + + btrfs_file_extent_ram_bytes(leaf, fi)) { + CORRUPT("plaintext inline extent has invalid size", + leaf, root, slot); + return -EUCLEAN; + } + return 0; + } + + /* Regular or preallocated extent has fixed item size */ + if (item_size != sizeof(*fi)) { + CORRUPT( + "regluar or preallocated extent data item size is invalid", + leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(btrfs_file_extent_ram_bytes(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_disk_bytenr(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_disk_num_bytes(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_offset(leaf, fi), sectorsize) || + !IS_ALIGNED(btrfs_file_extent_num_bytes(leaf, fi), sectorsize)) { + CORRUPT( + "regular or preallocated extent data item has unaligned value", + leaf, root, slot); + return -EUCLEAN; + } + + return 0; +} + +static int check_csum_item(struct btrfs_root *root, struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + u32 sectorsize = root->fs_info->sectorsize; + u32 csumsize = btrfs_super_csum_size(root->fs_info->super_copy); + + if (key->objectid != BTRFS_EXTENT_CSUM_OBJECTID) { + CORRUPT("invalid objectid for csum item", leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(key->offset, sectorsize)) { + CORRUPT("unaligned key offset for csum item", leaf, root, slot); + return -EUCLEAN; + } + if (!IS_ALIGNED(btrfs_item_size_nr(leaf, slot), csumsize)) { + CORRUPT("unaligned csum item size", leaf, root, slot); + return -EUCLEAN; + } + return 0; +} + +/* + * Common point to switch the item-specific validation. + */ +static int check_leaf_item(struct btrfs_root *root, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + int ret = 0; + + switch (key->type) { + case BTRFS_EXTENT_DATA_KEY: + ret = check_extent_data_item(root, leaf, key, slot); + break; + case BTRFS_EXTENT_CSUM_KEY: + ret = check_csum_item(root, leaf, key, slot); + break; + } + return ret; +} + +int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) +{ + struct btrfs_fs_info *fs_info = root->fs_info; + /* No valid key type is 0, so all key should be larger than this key */ + struct btrfs_key prev_key = {0, 0, 0}; + struct btrfs_key key; + u32 nritems = btrfs_header_nritems(leaf); + int slot; + + /* + * Extent buffers from a relocation tree have a owner field that + * corresponds to the subvolume tree they are based on. So just from an + * extent buffer alone we can not find out what is the id of the + * corresponding subvolume tree, so we can not figure out if the extent + * buffer corresponds to the root of the relocation tree or not. So + * skip this check for relocation trees. + */ + if (nritems == 0 && !btrfs_header_flag(leaf, BTRFS_HEADER_FLAG_RELOC)) { + struct btrfs_root *check_root; + + key.objectid = btrfs_header_owner(leaf); + key.type = BTRFS_ROOT_ITEM_KEY; + key.offset = (u64)-1; + + check_root = btrfs_get_fs_root(fs_info, &key, false); + /* + * The only reason we also check NULL here is that during + * open_ctree() some roots has not yet been set up. + */ + if (!IS_ERR_OR_NULL(check_root)) { + struct extent_buffer *eb; + + eb = btrfs_root_node(check_root); + /* if leaf is the root, then it's fine */ + if (leaf != eb) { + CORRUPT("non-root leaf's nritems is 0", + leaf, check_root, 0); + free_extent_buffer(eb); + return -EUCLEAN; + } + free_extent_buffer(eb); + } + return 0; + } + + if (nritems == 0) + return 0; + + /* + * Check the following things to make sure this is a good leaf, and + * leaf users won't need to bother with similar sanity checks: + * + * 1) key ordering + * 2) item offset and size + * No overlap, no hole, all inside the leaf. + * 3) item content + * If possible, do comprehensive sanity check. + * NOTE: All checks must only rely on the item data itself. + */ + for (slot = 0; slot < nritems; slot++) { + u32 item_end_expected; + int ret; + + btrfs_item_key_to_cpu(leaf, &key, slot); + + /* Make sure the keys are in the right order */ + if (btrfs_comp_cpu_keys(&prev_key, &key) >= 0) { + CORRUPT("bad key order", leaf, root, slot); + return -EUCLEAN; + } + + /* + * Make sure the offset and ends are right, remember that the + * item data starts at the end of the leaf and grows towards the + * front. + */ + if (slot == 0) + item_end_expected = BTRFS_LEAF_DATA_SIZE(fs_info); + else + item_end_expected = btrfs_item_offset_nr(leaf, + slot - 1); + if (btrfs_item_end_nr(leaf, slot) != item_end_expected) { + CORRUPT("slot offset bad", leaf, root, slot); + return -EUCLEAN; + } + + /* + * Check to make sure that we don't point outside of the leaf, + * just in case all the items are consistent to each other, but + * all point outside of the leaf. + */ + if (btrfs_item_end_nr(leaf, slot) > + BTRFS_LEAF_DATA_SIZE(fs_info)) { + CORRUPT("slot end outside of leaf", leaf, root, slot); + return -EUCLEAN; + } + + /* Also check if the item pointer overlaps with btrfs item. */ + if (btrfs_item_nr_offset(slot) + sizeof(struct btrfs_item) > + btrfs_item_ptr_offset(leaf, slot)) { + CORRUPT("slot overlap with its data", leaf, root, slot); + return -EUCLEAN; + } + + /* Check if the item size and content meet other criteria */ + ret = check_leaf_item(root, leaf, &key, slot); + if (ret < 0) + return ret; + + prev_key.objectid = key.objectid; + prev_key.type = key.type; + prev_key.offset = key.offset; + } + + return 0; +} + +int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node) +{ + unsigned long nr = btrfs_header_nritems(node); + struct btrfs_key key, next_key; + int slot; + u64 bytenr; + int ret = 0; + + if (nr == 0 || nr > BTRFS_NODEPTRS_PER_BLOCK(root->fs_info)) { + btrfs_crit(root->fs_info, + "corrupt node: block %llu root %llu nritems %lu", + node->start, root->objectid, nr); + return -EIO; + } + + for (slot = 0; slot < nr - 1; slot++) { + bytenr = btrfs_node_blockptr(node, slot); + btrfs_node_key_to_cpu(node, &key, slot); + btrfs_node_key_to_cpu(node, &next_key, slot + 1); + + if (!bytenr) { + CORRUPT("invalid item slot", node, root, slot); + ret = -EIO; + goto out; + } + + if (btrfs_comp_cpu_keys(&key, &next_key) >= 0) { + CORRUPT("bad key order", node, root, slot); + ret = -EIO; + goto out; + } + } +out: + return ret; +} diff --git a/fs/btrfs/tree-checker.h b/fs/btrfs/tree-checker.h new file mode 100644 index 000000000000..96c486e95d70 --- /dev/null +++ b/fs/btrfs/tree-checker.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) Qu Wenruo 2017. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public + * License v2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program. + */ + +#ifndef __BTRFS_TREE_CHECKER__ +#define __BTRFS_TREE_CHECKER__ + +#include "ctree.h" +#include "extent_io.h" + +int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf); +int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node); + +#endif -- GitLab From b3032dc25fb4d7ffdbb61df875cc09b3ec662c85 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Mon, 9 Oct 2017 01:51:03 +0000 Subject: [PATCH 0195/1286] btrfs: tree-checker: Enhance btrfs_check_node output commit bba4f29896c986c4cec17bc0f19f2ce644fceae1 upstream. Use inline function to replace macro since we don't need stringification. (Macro still exists until all callers get updated) And add more info about the error, and replace EIO with EUCLEAN. For nr_items error, report if it's too large or too small, and output the valid value range. For node block pointer, added a new alignment checker. For key order, also output the next key to make the problem more obvious. Signed-off-by: Qu Wenruo [ wording adjustments, unindented long strings ] Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 68 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index 56e25a630103..5acdf3355a3f 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -37,6 +37,46 @@ btrfs_header_level(eb) == 0 ? "leaf" : "node", \ reason, btrfs_header_bytenr(eb), root->objectid, slot) +/* + * Error message should follow the following format: + * corrupt : , [, ] + * + * @type: leaf or node + * @identifier: the necessary info to locate the leaf/node. + * It's recommened to decode key.objecitd/offset if it's + * meaningful. + * @reason: describe the error + * @bad_value: optional, it's recommened to output bad value and its + * expected value (range). + * + * Since comma is used to separate the components, only space is allowed + * inside each component. + */ + +/* + * Append generic "corrupt leaf/node root=%llu block=%llu slot=%d: " to @fmt. + * Allows callers to customize the output. + */ +__printf(4, 5) +static void generic_err(const struct btrfs_root *root, + const struct extent_buffer *eb, int slot, + const char *fmt, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, fmt); + + vaf.fmt = fmt; + vaf.va = &args; + + btrfs_crit(root->fs_info, + "corrupt %s: root=%llu block=%llu slot=%d, %pV", + btrfs_header_level(eb) == 0 ? "leaf" : "node", + root->objectid, btrfs_header_bytenr(eb), slot, &vaf); + va_end(args); +} + static int check_extent_data_item(struct btrfs_root *root, struct extent_buffer *leaf, struct btrfs_key *key, int slot) @@ -282,9 +322,11 @@ int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node) if (nr == 0 || nr > BTRFS_NODEPTRS_PER_BLOCK(root->fs_info)) { btrfs_crit(root->fs_info, - "corrupt node: block %llu root %llu nritems %lu", - node->start, root->objectid, nr); - return -EIO; +"corrupt node: root=%llu block=%llu, nritems too %s, have %lu expect range [1,%u]", + root->objectid, node->start, + nr == 0 ? "small" : "large", nr, + BTRFS_NODEPTRS_PER_BLOCK(root->fs_info)); + return -EUCLEAN; } for (slot = 0; slot < nr - 1; slot++) { @@ -293,14 +335,26 @@ int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node) btrfs_node_key_to_cpu(node, &next_key, slot + 1); if (!bytenr) { - CORRUPT("invalid item slot", node, root, slot); - ret = -EIO; + generic_err(root, node, slot, + "invalid NULL node pointer"); + ret = -EUCLEAN; + goto out; + } + if (!IS_ALIGNED(bytenr, root->fs_info->sectorsize)) { + generic_err(root, node, slot, + "unaligned pointer, have %llu should be aligned to %u", + bytenr, root->fs_info->sectorsize); + ret = -EUCLEAN; goto out; } if (btrfs_comp_cpu_keys(&key, &next_key) >= 0) { - CORRUPT("bad key order", node, root, slot); - ret = -EIO; + generic_err(root, node, slot, + "bad key order, current (%llu %u %llu) next (%llu %u %llu)", + key.objectid, key.type, key.offset, + next_key.objectid, next_key.type, + next_key.offset); + ret = -EUCLEAN; goto out; } } -- GitLab From b6a07f903543e45d3660d5fbc8385f89da763c81 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 8 Nov 2017 08:54:24 +0800 Subject: [PATCH 0196/1286] btrfs: tree-checker: Fix false panic for sanity test commit 69fc6cbbac542c349b3d350d10f6e394c253c81d upstream. [BUG] If we run btrfs with CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y, it will instantly cause kernel panic like: ------ ... assertion failed: 0, file: fs/btrfs/disk-io.c, line: 3853 ... Call Trace: btrfs_mark_buffer_dirty+0x187/0x1f0 [btrfs] setup_items_for_insert+0x385/0x650 [btrfs] __btrfs_drop_extents+0x129a/0x1870 [btrfs] ... ----- [Cause] Btrfs will call btrfs_check_leaf() in btrfs_mark_buffer_dirty() to check if the leaf is valid with CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y. However quite some btrfs_mark_buffer_dirty() callers(*) don't really initialize its item data but only initialize its item pointers, leaving item data uninitialized. This makes tree-checker catch uninitialized data as error, causing such panic. *: These callers include but not limited to setup_items_for_insert() btrfs_split_item() btrfs_expand_item() [Fix] Add a new parameter @check_item_data to btrfs_check_leaf(). With @check_item_data set to false, item data check will be skipped and fallback to old btrfs_check_leaf() behavior. So we can still get early warning if we screw up item pointers, and avoid false panic. Cc: Filipe Manana Reported-by: Lakshmipathi.G Signed-off-by: Qu Wenruo Reviewed-by: Liu Bo Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/disk-io.c | 10 ++++++++-- fs/btrfs/tree-checker.c | 27 ++++++++++++++++++++++----- fs/btrfs/tree-checker.h | 14 +++++++++++++- 3 files changed, 43 insertions(+), 8 deletions(-) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 2df5e906db08..e42673477c25 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -610,7 +610,7 @@ static int btree_readpage_end_io_hook(struct btrfs_io_bio *io_bio, * that we don't try and read the other copies of this block, just * return -EIO. */ - if (found_level == 0 && btrfs_check_leaf(root, eb)) { + if (found_level == 0 && btrfs_check_leaf_full(root, eb)) { set_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags); ret = -EIO; } @@ -3870,7 +3870,13 @@ void btrfs_mark_buffer_dirty(struct extent_buffer *buf) buf->len, fs_info->dirty_metadata_batch); #ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY - if (btrfs_header_level(buf) == 0 && btrfs_check_leaf(root, buf)) { + /* + * Since btrfs_mark_buffer_dirty() can be called with item pointer set + * but item data not updated. + * So here we should only check item pointers, not item data. + */ + if (btrfs_header_level(buf) == 0 && + btrfs_check_leaf_relaxed(root, buf)) { btrfs_print_leaf(buf); ASSERT(0); } diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index 5acdf3355a3f..ff4fa8f905d3 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -195,7 +195,8 @@ static int check_leaf_item(struct btrfs_root *root, return ret; } -int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) +static int check_leaf(struct btrfs_root *root, struct extent_buffer *leaf, + bool check_item_data) { struct btrfs_fs_info *fs_info = root->fs_info; /* No valid key type is 0, so all key should be larger than this key */ @@ -299,10 +300,15 @@ int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) return -EUCLEAN; } - /* Check if the item size and content meet other criteria */ - ret = check_leaf_item(root, leaf, &key, slot); - if (ret < 0) - return ret; + if (check_item_data) { + /* + * Check if the item size and content meet other + * criteria + */ + ret = check_leaf_item(root, leaf, &key, slot); + if (ret < 0) + return ret; + } prev_key.objectid = key.objectid; prev_key.type = key.type; @@ -312,6 +318,17 @@ int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf) return 0; } +int btrfs_check_leaf_full(struct btrfs_root *root, struct extent_buffer *leaf) +{ + return check_leaf(root, leaf, true); +} + +int btrfs_check_leaf_relaxed(struct btrfs_root *root, + struct extent_buffer *leaf) +{ + return check_leaf(root, leaf, false); +} + int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node) { unsigned long nr = btrfs_header_nritems(node); diff --git a/fs/btrfs/tree-checker.h b/fs/btrfs/tree-checker.h index 96c486e95d70..3d53e8d6fda0 100644 --- a/fs/btrfs/tree-checker.h +++ b/fs/btrfs/tree-checker.h @@ -20,7 +20,19 @@ #include "ctree.h" #include "extent_io.h" -int btrfs_check_leaf(struct btrfs_root *root, struct extent_buffer *leaf); +/* + * Comprehensive leaf checker. + * Will check not only the item pointers, but also every possible member + * in item data. + */ +int btrfs_check_leaf_full(struct btrfs_root *root, struct extent_buffer *leaf); + +/* + * Less strict leaf checker. + * Will only check item pointers, not reading item data. + */ +int btrfs_check_leaf_relaxed(struct btrfs_root *root, + struct extent_buffer *leaf); int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node); #endif -- GitLab From fe09fe216e502b17716689721a5c59d6a21277ac Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 8 Nov 2017 08:54:25 +0800 Subject: [PATCH 0197/1286] btrfs: tree-checker: Add checker for dir item commit ad7b0368f33cffe67fecd302028915926e50ef7e upstream. Add checker for dir item, for key types DIR_ITEM, DIR_INDEX and XATTR_ITEM. This checker does comprehensive checks for: 1) dir_item header and its data size Against item boundary and maximum name/xattr length. This part is mostly the same as old verify_dir_item(). 2) dir_type Against maximum file types, and against key type. Since XATTR key should only have FT_XATTR dir item, and normal dir item type should not have XATTR key. The check between key->type and dir_type is newly introduced by this patch. 3) name hash For XATTR and DIR_ITEM key, key->offset is name hash (crc32c). Check the hash of the name against the key to ensure it's correct. The name hash check is only found in btrfs-progs before this patch. Signed-off-by: Qu Wenruo Reviewed-by: Nikolay Borisov Reviewed-by: Su Yue Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 141 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index ff4fa8f905d3..b32df86de9bf 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -30,6 +30,7 @@ #include "tree-checker.h" #include "disk-io.h" #include "compression.h" +#include "hash.h" #define CORRUPT(reason, eb, root, slot) \ btrfs_crit(root->fs_info, \ @@ -175,6 +176,141 @@ static int check_csum_item(struct btrfs_root *root, struct extent_buffer *leaf, return 0; } +/* + * Customized reported for dir_item, only important new info is key->objectid, + * which represents inode number + */ +__printf(4, 5) +static void dir_item_err(const struct btrfs_root *root, + const struct extent_buffer *eb, int slot, + const char *fmt, ...) +{ + struct btrfs_key key; + struct va_format vaf; + va_list args; + + btrfs_item_key_to_cpu(eb, &key, slot); + va_start(args, fmt); + + vaf.fmt = fmt; + vaf.va = &args; + + btrfs_crit(root->fs_info, + "corrupt %s: root=%llu block=%llu slot=%d ino=%llu, %pV", + btrfs_header_level(eb) == 0 ? "leaf" : "node", root->objectid, + btrfs_header_bytenr(eb), slot, key.objectid, &vaf); + va_end(args); +} + +static int check_dir_item(struct btrfs_root *root, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + struct btrfs_dir_item *di; + u32 item_size = btrfs_item_size_nr(leaf, slot); + u32 cur = 0; + + di = btrfs_item_ptr(leaf, slot, struct btrfs_dir_item); + while (cur < item_size) { + char namebuf[max(BTRFS_NAME_LEN, XATTR_NAME_MAX)]; + u32 name_len; + u32 data_len; + u32 max_name_len; + u32 total_size; + u32 name_hash; + u8 dir_type; + + /* header itself should not cross item boundary */ + if (cur + sizeof(*di) > item_size) { + dir_item_err(root, leaf, slot, + "dir item header crosses item boundary, have %lu boundary %u", + cur + sizeof(*di), item_size); + return -EUCLEAN; + } + + /* dir type check */ + dir_type = btrfs_dir_type(leaf, di); + if (dir_type >= BTRFS_FT_MAX) { + dir_item_err(root, leaf, slot, + "invalid dir item type, have %u expect [0, %u)", + dir_type, BTRFS_FT_MAX); + return -EUCLEAN; + } + + if (key->type == BTRFS_XATTR_ITEM_KEY && + dir_type != BTRFS_FT_XATTR) { + dir_item_err(root, leaf, slot, + "invalid dir item type for XATTR key, have %u expect %u", + dir_type, BTRFS_FT_XATTR); + return -EUCLEAN; + } + if (dir_type == BTRFS_FT_XATTR && + key->type != BTRFS_XATTR_ITEM_KEY) { + dir_item_err(root, leaf, slot, + "xattr dir type found for non-XATTR key"); + return -EUCLEAN; + } + if (dir_type == BTRFS_FT_XATTR) + max_name_len = XATTR_NAME_MAX; + else + max_name_len = BTRFS_NAME_LEN; + + /* Name/data length check */ + name_len = btrfs_dir_name_len(leaf, di); + data_len = btrfs_dir_data_len(leaf, di); + if (name_len > max_name_len) { + dir_item_err(root, leaf, slot, + "dir item name len too long, have %u max %u", + name_len, max_name_len); + return -EUCLEAN; + } + if (name_len + data_len > BTRFS_MAX_XATTR_SIZE(root->fs_info)) { + dir_item_err(root, leaf, slot, + "dir item name and data len too long, have %u max %u", + name_len + data_len, + BTRFS_MAX_XATTR_SIZE(root->fs_info)); + return -EUCLEAN; + } + + if (data_len && dir_type != BTRFS_FT_XATTR) { + dir_item_err(root, leaf, slot, + "dir item with invalid data len, have %u expect 0", + data_len); + return -EUCLEAN; + } + + total_size = sizeof(*di) + name_len + data_len; + + /* header and name/data should not cross item boundary */ + if (cur + total_size > item_size) { + dir_item_err(root, leaf, slot, + "dir item data crosses item boundary, have %u boundary %u", + cur + total_size, item_size); + return -EUCLEAN; + } + + /* + * Special check for XATTR/DIR_ITEM, as key->offset is name + * hash, should match its name + */ + if (key->type == BTRFS_DIR_ITEM_KEY || + key->type == BTRFS_XATTR_ITEM_KEY) { + read_extent_buffer(leaf, namebuf, + (unsigned long)(di + 1), name_len); + name_hash = btrfs_name_hash(namebuf, name_len); + if (key->offset != name_hash) { + dir_item_err(root, leaf, slot, + "name hash mismatch with key, have 0x%016x expect 0x%016llx", + name_hash, key->offset); + return -EUCLEAN; + } + } + cur += total_size; + di = (struct btrfs_dir_item *)((void *)di + total_size); + } + return 0; +} + /* * Common point to switch the item-specific validation. */ @@ -191,6 +327,11 @@ static int check_leaf_item(struct btrfs_root *root, case BTRFS_EXTENT_CSUM_KEY: ret = check_csum_item(root, leaf, key, slot); break; + case BTRFS_DIR_ITEM_KEY: + case BTRFS_DIR_INDEX_KEY: + case BTRFS_XATTR_ITEM_KEY: + ret = check_dir_item(root, leaf, key, slot); + break; } return ret; } -- GitLab From 52ea16655aeed2571b9042c18db3eb089c37910c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 6 Dec 2017 15:18:14 +0100 Subject: [PATCH 0198/1286] btrfs: tree-checker: use %zu format string for size_t commit 7cfad65297bfe0aa2996cd72d21c898aa84436d9 upstream. The return value of sizeof() is of type size_t, so we must print it using the %z format modifier rather than %l to avoid this warning on some architectures: fs/btrfs/tree-checker.c: In function 'check_dir_item': fs/btrfs/tree-checker.c:273:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'u32' {aka 'unsigned int'} [-Werror=format=] Fixes: 005887f2e3e0 ("btrfs: tree-checker: Add checker for dir item") Signed-off-by: Arnd Bergmann Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index b32df86de9bf..9376739a4cc8 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -223,7 +223,7 @@ static int check_dir_item(struct btrfs_root *root, /* header itself should not cross item boundary */ if (cur + sizeof(*di) > item_size) { dir_item_err(root, leaf, slot, - "dir item header crosses item boundary, have %lu boundary %u", + "dir item header crosses item boundary, have %zu boundary %u", cur + sizeof(*di), item_size); return -EUCLEAN; } -- GitLab From e07e1c7561a7e087a5e512c972aa7d3e1388c057 Mon Sep 17 00:00:00 2001 From: David Sterba Date: Wed, 10 Jan 2018 15:13:07 +0100 Subject: [PATCH 0199/1286] btrfs: tree-check: reduce stack consumption in check_dir_item commit e2683fc9d219430f5b78889b50cde7f40efeba7b upstream. I've noticed that the updated item checker stack consumption increased dramatically in 542f5385e20cf97447 ("btrfs: tree-checker: Add checker for dir item") tree-checker.c:check_leaf +552 (176 -> 728) The array is 255 bytes long, dynamic allocation would slow down the sanity checks so it's more reasonable to keep it on-stack. Moving the variable to the scope of use reduces the stack usage again tree-checker.c:check_leaf -264 (728 -> 464) Reviewed-by: Josef Bacik Reviewed-by: Qu Wenruo Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index 9376739a4cc8..f7e7a455b710 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -212,7 +212,6 @@ static int check_dir_item(struct btrfs_root *root, di = btrfs_item_ptr(leaf, slot, struct btrfs_dir_item); while (cur < item_size) { - char namebuf[max(BTRFS_NAME_LEN, XATTR_NAME_MAX)]; u32 name_len; u32 data_len; u32 max_name_len; @@ -295,6 +294,8 @@ static int check_dir_item(struct btrfs_root *root, */ if (key->type == BTRFS_DIR_ITEM_KEY || key->type == BTRFS_XATTR_ITEM_KEY) { + char namebuf[max(BTRFS_NAME_LEN, XATTR_NAME_MAX)]; + read_extent_buffer(leaf, namebuf, (unsigned long)(di + 1), name_len); name_hash = btrfs_name_hash(namebuf, name_len); -- GitLab From 9f268b5cf2d6a716779dfe11f4bc02d6461db693 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Tue, 3 Jul 2018 17:10:05 +0800 Subject: [PATCH 0200/1286] btrfs: tree-checker: Verify block_group_item commit fce466eab7ac6baa9d2dcd88abcf945be3d4a089 upstream. A crafted image with invalid block group items could make free space cache code to cause panic. We could detect such invalid block group item by checking: 1) Item size Known fixed value. 2) Block group size (key.offset) We have an upper limit on block group item (10G) 3) Chunk objectid Known fixed value. 4) Type Only 4 valid type values, DATA, METADATA, SYSTEM and DATA|METADATA. No more than 1 bit set for profile type. 5) Used space No more than the block group size. This should allow btrfs to detect and refuse to mount the crafted image. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199849 Reported-by: Xu Wen Signed-off-by: Qu Wenruo Reviewed-by: Gu Jinxiang Reviewed-by: Nikolay Borisov Tested-by: Gu Jinxiang Reviewed-by: David Sterba Signed-off-by: David Sterba [bwh: Backported to 4.14: - In check_leaf_item(), pass root->fs_info to check_block_group_item() - Adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 100 ++++++++++++++++++++++++++++++++++++++++ fs/btrfs/volumes.c | 2 +- fs/btrfs/volumes.h | 2 + 3 files changed, 103 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index f7e7a455b710..cf9b10a07134 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -31,6 +31,7 @@ #include "disk-io.h" #include "compression.h" #include "hash.h" +#include "volumes.h" #define CORRUPT(reason, eb, root, slot) \ btrfs_crit(root->fs_info, \ @@ -312,6 +313,102 @@ static int check_dir_item(struct btrfs_root *root, return 0; } +__printf(4, 5) +__cold +static void block_group_err(const struct btrfs_fs_info *fs_info, + const struct extent_buffer *eb, int slot, + const char *fmt, ...) +{ + struct btrfs_key key; + struct va_format vaf; + va_list args; + + btrfs_item_key_to_cpu(eb, &key, slot); + va_start(args, fmt); + + vaf.fmt = fmt; + vaf.va = &args; + + btrfs_crit(fs_info, + "corrupt %s: root=%llu block=%llu slot=%d bg_start=%llu bg_len=%llu, %pV", + btrfs_header_level(eb) == 0 ? "leaf" : "node", + btrfs_header_owner(eb), btrfs_header_bytenr(eb), slot, + key.objectid, key.offset, &vaf); + va_end(args); +} + +static int check_block_group_item(struct btrfs_fs_info *fs_info, + struct extent_buffer *leaf, + struct btrfs_key *key, int slot) +{ + struct btrfs_block_group_item bgi; + u32 item_size = btrfs_item_size_nr(leaf, slot); + u64 flags; + u64 type; + + /* + * Here we don't really care about alignment since extent allocator can + * handle it. We care more about the size, as if one block group is + * larger than maximum size, it's must be some obvious corruption. + */ + if (key->offset > BTRFS_MAX_DATA_CHUNK_SIZE || key->offset == 0) { + block_group_err(fs_info, leaf, slot, + "invalid block group size, have %llu expect (0, %llu]", + key->offset, BTRFS_MAX_DATA_CHUNK_SIZE); + return -EUCLEAN; + } + + if (item_size != sizeof(bgi)) { + block_group_err(fs_info, leaf, slot, + "invalid item size, have %u expect %zu", + item_size, sizeof(bgi)); + return -EUCLEAN; + } + + read_extent_buffer(leaf, &bgi, btrfs_item_ptr_offset(leaf, slot), + sizeof(bgi)); + if (btrfs_block_group_chunk_objectid(&bgi) != + BTRFS_FIRST_CHUNK_TREE_OBJECTID) { + block_group_err(fs_info, leaf, slot, + "invalid block group chunk objectid, have %llu expect %llu", + btrfs_block_group_chunk_objectid(&bgi), + BTRFS_FIRST_CHUNK_TREE_OBJECTID); + return -EUCLEAN; + } + + if (btrfs_block_group_used(&bgi) > key->offset) { + block_group_err(fs_info, leaf, slot, + "invalid block group used, have %llu expect [0, %llu)", + btrfs_block_group_used(&bgi), key->offset); + return -EUCLEAN; + } + + flags = btrfs_block_group_flags(&bgi); + if (hweight64(flags & BTRFS_BLOCK_GROUP_PROFILE_MASK) > 1) { + block_group_err(fs_info, leaf, slot, +"invalid profile flags, have 0x%llx (%lu bits set) expect no more than 1 bit set", + flags & BTRFS_BLOCK_GROUP_PROFILE_MASK, + hweight64(flags & BTRFS_BLOCK_GROUP_PROFILE_MASK)); + return -EUCLEAN; + } + + type = flags & BTRFS_BLOCK_GROUP_TYPE_MASK; + if (type != BTRFS_BLOCK_GROUP_DATA && + type != BTRFS_BLOCK_GROUP_METADATA && + type != BTRFS_BLOCK_GROUP_SYSTEM && + type != (BTRFS_BLOCK_GROUP_METADATA | + BTRFS_BLOCK_GROUP_DATA)) { + block_group_err(fs_info, leaf, slot, +"invalid type, have 0x%llx (%lu bits set) expect either 0x%llx, 0x%llx, 0x%llu or 0x%llx", + type, hweight64(type), + BTRFS_BLOCK_GROUP_DATA, BTRFS_BLOCK_GROUP_METADATA, + BTRFS_BLOCK_GROUP_SYSTEM, + BTRFS_BLOCK_GROUP_METADATA | BTRFS_BLOCK_GROUP_DATA); + return -EUCLEAN; + } + return 0; +} + /* * Common point to switch the item-specific validation. */ @@ -333,6 +430,9 @@ static int check_leaf_item(struct btrfs_root *root, case BTRFS_XATTR_ITEM_KEY: ret = check_dir_item(root, leaf, key, slot); break; + case BTRFS_BLOCK_GROUP_ITEM_KEY: + ret = check_block_group_item(root->fs_info, leaf, key, slot); + break; } return ret; } diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index cfd5728e7519..9663b6aa2a56 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -4647,7 +4647,7 @@ static int __btrfs_alloc_chunk(struct btrfs_trans_handle *trans, if (type & BTRFS_BLOCK_GROUP_DATA) { max_stripe_size = SZ_1G; - max_chunk_size = 10 * max_stripe_size; + max_chunk_size = BTRFS_MAX_DATA_CHUNK_SIZE; if (!devs_max) devs_max = BTRFS_MAX_DEVS(info->chunk_root); } else if (type & BTRFS_BLOCK_GROUP_METADATA) { diff --git a/fs/btrfs/volumes.h b/fs/btrfs/volumes.h index c5dd48eb7b3d..76fb6e84f201 100644 --- a/fs/btrfs/volumes.h +++ b/fs/btrfs/volumes.h @@ -24,6 +24,8 @@ #include #include "async-thread.h" +#define BTRFS_MAX_DATA_CHUNK_SIZE (10ULL * SZ_1G) + extern struct mutex uuid_mutex; #define BTRFS_STRIPE_LEN SZ_64K -- GitLab From c0dfb99847851fb830d1e8ea7d5e0571f50c325a Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Tue, 3 Jul 2018 17:10:06 +0800 Subject: [PATCH 0201/1286] btrfs: tree-checker: Detect invalid and empty essential trees commit ba480dd4db9f1798541eb2d1c423fc95feee8d36 upstream. A crafted image has empty root tree block, which will later cause NULL pointer dereference. The following trees should never be empty: 1) Tree root Must contain at least root items for extent tree, device tree and fs tree 2) Chunk tree Or we can't even bootstrap as it contains the mapping. 3) Fs tree At least inode item for top level inode (.). 4) Device tree Dev extents for chunks 5) Extent tree Must have corresponding extent for each chunk. If any of them is empty, we are sure the fs is corrupted and no need to mount it. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199847 Reported-by: Xu Wen Signed-off-by: Qu Wenruo Tested-by: Gu Jinxiang Reviewed-by: David Sterba Signed-off-by: David Sterba [bwh: Backported to 4.14: Pass root instead of fs_info to generic_err()] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index cf9b10a07134..31756bac75b4 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -456,9 +456,22 @@ static int check_leaf(struct btrfs_root *root, struct extent_buffer *leaf, * skip this check for relocation trees. */ if (nritems == 0 && !btrfs_header_flag(leaf, BTRFS_HEADER_FLAG_RELOC)) { + u64 owner = btrfs_header_owner(leaf); struct btrfs_root *check_root; - key.objectid = btrfs_header_owner(leaf); + /* These trees must never be empty */ + if (owner == BTRFS_ROOT_TREE_OBJECTID || + owner == BTRFS_CHUNK_TREE_OBJECTID || + owner == BTRFS_EXTENT_TREE_OBJECTID || + owner == BTRFS_DEV_TREE_OBJECTID || + owner == BTRFS_FS_TREE_OBJECTID || + owner == BTRFS_DATA_RELOC_TREE_OBJECTID) { + generic_err(root, leaf, 0, + "invalid root, root %llu must never be empty", + owner); + return -EUCLEAN; + } + key.objectid = owner; key.type = BTRFS_ROOT_ITEM_KEY; key.offset = (u64)-1; -- GitLab From 34407a175a59b668a1a2bbf0d0e495d87a7777d8 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Wed, 1 Aug 2018 10:37:16 +0800 Subject: [PATCH 0202/1286] btrfs: Check that each block group has corresponding chunk at mount time commit 514c7dca85a0bf40be984dab0b477403a6db901f upstream. A crafted btrfs image with incorrect chunk<->block group mapping will trigger a lot of unexpected things as the mapping is essential. Although the problem can be caught by block group item checker added in "btrfs: tree-checker: Verify block_group_item", it's still not sufficient. A sufficiently valid block group item can pass the check added by the mentioned patch but could fail to match the existing chunk. This patch will add extra block group -> chunk mapping check, to ensure we have a completely matching (start, len, flags) chunk for each block group at mount time. Here we reuse the original helper find_first_block_group(), which is already doing the basic bg -> chunk checks, adding further checks of the start/len and type flags. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199837 Reported-by: Xu Wen Signed-off-by: Qu Wenruo Reviewed-by: Su Yue Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/extent-tree.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index fdc42eddccc2..83791d13c204 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -9828,6 +9828,8 @@ static int find_first_block_group(struct btrfs_fs_info *fs_info, int ret = 0; struct btrfs_key found_key; struct extent_buffer *leaf; + struct btrfs_block_group_item bg; + u64 flags; int slot; ret = btrfs_search_slot(NULL, root, key, path, 0, 0); @@ -9862,8 +9864,32 @@ static int find_first_block_group(struct btrfs_fs_info *fs_info, "logical %llu len %llu found bg but no related chunk", found_key.objectid, found_key.offset); ret = -ENOENT; + } else if (em->start != found_key.objectid || + em->len != found_key.offset) { + btrfs_err(fs_info, + "block group %llu len %llu mismatch with chunk %llu len %llu", + found_key.objectid, found_key.offset, + em->start, em->len); + ret = -EUCLEAN; } else { - ret = 0; + read_extent_buffer(leaf, &bg, + btrfs_item_ptr_offset(leaf, slot), + sizeof(bg)); + flags = btrfs_block_group_flags(&bg) & + BTRFS_BLOCK_GROUP_TYPE_MASK; + + if (flags != (em->map_lookup->type & + BTRFS_BLOCK_GROUP_TYPE_MASK)) { + btrfs_err(fs_info, +"block group %llu len %llu type flags 0x%llx mismatch with chunk type flags 0x%llx", + found_key.objectid, + found_key.offset, flags, + (BTRFS_BLOCK_GROUP_TYPE_MASK & + em->map_lookup->type)); + ret = -EUCLEAN; + } else { + ret = 0; + } } free_extent_map(em); goto out; -- GitLab From cf968bbccba9860eef9480ae560711fbc5cbc1b5 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Fri, 28 Sep 2018 07:59:34 +0800 Subject: [PATCH 0203/1286] btrfs: tree-checker: Check level for leaves and nodes commit f556faa46eb4e96d0d0772e74ecf66781e132f72 upstream. Although we have tree level check at tree read runtime, it's completely based on its parent level. We still need to do accurate level check to avoid invalid tree blocks sneak into kernel space. The check itself is simple, for leaf its level should always be 0. For nodes its level should be in range [1, BTRFS_MAX_LEVEL - 1]. Signed-off-by: Qu Wenruo Reviewed-by: Su Yue Reviewed-by: David Sterba Signed-off-by: David Sterba [bwh: Backported to 4.14: - Pass root instead of fs_info to generic_err() - Adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index 31756bac75b4..fa8f64119e6f 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -447,6 +447,13 @@ static int check_leaf(struct btrfs_root *root, struct extent_buffer *leaf, u32 nritems = btrfs_header_nritems(leaf); int slot; + if (btrfs_header_level(leaf) != 0) { + generic_err(root, leaf, 0, + "invalid level for leaf, have %d expect 0", + btrfs_header_level(leaf)); + return -EUCLEAN; + } + /* * Extent buffers from a relocation tree have a owner field that * corresponds to the subvolume tree they are based on. So just from an @@ -589,9 +596,16 @@ int btrfs_check_node(struct btrfs_root *root, struct extent_buffer *node) unsigned long nr = btrfs_header_nritems(node); struct btrfs_key key, next_key; int slot; + int level = btrfs_header_level(node); u64 bytenr; int ret = 0; + if (level <= 0 || level >= BTRFS_MAX_LEVEL) { + generic_err(root, node, 0, + "invalid level for node, have %d expect [1, %d]", + level, BTRFS_MAX_LEVEL - 1); + return -EUCLEAN; + } if (nr == 0 || nr > BTRFS_NODEPTRS_PER_BLOCK(root->fs_info)) { btrfs_crit(root->fs_info, "corrupt node: root=%llu block=%llu, nritems too %s, have %lu expect range [1,%u]", -- GitLab From 4b356df11ba2b44627e2fad7441e05abee46a628 Mon Sep 17 00:00:00 2001 From: Shaokun Zhang Date: Mon, 5 Nov 2018 18:49:09 +0800 Subject: [PATCH 0204/1286] btrfs: tree-checker: Fix misleading group system information commit 761333f2f50ccc887aa9957ae829300262c0d15b upstream. block_group_err shows the group system as a decimal value with a '0x' prefix, which is somewhat misleading. Fix it to print hexadecimal, as was intended. Fixes: fce466eab7ac6 ("btrfs: tree-checker: Verify block_group_item") Reviewed-by: Nikolay Borisov Reviewed-by: Qu Wenruo Signed-off-by: Shaokun Zhang Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/btrfs/tree-checker.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index fa8f64119e6f..f206aec1525d 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -399,7 +399,7 @@ static int check_block_group_item(struct btrfs_fs_info *fs_info, type != (BTRFS_BLOCK_GROUP_METADATA | BTRFS_BLOCK_GROUP_DATA)) { block_group_err(fs_info, leaf, slot, -"invalid type, have 0x%llx (%lu bits set) expect either 0x%llx, 0x%llx, 0x%llu or 0x%llx", +"invalid type, have 0x%llx (%lu bits set) expect either 0x%llx, 0x%llx, 0x%llx or 0x%llx", type, hweight64(type), BTRFS_BLOCK_GROUP_DATA, BTRFS_BLOCK_GROUP_METADATA, BTRFS_BLOCK_GROUP_SYSTEM, -- GitLab From aec6ccb3dcc1ad9b8cfe12d086430ffcce887dda Mon Sep 17 00:00:00 2001 From: Yunlei He Date: Thu, 8 Mar 2018 16:29:13 +0800 Subject: [PATCH 0205/1286] f2fs: check blkaddr more accuratly before issue a bio commit 0833721ec3658a4e9d5e58b6fa82cf9edc431e59 upstream. This patch check blkaddr more accuratly before issue a write or read bio. Signed-off-by: Yunlei He Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 2 ++ fs/f2fs/data.c | 5 +++-- fs/f2fs/f2fs.h | 1 + fs/f2fs/segment.h | 25 +++++++++++++++++++------ 4 files changed, 25 insertions(+), 8 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index 41fce930f44c..1bd4cd8c79c6 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -69,6 +69,7 @@ static struct page *__get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index, .old_blkaddr = index, .new_blkaddr = index, .encrypted_page = NULL, + .is_meta = is_meta, }; if (unlikely(!is_meta)) @@ -163,6 +164,7 @@ int ra_meta_pages(struct f2fs_sb_info *sbi, block_t start, int nrpages, .op_flags = sync ? (REQ_META | REQ_PRIO) : REQ_RAHEAD, .encrypted_page = NULL, .in_list = false, + .is_meta = (type != META_POR), }; struct blk_plug plug; diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 6fbb6d75318a..5913de3f661d 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -369,6 +369,7 @@ int f2fs_submit_page_bio(struct f2fs_io_info *fio) struct page *page = fio->encrypted_page ? fio->encrypted_page : fio->page; + verify_block_addr(fio, fio->new_blkaddr); trace_f2fs_submit_page_bio(page, fio); f2fs_trace_ios(fio, 0); @@ -413,8 +414,8 @@ int f2fs_submit_page_write(struct f2fs_io_info *fio) } if (fio->old_blkaddr != NEW_ADDR) - verify_block_addr(sbi, fio->old_blkaddr); - verify_block_addr(sbi, fio->new_blkaddr); + verify_block_addr(fio, fio->old_blkaddr); + verify_block_addr(fio, fio->new_blkaddr); bio_page = fio->encrypted_page ? fio->encrypted_page : fio->page; diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 54f8520ad7a2..aa7b033af1b0 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -910,6 +910,7 @@ struct f2fs_io_info { bool submitted; /* indicate IO submission */ int need_lock; /* indicate we need to lock cp_rwsem */ bool in_list; /* indicate fio is in io_list */ + bool is_meta; /* indicate borrow meta inode mapping or not */ enum iostat_type io_type; /* io type */ }; diff --git a/fs/f2fs/segment.h b/fs/f2fs/segment.h index 4dfb5080098f..4b635e8c91b0 100644 --- a/fs/f2fs/segment.h +++ b/fs/f2fs/segment.h @@ -53,13 +53,19 @@ ((secno) == CURSEG_I(sbi, CURSEG_COLD_NODE)->segno / \ (sbi)->segs_per_sec)) \ -#define MAIN_BLKADDR(sbi) (SM_I(sbi)->main_blkaddr) -#define SEG0_BLKADDR(sbi) (SM_I(sbi)->seg0_blkaddr) +#define MAIN_BLKADDR(sbi) \ + (SM_I(sbi) ? SM_I(sbi)->main_blkaddr : \ + le32_to_cpu(F2FS_RAW_SUPER(sbi)->main_blkaddr)) +#define SEG0_BLKADDR(sbi) \ + (SM_I(sbi) ? SM_I(sbi)->seg0_blkaddr : \ + le32_to_cpu(F2FS_RAW_SUPER(sbi)->segment0_blkaddr)) #define MAIN_SEGS(sbi) (SM_I(sbi)->main_segments) #define MAIN_SECS(sbi) ((sbi)->total_sections) -#define TOTAL_SEGS(sbi) (SM_I(sbi)->segment_count) +#define TOTAL_SEGS(sbi) \ + (SM_I(sbi) ? SM_I(sbi)->segment_count : \ + le32_to_cpu(F2FS_RAW_SUPER(sbi)->segment_count)) #define TOTAL_BLKS(sbi) (TOTAL_SEGS(sbi) << (sbi)->log_blocks_per_seg) #define MAX_BLKADDR(sbi) (SEG0_BLKADDR(sbi) + TOTAL_BLKS(sbi)) @@ -619,10 +625,17 @@ static inline void check_seg_range(struct f2fs_sb_info *sbi, unsigned int segno) f2fs_bug_on(sbi, segno > TOTAL_SEGS(sbi) - 1); } -static inline void verify_block_addr(struct f2fs_sb_info *sbi, block_t blk_addr) +static inline void verify_block_addr(struct f2fs_io_info *fio, block_t blk_addr) { - BUG_ON(blk_addr < SEG0_BLKADDR(sbi) - || blk_addr >= MAX_BLKADDR(sbi)); + struct f2fs_sb_info *sbi = fio->sbi; + + if (PAGE_TYPE_OF_BIO(fio->type) == META && + (!is_read_io(fio->op) || fio->is_meta)) + BUG_ON(blk_addr < SEG0_BLKADDR(sbi) || + blk_addr >= MAIN_BLKADDR(sbi)); + else + BUG_ON(blk_addr < MAIN_BLKADDR(sbi) || + blk_addr >= MAX_BLKADDR(sbi)); } /* -- GitLab From a8f40be69f80c7c5f969ae5cd93497dc7a764358 Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Tue, 24 Apr 2018 15:44:16 -0600 Subject: [PATCH 0206/1286] f2fs: sanity check on sit entry commit b2ca374f33bd33fd822eb871876e4888cf79dc97 upstream. syzbot hit the following crash on upstream commit 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539 (Wed Apr 18 19:48:17 2018 +0000) Merge tag 'ceph-for-4.17-rc2' of git://github.com/ceph/ceph-client syzbot dashboard link: https://syzkaller.appspot.com/bug?extid=83699adeb2d13579c31e C reproducer: https://syzkaller.appspot.com/x/repro.c?id=5805208181407744 syzkaller reproducer: https://syzkaller.appspot.com/x/repro.syz?id=6005073343676416 Raw console output: https://syzkaller.appspot.com/x/log.txt?id=6555047731134464 Kernel config: https://syzkaller.appspot.com/x/.config?id=1808800213120130118 compiler: gcc (GCC) 8.0.1 20180413 (experimental) IMPORTANT: if you fix the bug, please add the following tag to the commit: Reported-by: syzbot+83699adeb2d13579c31e@syzkaller.appspotmail.com It will help syzbot understand when the bug is fixed. See footer for details. If you forward the report, please keep this part and the footer. F2FS-fs (loop0): Magic Mismatch, valid(0xf2f52010) - read(0x0) F2FS-fs (loop0): Can't find valid F2FS filesystem in 1th superblock F2FS-fs (loop0): invalid crc value BUG: unable to handle kernel paging request at ffffed006b2a50c0 PGD 21ffee067 P4D 21ffee067 PUD 21fbeb067 PMD 0 Oops: 0000 [#1] SMP KASAN Dumping ftrace buffer: (ftrace buffer empty) Modules linked in: CPU: 0 PID: 4514 Comm: syzkaller989480 Not tainted 4.17.0-rc1+ #8 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:build_sit_entries fs/f2fs/segment.c:3653 [inline] RIP: 0010:build_segment_manager+0x7ef7/0xbf70 fs/f2fs/segment.c:3852 RSP: 0018:ffff8801b102e5b0 EFLAGS: 00010a06 RAX: 1ffff1006b2a50c0 RBX: 0000000000000004 RCX: 0000000000000001 RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffff8801ac74243e RBP: ffff8801b102f410 R08: ffff8801acbd46c0 R09: fffffbfff14d9af8 R10: fffffbfff14d9af8 R11: ffff8801acbd46c0 R12: ffff8801ac742a80 R13: ffff8801d9519100 R14: dffffc0000000000 R15: ffff880359528600 FS: 0000000001e04880(0000) GS:ffff8801dae00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffffed006b2a50c0 CR3: 00000001ac6ac000 CR4: 00000000001406f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: f2fs_fill_super+0x4095/0x7bf0 fs/f2fs/super.c:2803 mount_bdev+0x30c/0x3e0 fs/super.c:1165 f2fs_mount+0x34/0x40 fs/f2fs/super.c:3020 mount_fs+0xae/0x328 fs/super.c:1268 vfs_kern_mount.part.34+0xd4/0x4d0 fs/namespace.c:1037 vfs_kern_mount fs/namespace.c:1027 [inline] do_new_mount fs/namespace.c:2517 [inline] do_mount+0x564/0x3070 fs/namespace.c:2847 ksys_mount+0x12d/0x140 fs/namespace.c:3063 __do_sys_mount fs/namespace.c:3077 [inline] __se_sys_mount fs/namespace.c:3074 [inline] __x64_sys_mount+0xbe/0x150 fs/namespace.c:3074 do_syscall_64+0x1b1/0x800 arch/x86/entry/common.c:287 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x443d6a RSP: 002b:00007ffd312813c8 EFLAGS: 00000297 ORIG_RAX: 00000000000000a5 RAX: ffffffffffffffda RBX: 0000000020000c00 RCX: 0000000000443d6a RDX: 0000000020000000 RSI: 0000000020000100 RDI: 00007ffd312813d0 RBP: 0000000000000003 R08: 0000000020016a00 R09: 000000000000000a R10: 0000000000000000 R11: 0000000000000297 R12: 0000000000000004 R13: 0000000000402c60 R14: 0000000000000000 R15: 0000000000000000 RIP: build_sit_entries fs/f2fs/segment.c:3653 [inline] RSP: ffff8801b102e5b0 RIP: build_segment_manager+0x7ef7/0xbf70 fs/f2fs/segment.c:3852 RSP: ffff8801b102e5b0 CR2: ffffed006b2a50c0 ---[ end trace a2034989e196ff17 ]--- Reported-and-tested-by: syzbot+83699adeb2d13579c31e@syzkaller.appspotmail.com Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/segment.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index 3c7bbbae0afa..1104a6c80251 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -3304,6 +3304,15 @@ static int build_sit_entries(struct f2fs_sb_info *sbi) unsigned int old_valid_blocks; start = le32_to_cpu(segno_in_journal(journal, i)); + if (start >= MAIN_SEGS(sbi)) { + f2fs_msg(sbi->sb, KERN_ERR, + "Wrong journal entry on segno %u", + start); + set_sbi_flag(sbi, SBI_NEED_FSCK); + err = -EINVAL; + break; + } + se = &sit_i->sentries[start]; sit = sit_in_journal(journal, i); -- GitLab From e60b97231950fb5b55d2a981b080e3a6f7516a00 Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Fri, 27 Apr 2018 19:03:22 -0700 Subject: [PATCH 0207/1286] f2fs: enhance sanity_check_raw_super() to avoid potential overflow commit 0cfe75c5b011994651a4ca6d74f20aa997bfc69a upstream. In order to avoid the below overflow issue, we should have checked the boundaries in superblock before reaching out to allocation. As Linus suggested, the right place should be sanity_check_raw_super(). Dr Silvio Cesare of InfoSect reported: There are integer overflows with using the cp_payload superblock field in the f2fs filesystem potentially leading to memory corruption. include/linux/f2fs_fs.h struct f2fs_super_block { ... __le32 cp_payload; fs/f2fs/f2fs.h typedef u32 block_t; /* * should not change u32, since it is the on-disk block * address format, __le32. */ ... static inline block_t __cp_payload(struct f2fs_sb_info *sbi) { return le32_to_cpu(F2FS_RAW_SUPER(sbi)->cp_payload); } fs/f2fs/checkpoint.c block_t start_blk, orphan_blocks, i, j; ... start_blk = __start_cp_addr(sbi) + 1 + __cp_payload(sbi); orphan_blocks = __start_sum_addr(sbi) - 1 - __cp_payload(sbi); +++ integer overflows ... unsigned int cp_blks = 1 + __cp_payload(sbi); ... sbi->ckpt = kzalloc(cp_blks * blk_size, GFP_KERNEL); +++ integer overflow leading to incorrect heap allocation. int cp_payload_blks = __cp_payload(sbi); ... ckpt->cp_pack_start_sum = cpu_to_le32(1 + cp_payload_blks + orphan_blocks); +++ sign bug and integer overflow ... for (i = 1; i < 1 + cp_payload_blks; i++) +++ integer overflow ... sbi->max_orphans = (sbi->blocks_per_seg - F2FS_CP_PACKS - NR_CURSEG_TYPE - __cp_payload(sbi)) * F2FS_ORPHANS_PER_BLOCK; +++ integer overflow Reported-by: Greg KH Reported-by: Silvio Cesare Suggested-by: Linus Torvalds Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: No hot file extension support] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/super.c | 71 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 7 deletions(-) diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index 7cda685296b2..c3e1090e7c0a 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -1807,6 +1807,8 @@ static inline bool sanity_check_area_boundary(struct f2fs_sb_info *sbi, static int sanity_check_raw_super(struct f2fs_sb_info *sbi, struct buffer_head *bh) { + block_t segment_count, segs_per_sec, secs_per_zone; + block_t total_sections, blocks_per_seg; struct f2fs_super_block *raw_super = (struct f2fs_super_block *) (bh->b_data + F2FS_SUPER_OFFSET); struct super_block *sb = sbi->sb; @@ -1863,6 +1865,68 @@ static int sanity_check_raw_super(struct f2fs_sb_info *sbi, return 1; } + segment_count = le32_to_cpu(raw_super->segment_count); + segs_per_sec = le32_to_cpu(raw_super->segs_per_sec); + secs_per_zone = le32_to_cpu(raw_super->secs_per_zone); + total_sections = le32_to_cpu(raw_super->section_count); + + /* blocks_per_seg should be 512, given the above check */ + blocks_per_seg = 1 << le32_to_cpu(raw_super->log_blocks_per_seg); + + if (segment_count > F2FS_MAX_SEGMENT || + segment_count < F2FS_MIN_SEGMENTS) { + f2fs_msg(sb, KERN_INFO, + "Invalid segment count (%u)", + segment_count); + return 1; + } + + if (total_sections > segment_count || + total_sections < F2FS_MIN_SEGMENTS || + segs_per_sec > segment_count || !segs_per_sec) { + f2fs_msg(sb, KERN_INFO, + "Invalid segment/section count (%u, %u x %u)", + segment_count, total_sections, segs_per_sec); + return 1; + } + + if ((segment_count / segs_per_sec) < total_sections) { + f2fs_msg(sb, KERN_INFO, + "Small segment_count (%u < %u * %u)", + segment_count, segs_per_sec, total_sections); + return 1; + } + + if (segment_count > (le32_to_cpu(raw_super->block_count) >> 9)) { + f2fs_msg(sb, KERN_INFO, + "Wrong segment_count / block_count (%u > %u)", + segment_count, le32_to_cpu(raw_super->block_count)); + return 1; + } + + if (secs_per_zone > total_sections) { + f2fs_msg(sb, KERN_INFO, + "Wrong secs_per_zone (%u > %u)", + secs_per_zone, total_sections); + return 1; + } + if (le32_to_cpu(raw_super->extension_count) > F2FS_MAX_EXTENSION) { + f2fs_msg(sb, KERN_INFO, + "Corrupted extension count (%u > %u)", + le32_to_cpu(raw_super->extension_count), + F2FS_MAX_EXTENSION); + return 1; + } + + if (le32_to_cpu(raw_super->cp_payload) > + (blocks_per_seg - F2FS_CP_PACKS)) { + f2fs_msg(sb, KERN_INFO, + "Insane cp_payload (%u > %u)", + le32_to_cpu(raw_super->cp_payload), + blocks_per_seg - F2FS_CP_PACKS); + return 1; + } + /* check reserved ino info */ if (le32_to_cpu(raw_super->node_ino) != 1 || le32_to_cpu(raw_super->meta_ino) != 2 || @@ -1875,13 +1939,6 @@ static int sanity_check_raw_super(struct f2fs_sb_info *sbi, return 1; } - if (le32_to_cpu(raw_super->segment_count) > F2FS_MAX_SEGMENT) { - f2fs_msg(sb, KERN_INFO, - "Invalid segment count (%u)", - le32_to_cpu(raw_super->segment_count)); - return 1; - } - /* check CP/SIT/NAT/SSA/MAIN_AREA area boundary */ if (sanity_check_area_boundary(sbi, bh)) return 1; -- GitLab From 9e6c4a8557e27c4f074a47e27ce981edfb1f8b91 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Wed, 23 May 2018 22:25:08 +0800 Subject: [PATCH 0208/1286] f2fs: clean up with is_valid_blkaddr() commit 7b525dd01365c6764018e374d391c92466be1b7a upstream. - rename is_valid_blkaddr() to is_valid_meta_blkaddr() for readability. - introduce is_valid_blkaddr() for cleanup. No logic change in this patch. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 4 ++-- fs/f2fs/data.c | 18 +++++------------- fs/f2fs/f2fs.h | 9 ++++++++- fs/f2fs/file.c | 2 +- fs/f2fs/inode.c | 2 +- fs/f2fs/node.c | 5 ++--- fs/f2fs/recovery.c | 6 +++--- fs/f2fs/segment.c | 4 ++-- fs/f2fs/segment.h | 2 +- 9 files changed, 25 insertions(+), 27 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index 1bd4cd8c79c6..2b951046657e 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -118,7 +118,7 @@ struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index) return __get_meta_page(sbi, index, false); } -bool is_valid_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type) +bool is_valid_meta_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type) { switch (type) { case META_NAT: @@ -174,7 +174,7 @@ int ra_meta_pages(struct f2fs_sb_info *sbi, block_t start, int nrpages, blk_start_plug(&plug); for (; nrpages-- > 0; blkno++) { - if (!is_valid_blkaddr(sbi, blkno, type)) + if (!is_valid_meta_blkaddr(sbi, blkno, type)) goto out; switch (type) { diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 5913de3f661d..f7b2909e9c5f 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -413,7 +413,7 @@ int f2fs_submit_page_write(struct f2fs_io_info *fio) spin_unlock(&io->io_lock); } - if (fio->old_blkaddr != NEW_ADDR) + if (is_valid_blkaddr(fio->old_blkaddr)) verify_block_addr(fio, fio->old_blkaddr); verify_block_addr(fio, fio->new_blkaddr); @@ -946,7 +946,7 @@ int f2fs_map_blocks(struct inode *inode, struct f2fs_map_blocks *map, next_block: blkaddr = datablock_addr(dn.inode, dn.node_page, dn.ofs_in_node); - if (blkaddr == NEW_ADDR || blkaddr == NULL_ADDR) { + if (!is_valid_blkaddr(blkaddr)) { if (create) { if (unlikely(f2fs_cp_error(sbi))) { err = -EIO; @@ -1388,15 +1388,6 @@ static inline bool need_inplace_update(struct f2fs_io_info *fio) return need_inplace_update_policy(inode, fio); } -static inline bool valid_ipu_blkaddr(struct f2fs_io_info *fio) -{ - if (fio->old_blkaddr == NEW_ADDR) - return false; - if (fio->old_blkaddr == NULL_ADDR) - return false; - return true; -} - int do_write_data_page(struct f2fs_io_info *fio) { struct page *page = fio->page; @@ -1411,7 +1402,7 @@ int do_write_data_page(struct f2fs_io_info *fio) f2fs_lookup_extent_cache(inode, page->index, &ei)) { fio->old_blkaddr = ei.blk + page->index - ei.fofs; - if (valid_ipu_blkaddr(fio)) { + if (is_valid_blkaddr(fio->old_blkaddr)) { ipu_force = true; fio->need_lock = LOCK_DONE; goto got_it; @@ -1438,7 +1429,8 @@ int do_write_data_page(struct f2fs_io_info *fio) * If current allocation needs SSR, * it had better in-place writes for updated data. */ - if (ipu_force || (valid_ipu_blkaddr(fio) && need_inplace_update(fio))) { + if (ipu_force || (is_valid_blkaddr(fio->old_blkaddr) && + need_inplace_update(fio))) { err = encrypt_one_page(fio); if (err) goto out_writepage; diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index aa7b033af1b0..d74c77b51b71 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -2355,6 +2355,13 @@ static inline void f2fs_update_iostat(struct f2fs_sb_info *sbi, spin_unlock(&sbi->iostat_lock); } +static inline bool is_valid_blkaddr(block_t blkaddr) +{ + if (blkaddr == NEW_ADDR || blkaddr == NULL_ADDR) + return false; + return true; +} + /* * file.c */ @@ -2565,7 +2572,7 @@ void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io); struct page *grab_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index); -bool is_valid_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type); +bool is_valid_meta_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type); int ra_meta_pages(struct f2fs_sb_info *sbi, block_t start, int nrpages, int type, bool sync); void ra_meta_pages_cond(struct f2fs_sb_info *sbi, pgoff_t index); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index 6f589730782d..d368eda462bb 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -334,7 +334,7 @@ static bool __found_offset(block_t blkaddr, pgoff_t dirty, pgoff_t pgofs, switch (whence) { case SEEK_DATA: if ((blkaddr == NEW_ADDR && dirty == pgofs) || - (blkaddr != NEW_ADDR && blkaddr != NULL_ADDR)) + is_valid_blkaddr(blkaddr)) return true; break; case SEEK_HOLE: diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 259b0aa283f0..2bcbbf566f0c 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -66,7 +66,7 @@ static bool __written_first_block(struct f2fs_inode *ri) { block_t addr = le32_to_cpu(ri->i_addr[offset_in_addr(ri)]); - if (addr != NEW_ADDR && addr != NULL_ADDR) + if (is_valid_blkaddr(addr)) return true; return false; } diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 712505ec5de4..5f212fb2d62b 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -334,8 +334,7 @@ static void set_node_addr(struct f2fs_sb_info *sbi, struct node_info *ni, new_blkaddr == NULL_ADDR); f2fs_bug_on(sbi, nat_get_blkaddr(e) == NEW_ADDR && new_blkaddr == NEW_ADDR); - f2fs_bug_on(sbi, nat_get_blkaddr(e) != NEW_ADDR && - nat_get_blkaddr(e) != NULL_ADDR && + f2fs_bug_on(sbi, is_valid_blkaddr(nat_get_blkaddr(e)) && new_blkaddr == NEW_ADDR); /* increment version no as node is removed */ @@ -350,7 +349,7 @@ static void set_node_addr(struct f2fs_sb_info *sbi, struct node_info *ni, /* change address */ nat_set_blkaddr(e, new_blkaddr); - if (new_blkaddr == NEW_ADDR || new_blkaddr == NULL_ADDR) + if (!is_valid_blkaddr(new_blkaddr)) set_nat_flag(e, IS_CHECKPOINTED, false); __set_nat_cache_dirty(nm_i, e); diff --git a/fs/f2fs/recovery.c b/fs/f2fs/recovery.c index 765fadf954af..53f41ad4cbe1 100644 --- a/fs/f2fs/recovery.c +++ b/fs/f2fs/recovery.c @@ -236,7 +236,7 @@ static int find_fsync_dnodes(struct f2fs_sb_info *sbi, struct list_head *head, while (1) { struct fsync_inode_entry *entry; - if (!is_valid_blkaddr(sbi, blkaddr, META_POR)) + if (!is_valid_meta_blkaddr(sbi, blkaddr, META_POR)) return 0; page = get_tmp_page(sbi, blkaddr); @@ -479,7 +479,7 @@ static int do_recover_data(struct f2fs_sb_info *sbi, struct inode *inode, } /* dest is valid block, try to recover from src to dest */ - if (is_valid_blkaddr(sbi, dest, META_POR)) { + if (is_valid_meta_blkaddr(sbi, dest, META_POR)) { if (src == NULL_ADDR) { err = reserve_new_block(&dn); @@ -540,7 +540,7 @@ static int recover_data(struct f2fs_sb_info *sbi, struct list_head *inode_list, while (1) { struct fsync_inode_entry *entry; - if (!is_valid_blkaddr(sbi, blkaddr, META_POR)) + if (!is_valid_meta_blkaddr(sbi, blkaddr, META_POR)) break; ra_meta_pages_cond(sbi, blkaddr); diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index 1104a6c80251..483d7a869679 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -1758,7 +1758,7 @@ bool is_checkpointed_data(struct f2fs_sb_info *sbi, block_t blkaddr) struct seg_entry *se; bool is_cp = false; - if (blkaddr == NEW_ADDR || blkaddr == NULL_ADDR) + if (!is_valid_blkaddr(blkaddr)) return true; mutex_lock(&sit_i->sentry_lock); @@ -2571,7 +2571,7 @@ void f2fs_wait_on_block_writeback(struct f2fs_sb_info *sbi, block_t blkaddr) { struct page *cpage; - if (blkaddr == NEW_ADDR || blkaddr == NULL_ADDR) + if (!is_valid_blkaddr(blkaddr)) return; cpage = find_lock_page(META_MAPPING(sbi), blkaddr); diff --git a/fs/f2fs/segment.h b/fs/f2fs/segment.h index 4b635e8c91b0..f977774338c3 100644 --- a/fs/f2fs/segment.h +++ b/fs/f2fs/segment.h @@ -85,7 +85,7 @@ (GET_SEGOFF_FROM_SEG0(sbi, blk_addr) & ((sbi)->blocks_per_seg - 1)) #define GET_SEGNO(sbi, blk_addr) \ - ((((blk_addr) == NULL_ADDR) || ((blk_addr) == NEW_ADDR)) ? \ + ((!is_valid_blkaddr(blk_addr)) ? \ NULL_SEGNO : GET_L2R_SEGNO(FREE_I(sbi), \ GET_SEGNO_FROM_SEG0(sbi, blk_addr))) #define BLKS_PER_SEC(sbi) \ -- GitLab From eea715704673314769f2613b1ead310306b7de05 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Tue, 5 Jun 2018 17:44:11 +0800 Subject: [PATCH 0209/1286] f2fs: introduce and spread verify_blkaddr commit e1da7872f6eda977bd812346bf588c35e4495a1e upstream. This patch introduces verify_blkaddr to check meta/data block address with valid range to detect bug earlier. In addition, once we encounter an invalid blkaddr, notice user to run fsck to fix, and let the kernel panic. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: I skipped an earlier renaming of is_valid_meta_blkaddr() to f2fs_is_valid_meta_blkaddr()] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 11 +++++++++-- fs/f2fs/data.c | 8 ++++---- fs/f2fs/f2fs.h | 32 +++++++++++++++++++++++++++++--- fs/f2fs/file.c | 9 +++++---- fs/f2fs/inode.c | 7 ++++--- fs/f2fs/node.c | 4 ++-- fs/f2fs/recovery.c | 6 +++--- fs/f2fs/segment.c | 4 ++-- fs/f2fs/segment.h | 8 +++----- 9 files changed, 61 insertions(+), 28 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index 2b951046657e..d7bd9745e883 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -118,7 +118,8 @@ struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index) return __get_meta_page(sbi, index, false); } -bool is_valid_meta_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type) +bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, + block_t blkaddr, int type) { switch (type) { case META_NAT: @@ -138,10 +139,16 @@ bool is_valid_meta_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type) return false; break; case META_POR: + case DATA_GENERIC: if (unlikely(blkaddr >= MAX_BLKADDR(sbi) || blkaddr < MAIN_BLKADDR(sbi))) return false; break; + case META_GENERIC: + if (unlikely(blkaddr < SEG0_BLKADDR(sbi) || + blkaddr >= MAIN_BLKADDR(sbi))) + return false; + break; default: BUG(); } @@ -174,7 +181,7 @@ int ra_meta_pages(struct f2fs_sb_info *sbi, block_t start, int nrpages, blk_start_plug(&plug); for (; nrpages-- > 0; blkno++) { - if (!is_valid_meta_blkaddr(sbi, blkno, type)) + if (!f2fs_is_valid_blkaddr(sbi, blkno, type)) goto out; switch (type) { diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index f7b2909e9c5f..615878806611 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -413,7 +413,7 @@ int f2fs_submit_page_write(struct f2fs_io_info *fio) spin_unlock(&io->io_lock); } - if (is_valid_blkaddr(fio->old_blkaddr)) + if (__is_valid_data_blkaddr(fio->old_blkaddr)) verify_block_addr(fio, fio->old_blkaddr); verify_block_addr(fio, fio->new_blkaddr); @@ -946,7 +946,7 @@ int f2fs_map_blocks(struct inode *inode, struct f2fs_map_blocks *map, next_block: blkaddr = datablock_addr(dn.inode, dn.node_page, dn.ofs_in_node); - if (!is_valid_blkaddr(blkaddr)) { + if (!is_valid_data_blkaddr(sbi, blkaddr)) { if (create) { if (unlikely(f2fs_cp_error(sbi))) { err = -EIO; @@ -1402,7 +1402,7 @@ int do_write_data_page(struct f2fs_io_info *fio) f2fs_lookup_extent_cache(inode, page->index, &ei)) { fio->old_blkaddr = ei.blk + page->index - ei.fofs; - if (is_valid_blkaddr(fio->old_blkaddr)) { + if (is_valid_data_blkaddr(fio->sbi, fio->old_blkaddr)) { ipu_force = true; fio->need_lock = LOCK_DONE; goto got_it; @@ -1429,7 +1429,7 @@ int do_write_data_page(struct f2fs_io_info *fio) * If current allocation needs SSR, * it had better in-place writes for updated data. */ - if (ipu_force || (is_valid_blkaddr(fio->old_blkaddr) && + if (ipu_force || (is_valid_data_blkaddr(fio->sbi, fio->old_blkaddr) && need_inplace_update(fio))) { err = encrypt_one_page(fio); if (err) diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index d74c77b51b71..d15d79457f5c 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -162,7 +162,7 @@ struct cp_control { }; /* - * For CP/NAT/SIT/SSA readahead + * indicate meta/data type */ enum { META_CP, @@ -170,6 +170,8 @@ enum { META_SIT, META_SSA, META_POR, + DATA_GENERIC, + META_GENERIC, }; /* for the list of ino */ @@ -2355,13 +2357,36 @@ static inline void f2fs_update_iostat(struct f2fs_sb_info *sbi, spin_unlock(&sbi->iostat_lock); } -static inline bool is_valid_blkaddr(block_t blkaddr) +bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, + block_t blkaddr, int type); +void f2fs_msg(struct super_block *sb, const char *level, const char *fmt, ...); +static inline void verify_blkaddr(struct f2fs_sb_info *sbi, + block_t blkaddr, int type) +{ + if (!f2fs_is_valid_blkaddr(sbi, blkaddr, type)) { + f2fs_msg(sbi->sb, KERN_ERR, + "invalid blkaddr: %u, type: %d, run fsck to fix.", + blkaddr, type); + f2fs_bug_on(sbi, 1); + } +} + +static inline bool __is_valid_data_blkaddr(block_t blkaddr) { if (blkaddr == NEW_ADDR || blkaddr == NULL_ADDR) return false; return true; } +static inline bool is_valid_data_blkaddr(struct f2fs_sb_info *sbi, + block_t blkaddr) +{ + if (!__is_valid_data_blkaddr(blkaddr)) + return false; + verify_blkaddr(sbi, blkaddr, DATA_GENERIC); + return true; +} + /* * file.c */ @@ -2572,7 +2597,8 @@ void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io); struct page *grab_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index); -bool is_valid_meta_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type); +bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, + block_t blkaddr, int type); int ra_meta_pages(struct f2fs_sb_info *sbi, block_t start, int nrpages, int type, bool sync); void ra_meta_pages_cond(struct f2fs_sb_info *sbi, pgoff_t index); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index d368eda462bb..e9c575ef70b5 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -328,13 +328,13 @@ static pgoff_t __get_first_dirty_index(struct address_space *mapping, return pgofs; } -static bool __found_offset(block_t blkaddr, pgoff_t dirty, pgoff_t pgofs, - int whence) +static bool __found_offset(struct f2fs_sb_info *sbi, block_t blkaddr, + pgoff_t dirty, pgoff_t pgofs, int whence) { switch (whence) { case SEEK_DATA: if ((blkaddr == NEW_ADDR && dirty == pgofs) || - is_valid_blkaddr(blkaddr)) + is_valid_data_blkaddr(sbi, blkaddr)) return true; break; case SEEK_HOLE: @@ -397,7 +397,8 @@ static loff_t f2fs_seek_block(struct file *file, loff_t offset, int whence) blkaddr = datablock_addr(dn.inode, dn.node_page, dn.ofs_in_node); - if (__found_offset(blkaddr, dirty, pgofs, whence)) { + if (__found_offset(F2FS_I_SB(inode), blkaddr, dirty, + pgofs, whence)) { f2fs_put_dnode(&dn); goto found; } diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 2bcbbf566f0c..b1c0eb433841 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -62,11 +62,12 @@ static void __get_inode_rdev(struct inode *inode, struct f2fs_inode *ri) } } -static bool __written_first_block(struct f2fs_inode *ri) +static bool __written_first_block(struct f2fs_sb_info *sbi, + struct f2fs_inode *ri) { block_t addr = le32_to_cpu(ri->i_addr[offset_in_addr(ri)]); - if (is_valid_blkaddr(addr)) + if (is_valid_data_blkaddr(sbi, addr)) return true; return false; } @@ -235,7 +236,7 @@ static int do_read_inode(struct inode *inode) /* get rdev by using inline_info */ __get_inode_rdev(inode, ri); - if (__written_first_block(ri)) + if (__written_first_block(sbi, ri)) set_inode_flag(inode, FI_FIRST_BLOCK_WRITTEN); if (!need_inode_block_update(sbi, inode->i_ino)) diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 5f212fb2d62b..999814c8cbea 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -334,7 +334,7 @@ static void set_node_addr(struct f2fs_sb_info *sbi, struct node_info *ni, new_blkaddr == NULL_ADDR); f2fs_bug_on(sbi, nat_get_blkaddr(e) == NEW_ADDR && new_blkaddr == NEW_ADDR); - f2fs_bug_on(sbi, is_valid_blkaddr(nat_get_blkaddr(e)) && + f2fs_bug_on(sbi, is_valid_data_blkaddr(sbi, nat_get_blkaddr(e)) && new_blkaddr == NEW_ADDR); /* increment version no as node is removed */ @@ -349,7 +349,7 @@ static void set_node_addr(struct f2fs_sb_info *sbi, struct node_info *ni, /* change address */ nat_set_blkaddr(e, new_blkaddr); - if (!is_valid_blkaddr(new_blkaddr)) + if (!is_valid_data_blkaddr(sbi, new_blkaddr)) set_nat_flag(e, IS_CHECKPOINTED, false); __set_nat_cache_dirty(nm_i, e); diff --git a/fs/f2fs/recovery.c b/fs/f2fs/recovery.c index 53f41ad4cbe1..6ea445377767 100644 --- a/fs/f2fs/recovery.c +++ b/fs/f2fs/recovery.c @@ -236,7 +236,7 @@ static int find_fsync_dnodes(struct f2fs_sb_info *sbi, struct list_head *head, while (1) { struct fsync_inode_entry *entry; - if (!is_valid_meta_blkaddr(sbi, blkaddr, META_POR)) + if (!f2fs_is_valid_blkaddr(sbi, blkaddr, META_POR)) return 0; page = get_tmp_page(sbi, blkaddr); @@ -479,7 +479,7 @@ static int do_recover_data(struct f2fs_sb_info *sbi, struct inode *inode, } /* dest is valid block, try to recover from src to dest */ - if (is_valid_meta_blkaddr(sbi, dest, META_POR)) { + if (f2fs_is_valid_blkaddr(sbi, dest, META_POR)) { if (src == NULL_ADDR) { err = reserve_new_block(&dn); @@ -540,7 +540,7 @@ static int recover_data(struct f2fs_sb_info *sbi, struct list_head *inode_list, while (1) { struct fsync_inode_entry *entry; - if (!is_valid_meta_blkaddr(sbi, blkaddr, META_POR)) + if (!f2fs_is_valid_blkaddr(sbi, blkaddr, META_POR)) break; ra_meta_pages_cond(sbi, blkaddr); diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index 483d7a869679..5c698757e116 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -1758,7 +1758,7 @@ bool is_checkpointed_data(struct f2fs_sb_info *sbi, block_t blkaddr) struct seg_entry *se; bool is_cp = false; - if (!is_valid_blkaddr(blkaddr)) + if (!is_valid_data_blkaddr(sbi, blkaddr)) return true; mutex_lock(&sit_i->sentry_lock); @@ -2571,7 +2571,7 @@ void f2fs_wait_on_block_writeback(struct f2fs_sb_info *sbi, block_t blkaddr) { struct page *cpage; - if (!is_valid_blkaddr(blkaddr)) + if (!is_valid_data_blkaddr(sbi, blkaddr)) return; cpage = find_lock_page(META_MAPPING(sbi), blkaddr); diff --git a/fs/f2fs/segment.h b/fs/f2fs/segment.h index f977774338c3..dd8f977fc273 100644 --- a/fs/f2fs/segment.h +++ b/fs/f2fs/segment.h @@ -85,7 +85,7 @@ (GET_SEGOFF_FROM_SEG0(sbi, blk_addr) & ((sbi)->blocks_per_seg - 1)) #define GET_SEGNO(sbi, blk_addr) \ - ((!is_valid_blkaddr(blk_addr)) ? \ + ((!is_valid_data_blkaddr(sbi, blk_addr)) ? \ NULL_SEGNO : GET_L2R_SEGNO(FREE_I(sbi), \ GET_SEGNO_FROM_SEG0(sbi, blk_addr))) #define BLKS_PER_SEC(sbi) \ @@ -631,11 +631,9 @@ static inline void verify_block_addr(struct f2fs_io_info *fio, block_t blk_addr) if (PAGE_TYPE_OF_BIO(fio->type) == META && (!is_read_io(fio->op) || fio->is_meta)) - BUG_ON(blk_addr < SEG0_BLKADDR(sbi) || - blk_addr >= MAIN_BLKADDR(sbi)); + verify_blkaddr(sbi, blk_addr, META_GENERIC); else - BUG_ON(blk_addr < MAIN_BLKADDR(sbi) || - blk_addr >= MAX_BLKADDR(sbi)); + verify_blkaddr(sbi, blk_addr, DATA_GENERIC); } /* -- GitLab From f3d6361a96a455c8ba12226a04efa67a0ada4966 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Sat, 23 Jun 2018 00:12:36 +0800 Subject: [PATCH 0210/1286] f2fs: fix to do sanity check with secs_per_zone commit 42bf546c1fe3f3654bdf914e977acbc2b80a5be5 upstream. As Wen Xu reported in below link: https://bugzilla.kernel.org/show_bug.cgi?id=200183 - Overview Divide zero in reset_curseg() when mounting a crafted f2fs image - Reproduce - Kernel message [ 588.281510] divide error: 0000 [#1] SMP KASAN PTI [ 588.282701] CPU: 0 PID: 1293 Comm: mount Not tainted 4.18.0-rc1+ #4 [ 588.284000] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 588.286178] RIP: 0010:reset_curseg+0x94/0x1a0 [ 588.298166] RSP: 0018:ffff8801e88d7940 EFLAGS: 00010246 [ 588.299360] RAX: 0000000000000014 RBX: ffff8801e1d46d00 RCX: ffffffffb88bf60b [ 588.300809] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff8801e1d46d64 [ 588.305272] R13: 0000000000000000 R14: 0000000000000014 R15: 0000000000000000 [ 588.306822] FS: 00007fad85008840(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 588.308456] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 588.309623] CR2: 0000000001705078 CR3: 00000001f30f8000 CR4: 00000000000006f0 [ 588.311085] Call Trace: [ 588.311637] f2fs_build_segment_manager+0x103f/0x3410 [ 588.316136] ? f2fs_commit_super+0x1b0/0x1b0 [ 588.317031] ? set_blocksize+0x90/0x140 [ 588.319473] f2fs_mount+0x15/0x20 [ 588.320166] mount_fs+0x60/0x1a0 [ 588.320847] ? alloc_vfsmnt+0x309/0x360 [ 588.321647] vfs_kern_mount+0x6b/0x1a0 [ 588.322432] do_mount+0x34a/0x18c0 [ 588.323175] ? strndup_user+0x46/0x70 [ 588.323937] ? copy_mount_string+0x20/0x20 [ 588.324793] ? memcg_kmem_put_cache+0x1b/0xa0 [ 588.325702] ? kasan_check_write+0x14/0x20 [ 588.326562] ? _copy_from_user+0x6a/0x90 [ 588.327375] ? memdup_user+0x42/0x60 [ 588.328118] ksys_mount+0x83/0xd0 [ 588.328808] __x64_sys_mount+0x67/0x80 [ 588.329607] do_syscall_64+0x78/0x170 [ 588.330400] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 588.331461] RIP: 0033:0x7fad848e8b9a [ 588.336022] RSP: 002b:00007ffd7c5b6be8 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5 [ 588.337547] RAX: ffffffffffffffda RBX: 00000000016f8030 RCX: 00007fad848e8b9a [ 588.338999] RDX: 00000000016f8210 RSI: 00000000016f9f30 RDI: 0000000001700ec0 [ 588.340442] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000013 [ 588.341887] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 0000000001700ec0 [ 588.343341] R13: 00000000016f8210 R14: 0000000000000000 R15: 0000000000000003 [ 588.354891] ---[ end trace 4ce02f25ff7d3df5 ]--- [ 588.355862] RIP: 0010:reset_curseg+0x94/0x1a0 [ 588.360742] RSP: 0018:ffff8801e88d7940 EFLAGS: 00010246 [ 588.361812] RAX: 0000000000000014 RBX: ffff8801e1d46d00 RCX: ffffffffb88bf60b [ 588.363485] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff8801e1d46d64 [ 588.365213] RBP: ffff8801e88d7968 R08: ffffed003c32266f R09: ffffed003c32266f [ 588.366661] R10: 0000000000000001 R11: ffffed003c32266e R12: ffff8801f0337700 [ 588.368110] R13: 0000000000000000 R14: 0000000000000014 R15: 0000000000000000 [ 588.370057] FS: 00007fad85008840(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 588.372099] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 588.373291] CR2: 0000000001705078 CR3: 00000001f30f8000 CR4: 00000000000006f0 - Location https://elixir.bootlin.com/linux/latest/source/fs/f2fs/segment.c#L2147 curseg->zone = GET_ZONE_FROM_SEG(sbi, curseg->segno); If secs_per_zone is corrupted due to fuzzing test, it will cause divide zero operation when using GET_ZONE_FROM_SEG macro, so we should do more sanity check with secs_per_zone during mount to avoid this issue. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/super.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index c3e1090e7c0a..084ff9c82a37 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -1904,9 +1904,9 @@ static int sanity_check_raw_super(struct f2fs_sb_info *sbi, return 1; } - if (secs_per_zone > total_sections) { + if (secs_per_zone > total_sections || !secs_per_zone) { f2fs_msg(sb, KERN_INFO, - "Wrong secs_per_zone (%u > %u)", + "Wrong secs_per_zone / total_sections (%u, %u)", secs_per_zone, total_sections); return 1; } -- GitLab From 2598fc56ed65f69e303ccee6d5fe756a56f87779 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Thu, 29 Nov 2018 19:17:34 +0000 Subject: [PATCH 0211/1286] f2fs: Add sanity_check_inode() function This was done as part of commit 5d64600d4f33 "f2fs: avoid bug_on on corrupted inode" upstream, but the specific check that commit added is not applicable to 4.14. Cc: Jaegeuk Kim Cc: Chao Yu Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/inode.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index b1c0eb433841..917a6c3d5649 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -180,6 +180,13 @@ void f2fs_inode_chksum_set(struct f2fs_sb_info *sbi, struct page *page) ri->i_inode_checksum = cpu_to_le32(f2fs_inode_chksum(sbi, page)); } +static bool sanity_check_inode(struct inode *inode) +{ + struct f2fs_sb_info *sbi = F2FS_I_SB(inode); + + return true; +} + static int do_read_inode(struct inode *inode) { struct f2fs_sb_info *sbi = F2FS_I_SB(inode); @@ -281,6 +288,10 @@ struct inode *f2fs_iget(struct super_block *sb, unsigned long ino) ret = do_read_inode(inode); if (ret) goto bad_inode; + if (!sanity_check_inode(inode)) { + ret = -EINVAL; + goto bad_inode; + } make_now: if (ino == F2FS_NODE_INO(sbi)) { inode->i_mapping->a_ops = &f2fs_node_aops; -- GitLab From 0081c90ebacebb3a82d0d24bf0f42273ce2d902e Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Mon, 25 Jun 2018 23:29:49 +0800 Subject: [PATCH 0212/1286] f2fs: fix to do sanity check with extra_attr feature commit 76d56d4ab4f2a9e4f085c7d77172194ddaccf7d2 upstream. If FI_EXTRA_ATTR is set in inode by fuzzing, inode.i_addr[0] will be parsed as inode.i_extra_isize, then in __recover_inline_status, inline data address will beyond boundary of page, result in accessing invalid memory. So in this condition, during reading inode page, let's do sanity check with EXTRA_ATTR feature of fs and extra_attr bit of inode, if they're inconsistent, deny to load this inode. - Overview Out-of-bound access in f2fs_iget() when mounting a corrupted f2fs image - Reproduce The following message will be got in KASAN build of 4.18 upstream kernel. [ 819.392227] ================================================================== [ 819.393901] BUG: KASAN: slab-out-of-bounds in f2fs_iget+0x736/0x1530 [ 819.395329] Read of size 4 at addr ffff8801f099c968 by task mount/1292 [ 819.397079] CPU: 1 PID: 1292 Comm: mount Not tainted 4.18.0-rc1+ #4 [ 819.397082] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 819.397088] Call Trace: [ 819.397124] dump_stack+0x7b/0xb5 [ 819.397154] print_address_description+0x70/0x290 [ 819.397159] kasan_report+0x291/0x390 [ 819.397163] ? f2fs_iget+0x736/0x1530 [ 819.397176] check_memory_region+0x139/0x190 [ 819.397182] __asan_loadN+0xf/0x20 [ 819.397185] f2fs_iget+0x736/0x1530 [ 819.397197] f2fs_fill_super+0x1b4f/0x2b40 [ 819.397202] ? f2fs_fill_super+0x1b4f/0x2b40 [ 819.397208] ? f2fs_commit_super+0x1b0/0x1b0 [ 819.397227] ? set_blocksize+0x90/0x140 [ 819.397241] mount_bdev+0x1c5/0x210 [ 819.397245] ? f2fs_commit_super+0x1b0/0x1b0 [ 819.397252] f2fs_mount+0x15/0x20 [ 819.397256] mount_fs+0x60/0x1a0 [ 819.397267] ? alloc_vfsmnt+0x309/0x360 [ 819.397272] vfs_kern_mount+0x6b/0x1a0 [ 819.397282] do_mount+0x34a/0x18c0 [ 819.397300] ? lockref_put_or_lock+0xcf/0x160 [ 819.397306] ? copy_mount_string+0x20/0x20 [ 819.397318] ? memcg_kmem_put_cache+0x1b/0xa0 [ 819.397324] ? kasan_check_write+0x14/0x20 [ 819.397334] ? _copy_from_user+0x6a/0x90 [ 819.397353] ? memdup_user+0x42/0x60 [ 819.397359] ksys_mount+0x83/0xd0 [ 819.397365] __x64_sys_mount+0x67/0x80 [ 819.397388] do_syscall_64+0x78/0x170 [ 819.397403] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 819.397422] RIP: 0033:0x7f54c667cb9a [ 819.397424] Code: 48 8b 0d 01 c3 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ce c2 2b 00 f7 d8 64 89 01 48 [ 819.397483] RSP: 002b:00007ffd8f46cd08 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5 [ 819.397496] RAX: ffffffffffffffda RBX: 0000000000dfa030 RCX: 00007f54c667cb9a [ 819.397498] RDX: 0000000000dfa210 RSI: 0000000000dfbf30 RDI: 0000000000e02ec0 [ 819.397501] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000013 [ 819.397503] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 0000000000e02ec0 [ 819.397505] R13: 0000000000dfa210 R14: 0000000000000000 R15: 0000000000000003 [ 819.397866] Allocated by task 139: [ 819.398702] save_stack+0x46/0xd0 [ 819.398705] kasan_kmalloc+0xad/0xe0 [ 819.398709] kasan_slab_alloc+0x11/0x20 [ 819.398713] kmem_cache_alloc+0xd1/0x1e0 [ 819.398717] dup_fd+0x50/0x4c0 [ 819.398740] copy_process.part.37+0xbed/0x32e0 [ 819.398744] _do_fork+0x16e/0x590 [ 819.398748] __x64_sys_clone+0x69/0x80 [ 819.398752] do_syscall_64+0x78/0x170 [ 819.398756] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 819.399097] Freed by task 159: [ 819.399743] save_stack+0x46/0xd0 [ 819.399747] __kasan_slab_free+0x13c/0x1a0 [ 819.399750] kasan_slab_free+0xe/0x10 [ 819.399754] kmem_cache_free+0x89/0x1e0 [ 819.399757] put_files_struct+0x132/0x150 [ 819.399761] exit_files+0x62/0x70 [ 819.399766] do_exit+0x47b/0x1390 [ 819.399770] do_group_exit+0x86/0x130 [ 819.399774] __x64_sys_exit_group+0x2c/0x30 [ 819.399778] do_syscall_64+0x78/0x170 [ 819.399782] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 819.400115] The buggy address belongs to the object at ffff8801f099c680 which belongs to the cache files_cache of size 704 [ 819.403234] The buggy address is located 40 bytes to the right of 704-byte region [ffff8801f099c680, ffff8801f099c940) [ 819.405689] The buggy address belongs to the page: [ 819.406709] page:ffffea0007c26700 count:1 mapcount:0 mapping:ffff8801f69a3340 index:0xffff8801f099d380 compound_mapcount: 0 [ 819.408984] flags: 0x2ffff0000008100(slab|head) [ 819.409932] raw: 02ffff0000008100 ffffea00077fb600 0000000200000002 ffff8801f69a3340 [ 819.411514] raw: ffff8801f099d380 0000000080130000 00000001ffffffff 0000000000000000 [ 819.413073] page dumped because: kasan: bad access detected [ 819.414539] Memory state around the buggy address: [ 819.415521] ffff8801f099c800: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 819.416981] ffff8801f099c880: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 819.418454] >ffff8801f099c900: fb fb fb fb fb fb fb fb fc fc fc fc fc fc fc fc [ 819.419921] ^ [ 819.421265] ffff8801f099c980: fc fc fc fc fc fc fc fc fb fb fb fb fb fb fb fb [ 819.422745] ffff8801f099ca00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 819.424206] ================================================================== [ 819.425668] Disabling lock debugging due to kernel taint [ 819.457463] F2FS-fs (loop0): Mounted with checkpoint version = 3 The kernel still mounts the image. If you run the following program on the mounted folder mnt, (poc.c) static void activity(char *mpoint) { char *foo_bar_baz; int err; static int buf[8192]; memset(buf, 0, sizeof(buf)); err = asprintf(&foo_bar_baz, "%s/foo/bar/baz", mpoint); int fd = open(foo_bar_baz, O_RDONLY, 0); if (fd >= 0) { read(fd, (char *)buf, 11); close(fd); } } int main(int argc, char *argv[]) { activity(argv[1]); return 0; } You can get kernel crash: [ 819.457463] F2FS-fs (loop0): Mounted with checkpoint version = 3 [ 918.028501] BUG: unable to handle kernel paging request at ffffed0048000d82 [ 918.044020] PGD 23ffee067 P4D 23ffee067 PUD 23fbef067 PMD 0 [ 918.045207] Oops: 0000 [#1] SMP KASAN PTI [ 918.046048] CPU: 0 PID: 1309 Comm: poc Tainted: G B 4.18.0-rc1+ #4 [ 918.047573] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 918.049552] RIP: 0010:check_memory_region+0x5e/0x190 [ 918.050565] Code: f8 49 c1 e8 03 49 89 db 49 c1 eb 03 4d 01 cb 4d 01 c1 4d 8d 63 01 4c 89 c8 4d 89 e2 4d 29 ca 49 83 fa 10 7f 3d 4d 85 d2 74 32 <41> 80 39 00 75 23 48 b8 01 00 00 00 00 fc ff df 4d 01 d1 49 01 c0 [ 918.054322] RSP: 0018:ffff8801e3a1f258 EFLAGS: 00010202 [ 918.055400] RAX: ffffed0048000d82 RBX: ffff880240006c11 RCX: ffffffffb8867d14 [ 918.056832] RDX: 0000000000000000 RSI: 0000000000000002 RDI: ffff880240006c10 [ 918.058253] RBP: ffff8801e3a1f268 R08: 1ffff10048000d82 R09: ffffed0048000d82 [ 918.059717] R10: 0000000000000001 R11: ffffed0048000d82 R12: ffffed0048000d83 [ 918.061159] R13: ffff8801e3a1f390 R14: 0000000000000000 R15: ffff880240006c08 [ 918.062614] FS: 00007fac9732c700(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 918.064246] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 918.065412] CR2: ffffed0048000d82 CR3: 00000001df77a000 CR4: 00000000000006f0 [ 918.066882] Call Trace: [ 918.067410] __asan_loadN+0xf/0x20 [ 918.068149] f2fs_find_target_dentry+0xf4/0x270 [ 918.069083] ? __get_node_page+0x331/0x5b0 [ 918.069925] f2fs_find_in_inline_dir+0x24b/0x310 [ 918.070881] ? f2fs_recover_inline_data+0x4c0/0x4c0 [ 918.071905] ? unwind_next_frame.part.5+0x34f/0x490 [ 918.072901] ? unwind_dump+0x290/0x290 [ 918.073695] ? is_bpf_text_address+0xe/0x20 [ 918.074566] __f2fs_find_entry+0x599/0x670 [ 918.075408] ? kasan_unpoison_shadow+0x36/0x50 [ 918.076315] ? kasan_kmalloc+0xad/0xe0 [ 918.077100] ? memcg_kmem_put_cache+0x55/0xa0 [ 918.077998] ? f2fs_find_target_dentry+0x270/0x270 [ 918.079006] ? d_set_d_op+0x30/0x100 [ 918.079749] ? __d_lookup_rcu+0x69/0x2e0 [ 918.080556] ? __d_alloc+0x275/0x450 [ 918.081297] ? kasan_check_write+0x14/0x20 [ 918.082135] ? memset+0x31/0x40 [ 918.082820] ? fscrypt_setup_filename+0x1ec/0x4c0 [ 918.083782] ? d_alloc_parallel+0x5bb/0x8c0 [ 918.084640] f2fs_find_entry+0xe9/0x110 [ 918.085432] ? __f2fs_find_entry+0x670/0x670 [ 918.086308] ? kasan_check_write+0x14/0x20 [ 918.087163] f2fs_lookup+0x297/0x590 [ 918.087902] ? f2fs_link+0x2b0/0x2b0 [ 918.088646] ? legitimize_path.isra.29+0x61/0xa0 [ 918.089589] __lookup_slow+0x12e/0x240 [ 918.090371] ? may_delete+0x2b0/0x2b0 [ 918.091123] ? __nd_alloc_stack+0xa0/0xa0 [ 918.091944] lookup_slow+0x44/0x60 [ 918.092642] walk_component+0x3ee/0xa40 [ 918.093428] ? is_bpf_text_address+0xe/0x20 [ 918.094283] ? pick_link+0x3e0/0x3e0 [ 918.095047] ? in_group_p+0xa5/0xe0 [ 918.095771] ? generic_permission+0x53/0x1e0 [ 918.096666] ? security_inode_permission+0x1d/0x70 [ 918.097646] ? inode_permission+0x7a/0x1f0 [ 918.098497] link_path_walk+0x2a2/0x7b0 [ 918.099298] ? apparmor_capget+0x3d0/0x3d0 [ 918.100140] ? walk_component+0xa40/0xa40 [ 918.100958] ? path_init+0x2e6/0x580 [ 918.101695] path_openat+0x1bb/0x2160 [ 918.102471] ? __save_stack_trace+0x92/0x100 [ 918.103352] ? save_stack+0xb5/0xd0 [ 918.104070] ? vfs_unlink+0x250/0x250 [ 918.104822] ? save_stack+0x46/0xd0 [ 918.105538] ? kasan_slab_alloc+0x11/0x20 [ 918.106370] ? kmem_cache_alloc+0xd1/0x1e0 [ 918.107213] ? getname_flags+0x76/0x2c0 [ 918.107997] ? getname+0x12/0x20 [ 918.108677] ? do_sys_open+0x14b/0x2c0 [ 918.109450] ? __x64_sys_open+0x4c/0x60 [ 918.110255] ? do_syscall_64+0x78/0x170 [ 918.111083] ? entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 918.112148] ? entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 918.113204] ? f2fs_empty_inline_dir+0x1e0/0x1e0 [ 918.114150] ? timespec64_trunc+0x5c/0x90 [ 918.114993] ? wb_io_lists_depopulated+0x1a/0xc0 [ 918.115937] ? inode_io_list_move_locked+0x102/0x110 [ 918.116949] do_filp_open+0x12b/0x1d0 [ 918.117709] ? may_open_dev+0x50/0x50 [ 918.118475] ? kasan_kmalloc+0xad/0xe0 [ 918.119246] do_sys_open+0x17c/0x2c0 [ 918.119983] ? do_sys_open+0x17c/0x2c0 [ 918.120751] ? filp_open+0x60/0x60 [ 918.121463] ? task_work_run+0x4d/0xf0 [ 918.122237] __x64_sys_open+0x4c/0x60 [ 918.123001] do_syscall_64+0x78/0x170 [ 918.123759] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 918.124802] RIP: 0033:0x7fac96e3e040 [ 918.125537] Code: 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 83 3d 09 27 2d 00 00 75 10 b8 02 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 31 c3 48 83 ec 08 e8 7e e0 01 00 48 89 04 24 [ 918.129341] RSP: 002b:00007fff1b37f848 EFLAGS: 00000246 ORIG_RAX: 0000000000000002 [ 918.130870] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fac96e3e040 [ 918.132295] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 000000000122d080 [ 918.133748] RBP: 00007fff1b37f9b0 R08: 00007fac9710bbd8 R09: 0000000000000001 [ 918.135209] R10: 000000000000069d R11: 0000000000000246 R12: 0000000000400c20 [ 918.136650] R13: 00007fff1b37fab0 R14: 0000000000000000 R15: 0000000000000000 [ 918.138093] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mac_hid i2c_piix4 soundcore ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 multipath linear 8139too crct10dif_pclmul crc32_pclmul qxl drm_kms_helper syscopyarea aesni_intel sysfillrect sysimgblt fb_sys_fops ttm drm aes_x86_64 crypto_simd cryptd 8139cp glue_helper mii pata_acpi floppy [ 918.147924] CR2: ffffed0048000d82 [ 918.148619] ---[ end trace 4ce02f25ff7d3df5 ]--- [ 918.149563] RIP: 0010:check_memory_region+0x5e/0x190 [ 918.150576] Code: f8 49 c1 e8 03 49 89 db 49 c1 eb 03 4d 01 cb 4d 01 c1 4d 8d 63 01 4c 89 c8 4d 89 e2 4d 29 ca 49 83 fa 10 7f 3d 4d 85 d2 74 32 <41> 80 39 00 75 23 48 b8 01 00 00 00 00 fc ff df 4d 01 d1 49 01 c0 [ 918.154360] RSP: 0018:ffff8801e3a1f258 EFLAGS: 00010202 [ 918.155411] RAX: ffffed0048000d82 RBX: ffff880240006c11 RCX: ffffffffb8867d14 [ 918.156833] RDX: 0000000000000000 RSI: 0000000000000002 RDI: ffff880240006c10 [ 918.158257] RBP: ffff8801e3a1f268 R08: 1ffff10048000d82 R09: ffffed0048000d82 [ 918.159722] R10: 0000000000000001 R11: ffffed0048000d82 R12: ffffed0048000d83 [ 918.161149] R13: ffff8801e3a1f390 R14: 0000000000000000 R15: ffff880240006c08 [ 918.162587] FS: 00007fac9732c700(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 918.164203] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 918.165356] CR2: ffffed0048000d82 CR3: 00000001df77a000 CR4: 00000000000006f0 Reported-by: Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/inode.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 917a6c3d5649..428d502f23e8 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -184,6 +184,15 @@ static bool sanity_check_inode(struct inode *inode) { struct f2fs_sb_info *sbi = F2FS_I_SB(inode); + if (f2fs_has_extra_attr(inode) && + !f2fs_sb_has_extra_attr(sbi->sb)) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "%s: inode (ino=%lx) is with extra_attr, " + "but extra_attr feature is off", + __func__, inode->i_ino); + return false; + } return true; } @@ -233,6 +242,11 @@ static int do_read_inode(struct inode *inode) get_inline_info(inode, ri); + if (!sanity_check_inode(inode)) { + f2fs_put_page(node_page, 1); + return -EINVAL; + } + fi->i_extra_isize = f2fs_has_extra_attr(inode) ? le16_to_cpu(ri->i_extra_isize) : 0; @@ -288,10 +302,6 @@ struct inode *f2fs_iget(struct super_block *sb, unsigned long ino) ret = do_read_inode(inode); if (ret) goto bad_inode; - if (!sanity_check_inode(inode)) { - ret = -EINVAL; - goto bad_inode; - } make_now: if (ino == F2FS_NODE_INO(sbi)) { inode->i_mapping->a_ops = &f2fs_node_aops; -- GitLab From f9cf5462b51d98026275cc51437fc531e808b64a Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Wed, 27 Jun 2018 18:05:54 +0800 Subject: [PATCH 0213/1286] f2fs: fix to do sanity check with user_block_count commit 9dc956b2c8523aed39d1e6508438be9fea28c8fc upstream. This patch fixs to do sanity check with user_block_count. - Overview Divide zero in utilization when mount() a corrupted f2fs image - Reproduce (4.18 upstream kernel) - Kernel message [ 564.099503] F2FS-fs (loop0): invalid crc value [ 564.101991] divide error: 0000 [#1] SMP KASAN PTI [ 564.103103] CPU: 1 PID: 1298 Comm: f2fs_discard-7: Not tainted 4.18.0-rc1+ #4 [ 564.104584] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 564.106624] RIP: 0010:issue_discard_thread+0x248/0x5c0 [ 564.107692] Code: ff ff 48 8b bd e8 fe ff ff 41 8b 9d 4c 04 00 00 e8 cd b8 ad ff 41 8b 85 50 04 00 00 31 d2 48 8d 04 80 48 8d 04 80 48 c1 e0 02 <48> f7 f3 83 f8 50 7e 16 41 c7 86 7c ff ff ff 01 00 00 00 41 c7 86 [ 564.111686] RSP: 0018:ffff8801f3117dc0 EFLAGS: 00010206 [ 564.112775] RAX: 0000000000000384 RBX: 0000000000000000 RCX: ffffffffb88c1e03 [ 564.114250] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff8801e3aa4850 [ 564.115706] RBP: ffff8801f3117f00 R08: 1ffffffff751a1d0 R09: fffffbfff751a1d0 [ 564.117177] R10: 0000000000000001 R11: fffffbfff751a1d0 R12: 00000000fffffffc [ 564.118634] R13: ffff8801e3aa4400 R14: ffff8801f3117ed8 R15: ffff8801e2050000 [ 564.120094] FS: 0000000000000000(0000) GS:ffff8801f6f00000(0000) knlGS:0000000000000000 [ 564.121748] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 564.122923] CR2: 000000000202b078 CR3: 00000001f11ac000 CR4: 00000000000006e0 [ 564.124383] Call Trace: [ 564.124924] ? __issue_discard_cmd+0x480/0x480 [ 564.125882] ? __sched_text_start+0x8/0x8 [ 564.126756] ? __kthread_parkme+0xcb/0x100 [ 564.127620] ? kthread_blkcg+0x70/0x70 [ 564.128412] kthread+0x180/0x1d0 [ 564.129105] ? __issue_discard_cmd+0x480/0x480 [ 564.130029] ? kthread_associate_blkcg+0x150/0x150 [ 564.131033] ret_from_fork+0x35/0x40 [ 564.131794] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mac_hid i2c_piix4 soundcore ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 multipath linear 8139too crct10dif_pclmul crc32_pclmul qxl drm_kms_helper syscopyarea aesni_intel sysfillrect sysimgblt fb_sys_fops ttm drm aes_x86_64 crypto_simd cryptd 8139cp glue_helper mii pata_acpi floppy [ 564.141798] ---[ end trace 4ce02f25ff7d3df5 ]--- [ 564.142773] RIP: 0010:issue_discard_thread+0x248/0x5c0 [ 564.143885] Code: ff ff 48 8b bd e8 fe ff ff 41 8b 9d 4c 04 00 00 e8 cd b8 ad ff 41 8b 85 50 04 00 00 31 d2 48 8d 04 80 48 8d 04 80 48 c1 e0 02 <48> f7 f3 83 f8 50 7e 16 41 c7 86 7c ff ff ff 01 00 00 00 41 c7 86 [ 564.147776] RSP: 0018:ffff8801f3117dc0 EFLAGS: 00010206 [ 564.148856] RAX: 0000000000000384 RBX: 0000000000000000 RCX: ffffffffb88c1e03 [ 564.150424] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff8801e3aa4850 [ 564.151906] RBP: ffff8801f3117f00 R08: 1ffffffff751a1d0 R09: fffffbfff751a1d0 [ 564.153463] R10: 0000000000000001 R11: fffffbfff751a1d0 R12: 00000000fffffffc [ 564.154915] R13: ffff8801e3aa4400 R14: ffff8801f3117ed8 R15: ffff8801e2050000 [ 564.156405] FS: 0000000000000000(0000) GS:ffff8801f6f00000(0000) knlGS:0000000000000000 [ 564.158070] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 564.159279] CR2: 000000000202b078 CR3: 00000001f11ac000 CR4: 00000000000006e0 [ 564.161043] ================================================================== [ 564.162587] BUG: KASAN: stack-out-of-bounds in from_kuid_munged+0x1d/0x50 [ 564.163994] Read of size 4 at addr ffff8801f3117c84 by task f2fs_discard-7:/1298 [ 564.165852] CPU: 1 PID: 1298 Comm: f2fs_discard-7: Tainted: G D 4.18.0-rc1+ #4 [ 564.167593] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 564.169522] Call Trace: [ 564.170057] dump_stack+0x7b/0xb5 [ 564.170778] print_address_description+0x70/0x290 [ 564.171765] kasan_report+0x291/0x390 [ 564.172540] ? from_kuid_munged+0x1d/0x50 [ 564.173408] __asan_load4+0x78/0x80 [ 564.174148] from_kuid_munged+0x1d/0x50 [ 564.174962] do_notify_parent+0x1f5/0x4f0 [ 564.175808] ? send_sigqueue+0x390/0x390 [ 564.176639] ? css_set_move_task+0x152/0x340 [ 564.184197] do_exit+0x1290/0x1390 [ 564.184950] ? __issue_discard_cmd+0x480/0x480 [ 564.185884] ? mm_update_next_owner+0x380/0x380 [ 564.186829] ? __sched_text_start+0x8/0x8 [ 564.187672] ? __kthread_parkme+0xcb/0x100 [ 564.188528] ? kthread_blkcg+0x70/0x70 [ 564.189333] ? kthread+0x180/0x1d0 [ 564.190052] ? __issue_discard_cmd+0x480/0x480 [ 564.190983] rewind_stack_do_exit+0x17/0x20 [ 564.192190] The buggy address belongs to the page: [ 564.193213] page:ffffea0007cc45c0 count:0 mapcount:0 mapping:0000000000000000 index:0x0 [ 564.194856] flags: 0x2ffff0000000000() [ 564.195644] raw: 02ffff0000000000 0000000000000000 dead000000000200 0000000000000000 [ 564.197247] raw: 0000000000000000 0000000000000000 00000000ffffffff 0000000000000000 [ 564.198826] page dumped because: kasan: bad access detected [ 564.200299] Memory state around the buggy address: [ 564.201306] ffff8801f3117b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 564.202779] ffff8801f3117c00: 00 00 00 00 00 00 00 00 00 00 00 f3 f3 f3 f3 f3 [ 564.204252] >ffff8801f3117c80: f3 f3 f3 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 [ 564.205742] ^ [ 564.206424] ffff8801f3117d00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 564.207908] ffff8801f3117d80: f3 f3 f3 f3 f3 f3 f3 f3 00 00 00 00 00 00 00 00 [ 564.209389] ================================================================== [ 564.231795] F2FS-fs (loop0): Mounted with checkpoint version = 2 - Location https://elixir.bootlin.com/linux/v4.18-rc1/source/fs/f2fs/segment.h#L586 return div_u64((u64)valid_user_blocks(sbi) * 100, sbi->user_block_count); Missing checks on sbi->user_block_count. Reported-by: Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/super.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index 084ff9c82a37..9fafb1404f39 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -1956,6 +1956,8 @@ int sanity_check_ckpt(struct f2fs_sb_info *sbi) unsigned int sit_segs, nat_segs; unsigned int sit_bitmap_size, nat_bitmap_size; unsigned int log_blocks_per_seg; + unsigned int segment_count_main; + block_t user_block_count; int i; total = le32_to_cpu(raw_super->segment_count); @@ -1980,6 +1982,16 @@ int sanity_check_ckpt(struct f2fs_sb_info *sbi) return 1; } + user_block_count = le64_to_cpu(ckpt->user_block_count); + segment_count_main = le32_to_cpu(raw_super->segment_count_main); + log_blocks_per_seg = le32_to_cpu(raw_super->log_blocks_per_seg); + if (!user_block_count || user_block_count >= + segment_count_main << log_blocks_per_seg) { + f2fs_msg(sbi->sb, KERN_ERR, + "Wrong user_block_count: %u", user_block_count); + return 1; + } + main_segs = le32_to_cpu(raw_super->segment_count_main); blocks_per_seg = sbi->blocks_per_seg; @@ -1996,7 +2008,6 @@ int sanity_check_ckpt(struct f2fs_sb_info *sbi) sit_bitmap_size = le32_to_cpu(ckpt->sit_ver_bitmap_bytesize); nat_bitmap_size = le32_to_cpu(ckpt->nat_ver_bitmap_bytesize); - log_blocks_per_seg = le32_to_cpu(raw_super->log_blocks_per_seg); if (sit_bitmap_size != ((sit_segs / 2) << log_blocks_per_seg) / 8 || nat_bitmap_size != ((nat_segs / 2) << log_blocks_per_seg) / 8) { -- GitLab From b8321ccd045710ee04fd5322c34cadd13a5e58af Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Fri, 29 Jun 2018 13:55:22 +0800 Subject: [PATCH 0214/1286] f2fs: fix to do sanity check with node footer and iblocks commit e34438c903b653daca2b2a7de95aed46226f8ed3 upstream. This patch adds to do sanity check with below fields of inode to avoid reported panic. - node footer - iblocks https://bugzilla.kernel.org/show_bug.cgi?id=200223 - Overview BUG() triggered in f2fs_truncate_inode_blocks() when un-mounting a mounted f2fs image after writing to it - Reproduce - POC (poc.c) static void activity(char *mpoint) { char *foo_bar_baz; int err; static int buf[8192]; memset(buf, 0, sizeof(buf)); err = asprintf(&foo_bar_baz, "%s/foo/bar/baz", mpoint); // open / write / read int fd = open(foo_bar_baz, O_RDWR | O_TRUNC, 0777); if (fd >= 0) { write(fd, (char *)buf, 517); write(fd, (char *)buf, sizeof(buf)); close(fd); } } int main(int argc, char *argv[]) { activity(argv[1]); return 0; } - Kernel meesage [ 552.479723] F2FS-fs (loop0): Mounted with checkpoint version = 2 [ 556.451891] ------------[ cut here ]------------ [ 556.451899] kernel BUG at fs/f2fs/node.c:987! [ 556.452920] invalid opcode: 0000 [#1] SMP KASAN PTI [ 556.453936] CPU: 1 PID: 1310 Comm: umount Not tainted 4.18.0-rc1+ #4 [ 556.455213] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 556.457140] RIP: 0010:f2fs_truncate_inode_blocks+0x4a7/0x6f0 [ 556.458280] Code: e8 ae ea ff ff 41 89 c7 c1 e8 1f 84 c0 74 0a 41 83 ff fe 0f 85 35 ff ff ff 81 85 b0 fe ff ff fb 03 00 00 e9 f7 fd ff ff 0f 0b <0f> 0b e8 62 b7 9a 00 48 8b bd a0 fe ff ff e8 56 54 ae ff 48 8b b5 [ 556.462015] RSP: 0018:ffff8801f292f808 EFLAGS: 00010286 [ 556.463068] RAX: ffffed003e73242d RBX: ffff8801f292f958 RCX: ffffffffb88b81bc [ 556.464479] RDX: 0000000000000000 RSI: 0000000000000004 RDI: ffff8801f3992164 [ 556.465901] RBP: ffff8801f292f980 R08: ffffed003e73242d R09: ffffed003e73242d [ 556.467311] R10: 0000000000000001 R11: ffffed003e73242c R12: 00000000fffffc64 [ 556.468706] R13: ffff8801f3992000 R14: 0000000000000058 R15: 00000000ffff8801 [ 556.470117] FS: 00007f8029297840(0000) GS:ffff8801f6f00000(0000) knlGS:0000000000000000 [ 556.471702] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 556.472838] CR2: 000055f5f57305d8 CR3: 00000001f18b0000 CR4: 00000000000006e0 [ 556.474265] Call Trace: [ 556.474782] ? f2fs_alloc_nid_failed+0xf0/0xf0 [ 556.475686] ? truncate_nodes+0x980/0x980 [ 556.476516] ? pagecache_get_page+0x21f/0x2f0 [ 556.477412] ? __asan_loadN+0xf/0x20 [ 556.478153] ? __get_node_page+0x331/0x5b0 [ 556.478992] ? reweight_entity+0x1e6/0x3b0 [ 556.479826] f2fs_truncate_blocks+0x55e/0x740 [ 556.480709] ? f2fs_truncate_data_blocks+0x20/0x20 [ 556.481689] ? __radix_tree_lookup+0x34/0x160 [ 556.482630] ? radix_tree_lookup+0xd/0x10 [ 556.483445] f2fs_truncate+0xd4/0x1a0 [ 556.484206] f2fs_evict_inode+0x5ce/0x630 [ 556.485032] evict+0x16f/0x290 [ 556.485664] iput+0x280/0x300 [ 556.486300] dentry_unlink_inode+0x165/0x1e0 [ 556.487169] __dentry_kill+0x16a/0x260 [ 556.487936] dentry_kill+0x70/0x250 [ 556.488651] shrink_dentry_list+0x125/0x260 [ 556.489504] shrink_dcache_parent+0xc1/0x110 [ 556.490379] ? shrink_dcache_sb+0x200/0x200 [ 556.491231] ? bit_wait_timeout+0xc0/0xc0 [ 556.492047] do_one_tree+0x12/0x40 [ 556.492743] shrink_dcache_for_umount+0x3f/0xa0 [ 556.493656] generic_shutdown_super+0x43/0x1c0 [ 556.494561] kill_block_super+0x52/0x80 [ 556.495341] kill_f2fs_super+0x62/0x70 [ 556.496105] deactivate_locked_super+0x6f/0xa0 [ 556.497004] deactivate_super+0x5e/0x80 [ 556.497785] cleanup_mnt+0x61/0xa0 [ 556.498492] __cleanup_mnt+0x12/0x20 [ 556.499218] task_work_run+0xc8/0xf0 [ 556.499949] exit_to_usermode_loop+0x125/0x130 [ 556.500846] do_syscall_64+0x138/0x170 [ 556.501609] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 556.502659] RIP: 0033:0x7f8028b77487 [ 556.503384] Code: 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 31 f6 e9 09 00 00 00 66 0f 1f 84 00 00 00 00 00 b8 a6 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d e1 c9 2b 00 f7 d8 64 89 01 48 [ 556.507137] RSP: 002b:00007fff9f2e3598 EFLAGS: 00000246 ORIG_RAX: 00000000000000a6 [ 556.508637] RAX: 0000000000000000 RBX: 0000000000ebd030 RCX: 00007f8028b77487 [ 556.510069] RDX: 0000000000000001 RSI: 0000000000000000 RDI: 0000000000ec41e0 [ 556.511481] RBP: 0000000000ec41e0 R08: 0000000000000000 R09: 0000000000000014 [ 556.512892] R10: 00000000000006b2 R11: 0000000000000246 R12: 00007f802908083c [ 556.514320] R13: 0000000000000000 R14: 0000000000ebd210 R15: 00007fff9f2e3820 [ 556.515745] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mac_hid i2c_piix4 soundcore ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 multipath linear 8139too crct10dif_pclmul crc32_pclmul qxl drm_kms_helper syscopyarea aesni_intel sysfillrect sysimgblt fb_sys_fops ttm drm aes_x86_64 crypto_simd cryptd 8139cp glue_helper mii pata_acpi floppy [ 556.529276] ---[ end trace 4ce02f25ff7d3df5 ]--- [ 556.530340] RIP: 0010:f2fs_truncate_inode_blocks+0x4a7/0x6f0 [ 556.531513] Code: e8 ae ea ff ff 41 89 c7 c1 e8 1f 84 c0 74 0a 41 83 ff fe 0f 85 35 ff ff ff 81 85 b0 fe ff ff fb 03 00 00 e9 f7 fd ff ff 0f 0b <0f> 0b e8 62 b7 9a 00 48 8b bd a0 fe ff ff e8 56 54 ae ff 48 8b b5 [ 556.535330] RSP: 0018:ffff8801f292f808 EFLAGS: 00010286 [ 556.536395] RAX: ffffed003e73242d RBX: ffff8801f292f958 RCX: ffffffffb88b81bc [ 556.537824] RDX: 0000000000000000 RSI: 0000000000000004 RDI: ffff8801f3992164 [ 556.539290] RBP: ffff8801f292f980 R08: ffffed003e73242d R09: ffffed003e73242d [ 556.540709] R10: 0000000000000001 R11: ffffed003e73242c R12: 00000000fffffc64 [ 556.542131] R13: ffff8801f3992000 R14: 0000000000000058 R15: 00000000ffff8801 [ 556.543579] FS: 00007f8029297840(0000) GS:ffff8801f6f00000(0000) knlGS:0000000000000000 [ 556.545180] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 556.546338] CR2: 000055f5f57305d8 CR3: 00000001f18b0000 CR4: 00000000000006e0 [ 556.547809] ================================================================== [ 556.549248] BUG: KASAN: stack-out-of-bounds in arch_tlb_gather_mmu+0x52/0x170 [ 556.550672] Write of size 8 at addr ffff8801f292fd10 by task umount/1310 [ 556.552338] CPU: 1 PID: 1310 Comm: umount Tainted: G D 4.18.0-rc1+ #4 [ 556.553886] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 556.555756] Call Trace: [ 556.556264] dump_stack+0x7b/0xb5 [ 556.556944] print_address_description+0x70/0x290 [ 556.557903] kasan_report+0x291/0x390 [ 556.558649] ? arch_tlb_gather_mmu+0x52/0x170 [ 556.559537] __asan_store8+0x57/0x90 [ 556.560268] arch_tlb_gather_mmu+0x52/0x170 [ 556.561110] tlb_gather_mmu+0x12/0x40 [ 556.561862] exit_mmap+0x123/0x2a0 [ 556.562555] ? __ia32_sys_munmap+0x50/0x50 [ 556.563384] ? exit_aio+0x98/0x230 [ 556.564079] ? __x32_compat_sys_io_submit+0x260/0x260 [ 556.565099] ? taskstats_exit+0x1f4/0x640 [ 556.565925] ? kasan_check_read+0x11/0x20 [ 556.566739] ? mm_update_next_owner+0x322/0x380 [ 556.567652] mmput+0x8b/0x1d0 [ 556.568260] do_exit+0x43a/0x1390 [ 556.568937] ? mm_update_next_owner+0x380/0x380 [ 556.569855] ? deactivate_super+0x5e/0x80 [ 556.570668] ? cleanup_mnt+0x61/0xa0 [ 556.571395] ? __cleanup_mnt+0x12/0x20 [ 556.572156] ? task_work_run+0xc8/0xf0 [ 556.572917] ? exit_to_usermode_loop+0x125/0x130 [ 556.573861] rewind_stack_do_exit+0x17/0x20 [ 556.574707] RIP: 0033:0x7f8028b77487 [ 556.575428] Code: Bad RIP value. [ 556.576106] RSP: 002b:00007fff9f2e3598 EFLAGS: 00000246 ORIG_RAX: 00000000000000a6 [ 556.577599] RAX: 0000000000000000 RBX: 0000000000ebd030 RCX: 00007f8028b77487 [ 556.579020] RDX: 0000000000000001 RSI: 0000000000000000 RDI: 0000000000ec41e0 [ 556.580422] RBP: 0000000000ec41e0 R08: 0000000000000000 R09: 0000000000000014 [ 556.581833] R10: 00000000000006b2 R11: 0000000000000246 R12: 00007f802908083c [ 556.583252] R13: 0000000000000000 R14: 0000000000ebd210 R15: 00007fff9f2e3820 [ 556.584983] The buggy address belongs to the page: [ 556.585961] page:ffffea0007ca4bc0 count:0 mapcount:0 mapping:0000000000000000 index:0x0 [ 556.587540] flags: 0x2ffff0000000000() [ 556.588296] raw: 02ffff0000000000 0000000000000000 dead000000000200 0000000000000000 [ 556.589822] raw: 0000000000000000 0000000000000000 00000000ffffffff 0000000000000000 [ 556.591359] page dumped because: kasan: bad access detected [ 556.592786] Memory state around the buggy address: [ 556.593753] ffff8801f292fc00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 556.595191] ffff8801f292fc80: 00 00 00 00 00 00 00 00 f1 f1 f1 f1 00 00 00 00 [ 556.596613] >ffff8801f292fd00: 00 00 f3 00 00 00 00 f3 f3 00 00 00 00 f4 f4 f4 [ 556.598044] ^ [ 556.598797] ffff8801f292fd80: f3 f3 f3 f3 00 00 00 00 00 00 00 00 00 00 00 00 [ 556.600225] ffff8801f292fe00: 00 00 00 00 00 00 00 00 f1 f1 f1 f1 00 f4 f4 f4 [ 556.601647] ================================================================== - Location https://elixir.bootlin.com/linux/v4.18-rc1/source/fs/f2fs/node.c#L987 case NODE_DIND_BLOCK: err = truncate_nodes(&dn, nofs, offset[1], 3); cont = 0; break; default: BUG(); <--- } Reported-by Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/inode.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 428d502f23e8..be7d9773d291 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -180,9 +180,30 @@ void f2fs_inode_chksum_set(struct f2fs_sb_info *sbi, struct page *page) ri->i_inode_checksum = cpu_to_le32(f2fs_inode_chksum(sbi, page)); } -static bool sanity_check_inode(struct inode *inode) +static bool sanity_check_inode(struct inode *inode, struct page *node_page) { struct f2fs_sb_info *sbi = F2FS_I_SB(inode); + unsigned long long iblocks; + + iblocks = le64_to_cpu(F2FS_INODE(node_page)->i_blocks); + if (!iblocks) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "%s: corrupted inode i_blocks i_ino=%lx iblocks=%llu, " + "run fsck to fix.", + __func__, inode->i_ino, iblocks); + return false; + } + + if (ino_of_node(node_page) != nid_of_node(node_page)) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "%s: corrupted inode footer i_ino=%lx, ino,nid: " + "[%u, %u] run fsck to fix.", + __func__, inode->i_ino, + ino_of_node(node_page), nid_of_node(node_page)); + return false; + } if (f2fs_has_extra_attr(inode) && !f2fs_sb_has_extra_attr(sbi->sb)) { @@ -242,7 +263,7 @@ static int do_read_inode(struct inode *inode) get_inline_info(inode, ri); - if (!sanity_check_inode(inode)) { + if (!sanity_check_inode(inode, node_page)) { f2fs_put_page(node_page, 1); return -EINVAL; } -- GitLab From ad19d1e78fd51f5b4bf3ebbcbf3a133c8c03c49d Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Wed, 1 Aug 2018 19:13:44 +0800 Subject: [PATCH 0215/1286] f2fs: fix to do sanity check with block address in main area commit c9b60788fc760d136211853f10ce73dc152d1f4a upstream. This patch add to do sanity check with below field: - cp_pack_total_block_count - blkaddr of data/node - extent info - Overview BUG() in verify_block_addr() when writing to a corrupted f2fs image - Reproduce (4.18 upstream kernel) - POC (poc.c) static void activity(char *mpoint) { char *foo_bar_baz; int err; static int buf[8192]; memset(buf, 0, sizeof(buf)); err = asprintf(&foo_bar_baz, "%s/foo/bar/baz", mpoint); int fd = open(foo_bar_baz, O_RDWR | O_TRUNC, 0777); if (fd >= 0) { write(fd, (char *)buf, sizeof(buf)); fdatasync(fd); close(fd); } } int main(int argc, char *argv[]) { activity(argv[1]); return 0; } - Kernel message [ 689.349473] F2FS-fs (loop0): Mounted with checkpoint version = 3 [ 699.728662] WARNING: CPU: 0 PID: 1309 at fs/f2fs/segment.c:2860 f2fs_inplace_write_data+0x232/0x240 [ 699.728670] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mac_hid i2c_piix4 soundcore ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 multipath linear 8139too crct10dif_pclmul crc32_pclmul qxl drm_kms_helper syscopyarea aesni_intel sysfillrect sysimgblt fb_sys_fops ttm drm aes_x86_64 crypto_simd cryptd 8139cp glue_helper mii pata_acpi floppy [ 699.729056] CPU: 0 PID: 1309 Comm: a.out Not tainted 4.18.0-rc1+ #4 [ 699.729064] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 699.729074] RIP: 0010:f2fs_inplace_write_data+0x232/0x240 [ 699.729076] Code: ff e9 cf fe ff ff 49 8d 7d 10 e8 39 45 ad ff 4d 8b 7d 10 be 04 00 00 00 49 8d 7f 48 e8 07 49 ad ff 45 8b 7f 48 e9 fb fe ff ff <0f> 0b f0 41 80 4d 48 04 e9 65 fe ff ff 90 66 66 66 66 90 55 48 8d [ 699.729130] RSP: 0018:ffff8801f43af568 EFLAGS: 00010202 [ 699.729139] RAX: 000000000000003f RBX: ffff8801f43af7b8 RCX: ffffffffb88c9113 [ 699.729142] RDX: 0000000000000003 RSI: dffffc0000000000 RDI: ffff8802024e5540 [ 699.729144] RBP: ffff8801f43af590 R08: 0000000000000009 R09: ffffffffffffffe8 [ 699.729147] R10: 0000000000000001 R11: ffffed0039b0596a R12: ffff8802024e5540 [ 699.729149] R13: ffff8801f0335500 R14: ffff8801e3e7a700 R15: ffff8801e1ee4450 [ 699.729154] FS: 00007f9bf97f5700(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 699.729156] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 699.729159] CR2: 00007f9bf925d170 CR3: 00000001f0c34000 CR4: 00000000000006f0 [ 699.729171] Call Trace: [ 699.729192] f2fs_do_write_data_page+0x2e2/0xe00 [ 699.729203] ? f2fs_should_update_outplace+0xd0/0xd0 [ 699.729238] ? memcg_drain_all_list_lrus+0x280/0x280 [ 699.729269] ? __radix_tree_replace+0xa3/0x120 [ 699.729276] __write_data_page+0x5c7/0xe30 [ 699.729291] ? kasan_check_read+0x11/0x20 [ 699.729310] ? page_mapped+0x8a/0x110 [ 699.729321] ? page_mkclean+0xe9/0x160 [ 699.729327] ? f2fs_do_write_data_page+0xe00/0xe00 [ 699.729331] ? invalid_page_referenced_vma+0x130/0x130 [ 699.729345] ? clear_page_dirty_for_io+0x332/0x450 [ 699.729351] f2fs_write_cache_pages+0x4ca/0x860 [ 699.729358] ? __write_data_page+0xe30/0xe30 [ 699.729374] ? percpu_counter_add_batch+0x22/0xa0 [ 699.729380] ? kasan_check_write+0x14/0x20 [ 699.729391] ? _raw_spin_lock+0x17/0x40 [ 699.729403] ? f2fs_mark_inode_dirty_sync.part.18+0x16/0x30 [ 699.729413] ? iov_iter_advance+0x113/0x640 [ 699.729418] ? f2fs_write_end+0x133/0x2e0 [ 699.729423] ? balance_dirty_pages_ratelimited+0x239/0x640 [ 699.729428] f2fs_write_data_pages+0x329/0x520 [ 699.729433] ? generic_perform_write+0x250/0x320 [ 699.729438] ? f2fs_write_cache_pages+0x860/0x860 [ 699.729454] ? current_time+0x110/0x110 [ 699.729459] ? f2fs_preallocate_blocks+0x1ef/0x370 [ 699.729464] do_writepages+0x37/0xb0 [ 699.729468] ? f2fs_write_cache_pages+0x860/0x860 [ 699.729472] ? do_writepages+0x37/0xb0 [ 699.729478] __filemap_fdatawrite_range+0x19a/0x1f0 [ 699.729483] ? delete_from_page_cache_batch+0x4e0/0x4e0 [ 699.729496] ? __vfs_write+0x2b2/0x410 [ 699.729501] file_write_and_wait_range+0x66/0xb0 [ 699.729506] f2fs_do_sync_file+0x1f9/0xd90 [ 699.729511] ? truncate_partial_data_page+0x290/0x290 [ 699.729521] ? __sb_end_write+0x30/0x50 [ 699.729526] ? vfs_write+0x20f/0x260 [ 699.729530] f2fs_sync_file+0x9a/0xb0 [ 699.729534] ? f2fs_do_sync_file+0xd90/0xd90 [ 699.729548] vfs_fsync_range+0x68/0x100 [ 699.729554] ? __fget_light+0xc9/0xe0 [ 699.729558] do_fsync+0x3d/0x70 [ 699.729562] __x64_sys_fdatasync+0x24/0x30 [ 699.729585] do_syscall_64+0x78/0x170 [ 699.729595] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 699.729613] RIP: 0033:0x7f9bf930d800 [ 699.729615] Code: 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 83 3d 49 bf 2c 00 00 75 10 b8 4b 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 31 c3 48 83 ec 08 e8 be 78 01 00 48 89 04 24 [ 699.729668] RSP: 002b:00007ffee3606c68 EFLAGS: 00000246 ORIG_RAX: 000000000000004b [ 699.729673] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f9bf930d800 [ 699.729675] RDX: 0000000000008000 RSI: 00000000006010a0 RDI: 0000000000000003 [ 699.729678] RBP: 00007ffee3606ca0 R08: 0000000001503010 R09: 0000000000000000 [ 699.729680] R10: 00000000000002e8 R11: 0000000000000246 R12: 0000000000400610 [ 699.729683] R13: 00007ffee3606da0 R14: 0000000000000000 R15: 0000000000000000 [ 699.729687] ---[ end trace 4ce02f25ff7d3df5 ]--- [ 699.729782] ------------[ cut here ]------------ [ 699.729785] kernel BUG at fs/f2fs/segment.h:654! [ 699.731055] invalid opcode: 0000 [#1] SMP KASAN PTI [ 699.732104] CPU: 0 PID: 1309 Comm: a.out Tainted: G W 4.18.0-rc1+ #4 [ 699.733684] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 699.735611] RIP: 0010:f2fs_submit_page_bio+0x29b/0x730 [ 699.736649] Code: 54 49 8d bd 18 04 00 00 e8 b2 59 af ff 41 8b 8d 18 04 00 00 8b 45 b8 41 d3 e6 44 01 f0 4c 8d 73 14 41 39 c7 0f 82 37 fe ff ff <0f> 0b 65 8b 05 2c 04 77 47 89 c0 48 0f a3 05 52 c1 d5 01 0f 92 c0 [ 699.740524] RSP: 0018:ffff8801f43af508 EFLAGS: 00010283 [ 699.741573] RAX: 0000000000000000 RBX: ffff8801f43af7b8 RCX: ffffffffb88a7cef [ 699.743006] RDX: 0000000000000007 RSI: dffffc0000000000 RDI: ffff8801e3e7a64c [ 699.744426] RBP: ffff8801f43af558 R08: ffffed003e066b55 R09: ffffed003e066b55 [ 699.745833] R10: 0000000000000001 R11: ffffed003e066b54 R12: ffffea0007876940 [ 699.747256] R13: ffff8801f0335500 R14: ffff8801e3e7a600 R15: 0000000000000001 [ 699.748683] FS: 00007f9bf97f5700(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 699.750293] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 699.751462] CR2: 00007f9bf925d170 CR3: 00000001f0c34000 CR4: 00000000000006f0 [ 699.752874] Call Trace: [ 699.753386] ? f2fs_inplace_write_data+0x93/0x240 [ 699.754341] f2fs_inplace_write_data+0xd2/0x240 [ 699.755271] f2fs_do_write_data_page+0x2e2/0xe00 [ 699.756214] ? f2fs_should_update_outplace+0xd0/0xd0 [ 699.757215] ? memcg_drain_all_list_lrus+0x280/0x280 [ 699.758209] ? __radix_tree_replace+0xa3/0x120 [ 699.759164] __write_data_page+0x5c7/0xe30 [ 699.760002] ? kasan_check_read+0x11/0x20 [ 699.760823] ? page_mapped+0x8a/0x110 [ 699.761573] ? page_mkclean+0xe9/0x160 [ 699.762345] ? f2fs_do_write_data_page+0xe00/0xe00 [ 699.763332] ? invalid_page_referenced_vma+0x130/0x130 [ 699.764374] ? clear_page_dirty_for_io+0x332/0x450 [ 699.765347] f2fs_write_cache_pages+0x4ca/0x860 [ 699.766276] ? __write_data_page+0xe30/0xe30 [ 699.767161] ? percpu_counter_add_batch+0x22/0xa0 [ 699.768112] ? kasan_check_write+0x14/0x20 [ 699.768951] ? _raw_spin_lock+0x17/0x40 [ 699.769739] ? f2fs_mark_inode_dirty_sync.part.18+0x16/0x30 [ 699.770885] ? iov_iter_advance+0x113/0x640 [ 699.771743] ? f2fs_write_end+0x133/0x2e0 [ 699.772569] ? balance_dirty_pages_ratelimited+0x239/0x640 [ 699.773680] f2fs_write_data_pages+0x329/0x520 [ 699.774603] ? generic_perform_write+0x250/0x320 [ 699.775544] ? f2fs_write_cache_pages+0x860/0x860 [ 699.776510] ? current_time+0x110/0x110 [ 699.777299] ? f2fs_preallocate_blocks+0x1ef/0x370 [ 699.778279] do_writepages+0x37/0xb0 [ 699.779026] ? f2fs_write_cache_pages+0x860/0x860 [ 699.779978] ? do_writepages+0x37/0xb0 [ 699.780755] __filemap_fdatawrite_range+0x19a/0x1f0 [ 699.781746] ? delete_from_page_cache_batch+0x4e0/0x4e0 [ 699.782820] ? __vfs_write+0x2b2/0x410 [ 699.783597] file_write_and_wait_range+0x66/0xb0 [ 699.784540] f2fs_do_sync_file+0x1f9/0xd90 [ 699.785381] ? truncate_partial_data_page+0x290/0x290 [ 699.786415] ? __sb_end_write+0x30/0x50 [ 699.787204] ? vfs_write+0x20f/0x260 [ 699.787941] f2fs_sync_file+0x9a/0xb0 [ 699.788694] ? f2fs_do_sync_file+0xd90/0xd90 [ 699.789572] vfs_fsync_range+0x68/0x100 [ 699.790360] ? __fget_light+0xc9/0xe0 [ 699.791128] do_fsync+0x3d/0x70 [ 699.791779] __x64_sys_fdatasync+0x24/0x30 [ 699.792614] do_syscall_64+0x78/0x170 [ 699.793371] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 699.794406] RIP: 0033:0x7f9bf930d800 [ 699.795134] Code: 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 83 3d 49 bf 2c 00 00 75 10 b8 4b 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 31 c3 48 83 ec 08 e8 be 78 01 00 48 89 04 24 [ 699.798960] RSP: 002b:00007ffee3606c68 EFLAGS: 00000246 ORIG_RAX: 000000000000004b [ 699.800483] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f9bf930d800 [ 699.801923] RDX: 0000000000008000 RSI: 00000000006010a0 RDI: 0000000000000003 [ 699.803373] RBP: 00007ffee3606ca0 R08: 0000000001503010 R09: 0000000000000000 [ 699.804798] R10: 00000000000002e8 R11: 0000000000000246 R12: 0000000000400610 [ 699.806233] R13: 00007ffee3606da0 R14: 0000000000000000 R15: 0000000000000000 [ 699.807667] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_timer snd mac_hid i2c_piix4 soundcore ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx raid1 raid0 multipath linear 8139too crct10dif_pclmul crc32_pclmul qxl drm_kms_helper syscopyarea aesni_intel sysfillrect sysimgblt fb_sys_fops ttm drm aes_x86_64 crypto_simd cryptd 8139cp glue_helper mii pata_acpi floppy [ 699.817079] ---[ end trace 4ce02f25ff7d3df6 ]--- [ 699.818068] RIP: 0010:f2fs_submit_page_bio+0x29b/0x730 [ 699.819114] Code: 54 49 8d bd 18 04 00 00 e8 b2 59 af ff 41 8b 8d 18 04 00 00 8b 45 b8 41 d3 e6 44 01 f0 4c 8d 73 14 41 39 c7 0f 82 37 fe ff ff <0f> 0b 65 8b 05 2c 04 77 47 89 c0 48 0f a3 05 52 c1 d5 01 0f 92 c0 [ 699.822919] RSP: 0018:ffff8801f43af508 EFLAGS: 00010283 [ 699.823977] RAX: 0000000000000000 RBX: ffff8801f43af7b8 RCX: ffffffffb88a7cef [ 699.825436] RDX: 0000000000000007 RSI: dffffc0000000000 RDI: ffff8801e3e7a64c [ 699.826881] RBP: ffff8801f43af558 R08: ffffed003e066b55 R09: ffffed003e066b55 [ 699.828292] R10: 0000000000000001 R11: ffffed003e066b54 R12: ffffea0007876940 [ 699.829750] R13: ffff8801f0335500 R14: ffff8801e3e7a600 R15: 0000000000000001 [ 699.831192] FS: 00007f9bf97f5700(0000) GS:ffff8801f6e00000(0000) knlGS:0000000000000000 [ 699.832793] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 699.833981] CR2: 00007f9bf925d170 CR3: 00000001f0c34000 CR4: 00000000000006f0 [ 699.835556] ================================================================== [ 699.837029] BUG: KASAN: stack-out-of-bounds in update_stack_state+0x38c/0x3e0 [ 699.838462] Read of size 8 at addr ffff8801f43af970 by task a.out/1309 [ 699.840086] CPU: 0 PID: 1309 Comm: a.out Tainted: G D W 4.18.0-rc1+ #4 [ 699.841603] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 699.843475] Call Trace: [ 699.843982] dump_stack+0x7b/0xb5 [ 699.844661] print_address_description+0x70/0x290 [ 699.845607] kasan_report+0x291/0x390 [ 699.846351] ? update_stack_state+0x38c/0x3e0 [ 699.853831] __asan_load8+0x54/0x90 [ 699.854569] update_stack_state+0x38c/0x3e0 [ 699.855428] ? __read_once_size_nocheck.constprop.7+0x20/0x20 [ 699.856601] ? __save_stack_trace+0x5e/0x100 [ 699.857476] unwind_next_frame.part.5+0x18e/0x490 [ 699.858448] ? unwind_dump+0x290/0x290 [ 699.859217] ? clear_page_dirty_for_io+0x332/0x450 [ 699.860185] __unwind_start+0x106/0x190 [ 699.860974] __save_stack_trace+0x5e/0x100 [ 699.861808] ? __save_stack_trace+0x5e/0x100 [ 699.862691] ? unlink_anon_vmas+0xba/0x2c0 [ 699.863525] save_stack_trace+0x1f/0x30 [ 699.864312] save_stack+0x46/0xd0 [ 699.864993] ? __alloc_pages_slowpath+0x1420/0x1420 [ 699.865990] ? flush_tlb_mm_range+0x15e/0x220 [ 699.866889] ? kasan_check_write+0x14/0x20 [ 699.867724] ? __dec_node_state+0x92/0xb0 [ 699.868543] ? lock_page_memcg+0x85/0xf0 [ 699.869350] ? unlock_page_memcg+0x16/0x80 [ 699.870185] ? page_remove_rmap+0x198/0x520 [ 699.871048] ? mark_page_accessed+0x133/0x200 [ 699.871930] ? _cond_resched+0x1a/0x50 [ 699.872700] ? unmap_page_range+0xcd4/0xe50 [ 699.873551] ? rb_next+0x58/0x80 [ 699.874217] ? rb_next+0x58/0x80 [ 699.874895] __kasan_slab_free+0x13c/0x1a0 [ 699.875734] ? unlink_anon_vmas+0xba/0x2c0 [ 699.876563] kasan_slab_free+0xe/0x10 [ 699.877315] kmem_cache_free+0x89/0x1e0 [ 699.878095] unlink_anon_vmas+0xba/0x2c0 [ 699.878913] free_pgtables+0x101/0x1b0 [ 699.879677] exit_mmap+0x146/0x2a0 [ 699.880378] ? __ia32_sys_munmap+0x50/0x50 [ 699.881214] ? kasan_check_read+0x11/0x20 [ 699.882052] ? mm_update_next_owner+0x322/0x380 [ 699.882985] mmput+0x8b/0x1d0 [ 699.883602] do_exit+0x43a/0x1390 [ 699.884288] ? mm_update_next_owner+0x380/0x380 [ 699.885212] ? f2fs_sync_file+0x9a/0xb0 [ 699.885995] ? f2fs_do_sync_file+0xd90/0xd90 [ 699.886877] ? vfs_fsync_range+0x68/0x100 [ 699.887694] ? __fget_light+0xc9/0xe0 [ 699.888442] ? do_fsync+0x3d/0x70 [ 699.889118] ? __x64_sys_fdatasync+0x24/0x30 [ 699.889996] rewind_stack_do_exit+0x17/0x20 [ 699.890860] RIP: 0033:0x7f9bf930d800 [ 699.891585] Code: Bad RIP value. [ 699.892268] RSP: 002b:00007ffee3606c68 EFLAGS: 00000246 ORIG_RAX: 000000000000004b [ 699.893781] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f9bf930d800 [ 699.895220] RDX: 0000000000008000 RSI: 00000000006010a0 RDI: 0000000000000003 [ 699.896643] RBP: 00007ffee3606ca0 R08: 0000000001503010 R09: 0000000000000000 [ 699.898069] R10: 00000000000002e8 R11: 0000000000000246 R12: 0000000000400610 [ 699.899505] R13: 00007ffee3606da0 R14: 0000000000000000 R15: 0000000000000000 [ 699.901241] The buggy address belongs to the page: [ 699.902215] page:ffffea0007d0ebc0 count:0 mapcount:0 mapping:0000000000000000 index:0x0 [ 699.903811] flags: 0x2ffff0000000000() [ 699.904585] raw: 02ffff0000000000 0000000000000000 ffffffff07d00101 0000000000000000 [ 699.906125] raw: 0000000000000000 0000000000240000 00000000ffffffff 0000000000000000 [ 699.907673] page dumped because: kasan: bad access detected [ 699.909108] Memory state around the buggy address: [ 699.910077] ffff8801f43af800: 00 f1 f1 f1 f1 00 f4 f4 f4 f3 f3 f3 f3 00 00 00 [ 699.911528] ffff8801f43af880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 699.912953] >ffff8801f43af900: 00 00 00 00 00 00 00 00 f1 01 f4 f4 f4 f2 f2 f2 [ 699.914392] ^ [ 699.915758] ffff8801f43af980: f2 00 f4 f4 00 00 00 00 f2 00 00 00 00 00 00 00 [ 699.917193] ffff8801f43afa00: 00 00 00 00 00 00 00 00 00 f3 f3 f3 00 00 00 00 [ 699.918634] ================================================================== - Location https://elixir.bootlin.com/linux/v4.18-rc1/source/fs/f2fs/segment.h#L644 Reported-by Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: - Error label is different in validate_checkpoint() due to the earlier backport of "f2fs: fix invalid memory access" - Adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 22 +++++++++++++++++++--- fs/f2fs/data.c | 33 +++++++++++++++++++++++++++------ fs/f2fs/f2fs.h | 3 +++ fs/f2fs/file.c | 12 ++++++++++++ fs/f2fs/inode.c | 17 +++++++++++++++++ fs/f2fs/node.c | 4 ++++ fs/f2fs/segment.h | 3 +-- 7 files changed, 83 insertions(+), 11 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index d7bd9745e883..c81cd5057b8e 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -86,8 +86,10 @@ static struct page *__get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index, fio.page = page; if (f2fs_submit_page_bio(&fio)) { - f2fs_put_page(page, 1); - goto repeat; + memset(page_address(page), 0, PAGE_SIZE); + f2fs_stop_checkpoint(sbi, false); + f2fs_bug_on(sbi, 1); + return page; } lock_page(page); @@ -141,8 +143,14 @@ bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, case META_POR: case DATA_GENERIC: if (unlikely(blkaddr >= MAX_BLKADDR(sbi) || - blkaddr < MAIN_BLKADDR(sbi))) + blkaddr < MAIN_BLKADDR(sbi))) { + if (type == DATA_GENERIC) { + f2fs_msg(sbi->sb, KERN_WARNING, + "access invalid blkaddr:%u", blkaddr); + WARN_ON(1); + } return false; + } break; case META_GENERIC: if (unlikely(blkaddr < SEG0_BLKADDR(sbi) || @@ -746,6 +754,14 @@ static struct page *validate_checkpoint(struct f2fs_sb_info *sbi, &cp_page_1, version); if (err) return NULL; + + if (le32_to_cpu(cp_block->cp_pack_total_block_count) > + sbi->blocks_per_seg) { + f2fs_msg(sbi->sb, KERN_WARNING, + "invalid cp_pack_total_block_count:%u", + le32_to_cpu(cp_block->cp_pack_total_block_count)); + goto invalid_cp; + } pre_version = *version; cp_addr += le32_to_cpu(cp_block->cp_pack_total_block_count) - 1; diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 615878806611..8f6e7c3a10f8 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -369,7 +369,10 @@ int f2fs_submit_page_bio(struct f2fs_io_info *fio) struct page *page = fio->encrypted_page ? fio->encrypted_page : fio->page; - verify_block_addr(fio, fio->new_blkaddr); + if (!f2fs_is_valid_blkaddr(fio->sbi, fio->new_blkaddr, + __is_meta_io(fio) ? META_GENERIC : DATA_GENERIC)) + return -EFAULT; + trace_f2fs_submit_page_bio(page, fio); f2fs_trace_ios(fio, 0); @@ -946,6 +949,12 @@ int f2fs_map_blocks(struct inode *inode, struct f2fs_map_blocks *map, next_block: blkaddr = datablock_addr(dn.inode, dn.node_page, dn.ofs_in_node); + if (__is_valid_data_blkaddr(blkaddr) && + !f2fs_is_valid_blkaddr(sbi, blkaddr, DATA_GENERIC)) { + err = -EFAULT; + goto sync_out; + } + if (!is_valid_data_blkaddr(sbi, blkaddr)) { if (create) { if (unlikely(f2fs_cp_error(sbi))) { @@ -1264,6 +1273,10 @@ static int f2fs_mpage_readpages(struct address_space *mapping, SetPageUptodate(page); goto confused; } + + if (!f2fs_is_valid_blkaddr(F2FS_I_SB(inode), block_nr, + DATA_GENERIC)) + goto set_error_page; } else { zero_user_segment(page, 0, PAGE_SIZE); if (!PageUptodate(page)) @@ -1402,11 +1415,13 @@ int do_write_data_page(struct f2fs_io_info *fio) f2fs_lookup_extent_cache(inode, page->index, &ei)) { fio->old_blkaddr = ei.blk + page->index - ei.fofs; - if (is_valid_data_blkaddr(fio->sbi, fio->old_blkaddr)) { - ipu_force = true; - fio->need_lock = LOCK_DONE; - goto got_it; - } + if (!f2fs_is_valid_blkaddr(fio->sbi, fio->old_blkaddr, + DATA_GENERIC)) + return -EFAULT; + + ipu_force = true; + fio->need_lock = LOCK_DONE; + goto got_it; } /* Deadlock due to between page->lock and f2fs_lock_op */ @@ -1425,6 +1440,12 @@ int do_write_data_page(struct f2fs_io_info *fio) goto out_writepage; } got_it: + if (__is_valid_data_blkaddr(fio->old_blkaddr) && + !f2fs_is_valid_blkaddr(fio->sbi, fio->old_blkaddr, + DATA_GENERIC)) { + err = -EFAULT; + goto out_writepage; + } /* * If current allocation needs SSR, * it had better in-place writes for updated data. diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index d15d79457f5c..3f1a44696036 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -2357,6 +2357,9 @@ static inline void f2fs_update_iostat(struct f2fs_sb_info *sbi, spin_unlock(&sbi->iostat_lock); } +#define __is_meta_io(fio) (PAGE_TYPE_OF_BIO(fio->type) == META && \ + (!is_read_io(fio->op) || fio->is_meta)) + bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type); void f2fs_msg(struct super_block *sb, const char *level, const char *fmt, ...); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index e9c575ef70b5..7d3189f1941c 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -397,6 +397,13 @@ static loff_t f2fs_seek_block(struct file *file, loff_t offset, int whence) blkaddr = datablock_addr(dn.inode, dn.node_page, dn.ofs_in_node); + if (__is_valid_data_blkaddr(blkaddr) && + !f2fs_is_valid_blkaddr(F2FS_I_SB(inode), + blkaddr, DATA_GENERIC)) { + f2fs_put_dnode(&dn); + goto fail; + } + if (__found_offset(F2FS_I_SB(inode), blkaddr, dirty, pgofs, whence)) { f2fs_put_dnode(&dn); @@ -496,6 +503,11 @@ int truncate_data_blocks_range(struct dnode_of_data *dn, int count) dn->data_blkaddr = NULL_ADDR; set_data_blkaddr(dn); + + if (__is_valid_data_blkaddr(blkaddr) && + !f2fs_is_valid_blkaddr(sbi, blkaddr, DATA_GENERIC)) + continue; + invalidate_blocks(sbi, blkaddr); if (dn->ofs_in_node == 0 && IS_INODE(dn->node_page)) clear_inode_flag(dn->inode, FI_FIRST_BLOCK_WRITTEN); diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index be7d9773d291..aeed9943836a 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -214,6 +214,23 @@ static bool sanity_check_inode(struct inode *inode, struct page *node_page) __func__, inode->i_ino); return false; } + + if (F2FS_I(inode)->extent_tree) { + struct extent_info *ei = &F2FS_I(inode)->extent_tree->largest; + + if (ei->len && + (!f2fs_is_valid_blkaddr(sbi, ei->blk, DATA_GENERIC) || + !f2fs_is_valid_blkaddr(sbi, ei->blk + ei->len - 1, + DATA_GENERIC))) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "%s: inode (ino=%lx) extent info [%u, %u, %u] " + "is incorrect, run fsck to fix", + __func__, inode->i_ino, + ei->blk, ei->fofs, ei->len); + return false; + } + } return true; } diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 999814c8cbea..6adb6c60f017 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -1398,6 +1398,10 @@ static int __write_node_page(struct page *page, bool atomic, bool *submitted, return 0; } + if (__is_valid_data_blkaddr(ni.blk_addr) && + !f2fs_is_valid_blkaddr(sbi, ni.blk_addr, DATA_GENERIC)) + goto redirty_out; + if (atomic && !test_opt(sbi, NOBARRIER)) fio.op_flags |= REQ_PREFLUSH | REQ_FUA; diff --git a/fs/f2fs/segment.h b/fs/f2fs/segment.h index dd8f977fc273..47348d98165b 100644 --- a/fs/f2fs/segment.h +++ b/fs/f2fs/segment.h @@ -629,8 +629,7 @@ static inline void verify_block_addr(struct f2fs_io_info *fio, block_t blk_addr) { struct f2fs_sb_info *sbi = fio->sbi; - if (PAGE_TYPE_OF_BIO(fio->type) == META && - (!is_read_io(fio->op) || fio->is_meta)) + if (__is_meta_io(fio)) verify_blkaddr(sbi, blk_addr, META_GENERIC); else verify_blkaddr(sbi, blk_addr, DATA_GENERIC); -- GitLab From d7d9d29a837358636e12fe09c90a7882b53b2220 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Sun, 8 Jul 2018 22:16:55 +0800 Subject: [PATCH 0216/1286] f2fs: fix to do sanity check with i_extra_isize commit 18dd6470c2d14d10f5a2dd926925dc80dbd3abfd upstream. If inode.i_extra_isize was fuzzed to an abnormal value, when calculating inline data size, the result will overflow, result in accessing invalid memory area when operating inline data. Let's do sanity check with i_extra_isize during inode loading for fixing. https://bugzilla.kernel.org/show_bug.cgi?id=200421 - Reproduce - POC (poc.c) #define _GNU_SOURCE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static void activity(char *mpoint) { char *foo_bar_baz; char *foo_baz; char *xattr; int err; err = asprintf(&foo_bar_baz, "%s/foo/bar/baz", mpoint); err = asprintf(&foo_baz, "%s/foo/baz", mpoint); err = asprintf(&xattr, "%s/foo/bar/xattr", mpoint); rename(foo_bar_baz, foo_baz); char buf2[113]; memset(buf2, 0, sizeof(buf2)); listxattr(xattr, buf2, sizeof(buf2)); removexattr(xattr, "user.mime_type"); } int main(int argc, char *argv[]) { activity(argv[1]); return 0; } - Kernel message Umount the image will leave the following message [ 2910.995489] F2FS-fs (loop0): Mounted with checkpoint version = 2 [ 2918.416465] ================================================================== [ 2918.416807] BUG: KASAN: slab-out-of-bounds in f2fs_iget+0xcb9/0x1a80 [ 2918.417009] Read of size 4 at addr ffff88018efc2068 by task a.out/1229 [ 2918.417311] CPU: 1 PID: 1229 Comm: a.out Not tainted 4.17.0+ #1 [ 2918.417314] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 2918.417323] Call Trace: [ 2918.417366] dump_stack+0x71/0xab [ 2918.417401] print_address_description+0x6b/0x290 [ 2918.417407] kasan_report+0x28e/0x390 [ 2918.417411] ? f2fs_iget+0xcb9/0x1a80 [ 2918.417415] f2fs_iget+0xcb9/0x1a80 [ 2918.417422] ? f2fs_lookup+0x2e7/0x580 [ 2918.417425] f2fs_lookup+0x2e7/0x580 [ 2918.417433] ? __recover_dot_dentries+0x400/0x400 [ 2918.417447] ? legitimize_path.isra.29+0x5a/0xa0 [ 2918.417453] __lookup_slow+0x11c/0x220 [ 2918.417457] ? may_delete+0x2a0/0x2a0 [ 2918.417475] ? deref_stack_reg+0xe0/0xe0 [ 2918.417479] ? __lookup_hash+0xb0/0xb0 [ 2918.417483] lookup_slow+0x3e/0x60 [ 2918.417488] walk_component+0x3ac/0x990 [ 2918.417492] ? generic_permission+0x51/0x1e0 [ 2918.417495] ? inode_permission+0x51/0x1d0 [ 2918.417499] ? pick_link+0x3e0/0x3e0 [ 2918.417502] ? link_path_walk+0x4b1/0x770 [ 2918.417513] ? _raw_spin_lock_irqsave+0x25/0x50 [ 2918.417518] ? walk_component+0x990/0x990 [ 2918.417522] ? path_init+0x2e6/0x580 [ 2918.417526] path_lookupat+0x13f/0x430 [ 2918.417531] ? trailing_symlink+0x3a0/0x3a0 [ 2918.417534] ? do_renameat2+0x270/0x7b0 [ 2918.417538] ? __kasan_slab_free+0x14c/0x190 [ 2918.417541] ? do_renameat2+0x270/0x7b0 [ 2918.417553] ? kmem_cache_free+0x85/0x1e0 [ 2918.417558] ? do_renameat2+0x270/0x7b0 [ 2918.417563] filename_lookup+0x13c/0x280 [ 2918.417567] ? filename_parentat+0x2b0/0x2b0 [ 2918.417572] ? kasan_unpoison_shadow+0x31/0x40 [ 2918.417575] ? kasan_kmalloc+0xa6/0xd0 [ 2918.417593] ? strncpy_from_user+0xaa/0x1c0 [ 2918.417598] ? getname_flags+0x101/0x2b0 [ 2918.417614] ? path_listxattr+0x87/0x110 [ 2918.417619] path_listxattr+0x87/0x110 [ 2918.417623] ? listxattr+0xc0/0xc0 [ 2918.417637] ? mm_fault_error+0x1b0/0x1b0 [ 2918.417654] do_syscall_64+0x73/0x160 [ 2918.417660] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 2918.417676] RIP: 0033:0x7f2f3a3480d7 [ 2918.417677] Code: f0 ff ff 73 01 c3 48 8b 0d be dd 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 b8 c2 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 91 dd 2b 00 f7 d8 64 89 01 48 [ 2918.417732] RSP: 002b:00007fff4095b7d8 EFLAGS: 00000206 ORIG_RAX: 00000000000000c2 [ 2918.417744] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f2f3a3480d7 [ 2918.417746] RDX: 0000000000000071 RSI: 00007fff4095b810 RDI: 000000000126a0c0 [ 2918.417749] RBP: 00007fff4095b890 R08: 000000000126a010 R09: 0000000000000000 [ 2918.417751] R10: 00000000000001ab R11: 0000000000000206 R12: 00000000004005e0 [ 2918.417753] R13: 00007fff4095b990 R14: 0000000000000000 R15: 0000000000000000 [ 2918.417853] Allocated by task 329: [ 2918.418002] kasan_kmalloc+0xa6/0xd0 [ 2918.418007] kmem_cache_alloc+0xc8/0x1e0 [ 2918.418023] mempool_init_node+0x194/0x230 [ 2918.418027] mempool_init+0x12/0x20 [ 2918.418042] bioset_init+0x2bd/0x380 [ 2918.418052] blk_alloc_queue_node+0xe9/0x540 [ 2918.418075] dm_create+0x2c0/0x800 [ 2918.418080] dev_create+0xd2/0x530 [ 2918.418083] ctl_ioctl+0x2a3/0x5b0 [ 2918.418087] dm_ctl_ioctl+0xa/0x10 [ 2918.418092] do_vfs_ioctl+0x13e/0x8c0 [ 2918.418095] ksys_ioctl+0x66/0x70 [ 2918.418098] __x64_sys_ioctl+0x3d/0x50 [ 2918.418102] do_syscall_64+0x73/0x160 [ 2918.418106] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 2918.418204] Freed by task 0: [ 2918.418301] (stack is not available) [ 2918.418521] The buggy address belongs to the object at ffff88018efc0000 which belongs to the cache biovec-max of size 8192 [ 2918.418894] The buggy address is located 104 bytes to the right of 8192-byte region [ffff88018efc0000, ffff88018efc2000) [ 2918.419257] The buggy address belongs to the page: [ 2918.419431] page:ffffea00063bf000 count:1 mapcount:0 mapping:ffff8801f2242540 index:0x0 compound_mapcount: 0 [ 2918.419702] flags: 0x17fff8000008100(slab|head) [ 2918.419879] raw: 017fff8000008100 dead000000000100 dead000000000200 ffff8801f2242540 [ 2918.420101] raw: 0000000000000000 0000000000030003 00000001ffffffff 0000000000000000 [ 2918.420322] page dumped because: kasan: bad access detected [ 2918.420599] Memory state around the buggy address: [ 2918.420764] ffff88018efc1f00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 2918.420975] ffff88018efc1f80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 2918.421194] >ffff88018efc2000: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 2918.421406] ^ [ 2918.421627] ffff88018efc2080: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 2918.421838] ffff88018efc2100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 2918.422046] ================================================================== [ 2918.422264] Disabling lock debugging due to kernel taint [ 2923.901641] BUG: unable to handle kernel paging request at ffff88018f0db000 [ 2923.901884] PGD 22226a067 P4D 22226a067 PUD 222273067 PMD 18e642063 PTE 800000018f0db061 [ 2923.902120] Oops: 0003 [#1] SMP KASAN PTI [ 2923.902274] CPU: 1 PID: 1231 Comm: umount Tainted: G B 4.17.0+ #1 [ 2923.902490] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 2923.902761] RIP: 0010:__memset+0x24/0x30 [ 2923.902906] Code: 90 90 90 90 90 90 66 66 90 66 90 49 89 f9 48 89 d1 83 e2 07 48 c1 e9 03 40 0f b6 f6 48 b8 01 01 01 01 01 01 01 01 48 0f af c6 48 ab 89 d1 f3 aa 4c 89 c8 c3 90 49 89 f9 40 88 f0 48 89 d1 f3 [ 2923.903446] RSP: 0018:ffff88018ddf7ae0 EFLAGS: 00010206 [ 2923.903622] RAX: 0000000000000000 RBX: ffff8801d549d888 RCX: 1ffffffffffdaffb [ 2923.903833] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff88018f0daffc [ 2923.904062] RBP: ffff88018efc206c R08: 1ffff10031df840d R09: ffff88018efc206c [ 2923.904273] R10: ffffffffffffe1ee R11: ffffed0031df65fa R12: 0000000000000000 [ 2923.904485] R13: ffff8801d549dc98 R14: 00000000ffffc3db R15: ffffea00063bec80 [ 2923.904693] FS: 00007fa8b2f8a840(0000) GS:ffff8801f3b00000(0000) knlGS:0000000000000000 [ 2923.904937] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2923.910080] CR2: ffff88018f0db000 CR3: 000000018f892000 CR4: 00000000000006e0 [ 2923.914930] Call Trace: [ 2923.919724] f2fs_truncate_inline_inode+0x114/0x170 [ 2923.924487] f2fs_truncate_blocks+0x11b/0x7c0 [ 2923.929178] ? f2fs_truncate_data_blocks+0x10/0x10 [ 2923.933834] ? dqget+0x670/0x670 [ 2923.938437] ? f2fs_destroy_extent_tree+0xd6/0x270 [ 2923.943107] ? __radix_tree_lookup+0x2f/0x150 [ 2923.947772] f2fs_truncate+0xd4/0x1a0 [ 2923.952491] f2fs_evict_inode+0x5ab/0x610 [ 2923.957204] evict+0x15f/0x280 [ 2923.961898] __dentry_kill+0x161/0x250 [ 2923.966634] shrink_dentry_list+0xf3/0x250 [ 2923.971897] shrink_dcache_parent+0xa9/0x100 [ 2923.976561] ? shrink_dcache_sb+0x1f0/0x1f0 [ 2923.981177] ? wait_for_completion+0x8a/0x210 [ 2923.985781] ? migrate_swap_stop+0x2d0/0x2d0 [ 2923.990332] do_one_tree+0xe/0x40 [ 2923.994735] shrink_dcache_for_umount+0x3a/0xa0 [ 2923.999077] generic_shutdown_super+0x3e/0x1c0 [ 2924.003350] kill_block_super+0x4b/0x70 [ 2924.007619] deactivate_locked_super+0x65/0x90 [ 2924.011812] cleanup_mnt+0x5c/0xa0 [ 2924.015995] task_work_run+0xce/0xf0 [ 2924.020174] exit_to_usermode_loop+0x115/0x120 [ 2924.024293] do_syscall_64+0x12f/0x160 [ 2924.028479] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 2924.032709] RIP: 0033:0x7fa8b2868487 [ 2924.036888] Code: 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 31 f6 e9 09 00 00 00 66 0f 1f 84 00 00 00 00 00 b8 a6 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d e1 c9 2b 00 f7 d8 64 89 01 48 [ 2924.045750] RSP: 002b:00007ffc39824d58 EFLAGS: 00000246 ORIG_RAX: 00000000000000a6 [ 2924.050190] RAX: 0000000000000000 RBX: 00000000008ea030 RCX: 00007fa8b2868487 [ 2924.054604] RDX: 0000000000000001 RSI: 0000000000000000 RDI: 00000000008f4360 [ 2924.058940] RBP: 00000000008f4360 R08: 0000000000000000 R09: 0000000000000014 [ 2924.063186] R10: 00000000000006b2 R11: 0000000000000246 R12: 00007fa8b2d7183c [ 2924.067418] R13: 0000000000000000 R14: 00000000008ea210 R15: 00007ffc39824fe0 [ 2924.071534] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer joydev input_leds serio_raw snd soundcore mac_hid i2c_piix4 ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi btrfs zstd_decompress zstd_compress xxhash raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq libcrc32c raid1 raid0 multipath linear 8139too qxl ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel psmouse aes_x86_64 8139cp crypto_simd cryptd mii glue_helper pata_acpi floppy [ 2924.098044] CR2: ffff88018f0db000 [ 2924.102520] ---[ end trace a8e0d899985faf31 ]--- [ 2924.107012] RIP: 0010:__memset+0x24/0x30 [ 2924.111448] Code: 90 90 90 90 90 90 66 66 90 66 90 49 89 f9 48 89 d1 83 e2 07 48 c1 e9 03 40 0f b6 f6 48 b8 01 01 01 01 01 01 01 01 48 0f af c6 48 ab 89 d1 f3 aa 4c 89 c8 c3 90 49 89 f9 40 88 f0 48 89 d1 f3 [ 2924.120724] RSP: 0018:ffff88018ddf7ae0 EFLAGS: 00010206 [ 2924.125312] RAX: 0000000000000000 RBX: ffff8801d549d888 RCX: 1ffffffffffdaffb [ 2924.129931] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff88018f0daffc [ 2924.134537] RBP: ffff88018efc206c R08: 1ffff10031df840d R09: ffff88018efc206c [ 2924.139175] R10: ffffffffffffe1ee R11: ffffed0031df65fa R12: 0000000000000000 [ 2924.143825] R13: ffff8801d549dc98 R14: 00000000ffffc3db R15: ffffea00063bec80 [ 2924.148500] FS: 00007fa8b2f8a840(0000) GS:ffff8801f3b00000(0000) knlGS:0000000000000000 [ 2924.153247] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2924.158003] CR2: ffff88018f0db000 CR3: 000000018f892000 CR4: 00000000000006e0 [ 2924.164641] BUG: Bad rss-counter state mm:00000000fa04621e idx:0 val:4 [ 2924.170007] BUG: Bad rss-counter tate mm:00000000fa04621e idx:1 val:2 - Location https://elixir.bootlin.com/linux/v4.18-rc3/source/fs/f2fs/inline.c#L78 memset(addr + from, 0, MAX_INLINE_DATA(inode) - from); Here the length can be negative. Reported-by Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/inode.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index aeed9943836a..9a40724dbaa6 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -183,6 +183,7 @@ void f2fs_inode_chksum_set(struct f2fs_sb_info *sbi, struct page *page) static bool sanity_check_inode(struct inode *inode, struct page *node_page) { struct f2fs_sb_info *sbi = F2FS_I_SB(inode); + struct f2fs_inode_info *fi = F2FS_I(inode); unsigned long long iblocks; iblocks = le64_to_cpu(F2FS_INODE(node_page)->i_blocks); @@ -215,6 +216,17 @@ static bool sanity_check_inode(struct inode *inode, struct page *node_page) return false; } + if (fi->i_extra_isize > F2FS_TOTAL_EXTRA_ATTR_SIZE || + fi->i_extra_isize % sizeof(__le32)) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "%s: inode (ino=%lx) has corrupted i_extra_isize: %d, " + "max: %zu", + __func__, inode->i_ino, fi->i_extra_isize, + F2FS_TOTAL_EXTRA_ATTR_SIZE); + return false; + } + if (F2FS_I(inode)->extent_tree) { struct extent_info *ei = &F2FS_I(inode)->extent_tree->largest; @@ -280,14 +292,14 @@ static int do_read_inode(struct inode *inode) get_inline_info(inode, ri); + fi->i_extra_isize = f2fs_has_extra_attr(inode) ? + le16_to_cpu(ri->i_extra_isize) : 0; + if (!sanity_check_inode(inode, node_page)) { f2fs_put_page(node_page, 1); return -EINVAL; } - fi->i_extra_isize = f2fs_has_extra_attr(inode) ? - le16_to_cpu(ri->i_extra_isize) : 0; - /* check data exist */ if (f2fs_has_inline_data(inode) && !f2fs_exist_data(inode)) __recover_inline_status(inode, node_page); -- GitLab From 30130700acfad8a705c109325379f5bbe21b3ccc Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Wed, 1 Aug 2018 19:16:11 +0800 Subject: [PATCH 0217/1286] f2fs: fix to do sanity check with cp_pack_start_sum commit e494c2f995d6181d6e29c4927d68e0f295ecf75b upstream. After fuzzing, cp_pack_start_sum could be corrupted, so current log's summary info should be wrong due to loading incorrect summary block. Then, if segment's type in current log is exceeded NR_CURSEG_TYPE, it can lead accessing invalid dirty_i->dirty_segmap bitmap finally. Add sanity check for cp_pack_start_sum to fix this issue. https://bugzilla.kernel.org/show_bug.cgi?id=200419 - Reproduce - Kernel message (f2fs-dev w/ KASAN) [ 3117.578432] F2FS-fs (loop0): Invalid log blocks per segment (8) [ 3117.578445] F2FS-fs (loop0): Can't find valid F2FS filesystem in 2th superblock [ 3117.581364] F2FS-fs (loop0): invalid crc_offset: 30716 [ 3117.583564] WARNING: CPU: 1 PID: 1225 at fs/f2fs/checkpoint.c:90 __get_meta_page+0x448/0x4b0 [ 3117.583570] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer joydev input_leds serio_raw snd soundcore mac_hid i2c_piix4 ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi btrfs zstd_decompress zstd_compress xxhash raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq libcrc32c raid1 raid0 multipath linear 8139too qxl ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel psmouse aes_x86_64 8139cp crypto_simd cryptd mii glue_helper pata_acpi floppy [ 3117.584014] CPU: 1 PID: 1225 Comm: mount Not tainted 4.17.0+ #1 [ 3117.584017] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3117.584022] RIP: 0010:__get_meta_page+0x448/0x4b0 [ 3117.584023] Code: 00 49 8d bc 24 84 00 00 00 e8 74 54 da ff 41 83 8c 24 84 00 00 00 08 4c 89 f6 4c 89 ef e8 c0 d9 95 00 48 89 ef e8 18 e3 00 00 <0f> 0b f0 80 4d 48 04 e9 0f fe ff ff 0f 0b 48 89 c7 48 89 04 24 e8 [ 3117.584072] RSP: 0018:ffff88018eb678c0 EFLAGS: 00010286 [ 3117.584082] RAX: ffff88018f0a6a78 RBX: ffffea0007a46600 RCX: ffffffff9314d1b2 [ 3117.584085] RDX: ffffffff00000001 RSI: 0000000000000000 RDI: ffff88018f0a6a98 [ 3117.584087] RBP: ffff88018ebe9980 R08: 0000000000000002 R09: 0000000000000001 [ 3117.584090] R10: 0000000000000001 R11: ffffed00326e4450 R12: ffff880193722200 [ 3117.584092] R13: ffff88018ebe9afc R14: 0000000000000206 R15: ffff88018eb67900 [ 3117.584096] FS: 00007f5694636840(0000) GS:ffff8801f3b00000(0000) knlGS:0000000000000000 [ 3117.584098] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3117.584101] CR2: 00000000016f21b8 CR3: 0000000191c22000 CR4: 00000000000006e0 [ 3117.584112] Call Trace: [ 3117.584121] ? f2fs_set_meta_page_dirty+0x150/0x150 [ 3117.584127] ? f2fs_build_segment_manager+0xbf9/0x3190 [ 3117.584133] ? f2fs_npages_for_summary_flush+0x75/0x120 [ 3117.584145] f2fs_build_segment_manager+0xda8/0x3190 [ 3117.584151] ? f2fs_get_valid_checkpoint+0x298/0xa00 [ 3117.584156] ? f2fs_flush_sit_entries+0x10e0/0x10e0 [ 3117.584184] ? map_id_range_down+0x17c/0x1b0 [ 3117.584188] ? __put_user_ns+0x30/0x30 [ 3117.584206] ? find_next_bit+0x53/0x90 [ 3117.584237] ? cpumask_next+0x16/0x20 [ 3117.584249] f2fs_fill_super+0x1948/0x2b40 [ 3117.584258] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.584279] ? sget_userns+0x65e/0x690 [ 3117.584296] ? set_blocksize+0x88/0x130 [ 3117.584302] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.584305] mount_bdev+0x1c0/0x200 [ 3117.584310] mount_fs+0x5c/0x190 [ 3117.584320] vfs_kern_mount+0x64/0x190 [ 3117.584330] do_mount+0x2e4/0x1450 [ 3117.584343] ? lockref_put_return+0x130/0x130 [ 3117.584347] ? copy_mount_string+0x20/0x20 [ 3117.584357] ? kasan_unpoison_shadow+0x31/0x40 [ 3117.584362] ? kasan_kmalloc+0xa6/0xd0 [ 3117.584373] ? memcg_kmem_put_cache+0x16/0x90 [ 3117.584377] ? __kmalloc_track_caller+0x196/0x210 [ 3117.584383] ? _copy_from_user+0x61/0x90 [ 3117.584396] ? memdup_user+0x3e/0x60 [ 3117.584401] ksys_mount+0x7e/0xd0 [ 3117.584405] __x64_sys_mount+0x62/0x70 [ 3117.584427] do_syscall_64+0x73/0x160 [ 3117.584440] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 3117.584455] RIP: 0033:0x7f5693f14b9a [ 3117.584456] Code: 48 8b 0d 01 c3 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ce c2 2b 00 f7 d8 64 89 01 48 [ 3117.584505] RSP: 002b:00007fff27346488 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5 [ 3117.584510] RAX: ffffffffffffffda RBX: 00000000016e2030 RCX: 00007f5693f14b9a [ 3117.584512] RDX: 00000000016e2210 RSI: 00000000016e3f30 RDI: 00000000016ee040 [ 3117.584514] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000013 [ 3117.584516] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 00000000016ee040 [ 3117.584519] R13: 00000000016e2210 R14: 0000000000000000 R15: 0000000000000003 [ 3117.584523] ---[ end trace a8e0d899985faf31 ]--- [ 3117.685663] F2FS-fs (loop0): f2fs_check_nid_range: out-of-range nid=2, run fsck to fix. [ 3117.685673] F2FS-fs (loop0): recover_data: ino = 2 (i_size: recover) recovered = 1, err = 0 [ 3117.685707] ================================================================== [ 3117.685955] BUG: KASAN: slab-out-of-bounds in __remove_dirty_segment+0xdd/0x1e0 [ 3117.686175] Read of size 8 at addr ffff88018f0a63d0 by task mount/1225 [ 3117.686477] CPU: 0 PID: 1225 Comm: mount Tainted: G W 4.17.0+ #1 [ 3117.686481] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3117.686483] Call Trace: [ 3117.686494] dump_stack+0x71/0xab [ 3117.686512] print_address_description+0x6b/0x290 [ 3117.686517] kasan_report+0x28e/0x390 [ 3117.686522] ? __remove_dirty_segment+0xdd/0x1e0 [ 3117.686527] __remove_dirty_segment+0xdd/0x1e0 [ 3117.686532] locate_dirty_segment+0x189/0x190 [ 3117.686538] f2fs_allocate_new_segments+0xa9/0xe0 [ 3117.686543] recover_data+0x703/0x2c20 [ 3117.686547] ? f2fs_recover_fsync_data+0x48f/0xd50 [ 3117.686553] ? ksys_mount+0x7e/0xd0 [ 3117.686564] ? policy_nodemask+0x1a/0x90 [ 3117.686567] ? policy_node+0x56/0x70 [ 3117.686571] ? add_fsync_inode+0xf0/0xf0 [ 3117.686592] ? blk_finish_plug+0x44/0x60 [ 3117.686597] ? f2fs_ra_meta_pages+0x38b/0x5e0 [ 3117.686602] ? find_inode_fast+0xac/0xc0 [ 3117.686606] ? f2fs_is_valid_blkaddr+0x320/0x320 [ 3117.686618] ? __radix_tree_lookup+0x150/0x150 [ 3117.686633] ? dqget+0x670/0x670 [ 3117.686648] ? pagecache_get_page+0x29/0x410 [ 3117.686656] ? kmem_cache_alloc+0x176/0x1e0 [ 3117.686660] ? f2fs_is_valid_blkaddr+0x11d/0x320 [ 3117.686664] f2fs_recover_fsync_data+0xc23/0xd50 [ 3117.686670] ? f2fs_space_for_roll_forward+0x60/0x60 [ 3117.686674] ? rb_insert_color+0x323/0x3d0 [ 3117.686678] ? f2fs_recover_orphan_inodes+0xa5/0x700 [ 3117.686683] ? proc_register+0x153/0x1d0 [ 3117.686686] ? f2fs_remove_orphan_inode+0x10/0x10 [ 3117.686695] ? f2fs_attr_store+0x50/0x50 [ 3117.686700] ? proc_create_single_data+0x52/0x60 [ 3117.686707] f2fs_fill_super+0x1d06/0x2b40 [ 3117.686728] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.686735] ? sget_userns+0x65e/0x690 [ 3117.686740] ? set_blocksize+0x88/0x130 [ 3117.686745] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.686748] mount_bdev+0x1c0/0x200 [ 3117.686753] mount_fs+0x5c/0x190 [ 3117.686758] vfs_kern_mount+0x64/0x190 [ 3117.686762] do_mount+0x2e4/0x1450 [ 3117.686769] ? lockref_put_return+0x130/0x130 [ 3117.686773] ? copy_mount_string+0x20/0x20 [ 3117.686777] ? kasan_unpoison_shadow+0x31/0x40 [ 3117.686780] ? kasan_kmalloc+0xa6/0xd0 [ 3117.686786] ? memcg_kmem_put_cache+0x16/0x90 [ 3117.686790] ? __kmalloc_track_caller+0x196/0x210 [ 3117.686795] ? _copy_from_user+0x61/0x90 [ 3117.686801] ? memdup_user+0x3e/0x60 [ 3117.686804] ksys_mount+0x7e/0xd0 [ 3117.686809] __x64_sys_mount+0x62/0x70 [ 3117.686816] do_syscall_64+0x73/0x160 [ 3117.686824] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 3117.686829] RIP: 0033:0x7f5693f14b9a [ 3117.686830] Code: 48 8b 0d 01 c3 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ce c2 2b 00 f7 d8 64 89 01 48 [ 3117.686887] RSP: 002b:00007fff27346488 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5 [ 3117.686892] RAX: ffffffffffffffda RBX: 00000000016e2030 RCX: 00007f5693f14b9a [ 3117.686894] RDX: 00000000016e2210 RSI: 00000000016e3f30 RDI: 00000000016ee040 [ 3117.686896] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000013 [ 3117.686899] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 00000000016ee040 [ 3117.686901] R13: 00000000016e2210 R14: 0000000000000000 R15: 0000000000000003 [ 3117.687005] Allocated by task 1225: [ 3117.687152] kasan_kmalloc+0xa6/0xd0 [ 3117.687157] kmem_cache_alloc_trace+0xfd/0x200 [ 3117.687161] f2fs_build_segment_manager+0x2d09/0x3190 [ 3117.687165] f2fs_fill_super+0x1948/0x2b40 [ 3117.687168] mount_bdev+0x1c0/0x200 [ 3117.687171] mount_fs+0x5c/0x190 [ 3117.687174] vfs_kern_mount+0x64/0x190 [ 3117.687177] do_mount+0x2e4/0x1450 [ 3117.687180] ksys_mount+0x7e/0xd0 [ 3117.687182] __x64_sys_mount+0x62/0x70 [ 3117.687186] do_syscall_64+0x73/0x160 [ 3117.687190] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 3117.687285] Freed by task 19: [ 3117.687412] __kasan_slab_free+0x137/0x190 [ 3117.687416] kfree+0x8b/0x1b0 [ 3117.687460] ttm_bo_man_put_node+0x61/0x80 [ttm] [ 3117.687476] ttm_bo_cleanup_refs+0x15f/0x250 [ttm] [ 3117.687492] ttm_bo_delayed_delete+0x2f0/0x300 [ttm] [ 3117.687507] ttm_bo_delayed_workqueue+0x17/0x50 [ttm] [ 3117.687528] process_one_work+0x2f9/0x740 [ 3117.687531] worker_thread+0x78/0x6b0 [ 3117.687541] kthread+0x177/0x1c0 [ 3117.687545] ret_from_fork+0x35/0x40 [ 3117.687638] The buggy address belongs to the object at ffff88018f0a6300 which belongs to the cache kmalloc-192 of size 192 [ 3117.688014] The buggy address is located 16 bytes to the right of 192-byte region [ffff88018f0a6300, ffff88018f0a63c0) [ 3117.688382] The buggy address belongs to the page: [ 3117.688554] page:ffffea00063c2980 count:1 mapcount:0 mapping:ffff8801f3403180 index:0x0 [ 3117.688788] flags: 0x17fff8000000100(slab) [ 3117.688944] raw: 017fff8000000100 ffffea00063c2840 0000000e0000000e ffff8801f3403180 [ 3117.689166] raw: 0000000000000000 0000000080100010 00000001ffffffff 0000000000000000 [ 3117.689386] page dumped because: kasan: bad access detected [ 3117.689653] Memory state around the buggy address: [ 3117.689816] ffff88018f0a6280: fb fb fb fb fb fb fb fb fc fc fc fc fc fc fc fc [ 3117.690027] ffff88018f0a6300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 3117.690239] >ffff88018f0a6380: 00 00 fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 3117.690448] ^ [ 3117.690644] ffff88018f0a6400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 3117.690868] ffff88018f0a6480: 00 00 fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 3117.691077] ================================================================== [ 3117.691290] Disabling lock debugging due to kernel taint [ 3117.693893] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [ 3117.694120] PGD 80000001f01bc067 P4D 80000001f01bc067 PUD 1d9638067 PMD 0 [ 3117.694338] Oops: 0002 [#1] SMP KASAN PTI [ 3117.694490] CPU: 1 PID: 1225 Comm: mount Tainted: G B W 4.17.0+ #1 [ 3117.694703] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3117.695073] RIP: 0010:__remove_dirty_segment+0xe2/0x1e0 [ 3117.695246] Code: c4 48 89 c7 e8 cf bb d7 ff 45 0f b6 24 24 41 83 e4 3f 44 88 64 24 07 41 83 e4 3f 4a 8d 7c e3 08 e8 b3 bc d7 ff 4a 8b 4c e3 08 4c 0f b3 29 0f 82 94 00 00 00 48 8d bd 20 04 00 00 e8 97 bb d7 [ 3117.695793] RSP: 0018:ffff88018eb67638 EFLAGS: 00010292 [ 3117.695969] RAX: 0000000000000000 RBX: ffff88018f0a6300 RCX: 0000000000000000 [ 3117.696182] RDX: 0000000000000000 RSI: 0000000000000297 RDI: 0000000000000297 [ 3117.696391] RBP: ffff88018ebe9980 R08: ffffed003e743ebb R09: ffffed003e743ebb [ 3117.696604] R10: 0000000000000001 R11: ffffed003e743eba R12: 0000000000000019 [ 3117.696813] R13: 0000000000000014 R14: 0000000000000320 R15: ffff88018ebe99e0 [ 3117.697032] FS: 00007f5694636840(0000) GS:ffff8801f3b00000(0000) knlGS:0000000000000000 [ 3117.697280] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3117.702357] CR2: 00007fe89bb1a000 CR3: 0000000191c22000 CR4: 00000000000006e0 [ 3117.707235] Call Trace: [ 3117.712077] locate_dirty_segment+0x189/0x190 [ 3117.716891] f2fs_allocate_new_segments+0xa9/0xe0 [ 3117.721617] recover_data+0x703/0x2c20 [ 3117.726316] ? f2fs_recover_fsync_data+0x48f/0xd50 [ 3117.730957] ? ksys_mount+0x7e/0xd0 [ 3117.735573] ? policy_nodemask+0x1a/0x90 [ 3117.740198] ? policy_node+0x56/0x70 [ 3117.744829] ? add_fsync_inode+0xf0/0xf0 [ 3117.749487] ? blk_finish_plug+0x44/0x60 [ 3117.754152] ? f2fs_ra_meta_pages+0x38b/0x5e0 [ 3117.758831] ? find_inode_fast+0xac/0xc0 [ 3117.763448] ? f2fs_is_valid_blkaddr+0x320/0x320 [ 3117.768046] ? __radix_tree_lookup+0x150/0x150 [ 3117.772603] ? dqget+0x670/0x670 [ 3117.777159] ? pagecache_get_page+0x29/0x410 [ 3117.781648] ? kmem_cache_alloc+0x176/0x1e0 [ 3117.786067] ? f2fs_is_valid_blkaddr+0x11d/0x320 [ 3117.790476] f2fs_recover_fsync_data+0xc23/0xd50 [ 3117.794790] ? f2fs_space_for_roll_forward+0x60/0x60 [ 3117.799086] ? rb_insert_color+0x323/0x3d0 [ 3117.803304] ? f2fs_recover_orphan_inodes+0xa5/0x700 [ 3117.807563] ? proc_register+0x153/0x1d0 [ 3117.811766] ? f2fs_remove_orphan_inode+0x10/0x10 [ 3117.815947] ? f2fs_attr_store+0x50/0x50 [ 3117.820087] ? proc_create_single_data+0x52/0x60 [ 3117.824262] f2fs_fill_super+0x1d06/0x2b40 [ 3117.828367] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.832432] ? sget_userns+0x65e/0x690 [ 3117.836500] ? set_blocksize+0x88/0x130 [ 3117.840501] ? f2fs_commit_super+0x1a0/0x1a0 [ 3117.844420] mount_bdev+0x1c0/0x200 [ 3117.848275] mount_fs+0x5c/0x190 [ 3117.852053] vfs_kern_mount+0x64/0x190 [ 3117.855810] do_mount+0x2e4/0x1450 [ 3117.859441] ? lockref_put_return+0x130/0x130 [ 3117.862996] ? copy_mount_string+0x20/0x20 [ 3117.866417] ? kasan_unpoison_shadow+0x31/0x40 [ 3117.869719] ? kasan_kmalloc+0xa6/0xd0 [ 3117.872948] ? memcg_kmem_put_cache+0x16/0x90 [ 3117.876121] ? __kmalloc_track_caller+0x196/0x210 [ 3117.879333] ? _copy_from_user+0x61/0x90 [ 3117.882467] ? memdup_user+0x3e/0x60 [ 3117.885604] ksys_mount+0x7e/0xd0 [ 3117.888700] __x64_sys_mount+0x62/0x70 [ 3117.891742] do_syscall_64+0x73/0x160 [ 3117.894692] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 3117.897669] RIP: 0033:0x7f5693f14b9a [ 3117.900563] Code: 48 8b 0d 01 c3 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ce c2 2b 00 f7 d8 64 89 01 48 [ 3117.906922] RSP: 002b:00007fff27346488 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5 [ 3117.910159] RAX: ffffffffffffffda RBX: 00000000016e2030 RCX: 00007f5693f14b9a [ 3117.913469] RDX: 00000000016e2210 RSI: 00000000016e3f30 RDI: 00000000016ee040 [ 3117.916764] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000013 [ 3117.920071] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 00000000016ee040 [ 3117.923393] R13: 00000000016e2210 R14: 0000000000000000 R15: 0000000000000003 [ 3117.926680] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer joydev input_leds serio_raw snd soundcore mac_hid i2c_piix4 ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi btrfs zstd_decompress zstd_compress xxhash raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor async_tx xor raid6_pq libcrc32c raid1 raid0 multipath linear 8139too qxl ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel psmouse aes_x86_64 8139cp crypto_simd cryptd mii glue_helper pata_acpi floppy [ 3117.949979] CR2: 0000000000000000 [ 3117.954283] ---[ end trace a8e0d899985faf32 ]--- [ 3117.958575] RIP: 0010:__remove_dirty_segment+0xe2/0x1e0 [ 3117.962810] Code: c4 48 89 c7 e8 cf bb d7 ff 45 0f b6 24 24 41 83 e4 3f 44 88 64 24 07 41 83 e4 3f 4a 8d 7c e3 08 e8 b3 bc d7 ff 4a 8b 4c e3 08 4c 0f b3 29 0f 82 94 00 00 00 48 8d bd 20 04 00 00 e8 97 bb d7 [ 3117.971789] RSP: 0018:ffff88018eb67638 EFLAGS: 00010292 [ 3117.976333] RAX: 0000000000000000 RBX: ffff88018f0a6300 RCX: 0000000000000000 [ 3117.980926] RDX: 0000000000000000 RSI: 0000000000000297 RDI: 0000000000000297 [ 3117.985497] RBP: ffff88018ebe9980 R08: ffffed003e743ebb R09: ffffed003e743ebb [ 3117.990098] R10: 0000000000000001 R11: ffffed003e743eba R12: 0000000000000019 [ 3117.994761] R13: 0000000000000014 R14: 0000000000000320 R15: ffff88018ebe99e0 [ 3117.999392] FS: 00007f5694636840(0000) GS:ffff8801f3b00000(0000) knlGS:0000000000000000 [ 3118.004096] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3118.008816] CR2: 00007fe89bb1a000 CR3: 0000000191c22000 CR4: 00000000000006e0 - Location https://elixir.bootlin.com/linux/v4.18-rc3/source/fs/f2fs/segment.c#L775 if (test_and_clear_bit(segno, dirty_i->dirty_segmap[t])) dirty_i->nr_dirty[t]--; Here dirty_i->dirty_segmap[t] can be NULL which leads to crash in test_and_clear_bit() Reported-by Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: The function is called sanity_check_ckpt()] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 8 ++++---- fs/f2fs/super.c | 12 ++++++++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index c81cd5057b8e..624817eeb25e 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -825,15 +825,15 @@ int get_valid_checkpoint(struct f2fs_sb_info *sbi) cp_block = (struct f2fs_checkpoint *)page_address(cur_page); memcpy(sbi->ckpt, cp_block, blk_size); - /* Sanity checking of checkpoint */ - if (sanity_check_ckpt(sbi)) - goto free_fail_no_cp; - if (cur_page == cp1) sbi->cur_cp_pack = 1; else sbi->cur_cp_pack = 2; + /* Sanity checking of checkpoint */ + if (sanity_check_ckpt(sbi)) + goto free_fail_no_cp; + if (cp_blks <= 1) goto done; diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index 9fafb1404f39..de4de4ebe64c 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -1957,6 +1957,7 @@ int sanity_check_ckpt(struct f2fs_sb_info *sbi) unsigned int sit_bitmap_size, nat_bitmap_size; unsigned int log_blocks_per_seg; unsigned int segment_count_main; + unsigned int cp_pack_start_sum, cp_payload; block_t user_block_count; int i; @@ -2017,6 +2018,17 @@ int sanity_check_ckpt(struct f2fs_sb_info *sbi) return 1; } + cp_pack_start_sum = __start_sum_addr(sbi); + cp_payload = __cp_payload(sbi); + if (cp_pack_start_sum < cp_payload + 1 || + cp_pack_start_sum > blocks_per_seg - 1 - + NR_CURSEG_TYPE) { + f2fs_msg(sbi->sb, KERN_ERR, + "Wrong cp_pack_start_sum: %u", + cp_pack_start_sum); + return 1; + } + if (unlikely(f2fs_cp_error(sbi))) { f2fs_msg(sbi->sb, KERN_ERR, "A bug case: need to run fsck"); return 1; -- GitLab From cb7ccb9924bb3596f211badf0d2becf131a979cd Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Tue, 17 Apr 2018 19:10:15 -0700 Subject: [PATCH 0218/1286] xfs: don't fail when converting shortform attr to long form during ATTR_REPLACE commit 7b38460dc8e4eafba06c78f8e37099d3b34d473c upstream. Kanda Motohiro reported that expanding a tiny xattr into a large xattr fails on XFS because we remove the tiny xattr from a shortform fork and then try to re-add it after converting the fork to extents format having not removed the ATTR_REPLACE flag. This fails because the attr is no longer present, causing a fs shutdown. This is derived from the patch in his bug report, but we really shouldn't ignore a nonzero retval from the remove call. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=199119 Reported-by: kanda.motohiro@gmail.com Reviewed-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Darrick J. Wong Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/xfs/libxfs/xfs_attr.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fs/xfs/libxfs/xfs_attr.c b/fs/xfs/libxfs/xfs_attr.c index 6249c92671de..ea66f04f46f7 100644 --- a/fs/xfs/libxfs/xfs_attr.c +++ b/fs/xfs/libxfs/xfs_attr.c @@ -501,7 +501,14 @@ xfs_attr_shortform_addname(xfs_da_args_t *args) if (args->flags & ATTR_CREATE) return retval; retval = xfs_attr_shortform_remove(args); - ASSERT(retval == 0); + if (retval) + return retval; + /* + * Since we have removed the old attr, clear ATTR_REPLACE so + * that the leaf format add routine won't trip over the attr + * not being around. + */ + args->flags &= ~ATTR_REPLACE; } if (args->namelen >= XFS_ATTR_SF_ENTSIZE_MAX || -- GitLab From 04d269610ea35656fe4d9609f5a5fa043daa866e Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 2 Dec 2018 10:03:24 -0500 Subject: [PATCH 0219/1286] Revert "wlcore: Add missing PM call for wlcore_cmd_wait_for_event_or_timeout()" This reverts commit e87efc44dd36ba3db59847c418354711ebad779b which was upstream commit 4ec7cece87b3ed21ffcd407c62fb2f151a366bc1. From Dietmar May's report on the stable mailing list (https://www.spinics.net/lists/stable/msg272201.html): > I've run into some problems which appear due to (a) recent patch(es) on > the wlcore wifi driver. > > 4.4.160 - commit 3fdd34643ffc378b5924941fad40352c04610294 > 4.9.131 - commit afeeecc764436f31d4447575bb9007732333818c > > Earlier versions (4.9.130 and 4.4.159 - tested back to 4.4.49) do not > exhibit this problem. It is still present in 4.9.141. > > master as of 4.20.0-rc4 does not exhibit this problem. > > Basically, during client association when in AP mode (running hostapd), > handshake may or may not complete following a noticeable delay. If > successful, then the driver fails consistently in warn_slowpath_null > during disassociation. If unsuccessful, the wifi client attempts multiple > times, sometimes failing repeatedly. I've had clients unable to connect > for 3-5 minutes during testing, with the syslog filled with dozens of > backtraces. syslog details are below. > > I'm working on an embedded device with a TI 3352 ARM processor and a > murata wl1271 module in sdio mode. We're running a fully patched ubuntu > 18.04 ARM build, with a kernel built from kernel.org's stable/linux repo . > Relevant parts of the kernel config are included below. > > The commit message states: > > > /I've only seen this few times with the runtime PM patches enabled so > > this one is probably not needed before that. This seems to work > > currently based on the current PM implementation timer. Let's apply > > this separately though in case others are hitting this issue./ > We're not doing anything explicit with power management. The device is an > IoT edge gateway with battery backup, normally running on wall power. The > battery is currently used solely to shut down the system cleanly to avoid > filesystem corruption. > > The device tree is configured to keep power in suspend; but the device > should never suspend, so in our case, there is no need to call > wl1271_ps_elp_wakeup() or wl1271_ps_elp_sleep(), as occurs in the patch. Signed-off-by: Sasha Levin --- drivers/net/wireless/ti/wlcore/cmd.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/wireless/ti/wlcore/cmd.c b/drivers/net/wireless/ti/wlcore/cmd.c index f48c3f62966d..761cf8573a80 100644 --- a/drivers/net/wireless/ti/wlcore/cmd.c +++ b/drivers/net/wireless/ti/wlcore/cmd.c @@ -35,7 +35,6 @@ #include "wl12xx_80211.h" #include "cmd.h" #include "event.h" -#include "ps.h" #include "tx.h" #include "hw_ops.h" @@ -192,10 +191,6 @@ int wlcore_cmd_wait_for_event_or_timeout(struct wl1271 *wl, timeout_time = jiffies + msecs_to_jiffies(WL1271_EVENT_TIMEOUT); - ret = wl1271_ps_elp_wakeup(wl); - if (ret < 0) - return ret; - do { if (time_after(jiffies, timeout_time)) { wl1271_debug(DEBUG_CMD, "timeout waiting for event %d", @@ -227,7 +222,6 @@ int wlcore_cmd_wait_for_event_or_timeout(struct wl1271 *wl, } while (!event); out: - wl1271_ps_elp_sleep(wl); kfree(events_vector); return ret; } -- GitLab From 3a8a411c927716fad4004a6953a5b2cf988eb2df Mon Sep 17 00:00:00 2001 From: Petr Machata Date: Tue, 20 Nov 2018 11:39:56 +0000 Subject: [PATCH 0220/1286] net: skb_scrub_packet(): Scrub offload_fwd_mark [ Upstream commit b5dd186d10ba59e6b5ba60e42b3b083df56df6f3 ] When a packet is trapped and the corresponding SKB marked as already-forwarded, it retains this marking even after it is forwarded across veth links into another bridge. There, since it ingresses the bridge over veth, which doesn't have offload_fwd_mark, it triggers a warning in nbp_switchdev_frame_mark(). Then nbp_switchdev_allowed_egress() decides not to allow egress from this bridge through another veth, because the SKB is already marked, and the mark (of 0) of course matches. Thus the packet is incorrectly blocked. Solve by resetting offload_fwd_mark() in skb_scrub_packet(). That function is called from tunnels and also from veth, and thus catches the cases where traffic is forwarded between bridges and transformed in a way that invalidates the marking. Fixes: 6bc506b4fb06 ("bridge: switchdev: Add forward mark support for stacked devices") Fixes: abf4bb6b63d0 ("skbuff: Add the offload_mr_fwd_mark field") Signed-off-by: Petr Machata Suggested-by: Ido Schimmel Acked-by: Jiri Pirko Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/core/skbuff.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index c19a118f9f82..4067fa3fcbb2 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4882,6 +4882,10 @@ void skb_scrub_packet(struct sk_buff *skb, bool xnet) nf_reset(skb); nf_reset_trace(skb); +#ifdef CONFIG_NET_SWITCHDEV + skb->offload_fwd_mark = 0; +#endif + if (!xnet) return; -- GitLab From 44e4f3644934b65c91bc05245a9447dde2c7af40 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Wed, 21 Nov 2018 16:32:10 +0100 Subject: [PATCH 0221/1286] net: thunderx: set xdp_prog to NULL if bpf_prog_add fails [ Upstream commit 6d0f60b0f8588fd4380ea5df9601e12fddd55ce2 ] Set xdp_prog pointer to NULL if bpf_prog_add fails since that routine reports the error code instead of NULL in case of failure and xdp_prog pointer value is used in the driver to verify if XDP is currently enabled. Moreover report the error code to userspace if nicvf_xdp_setup fails Fixes: 05c773f52b96 ("net: thunderx: Add basic XDP support") Signed-off-by: Lorenzo Bianconi Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/cavium/thunder/nicvf_main.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c index 2237ef8e4344..f13256af8031 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c @@ -1691,6 +1691,7 @@ static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) bool if_up = netif_running(nic->netdev); struct bpf_prog *old_prog; bool bpf_attached = false; + int ret = 0; /* For now just support only the usual MTU sized frames */ if (prog && (dev->mtu > 1500)) { @@ -1724,8 +1725,12 @@ static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) if (nic->xdp_prog) { /* Attach BPF program */ nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1); - if (!IS_ERR(nic->xdp_prog)) + if (!IS_ERR(nic->xdp_prog)) { bpf_attached = true; + } else { + ret = PTR_ERR(nic->xdp_prog); + nic->xdp_prog = NULL; + } } /* Calculate Tx queues needed for XDP and network stack */ @@ -1737,7 +1742,7 @@ static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) netif_trans_update(nic->netdev); } - return 0; + return ret; } static int nicvf_xdp(struct net_device *netdev, struct netdev_xdp *xdp) -- GitLab From e5cfda6c5d04a04e9ec9834925e590f7e921c57f Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 22 Nov 2018 14:36:30 +0800 Subject: [PATCH 0222/1286] virtio-net: disable guest csum during XDP set [ Upstream commit e59ff2c49ae16e1d179de679aca81405829aee6c ] We don't disable VIRTIO_NET_F_GUEST_CSUM if XDP was set. This means we can receive partial csumed packets with metadata kept in the vnet_hdr. This may have several side effects: - It could be overridden by header adjustment, thus is might be not correct after XDP processing. - There's no way to pass such metadata information through XDP_REDIRECT to another driver. - XDP does not support checksum offload right now. So simply disable guest csum if possible in this the case of XDP. Fixes: 3f93522ffab2d ("virtio-net: switch off offloads on demand if possible on XDP set") Reported-by: Jesper Dangaard Brouer Cc: Jesper Dangaard Brouer Cc: Pavel Popa Cc: David Ahern Signed-off-by: Jason Wang Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/virtio_net.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index f528e9ac3413..2ffa7b290591 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -61,7 +61,8 @@ static const unsigned long guest_offloads[] = { VIRTIO_NET_F_GUEST_TSO4, VIRTIO_NET_F_GUEST_TSO6, VIRTIO_NET_F_GUEST_ECN, - VIRTIO_NET_F_GUEST_UFO + VIRTIO_NET_F_GUEST_UFO, + VIRTIO_NET_F_GUEST_CSUM }; struct virtnet_stats { @@ -1939,9 +1940,6 @@ static int virtnet_clear_guest_offloads(struct virtnet_info *vi) if (!vi->guest_offloads) return 0; - if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_CSUM)) - offloads = 1ULL << VIRTIO_NET_F_GUEST_CSUM; - return virtnet_set_guest_offloads(vi, offloads); } @@ -1951,8 +1949,6 @@ static int virtnet_restore_guest_offloads(struct virtnet_info *vi) if (!vi->guest_offloads) return 0; - if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_CSUM)) - offloads |= 1ULL << VIRTIO_NET_F_GUEST_CSUM; return virtnet_set_guest_offloads(vi, offloads); } -- GitLab From 0435cabc0d6a0f0ebb60589a9ad28d1a3aecd748 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 22 Nov 2018 14:36:31 +0800 Subject: [PATCH 0223/1286] virtio-net: fail XDP set if guest csum is negotiated [ Upstream commit 18ba58e1c234ea1a2d9835ac8c1735d965ce4640 ] We don't support partial csumed packet since its metadata will be lost or incorrect during XDP processing. So fail the XDP set if guest_csum feature is negotiated. Fixes: f600b6905015 ("virtio_net: Add XDP support") Reported-by: Jesper Dangaard Brouer Cc: Jesper Dangaard Brouer Cc: Pavel Popa Cc: David Ahern Signed-off-by: Jason Wang Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/virtio_net.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 2ffa7b290591..0e8e3be50332 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -1966,8 +1966,9 @@ static int virtnet_xdp_set(struct net_device *dev, struct bpf_prog *prog, && (virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_TSO4) || virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_TSO6) || virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_ECN) || - virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_UFO))) { - NL_SET_ERR_MSG_MOD(extack, "Can't set XDP while host is implementing LRO, disable LRO first"); + virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_UFO) || + virtio_has_feature(vi->vdev, VIRTIO_NET_F_GUEST_CSUM))) { + NL_SET_ERR_MSG_MOD(extack, "Can't set XDP while host is implementing LRO/CSUM, disable LRO/CSUM first"); return -EOPNOTSUPP; } -- GitLab From 42412faf1a9356e6967c5c5fc530fe0ab5e32e9f Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Fri, 23 Nov 2018 18:28:01 +0100 Subject: [PATCH 0224/1286] net: thunderx: set tso_hdrs pointer to NULL in nicvf_free_snd_queue [ Upstream commit ef2a7cf1d8831535b8991459567b385661eb4a36 ] Reset snd_queue tso_hdrs pointer to NULL in nicvf_free_snd_queue routine since it is used to check if tso dma descriptor queue has been previously allocated. The issue can be triggered with the following reproducer: $ip link set dev enP2p1s0v0 xdpdrv obj xdp_dummy.o $ip link set dev enP2p1s0v0 xdpdrv off [ 341.467649] WARNING: CPU: 74 PID: 2158 at mm/vmalloc.c:1511 __vunmap+0x98/0xe0 [ 341.515010] Hardware name: GIGABYTE H270-T70/MT70-HD0, BIOS T49 02/02/2018 [ 341.521874] pstate: 60400005 (nZCv daif +PAN -UAO) [ 341.526654] pc : __vunmap+0x98/0xe0 [ 341.530132] lr : __vunmap+0x98/0xe0 [ 341.533609] sp : ffff00001c5db860 [ 341.536913] x29: ffff00001c5db860 x28: 0000000000020000 [ 341.542214] x27: ffff810feb5090b0 x26: ffff000017e57000 [ 341.547515] x25: 0000000000000000 x24: 00000000fbd00000 [ 341.552816] x23: 0000000000000000 x22: ffff810feb5090b0 [ 341.558117] x21: 0000000000000000 x20: 0000000000000000 [ 341.563418] x19: ffff000017e57000 x18: 0000000000000000 [ 341.568719] x17: 0000000000000000 x16: 0000000000000000 [ 341.574020] x15: 0000000000000010 x14: ffffffffffffffff [ 341.579321] x13: ffff00008985eb27 x12: ffff00000985eb2f [ 341.584622] x11: ffff0000096b3000 x10: ffff00001c5db510 [ 341.589923] x9 : 00000000ffffffd0 x8 : ffff0000086868e8 [ 341.595224] x7 : 3430303030303030 x6 : 00000000000006ef [ 341.600525] x5 : 00000000003fffff x4 : 0000000000000000 [ 341.605825] x3 : 0000000000000000 x2 : ffffffffffffffff [ 341.611126] x1 : ffff0000096b3728 x0 : 0000000000000038 [ 341.616428] Call trace: [ 341.618866] __vunmap+0x98/0xe0 [ 341.621997] vunmap+0x3c/0x50 [ 341.624961] arch_dma_free+0x68/0xa0 [ 341.628534] dma_direct_free+0x50/0x80 [ 341.632285] nicvf_free_resources+0x160/0x2d8 [nicvf] [ 341.637327] nicvf_config_data_transfer+0x174/0x5e8 [nicvf] [ 341.642890] nicvf_stop+0x298/0x340 [nicvf] [ 341.647066] __dev_close_many+0x9c/0x108 [ 341.650977] dev_close_many+0xa4/0x158 [ 341.654720] rollback_registered_many+0x140/0x530 [ 341.659414] rollback_registered+0x54/0x80 [ 341.663499] unregister_netdevice_queue+0x9c/0xe8 [ 341.668192] unregister_netdev+0x28/0x38 [ 341.672106] nicvf_remove+0xa4/0xa8 [nicvf] [ 341.676280] nicvf_shutdown+0x20/0x30 [nicvf] [ 341.680630] pci_device_shutdown+0x44/0x88 [ 341.684720] device_shutdown+0x144/0x250 [ 341.688640] kernel_restart_prepare+0x44/0x50 [ 341.692986] kernel_restart+0x20/0x68 [ 341.696638] __se_sys_reboot+0x210/0x238 [ 341.700550] __arm64_sys_reboot+0x24/0x30 [ 341.704555] el0_svc_handler+0x94/0x110 [ 341.708382] el0_svc+0x8/0xc [ 341.711252] ---[ end trace 3f4019c8439959c9 ]--- [ 341.715874] page:ffff7e0003ef4000 count:0 mapcount:0 mapping:0000000000000000 index:0x4 [ 341.723872] flags: 0x1fffe000000000() [ 341.727527] raw: 001fffe000000000 ffff7e0003f1a008 ffff7e0003ef4048 0000000000000000 [ 341.735263] raw: 0000000000000004 0000000000000000 00000000ffffffff 0000000000000000 [ 341.742994] page dumped because: VM_BUG_ON_PAGE(page_ref_count(page) == 0) where xdp_dummy.c is a simple bpf program that forwards the incoming frames to the network stack (available here: https://github.com/altoor/xdp_walkthrough_examples/blob/master/sample_1/xdp_dummy.c) Fixes: 05c773f52b96 ("net: thunderx: Add basic XDP support") Fixes: 4863dea3fab0 ("net: Adding support for Cavium ThunderX network controller") Signed-off-by: Lorenzo Bianconi Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c index a3d12dbde95b..09494e1c77c5 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c @@ -585,10 +585,12 @@ static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) if (!sq->dmem.base) return; - if (sq->tso_hdrs) + if (sq->tso_hdrs) { dma_free_coherent(&nic->pdev->dev, sq->dmem.q_len * TSO_HEADER_SIZE, sq->tso_hdrs, sq->tso_hdrs_phys); + sq->tso_hdrs = NULL; + } /* Free pending skbs in the queue */ smp_rmb(); -- GitLab From 67f6fba765ef8cb19089d476e3c367212a2fbdfd Mon Sep 17 00:00:00 2001 From: Willem de Bruijn Date: Tue, 20 Nov 2018 13:00:18 -0500 Subject: [PATCH 0225/1286] packet: copy user buffers before orphan or clone [ Upstream commit 5cd8d46ea1562be80063f53c7c6a5f40224de623 ] tpacket_snd sends packets with user pages linked into skb frags. It notifies that pages can be reused when the skb is released by setting skb->destructor to tpacket_destruct_skb. This can cause data corruption if the skb is orphaned (e.g., on transmit through veth) or cloned (e.g., on mirror to another psock). Create a kernel-private copy of data in these cases, same as tun/tap zerocopy transmission. Reuse that infrastructure: mark the skb as SKBTX_ZEROCOPY_FRAG, which will trigger copy in skb_orphan_frags(_rx). Unlike other zerocopy packets, do not set shinfo destructor_arg to struct ubuf_info. tpacket_destruct_skb already uses that ptr to notify when the original skb is released and a timestamp is recorded. Do not change this timestamp behavior. The ubuf_info->callback is not needed anyway, as no zerocopy notification is expected. Mark destructor_arg as not-a-uarg by setting the lower bit to 1. The resulting value is not a valid ubuf_info pointer, nor a valid tpacket_snd frame address. Add skb_zcopy_.._nouarg helpers for this. The fix relies on features introduced in commit 52267790ef52 ("sock: add MSG_ZEROCOPY"), so can be backported as is only to 4.14. Tested with from `./in_netns.sh ./txring_overwrite` from http://github.com/wdebruij/kerneltools/tests Fixes: 69e3c75f4d54 ("net: TX_RING and packet mmap") Reported-by: Anand H. Krishnan Signed-off-by: Willem de Bruijn Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- include/linux/skbuff.h | 18 +++++++++++++++++- net/packet/af_packet.c | 4 ++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index f64e88444082..f6250555ce7d 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -1288,6 +1288,22 @@ static inline void skb_zcopy_set(struct sk_buff *skb, struct ubuf_info *uarg) } } +static inline void skb_zcopy_set_nouarg(struct sk_buff *skb, void *val) +{ + skb_shinfo(skb)->destructor_arg = (void *)((uintptr_t) val | 0x1UL); + skb_shinfo(skb)->tx_flags |= SKBTX_ZEROCOPY_FRAG; +} + +static inline bool skb_zcopy_is_nouarg(struct sk_buff *skb) +{ + return (uintptr_t) skb_shinfo(skb)->destructor_arg & 0x1UL; +} + +static inline void *skb_zcopy_get_nouarg(struct sk_buff *skb) +{ + return (void *)((uintptr_t) skb_shinfo(skb)->destructor_arg & ~0x1UL); +} + /* Release a reference on a zerocopy structure */ static inline void skb_zcopy_clear(struct sk_buff *skb, bool zerocopy) { @@ -1297,7 +1313,7 @@ static inline void skb_zcopy_clear(struct sk_buff *skb, bool zerocopy) if (uarg->callback == sock_zerocopy_callback) { uarg->zerocopy = uarg->zerocopy && zerocopy; sock_zerocopy_put(uarg); - } else { + } else if (!skb_zcopy_is_nouarg(skb)) { uarg->callback(uarg, zerocopy); } diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 8d1a7c900393..88d5b2645bb0 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -2433,7 +2433,7 @@ static void tpacket_destruct_skb(struct sk_buff *skb) void *ph; __u32 ts; - ph = skb_shinfo(skb)->destructor_arg; + ph = skb_zcopy_get_nouarg(skb); packet_dec_pending(&po->tx_ring); ts = __packet_set_timestamp(po, ph, skb); @@ -2499,7 +2499,7 @@ static int tpacket_fill_skb(struct packet_sock *po, struct sk_buff *skb, skb->priority = po->sk.sk_priority; skb->mark = po->sk.sk_mark; sock_tx_timestamp(&po->sk, sockc->tsflags, &skb_shinfo(skb)->tx_flags); - skb_shinfo(skb)->destructor_arg = ph.raw; + skb_zcopy_set_nouarg(skb, ph.raw); skb_reserve(skb, hlen); skb_reset_network_header(skb); -- GitLab From 47897682fe041a5898cfd30a5f24d3173e856d5a Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Wed, 28 Nov 2018 14:53:19 +0800 Subject: [PATCH 0226/1286] rapidio/rionet: do not free skb before reading its length [ Upstream commit cfc435198f53a6fa1f656d98466b24967ff457d0 ] skb is freed via dev_kfree_skb_any, however, skb->len is read then. This may result in a use-after-free bug. Fixes: e6161d64263 ("rapidio/rionet: rework driver initialization and removal") Signed-off-by: Pan Bian Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/rionet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/rionet.c b/drivers/net/rionet.c index e9f101c9bae2..bfbb39f93554 100644 --- a/drivers/net/rionet.c +++ b/drivers/net/rionet.c @@ -216,9 +216,9 @@ static int rionet_start_xmit(struct sk_buff *skb, struct net_device *ndev) * it just report sending a packet to the target * (without actual packet transfer). */ - dev_kfree_skb_any(skb); ndev->stats.tx_packets++; ndev->stats.tx_bytes += skb->len; + dev_kfree_skb_any(skb); } } -- GitLab From eb09c6dbe4bb799ba153c5d729e2d26098a3b410 Mon Sep 17 00:00:00 2001 From: Julian Wiedmann Date: Wed, 28 Nov 2018 16:20:50 +0100 Subject: [PATCH 0227/1286] s390/qeth: fix length check in SNMP processing [ Upstream commit 9a764c1e59684c0358e16ccaafd870629f2cfe67 ] The response for a SNMP request can consist of multiple parts, which the cmd callback stages into a kernel buffer until all parts have been received. If the callback detects that the staging buffer provides insufficient space, it bails out with error. This processing is buggy for the first part of the response - while it initially checks for a length of 'data_len', it later copies an additional amount of 'offsetof(struct qeth_snmp_cmd, data)' bytes. Fix the calculation of 'data_len' for the first part of the response. This also nicely cleans up the memcpy code. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Julian Wiedmann Reviewed-by: Ursula Braun Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/s390/net/qeth_core_main.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 169dd7127f9e..69ef5f4060ed 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -4545,8 +4545,8 @@ static int qeth_snmp_command_cb(struct qeth_card *card, { struct qeth_ipa_cmd *cmd; struct qeth_arp_query_info *qinfo; - struct qeth_snmp_cmd *snmp; unsigned char *data; + void *snmp_data; __u16 data_len; QETH_CARD_TEXT(card, 3, "snpcmdcb"); @@ -4554,7 +4554,6 @@ static int qeth_snmp_command_cb(struct qeth_card *card, cmd = (struct qeth_ipa_cmd *) sdata; data = (unsigned char *)((char *)cmd - reply->offset); qinfo = (struct qeth_arp_query_info *) reply->param; - snmp = &cmd->data.setadapterparms.data.snmp; if (cmd->hdr.return_code) { QETH_CARD_TEXT_(card, 4, "scer1%x", cmd->hdr.return_code); @@ -4567,10 +4566,15 @@ static int qeth_snmp_command_cb(struct qeth_card *card, return 0; } data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data)); - if (cmd->data.setadapterparms.hdr.seq_no == 1) - data_len -= (__u16)((char *)&snmp->data - (char *)cmd); - else - data_len -= (__u16)((char *)&snmp->request - (char *)cmd); + if (cmd->data.setadapterparms.hdr.seq_no == 1) { + snmp_data = &cmd->data.setadapterparms.data.snmp; + data_len -= offsetof(struct qeth_ipa_cmd, + data.setadapterparms.data.snmp); + } else { + snmp_data = &cmd->data.setadapterparms.data.snmp.request; + data_len -= offsetof(struct qeth_ipa_cmd, + data.setadapterparms.data.snmp.request); + } /* check if there is enough room in userspace */ if ((qinfo->udata_len - qinfo->udata_offset) < data_len) { @@ -4583,16 +4587,9 @@ static int qeth_snmp_command_cb(struct qeth_card *card, QETH_CARD_TEXT_(card, 4, "sseqn%i", cmd->data.setadapterparms.hdr.seq_no); /*copy entries to user buffer*/ - if (cmd->data.setadapterparms.hdr.seq_no == 1) { - memcpy(qinfo->udata + qinfo->udata_offset, - (char *)snmp, - data_len + offsetof(struct qeth_snmp_cmd, data)); - qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data); - } else { - memcpy(qinfo->udata + qinfo->udata_offset, - (char *)&snmp->request, data_len); - } + memcpy(qinfo->udata + qinfo->udata_offset, snmp_data, data_len); qinfo->udata_offset += data_len; + /* check if all replies received ... */ QETH_CARD_TEXT_(card, 4, "srtot%i", cmd->data.setadapterparms.hdr.used_total); -- GitLab From 72e5a2bdf753f5ba82ea6bfb7706aabc9587d0cb Mon Sep 17 00:00:00 2001 From: Bernd Eckstein <3erndeckstein@gmail.com> Date: Fri, 23 Nov 2018 13:51:26 +0100 Subject: [PATCH 0228/1286] usbnet: ipheth: fix potential recvmsg bug and recvmsg bug 2 [ Upstream commit 45611c61dd503454b2edae00aabe1e429ec49ebe ] The bug is not easily reproducable, as it may occur very infrequently (we had machines with 20minutes heavy downloading before it occurred) However, on a virual machine (VMWare on Windows 10 host) it occurred pretty frequently (1-2 seconds after a speedtest was started) dev->tx_skb mab be freed via dev_kfree_skb_irq on a callback before it is set. This causes the following problems: - double free of the skb or potential memory leak - in dmesg: 'recvmsg bug' and 'recvmsg bug 2' and eventually general protection fault Example dmesg output: [ 134.841986] ------------[ cut here ]------------ [ 134.841987] recvmsg bug: copied 9C24A555 seq 9C24B557 rcvnxt 9C25A6B3 fl 0 [ 134.841993] WARNING: CPU: 7 PID: 2629 at /build/linux-hwe-On9fm7/linux-hwe-4.15.0/net/ipv4/tcp.c:1865 tcp_recvmsg+0x44d/0xab0 [ 134.841994] Modules linked in: ipheth(OE) kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel aes_x86_64 crypto_simd glue_helper cryptd vmw_balloon intel_rapl_perf joydev input_leds serio_raw vmw_vsock_vmci_transport vsock shpchp i2c_piix4 mac_hid binfmt_misc vmw_vmci parport_pc ppdev lp parport autofs4 vmw_pvscsi vmxnet3 hid_generic usbhid hid vmwgfx ttm drm_kms_helper syscopyarea sysfillrect mptspi mptscsih sysimgblt ahci psmouse fb_sys_fops pata_acpi mptbase libahci e1000 drm scsi_transport_spi [ 134.842046] CPU: 7 PID: 2629 Comm: python Tainted: G W OE 4.15.0-34-generic #37~16.04.1-Ubuntu [ 134.842046] Hardware name: VMware, Inc. VMware Virtual Platform/440BX Desktop Reference Platform, BIOS 6.00 05/19/2017 [ 134.842048] RIP: 0010:tcp_recvmsg+0x44d/0xab0 [ 134.842048] RSP: 0018:ffffa6630422bcc8 EFLAGS: 00010286 [ 134.842049] RAX: 0000000000000000 RBX: ffff997616f4f200 RCX: 0000000000000006 [ 134.842049] RDX: 0000000000000007 RSI: 0000000000000082 RDI: ffff9976257d6490 [ 134.842050] RBP: ffffa6630422bd98 R08: 0000000000000001 R09: 000000000004bba4 [ 134.842050] R10: 0000000001e00c6f R11: 000000000004bba4 R12: ffff99760dee3000 [ 134.842051] R13: 0000000000000000 R14: ffff99760dee3514 R15: 0000000000000000 [ 134.842051] FS: 00007fe332347700(0000) GS:ffff9976257c0000(0000) knlGS:0000000000000000 [ 134.842052] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 134.842053] CR2: 0000000001e41000 CR3: 000000020e9b4006 CR4: 00000000003606e0 [ 134.842055] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 134.842055] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 134.842057] Call Trace: [ 134.842060] ? aa_sk_perm+0x53/0x1a0 [ 134.842064] inet_recvmsg+0x51/0xc0 [ 134.842066] sock_recvmsg+0x43/0x50 [ 134.842070] SYSC_recvfrom+0xe4/0x160 [ 134.842072] ? __schedule+0x3de/0x8b0 [ 134.842075] ? ktime_get_ts64+0x4c/0xf0 [ 134.842079] SyS_recvfrom+0xe/0x10 [ 134.842082] do_syscall_64+0x73/0x130 [ 134.842086] entry_SYSCALL_64_after_hwframe+0x3d/0xa2 [ 134.842086] RIP: 0033:0x7fe331f5a81d [ 134.842088] RSP: 002b:00007ffe8da98398 EFLAGS: 00000246 ORIG_RAX: 000000000000002d [ 134.842090] RAX: ffffffffffffffda RBX: ffffffffffffffff RCX: 00007fe331f5a81d [ 134.842094] RDX: 00000000000003fb RSI: 0000000001e00874 RDI: 0000000000000003 [ 134.842095] RBP: 00007fe32f642c70 R08: 0000000000000000 R09: 0000000000000000 [ 134.842097] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fe332347698 [ 134.842099] R13: 0000000001b7e0a0 R14: 0000000001e00874 R15: 0000000000000000 [ 134.842103] Code: 24 fd ff ff e9 cc fe ff ff 48 89 d8 41 8b 8c 24 10 05 00 00 44 8b 45 80 48 c7 c7 08 bd 59 8b 48 89 85 68 ff ff ff e8 b3 c4 7d ff <0f> 0b 48 8b 85 68 ff ff ff e9 e9 fe ff ff 41 8b 8c 24 10 05 00 [ 134.842126] ---[ end trace b7138fc08c83147f ]--- [ 134.842144] general protection fault: 0000 [#1] SMP PTI [ 134.842145] Modules linked in: ipheth(OE) kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel aes_x86_64 crypto_simd glue_helper cryptd vmw_balloon intel_rapl_perf joydev input_leds serio_raw vmw_vsock_vmci_transport vsock shpchp i2c_piix4 mac_hid binfmt_misc vmw_vmci parport_pc ppdev lp parport autofs4 vmw_pvscsi vmxnet3 hid_generic usbhid hid vmwgfx ttm drm_kms_helper syscopyarea sysfillrect mptspi mptscsih sysimgblt ahci psmouse fb_sys_fops pata_acpi mptbase libahci e1000 drm scsi_transport_spi [ 134.842161] CPU: 7 PID: 2629 Comm: python Tainted: G W OE 4.15.0-34-generic #37~16.04.1-Ubuntu [ 134.842162] Hardware name: VMware, Inc. VMware Virtual Platform/440BX Desktop Reference Platform, BIOS 6.00 05/19/2017 [ 134.842164] RIP: 0010:tcp_close+0x2c6/0x440 [ 134.842165] RSP: 0018:ffffa6630422bde8 EFLAGS: 00010202 [ 134.842167] RAX: 0000000000000000 RBX: ffff99760dee3000 RCX: 0000000180400034 [ 134.842168] RDX: 5c4afd407207a6c4 RSI: ffffe868495bd300 RDI: ffff997616f4f200 [ 134.842169] RBP: ffffa6630422be08 R08: 0000000016f4d401 R09: 0000000180400034 [ 134.842169] R10: ffffa6630422bd98 R11: 0000000000000000 R12: 000000000000600c [ 134.842170] R13: 0000000000000000 R14: ffff99760dee30c8 R15: ffff9975bd44fe00 [ 134.842171] FS: 00007fe332347700(0000) GS:ffff9976257c0000(0000) knlGS:0000000000000000 [ 134.842173] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 134.842174] CR2: 0000000001e41000 CR3: 000000020e9b4006 CR4: 00000000003606e0 [ 134.842177] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 134.842178] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 134.842179] Call Trace: [ 134.842181] inet_release+0x42/0x70 [ 134.842183] __sock_release+0x42/0xb0 [ 134.842184] sock_close+0x15/0x20 [ 134.842187] __fput+0xea/0x220 [ 134.842189] ____fput+0xe/0x10 [ 134.842191] task_work_run+0x8a/0xb0 [ 134.842193] exit_to_usermode_loop+0xc4/0xd0 [ 134.842195] do_syscall_64+0xf4/0x130 [ 134.842197] entry_SYSCALL_64_after_hwframe+0x3d/0xa2 [ 134.842197] RIP: 0033:0x7fe331f5a560 [ 134.842198] RSP: 002b:00007ffe8da982e8 EFLAGS: 00000246 ORIG_RAX: 0000000000000003 [ 134.842200] RAX: 0000000000000000 RBX: 00007fe32f642c70 RCX: 00007fe331f5a560 [ 134.842201] RDX: 00000000008f5320 RSI: 0000000001cd4b50 RDI: 0000000000000003 [ 134.842202] RBP: 00007fe32f6500f8 R08: 000000000000003c R09: 00000000009343c0 [ 134.842203] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fe32f6500d0 [ 134.842204] R13: 00000000008f5320 R14: 00000000008f5320 R15: 0000000001cd4770 [ 134.842205] Code: c8 00 00 00 45 31 e4 49 39 fe 75 4d eb 50 83 ab d8 00 00 00 01 48 8b 17 48 8b 47 08 48 c7 07 00 00 00 00 48 c7 47 08 00 00 00 00 <48> 89 42 08 48 89 10 0f b6 57 34 8b 47 2c 2b 47 28 83 e2 01 80 [ 134.842226] RIP: tcp_close+0x2c6/0x440 RSP: ffffa6630422bde8 [ 134.842227] ---[ end trace b7138fc08c831480 ]--- The proposed patch eliminates a potential racing condition. Before, usb_submit_urb was called and _after_ that, the skb was attached (dev->tx_skb). So, on a callback it was possible, however unlikely that the skb was freed before it was set. That way (because dev->tx_skb was not set to NULL after it was freed), it could happen that a skb from a earlier transmission was freed a second time (and the skb we should have freed did not get freed at all) Now we free the skb directly in ipheth_tx(). It is not passed to the callback anymore, eliminating the posibility of a double free of the same skb. Depending on the retval of usb_submit_urb() we use dev_kfree_skb_any() respectively dev_consume_skb_any() to free the skb. Signed-off-by: Oliver Zweigle Signed-off-by: Bernd Eckstein <3ernd.Eckstein@gmail.com> Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/ipheth.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c index d49c7103085e..aabbcfb6e6da 100644 --- a/drivers/net/usb/ipheth.c +++ b/drivers/net/usb/ipheth.c @@ -140,7 +140,6 @@ struct ipheth_device { struct usb_device *udev; struct usb_interface *intf; struct net_device *net; - struct sk_buff *tx_skb; struct urb *tx_urb; struct urb *rx_urb; unsigned char *tx_buf; @@ -229,6 +228,7 @@ static void ipheth_rcvbulk_callback(struct urb *urb) case -ENOENT: case -ECONNRESET: case -ESHUTDOWN: + case -EPROTO: return; case 0: break; @@ -280,7 +280,6 @@ static void ipheth_sndbulk_callback(struct urb *urb) dev_err(&dev->intf->dev, "%s: urb status: %d\n", __func__, status); - dev_kfree_skb_irq(dev->tx_skb); netif_wake_queue(dev->net); } @@ -410,7 +409,7 @@ static int ipheth_tx(struct sk_buff *skb, struct net_device *net) if (skb->len > IPHETH_BUF_SIZE) { WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len); dev->net->stats.tx_dropped++; - dev_kfree_skb_irq(skb); + dev_kfree_skb_any(skb); return NETDEV_TX_OK; } @@ -430,12 +429,11 @@ static int ipheth_tx(struct sk_buff *skb, struct net_device *net) dev_err(&dev->intf->dev, "%s: usb_submit_urb: %d\n", __func__, retval); dev->net->stats.tx_errors++; - dev_kfree_skb_irq(skb); + dev_kfree_skb_any(skb); } else { - dev->tx_skb = skb; - dev->net->stats.tx_packets++; dev->net->stats.tx_bytes += skb->len; + dev_consume_skb_any(skb); netif_stop_queue(net); } -- GitLab From e5d981df9a1d3f13dfff083ab0578daedbcd9e8a Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 22 Jan 2018 22:53:28 +0100 Subject: [PATCH 0229/1286] sched/core: Fix cpu.max vs. cpuhotplug deadlock commit ce48c146495a1a50e48cdbfbfaba3e708be7c07c upstream Tejun reported the following cpu-hotplug lock (percpu-rwsem) read recursion: tg_set_cfs_bandwidth() get_online_cpus() cpus_read_lock() cfs_bandwidth_usage_inc() static_key_slow_inc() cpus_read_lock() Reported-by: Tejun Heo Tested-by: Tejun Heo Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20180122215328.GP3397@worktop Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- include/linux/jump_label.h | 7 +++++++ kernel/jump_label.c | 12 +++++++++--- kernel/sched/fair.c | 4 ++-- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/include/linux/jump_label.h b/include/linux/jump_label.h index 3b7675bcca64..cd0d2270998f 100644 --- a/include/linux/jump_label.h +++ b/include/linux/jump_label.h @@ -160,6 +160,8 @@ extern void arch_jump_label_transform_static(struct jump_entry *entry, extern int jump_label_text_reserved(void *start, void *end); extern void static_key_slow_inc(struct static_key *key); extern void static_key_slow_dec(struct static_key *key); +extern void static_key_slow_inc_cpuslocked(struct static_key *key); +extern void static_key_slow_dec_cpuslocked(struct static_key *key); extern void jump_label_apply_nops(struct module *mod); extern int static_key_count(struct static_key *key); extern void static_key_enable(struct static_key *key); @@ -222,6 +224,9 @@ static inline void static_key_slow_dec(struct static_key *key) atomic_dec(&key->enabled); } +#define static_key_slow_inc_cpuslocked(key) static_key_slow_inc(key) +#define static_key_slow_dec_cpuslocked(key) static_key_slow_dec(key) + static inline int jump_label_text_reserved(void *start, void *end) { return 0; @@ -416,6 +421,8 @@ extern bool ____wrong_branch_error(void); #define static_branch_inc(x) static_key_slow_inc(&(x)->key) #define static_branch_dec(x) static_key_slow_dec(&(x)->key) +#define static_branch_inc_cpuslocked(x) static_key_slow_inc_cpuslocked(&(x)->key) +#define static_branch_dec_cpuslocked(x) static_key_slow_dec_cpuslocked(&(x)->key) /* * Normal usage; boolean enable/disable. diff --git a/kernel/jump_label.c b/kernel/jump_label.c index 7c3774ac1d51..70be35a19be2 100644 --- a/kernel/jump_label.c +++ b/kernel/jump_label.c @@ -79,7 +79,7 @@ int static_key_count(struct static_key *key) } EXPORT_SYMBOL_GPL(static_key_count); -static void static_key_slow_inc_cpuslocked(struct static_key *key) +void static_key_slow_inc_cpuslocked(struct static_key *key) { int v, v1; @@ -180,7 +180,7 @@ void static_key_disable(struct static_key *key) } EXPORT_SYMBOL_GPL(static_key_disable); -static void static_key_slow_dec_cpuslocked(struct static_key *key, +static void __static_key_slow_dec_cpuslocked(struct static_key *key, unsigned long rate_limit, struct delayed_work *work) { @@ -211,7 +211,7 @@ static void __static_key_slow_dec(struct static_key *key, struct delayed_work *work) { cpus_read_lock(); - static_key_slow_dec_cpuslocked(key, rate_limit, work); + __static_key_slow_dec_cpuslocked(key, rate_limit, work); cpus_read_unlock(); } @@ -229,6 +229,12 @@ void static_key_slow_dec(struct static_key *key) } EXPORT_SYMBOL_GPL(static_key_slow_dec); +void static_key_slow_dec_cpuslocked(struct static_key *key) +{ + STATIC_KEY_CHECK_USE(); + __static_key_slow_dec_cpuslocked(key, 0, NULL); +} + void static_key_slow_dec_deferred(struct static_key_deferred *key) { STATIC_KEY_CHECK_USE(); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 2d4d79420e36..7240bb4a4090 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -4040,12 +4040,12 @@ static inline bool cfs_bandwidth_used(void) void cfs_bandwidth_usage_inc(void) { - static_key_slow_inc(&__cfs_bandwidth_used); + static_key_slow_inc_cpuslocked(&__cfs_bandwidth_used); } void cfs_bandwidth_usage_dec(void) { - static_key_slow_dec(&__cfs_bandwidth_used); + static_key_slow_dec_cpuslocked(&__cfs_bandwidth_used); } #else /* HAVE_JUMP_LABEL */ static bool cfs_bandwidth_used(void) -- GitLab From da06d6d14a0a14d398b1e7c8024b090e40f4ec89 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Fri, 1 Jun 2018 10:59:19 -0400 Subject: [PATCH 0230/1286] x86/bugs: Add AMD's variant of SSB_NO commit 24809860012e0130fbafe536709e08a22b3e959e upstream The AMD document outlining the SSBD handling 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf mentions that the CPUID 8000_0008.EBX[26] will mean that the speculative store bypass disable is no longer needed. A copy of this document is available at: https://bugzilla.kernel.org/show_bug.cgi?id=199889 Signed-off-by: Konrad Rzeszutek Wilk Signed-off-by: Thomas Gleixner Cc: Tom Lendacky Cc: Janakarajan Natarajan Cc: kvm@vger.kernel.org Cc: andrew.cooper3@citrix.com Cc: Andy Lutomirski Cc: "H. Peter Anvin" Cc: Borislav Petkov Cc: David Woodhouse Link: https://lkml.kernel.org/r/20180601145921.9500-2-konrad.wilk@oracle.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 3 ++- arch/x86/kvm/cpuid.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 673d6e988196..21a653dfc01b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -285,6 +285,7 @@ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ +#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 96643e2c75b8..065582692446 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -958,7 +958,8 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); if (!x86_match_cpu(cpu_no_spec_store_bypass) && - !(ia32_cap & ARCH_CAP_SSB_NO)) + !(ia32_cap & ARCH_CAP_SSB_NO) && + !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); if (x86_match_cpu(cpu_no_speculation)) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index d1f5c744142b..95a98397beca 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -367,7 +367,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_8000_0008_ebx_x86_features = - F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD); + F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD) | F(AMD_SSB_NO); /* cpuid 0xC0000001.edx */ const u32 kvm_cpuid_C000_0001_edx_x86_features = -- GitLab From 54b65f8eaf75872052565976f524e91133778c54 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Fri, 1 Jun 2018 10:59:20 -0400 Subject: [PATCH 0231/1286] x86/bugs: Add AMD's SPEC_CTRL MSR usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6ac2f49edb1ef5446089c7c660017732886d62d6 upstream The AMD document outlining the SSBD handling 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf mentions that if CPUID 8000_0008.EBX[24] is set we should be using the SPEC_CTRL MSR (0x48) over the VIRT SPEC_CTRL MSR (0xC001_011f) for speculative store bypass disable. This in effect means we should clear the X86_FEATURE_VIRT_SSBD flag so that we would prefer the SPEC_CTRL MSR. See the document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Signed-off-by: Konrad Rzeszutek Wilk Signed-off-by: Thomas Gleixner Cc: Tom Lendacky Cc: Janakarajan Natarajan Cc: kvm@vger.kernel.org Cc: KarimAllah Ahmed Cc: andrew.cooper3@citrix.com Cc: Joerg Roedel Cc: Radim Krčmář Cc: Andy Lutomirski Cc: "H. Peter Anvin" Cc: Paolo Bonzini Cc: Borislav Petkov Cc: David Woodhouse Cc: Kees Cook Link: https://lkml.kernel.org/r/20180601145921.9500-3-konrad.wilk@oracle.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/bugs.c | 12 +++++++----- arch/x86/kernel/cpu/common.c | 6 ++++++ arch/x86/kvm/cpuid.c | 10 ++++++++-- arch/x86/kvm/svm.c | 8 +++++--- 5 files changed, 27 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 21a653dfc01b..7d910827126b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -284,6 +284,7 @@ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e92aedd93806..fd79e16dab07 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -532,18 +532,20 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) if (mode == SPEC_STORE_BYPASS_DISABLE) { setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); /* - * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses - * a completely different MSR and bit dependent on family. + * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may + * use a completely different MSR and bit dependent on family. */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: + case X86_VENDOR_AMD: + if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { + x86_amd_ssb_disable(); + break; + } x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); break; - case X86_VENDOR_AMD: - x86_amd_ssb_disable(); - break; } } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 065582692446..51e49f6fe8e1 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -760,6 +760,12 @@ static void init_speculation_control(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_STIBP); set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); } + + if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { + set_cpu_cap(c, X86_FEATURE_SSBD); + set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); + clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); + } } void get_cpu_cap(struct cpuinfo_x86 *c) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 95a98397beca..bbcd69c76d96 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -367,7 +367,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_8000_0008_ebx_x86_features = - F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD) | F(AMD_SSB_NO); + F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | + F(AMD_SSB_NO); /* cpuid 0xC0000001.edx */ const u32 kvm_cpuid_C000_0001_edx_x86_features = @@ -649,7 +650,12 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->ebx |= F(VIRT_SSBD); entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features; cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX); - if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) + /* + * The preference is to use SPEC CTRL MSR instead of the + * VIRT_SPEC MSR. + */ + if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && + !boot_cpu_has(X86_FEATURE_AMD_SSBD)) entry->ebx |= F(VIRT_SSBD); break; } diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index f6bebcec60b4..e9dbd62bb46e 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -3644,7 +3644,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) break; case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && - !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) + !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && + !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) return 1; msr_info->data = svm->spec_ctrl; @@ -3749,11 +3750,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) break; case MSR_IA32_SPEC_CTRL: if (!msr->host_initiated && - !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) + !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) && + !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) return 1; /* The STIBP bit doesn't fault even if it's not advertised */ - if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP)) + if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) return 1; svm->spec_ctrl = data; -- GitLab From 6d2533a6818274602ef1a783594f2d6fc65d8fc6 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Fri, 1 Jun 2018 10:59:21 -0400 Subject: [PATCH 0232/1286] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features commit 108fab4b5c8f12064ef86e02cb0459992affb30f upstream Both AMD and Intel can have SPEC_CTRL_MSR for SSBD. However AMD also has two more other ways of doing it - which are !SPEC_CTRL MSR ways. Signed-off-by: Konrad Rzeszutek Wilk Signed-off-by: Thomas Gleixner Cc: Kees Cook Cc: kvm@vger.kernel.org Cc: KarimAllah Ahmed Cc: andrew.cooper3@citrix.com Cc: "H. Peter Anvin" Cc: Borislav Petkov Cc: David Woodhouse Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index fd79e16dab07..63a9f3fd3a37 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -535,17 +535,12 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * use a completely different MSR and bit dependent on family. */ - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - case X86_VENDOR_AMD: - if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { - x86_amd_ssb_disable(); - break; - } + if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + x86_amd_ssb_disable(); + else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); - break; } } -- GitLab From 0071cdff923922f85a8204fd9bff56a44af2b9a3 Mon Sep 17 00:00:00 2001 From: Tom Lendacky Date: Mon, 2 Jul 2018 16:35:53 -0500 Subject: [PATCH 0233/1286] x86/bugs: Update when to check for the LS_CFG SSBD mitigation commit 845d382bb15c6e7dc5026c0ff919c5b13fc7e11b upstream If either the X86_FEATURE_AMD_SSBD or X86_FEATURE_VIRT_SSBD features are present, then there is no need to perform the check for the LS_CFG SSBD mitigation support. Signed-off-by: Tom Lendacky Cc: Borislav Petkov Cc: David Woodhouse Cc: Konrad Rzeszutek Wilk Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20180702213553.29202.21089.stgit@tlendack-t1.amdoffice.net Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/amd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index dda741bd5789..7e03515662c0 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -554,7 +554,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) nodes_per_socket = ((value >> 3) & 7) + 1; } - if (c->x86 >= 0x15 && c->x86 <= 0x17) { + if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && + !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && + c->x86 >= 0x15 && c->x86 <= 0x17) { unsigned int bit; switch (c->x86) { -- GitLab From 82647e461639a7cae7beaf2391f6b58f69b81110 Mon Sep 17 00:00:00 2001 From: Tom Lendacky Date: Mon, 2 Jul 2018 16:36:02 -0500 Subject: [PATCH 0234/1286] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR commit 612bc3b3d4be749f73a513a17d9b3ee1330d3487 upstream On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the SSBD mitigation support should use the SPEC_CTRL MSR. Other features could have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD mitigation option is in place. Update the SSBD support to check for the actual SSBD features that will use the SPEC_CTRL MSR. Signed-off-by: Tom Lendacky Cc: Borislav Petkov Cc: David Woodhouse Cc: Konrad Rzeszutek Wilk Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage") Link: http://lkml.kernel.org/r/20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 63a9f3fd3a37..50941119e13e 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -166,7 +166,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; /* SSBD controlled in MSR_SPEC_CTRL */ - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) + if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || + static_cpu_has(X86_FEATURE_AMD_SSBD)) hostval |= ssbd_tif_to_spec_ctrl(ti->flags); if (hostval != guestval) { @@ -535,9 +536,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * use a completely different MSR and bit dependent on family. */ - if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && + !static_cpu_has(X86_FEATURE_AMD_SSBD)) { x86_amd_ssb_disable(); - else { + } else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); -- GitLab From 300a6f27dd8277843e39b37cca5e0c5b203743cb Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 25 Sep 2018 14:38:55 +0200 Subject: [PATCH 0235/1286] x86/speculation: Enable cross-hyperthread spectre v2 STIBP mitigation commit 53c613fe6349994f023245519265999eed75957f upstream STIBP is a feature provided by certain Intel ucodes / CPUs. This feature (once enabled) prevents cross-hyperthread control of decisions made by indirect branch predictors. Enable this feature if - the CPU is vulnerable to spectre v2 - the CPU supports SMT and has SMT siblings online - spectre_v2 mitigation autoselection is enabled (default) After some previous discussion, this leaves STIBP on all the time, as wrmsr on crossing kernel boundary is a no-no. This could perhaps later be a bit more optimized (like disabling it in NOHZ, experiment with disabling it in idle, etc) if needed. Note that the synchronization of the mask manipulation via newly added spec_ctrl_mutex is currently not strictly needed, as the only updater is already being serialized by cpu_add_remove_lock, but let's make this a little bit more future-proof. Signed-off-by: Jiri Kosina Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: "WoodhouseDavid" Cc: Andi Kleen Cc: Tim Chen Cc: "SchauflerCasey" Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1809251438240.15880@cbobk.fhfr.pm Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 57 ++++++++++++++++++++++++++++++++++---- kernel/cpu.c | 11 +++++++- 2 files changed, 61 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 50941119e13e..ef02230221c5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -34,12 +34,10 @@ static void __init spectre_v2_select_mitigation(void); static void __init ssb_select_mitigation(void); static void __init l1tf_select_mitigation(void); -/* - * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any - * writes to SPEC_CTRL contain whatever reserved bits have been set. - */ -u64 __ro_after_init x86_spec_ctrl_base; +/* The base value of the SPEC_CTRL MSR that always has to be preserved. */ +u64 x86_spec_ctrl_base; EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); +static DEFINE_MUTEX(spec_ctrl_mutex); /* * The vendor and possibly platform specific bits which can be modified in @@ -324,6 +322,46 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return cmd; } +static bool stibp_needed(void) +{ + if (spectre_v2_enabled == SPECTRE_V2_NONE) + return false; + + if (!boot_cpu_has(X86_FEATURE_STIBP)) + return false; + + return true; +} + +static void update_stibp_msr(void *info) +{ + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); +} + +void arch_smt_update(void) +{ + u64 mask; + + if (!stibp_needed()) + return; + + mutex_lock(&spec_ctrl_mutex); + mask = x86_spec_ctrl_base; + if (cpu_smt_control == CPU_SMT_ENABLED) + mask |= SPEC_CTRL_STIBP; + else + mask &= ~SPEC_CTRL_STIBP; + + if (mask != x86_spec_ctrl_base) { + pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", + cpu_smt_control == CPU_SMT_ENABLED ? + "Enabling" : "Disabling"); + x86_spec_ctrl_base = mask; + on_each_cpu(update_stibp_msr, NULL, 1); + } + mutex_unlock(&spec_ctrl_mutex); +} + static void __init spectre_v2_select_mitigation(void) { enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); @@ -423,6 +461,9 @@ static void __init spectre_v2_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); pr_info("Enabling Restricted Speculation for firmware calls\n"); } + + /* Enable STIBP if appropriate */ + arch_smt_update(); } #undef pr_fmt @@ -813,6 +854,8 @@ static ssize_t l1tf_show_state(char *buf) static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, char *buf, unsigned int bug) { + int ret; + if (!boot_cpu_has_bug(bug)) return sprintf(buf, "Not affected\n"); @@ -827,10 +870,12 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr return sprintf(buf, "Mitigation: __user pointer sanitization\n"); case X86_BUG_SPECTRE_V2: - return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], + ret = sprintf(buf, "%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", + (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", spectre_v2_module_string()); + return ret; case X86_BUG_SPEC_STORE_BYPASS: return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); diff --git a/kernel/cpu.c b/kernel/cpu.c index f3f389e33343..90cf6a04e08a 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -2045,6 +2045,12 @@ static void cpuhp_online_cpu_device(unsigned int cpu) kobject_uevent(&dev->kobj, KOBJ_ONLINE); } +/* + * Architectures that need SMT-specific errata handling during SMT hotplug + * should override this. + */ +void __weak arch_smt_update(void) { }; + static int cpuhp_smt_disable(enum cpuhp_smt_control ctrlval) { int cpu, ret = 0; @@ -2071,8 +2077,10 @@ static int cpuhp_smt_disable(enum cpuhp_smt_control ctrlval) */ cpuhp_offline_cpu_device(cpu); } - if (!ret) + if (!ret) { cpu_smt_control = ctrlval; + arch_smt_update(); + } cpu_maps_update_done(); return ret; } @@ -2083,6 +2091,7 @@ static int cpuhp_smt_enable(void) cpu_maps_update_begin(); cpu_smt_control = CPU_SMT_ENABLED; + arch_smt_update(); for_each_present_cpu(cpu) { /* Skip online CPUs and CPUs on offline nodes */ if (cpu_online(cpu) || !node_online(cpu_to_node(cpu))) -- GitLab From 4741e31931b27b9eba1e9df02d781a2f808b7d82 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 25 Sep 2018 14:38:18 +0200 Subject: [PATCH 0236/1286] x86/speculation: Apply IBPB more strictly to avoid cross-process data leak commit dbfe2953f63c640463c630746cd5d9de8b2f63ae upstream Currently, IBPB is only issued in cases when switching into a non-dumpable process, the rationale being to protect such 'important and security sensitive' processess (such as GPG) from data leaking into a different userspace process via spectre v2. This is however completely insufficient to provide proper userspace-to-userpace spectrev2 protection, as any process can poison branch buffers before being scheduled out, and the newly scheduled process immediately becomes spectrev2 victim. In order to minimize the performance impact (for usecases that do require spectrev2 protection), issue the barrier only in cases when switching between processess where the victim can't be ptraced by the potential attacker (as in such cases, the attacker doesn't have to bother with branch buffers at all). [ tglx: Split up PTRACE_MODE_NOACCESS_CHK into PTRACE_MODE_SCHED and PTRACE_MODE_IBPB to be able to do ptrace() context tracking reasonably fine-grained ] Fixes: 18bf3c3ea8 ("x86/speculation: Use Indirect Branch Prediction Barrier in context switch") Originally-by: Tim Chen Signed-off-by: Jiri Kosina Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: "WoodhouseDavid" Cc: Andi Kleen Cc: "SchauflerCasey" Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1809251437340.15880@cbobk.fhfr.pm Signed-off-by: Greg Kroah-Hartman --- arch/x86/mm/tlb.c | 31 ++++++++++++++++++++----------- include/linux/ptrace.h | 21 +++++++++++++++++++-- kernel/ptrace.c | 10 ++++++++++ 3 files changed, 49 insertions(+), 13 deletions(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 83a3f4c935fc..9e943de9d628 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -180,6 +181,19 @@ static void sync_current_stack_to_mm(struct mm_struct *mm) } } +static bool ibpb_needed(struct task_struct *tsk, u64 last_ctx_id) +{ + /* + * Check if the current (previous) task has access to the memory + * of the @tsk (next) task. If access is denied, make sure to + * issue a IBPB to stop user->user Spectre-v2 attacks. + * + * Note: __ptrace_may_access() returns 0 or -ERRNO. + */ + return (tsk && tsk->mm && tsk->mm->context.ctx_id != last_ctx_id && + ptrace_may_access_sched(tsk, PTRACE_MODE_SPEC_IBPB)); +} + void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { @@ -256,18 +270,13 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, * one process from doing Spectre-v2 attacks on another. * * As an optimization, flush indirect branches only when - * switching into processes that disable dumping. This - * protects high value processes like gpg, without having - * too high performance overhead. IBPB is *expensive*! - * - * This will not flush branches when switching into kernel - * threads. It will also not flush if we switch to idle - * thread and back to the same process. It will flush if we - * switch to a different non-dumpable process. + * switching into a processes that can't be ptrace by the + * current one (as in such case, attacker has much more + * convenient way how to tamper with the next process than + * branch buffer poisoning). */ - if (tsk && tsk->mm && - tsk->mm->context.ctx_id != last_ctx_id && - get_dumpable(tsk->mm) != SUID_DUMP_USER) + if (static_cpu_has(X86_FEATURE_USE_IBPB) && + ibpb_needed(tsk, last_ctx_id)) indirect_branch_prediction_barrier(); if (IS_ENABLED(CONFIG_VMAP_STACK)) { diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index 919b2a0b0307..b1d43b80abfa 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -62,14 +62,17 @@ extern void exit_ptrace(struct task_struct *tracer, struct list_head *dead); #define PTRACE_MODE_READ 0x01 #define PTRACE_MODE_ATTACH 0x02 #define PTRACE_MODE_NOAUDIT 0x04 -#define PTRACE_MODE_FSCREDS 0x08 -#define PTRACE_MODE_REALCREDS 0x10 +#define PTRACE_MODE_FSCREDS 0x08 +#define PTRACE_MODE_REALCREDS 0x10 +#define PTRACE_MODE_SCHED 0x20 +#define PTRACE_MODE_IBPB 0x40 /* shorthands for READ/ATTACH and FSCREDS/REALCREDS combinations */ #define PTRACE_MODE_READ_FSCREDS (PTRACE_MODE_READ | PTRACE_MODE_FSCREDS) #define PTRACE_MODE_READ_REALCREDS (PTRACE_MODE_READ | PTRACE_MODE_REALCREDS) #define PTRACE_MODE_ATTACH_FSCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_FSCREDS) #define PTRACE_MODE_ATTACH_REALCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_REALCREDS) +#define PTRACE_MODE_SPEC_IBPB (PTRACE_MODE_ATTACH_REALCREDS | PTRACE_MODE_IBPB) /** * ptrace_may_access - check whether the caller is permitted to access @@ -87,6 +90,20 @@ extern void exit_ptrace(struct task_struct *tracer, struct list_head *dead); */ extern bool ptrace_may_access(struct task_struct *task, unsigned int mode); +/** + * ptrace_may_access - check whether the caller is permitted to access + * a target task. + * @task: target task + * @mode: selects type of access and caller credentials + * + * Returns true on success, false on denial. + * + * Similar to ptrace_may_access(). Only to be called from context switch + * code. Does not call into audit and the regular LSM hooks due to locking + * constraints. + */ +extern bool ptrace_may_access_sched(struct task_struct *task, unsigned int mode); + static inline int ptrace_reparented(struct task_struct *child) { return !same_thread_group(child->real_parent, child->parent); diff --git a/kernel/ptrace.c b/kernel/ptrace.c index 84b1367935e4..d7be2159ac09 100644 --- a/kernel/ptrace.c +++ b/kernel/ptrace.c @@ -261,6 +261,9 @@ static int ptrace_check_attach(struct task_struct *child, bool ignore_state) static int ptrace_has_cap(struct user_namespace *ns, unsigned int mode) { + if (mode & PTRACE_MODE_SCHED) + return false; + if (mode & PTRACE_MODE_NOAUDIT) return has_ns_capability_noaudit(current, ns, CAP_SYS_PTRACE); else @@ -328,9 +331,16 @@ static int __ptrace_may_access(struct task_struct *task, unsigned int mode) !ptrace_has_cap(mm->user_ns, mode))) return -EPERM; + if (mode & PTRACE_MODE_SCHED) + return 0; return security_ptrace_access_check(task, mode); } +bool ptrace_may_access_sched(struct task_struct *task, unsigned int mode) +{ + return __ptrace_may_access(task, mode | PTRACE_MODE_SCHED); +} + bool ptrace_may_access(struct task_struct *task, unsigned int mode) { int err; -- GitLab From 0d55dce78a0e96f0909f4b7395887e84ba637254 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 25 Sep 2018 14:39:28 +0200 Subject: [PATCH 0237/1286] x86/speculation: Propagate information about RSB filling mitigation to sysfs commit bb4b3b7762735cdaba5a40fd94c9303d9ffa147a upstream If spectrev2 mitigation has been enabled, RSB is filled on context switch in order to protect from various classes of spectrev2 attacks. If this mitigation is enabled, say so in sysfs for spectrev2. Signed-off-by: Jiri Kosina Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: "WoodhouseDavid" Cc: Andi Kleen Cc: Tim Chen Cc: "SchauflerCasey" Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1809251438580.15880@cbobk.fhfr.pm Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ef02230221c5..700d1149601e 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -870,10 +870,11 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr return sprintf(buf, "Mitigation: __user pointer sanitization\n"); case X86_BUG_SPECTRE_V2: - ret = sprintf(buf, "%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], + ret = sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", + boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", spectre_v2_module_string()); return ret; -- GitLab From 46dfe55fbee9be96f70482f3053b084fad3858d0 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Tue, 18 Sep 2018 07:45:00 -0700 Subject: [PATCH 0238/1286] x86/speculation: Add RETPOLINE_AMD support to the inline asm CALL_NOSPEC variant commit 0cbb76d6285794f30953bfa3ab831714b59dd700 upstream ..so that they match their asm counterpart. Add the missing ANNOTATE_NOSPEC_ALTERNATIVE in CALL_NOSPEC, while at it. Signed-off-by: Zhenzhong Duan Signed-off-by: Borislav Petkov Cc: Daniel Borkmann Cc: David Woodhouse Cc: H. Peter Anvin Cc: Ingo Molnar Cc: Konrad Rzeszutek Wilk Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Wang YanQing Cc: dhaval.giani@oracle.com Cc: srinivas.eeda@oracle.com Link: http://lkml.kernel.org/r/c3975665-173e-4d70-8dee-06c926ac26ee@default Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/nospec-branch.h | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 1b4132161c1f..7827f17e9a8a 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -170,11 +170,15 @@ */ # define CALL_NOSPEC \ ANNOTATE_NOSPEC_ALTERNATIVE \ - ALTERNATIVE( \ + ALTERNATIVE_2( \ ANNOTATE_RETPOLINE_SAFE \ "call *%[thunk_target]\n", \ "call __x86_indirect_thunk_%V[thunk_target]\n", \ - X86_FEATURE_RETPOLINE) + X86_FEATURE_RETPOLINE, \ + "lfence;\n" \ + ANNOTATE_RETPOLINE_SAFE \ + "call *%[thunk_target]\n", \ + X86_FEATURE_RETPOLINE_AMD) # define THUNK_TARGET(addr) [thunk_target] "r" (addr) #elif defined(CONFIG_X86_32) && defined(CONFIG_RETPOLINE) @@ -184,7 +188,8 @@ * here, anyway. */ # define CALL_NOSPEC \ - ALTERNATIVE( \ + ANNOTATE_NOSPEC_ALTERNATIVE \ + ALTERNATIVE_2( \ ANNOTATE_RETPOLINE_SAFE \ "call *%[thunk_target]\n", \ " jmp 904f;\n" \ @@ -199,7 +204,11 @@ " ret;\n" \ " .align 16\n" \ "904: call 901b;\n", \ - X86_FEATURE_RETPOLINE) + X86_FEATURE_RETPOLINE, \ + "lfence;\n" \ + ANNOTATE_RETPOLINE_SAFE \ + "call *%[thunk_target]\n", \ + X86_FEATURE_RETPOLINE_AMD) # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) #else /* No retpoline for C / inline asm */ -- GitLab From a9c90037af800bcc74bbdac338355c7f331bd913 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 2 Nov 2018 01:45:41 -0700 Subject: [PATCH 0239/1286] x86/retpoline: Make CONFIG_RETPOLINE depend on compiler support commit 4cd24de3a0980bf3100c9dcb08ef65ca7c31af48 upstream Since retpoline capable compilers are widely available, make CONFIG_RETPOLINE hard depend on the compiler capability. Break the build when CONFIG_RETPOLINE is enabled and the compiler does not support it. Emit an error message in that case: "arch/x86/Makefile:226: *** You are building kernel with non-retpoline compiler, please update your compiler.. Stop." [dwmw: Fail the build with non-retpoline compiler] Suggested-by: Peter Zijlstra Signed-off-by: Zhenzhong Duan Signed-off-by: Thomas Gleixner Cc: David Woodhouse Cc: Borislav Petkov Cc: Daniel Borkmann Cc: H. Peter Anvin Cc: Konrad Rzeszutek Wilk Cc: Andy Lutomirski Cc: Masahiro Yamada Cc: Michal Marek Cc: Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/cca0cb20-f9e2-4094-840b-fb0f8810cd34@default Signed-off-by: Greg Kroah-Hartman --- arch/x86/Kconfig | 4 ---- arch/x86/Makefile | 5 +++-- arch/x86/include/asm/nospec-branch.h | 10 ++++++---- arch/x86/kernel/cpu/bugs.c | 2 +- scripts/Makefile.build | 2 -- 5 files changed, 10 insertions(+), 13 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 2af0af33362a..026c2f2ac702 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -440,10 +440,6 @@ config RETPOLINE branches. Requires a compiler with -mindirect-branch=thunk-extern support for full protection. The kernel may run slower. - Without compiler support, at least indirect branches in assembler - code are eliminated. Since this includes the syscall entry path, - it is not entirely pointless. - config INTEL_RDT bool "Intel Resource Director Technology support" default n diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 1c4d012550ec..ce3658dd98e8 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -241,9 +241,10 @@ KBUILD_CFLAGS += -fno-asynchronous-unwind-tables # Avoid indirect branches in kernel to deal with Spectre ifdef CONFIG_RETPOLINE -ifneq ($(RETPOLINE_CFLAGS),) - KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) -DRETPOLINE +ifeq ($(RETPOLINE_CFLAGS),) + $(error You are building kernel with non-retpoline compiler, please update your compiler.) endif + KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) endif archscripts: scripts_basic diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 7827f17e9a8a..690c838e3a7e 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -162,11 +162,12 @@ _ASM_PTR " 999b\n\t" \ ".popsection\n\t" -#if defined(CONFIG_X86_64) && defined(RETPOLINE) +#ifdef CONFIG_RETPOLINE +#ifdef CONFIG_X86_64 /* - * Since the inline asm uses the %V modifier which is only in newer GCC, - * the 64-bit one is dependent on RETPOLINE not CONFIG_RETPOLINE. + * Inline asm uses the %V modifier which is only in newer GCC + * which is ensured when CONFIG_RETPOLINE is defined. */ # define CALL_NOSPEC \ ANNOTATE_NOSPEC_ALTERNATIVE \ @@ -181,7 +182,7 @@ X86_FEATURE_RETPOLINE_AMD) # define THUNK_TARGET(addr) [thunk_target] "r" (addr) -#elif defined(CONFIG_X86_32) && defined(CONFIG_RETPOLINE) +#else /* CONFIG_X86_32 */ /* * For i386 we use the original ret-equivalent retpoline, because * otherwise we'll run out of registers. We don't care about CET @@ -211,6 +212,7 @@ X86_FEATURE_RETPOLINE_AMD) # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) +#endif #else /* No retpoline for C / inline asm */ # define CALL_NOSPEC "call *%[thunk_target]\n" # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 700d1149601e..a0146ee52124 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -251,7 +251,7 @@ static void __init spec2_print_if_secure(const char *reason) static inline bool retp_compiler(void) { - return __is_defined(RETPOLINE); + return __is_defined(CONFIG_RETPOLINE); } static inline bool match_option(const char *arg, int arglen, const char *opt) diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 7143da06d702..be9e5deb58ba 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -272,10 +272,8 @@ else objtool_args += $(call cc-ifversion, -lt, 0405, --no-unreachable) endif ifdef CONFIG_RETPOLINE -ifneq ($(RETPOLINE_CFLAGS),) objtool_args += --retpoline endif -endif ifdef CONFIG_MODVERSIONS -- GitLab From 8bbb50b6de99c178acd648a73098009073139f46 Mon Sep 17 00:00:00 2001 From: Zhenzhong Duan Date: Fri, 2 Nov 2018 01:45:41 -0700 Subject: [PATCH 0240/1286] x86/retpoline: Remove minimal retpoline support commit ef014aae8f1cd2793e4e014bbb102bed53f852b7 upstream Now that CONFIG_RETPOLINE hard depends on compiler support, there is no reason to keep the minimal retpoline support around which only provided basic protection in the assembly files. Suggested-by: Peter Zijlstra Signed-off-by: Zhenzhong Duan Signed-off-by: Thomas Gleixner Cc: David Woodhouse Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Konrad Rzeszutek Wilk Cc: Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/f06f0a89-5587-45db-8ed2-0a9d6638d5c0@default Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/nospec-branch.h | 3 --- arch/x86/kernel/cpu/bugs.c | 13 ++----------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 690c838e3a7e..20d016b4e986 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -221,11 +221,8 @@ /* The Spectre V2 mitigation variants */ enum spectre_v2_mitigation { SPECTRE_V2_NONE, - SPECTRE_V2_RETPOLINE_MINIMAL, - SPECTRE_V2_RETPOLINE_MINIMAL_AMD, SPECTRE_V2_RETPOLINE_GENERIC, SPECTRE_V2_RETPOLINE_AMD, - SPECTRE_V2_IBRS, SPECTRE_V2_IBRS_ENHANCED, }; diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index a0146ee52124..dd87fe5397c3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -134,8 +134,6 @@ enum spectre_v2_mitigation_cmd { static const char *spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", - [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", - [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", @@ -249,11 +247,6 @@ static void __init spec2_print_if_secure(const char *reason) pr_info("%s selected on command line.\n", reason); } -static inline bool retp_compiler(void) -{ - return __is_defined(CONFIG_RETPOLINE); -} - static inline bool match_option(const char *arg, int arglen, const char *opt) { int len = strlen(opt); @@ -414,14 +407,12 @@ static void __init spectre_v2_select_mitigation(void) pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); goto retpoline_generic; } - mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : - SPECTRE_V2_RETPOLINE_MINIMAL_AMD; + mode = SPECTRE_V2_RETPOLINE_AMD; setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); setup_force_cpu_cap(X86_FEATURE_RETPOLINE); } else { retpoline_generic: - mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : - SPECTRE_V2_RETPOLINE_MINIMAL; + mode = SPECTRE_V2_RETPOLINE_GENERIC; setup_force_cpu_cap(X86_FEATURE_RETPOLINE); } -- GitLab From 7d422ca1950a1f04bc467e706ae6f89840b0bd16 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:29 +0100 Subject: [PATCH 0241/1286] x86/speculation: Update the TIF_SSBD comment commit 8eb729b77faf83ac4c1f363a9ad68d042415f24c upstream "Reduced Data Speculation" is an obsolete term. The correct new name is "Speculative store bypass disable" - which is abbreviated into SSBD. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185003.593893901@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/thread_info.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 95ff2d7f553f..2976312b826a 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -81,7 +81,7 @@ struct thread_info { #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/ -#define TIF_SSBD 5 /* Reduced data speculation */ +#define TIF_SSBD 5 /* Speculative store bypass disable */ #define TIF_SYSCALL_EMU 6 /* syscall emulation active */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ -- GitLab From 4398714cb7d595725a4840da137faeac47c10669 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:30 +0100 Subject: [PATCH 0242/1286] x86/speculation: Clean up spectre_v2_parse_cmdline() commit 24848509aa55eac39d524b587b051f4e86df3c12 upstream Remove the unnecessary 'else' statement in spectre_v2_parse_cmdline() to save an indentation level. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185003.688010903@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index dd87fe5397c3..cb087dee5117 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -275,22 +275,21 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) return SPECTRE_V2_CMD_NONE; - else { - ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); - if (ret < 0) - return SPECTRE_V2_CMD_AUTO; - for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { - if (!match_option(arg, ret, mitigation_options[i].option)) - continue; - cmd = mitigation_options[i].cmd; - break; - } + ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); + if (ret < 0) + return SPECTRE_V2_CMD_AUTO; - if (i >= ARRAY_SIZE(mitigation_options)) { - pr_err("unknown option (%s). Switching to AUTO select\n", arg); - return SPECTRE_V2_CMD_AUTO; - } + for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { + if (!match_option(arg, ret, mitigation_options[i].option)) + continue; + cmd = mitigation_options[i].cmd; + break; + } + + if (i >= ARRAY_SIZE(mitigation_options)) { + pr_err("unknown option (%s). Switching to AUTO select\n", arg); + return SPECTRE_V2_CMD_AUTO; } if ((cmd == SPECTRE_V2_CMD_RETPOLINE || -- GitLab From 05dd5dc4c4fba8a8457b0bcb5336d4fe22d5c013 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:31 +0100 Subject: [PATCH 0243/1286] x86/speculation: Remove unnecessary ret variable in cpu_show_common() commit b86bda0426853bfe8a3506c7d2a5b332760ae46b upstream Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185003.783903657@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index cb087dee5117..fcd710ab26b5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -844,8 +844,6 @@ static ssize_t l1tf_show_state(char *buf) static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, char *buf, unsigned int bug) { - int ret; - if (!boot_cpu_has_bug(bug)) return sprintf(buf, "Not affected\n"); @@ -860,13 +858,12 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr return sprintf(buf, "Mitigation: __user pointer sanitization\n"); case X86_BUG_SPECTRE_V2: - ret = sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], + return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", spectre_v2_module_string()); - return ret; case X86_BUG_SPEC_STORE_BYPASS: return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); -- GitLab From 8588c7d4a487927356a5026982bd89b45a2092fe Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:32 +0100 Subject: [PATCH 0244/1286] x86/speculation: Move STIPB/IBPB string conditionals out of cpu_show_common() commit a8f76ae41cd633ac00be1b3019b1eb4741be3828 upstream The Spectre V2 printout in cpu_show_common() handles conditionals for the various mitigation methods directly in the sprintf() argument list. That's hard to read and will become unreadable if more complex decisions need to be made for a particular method. Move the conditionals for STIBP and IBPB string selection into helper functions, so they can be extended later on. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185003.874479208@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index fcd710ab26b5..06494a0cb107 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -841,6 +841,22 @@ static ssize_t l1tf_show_state(char *buf) } #endif +static char *stibp_state(void) +{ + if (x86_spec_ctrl_base & SPEC_CTRL_STIBP) + return ", STIBP"; + else + return ""; +} + +static char *ibpb_state(void) +{ + if (boot_cpu_has(X86_FEATURE_USE_IBPB)) + return ", IBPB"; + else + return ""; +} + static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, char *buf, unsigned int bug) { @@ -859,9 +875,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr case X86_BUG_SPECTRE_V2: return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], - boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", + ibpb_state(), boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", - (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", + stibp_state(), boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", spectre_v2_module_string()); -- GitLab From aca2ddbc23800652ec2f09c2df76f417823cda77 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:33 +0100 Subject: [PATCH 0245/1286] x86/speculation: Disable STIBP when enhanced IBRS is in use commit 34bce7c9690b1d897686aac89604ba7adc365556 upstream If enhanced IBRS is active, STIBP is redundant for mitigating Spectre v2 user space exploits from hyperthread sibling. Disable STIBP when enhanced IBRS is used. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185003.966801480@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 06494a0cb107..3b2c5f26bde2 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -319,6 +319,10 @@ static bool stibp_needed(void) if (spectre_v2_enabled == SPECTRE_V2_NONE) return false; + /* Enhanced IBRS makes using STIBP unnecessary. */ + if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) + return false; + if (!boot_cpu_has(X86_FEATURE_STIBP)) return false; @@ -843,6 +847,9 @@ static ssize_t l1tf_show_state(char *buf) static char *stibp_state(void) { + if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) + return ""; + if (x86_spec_ctrl_base & SPEC_CTRL_STIBP) return ", STIBP"; else -- GitLab From 999b295ad1a9980754c6d63e9f8be109a3574118 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:34 +0100 Subject: [PATCH 0246/1286] x86/speculation: Rename SSBD update functions commit 26c4d75b234040c11728a8acb796b3a85ba7507c upstream During context switch, the SSBD bit in SPEC_CTRL MSR is updated according to changes of the TIF_SSBD flag in the current and next running task. Currently, only the bit controlling speculative store bypass disable in SPEC_CTRL MSR is updated and the related update functions all have "speculative_store" or "ssb" in their names. For enhanced mitigation control other bits in SPEC_CTRL MSR need to be updated as well, which makes the SSB names inadequate. Rename the "speculative_store*" functions to a more generic name. No functional change. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.058866968@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/spec-ctrl.h | 6 +++--- arch/x86/kernel/cpu/bugs.c | 4 ++-- arch/x86/kernel/process.c | 12 ++++++------ 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index ae7c2c5cd7f0..8e2f8411c7a7 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -70,11 +70,11 @@ extern void speculative_store_bypass_ht_init(void); static inline void speculative_store_bypass_ht_init(void) { } #endif -extern void speculative_store_bypass_update(unsigned long tif); +extern void speculation_ctrl_update(unsigned long tif); -static inline void speculative_store_bypass_update_current(void) +static inline void speculation_ctrl_update_current(void) { - speculative_store_bypass_update(current_thread_info()->flags); + speculation_ctrl_update(current_thread_info()->flags); } #endif diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 3b2c5f26bde2..a06ddbd25219 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -199,7 +199,7 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : ssbd_spec_ctrl_to_tif(hostval); - speculative_store_bypass_update(tif); + speculation_ctrl_update(tif); } } EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); @@ -629,7 +629,7 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) * mitigation until it is next scheduled. */ if (task == current && update) - speculative_store_bypass_update_current(); + speculation_ctrl_update_current(); return 0; } diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 988a98f34c66..48c4a0fbd764 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -398,27 +398,27 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); } -static __always_inline void intel_set_ssb_state(unsigned long tifn) +static __always_inline void spec_ctrl_update_msr(unsigned long tifn) { u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); wrmsrl(MSR_IA32_SPEC_CTRL, msr); } -static __always_inline void __speculative_store_bypass_update(unsigned long tifn) +static __always_inline void __speculation_ctrl_update(unsigned long tifn) { if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) amd_set_ssb_virt_state(tifn); else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) amd_set_core_ssb_state(tifn); else - intel_set_ssb_state(tifn); + spec_ctrl_update_msr(tifn); } -void speculative_store_bypass_update(unsigned long tif) +void speculation_ctrl_update(unsigned long tif) { preempt_disable(); - __speculative_store_bypass_update(tif); + __speculation_ctrl_update(tif); preempt_enable(); } @@ -455,7 +455,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); if ((tifp ^ tifn) & _TIF_SSBD) - __speculative_store_bypass_update(tifn); + __speculation_ctrl_update(tifn); } /* -- GitLab From bc4aa78e6954bd71295543163271262fede5d46f Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:35 +0100 Subject: [PATCH 0247/1286] x86/speculation: Reorganize speculation control MSRs update commit 01daf56875ee0cd50ed496a09b20eb369b45dfa5 upstream The logic to detect whether there's a change in the previous and next task's flag relevant to update speculation control MSRs is spread out across multiple functions. Consolidate all checks needed for updating speculation control MSRs into the new __speculation_ctrl_update() helper function. This makes it easy to pick the right speculation control MSR and the bits in MSR_IA32_SPEC_CTRL that need updating based on TIF flags changes. Originally-by: Thomas Lendacky Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.151077005@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/process.c | 46 ++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 48c4a0fbd764..65c9edd08c27 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -398,27 +398,40 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); } -static __always_inline void spec_ctrl_update_msr(unsigned long tifn) -{ - u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn); - - wrmsrl(MSR_IA32_SPEC_CTRL, msr); -} +/* + * Update the MSRs managing speculation control, during context switch. + * + * tifp: Previous task's thread flags + * tifn: Next task's thread flags + */ +static __always_inline void __speculation_ctrl_update(unsigned long tifp, + unsigned long tifn) +{ + u64 msr = x86_spec_ctrl_base; + bool updmsr = false; + + /* If TIF_SSBD is different, select the proper mitigation method */ + if ((tifp ^ tifn) & _TIF_SSBD) { + if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { + amd_set_ssb_virt_state(tifn); + } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { + amd_set_core_ssb_state(tifn); + } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || + static_cpu_has(X86_FEATURE_AMD_SSBD)) { + msr |= ssbd_tif_to_spec_ctrl(tifn); + updmsr = true; + } + } -static __always_inline void __speculation_ctrl_update(unsigned long tifn) -{ - if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) - amd_set_ssb_virt_state(tifn); - else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) - amd_set_core_ssb_state(tifn); - else - spec_ctrl_update_msr(tifn); + if (updmsr) + wrmsrl(MSR_IA32_SPEC_CTRL, msr); } void speculation_ctrl_update(unsigned long tif) { + /* Forced update. Make sure all relevant TIF flags are different */ preempt_disable(); - __speculation_ctrl_update(tif); + __speculation_ctrl_update(~tif, tif); preempt_enable(); } @@ -454,8 +467,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, if ((tifp ^ tifn) & _TIF_NOCPUID) set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); - if ((tifp ^ tifn) & _TIF_SSBD) - __speculation_ctrl_update(tifn); + __speculation_ctrl_update(tifp, tifn); } /* -- GitLab From 01659361c63fdc91c0af239d08cdd211d590a656 Mon Sep 17 00:00:00 2001 From: "Peter Zijlstra (Intel)" Date: Sun, 25 Nov 2018 19:33:36 +0100 Subject: [PATCH 0248/1286] sched/smt: Make sched_smt_present track topology commit c5511d03ec090980732e929c318a7a6374b5550e upstream Currently the 'sched_smt_present' static key is enabled when at CPU bringup SMT topology is observed, but it is never disabled. However there is demand to also disable the key when the topology changes such that there is no SMT present anymore. Implement this by making the key count the number of cores that have SMT enabled. In particular, the SMT topology bits are set before interrrupts are enabled and similarly, are cleared after interrupts are disabled for the last time and the CPU dies. Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.246110444@linutronix.de Signed-off-by: Greg Kroah-Hartman --- kernel/sched/core.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 3bc664662081..0552ddbb25e2 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5617,15 +5617,10 @@ int sched_cpu_activate(unsigned int cpu) #ifdef CONFIG_SCHED_SMT /* - * The sched_smt_present static key needs to be evaluated on every - * hotplug event because at boot time SMT might be disabled when - * the number of booted CPUs is limited. - * - * If then later a sibling gets hotplugged, then the key would stay - * off and SMT scheduling would never be functional. + * When going up, increment the number of cores with SMT present. */ - if (cpumask_weight(cpu_smt_mask(cpu)) > 1) - static_branch_enable_cpuslocked(&sched_smt_present); + if (cpumask_weight(cpu_smt_mask(cpu)) == 2) + static_branch_inc_cpuslocked(&sched_smt_present); #endif set_cpu_active(cpu, true); @@ -5669,6 +5664,14 @@ int sched_cpu_deactivate(unsigned int cpu) */ synchronize_rcu_mult(call_rcu, call_rcu_sched); +#ifdef CONFIG_SCHED_SMT + /* + * When going down, decrement the number of cores with SMT present. + */ + if (cpumask_weight(cpu_smt_mask(cpu)) == 2) + static_branch_dec_cpuslocked(&sched_smt_present); +#endif + if (!sched_smp_initialized) return 0; -- GitLab From 44ac7cd01544dd12241bc0c0e0eb5604ad77379a Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:37 +0100 Subject: [PATCH 0249/1286] x86/Kconfig: Select SCHED_SMT if SMP enabled commit dbe733642e01dd108f71436aaea7b328cb28fd87 upstream CONFIG_SCHED_SMT is enabled by all distros, so there is not a real point to have it configurable. The runtime overhead in the core scheduler code is minimal because the actual SMT scheduling parts are conditional on a static key. This allows to expose the scheduler's SMT state static key to the speculation control code. Alternatively the scheduler's static key could be made always available when CONFIG_SMP is enabled, but that's just adding an unused static key to every other architecture for nothing. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.337452245@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/Kconfig | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 026c2f2ac702..4f393eb9745f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -955,13 +955,7 @@ config NR_CPUS approximately eight kilobytes to the kernel image. config SCHED_SMT - bool "SMT (Hyperthreading) scheduler support" - depends on SMP - ---help--- - SMT scheduler support improves the CPU scheduler's decision making - when dealing with Intel Pentium 4 chips with HyperThreading at a - cost of slightly increased overhead in some places. If unsure say - N here. + def_bool y if SMP config SCHED_MC def_bool y -- GitLab From 0e797117f18573ab31f72aed0924ff7999d860ea Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:38 +0100 Subject: [PATCH 0250/1286] sched/smt: Expose sched_smt_present static key commit 321a874a7ef85655e93b3206d0f36b4a6097f948 upstream Make the scheduler's 'sched_smt_present' static key globaly available, so it can be used in the x86 speculation control code. Provide a query function and a stub for the CONFIG_SMP=n case. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.430168326@linutronix.de Signed-off-by: Greg Kroah-Hartman --- include/linux/sched/smt.h | 18 ++++++++++++++++++ kernel/sched/sched.h | 4 +--- 2 files changed, 19 insertions(+), 3 deletions(-) create mode 100644 include/linux/sched/smt.h diff --git a/include/linux/sched/smt.h b/include/linux/sched/smt.h new file mode 100644 index 000000000000..c9e0be514110 --- /dev/null +++ b/include/linux/sched/smt.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_SCHED_SMT_H +#define _LINUX_SCHED_SMT_H + +#include + +#ifdef CONFIG_SCHED_SMT +extern struct static_key_false sched_smt_present; + +static __always_inline bool sched_smt_active(void) +{ + return static_branch_likely(&sched_smt_present); +} +#else +static inline bool sched_smt_active(void) { return false; } +#endif + +#endif diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 63d999dfec80..b3ba6e5e99f2 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -825,9 +826,6 @@ static inline int cpu_of(struct rq *rq) #ifdef CONFIG_SCHED_SMT - -extern struct static_key_false sched_smt_present; - extern void __update_idle_core(struct rq *rq); static inline void update_idle_core(struct rq *rq) -- GitLab From 36a4c5fc92857711019dc56be2669e19f8c3c86e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:39 +0100 Subject: [PATCH 0251/1286] x86/speculation: Rework SMT state change commit a74cfffb03b73d41e08f84c2e5c87dec0ce3db9f upstream arch_smt_update() is only called when the sysfs SMT control knob is changed. This means that when SMT is enabled in the sysfs control knob the system is considered to have SMT active even if all siblings are offline. To allow finegrained control of the speculation mitigations, the actual SMT state is more interesting than the fact that siblings could be enabled. Rework the code, so arch_smt_update() is invoked from each individual CPU hotplug function, and simplify the update function while at it. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.521974984@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 11 +++++------ include/linux/sched/smt.h | 2 ++ kernel/cpu.c | 15 +++++++++------ 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index a06ddbd25219..fa7a35ab831f 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -342,16 +343,14 @@ void arch_smt_update(void) return; mutex_lock(&spec_ctrl_mutex); - mask = x86_spec_ctrl_base; - if (cpu_smt_control == CPU_SMT_ENABLED) + + mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; + if (sched_smt_active()) mask |= SPEC_CTRL_STIBP; - else - mask &= ~SPEC_CTRL_STIBP; if (mask != x86_spec_ctrl_base) { pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", - cpu_smt_control == CPU_SMT_ENABLED ? - "Enabling" : "Disabling"); + mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); x86_spec_ctrl_base = mask; on_each_cpu(update_stibp_msr, NULL, 1); } diff --git a/include/linux/sched/smt.h b/include/linux/sched/smt.h index c9e0be514110..59d3736c454c 100644 --- a/include/linux/sched/smt.h +++ b/include/linux/sched/smt.h @@ -15,4 +15,6 @@ static __always_inline bool sched_smt_active(void) static inline bool sched_smt_active(void) { return false; } #endif +void arch_smt_update(void); + #endif diff --git a/kernel/cpu.c b/kernel/cpu.c index 90cf6a04e08a..5c907d96e3dd 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -347,6 +348,12 @@ void cpu_hotplug_enable(void) EXPORT_SYMBOL_GPL(cpu_hotplug_enable); #endif /* CONFIG_HOTPLUG_CPU */ +/* + * Architectures that need SMT-specific errata handling during SMT hotplug + * should override this. + */ +void __weak arch_smt_update(void) { } + #ifdef CONFIG_HOTPLUG_SMT enum cpuhp_smt_control cpu_smt_control __read_mostly = CPU_SMT_ENABLED; EXPORT_SYMBOL_GPL(cpu_smt_control); @@ -998,6 +1005,7 @@ static int __ref _cpu_down(unsigned int cpu, int tasks_frozen, * concurrent CPU hotplug via cpu_add_remove_lock. */ lockup_detector_cleanup(); + arch_smt_update(); return ret; } @@ -1126,6 +1134,7 @@ static int _cpu_up(unsigned int cpu, int tasks_frozen, enum cpuhp_state target) ret = cpuhp_up_callbacks(cpu, st, target); out: cpus_write_unlock(); + arch_smt_update(); return ret; } @@ -2045,12 +2054,6 @@ static void cpuhp_online_cpu_device(unsigned int cpu) kobject_uevent(&dev->kobj, KOBJ_ONLINE); } -/* - * Architectures that need SMT-specific errata handling during SMT hotplug - * should override this. - */ -void __weak arch_smt_update(void) { }; - static int cpuhp_smt_disable(enum cpuhp_smt_control ctrlval) { int cpu, ret = 0; -- GitLab From 8345d546238f68e7fe219df25eeecb200f34334b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:40 +0100 Subject: [PATCH 0252/1286] x86/l1tf: Show actual SMT state commit 130d6f946f6f2a972ee3ec8540b7243ab99abe97 upstream Use the now exposed real SMT state, not the SMT sysfs control knob state. This reflects the state of the system when the mitigation status is queried. This does not change the warning in the VMX launch code. There the dependency on the control knob makes sense because siblings could be brought online anytime after launching the VM. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.613357354@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index fa7a35ab831f..ccd08d127624 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -829,13 +829,14 @@ static ssize_t l1tf_show_state(char *buf) if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && - cpu_smt_control == CPU_SMT_ENABLED)) + sched_smt_active())) { return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, l1tf_vmx_states[l1tf_vmx_mitigation]); + } return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, l1tf_vmx_states[l1tf_vmx_mitigation], - cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled"); + sched_smt_active() ? "vulnerable" : "disabled"); } #else static ssize_t l1tf_show_state(char *buf) -- GitLab From 72f90a89be9e125c1dd44a4d70b83055d1c3753e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:41 +0100 Subject: [PATCH 0253/1286] x86/speculation: Reorder the spec_v2 code commit 15d6b7aab0793b2de8a05d8a828777dd24db424e upstream Reorder the code so it is better grouped. No functional change. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.707122879@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 168 ++++++++++++++++++------------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ccd08d127624..9fea8ff20c1f 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -123,29 +123,6 @@ void __init check_bugs(void) #endif } -/* The kernel command line selection */ -enum spectre_v2_mitigation_cmd { - SPECTRE_V2_CMD_NONE, - SPECTRE_V2_CMD_AUTO, - SPECTRE_V2_CMD_FORCE, - SPECTRE_V2_CMD_RETPOLINE, - SPECTRE_V2_CMD_RETPOLINE_GENERIC, - SPECTRE_V2_CMD_RETPOLINE_AMD, -}; - -static const char *spectre_v2_strings[] = { - [SPECTRE_V2_NONE] = "Vulnerable", - [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", - [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", - [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", -}; - -#undef pr_fmt -#define pr_fmt(fmt) "Spectre V2 : " fmt - -static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = - SPECTRE_V2_NONE; - void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) { @@ -215,6 +192,12 @@ static void x86_amd_ssb_disable(void) wrmsrl(MSR_AMD64_LS_CFG, msrval); } +#undef pr_fmt +#define pr_fmt(fmt) "Spectre V2 : " fmt + +static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = + SPECTRE_V2_NONE; + #ifdef RETPOLINE static bool spectre_v2_bad_module; @@ -236,18 +219,6 @@ static inline const char *spectre_v2_module_string(void) static inline const char *spectre_v2_module_string(void) { return ""; } #endif -static void __init spec2_print_if_insecure(const char *reason) -{ - if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) - pr_info("%s selected on command line.\n", reason); -} - -static void __init spec2_print_if_secure(const char *reason) -{ - if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) - pr_info("%s selected on command line.\n", reason); -} - static inline bool match_option(const char *arg, int arglen, const char *opt) { int len = strlen(opt); @@ -255,24 +226,53 @@ static inline bool match_option(const char *arg, int arglen, const char *opt) return len == arglen && !strncmp(arg, opt, len); } +/* The kernel command line selection for spectre v2 */ +enum spectre_v2_mitigation_cmd { + SPECTRE_V2_CMD_NONE, + SPECTRE_V2_CMD_AUTO, + SPECTRE_V2_CMD_FORCE, + SPECTRE_V2_CMD_RETPOLINE, + SPECTRE_V2_CMD_RETPOLINE_GENERIC, + SPECTRE_V2_CMD_RETPOLINE_AMD, +}; + +static const char *spectre_v2_strings[] = { + [SPECTRE_V2_NONE] = "Vulnerable", + [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", + [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", + [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", +}; + static const struct { const char *option; enum spectre_v2_mitigation_cmd cmd; bool secure; } mitigation_options[] = { - { "off", SPECTRE_V2_CMD_NONE, false }, - { "on", SPECTRE_V2_CMD_FORCE, true }, - { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, - { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, - { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, - { "auto", SPECTRE_V2_CMD_AUTO, false }, + { "off", SPECTRE_V2_CMD_NONE, false }, + { "on", SPECTRE_V2_CMD_FORCE, true }, + { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, + { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, + { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, + { "auto", SPECTRE_V2_CMD_AUTO, false }, }; +static void __init spec2_print_if_insecure(const char *reason) +{ + if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) + pr_info("%s selected on command line.\n", reason); +} + +static void __init spec2_print_if_secure(const char *reason) +{ + if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) + pr_info("%s selected on command line.\n", reason); +} + static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) { + enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; char arg[20]; int ret, i; - enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) return SPECTRE_V2_CMD_NONE; @@ -315,48 +315,6 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return cmd; } -static bool stibp_needed(void) -{ - if (spectre_v2_enabled == SPECTRE_V2_NONE) - return false; - - /* Enhanced IBRS makes using STIBP unnecessary. */ - if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) - return false; - - if (!boot_cpu_has(X86_FEATURE_STIBP)) - return false; - - return true; -} - -static void update_stibp_msr(void *info) -{ - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); -} - -void arch_smt_update(void) -{ - u64 mask; - - if (!stibp_needed()) - return; - - mutex_lock(&spec_ctrl_mutex); - - mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; - if (sched_smt_active()) - mask |= SPEC_CTRL_STIBP; - - if (mask != x86_spec_ctrl_base) { - pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", - mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); - x86_spec_ctrl_base = mask; - on_each_cpu(update_stibp_msr, NULL, 1); - } - mutex_unlock(&spec_ctrl_mutex); -} - static void __init spectre_v2_select_mitigation(void) { enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); @@ -459,6 +417,48 @@ static void __init spectre_v2_select_mitigation(void) arch_smt_update(); } +static bool stibp_needed(void) +{ + if (spectre_v2_enabled == SPECTRE_V2_NONE) + return false; + + /* Enhanced IBRS makes using STIBP unnecessary. */ + if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) + return false; + + if (!boot_cpu_has(X86_FEATURE_STIBP)) + return false; + + return true; +} + +static void update_stibp_msr(void *info) +{ + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); +} + +void arch_smt_update(void) +{ + u64 mask; + + if (!stibp_needed()) + return; + + mutex_lock(&spec_ctrl_mutex); + + mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; + if (sched_smt_active()) + mask |= SPEC_CTRL_STIBP; + + if (mask != x86_spec_ctrl_base) { + pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", + mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); + x86_spec_ctrl_base = mask; + on_each_cpu(update_stibp_msr, NULL, 1); + } + mutex_unlock(&spec_ctrl_mutex); +} + #undef pr_fmt #define pr_fmt(fmt) "Speculative Store Bypass: " fmt -- GitLab From caa118cf4c7997a35f6a18f5a16c38c7a9c71e3f Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:42 +0100 Subject: [PATCH 0254/1286] x86/speculation: Mark string arrays const correctly commit 8770709f411763884535662744a3786a1806afd3 upstream checkpatch.pl muttered when reshuffling the code: WARNING: static const char * array should probably be static const char * const Fix up all the string arrays. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.800018931@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 9fea8ff20c1f..45e08aacefe3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -236,7 +236,7 @@ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_RETPOLINE_AMD, }; -static const char *spectre_v2_strings[] = { +static const char * const spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", @@ -473,7 +473,7 @@ enum ssb_mitigation_cmd { SPEC_STORE_BYPASS_CMD_SECCOMP, }; -static const char *ssb_strings[] = { +static const char * const ssb_strings[] = { [SPEC_STORE_BYPASS_NONE] = "Vulnerable", [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", @@ -813,7 +813,7 @@ early_param("l1tf", l1tf_cmdline); #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" #if IS_ENABLED(CONFIG_KVM_INTEL) -static const char *l1tf_vmx_states[] = { +static const char * const l1tf_vmx_states[] = { [VMENTER_L1D_FLUSH_AUTO] = "auto", [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", -- GitLab From 95d41f1332f78fa6ad19459d1b98ad70407dd88b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:43 +0100 Subject: [PATCH 0255/1286] x86/speculataion: Mark command line parser data __initdata commit 30ba72a990f5096ae08f284de17986461efcc408 upstream No point to keep that around. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.893886356@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 45e08aacefe3..b11c7dfcae0e 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -247,7 +247,7 @@ static const struct { const char *option; enum spectre_v2_mitigation_cmd cmd; bool secure; -} mitigation_options[] = { +} mitigation_options[] __initdata = { { "off", SPECTRE_V2_CMD_NONE, false }, { "on", SPECTRE_V2_CMD_FORCE, true }, { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, @@ -483,7 +483,7 @@ static const char * const ssb_strings[] = { static const struct { const char *option; enum ssb_mitigation_cmd cmd; -} ssb_mitigation_options[] = { +} ssb_mitigation_options[] __initdata = { { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ -- GitLab From ebd473909994d4ecce8e973f048f06d999f84845 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:44 +0100 Subject: [PATCH 0256/1286] x86/speculation: Unify conditional spectre v2 print functions commit 495d470e9828500e0155027f230449ac5e29c025 upstream There is no point in having two functions and a conditional at the call site. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185004.986890749@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index b11c7dfcae0e..e3b444dd0039 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -256,15 +256,9 @@ static const struct { { "auto", SPECTRE_V2_CMD_AUTO, false }, }; -static void __init spec2_print_if_insecure(const char *reason) +static void __init spec_v2_print_cond(const char *reason, bool secure) { - if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) - pr_info("%s selected on command line.\n", reason); -} - -static void __init spec2_print_if_secure(const char *reason) -{ - if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) + if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) pr_info("%s selected on command line.\n", reason); } @@ -307,11 +301,8 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return SPECTRE_V2_CMD_AUTO; } - if (mitigation_options[i].secure) - spec2_print_if_secure(mitigation_options[i].option); - else - spec2_print_if_insecure(mitigation_options[i].option); - + spec_v2_print_cond(mitigation_options[i].option, + mitigation_options[i].secure); return cmd; } -- GitLab From 90f293cc49fa44e24c07e74c89f3d87bc97cf41e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:45 +0100 Subject: [PATCH 0257/1286] x86/speculation: Add command line control for indirect branch speculation commit fa1202ef224391b6f5b26cdd44cc50495e8fab54 upstream Add command line control for user space indirect branch speculation mitigations. The new option is: spectre_v2_user= The initial options are: - on: Unconditionally enabled - off: Unconditionally disabled -auto: Kernel selects mitigation (default off for now) When the spectre_v2= command line argument is either 'on' or 'off' this implies that the application to application control follows that state even if a contradicting spectre_v2_user= argument is supplied. Originally-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.082720373@linutronix.de Signed-off-by: Greg Kroah-Hartman --- .../admin-guide/kernel-parameters.txt | 32 ++++- arch/x86/include/asm/nospec-branch.h | 10 ++ arch/x86/kernel/cpu/bugs.c | 133 +++++++++++++++--- 3 files changed, 156 insertions(+), 19 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 99a08722124d..f0c19f61db80 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3994,9 +3994,13 @@ spectre_v2= [X86] Control mitigation of Spectre variant 2 (indirect branch speculation) vulnerability. + The default operation protects the kernel from + user space attacks. - on - unconditionally enable - off - unconditionally disable + on - unconditionally enable, implies + spectre_v2_user=on + off - unconditionally disable, implies + spectre_v2_user=off auto - kernel detects whether your CPU model is vulnerable @@ -4006,6 +4010,12 @@ CONFIG_RETPOLINE configuration option, and the compiler with which the kernel was built. + Selecting 'on' will also enable the mitigation + against user space to user space task attacks. + + Selecting 'off' will disable both the kernel and + the user space protections. + Specific mitigations can also be selected manually: retpoline - replace indirect branches @@ -4015,6 +4025,24 @@ Not specifying this option is equivalent to spectre_v2=auto. + spectre_v2_user= + [X86] Control mitigation of Spectre variant 2 + (indirect branch speculation) vulnerability between + user space tasks + + on - Unconditionally enable mitigations. Is + enforced by spectre_v2=on + + off - Unconditionally disable mitigations. Is + enforced by spectre_v2=off + + auto - Kernel selects the mitigation depending on + the available CPU features and vulnerability. + Default is off. + + Not specifying this option is equivalent to + spectre_v2_user=auto. + spec_store_bypass_disable= [HW] Control Speculative Store Bypass (SSB) Disable mitigation (Speculative Store Bypass vulnerability) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 20d016b4e986..6057086fde1c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -3,6 +3,8 @@ #ifndef _ASM_X86_NOSPEC_BRANCH_H_ #define _ASM_X86_NOSPEC_BRANCH_H_ +#include + #include #include #include @@ -226,6 +228,12 @@ enum spectre_v2_mitigation { SPECTRE_V2_IBRS_ENHANCED, }; +/* The indirect branch speculation control variants */ +enum spectre_v2_user_mitigation { + SPECTRE_V2_USER_NONE, + SPECTRE_V2_USER_STRICT, +}; + /* The Speculative Store Bypass disable variants */ enum ssb_mitigation { SPEC_STORE_BYPASS_NONE, @@ -303,6 +311,8 @@ do { \ preempt_enable(); \ } while (0) +DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); + #endif /* __ASSEMBLY__ */ /* diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e3b444dd0039..bf5c3c4b9c19 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -53,6 +53,9 @@ static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; u64 __ro_after_init x86_amd_ls_cfg_base; u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; +/* Control conditional STIPB in switch_to() */ +DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); + void __init check_bugs(void) { identify_boot_cpu(); @@ -198,6 +201,9 @@ static void x86_amd_ssb_disable(void) static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE; +static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = + SPECTRE_V2_USER_NONE; + #ifdef RETPOLINE static bool spectre_v2_bad_module; @@ -236,6 +242,104 @@ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_RETPOLINE_AMD, }; +enum spectre_v2_user_cmd { + SPECTRE_V2_USER_CMD_NONE, + SPECTRE_V2_USER_CMD_AUTO, + SPECTRE_V2_USER_CMD_FORCE, +}; + +static const char * const spectre_v2_user_strings[] = { + [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", + [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", +}; + +static const struct { + const char *option; + enum spectre_v2_user_cmd cmd; + bool secure; +} v2_user_options[] __initdata = { + { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, + { "off", SPECTRE_V2_USER_CMD_NONE, false }, + { "on", SPECTRE_V2_USER_CMD_FORCE, true }, +}; + +static void __init spec_v2_user_print_cond(const char *reason, bool secure) +{ + if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) + pr_info("spectre_v2_user=%s forced on command line.\n", reason); +} + +static enum spectre_v2_user_cmd __init +spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) +{ + char arg[20]; + int ret, i; + + switch (v2_cmd) { + case SPECTRE_V2_CMD_NONE: + return SPECTRE_V2_USER_CMD_NONE; + case SPECTRE_V2_CMD_FORCE: + return SPECTRE_V2_USER_CMD_FORCE; + default: + break; + } + + ret = cmdline_find_option(boot_command_line, "spectre_v2_user", + arg, sizeof(arg)); + if (ret < 0) + return SPECTRE_V2_USER_CMD_AUTO; + + for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { + if (match_option(arg, ret, v2_user_options[i].option)) { + spec_v2_user_print_cond(v2_user_options[i].option, + v2_user_options[i].secure); + return v2_user_options[i].cmd; + } + } + + pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); + return SPECTRE_V2_USER_CMD_AUTO; +} + +static void __init +spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) +{ + enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; + bool smt_possible = IS_ENABLED(CONFIG_SMP); + + if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) + return; + + if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || + cpu_smt_control == CPU_SMT_NOT_SUPPORTED) + smt_possible = false; + + switch (spectre_v2_parse_user_cmdline(v2_cmd)) { + case SPECTRE_V2_USER_CMD_AUTO: + case SPECTRE_V2_USER_CMD_NONE: + goto set_mode; + case SPECTRE_V2_USER_CMD_FORCE: + mode = SPECTRE_V2_USER_STRICT; + break; + } + + /* Initialize Indirect Branch Prediction Barrier */ + if (boot_cpu_has(X86_FEATURE_IBPB)) { + setup_force_cpu_cap(X86_FEATURE_USE_IBPB); + pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); + } + + /* If enhanced IBRS is enabled no STIPB required */ + if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) + return; + +set_mode: + spectre_v2_user = mode; + /* Only print the STIBP mode when SMT possible */ + if (smt_possible) + pr_info("%s\n", spectre_v2_user_strings[mode]); +} + static const char * const spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", @@ -382,12 +486,6 @@ static void __init spectre_v2_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); - /* Initialize Indirect Branch Prediction Barrier if supported */ - if (boot_cpu_has(X86_FEATURE_IBPB)) { - setup_force_cpu_cap(X86_FEATURE_USE_IBPB); - pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); - } - /* * Retpoline means the kernel is safe because it has no indirect * branches. Enhanced IBRS protects firmware too, so, enable restricted @@ -404,23 +502,21 @@ static void __init spectre_v2_select_mitigation(void) pr_info("Enabling Restricted Speculation for firmware calls\n"); } + /* Set up IBPB and STIBP depending on the general spectre V2 command */ + spectre_v2_user_select_mitigation(cmd); + /* Enable STIBP if appropriate */ arch_smt_update(); } static bool stibp_needed(void) { - if (spectre_v2_enabled == SPECTRE_V2_NONE) - return false; - /* Enhanced IBRS makes using STIBP unnecessary. */ if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) return false; - if (!boot_cpu_has(X86_FEATURE_STIBP)) - return false; - - return true; + /* Check for strict user mitigation mode */ + return spectre_v2_user == SPECTRE_V2_USER_STRICT; } static void update_stibp_msr(void *info) @@ -841,10 +937,13 @@ static char *stibp_state(void) if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) return ""; - if (x86_spec_ctrl_base & SPEC_CTRL_STIBP) - return ", STIBP"; - else - return ""; + switch (spectre_v2_user) { + case SPECTRE_V2_USER_NONE: + return ", STIBP: disabled"; + case SPECTRE_V2_USER_STRICT: + return ", STIBP: forced"; + } + return ""; } static char *ibpb_state(void) -- GitLab From 1fe4e69a5ce7bf36fbd303e64cb63adb14708c0b Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Sun, 25 Nov 2018 19:33:46 +0100 Subject: [PATCH 0258/1286] x86/speculation: Prepare for per task indirect branch speculation control commit 5bfbe3ad5840d941b89bcac54b821ba14f50a0ba upstream To avoid the overhead of STIBP always on, it's necessary to allow per task control of STIBP. Add a new task flag TIF_SPEC_IB and evaluate it during context switch if SMT is active and flag evaluation is enabled by the speculation control code. Add the conditional evaluation to x86_virt_spec_ctrl() as well so the guest/host switch works properly. This has no effect because TIF_SPEC_IB cannot be set yet and the static key which controls evaluation is off. Preparatory patch for adding the control code. [ tglx: Simplify the context switch logic and make the TIF evaluation depend on SMP=y and on the static key controlling the conditional update. Rename it to TIF_SPEC_IB because it controls both STIBP and IBPB ] Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.176917199@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 5 +++-- arch/x86/include/asm/spec-ctrl.h | 12 ++++++++++++ arch/x86/include/asm/thread_info.h | 5 ++++- arch/x86/kernel/cpu/bugs.c | 4 ++++ arch/x86/kernel/process.c | 20 ++++++++++++++++++-- 5 files changed, 41 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ef7eec669a1b..62c62d3eb0ff 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -41,9 +41,10 @@ #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ -#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ +#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ +#define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ -#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ +#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index 8e2f8411c7a7..27b0bce3933b 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -53,12 +53,24 @@ static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn) return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); } +static inline u64 stibp_tif_to_spec_ctrl(u64 tifn) +{ + BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT); + return (tifn & _TIF_SPEC_IB) >> (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT); +} + static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl) { BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); } +static inline unsigned long stibp_spec_ctrl_to_tif(u64 spec_ctrl) +{ + BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT); + return (spec_ctrl & SPEC_CTRL_STIBP) << (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT); +} + static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) { return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 2976312b826a..78ebda74b225 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -85,6 +85,7 @@ struct thread_info { #define TIF_SYSCALL_EMU 6 /* syscall emulation active */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ +#define TIF_SPEC_IB 9 /* Indirect branch speculation mitigation */ #define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */ #define TIF_UPROBE 12 /* breakpointed or singlestepping */ #define TIF_PATCH_PENDING 13 /* pending live patching update */ @@ -112,6 +113,7 @@ struct thread_info { #define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) +#define _TIF_SPEC_IB (1 << TIF_SPEC_IB) #define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY) #define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) @@ -148,7 +150,8 @@ struct thread_info { /* flags to check in __switch_to() */ #define _TIF_WORK_CTXSW \ - (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD) + (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP| \ + _TIF_SSBD|_TIF_SPEC_IB) #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY) #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index bf5c3c4b9c19..5bba757fead1 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -147,6 +147,10 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) static_cpu_has(X86_FEATURE_AMD_SSBD)) hostval |= ssbd_tif_to_spec_ctrl(ti->flags); + /* Conditional STIBP enabled? */ + if (static_branch_unlikely(&switch_to_cond_stibp)) + hostval |= stibp_tif_to_spec_ctrl(ti->flags); + if (hostval != guestval) { msrval = setguest ? guestval : hostval; wrmsrl(MSR_IA32_SPEC_CTRL, msrval); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 65c9edd08c27..2baa10f05052 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -407,11 +407,17 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn) static __always_inline void __speculation_ctrl_update(unsigned long tifp, unsigned long tifn) { + unsigned long tif_diff = tifp ^ tifn; u64 msr = x86_spec_ctrl_base; bool updmsr = false; - /* If TIF_SSBD is different, select the proper mitigation method */ - if ((tifp ^ tifn) & _TIF_SSBD) { + /* + * If TIF_SSBD is different, select the proper mitigation + * method. Note that if SSBD mitigation is disabled or permanentely + * enabled this branch can't be taken because nothing can set + * TIF_SSBD. + */ + if (tif_diff & _TIF_SSBD) { if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { amd_set_ssb_virt_state(tifn); } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { @@ -423,6 +429,16 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, } } + /* + * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled, + * otherwise avoid the MSR write. + */ + if (IS_ENABLED(CONFIG_SMP) && + static_branch_unlikely(&switch_to_cond_stibp)) { + updmsr |= !!(tif_diff & _TIF_SPEC_IB); + msr |= stibp_tif_to_spec_ctrl(tifn); + } + if (updmsr) wrmsrl(MSR_IA32_SPEC_CTRL, msr); } -- GitLab From 7fe6a4baff26dc90fa8ebcbb8f844cc8d3fb256f Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:47 +0100 Subject: [PATCH 0259/1286] x86/process: Consolidate and simplify switch_to_xtra() code commit ff16701a29cba3aafa0bd1656d766813b2d0a811 upstream Move the conditional invocation of __switch_to_xtra() into an inline function so the logic can be shared between 32 and 64 bit. Remove the handthrough of the TSS pointer and retrieve the pointer directly in the bitmap handling function. Use this_cpu_ptr() instead of the per_cpu() indirection. This is a preparatory change so integration of conditional indirect branch speculation optimization happens only in one place. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.280855518@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/switch_to.h | 3 --- arch/x86/kernel/process.c | 12 +++++++----- arch/x86/kernel/process.h | 24 ++++++++++++++++++++++++ arch/x86/kernel/process_32.c | 10 +++------- arch/x86/kernel/process_64.c | 10 +++------- 5 files changed, 37 insertions(+), 22 deletions(-) create mode 100644 arch/x86/kernel/process.h diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 9b6df68d8fd1..12ef2b49d11b 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -11,9 +11,6 @@ struct task_struct *__switch_to_asm(struct task_struct *prev, __visible struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next); -struct tss_struct; -void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, - struct tss_struct *tss); /* This runs runs on the previous thread's stack. */ static inline void prepare_switch_to(struct task_struct *prev, diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 2baa10f05052..dd1157b4bd15 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -41,6 +41,8 @@ #include #include +#include "process.h" + /* * per-CPU TSS segments. Threads are completely 'soft' on Linux, * no more per-task TSS's. The TSS size is kept cacheline-aligned @@ -255,11 +257,12 @@ void arch_setup_new_exec(void) enable_cpuid(); } -static inline void switch_to_bitmap(struct tss_struct *tss, - struct thread_struct *prev, +static inline void switch_to_bitmap(struct thread_struct *prev, struct thread_struct *next, unsigned long tifp, unsigned long tifn) { + struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); + if (tifn & _TIF_IO_BITMAP) { /* * Copy the relevant range of the IO bitmap. @@ -451,8 +454,7 @@ void speculation_ctrl_update(unsigned long tif) preempt_enable(); } -void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, - struct tss_struct *tss) +void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) { struct thread_struct *prev, *next; unsigned long tifp, tifn; @@ -462,7 +464,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, tifn = READ_ONCE(task_thread_info(next_p)->flags); tifp = READ_ONCE(task_thread_info(prev_p)->flags); - switch_to_bitmap(tss, prev, next, tifp, tifn); + switch_to_bitmap(prev, next, tifp, tifn); propagate_user_return_notify(prev_p, next_p); diff --git a/arch/x86/kernel/process.h b/arch/x86/kernel/process.h new file mode 100644 index 000000000000..020fbfac3a27 --- /dev/null +++ b/arch/x86/kernel/process.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Code shared between 32 and 64 bit + +void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p); + +/* + * This needs to be inline to optimize for the common case where no extra + * work needs to be done. + */ +static inline void switch_to_extra(struct task_struct *prev, + struct task_struct *next) +{ + unsigned long next_tif = task_thread_info(next)->flags; + unsigned long prev_tif = task_thread_info(prev)->flags; + + /* + * __switch_to_xtra() handles debug registers, i/o bitmaps, + * speculation mitigations etc. + */ + if (unlikely(next_tif & _TIF_WORK_CTXSW_NEXT || + prev_tif & _TIF_WORK_CTXSW_PREV)) + __switch_to_xtra(prev, next); +} diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 5224c6099184..c2df91eab573 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -59,6 +59,8 @@ #include #include +#include "process.h" + void __show_regs(struct pt_regs *regs, int all) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; @@ -234,7 +236,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) struct fpu *prev_fpu = &prev->fpu; struct fpu *next_fpu = &next->fpu; int cpu = smp_processor_id(); - struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu); /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */ @@ -266,12 +267,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl)) set_iopl_mask(next->iopl); - /* - * Now maybe handle debug registers and/or IO bitmaps - */ - if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV || - task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT)) - __switch_to_xtra(prev_p, next_p, tss); + switch_to_extra(prev_p, next_p); /* * Leave lazy mode, flushing any hypercalls made here. diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index cbeecfcc66d6..ec63d6be5e02 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -59,6 +59,8 @@ #include #endif +#include "process.h" + __visible DEFINE_PER_CPU(unsigned long, rsp_scratch); /* Prints also some state that isn't saved in the pt_regs */ @@ -400,7 +402,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) struct fpu *prev_fpu = &prev->fpu; struct fpu *next_fpu = &next->fpu; int cpu = smp_processor_id(); - struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu); WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) && this_cpu_read(irq_count) != -1); @@ -467,12 +468,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Reload sp0. */ update_sp0(next_p); - /* - * Now maybe reload the debug registers and handle I/O bitmaps - */ - if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT || - task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV)) - __switch_to_xtra(prev_p, next_p, tss); + __switch_to_xtra(prev_p, next_p); #ifdef CONFIG_XEN_PV /* -- GitLab From ba523588b1bc0b9601e7ef102b56dc246a91d026 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:48 +0100 Subject: [PATCH 0260/1286] x86/speculation: Avoid __switch_to_xtra() calls commit 5635d99953f04b550738f6f4c1c532667c3fd872 upstream The TIF_SPEC_IB bit does not need to be evaluated in the decision to invoke __switch_to_xtra() when: - CONFIG_SMP is disabled - The conditional STIPB mode is disabled The TIF_SPEC_IB bit still controls IBPB in both cases so the TIF work mask checks might invoke __switch_to_xtra() for nothing if TIF_SPEC_IB is the only set bit in the work masks. Optimize it out by masking the bit at compile time for CONFIG_SMP=n and at run time when the static key controlling the conditional STIBP mode is disabled. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.374062201@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/thread_info.h | 13 +++++++++++-- arch/x86/kernel/process.h | 15 +++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 78ebda74b225..7b30338ca55b 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -149,9 +149,18 @@ struct thread_info { _TIF_FSCHECK) /* flags to check in __switch_to() */ -#define _TIF_WORK_CTXSW \ +#define _TIF_WORK_CTXSW_BASE \ (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP| \ - _TIF_SSBD|_TIF_SPEC_IB) + _TIF_SSBD) + +/* + * Avoid calls to __switch_to_xtra() on UP as STIBP is not evaluated. + */ +#ifdef CONFIG_SMP +# define _TIF_WORK_CTXSW (_TIF_WORK_CTXSW_BASE | _TIF_SPEC_IB) +#else +# define _TIF_WORK_CTXSW (_TIF_WORK_CTXSW_BASE) +#endif #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY) #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW) diff --git a/arch/x86/kernel/process.h b/arch/x86/kernel/process.h index 020fbfac3a27..898e97cf6629 100644 --- a/arch/x86/kernel/process.h +++ b/arch/x86/kernel/process.h @@ -2,6 +2,8 @@ // // Code shared between 32 and 64 bit +#include + void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p); /* @@ -14,6 +16,19 @@ static inline void switch_to_extra(struct task_struct *prev, unsigned long next_tif = task_thread_info(next)->flags; unsigned long prev_tif = task_thread_info(prev)->flags; + if (IS_ENABLED(CONFIG_SMP)) { + /* + * Avoid __switch_to_xtra() invocation when conditional + * STIPB is disabled and the only different bit is + * TIF_SPEC_IB. For CONFIG_SMP=n TIF_SPEC_IB is not + * in the TIF_WORK_CTXSW masks. + */ + if (!static_branch_likely(&switch_to_cond_stibp)) { + prev_tif &= ~_TIF_SPEC_IB; + next_tif &= ~_TIF_SPEC_IB; + } + } + /* * __switch_to_xtra() handles debug registers, i/o bitmaps, * speculation mitigations etc. -- GitLab From cbca99b96f06f540669f07f768e228014e38b3b6 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:49 +0100 Subject: [PATCH 0261/1286] x86/speculation: Prepare for conditional IBPB in switch_mm() commit 4c71a2b6fd7e42814aa68a6dec88abf3b42ea573 upstream The IBPB speculation barrier is issued from switch_mm() when the kernel switches to a user space task with a different mm than the user space task which ran last on the same CPU. An additional optimization is to avoid IBPB when the incoming task can be ptraced by the outgoing task. This optimization only works when switching directly between two user space tasks. When switching from a kernel task to a user space task the optimization fails because the previous task cannot be accessed anymore. So for quite some scenarios the optimization is just adding overhead. The upcoming conditional IBPB support will issue IBPB only for user space tasks which have the TIF_SPEC_IB bit set. This requires to handle the following cases: 1) Switch from a user space task (potential attacker) which has TIF_SPEC_IB set to a user space task (potential victim) which has TIF_SPEC_IB not set. 2) Switch from a user space task (potential attacker) which has TIF_SPEC_IB not set to a user space task (potential victim) which has TIF_SPEC_IB set. This needs to be optimized for the case where the IBPB can be avoided when only kernel threads ran in between user space tasks which belong to the same process. The current check whether two tasks belong to the same context is using the tasks context id. While correct, it's simpler to use the mm pointer because it allows to mangle the TIF_SPEC_IB bit into it. The context id based mechanism requires extra storage, which creates worse code. When a task is scheduled out its TIF_SPEC_IB bit is mangled as bit 0 into the per CPU storage which is used to track the last user space mm which was running on a CPU. This bit can be used together with the TIF_SPEC_IB bit of the incoming task to make the decision whether IBPB needs to be issued or not to cover the two cases above. As conditional IBPB is going to be the default, remove the dubious ptrace check for the IBPB always case and simply issue IBPB always when the process changes. Move the storage to a different place in the struct as the original one created a hole. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.466447057@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/nospec-branch.h | 2 + arch/x86/include/asm/tlbflush.h | 8 +- arch/x86/kernel/cpu/bugs.c | 29 +++++-- arch/x86/mm/tlb.c | 114 ++++++++++++++++++++------- 4 files changed, 118 insertions(+), 35 deletions(-) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 6057086fde1c..2de273c47521 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -312,6 +312,8 @@ do { \ } while (0) DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); +DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); +DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 2501be609b82..e31040333f0c 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -185,10 +185,14 @@ struct tlb_state { #define LOADED_MM_SWITCHING ((struct mm_struct *)1) + /* Last user mm for optimizing IBPB */ + union { + struct mm_struct *last_user_mm; + unsigned long last_user_mm_ibpb; + }; + u16 loaded_mm_asid; u16 next_asid; - /* last user mm's ctx id */ - u64 last_ctx_id; /* * We can be in one of several states: diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 5bba757fead1..f4bcdae79907 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -55,6 +55,10 @@ u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; /* Control conditional STIPB in switch_to() */ DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); +/* Control conditional IBPB in switch_mm() */ +DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); +/* Control unconditional IBPB in switch_mm() */ +DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); void __init check_bugs(void) { @@ -330,7 +334,17 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) /* Initialize Indirect Branch Prediction Barrier */ if (boot_cpu_has(X86_FEATURE_IBPB)) { setup_force_cpu_cap(X86_FEATURE_USE_IBPB); - pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); + + switch (mode) { + case SPECTRE_V2_USER_STRICT: + static_branch_enable(&switch_mm_always_ibpb); + break; + default: + break; + } + + pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", + mode == SPECTRE_V2_USER_STRICT ? "always-on" : "conditional"); } /* If enhanced IBRS is enabled no STIPB required */ @@ -952,10 +966,15 @@ static char *stibp_state(void) static char *ibpb_state(void) { - if (boot_cpu_has(X86_FEATURE_USE_IBPB)) - return ", IBPB"; - else - return ""; + if (boot_cpu_has(X86_FEATURE_IBPB)) { + switch (spectre_v2_user) { + case SPECTRE_V2_USER_NONE: + return ", IBPB: disabled"; + case SPECTRE_V2_USER_STRICT: + return ", IBPB: always-on"; + } + } + return ""; } static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 9e943de9d628..5400a24e1a8c 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include @@ -30,6 +29,12 @@ * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi */ +/* + * Use bit 0 to mangle the TIF_SPEC_IB state into the mm pointer which is + * stored in cpu_tlb_state.last_user_mm_ibpb. + */ +#define LAST_USER_MM_IBPB 0x1UL + /* * We get here when we do something requiring a TLB invalidation * but could not go invalidate all of the contexts. We do the @@ -181,17 +186,87 @@ static void sync_current_stack_to_mm(struct mm_struct *mm) } } -static bool ibpb_needed(struct task_struct *tsk, u64 last_ctx_id) +static inline unsigned long mm_mangle_tif_spec_ib(struct task_struct *next) +{ + unsigned long next_tif = task_thread_info(next)->flags; + unsigned long ibpb = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_IBPB; + + return (unsigned long)next->mm | ibpb; +} + +static void cond_ibpb(struct task_struct *next) { + if (!next || !next->mm) + return; + /* - * Check if the current (previous) task has access to the memory - * of the @tsk (next) task. If access is denied, make sure to - * issue a IBPB to stop user->user Spectre-v2 attacks. - * - * Note: __ptrace_may_access() returns 0 or -ERRNO. + * Both, the conditional and the always IBPB mode use the mm + * pointer to avoid the IBPB when switching between tasks of the + * same process. Using the mm pointer instead of mm->context.ctx_id + * opens a hypothetical hole vs. mm_struct reuse, which is more or + * less impossible to control by an attacker. Aside of that it + * would only affect the first schedule so the theoretically + * exposed data is not really interesting. */ - return (tsk && tsk->mm && tsk->mm->context.ctx_id != last_ctx_id && - ptrace_may_access_sched(tsk, PTRACE_MODE_SPEC_IBPB)); + if (static_branch_likely(&switch_mm_cond_ibpb)) { + unsigned long prev_mm, next_mm; + + /* + * This is a bit more complex than the always mode because + * it has to handle two cases: + * + * 1) Switch from a user space task (potential attacker) + * which has TIF_SPEC_IB set to a user space task + * (potential victim) which has TIF_SPEC_IB not set. + * + * 2) Switch from a user space task (potential attacker) + * which has TIF_SPEC_IB not set to a user space task + * (potential victim) which has TIF_SPEC_IB set. + * + * This could be done by unconditionally issuing IBPB when + * a task which has TIF_SPEC_IB set is either scheduled in + * or out. Though that results in two flushes when: + * + * - the same user space task is scheduled out and later + * scheduled in again and only a kernel thread ran in + * between. + * + * - a user space task belonging to the same process is + * scheduled in after a kernel thread ran in between + * + * - a user space task belonging to the same process is + * scheduled in immediately. + * + * Optimize this with reasonably small overhead for the + * above cases. Mangle the TIF_SPEC_IB bit into the mm + * pointer of the incoming task which is stored in + * cpu_tlbstate.last_user_mm_ibpb for comparison. + */ + next_mm = mm_mangle_tif_spec_ib(next); + prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_ibpb); + + /* + * Issue IBPB only if the mm's are different and one or + * both have the IBPB bit set. + */ + if (next_mm != prev_mm && + (next_mm | prev_mm) & LAST_USER_MM_IBPB) + indirect_branch_prediction_barrier(); + + this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, next_mm); + } + + if (static_branch_unlikely(&switch_mm_always_ibpb)) { + /* + * Only flush when switching to a user space task with a + * different context than the user space task which ran + * last on this CPU. + */ + if (this_cpu_read(cpu_tlbstate.last_user_mm) != next->mm) { + indirect_branch_prediction_barrier(); + this_cpu_write(cpu_tlbstate.last_user_mm, next->mm); + } + } } void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, @@ -262,22 +337,13 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, } else { u16 new_asid; bool need_flush; - u64 last_ctx_id = this_cpu_read(cpu_tlbstate.last_ctx_id); /* * Avoid user/user BTB poisoning by flushing the branch * predictor when switching between processes. This stops * one process from doing Spectre-v2 attacks on another. - * - * As an optimization, flush indirect branches only when - * switching into a processes that can't be ptrace by the - * current one (as in such case, attacker has much more - * convenient way how to tamper with the next process than - * branch buffer poisoning). */ - if (static_cpu_has(X86_FEATURE_USE_IBPB) && - ibpb_needed(tsk, last_ctx_id)) - indirect_branch_prediction_barrier(); + cond_ibpb(tsk); if (IS_ENABLED(CONFIG_VMAP_STACK)) { /* @@ -327,14 +393,6 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0); } - /* - * Record last user mm's context id, so we can avoid - * flushing branch buffer with IBPB if we switch back - * to the same user. - */ - if (next != &init_mm) - this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id); - /* Make sure we write CR3 before loaded_mm. */ barrier(); @@ -415,7 +473,7 @@ void initialize_tlbstate_and_flush(void) write_cr3(build_cr3(mm->pgd, 0)); /* Reinitialize tlbstate. */ - this_cpu_write(cpu_tlbstate.last_ctx_id, mm->context.ctx_id); + this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, LAST_USER_MM_IBPB); this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); this_cpu_write(cpu_tlbstate.next_asid, 1); this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); -- GitLab From dae4d59096700703266190f8dff92f9edb82b1b5 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:50 +0100 Subject: [PATCH 0262/1286] ptrace: Remove unused ptrace_may_access_sched() and MODE_IBRS commit 46f7ecb1e7359f183f5bbd1e08b90e10e52164f9 upstream The IBPB control code in x86 removed the usage. Remove the functionality which was introduced for this. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.559149393@linutronix.de Signed-off-by: Greg Kroah-Hartman --- include/linux/ptrace.h | 17 ----------------- kernel/ptrace.c | 10 ---------- 2 files changed, 27 deletions(-) diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index b1d43b80abfa..38342e88b3f3 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -64,15 +64,12 @@ extern void exit_ptrace(struct task_struct *tracer, struct list_head *dead); #define PTRACE_MODE_NOAUDIT 0x04 #define PTRACE_MODE_FSCREDS 0x08 #define PTRACE_MODE_REALCREDS 0x10 -#define PTRACE_MODE_SCHED 0x20 -#define PTRACE_MODE_IBPB 0x40 /* shorthands for READ/ATTACH and FSCREDS/REALCREDS combinations */ #define PTRACE_MODE_READ_FSCREDS (PTRACE_MODE_READ | PTRACE_MODE_FSCREDS) #define PTRACE_MODE_READ_REALCREDS (PTRACE_MODE_READ | PTRACE_MODE_REALCREDS) #define PTRACE_MODE_ATTACH_FSCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_FSCREDS) #define PTRACE_MODE_ATTACH_REALCREDS (PTRACE_MODE_ATTACH | PTRACE_MODE_REALCREDS) -#define PTRACE_MODE_SPEC_IBPB (PTRACE_MODE_ATTACH_REALCREDS | PTRACE_MODE_IBPB) /** * ptrace_may_access - check whether the caller is permitted to access @@ -90,20 +87,6 @@ extern void exit_ptrace(struct task_struct *tracer, struct list_head *dead); */ extern bool ptrace_may_access(struct task_struct *task, unsigned int mode); -/** - * ptrace_may_access - check whether the caller is permitted to access - * a target task. - * @task: target task - * @mode: selects type of access and caller credentials - * - * Returns true on success, false on denial. - * - * Similar to ptrace_may_access(). Only to be called from context switch - * code. Does not call into audit and the regular LSM hooks due to locking - * constraints. - */ -extern bool ptrace_may_access_sched(struct task_struct *task, unsigned int mode); - static inline int ptrace_reparented(struct task_struct *child) { return !same_thread_group(child->real_parent, child->parent); diff --git a/kernel/ptrace.c b/kernel/ptrace.c index d7be2159ac09..84b1367935e4 100644 --- a/kernel/ptrace.c +++ b/kernel/ptrace.c @@ -261,9 +261,6 @@ static int ptrace_check_attach(struct task_struct *child, bool ignore_state) static int ptrace_has_cap(struct user_namespace *ns, unsigned int mode) { - if (mode & PTRACE_MODE_SCHED) - return false; - if (mode & PTRACE_MODE_NOAUDIT) return has_ns_capability_noaudit(current, ns, CAP_SYS_PTRACE); else @@ -331,16 +328,9 @@ static int __ptrace_may_access(struct task_struct *task, unsigned int mode) !ptrace_has_cap(mm->user_ns, mode))) return -EPERM; - if (mode & PTRACE_MODE_SCHED) - return 0; return security_ptrace_access_check(task, mode); } -bool ptrace_may_access_sched(struct task_struct *task, unsigned int mode) -{ - return __ptrace_may_access(task, mode | PTRACE_MODE_SCHED); -} - bool ptrace_may_access(struct task_struct *task, unsigned int mode) { int err; -- GitLab From dcb4ac34f9373b1f4365b24ddfac2bcdefd59f6e Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:51 +0100 Subject: [PATCH 0263/1286] x86/speculation: Split out TIF update commit e6da8bb6f9abb2628381904b24163c770e630bac upstream The update of the TIF_SSBD flag and the conditional speculation control MSR update is done in the ssb_prctl_set() function directly. The upcoming prctl support for controlling indirect branch speculation via STIBP needs the same mechanism. Split the code out and make it reusable. Reword the comment about updates for other tasks. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.652305076@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index f4bcdae79907..68da43cacead 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -699,10 +699,29 @@ static void ssb_select_mitigation(void) #undef pr_fmt #define pr_fmt(fmt) "Speculation prctl: " fmt -static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) +static void task_update_spec_tif(struct task_struct *tsk, int tifbit, bool on) { bool update; + if (on) + update = !test_and_set_tsk_thread_flag(tsk, tifbit); + else + update = test_and_clear_tsk_thread_flag(tsk, tifbit); + + /* + * Immediately update the speculation control MSRs for the current + * task, but for a non-current task delay setting the CPU + * mitigation until it is scheduled next. + * + * This can only happen for SECCOMP mitigation. For PRCTL it's + * always the current task. + */ + if (tsk == current && update) + speculation_ctrl_update_current(); +} + +static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) +{ if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && ssb_mode != SPEC_STORE_BYPASS_SECCOMP) return -ENXIO; @@ -713,28 +732,20 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) if (task_spec_ssb_force_disable(task)) return -EPERM; task_clear_spec_ssb_disable(task); - update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); + task_update_spec_tif(task, TIF_SSBD, false); break; case PR_SPEC_DISABLE: task_set_spec_ssb_disable(task); - update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); + task_update_spec_tif(task, TIF_SSBD, true); break; case PR_SPEC_FORCE_DISABLE: task_set_spec_ssb_disable(task); task_set_spec_ssb_force_disable(task); - update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); + task_update_spec_tif(task, TIF_SSBD, true); break; default: return -ERANGE; } - - /* - * If being set on non-current task, delay setting the CPU - * mitigation until it is next scheduled. - */ - if (task == current && update) - speculation_ctrl_update_current(); - return 0; } -- GitLab From e3f822b628a0d715a46d233e81881f6c2885247b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 28 Nov 2018 10:56:57 +0100 Subject: [PATCH 0264/1286] x86/speculation: Prevent stale SPEC_CTRL msr content commit 6d991ba509ebcfcc908e009d1db51972a4f7a064 upstream The seccomp speculation control operates on all tasks of a process, but only the current task of a process can update the MSR immediately. For the other threads the update is deferred to the next context switch. This creates the following situation with Process A and B: Process A task 2 and Process B task 1 are pinned on CPU1. Process A task 2 does not have the speculation control TIF bit set. Process B task 1 has the speculation control TIF bit set. CPU0 CPU1 MSR bit is set ProcB.T1 schedules out ProcA.T2 schedules in MSR bit is cleared ProcA.T1 seccomp_update() set TIF bit on ProcA.T2 ProcB.T1 schedules in MSR is not updated <-- FAIL This happens because the context switch code tries to avoid the MSR update if the speculation control TIF bits of the incoming and the outgoing task are the same. In the worst case ProcB.T1 and ProcA.T2 are the only tasks scheduling back and forth on CPU1, which keeps the MSR stale forever. In theory this could be remedied by IPIs, but chasing the remote task which could be migrated is complex and full of races. The straight forward solution is to avoid the asychronous update of the TIF bit and defer it to the next context switch. The speculation control state is stored in task_struct::atomic_flags by the prctl and seccomp updates already. Add a new TIF_SPEC_FORCE_UPDATE bit and set this after updating the atomic_flags. Check the bit on context switch and force a synchronous update of the speculation control if set. Use the same mechanism for updating the current task. Reported-by: Tim Chen Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1811272247140.1875@nanos.tec.linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/spec-ctrl.h | 6 +----- arch/x86/include/asm/thread_info.h | 4 +++- arch/x86/kernel/cpu/bugs.c | 18 +++++++----------- arch/x86/kernel/process.c | 30 +++++++++++++++++++++++++++++- 4 files changed, 40 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index 27b0bce3933b..5393babc0598 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -83,10 +83,6 @@ static inline void speculative_store_bypass_ht_init(void) { } #endif extern void speculation_ctrl_update(unsigned long tif); - -static inline void speculation_ctrl_update_current(void) -{ - speculation_ctrl_update(current_thread_info()->flags); -} +extern void speculation_ctrl_update_current(void); #endif diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 7b30338ca55b..bf9175d87844 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -86,6 +86,7 @@ struct thread_info { #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ #define TIF_SPEC_IB 9 /* Indirect branch speculation mitigation */ +#define TIF_SPEC_FORCE_UPDATE 10 /* Force speculation MSR update in context switch */ #define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */ #define TIF_UPROBE 12 /* breakpointed or singlestepping */ #define TIF_PATCH_PENDING 13 /* pending live patching update */ @@ -114,6 +115,7 @@ struct thread_info { #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) #define _TIF_SPEC_IB (1 << TIF_SPEC_IB) +#define _TIF_SPEC_FORCE_UPDATE (1 << TIF_SPEC_FORCE_UPDATE) #define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY) #define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING) @@ -151,7 +153,7 @@ struct thread_info { /* flags to check in __switch_to() */ #define _TIF_WORK_CTXSW_BASE \ (_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP| \ - _TIF_SSBD) + _TIF_SSBD | _TIF_SPEC_FORCE_UPDATE) /* * Avoid calls to __switch_to_xtra() on UP as STIBP is not evaluated. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 68da43cacead..9f9b03094628 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -699,14 +699,10 @@ static void ssb_select_mitigation(void) #undef pr_fmt #define pr_fmt(fmt) "Speculation prctl: " fmt -static void task_update_spec_tif(struct task_struct *tsk, int tifbit, bool on) +static void task_update_spec_tif(struct task_struct *tsk) { - bool update; - - if (on) - update = !test_and_set_tsk_thread_flag(tsk, tifbit); - else - update = test_and_clear_tsk_thread_flag(tsk, tifbit); + /* Force the update of the real TIF bits */ + set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); /* * Immediately update the speculation control MSRs for the current @@ -716,7 +712,7 @@ static void task_update_spec_tif(struct task_struct *tsk, int tifbit, bool on) * This can only happen for SECCOMP mitigation. For PRCTL it's * always the current task. */ - if (tsk == current && update) + if (tsk == current) speculation_ctrl_update_current(); } @@ -732,16 +728,16 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) if (task_spec_ssb_force_disable(task)) return -EPERM; task_clear_spec_ssb_disable(task); - task_update_spec_tif(task, TIF_SSBD, false); + task_update_spec_tif(task); break; case PR_SPEC_DISABLE: task_set_spec_ssb_disable(task); - task_update_spec_tif(task, TIF_SSBD, true); + task_update_spec_tif(task); break; case PR_SPEC_FORCE_DISABLE: task_set_spec_ssb_disable(task); task_set_spec_ssb_force_disable(task); - task_update_spec_tif(task, TIF_SSBD, true); + task_update_spec_tif(task); break; default: return -ERANGE; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index dd1157b4bd15..0b7be5f31fb4 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -446,6 +446,18 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, wrmsrl(MSR_IA32_SPEC_CTRL, msr); } +static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) +{ + if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) { + if (task_spec_ssb_disable(tsk)) + set_tsk_thread_flag(tsk, TIF_SSBD); + else + clear_tsk_thread_flag(tsk, TIF_SSBD); + } + /* Return the updated threadinfo flags*/ + return task_thread_info(tsk)->flags; +} + void speculation_ctrl_update(unsigned long tif) { /* Forced update. Make sure all relevant TIF flags are different */ @@ -454,6 +466,14 @@ void speculation_ctrl_update(unsigned long tif) preempt_enable(); } +/* Called from seccomp/prctl update */ +void speculation_ctrl_update_current(void) +{ + preempt_disable(); + speculation_ctrl_update(speculation_ctrl_update_tif(current)); + preempt_enable(); +} + void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) { struct thread_struct *prev, *next; @@ -485,7 +505,15 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) if ((tifp ^ tifn) & _TIF_NOCPUID) set_cpuid_faulting(!!(tifn & _TIF_NOCPUID)); - __speculation_ctrl_update(tifp, tifn); + if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) { + __speculation_ctrl_update(tifp, tifn); + } else { + speculation_ctrl_update_tif(prev_p); + tifn = speculation_ctrl_update_tif(next_p); + + /* Enforce MSR update to ensure consistent state */ + __speculation_ctrl_update(~tifn, tifn); + } } /* -- GitLab From 99f1cb80daab80107c4b7f7f9a9ddf041a8b2137 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:52 +0100 Subject: [PATCH 0265/1286] x86/speculation: Prepare arch_smt_update() for PRCTL mode commit 6893a959d7fdebbab5f5aa112c277d5a44435ba1 upstream The upcoming fine grained per task STIBP control needs to be updated on CPU hotplug as well. Split out the code which controls the strict mode so the prctl control code can be added later. Mark the SMP function call argument __unused while at it. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.759457117@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 46 +++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 9f9b03094628..2e3da643d3fd 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -527,40 +527,44 @@ static void __init spectre_v2_select_mitigation(void) arch_smt_update(); } -static bool stibp_needed(void) +static void update_stibp_msr(void * __unused) { - /* Enhanced IBRS makes using STIBP unnecessary. */ - if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) - return false; - - /* Check for strict user mitigation mode */ - return spectre_v2_user == SPECTRE_V2_USER_STRICT; + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); } -static void update_stibp_msr(void *info) +/* Update x86_spec_ctrl_base in case SMT state changed. */ +static void update_stibp_strict(void) { - wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; + + if (sched_smt_active()) + mask |= SPEC_CTRL_STIBP; + + if (mask == x86_spec_ctrl_base) + return; + + pr_info("Update user space SMT mitigation: STIBP %s\n", + mask & SPEC_CTRL_STIBP ? "always-on" : "off"); + x86_spec_ctrl_base = mask; + on_each_cpu(update_stibp_msr, NULL, 1); } void arch_smt_update(void) { - u64 mask; - - if (!stibp_needed()) + /* Enhanced IBRS implies STIBP. No update required. */ + if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) return; mutex_lock(&spec_ctrl_mutex); - mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; - if (sched_smt_active()) - mask |= SPEC_CTRL_STIBP; - - if (mask != x86_spec_ctrl_base) { - pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", - mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling"); - x86_spec_ctrl_base = mask; - on_each_cpu(update_stibp_msr, NULL, 1); + switch (spectre_v2_user) { + case SPECTRE_V2_USER_NONE: + break; + case SPECTRE_V2_USER_STRICT: + update_stibp_strict(); + break; } + mutex_unlock(&spec_ctrl_mutex); } -- GitLab From 6a847a6057721011b9534e709e5286c51ea31b9f Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:53 +0100 Subject: [PATCH 0266/1286] x86/speculation: Add prctl() control for indirect branch speculation commit 9137bb27e60e554dab694eafa4cca241fa3a694f upstream Add the PR_SPEC_INDIRECT_BRANCH option for the PR_GET_SPECULATION_CTRL and PR_SET_SPECULATION_CTRL prctls to allow fine grained per task control of indirect branch speculation via STIBP and IBPB. Invocations: Check indirect branch speculation status with - prctl(PR_GET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, 0, 0, 0); Enable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_ENABLE, 0, 0); Disable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_DISABLE, 0, 0); Force disable indirect branch speculation with - prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_FORCE_DISABLE, 0, 0); See Documentation/userspace-api/spec_ctrl.rst. Signed-off-by: Tim Chen Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.866780996@linutronix.de Signed-off-by: Greg Kroah-Hartman --- Documentation/userspace-api/spec_ctrl.rst | 9 +++ arch/x86/include/asm/nospec-branch.h | 1 + arch/x86/kernel/cpu/bugs.c | 67 +++++++++++++++++++++++ arch/x86/kernel/process.c | 5 ++ include/linux/sched.h | 9 +++ include/uapi/linux/prctl.h | 1 + 6 files changed, 92 insertions(+) diff --git a/Documentation/userspace-api/spec_ctrl.rst b/Documentation/userspace-api/spec_ctrl.rst index 32f3d55c54b7..c4dbe6f7cdae 100644 --- a/Documentation/userspace-api/spec_ctrl.rst +++ b/Documentation/userspace-api/spec_ctrl.rst @@ -92,3 +92,12 @@ Speculation misfeature controls * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_ENABLE, 0, 0); * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_DISABLE, 0, 0); * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_FORCE_DISABLE, 0, 0); + +- PR_SPEC_INDIR_BRANCH: Indirect Branch Speculation in User Processes + (Mitigate Spectre V2 style attacks against user processes) + + Invocations: + * prctl(PR_GET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, 0, 0, 0); + * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_ENABLE, 0, 0); + * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_DISABLE, 0, 0); + * prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_INDIRECT_BRANCH, PR_SPEC_FORCE_DISABLE, 0, 0); diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 2de273c47521..35ef92c5cc66 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -232,6 +232,7 @@ enum spectre_v2_mitigation { enum spectre_v2_user_mitigation { SPECTRE_V2_USER_NONE, SPECTRE_V2_USER_STRICT, + SPECTRE_V2_USER_PRCTL, }; /* The Speculative Store Bypass disable variants */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 2e3da643d3fd..bcd39b928fea 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -563,6 +563,8 @@ void arch_smt_update(void) case SPECTRE_V2_USER_STRICT: update_stibp_strict(); break; + case SPECTRE_V2_USER_PRCTL: + break; } mutex_unlock(&spec_ctrl_mutex); @@ -749,12 +751,50 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) return 0; } +static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) +{ + switch (ctrl) { + case PR_SPEC_ENABLE: + if (spectre_v2_user == SPECTRE_V2_USER_NONE) + return 0; + /* + * Indirect branch speculation is always disabled in strict + * mode. + */ + if (spectre_v2_user == SPECTRE_V2_USER_STRICT) + return -EPERM; + task_clear_spec_ib_disable(task); + task_update_spec_tif(task); + break; + case PR_SPEC_DISABLE: + case PR_SPEC_FORCE_DISABLE: + /* + * Indirect branch speculation is always allowed when + * mitigation is force disabled. + */ + if (spectre_v2_user == SPECTRE_V2_USER_NONE) + return -EPERM; + if (spectre_v2_user == SPECTRE_V2_USER_STRICT) + return 0; + task_set_spec_ib_disable(task); + if (ctrl == PR_SPEC_FORCE_DISABLE) + task_set_spec_ib_force_disable(task); + task_update_spec_tif(task); + break; + default: + return -ERANGE; + } + return 0; +} + int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, unsigned long ctrl) { switch (which) { case PR_SPEC_STORE_BYPASS: return ssb_prctl_set(task, ctrl); + case PR_SPEC_INDIRECT_BRANCH: + return ib_prctl_set(task, ctrl); default: return -ENODEV; } @@ -787,11 +827,34 @@ static int ssb_prctl_get(struct task_struct *task) } } +static int ib_prctl_get(struct task_struct *task) +{ + if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) + return PR_SPEC_NOT_AFFECTED; + + switch (spectre_v2_user) { + case SPECTRE_V2_USER_NONE: + return PR_SPEC_ENABLE; + case SPECTRE_V2_USER_PRCTL: + if (task_spec_ib_force_disable(task)) + return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; + if (task_spec_ib_disable(task)) + return PR_SPEC_PRCTL | PR_SPEC_DISABLE; + return PR_SPEC_PRCTL | PR_SPEC_ENABLE; + case SPECTRE_V2_USER_STRICT: + return PR_SPEC_DISABLE; + default: + return PR_SPEC_NOT_AFFECTED; + } +} + int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) { switch (which) { case PR_SPEC_STORE_BYPASS: return ssb_prctl_get(task); + case PR_SPEC_INDIRECT_BRANCH: + return ib_prctl_get(task); default: return -ENODEV; } @@ -971,6 +1034,8 @@ static char *stibp_state(void) return ", STIBP: disabled"; case SPECTRE_V2_USER_STRICT: return ", STIBP: forced"; + case SPECTRE_V2_USER_PRCTL: + return ""; } return ""; } @@ -983,6 +1048,8 @@ static char *ibpb_state(void) return ", IBPB: disabled"; case SPECTRE_V2_USER_STRICT: return ", IBPB: always-on"; + case SPECTRE_V2_USER_PRCTL: + return ""; } } return ""; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 0b7be5f31fb4..a98d1cdd6299 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -453,6 +453,11 @@ static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk) set_tsk_thread_flag(tsk, TIF_SSBD); else clear_tsk_thread_flag(tsk, TIF_SSBD); + + if (task_spec_ib_disable(tsk)) + set_tsk_thread_flag(tsk, TIF_SPEC_IB); + else + clear_tsk_thread_flag(tsk, TIF_SPEC_IB); } /* Return the updated threadinfo flags*/ return task_thread_info(tsk)->flags; diff --git a/include/linux/sched.h b/include/linux/sched.h index e04919aa8201..866439c361a9 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1405,6 +1405,8 @@ static inline bool is_percpu_thread(void) #define PFA_SPREAD_SLAB 2 /* Spread some slab caches over cpuset */ #define PFA_SPEC_SSB_DISABLE 3 /* Speculative Store Bypass disabled */ #define PFA_SPEC_SSB_FORCE_DISABLE 4 /* Speculative Store Bypass force disabled*/ +#define PFA_SPEC_IB_DISABLE 5 /* Indirect branch speculation restricted */ +#define PFA_SPEC_IB_FORCE_DISABLE 6 /* Indirect branch speculation permanently restricted */ #define TASK_PFA_TEST(name, func) \ static inline bool task_##func(struct task_struct *p) \ @@ -1436,6 +1438,13 @@ TASK_PFA_CLEAR(SPEC_SSB_DISABLE, spec_ssb_disable) TASK_PFA_TEST(SPEC_SSB_FORCE_DISABLE, spec_ssb_force_disable) TASK_PFA_SET(SPEC_SSB_FORCE_DISABLE, spec_ssb_force_disable) +TASK_PFA_TEST(SPEC_IB_DISABLE, spec_ib_disable) +TASK_PFA_SET(SPEC_IB_DISABLE, spec_ib_disable) +TASK_PFA_CLEAR(SPEC_IB_DISABLE, spec_ib_disable) + +TASK_PFA_TEST(SPEC_IB_FORCE_DISABLE, spec_ib_force_disable) +TASK_PFA_SET(SPEC_IB_FORCE_DISABLE, spec_ib_force_disable) + static inline void current_restore_flags(unsigned long orig_flags, unsigned long flags) { diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 3027f943f4b3..214102fab940 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -203,6 +203,7 @@ struct prctl_mm_map { #define PR_SET_SPECULATION_CTRL 53 /* Speculation control variants */ # define PR_SPEC_STORE_BYPASS 0 +# define PR_SPEC_INDIRECT_BRANCH 1 /* Return and control values for PR_SET/GET_SPECULATION_CTRL */ # define PR_SPEC_NOT_AFFECTED 0 # define PR_SPEC_PRCTL (1UL << 0) -- GitLab From 605b2828ff55471d8b2ab0b405991895a2216e06 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:54 +0100 Subject: [PATCH 0267/1286] x86/speculation: Enable prctl mode for spectre_v2_user commit 7cc765a67d8e04ef7d772425ca5a2a1e2b894c15 upstream Now that all prerequisites are in place: - Add the prctl command line option - Default the 'auto' mode to 'prctl' - When SMT state changes, update the static key which controls the conditional STIBP evaluation on context switch. - At init update the static key which controls the conditional IBPB evaluation on context switch. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185005.958421388@linutronix.de Signed-off-by: Greg Kroah-Hartman --- .../admin-guide/kernel-parameters.txt | 7 +++- arch/x86/kernel/cpu/bugs.c | 41 +++++++++++++++---- 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index f0c19f61db80..dd9783e43443 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4036,9 +4036,14 @@ off - Unconditionally disable mitigations. Is enforced by spectre_v2=off + prctl - Indirect branch speculation is enabled, + but mitigation can be enabled via prctl + per thread. The mitigation control state + is inherited on fork. + auto - Kernel selects the mitigation depending on the available CPU features and vulnerability. - Default is off. + Default is prctl. Not specifying this option is equivalent to spectre_v2_user=auto. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index bcd39b928fea..d87a877b1b38 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -254,11 +254,13 @@ enum spectre_v2_user_cmd { SPECTRE_V2_USER_CMD_NONE, SPECTRE_V2_USER_CMD_AUTO, SPECTRE_V2_USER_CMD_FORCE, + SPECTRE_V2_USER_CMD_PRCTL, }; static const char * const spectre_v2_user_strings[] = { [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", + [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", }; static const struct { @@ -269,6 +271,7 @@ static const struct { { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, { "off", SPECTRE_V2_USER_CMD_NONE, false }, { "on", SPECTRE_V2_USER_CMD_FORCE, true }, + { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, }; static void __init spec_v2_user_print_cond(const char *reason, bool secure) @@ -323,12 +326,15 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) smt_possible = false; switch (spectre_v2_parse_user_cmdline(v2_cmd)) { - case SPECTRE_V2_USER_CMD_AUTO: case SPECTRE_V2_USER_CMD_NONE: goto set_mode; case SPECTRE_V2_USER_CMD_FORCE: mode = SPECTRE_V2_USER_STRICT; break; + case SPECTRE_V2_USER_CMD_AUTO: + case SPECTRE_V2_USER_CMD_PRCTL: + mode = SPECTRE_V2_USER_PRCTL; + break; } /* Initialize Indirect Branch Prediction Barrier */ @@ -339,6 +345,9 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) case SPECTRE_V2_USER_STRICT: static_branch_enable(&switch_mm_always_ibpb); break; + case SPECTRE_V2_USER_PRCTL: + static_branch_enable(&switch_mm_cond_ibpb); + break; default: break; } @@ -351,6 +360,12 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) return; + /* + * If SMT is not possible or STIBP is not available clear the STIPB + * mode. + */ + if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) + mode = SPECTRE_V2_USER_NONE; set_mode: spectre_v2_user = mode; /* Only print the STIBP mode when SMT possible */ @@ -549,6 +564,15 @@ static void update_stibp_strict(void) on_each_cpu(update_stibp_msr, NULL, 1); } +/* Update the static key controlling the evaluation of TIF_SPEC_IB */ +static void update_indir_branch_cond(void) +{ + if (sched_smt_active()) + static_branch_enable(&switch_to_cond_stibp); + else + static_branch_disable(&switch_to_cond_stibp); +} + void arch_smt_update(void) { /* Enhanced IBRS implies STIBP. No update required. */ @@ -564,6 +588,7 @@ void arch_smt_update(void) update_stibp_strict(); break; case SPECTRE_V2_USER_PRCTL: + update_indir_branch_cond(); break; } @@ -1035,7 +1060,8 @@ static char *stibp_state(void) case SPECTRE_V2_USER_STRICT: return ", STIBP: forced"; case SPECTRE_V2_USER_PRCTL: - return ""; + if (static_key_enabled(&switch_to_cond_stibp)) + return ", STIBP: conditional"; } return ""; } @@ -1043,14 +1069,11 @@ static char *stibp_state(void) static char *ibpb_state(void) { if (boot_cpu_has(X86_FEATURE_IBPB)) { - switch (spectre_v2_user) { - case SPECTRE_V2_USER_NONE: - return ", IBPB: disabled"; - case SPECTRE_V2_USER_STRICT: + if (static_key_enabled(&switch_mm_always_ibpb)) return ", IBPB: always-on"; - case SPECTRE_V2_USER_PRCTL: - return ""; - } + if (static_key_enabled(&switch_mm_cond_ibpb)) + return ", IBPB: conditional"; + return ", IBPB: disabled"; } return ""; } -- GitLab From ca97dd0009e688a67f6e22ce3fce0b4523741243 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:55 +0100 Subject: [PATCH 0268/1286] x86/speculation: Add seccomp Spectre v2 user space protection mode commit 6b3e64c237c072797a9ec918654a60e3a46488e2 upstream If 'prctl' mode of user space protection from spectre v2 is selected on the kernel command-line, STIBP and IBPB are applied on tasks which restrict their indirect branch speculation via prctl. SECCOMP enables the SSBD mitigation for sandboxed tasks already, so it makes sense to prevent spectre v2 user space to user space attacks as well. The Intel mitigation guide documents how STIPB works: Setting bit 1 (STIBP) of the IA32_SPEC_CTRL MSR on a logical processor prevents the predicted targets of indirect branches on any logical processor of that core from being controlled by software that executes (or executed previously) on another logical processor of the same core. Ergo setting STIBP protects the task itself from being attacked from a task running on a different hyper-thread and protects the tasks running on different hyper-threads from being attacked. While the document suggests that the branch predictors are shielded between the logical processors, the observed performance regressions suggest that STIBP simply disables the branch predictor more or less completely. Of course the document wording is vague, but the fact that there is also no requirement for issuing IBPB when STIBP is used points clearly in that direction. The kernel still issues IBPB even when STIBP is used until Intel clarifies the whole mechanism. IBPB is issued when the task switches out, so malicious sandbox code cannot mistrain the branch predictor for the next user space task on the same logical processor. Signed-off-by: Jiri Kosina Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185006.051663132@linutronix.de Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/kernel-parameters.txt | 9 ++++++++- arch/x86/include/asm/nospec-branch.h | 1 + arch/x86/kernel/cpu/bugs.c | 17 ++++++++++++++++- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index dd9783e43443..10a28f7b1ec6 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4041,9 +4041,16 @@ per thread. The mitigation control state is inherited on fork. + seccomp + - Same as "prctl" above, but all seccomp + threads will enable the mitigation unless + they explicitly opt out. + auto - Kernel selects the mitigation depending on the available CPU features and vulnerability. - Default is prctl. + + Default mitigation: + If CONFIG_SECCOMP=y then "seccomp", otherwise "prctl" Not specifying this option is equivalent to spectre_v2_user=auto. diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 35ef92c5cc66..a633767419f2 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -233,6 +233,7 @@ enum spectre_v2_user_mitigation { SPECTRE_V2_USER_NONE, SPECTRE_V2_USER_STRICT, SPECTRE_V2_USER_PRCTL, + SPECTRE_V2_USER_SECCOMP, }; /* The Speculative Store Bypass disable variants */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index d87a877b1b38..5a03082ee189 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -255,12 +255,14 @@ enum spectre_v2_user_cmd { SPECTRE_V2_USER_CMD_AUTO, SPECTRE_V2_USER_CMD_FORCE, SPECTRE_V2_USER_CMD_PRCTL, + SPECTRE_V2_USER_CMD_SECCOMP, }; static const char * const spectre_v2_user_strings[] = { [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", + [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", }; static const struct { @@ -272,6 +274,7 @@ static const struct { { "off", SPECTRE_V2_USER_CMD_NONE, false }, { "on", SPECTRE_V2_USER_CMD_FORCE, true }, { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, + { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, }; static void __init spec_v2_user_print_cond(const char *reason, bool secure) @@ -331,10 +334,16 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) case SPECTRE_V2_USER_CMD_FORCE: mode = SPECTRE_V2_USER_STRICT; break; - case SPECTRE_V2_USER_CMD_AUTO: case SPECTRE_V2_USER_CMD_PRCTL: mode = SPECTRE_V2_USER_PRCTL; break; + case SPECTRE_V2_USER_CMD_AUTO: + case SPECTRE_V2_USER_CMD_SECCOMP: + if (IS_ENABLED(CONFIG_SECCOMP)) + mode = SPECTRE_V2_USER_SECCOMP; + else + mode = SPECTRE_V2_USER_PRCTL; + break; } /* Initialize Indirect Branch Prediction Barrier */ @@ -346,6 +355,7 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) static_branch_enable(&switch_mm_always_ibpb); break; case SPECTRE_V2_USER_PRCTL: + case SPECTRE_V2_USER_SECCOMP: static_branch_enable(&switch_mm_cond_ibpb); break; default: @@ -588,6 +598,7 @@ void arch_smt_update(void) update_stibp_strict(); break; case SPECTRE_V2_USER_PRCTL: + case SPECTRE_V2_USER_SECCOMP: update_indir_branch_cond(); break; } @@ -830,6 +841,8 @@ void arch_seccomp_spec_mitigate(struct task_struct *task) { if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); + if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) + ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); } #endif @@ -861,6 +874,7 @@ static int ib_prctl_get(struct task_struct *task) case SPECTRE_V2_USER_NONE: return PR_SPEC_ENABLE; case SPECTRE_V2_USER_PRCTL: + case SPECTRE_V2_USER_SECCOMP: if (task_spec_ib_force_disable(task)) return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; if (task_spec_ib_disable(task)) @@ -1060,6 +1074,7 @@ static char *stibp_state(void) case SPECTRE_V2_USER_STRICT: return ", STIBP: forced"; case SPECTRE_V2_USER_PRCTL: + case SPECTRE_V2_USER_SECCOMP: if (static_key_enabled(&switch_to_cond_stibp)) return ", STIBP: conditional"; } -- GitLab From 78085d7e3816606d6aa211245ab2cde3463d7795 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sun, 25 Nov 2018 19:33:56 +0100 Subject: [PATCH 0269/1286] x86/speculation: Provide IBPB always command line options commit 55a974021ec952ee460dc31ca08722158639de72 upstream Provide the possibility to enable IBPB always in combination with 'prctl' and 'seccomp'. Add the extra command line options and rework the IBPB selection to evaluate the command instead of the mode selected by the STIPB switch case. Signed-off-by: Thomas Gleixner Reviewed-by: Ingo Molnar Cc: Peter Zijlstra Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Jiri Kosina Cc: Tom Lendacky Cc: Josh Poimboeuf Cc: Andrea Arcangeli Cc: David Woodhouse Cc: Tim Chen Cc: Andi Kleen Cc: Dave Hansen Cc: Casey Schaufler Cc: Asit Mallick Cc: Arjan van de Ven Cc: Jon Masters Cc: Waiman Long Cc: Greg KH Cc: Dave Stewart Cc: Kees Cook Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20181125185006.144047038@linutronix.de Signed-off-by: Greg Kroah-Hartman --- .../admin-guide/kernel-parameters.txt | 12 +++++++ arch/x86/kernel/cpu/bugs.c | 34 +++++++++++++------ 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 10a28f7b1ec6..5f3d58142600 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4041,11 +4041,23 @@ per thread. The mitigation control state is inherited on fork. + prctl,ibpb + - Like "prctl" above, but only STIBP is + controlled per thread. IBPB is issued + always when switching between different user + space processes. + seccomp - Same as "prctl" above, but all seccomp threads will enable the mitigation unless they explicitly opt out. + seccomp,ibpb + - Like "seccomp" above, but only STIBP is + controlled per thread. IBPB is issued + always when switching between different + user space processes. + auto - Kernel selects the mitigation depending on the available CPU features and vulnerability. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 5a03082ee189..f7a6d6203e13 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -255,7 +255,9 @@ enum spectre_v2_user_cmd { SPECTRE_V2_USER_CMD_AUTO, SPECTRE_V2_USER_CMD_FORCE, SPECTRE_V2_USER_CMD_PRCTL, + SPECTRE_V2_USER_CMD_PRCTL_IBPB, SPECTRE_V2_USER_CMD_SECCOMP, + SPECTRE_V2_USER_CMD_SECCOMP_IBPB, }; static const char * const spectre_v2_user_strings[] = { @@ -270,11 +272,13 @@ static const struct { enum spectre_v2_user_cmd cmd; bool secure; } v2_user_options[] __initdata = { - { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, - { "off", SPECTRE_V2_USER_CMD_NONE, false }, - { "on", SPECTRE_V2_USER_CMD_FORCE, true }, - { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, - { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, + { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, + { "off", SPECTRE_V2_USER_CMD_NONE, false }, + { "on", SPECTRE_V2_USER_CMD_FORCE, true }, + { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, + { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, + { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, + { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, }; static void __init spec_v2_user_print_cond(const char *reason, bool secure) @@ -320,6 +324,7 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) { enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; bool smt_possible = IS_ENABLED(CONFIG_SMP); + enum spectre_v2_user_cmd cmd; if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) return; @@ -328,17 +333,20 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) cpu_smt_control == CPU_SMT_NOT_SUPPORTED) smt_possible = false; - switch (spectre_v2_parse_user_cmdline(v2_cmd)) { + cmd = spectre_v2_parse_user_cmdline(v2_cmd); + switch (cmd) { case SPECTRE_V2_USER_CMD_NONE: goto set_mode; case SPECTRE_V2_USER_CMD_FORCE: mode = SPECTRE_V2_USER_STRICT; break; case SPECTRE_V2_USER_CMD_PRCTL: + case SPECTRE_V2_USER_CMD_PRCTL_IBPB: mode = SPECTRE_V2_USER_PRCTL; break; case SPECTRE_V2_USER_CMD_AUTO: case SPECTRE_V2_USER_CMD_SECCOMP: + case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: if (IS_ENABLED(CONFIG_SECCOMP)) mode = SPECTRE_V2_USER_SECCOMP; else @@ -350,12 +358,15 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) if (boot_cpu_has(X86_FEATURE_IBPB)) { setup_force_cpu_cap(X86_FEATURE_USE_IBPB); - switch (mode) { - case SPECTRE_V2_USER_STRICT: + switch (cmd) { + case SPECTRE_V2_USER_CMD_FORCE: + case SPECTRE_V2_USER_CMD_PRCTL_IBPB: + case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: static_branch_enable(&switch_mm_always_ibpb); break; - case SPECTRE_V2_USER_PRCTL: - case SPECTRE_V2_USER_SECCOMP: + case SPECTRE_V2_USER_CMD_PRCTL: + case SPECTRE_V2_USER_CMD_AUTO: + case SPECTRE_V2_USER_CMD_SECCOMP: static_branch_enable(&switch_mm_cond_ibpb); break; default: @@ -363,7 +374,8 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) } pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", - mode == SPECTRE_V2_USER_STRICT ? "always-on" : "conditional"); + static_key_enabled(&switch_mm_always_ibpb) ? + "always-on" : "conditional"); } /* If enhanced IBRS is enabled no STIPB required */ -- GitLab From a06361526cc71cb0ebef6ab7aa698ec63465b562 Mon Sep 17 00:00:00 2001 From: Junaid Shahid Date: Wed, 31 Oct 2018 14:53:57 -0700 Subject: [PATCH 0270/1286] kvm: mmu: Fix race in emulated page table writes commit 0e0fee5c539b61fdd098332e0e2cc375d9073706 upstream. When a guest page table is updated via an emulated write, kvm_mmu_pte_write() is called to update the shadow PTE using the just written guest PTE value. But if two emulated guest PTE writes happened concurrently, it is possible that the guest PTE and the shadow PTE end up being out of sync. Emulated writes do not mark the shadow page as unsync-ed, so this inconsistency will not be resolved even by a guest TLB flush (unless the page was marked as unsync-ed at some other point). This is fixed by re-reading the current value of the guest PTE after the MMU lock has been acquired instead of just using the value that was written prior to calling kvm_mmu_pte_write(). Signed-off-by: Junaid Shahid Reviewed-by: Wanpeng Li Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/mmu.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index d755e0d44ac1..364d9895dd56 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -4734,9 +4734,9 @@ static bool need_remote_flush(u64 old, u64 new) } static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, - const u8 *new, int *bytes) + int *bytes) { - u64 gentry; + u64 gentry = 0; int r; /* @@ -4748,22 +4748,12 @@ static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ *gpa &= ~(gpa_t)7; *bytes = 8; - r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); - if (r) - gentry = 0; - new = (const u8 *)&gentry; } - switch (*bytes) { - case 4: - gentry = *(const u32 *)new; - break; - case 8: - gentry = *(const u64 *)new; - break; - default: - gentry = 0; - break; + if (*bytes == 4 || *bytes == 8) { + r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); + if (r) + gentry = 0; } return gentry; @@ -4876,8 +4866,6 @@ static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); - gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); - /* * No need to care whether allocation memory is successful * or not since pte prefetch is skiped if it does not have @@ -4886,6 +4874,9 @@ static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, mmu_topup_memory_caches(vcpu); spin_lock(&vcpu->kvm->mmu_lock); + + gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); + ++vcpu->kvm->stat.mmu_pte_write; kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); -- GitLab From 57e972ecad4fdee027a690b64c7d619dae489015 Mon Sep 17 00:00:00 2001 From: Jim Mattson Date: Tue, 22 May 2018 09:54:20 -0700 Subject: [PATCH 0271/1286] kvm: svm: Ensure an IBPB on all affected CPUs when freeing a vmcb commit fd65d3142f734bc4376053c8d75670041903134d upstream. Previously, we only called indirect_branch_prediction_barrier on the logical CPU that freed a vmcb. This function should be called on all logical CPUs that last loaded the vmcb in question. Fixes: 15d45071523d ("KVM/x86: Add IBPB support") Reported-by: Neel Natu Signed-off-by: Jim Mattson Reviewed-by: Konrad Rzeszutek Wilk Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/svm.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index e9dbd62bb46e..17f08db34547 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1733,21 +1733,31 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) return ERR_PTR(err); } +static void svm_clear_current_vmcb(struct vmcb *vmcb) +{ + int i; + + for_each_online_cpu(i) + cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL); +} + static void svm_free_vcpu(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); + /* + * The vmcb page can be recycled, causing a false negative in + * svm_vcpu_load(). So, ensure that no logical CPU has this + * vmcb page recorded as its current vmcb. + */ + svm_clear_current_vmcb(svm->vmcb); + __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT)); __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); __free_page(virt_to_page(svm->nested.hsave)); __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); kvm_vcpu_uninit(vcpu); kmem_cache_free(kvm_vcpu_cache, svm); - /* - * The vmcb page can be recycled, causing a false negative in - * svm_vcpu_load(). So do a full IBPB now. - */ - indirect_branch_prediction_barrier(); } static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) -- GitLab From 08b9a96720a1e67dfed4b22a5192892d556fc5fc Mon Sep 17 00:00:00 2001 From: Liran Alon Date: Thu, 8 Nov 2018 00:43:06 +0200 Subject: [PATCH 0272/1286] KVM: x86: Fix kernel info-leak in KVM_HC_CLOCK_PAIRING hypercall commit bcbfbd8ec21096027f1ee13ce6c185e8175166f6 upstream. kvm_pv_clock_pairing() allocates local var "struct kvm_clock_pairing clock_pairing" on stack and initializes all it's fields besides padding (clock_pairing.pad[]). Because clock_pairing var is written completely (including padding) to guest memory, failure to init struct padding results in kernel info-leak. Fix the issue by making sure to also init the padding with zeroes. Fixes: 55dd00a73a51 ("KVM: x86: add KVM_HC_CLOCK_PAIRING hypercall") Reported-by: syzbot+a8ef68d71211ba264f56@syzkaller.appspotmail.com Reviewed-by: Mark Kanda Signed-off-by: Liran Alon Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/x86.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 8d688b213504..7c4d02dba110 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6378,6 +6378,7 @@ static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, clock_pairing.nsec = ts.tv_nsec; clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); clock_pairing.flags = 0; + memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); ret = 0; if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, -- GitLab From 83f00ab9a7c03e9f1410727d985b7fe9473002e1 Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Tue, 20 Nov 2018 16:34:18 +0800 Subject: [PATCH 0273/1286] KVM: X86: Fix scan ioapic use-before-initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit e97f852fd4561e77721bb9a4e0ea9d98305b1e93 upstream. Reported by syzkaller: BUG: unable to handle kernel NULL pointer dereference at 00000000000001c8 PGD 80000003ec4da067 P4D 80000003ec4da067 PUD 3f7bfa067 PMD 0 Oops: 0000 [#1] PREEMPT SMP PTI CPU: 7 PID: 5059 Comm: debug Tainted: G OE 4.19.0-rc5 #16 RIP: 0010:__lock_acquire+0x1a6/0x1990 Call Trace: lock_acquire+0xdb/0x210 _raw_spin_lock+0x38/0x70 kvm_ioapic_scan_entry+0x3e/0x110 [kvm] vcpu_enter_guest+0x167e/0x1910 [kvm] kvm_arch_vcpu_ioctl_run+0x35c/0x610 [kvm] kvm_vcpu_ioctl+0x3e9/0x6d0 [kvm] do_vfs_ioctl+0xa5/0x690 ksys_ioctl+0x6d/0x80 __x64_sys_ioctl+0x1a/0x20 do_syscall_64+0x83/0x6e0 entry_SYSCALL_64_after_hwframe+0x49/0xbe The reason is that the testcase writes hyperv synic HV_X64_MSR_SINT6 msr and triggers scan ioapic logic to load synic vectors into EOI exit bitmap. However, irqchip is not initialized by this simple testcase, ioapic/apic objects should not be accessed. This can be triggered by the following program: #define _GNU_SOURCE #include #include #include #include #include #include #include #include uint64_t r[3] = {0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff}; int main(void) { syscall(__NR_mmap, 0x20000000, 0x1000000, 3, 0x32, -1, 0); long res = 0; memcpy((void*)0x20000040, "/dev/kvm", 9); res = syscall(__NR_openat, 0xffffffffffffff9c, 0x20000040, 0, 0); if (res != -1) r[0] = res; res = syscall(__NR_ioctl, r[0], 0xae01, 0); if (res != -1) r[1] = res; res = syscall(__NR_ioctl, r[1], 0xae41, 0); if (res != -1) r[2] = res; memcpy( (void*)0x20000080, "\x01\x00\x00\x00\x00\x5b\x61\xbb\x96\x00\x00\x40\x00\x00\x00\x00\x01\x00" "\x08\x00\x00\x00\x00\x00\x0b\x77\xd1\x78\x4d\xd8\x3a\xed\xb1\x5c\x2e\x43" "\xaa\x43\x39\xd6\xff\xf5\xf0\xa8\x98\xf2\x3e\x37\x29\x89\xde\x88\xc6\x33" "\xfc\x2a\xdb\xb7\xe1\x4c\xac\x28\x61\x7b\x9c\xa9\xbc\x0d\xa0\x63\xfe\xfe" "\xe8\x75\xde\xdd\x19\x38\xdc\x34\xf5\xec\x05\xfd\xeb\x5d\xed\x2e\xaf\x22" "\xfa\xab\xb7\xe4\x42\x67\xd0\xaf\x06\x1c\x6a\x35\x67\x10\x55\xcb", 106); syscall(__NR_ioctl, r[2], 0x4008ae89, 0x20000080); syscall(__NR_ioctl, r[2], 0xae80, 0); return 0; } This patch fixes it by bailing out scan ioapic if ioapic is not initialized in kernel. Reported-by: Wei Wu Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Wei Wu Signed-off-by: Wanpeng Li Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/x86.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7c4d02dba110..f24329659bea 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6885,7 +6885,8 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) else { if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) kvm_x86_ops->sync_pir_to_irr(vcpu); - kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); + if (ioapic_in_kernel(vcpu->kvm)) + kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); } bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, vcpu_to_synic(vcpu)->vec_bitmap, 256); -- GitLab From d039837ab8cb7fb7095ec9746fb04a854987179e Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 26 Nov 2018 13:29:41 -0800 Subject: [PATCH 0274/1286] xtensa: enable coprocessors that are being flushed commit 2958b66694e018c552be0b60521fec27e8d12988 upstream. coprocessor_flush_all may be called from a context of a thread that is different from the thread being flushed. In that case contents of the cpenable special register may not match ti->cpenable of the target thread, resulting in unhandled coprocessor exception in the kernel context. Set cpenable special register to the ti->cpenable of the target register for the duration of the flush and restore it afterwards. This fixes the following crash caused by coprocessor register inspection in native gdb: (gdb) p/x $w0 Illegal instruction in kernel: sig: 9 [#1] PREEMPT Call Trace: ___might_sleep+0x184/0x1a4 __might_sleep+0x41/0xac exit_signals+0x14/0x218 do_exit+0xc9/0x8b8 die+0x99/0xa0 do_illegal_instruction+0x18/0x6c common_exception+0x77/0x77 coprocessor_flush+0x16/0x3c arch_ptrace+0x46c/0x674 sys_ptrace+0x2ce/0x3b4 system_call+0x54/0x80 common_exception+0x77/0x77 note: gdb[100] exited with preempt_count 1 Killed Cc: stable@vger.kernel.org Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman --- arch/xtensa/kernel/process.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index ff4f0ecb03dd..f1c46bc5d465 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c @@ -88,18 +88,21 @@ void coprocessor_release_all(struct thread_info *ti) void coprocessor_flush_all(struct thread_info *ti) { - unsigned long cpenable; + unsigned long cpenable, old_cpenable; int i; preempt_disable(); + RSR_CPENABLE(old_cpenable); cpenable = ti->cpenable; + WSR_CPENABLE(cpenable); for (i = 0; i < XCHAL_CP_MAX; i++) { if ((cpenable & 1) != 0 && coprocessor_owner[i] == ti) coprocessor_flush(ti, i); cpenable >>= 1; } + WSR_CPENABLE(old_cpenable); preempt_enable(); } -- GitLab From b35182226166c03713a10ffebcf2838569c95d57 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 26 Nov 2018 15:18:26 -0800 Subject: [PATCH 0275/1286] xtensa: fix coprocessor context offset definitions commit 03bc996af0cc71c7f30c384d8ce7260172423b34 upstream. Coprocessor context offsets are used by the assembly code that moves coprocessor context between the individual fields of the thread_info::xtregs_cp structure and coprocessor registers. This fixes coprocessor context clobbering on flushing and reloading during normal user code execution and user process debugging in the presence of more than one coprocessor in the core configuration. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman --- arch/xtensa/kernel/asm-offsets.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c index bcb5beb81177..7df02fc934a9 100644 --- a/arch/xtensa/kernel/asm-offsets.c +++ b/arch/xtensa/kernel/asm-offsets.c @@ -91,14 +91,14 @@ int main(void) DEFINE(THREAD_SP, offsetof (struct task_struct, thread.sp)); DEFINE(THREAD_CPENABLE, offsetof (struct thread_info, cpenable)); #if XTENSA_HAVE_COPROCESSORS - DEFINE(THREAD_XTREGS_CP0, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP1, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP2, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP3, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP4, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP5, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP6, offsetof (struct thread_info, xtregs_cp)); - DEFINE(THREAD_XTREGS_CP7, offsetof (struct thread_info, xtregs_cp)); + DEFINE(THREAD_XTREGS_CP0, offsetof(struct thread_info, xtregs_cp.cp0)); + DEFINE(THREAD_XTREGS_CP1, offsetof(struct thread_info, xtregs_cp.cp1)); + DEFINE(THREAD_XTREGS_CP2, offsetof(struct thread_info, xtregs_cp.cp2)); + DEFINE(THREAD_XTREGS_CP3, offsetof(struct thread_info, xtregs_cp.cp3)); + DEFINE(THREAD_XTREGS_CP4, offsetof(struct thread_info, xtregs_cp.cp4)); + DEFINE(THREAD_XTREGS_CP5, offsetof(struct thread_info, xtregs_cp.cp5)); + DEFINE(THREAD_XTREGS_CP6, offsetof(struct thread_info, xtregs_cp.cp6)); + DEFINE(THREAD_XTREGS_CP7, offsetof(struct thread_info, xtregs_cp.cp7)); #endif DEFINE(THREAD_XTREGS_USER, offsetof (struct thread_info, xtregs_user)); DEFINE(XTREGS_USER_SIZE, sizeof(xtregs_user_t)); -- GitLab From d36e4ee3b3ce4cf93e8fa145841287bbdb140fec Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 26 Nov 2018 18:06:01 -0800 Subject: [PATCH 0276/1286] xtensa: fix coprocessor part of ptrace_{get,set}xregs commit 38a35a78c5e270cbe53c4fef6b0d3c2da90dd849 upstream. Layout of coprocessor registers in the elf_xtregs_t and xtregs_coprocessor_t may be different due to alignment. Thus it is not always possible to copy data between the xtregs_coprocessor_t structure and the elf_xtregs_t and get correct values for all registers. Use a table of offsets and sizes of individual coprocessor register groups to do coprocessor context copying in the ptrace_getxregs and ptrace_setxregs. This fixes incorrect coprocessor register values reading from the user process by the native gdb on an xtensa core with multiple coprocessors and registers with high alignment requirements. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman --- arch/xtensa/kernel/ptrace.c | 42 +++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c index e2461968efb2..7c3ed7d78075 100644 --- a/arch/xtensa/kernel/ptrace.c +++ b/arch/xtensa/kernel/ptrace.c @@ -127,12 +127,37 @@ static int ptrace_setregs(struct task_struct *child, void __user *uregs) } +#if XTENSA_HAVE_COPROCESSORS +#define CP_OFFSETS(cp) \ + { \ + .elf_xtregs_offset = offsetof(elf_xtregs_t, cp), \ + .ti_offset = offsetof(struct thread_info, xtregs_cp.cp), \ + .sz = sizeof(xtregs_ ## cp ## _t), \ + } + +static const struct { + size_t elf_xtregs_offset; + size_t ti_offset; + size_t sz; +} cp_offsets[] = { + CP_OFFSETS(cp0), + CP_OFFSETS(cp1), + CP_OFFSETS(cp2), + CP_OFFSETS(cp3), + CP_OFFSETS(cp4), + CP_OFFSETS(cp5), + CP_OFFSETS(cp6), + CP_OFFSETS(cp7), +}; +#endif + static int ptrace_getxregs(struct task_struct *child, void __user *uregs) { struct pt_regs *regs = task_pt_regs(child); struct thread_info *ti = task_thread_info(child); elf_xtregs_t __user *xtregs = uregs; int ret = 0; + int i __maybe_unused; if (!access_ok(VERIFY_WRITE, uregs, sizeof(elf_xtregs_t))) return -EIO; @@ -140,8 +165,13 @@ static int ptrace_getxregs(struct task_struct *child, void __user *uregs) #if XTENSA_HAVE_COPROCESSORS /* Flush all coprocessor registers to memory. */ coprocessor_flush_all(ti); - ret |= __copy_to_user(&xtregs->cp0, &ti->xtregs_cp, - sizeof(xtregs_coprocessor_t)); + + for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i) + ret |= __copy_to_user((char __user *)xtregs + + cp_offsets[i].elf_xtregs_offset, + (const char *)ti + + cp_offsets[i].ti_offset, + cp_offsets[i].sz); #endif ret |= __copy_to_user(&xtregs->opt, ®s->xtregs_opt, sizeof(xtregs->opt)); @@ -157,6 +187,7 @@ static int ptrace_setxregs(struct task_struct *child, void __user *uregs) struct pt_regs *regs = task_pt_regs(child); elf_xtregs_t *xtregs = uregs; int ret = 0; + int i __maybe_unused; if (!access_ok(VERIFY_READ, uregs, sizeof(elf_xtregs_t))) return -EFAULT; @@ -166,8 +197,11 @@ static int ptrace_setxregs(struct task_struct *child, void __user *uregs) coprocessor_flush_all(ti); coprocessor_release_all(ti); - ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0, - sizeof(xtregs_coprocessor_t)); + for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i) + ret |= __copy_from_user((char *)ti + cp_offsets[i].ti_offset, + (const char __user *)xtregs + + cp_offsets[i].elf_xtregs_offset, + cp_offsets[i].sz); #endif ret |= __copy_from_user(®s->xtregs_opt, &xtregs->opt, sizeof(xtregs->opt)); -- GitLab From 52fa8eaac8149594d57bd4fe0cfeaa329037d400 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Wed, 14 Nov 2018 11:35:24 +0000 Subject: [PATCH 0277/1286] Btrfs: ensure path name is null terminated at btrfs_control_ioctl commit f505754fd6599230371cb01b9332754ddc104be1 upstream. We were using the path name received from user space without checking that it is null terminated. While btrfs-progs is well behaved and does proper validation and null termination, someone could call the ioctl and pass a non-null terminated patch, leading to buffer overrun problems in the kernel. The ioctl is protected by CAP_SYS_ADMIN. So just set the last byte of the path to a null character, similar to what we do in other ioctls (add/remove/resize device, snapshot creation, etc). CC: stable@vger.kernel.org # 4.4+ Reviewed-by: Anand Jain Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/super.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index fe960d5e8913..49a02bf091ae 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -2176,6 +2176,7 @@ static long btrfs_control_ioctl(struct file *file, unsigned int cmd, vol = memdup_user((void __user *)arg, sizeof(*vol)); if (IS_ERR(vol)) return PTR_ERR(vol); + vol->name[BTRFS_PATH_NAME_MAX] = '\0'; switch (cmd) { case BTRFS_IOC_SCAN_DEV: -- GitLab From e380f318e63d851607cfc8b288281668aad11d53 Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Fri, 23 Nov 2018 18:10:15 +0800 Subject: [PATCH 0278/1286] btrfs: relocation: set trans to be NULL after ending transaction commit 42a657f57628402c73237547f0134e083e2f6764 upstream. The function relocate_block_group calls btrfs_end_transaction to release trans when update_backref_cache returns 1, and then continues the loop body. If btrfs_block_rsv_refill fails this time, it will jump out the loop and the freed trans will be accessed. This may result in a use-after-free bug. The patch assigns NULL to trans after trans is released so that it will not be accessed. Fixes: 0647bf564f1 ("Btrfs: improve forever loop when doing balance relocation") CC: stable@vger.kernel.org # 4.4+ Reviewed-by: Qu Wenruo Signed-off-by: Pan Bian Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/relocation.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c index eeae2c3ab17e..5feb8b03ffe8 100644 --- a/fs/btrfs/relocation.c +++ b/fs/btrfs/relocation.c @@ -4048,6 +4048,7 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc) restart: if (update_backref_cache(trans, &rc->backref_cache)) { btrfs_end_transaction(trans); + trans = NULL; continue; } -- GitLab From ee48a9df170c233b406d49aa8840625a51ee9c0c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:16:49 +0000 Subject: [PATCH 0279/1286] PCI: layerscape: Fix wrong invocation of outbound window disable accessor commit c6fd6fe9dea44732cdcd970f1130b8cc50ad685a upstream. The order of parameters is not correct when invoking the outbound window disable routine. Fix it. Fixes: 4a2745d760fa ("PCI: layerscape: Disable outbound windows configured by bootloader") Signed-off-by: Hou Zhiqiang [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/dwc/pci-layerscape.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 87fa486bee2c..1ede4b60aac3 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -89,7 +89,7 @@ static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) int i; for (i = 0; i < PCIE_IATU_NUM; i++) - dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i); + dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); } static int ls1021_pcie_link_up(struct dw_pcie *pci) -- GitLab From ad953dfdfa9543d224abd18fbf12bcac6454c376 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Tue, 13 Nov 2018 11:25:35 +0100 Subject: [PATCH 0280/1286] arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou. commit c1d91f86a1b4c9c05854d59c6a0abd5d0f75b849 upstream. This patch fixes the wrong polarity setting for the PCIe host driver's pre-reset pin for rk3399-puma-haikou. Without this patch link training will most likely fail. Fixes: 60fd9f72ce8a ("arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM") Cc: stable@vger.kernel.org Signed-off-by: Christoph Muellner Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 9a7486058455..eea7f8f070cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -130,7 +130,7 @@ }; &pcie0 { - ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; -- GitLab From 855eefd9124a5a963625c046faca862c9369b37c Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Tue, 27 Nov 2018 14:41:37 +0100 Subject: [PATCH 0281/1286] x86/MCE/AMD: Fix the thresholding machinery initialization order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 60c8144afc287ef09ce8c1230c6aa972659ba1bb upstream. Currently, the code sets up the thresholding interrupt vector and only then goes about initializing the thresholding banks. Which is wrong, because an early thresholding interrupt would cause a NULL pointer dereference when accessing those banks and prevent the machine from booting. Therefore, set the thresholding interrupt vector only *after* having initialized the banks successfully. Fixes: 18807ddb7f88 ("x86/mce/AMD: Reset Threshold Limit after logging error") Reported-by: Rafał Miłecki Reported-by: John Clemens Signed-off-by: Borislav Petkov Tested-by: Rafał Miłecki Tested-by: John Clemens Cc: Aravind Gopalakrishnan Cc: linux-edac@vger.kernel.org Cc: stable@vger.kernel.org Cc: Tony Luck Cc: x86@kernel.org Cc: Yazen Ghannam Link: https://lkml.kernel.org/r/20181127101700.2964-1-zajec5@gmail.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=201291 Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index dbcb01006749..beec0daecbc5 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -56,7 +56,7 @@ /* Threshold LVT offset is at MSR0xC0000410[15:12] */ #define SMCA_THR_LVT_OFF 0xF000 -static bool thresholding_en; +static bool thresholding_irq_en; static const char * const th_names[] = { "load_store", @@ -533,9 +533,8 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, set_offset: offset = setup_APIC_mce_threshold(offset, new); - - if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) - mce_threshold_vector = amd_threshold_interrupt; + if (offset == new) + thresholding_irq_en = true; done: mce_threshold_block_init(&b, offset); @@ -1356,9 +1355,6 @@ int mce_threshold_remove_device(unsigned int cpu) { unsigned int bank; - if (!thresholding_en) - return 0; - for (bank = 0; bank < mca_cfg.banks; ++bank) { if (!(per_cpu(bank_map, cpu) & (1 << bank))) continue; @@ -1376,9 +1372,6 @@ int mce_threshold_create_device(unsigned int cpu) struct threshold_bank **bp; int err = 0; - if (!thresholding_en) - return 0; - bp = per_cpu(threshold_banks, cpu); if (bp) return 0; @@ -1407,9 +1400,6 @@ static __init int threshold_init_device(void) { unsigned lcpu = 0; - if (mce_threshold_vector == amd_threshold_interrupt) - thresholding_en = true; - /* to hit CPUs online before the notifier is up */ for_each_online_cpu(lcpu) { int err = mce_threshold_create_device(lcpu); @@ -1418,6 +1408,9 @@ static __init int threshold_init_device(void) return err; } + if (thresholding_irq_en) + mce_threshold_vector = amd_threshold_interrupt; + return 0; } /* -- GitLab From e8499ab5b93aca271c343786084c000c6f7839b5 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Tue, 20 Nov 2018 11:26:35 +0100 Subject: [PATCH 0282/1286] x86/fpu: Disable bottom halves while loading FPU registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 68239654acafe6aad5a3c1dc7237e60accfebc03 upstream. The sequence fpu->initialized = 1; /* step A */ preempt_disable(); /* step B */ fpu__restore(fpu); preempt_enable(); in __fpu__restore_sig() is racy in regard to a context switch. For 32bit frames, __fpu__restore_sig() prepares the FPU state within fpu->state. To ensure that a context switch (switch_fpu_prepare() in particular) does not modify fpu->state it uses fpu__drop() which sets fpu->initialized to 0. After fpu->initialized is cleared, the CPU's FPU state is not saved to fpu->state during a context switch. The new state is loaded via fpu__restore(). It gets loaded into fpu->state from userland and ensured it is sane. fpu->initialized is then set to 1 in order to avoid fpu__initialize() doing anything (overwrite the new state) which is part of fpu__restore(). A context switch between step A and B above would save CPU's current FPU registers to fpu->state and overwrite the newly prepared state. This looks like a tiny race window but the Kernel Test Robot reported this back in 2016 while we had lazy FPU support. Borislav Petkov made the link between that report and another patch that has been posted. Since the removal of the lazy FPU support, this race goes unnoticed because the warning has been removed. Disable bottom halves around the restore sequence to avoid the race. BH need to be disabled because BH is allowed to run (even with preemption disabled) and might invoke kernel_fpu_begin() by doing IPsec. [ bp: massage commit message a bit. ] Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Borislav Petkov Acked-by: Ingo Molnar Acked-by: Thomas Gleixner Cc: Andy Lutomirski Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: "Jason A. Donenfeld" Cc: kvm ML Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Rik van Riel Cc: stable@vger.kernel.org Cc: x86-ml Link: http://lkml.kernel.org/r/20181120102635.ddv3fvavxajjlfqk@linutronix.de Link: https://lkml.kernel.org/r/20160226074940.GA28911@pd.tnic Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/fpu/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index 61a949d84dfa..d99a8ee9e185 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -344,10 +344,10 @@ static int __fpu__restore_sig(void __user *buf, void __user *buf_fx, int size) sanitize_restored_xstate(tsk, &env, xfeatures, fx_only); } + local_bh_disable(); fpu->initialized = 1; - preempt_disable(); fpu__restore(fpu); - preempt_enable(); + local_bh_enable(); return err; } else { -- GitLab From fae1bec5c2b29e809bd81b2ce8b5ba979ad23a92 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 21 Nov 2018 11:16:10 +0100 Subject: [PATCH 0283/1286] perf/x86/intel: Move branch tracing setup to the Intel-specific source file commit ed6101bbf6266ee83e620b19faa7c6ad56bb41ab upstream. Moving branch tracing setup to Intel core object into separate intel_pmu_bts_config function, because it's Intel specific. Suggested-by: Peter Zijlstra Signed-off-by: Jiri Olsa Acked-by: Peter Zijlstra Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/20181121101612.16272-1-jolsa@kernel.org Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/core.c | 20 ------------------ arch/x86/events/intel/core.c | 41 +++++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 21 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e5097dc85a06..7d12b0d1f359 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -438,26 +438,6 @@ int x86_setup_perfctr(struct perf_event *event) if (config == -1LL) return -EINVAL; - /* - * Branch tracing: - */ - if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && - !attr->freq && hwc->sample_period == 1) { - /* BTS is not supported by this architecture. */ - if (!x86_pmu.bts_active) - return -EOPNOTSUPP; - - /* BTS is currently only allowed for user-mode. */ - if (!attr->exclude_kernel) - return -EOPNOTSUPP; - - /* disallow bts if conflicting events are present */ - if (x86_add_exclusive(x86_lbr_exclusive_lbr)) - return -EBUSY; - - event->destroy = hw_perf_lbr_event_destroy; - } - hwc->config |= config; return 0; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 228732654cfe..20501336fd94 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2973,10 +2973,49 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event) return flags; } +static int intel_pmu_bts_config(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + struct hw_perf_event *hwc = &event->hw; + + if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && + !attr->freq && hwc->sample_period == 1) { + /* BTS is not supported by this architecture. */ + if (!x86_pmu.bts_active) + return -EOPNOTSUPP; + + /* BTS is currently only allowed for user-mode. */ + if (!attr->exclude_kernel) + return -EOPNOTSUPP; + + /* disallow bts if conflicting events are present */ + if (x86_add_exclusive(x86_lbr_exclusive_lbr)) + return -EBUSY; + + event->destroy = hw_perf_lbr_event_destroy; + } + + return 0; +} + +static int core_pmu_hw_config(struct perf_event *event) +{ + int ret = x86_pmu_hw_config(event); + + if (ret) + return ret; + + return intel_pmu_bts_config(event); +} + static int intel_pmu_hw_config(struct perf_event *event) { int ret = x86_pmu_hw_config(event); + if (ret) + return ret; + + ret = intel_pmu_bts_config(event); if (ret) return ret; @@ -3462,7 +3501,7 @@ static __initconst const struct x86_pmu core_pmu = { .enable_all = core_pmu_enable_all, .enable = core_pmu_enable_event, .disable = x86_pmu_disable_event, - .hw_config = x86_pmu_hw_config, + .hw_config = core_pmu_hw_config, .schedule_events = x86_schedule_events, .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, .perfctr = MSR_ARCH_PERFMON_PERFCTR0, -- GitLab From ecef7c1ad46bfdc64c99574488252f4ba029afbc Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Wed, 21 Nov 2018 11:16:11 +0100 Subject: [PATCH 0284/1286] perf/x86/intel: Add generic branch tracing check to intel_pmu_has_bts() commit 67266c1080ad56c31af72b9c18355fde8ccc124a upstream. Currently we check the branch tracing only by checking for the PERF_COUNT_HW_BRANCH_INSTRUCTIONS event of PERF_TYPE_HARDWARE type. But we can define the same event with the PERF_TYPE_RAW type. Changing the intel_pmu_has_bts() code to check on event's final hw config value, so both HW types are covered. Adding unlikely to intel_pmu_has_bts() condition calls, because it was used in the original code in intel_bts_constraints. Signed-off-by: Jiri Olsa Acked-by: Peter Zijlstra Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/20181121101612.16272-2-jolsa@kernel.org Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/core.c | 17 +++-------------- arch/x86/events/perf_event.h | 13 +++++++++---- 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 20501336fd94..7bb80151bfff 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2345,16 +2345,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) static struct event_constraint * intel_bts_constraints(struct perf_event *event) { - struct hw_perf_event *hwc = &event->hw; - unsigned int hw_event, bts_event; - - if (event->attr.freq) - return NULL; - - hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; - bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); - - if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) + if (unlikely(intel_pmu_has_bts(event))) return &bts_constraint; return NULL; @@ -2976,10 +2967,8 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event) static int intel_pmu_bts_config(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; - struct hw_perf_event *hwc = &event->hw; - if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && - !attr->freq && hwc->sample_period == 1) { + if (unlikely(intel_pmu_has_bts(event))) { /* BTS is not supported by this architecture. */ if (!x86_pmu.bts_active) return -EOPNOTSUPP; @@ -3038,7 +3027,7 @@ static int intel_pmu_hw_config(struct perf_event *event) /* * BTS is set up earlier in this path, so don't account twice */ - if (!intel_pmu_has_bts(event)) { + if (!unlikely(intel_pmu_has_bts(event))) { /* disallow lbr if conflicting events are present */ if (x86_add_exclusive(x86_lbr_exclusive_lbr)) return -EBUSY; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index c6698c63c047..3c51fcaf1e34 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -850,11 +850,16 @@ static inline int amd_pmu_init(void) static inline bool intel_pmu_has_bts(struct perf_event *event) { - if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && - !event->attr.freq && event->hw.sample_period == 1) - return true; + struct hw_perf_event *hwc = &event->hw; + unsigned int hw_event, bts_event; + + if (event->attr.freq) + return false; + + hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; + bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); - return false; + return hw_event == bts_event && hwc->sample_period == 1; } int intel_pmu_save_and_restart(struct perf_event *event); -- GitLab From b7c769ebd9db6e67a6e01c962f7c92b706fa6acf Mon Sep 17 00:00:00 2001 From: Maximilian Heyne Date: Fri, 30 Nov 2018 08:35:14 -0700 Subject: [PATCH 0285/1286] fs: fix lost error code in dio_complete commit 41e817bca3acd3980efe5dd7d28af0e6f4ab9247 upstream. commit e259221763a40403d5bb232209998e8c45804ab8 ("fs: simplify the generic_write_sync prototype") reworked callers of generic_write_sync(), and ended up dropping the error return for the directio path. Prior to that commit, in dio_complete(), an error would be bubbled up the stack, but after that commit, errors passed on to dio_complete were eaten up. This was reported on the list earlier, and a fix was proposed in https://lore.kernel.org/lkml/20160921141539.GA17898@infradead.org/, but never followed up with. We recently hit this bug in our testing where fencing io errors, which were previously erroring out with EIO, were being returned as success operations after this commit. The fix proposed on the list earlier was a little short -- it would have still called generic_write_sync() in case `ret` already contained an error. This fix ensures generic_write_sync() is only called when there's no pending error in the write. Additionally, transferred is replaced with ret to bring this code in line with other callers. Fixes: e259221763a4 ("fs: simplify the generic_write_sync prototype") Reported-by: Ravi Nankani Signed-off-by: Maximilian Heyne Reviewed-by: Christoph Hellwig CC: Torsten Mehlan CC: Uwe Dannowski CC: Amit Shah CC: David Woodhouse CC: stable@vger.kernel.org Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- fs/direct-io.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/direct-io.c b/fs/direct-io.c index 625a84aa6484..40567501015f 100644 --- a/fs/direct-io.c +++ b/fs/direct-io.c @@ -304,8 +304,8 @@ static ssize_t dio_complete(struct dio *dio, ssize_t ret, unsigned int flags) */ dio->iocb->ki_pos += transferred; - if (dio->op == REQ_OP_WRITE) - ret = generic_write_sync(dio->iocb, transferred); + if (ret > 0 && dio->op == REQ_OP_WRITE) + ret = generic_write_sync(dio->iocb, ret); dio->iocb->ki_complete(dio->iocb, ret, 0); } -- GitLab From 0d542d58b6b5fe01095484c2628e46afe88312a9 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 23 Nov 2018 18:16:33 +0100 Subject: [PATCH 0286/1286] ALSA: wss: Fix invalid snd_free_pages() at error path commit 7b69154171b407844c273ab4c10b5f0ddcd6aa29 upstream. Some spurious calls of snd_free_pages() have been overlooked and remain in the error paths of wss driver code. Since runtime->dma_area is managed by the PCM core helper, we shouldn't release manually. Drop the superfluous calls. Reviewed-by: Takashi Sakamoto Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/isa/wss/wss_lib.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/isa/wss/wss_lib.c b/sound/isa/wss/wss_lib.c index 8a852042a066..91cd305cabd7 100644 --- a/sound/isa/wss/wss_lib.c +++ b/sound/isa/wss/wss_lib.c @@ -1531,7 +1531,6 @@ static int snd_wss_playback_open(struct snd_pcm_substream *substream) if (err < 0) { if (chip->release_dma) chip->release_dma(chip, chip->dma_private_data, chip->dma1); - snd_free_pages(runtime->dma_area, runtime->dma_bytes); return err; } chip->playback_substream = substream; @@ -1572,7 +1571,6 @@ static int snd_wss_capture_open(struct snd_pcm_substream *substream) if (err < 0) { if (chip->release_dma) chip->release_dma(chip, chip->dma_private_data, chip->dma2); - snd_free_pages(runtime->dma_area, runtime->dma_bytes); return err; } chip->capture_substream = substream; -- GitLab From ef8944bf5a97557bf0cb7b0da78bc60eb78bff33 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 23 Nov 2018 15:44:00 +0100 Subject: [PATCH 0287/1286] ALSA: ac97: Fix incorrect bit shift at AC97-SPSA control write commit 7194eda1ba0872d917faf3b322540b4f57f11ba5 upstream. The function snd_ac97_put_spsa() gets the bit shift value from the associated private_value, but it extracts too much; the current code extracts 8 bit values in bits 8-15, but this is a combination of two nibbles (bits 8-11 and bits 12-15) for left and right shifts. Due to the incorrect bits extraction, the actual shift may go beyond the 32bit value, as spotted recently by UBSAN check: UBSAN: Undefined behaviour in sound/pci/ac97/ac97_codec.c:836:7 shift exponent 68 is too large for 32-bit type 'int' This patch fixes the shift value extraction by masking the properly with 0x0f instead of 0xff. Reported-and-tested-by: Meelis Roos Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/ac97/ac97_codec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index 1ef7cdf1d3e8..38f355ae1863 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -824,7 +824,7 @@ static int snd_ac97_put_spsa(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_ { struct snd_ac97 *ac97 = snd_kcontrol_chip(kcontrol); int reg = kcontrol->private_value & 0xff; - int shift = (kcontrol->private_value >> 8) & 0xff; + int shift = (kcontrol->private_value >> 8) & 0x0f; int mask = (kcontrol->private_value >> 16) & 0xff; // int invert = (kcontrol->private_value >> 24) & 0xff; unsigned short value, old, new; -- GitLab From 73ce314c172d4f7340b217c08861863665888972 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 22 Nov 2018 14:36:17 +0100 Subject: [PATCH 0288/1286] ALSA: control: Fix race between adding and removing a user element commit e1a7bfe3807974e66f971f2589d4e0197ec0fced upstream. The procedure for adding a user control element has some window opened for race against the concurrent removal of a user element. This was caught by syzkaller, hitting a KASAN use-after-free error. This patch addresses the bug by wrapping the whole procedure to add a user control element with the card->controls_rwsem, instead of only around the increment of card->user_ctl_count. This required a slight code refactoring, too. The function snd_ctl_add() is split to two parts: a core function to add the control element and a part calling it. The former is called from the function for adding a user control element inside the controls_rwsem. One change to be noted is that snd_ctl_notify() for adding a control element gets called inside the controls_rwsem as well while it was called outside the rwsem. But this should be OK, as snd_ctl_notify() takes another (finer) rwlock instead of rwsem, and the call of snd_ctl_notify() inside rwsem is already done in another code path. Reported-by: syzbot+dc09047bce3820621ba2@syzkaller.appspotmail.com Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/control.c | 80 +++++++++++++++++++++++++------------------- 1 file changed, 45 insertions(+), 35 deletions(-) diff --git a/sound/core/control.c b/sound/core/control.c index af7e6165e21e..36571cd49be3 100644 --- a/sound/core/control.c +++ b/sound/core/control.c @@ -347,6 +347,40 @@ static int snd_ctl_find_hole(struct snd_card *card, unsigned int count) return 0; } +/* add a new kcontrol object; call with card->controls_rwsem locked */ +static int __snd_ctl_add(struct snd_card *card, struct snd_kcontrol *kcontrol) +{ + struct snd_ctl_elem_id id; + unsigned int idx; + unsigned int count; + + id = kcontrol->id; + if (id.index > UINT_MAX - kcontrol->count) + return -EINVAL; + + if (snd_ctl_find_id(card, &id)) { + dev_err(card->dev, + "control %i:%i:%i:%s:%i is already present\n", + id.iface, id.device, id.subdevice, id.name, id.index); + return -EBUSY; + } + + if (snd_ctl_find_hole(card, kcontrol->count) < 0) + return -ENOMEM; + + list_add_tail(&kcontrol->list, &card->controls); + card->controls_count += kcontrol->count; + kcontrol->id.numid = card->last_numid + 1; + card->last_numid += kcontrol->count; + + id = kcontrol->id; + count = kcontrol->count; + for (idx = 0; idx < count; idx++, id.index++, id.numid++) + snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_ADD, &id); + + return 0; +} + /** * snd_ctl_add - add the control instance to the card * @card: the card instance @@ -363,45 +397,18 @@ static int snd_ctl_find_hole(struct snd_card *card, unsigned int count) */ int snd_ctl_add(struct snd_card *card, struct snd_kcontrol *kcontrol) { - struct snd_ctl_elem_id id; - unsigned int idx; - unsigned int count; int err = -EINVAL; if (! kcontrol) return err; if (snd_BUG_ON(!card || !kcontrol->info)) goto error; - id = kcontrol->id; - if (id.index > UINT_MAX - kcontrol->count) - goto error; down_write(&card->controls_rwsem); - if (snd_ctl_find_id(card, &id)) { - up_write(&card->controls_rwsem); - dev_err(card->dev, "control %i:%i:%i:%s:%i is already present\n", - id.iface, - id.device, - id.subdevice, - id.name, - id.index); - err = -EBUSY; - goto error; - } - if (snd_ctl_find_hole(card, kcontrol->count) < 0) { - up_write(&card->controls_rwsem); - err = -ENOMEM; - goto error; - } - list_add_tail(&kcontrol->list, &card->controls); - card->controls_count += kcontrol->count; - kcontrol->id.numid = card->last_numid + 1; - card->last_numid += kcontrol->count; - id = kcontrol->id; - count = kcontrol->count; + err = __snd_ctl_add(card, kcontrol); up_write(&card->controls_rwsem); - for (idx = 0; idx < count; idx++, id.index++, id.numid++) - snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_ADD, &id); + if (err < 0) + goto error; return 0; error: @@ -1360,9 +1367,12 @@ static int snd_ctl_elem_add(struct snd_ctl_file *file, kctl->tlv.c = snd_ctl_elem_user_tlv; /* This function manage to free the instance on failure. */ - err = snd_ctl_add(card, kctl); - if (err < 0) - return err; + down_write(&card->controls_rwsem); + err = __snd_ctl_add(card, kctl); + if (err < 0) { + snd_ctl_free_one(kctl); + goto unlock; + } offset = snd_ctl_get_ioff(kctl, &info->id); snd_ctl_build_ioff(&info->id, kctl, offset); /* @@ -1373,10 +1383,10 @@ static int snd_ctl_elem_add(struct snd_ctl_file *file, * which locks the element. */ - down_write(&card->controls_rwsem); card->user_ctl_count++; - up_write(&card->controls_rwsem); + unlock: + up_write(&card->controls_rwsem); return 0; } -- GitLab From 46663071adbc33e7b2a299b8e15bf36166101bcf Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 23 Nov 2018 18:18:30 +0100 Subject: [PATCH 0289/1286] ALSA: sparc: Fix invalid snd_free_pages() at error path commit 9a20332ab373b1f8f947e0a9c923652b32dab031 upstream. Some spurious calls of snd_free_pages() have been overlooked and remain in the error paths of sparc cs4231 driver code. Since runtime->dma_area is managed by the PCM core helper, we shouldn't release manually. Drop the superfluous calls. Reviewed-by: Takashi Sakamoto Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/sparc/cs4231.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/sound/sparc/cs4231.c b/sound/sparc/cs4231.c index e73c962590eb..079063d8038d 100644 --- a/sound/sparc/cs4231.c +++ b/sound/sparc/cs4231.c @@ -1146,10 +1146,8 @@ static int snd_cs4231_playback_open(struct snd_pcm_substream *substream) runtime->hw = snd_cs4231_playback; err = snd_cs4231_open(chip, CS4231_MODE_PLAY); - if (err < 0) { - snd_free_pages(runtime->dma_area, runtime->dma_bytes); + if (err < 0) return err; - } chip->playback_substream = substream; chip->p_periods_sent = 0; snd_pcm_set_sync(substream); @@ -1167,10 +1165,8 @@ static int snd_cs4231_capture_open(struct snd_pcm_substream *substream) runtime->hw = snd_cs4231_capture; err = snd_cs4231_open(chip, CS4231_MODE_RECORD); - if (err < 0) { - snd_free_pages(runtime->dma_area, runtime->dma_bytes); + if (err < 0) return err; - } chip->capture_substream = substream; chip->c_periods_sent = 0; snd_pcm_set_sync(substream); -- GitLab From e50476e9da270e1dfc742187aa1520ac4edb3a74 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Thu, 8 Nov 2018 16:36:15 +0800 Subject: [PATCH 0290/1286] ALSA: hda/realtek - Support ALC300 commit 1078bef0cd9291355a20369b21cd823026ab8eaa upstream. This patch will enable ALC300. [ It's almost equivalent with other ALC269-compatible ones, and apparently has no loopback mixer -- tiwai ] Signed-off-by: Kailang Yang Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index eb8807de3ebc..31c71ba3248e 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -343,6 +343,7 @@ static void alc_fill_eapd_coef(struct hda_codec *codec) case 0x10ec0285: case 0x10ec0298: case 0x10ec0289: + case 0x10ec0300: alc_update_coef_idx(codec, 0x10, 1<<9, 0); break; case 0x10ec0275: @@ -2758,6 +2759,7 @@ enum { ALC269_TYPE_ALC215, ALC269_TYPE_ALC225, ALC269_TYPE_ALC294, + ALC269_TYPE_ALC300, ALC269_TYPE_ALC700, }; @@ -2792,6 +2794,7 @@ static int alc269_parse_auto_config(struct hda_codec *codec) case ALC269_TYPE_ALC215: case ALC269_TYPE_ALC225: case ALC269_TYPE_ALC294: + case ALC269_TYPE_ALC300: case ALC269_TYPE_ALC700: ssids = alc269_ssids; break; @@ -7089,6 +7092,10 @@ static int patch_alc269(struct hda_codec *codec) spec->gen.mixer_nid = 0; /* ALC2x4 does not have any loopback mixer path */ alc_update_coef_idx(codec, 0x6b, 0x0018, (1<<4) | (1<<3)); /* UAJ MIC Vref control by verb */ break; + case 0x10ec0300: + spec->codec_variant = ALC269_TYPE_ALC300; + spec->gen.mixer_nid = 0; /* no loopback on ALC300 */ + break; case 0x10ec0700: case 0x10ec0701: case 0x10ec0703: @@ -8160,6 +8167,7 @@ static const struct hda_device_id snd_hda_id_realtek[] = { HDA_CODEC_ENTRY(0x10ec0295, "ALC295", patch_alc269), HDA_CODEC_ENTRY(0x10ec0298, "ALC298", patch_alc269), HDA_CODEC_ENTRY(0x10ec0299, "ALC299", patch_alc269), + HDA_CODEC_ENTRY(0x10ec0300, "ALC300", patch_alc269), HDA_CODEC_REV_ENTRY(0x10ec0861, 0x100340, "ALC660", patch_alc861), HDA_CODEC_ENTRY(0x10ec0660, "ALC660-VD", patch_alc861vd), HDA_CODEC_ENTRY(0x10ec0861, "ALC861", patch_alc861), -- GitLab From e2ec0cb4d09277730decd5e1a9c75fb18ccb7d7a Mon Sep 17 00:00:00 2001 From: Anisse Astier Date: Fri, 23 Nov 2018 17:59:11 +0100 Subject: [PATCH 0291/1286] ALSA: hda/realtek - fix headset mic detection for MSI MS-B171 commit 8cd65271f8e545ddeed10ecc2e417936bdff168e upstream. MSI Cubi N 8GL (MS-B171) needs the same fixup as its older model, the MS-B120, in order for the headset mic to be properly detected. They both use a single 3-way jack for both mic and headset with an ALC283 codec, with the same pins used. Cc: stable@vger.kernel.org Signed-off-by: Anisse Astier Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 31c71ba3248e..66b0a124beae 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -6411,6 +6411,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x144d, 0xc740, "Samsung Ativ book 8 (NP870Z5G)", ALC269_FIXUP_ATIV_BOOK_8), SND_PCI_QUIRK(0x1458, 0xfa53, "Gigabyte BXBT-2807", ALC283_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x1462, 0xb120, "MSI Cubi MS-B120", ALC283_FIXUP_HEADSET_MIC), + SND_PCI_QUIRK(0x1462, 0xb171, "Cubi N 8GL (MS-B171)", ALC283_FIXUP_HEADSET_MIC), SND_PCI_QUIRK(0x17aa, 0x1036, "Lenovo P520", ALC233_FIXUP_LENOVO_MULTI_CODECS), SND_PCI_QUIRK(0x17aa, 0x20f2, "Thinkpad SL410/510", ALC269_FIXUP_SKU_IGNORE), SND_PCI_QUIRK(0x17aa, 0x215e, "Thinkpad L512", ALC269_FIXUP_SKU_IGNORE), -- GitLab From 086d1f60f874829124ebeaf7d2223a414221ca3b Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Sun, 25 Nov 2018 08:58:02 +0800 Subject: [PATCH 0292/1286] ext2: fix potential use after free commit ecebf55d27a11538ea84aee0be643dd953f830d5 upstream. The function ext2_xattr_set calls brelse(bh) to drop the reference count of bh. After that, bh may be freed. However, following brelse(bh), it reads bh->b_data via macro HDR(bh). This may result in a use-after-free bug. This patch moves brelse(bh) after reading field. CC: stable@vger.kernel.org Signed-off-by: Pan Bian Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/ext2/xattr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ext2/xattr.c b/fs/ext2/xattr.c index 62d9a659a8ff..dd8f10db82e9 100644 --- a/fs/ext2/xattr.c +++ b/fs/ext2/xattr.c @@ -612,9 +612,9 @@ bad_block: ext2_error(sb, "ext2_xattr_set", } cleanup: - brelse(bh); if (!(bh && header == HDR(bh))) kfree(header); + brelse(bh); up_write(&EXT2_I(inode)->xattr_sem); return error; -- GitLab From 2a9443a9358031c6192c876f3e51e1fa00c4d497 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 18 Nov 2018 20:03:02 +0100 Subject: [PATCH 0293/1286] ARM: dts: rockchip: Remove @0 from the veyron memory node commit 672e60b72bbe7aace88721db55b380b6a51fb8f9 upstream. The Coreboot version on veyron ChromeOS devices seems to ignore memory@0 nodes when updating the available memory and instead inserts another memory node without the address. This leads to 4GB systems only ever be using 2GB as the memory@0 node takes precedence. So remove the @0 for veyron devices. Fixes: 0b639b815f15 ("ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards") Cc: stable@vger.kernel.org Reported-by: Heikki Lindholm Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/rk3288-veyron.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 6e5bd8974f22..679b839bb2eb 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -47,7 +47,11 @@ #include "rk3288.dtsi" / { - memory@0 { + /* + * The default coreboot on veyron devices ignores memory@0 nodes + * and would instead create another memory node. + */ + memory { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; -- GitLab From 7e572222d3c9d67581f5409d7dbaf1e0e7b8de19 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Tue, 27 Nov 2018 17:06:34 +0100 Subject: [PATCH 0294/1286] dmaengine: at_hdmac: fix memory leak in at_dma_xlate() commit 98f5f932254b88ce828bc8e4d1642d14e5854caa upstream. The leak was found when opening/closing a serial port a great number of time, increasing kmalloc-32 in slabinfo. Each time the port was opened, dma_request_slave_channel() was called. Then, in at_dma_xlate(), atslave was allocated with devm_kzalloc() and never freed. (Well, it was free at module unload, but that's not what we want). So, here, kzalloc is more suited for the job since it has to be freed in atc_free_chan_resources(). Cc: stable@vger.kernel.org Fixes: bbe89c8e3d59 ("at_hdmac: move to generic DMA binding") Reported-by: Mario Forner Suggested-by: Alexandre Belloni Acked-by: Alexandre Belloni Acked-by: Ludovic Desroches Signed-off-by: Richard Genoud Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/at_hdmac.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index a861b5b4d443..b87892a14ba9 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -1641,6 +1641,12 @@ static void atc_free_chan_resources(struct dma_chan *chan) atchan->descs_allocated = 0; atchan->status = 0; + /* + * Free atslave allocated in at_dma_xlate() + */ + kfree(chan->private); + chan->private = NULL; + dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); } @@ -1675,7 +1681,7 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL); + atslave = kzalloc(sizeof(*atslave), GFP_KERNEL); if (!atslave) return NULL; -- GitLab From 39c49a757d7c3e27d3bfabd1e102e9544372e103 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Tue, 27 Nov 2018 17:06:35 +0100 Subject: [PATCH 0295/1286] dmaengine: at_hdmac: fix module unloading commit 77e75fda94d2ebb86aa9d35fb1860f6395bf95de upstream. of_dma_controller_free() was not called on module onloading. This lead to a soft lockup: watchdog: BUG: soft lockup - CPU#0 stuck for 23s! Modules linked in: at_hdmac [last unloaded: at_hdmac] when of_dma_request_slave_channel() tried to call ofdma->of_dma_xlate(). Cc: stable@vger.kernel.org Fixes: bbe89c8e3d59 ("at_hdmac: move to generic DMA binding") Acked-by: Ludovic Desroches Signed-off-by: Richard Genoud Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/at_hdmac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index b87892a14ba9..21ed0e20c5d9 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -2006,6 +2006,8 @@ static int at_dma_remove(struct platform_device *pdev) struct resource *io; at_dma_off(atdma); + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&atdma->dma_common); dma_pool_destroy(atdma->memset_pool); -- GitLab From 85df1f9f8fb0c9c4801f5cc8ab1b25e77c1f06cd Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Mon, 3 Dec 2018 13:06:57 +0200 Subject: [PATCH 0296/1286] btrfs: release metadata before running delayed refs We want to release the unused reservation we have since it refills the delayed refs reserve, which will make everything go smoother when running the delayed refs if we're short on our reservation. CC: stable@vger.kernel.org # 4.4+ Reviewed-by: Omar Sandoval Reviewed-by: Liu Bo Reviewed-by: Nikolay Borisov Signed-off-by: Josef Bacik Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/transaction.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index f74005ca8f08..73c1fbca0c35 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c @@ -1955,6 +1955,9 @@ int btrfs_commit_transaction(struct btrfs_trans_handle *trans) return ret; } + btrfs_trans_release_metadata(trans, fs_info); + trans->block_rsv = NULL; + /* make a pass through all the delayed refs we have so far * any runnings procs may add more while we are here */ @@ -1964,9 +1967,6 @@ int btrfs_commit_transaction(struct btrfs_trans_handle *trans) return ret; } - btrfs_trans_release_metadata(trans, fs_info); - trans->block_rsv = NULL; - cur_trans = trans->transaction; /* -- GitLab From ca0908ddcd303d5e91982c6e5a91ad3d99cc99b6 Mon Sep 17 00:00:00 2001 From: Ben Wolsieffer Date: Sat, 3 Nov 2018 19:32:20 -0400 Subject: [PATCH 0297/1286] staging: vchiq_arm: fix compat VCHIQ_IOC_AWAIT_COMPLETION commit 5a96b2d38dc054c0bbcbcd585b116566cbd877fe upstream. The compatibility ioctl wrapper for VCHIQ_IOC_AWAIT_COMPLETION assumes that the native ioctl always uses a message buffer and decrements msgbufcount. Certain message types do not use a message buffer and in this case msgbufcount is not decremented, and completion->header for the message is NULL. Because the wrapper unconditionally decrements msgbufcount, the calling process may assume that a message buffer has been used even when it has not. This results in a memory leak in the userspace code that interfaces with this driver. When msgbufcount is decremented, the userspace code assumes that the buffer can be freed though the reference in completion->header, which cannot happen when the reference is NULL. This patch causes the wrapper to only decrement msgbufcount when the native ioctl decrements it. Note that we cannot simply copy the native ioctl's value of msgbufcount, because the wrapper only retrieves messages from the native ioctl one at a time, while userspace may request multiple messages. See https://github.com/raspberrypi/linux/pull/2703 for more discussion of this patch. Fixes: 5569a1260933 ("staging: vchiq_arm: Add compatibility wrappers for ioctls") Signed-off-by: Ben Wolsieffer Acked-by: Stefan Wahren Cc: stable Signed-off-by: Greg Kroah-Hartman --- .../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c index 314ffac50bb8..f05e9af4fe81 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c @@ -1461,6 +1461,7 @@ vchiq_compat_ioctl_await_completion(struct file *file, struct vchiq_await_completion32 args32; struct vchiq_completion_data32 completion32; unsigned int *msgbufcount32; + unsigned int msgbufcount_native; compat_uptr_t msgbuf32; void *msgbuf; void **msgbufptr; @@ -1572,7 +1573,11 @@ vchiq_compat_ioctl_await_completion(struct file *file, sizeof(completion32))) return -EFAULT; - args32.msgbufcount--; + if (get_user(msgbufcount_native, &args->msgbufcount)) + return -EFAULT; + + if (!msgbufcount_native) + args32.msgbufcount--; msgbufcount32 = &((struct vchiq_await_completion32 __user *)arg)->msgbufcount; -- GitLab From 74abe400e12b45f871c98c99f0f65521cc0c8ca6 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 8 Nov 2018 23:30:09 -0600 Subject: [PATCH 0298/1286] staging: rtl8723bs: Add missing return for cfg80211_rtw_get_station commit 8561fb31a1f9594e2807681f5c0721894e367f19 upstream. With Androidx86 8.1, wificond returns "failed to get nl80211_sta_info_tx_failed" and wificondControl returns "Invalid signal poll result from wificond". The fix is to OR sinfo->filled with BIT_ULL(NL80211_STA_INFO_TX_FAILED). This missing bit is apparently not needed with NetworkManager, but it does no harm in that case. Reported-and-Tested-by: youling257 Cc: linux-wireless@vger.kernel.org Cc: youling257 Signed-off-by: Larry Finger Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c index bd4352fe2de3..83852f323c5e 100644 --- a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c +++ b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c @@ -1293,7 +1293,7 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, sinfo->filled |= BIT(NL80211_STA_INFO_TX_PACKETS); sinfo->tx_packets = psta->sta_stats.tx_pkts; - + sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_FAILED); } /* for Ad-Hoc/AP mode */ -- GitLab From 403a2001bd795c43f59a5dd6695273fdfe0a3dcf Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Fri, 23 Nov 2018 08:42:19 +0000 Subject: [PATCH 0299/1286] USB: usb-storage: Add new IDs to ums-realtek commit a84a1bcc992f0545a51d2e120b8ca2ef20e2ea97 upstream. There are two new Realtek card readers require ums-realtek to work correctly. Add the new IDs to support them. Signed-off-by: Kai-Heng Feng Acked-by: Alan Stern Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/unusual_realtek.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/usb/storage/unusual_realtek.h b/drivers/usb/storage/unusual_realtek.h index 8fe624ad302a..7ca779493671 100644 --- a/drivers/usb/storage/unusual_realtek.h +++ b/drivers/usb/storage/unusual_realtek.h @@ -39,4 +39,14 @@ UNUSUAL_DEV(0x0bda, 0x0159, 0x0000, 0x9999, "USB Card Reader", USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0), +UNUSUAL_DEV(0x0bda, 0x0177, 0x0000, 0x9999, + "Realtek", + "USB Card Reader", + USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0), + +UNUSUAL_DEV(0x0bda, 0x0184, 0x0000, 0x9999, + "Realtek", + "USB Card Reader", + USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0), + #endif /* defined(CONFIG_USB_STORAGE_REALTEK) || ... */ -- GitLab From 2b7456f46ff957a3f04b3658a8d71b645d8cf172 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 25 Nov 2018 17:57:33 +0100 Subject: [PATCH 0300/1286] usb: core: quirks: add RESET_RESUME quirk for Cherry G230 Stream series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit effd14f66cc1ef6701a19c5a56e39c35f4d395a5 upstream. Cherry G230 Stream 2.0 (G85-231) and 3.0 (G85-232) need this quirk to function correctly. This fixes a but where double pressing numlock locks up the device completely with need to replug the keyboard. Signed-off-by: Michael Niewöhner Tested-by: Michael Niewöhner Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 1e8f68960014..808437c5ec49 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -64,6 +64,9 @@ static const struct usb_device_id usb_quirk_list[] = { /* Microsoft LifeCam-VX700 v2.0 */ { USB_DEVICE(0x045e, 0x0770), .driver_info = USB_QUIRK_RESET_RESUME }, + /* Cherry Stream G230 2.0 (G85-231) and 3.0 (G85-232) */ + { USB_DEVICE(0x046a, 0x0023), .driver_info = USB_QUIRK_RESET_RESUME }, + /* Logitech HD Pro Webcams C920, C920-C, C925e and C930e */ { USB_DEVICE(0x046d, 0x082d), .driver_info = USB_QUIRK_DELAY_INIT }, { USB_DEVICE(0x046d, 0x0841), .driver_info = USB_QUIRK_DELAY_INIT }, -- GitLab From f1a4876f0435dc43fc55f42bd30763de5e5ef9ec Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 19 Nov 2018 08:34:04 +0200 Subject: [PATCH 0301/1286] Revert "usb: dwc3: gadget: skip Set/Clear Halt when invalid" commit 38317f5c0f2faae5110854f36edad810f841d62f upstream. This reverts commit ffb80fc672c3a7b6afd0cefcb1524fb99917b2f3. Turns out that commit is wrong. Host controllers are allowed to use Clear Feature HALT as means to sync data toggle between host and periperal. Cc: Signed-off-by: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/gadget.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index ac8d619ff887..b8704c0678f9 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1511,9 +1511,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) unsigned transfer_in_flight; unsigned started; - if (dep->flags & DWC3_EP_STALL) - return 0; - if (dep->number > 1) trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); else @@ -1535,8 +1532,6 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) else dep->flags |= DWC3_EP_STALL; } else { - if (!(dep->flags & DWC3_EP_STALL)) - return 0; ret = dwc3_send_clear_stall_ep_cmd(dep); if (ret) -- GitLab From d08c62878fe2040e2cbc70554f86c54895a9f708 Mon Sep 17 00:00:00 2001 From: Martin Kelly Date: Sun, 28 Oct 2018 20:18:53 -0700 Subject: [PATCH 0302/1286] iio:st_magn: Fix enable device after trigger commit fe5192ac81ad0d4dfe1395d11f393f0513c15f7f upstream. Currently, we enable the device before we enable the device trigger. At high frequencies, this can cause interrupts that don't yet have a poll function associated with them and are thus treated as spurious. At high frequencies with level interrupts, this can even cause an interrupt storm of repeated spurious interrupts (~100,000 on my Beagleboard with the LSM9DS1 magnetometer). If these repeat too much, the interrupt will get disabled and the device will stop functioning. To prevent these problems, enable the device prior to enabling the device trigger, and disable the divec prior to disabling the trigger. This means there's no window of time during which the device creates interrupts but we have no trigger to answer them. Fixes: 90efe055629 ("iio: st_sensors: harden interrupt handling") Signed-off-by: Martin Kelly Tested-by: Denis Ciocca Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/magnetometer/st_magn_buffer.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/iio/magnetometer/st_magn_buffer.c b/drivers/iio/magnetometer/st_magn_buffer.c index 0a9e8fadfa9d..37ab30566464 100644 --- a/drivers/iio/magnetometer/st_magn_buffer.c +++ b/drivers/iio/magnetometer/st_magn_buffer.c @@ -30,11 +30,6 @@ int st_magn_trig_set_state(struct iio_trigger *trig, bool state) return st_sensors_set_dataready_irq(indio_dev, state); } -static int st_magn_buffer_preenable(struct iio_dev *indio_dev) -{ - return st_sensors_set_enable(indio_dev, true); -} - static int st_magn_buffer_postenable(struct iio_dev *indio_dev) { int err; @@ -50,7 +45,7 @@ static int st_magn_buffer_postenable(struct iio_dev *indio_dev) if (err < 0) goto st_magn_buffer_postenable_error; - return err; + return st_sensors_set_enable(indio_dev, true); st_magn_buffer_postenable_error: kfree(mdata->buffer_data); @@ -63,11 +58,11 @@ static int st_magn_buffer_predisable(struct iio_dev *indio_dev) int err; struct st_sensor_data *mdata = iio_priv(indio_dev); - err = iio_triggered_buffer_predisable(indio_dev); + err = st_sensors_set_enable(indio_dev, false); if (err < 0) goto st_magn_buffer_predisable_error; - err = st_sensors_set_enable(indio_dev, false); + err = iio_triggered_buffer_predisable(indio_dev); st_magn_buffer_predisable_error: kfree(mdata->buffer_data); @@ -75,7 +70,6 @@ static int st_magn_buffer_predisable(struct iio_dev *indio_dev) } static const struct iio_buffer_setup_ops st_magn_buffer_setup_ops = { - .preenable = &st_magn_buffer_preenable, .postenable = &st_magn_buffer_postenable, .predisable = &st_magn_buffer_predisable, }; -- GitLab From 397dbde6149057b4b84acb37012b57801fbc9221 Mon Sep 17 00:00:00 2001 From: Luis Chamberlain Date: Fri, 30 Nov 2018 14:09:21 -0800 Subject: [PATCH 0303/1286] lib/test_kmod.c: fix rmmod double free commit 5618cf031fecda63847cafd1091e7b8bd626cdb1 upstream. We free the misc device string twice on rmmod; fix this. Without this we cannot remove the module without crashing. Link: http://lkml.kernel.org/r/20181124050500.5257-1-mcgrof@kernel.org Signed-off-by: Luis Chamberlain Reported-by: Randy Dunlap Reviewed-by: Andrew Morton Cc: [4.12+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- lib/test_kmod.c | 1 - 1 file changed, 1 deletion(-) diff --git a/lib/test_kmod.c b/lib/test_kmod.c index 96c304fd656a..7abb59ce6613 100644 --- a/lib/test_kmod.c +++ b/lib/test_kmod.c @@ -1221,7 +1221,6 @@ void unregister_test_dev_kmod(struct kmod_test_device *test_dev) dev_info(test_dev->dev, "removing interface\n"); misc_deregister(&test_dev->misc_dev); - kfree(&test_dev->misc_dev.name); mutex_unlock(&test_dev->config_mutex); mutex_unlock(&test_dev->trigger_mutex); -- GitLab From 7c1ba1a1bb0d1a5dcebc737343f0c45840cf181d Mon Sep 17 00:00:00 2001 From: Yu Zhao Date: Fri, 30 Nov 2018 14:09:03 -0800 Subject: [PATCH 0304/1286] mm: use swp_offset as key in shmem_replace_page() commit c1cb20d43728aa9b5393bd8d489bc85c142949b2 upstream. We changed the key of swap cache tree from swp_entry_t.val to swp_offset. We need to do so in shmem_replace_page() as well. Hugh said: "shmem_replace_page() has been wrong since the day I wrote it: good enough to work on swap "type" 0, which is all most people ever use (especially those few who need shmem_replace_page() at all), but broken once there are any non-0 swp_type bits set in the higher order bits" Link: http://lkml.kernel.org/r/20181121215442.138545-1-yuzhao@google.com Fixes: f6ab1f7f6b2d ("mm, swap: use offset of swap entry as key of swap cache") Signed-off-by: Yu Zhao Reviewed-by: Matthew Wilcox Acked-by: Hugh Dickins Cc: [4.9+] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/shmem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/mm/shmem.c b/mm/shmem.c index 177fef62cbbd..ab7ff0aeae2d 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -1532,11 +1532,13 @@ static int shmem_replace_page(struct page **pagep, gfp_t gfp, { struct page *oldpage, *newpage; struct address_space *swap_mapping; + swp_entry_t entry; pgoff_t swap_index; int error; oldpage = *pagep; - swap_index = page_private(oldpage); + entry.val = page_private(oldpage); + swap_index = swp_offset(entry); swap_mapping = page_mapping(oldpage); /* @@ -1555,7 +1557,7 @@ static int shmem_replace_page(struct page **pagep, gfp_t gfp, __SetPageLocked(newpage); __SetPageSwapBacked(newpage); SetPageUptodate(newpage); - set_page_private(newpage, swap_index); + set_page_private(newpage, entry.val); SetPageSwapCache(newpage); /* -- GitLab From 3c44b197448dfb8bef4fa9cab92b7a73153a6f76 Mon Sep 17 00:00:00 2001 From: Dexuan Cui Date: Mon, 26 Nov 2018 02:29:56 +0000 Subject: [PATCH 0305/1286] Drivers: hv: vmbus: check the creation_status in vmbus_establish_gpadl() commit eceb05965489784f24bbf4d61ba60e475a983016 upstream. This is a longstanding issue: if the vmbus upper-layer drivers try to consume too many GPADLs, the host may return with an error 0xC0000044 (STATUS_QUOTA_EXCEEDED), but currently we forget to check the creation_status, and hence we can pass an invalid GPADL handle into the OPEN_CHANNEL message, and get an error code 0xc0000225 in open_info->response.open_result.status, and finally we hang in vmbus_open() -> "goto error_free_info" -> vmbus_teardown_gpadl(). With this patch, we can exit gracefully on STATUS_QUOTA_EXCEEDED. Cc: Stephen Hemminger Cc: K. Y. Srinivasan Cc: Haiyang Zhang Cc: stable@vger.kernel.org Signed-off-by: Dexuan Cui Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/hv/channel.c b/drivers/hv/channel.c index d96b09fea835..e05de5032f0c 100644 --- a/drivers/hv/channel.c +++ b/drivers/hv/channel.c @@ -454,6 +454,14 @@ int vmbus_establish_gpadl(struct vmbus_channel *channel, void *kbuffer, } wait_for_completion(&msginfo->waitevent); + if (msginfo->response.gpadl_created.creation_status != 0) { + pr_err("Failed to establish GPADL: err = 0x%x\n", + msginfo->response.gpadl_created.creation_status); + + ret = -EDQUOT; + goto cleanup; + } + if (channel->rescind) { ret = -ENODEV; goto cleanup; -- GitLab From f7d33988bd923310934c8481a2e68b53f716df13 Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Wed, 14 Nov 2018 01:57:03 +0000 Subject: [PATCH 0306/1286] misc: mic/scif: fix copy-paste error in scif_create_remote_lookup commit 6484a677294aa5d08c0210f2f387ebb9be646115 upstream. gcc '-Wunused-but-set-variable' warning: drivers/misc/mic/scif/scif_rma.c: In function 'scif_create_remote_lookup': drivers/misc/mic/scif/scif_rma.c:373:25: warning: variable 'vmalloc_num_pages' set but not used [-Wunused-but-set-variable] 'vmalloc_num_pages' should be used to determine if the address is within the vmalloc range. Fixes: ba612aa8b487 ("misc: mic: SCIF memory registration and unregistration") Signed-off-by: YueHaibing Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/misc/mic/scif/scif_rma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/mic/scif/scif_rma.c b/drivers/misc/mic/scif/scif_rma.c index 329727e00e97..95745dc4e0ec 100644 --- a/drivers/misc/mic/scif/scif_rma.c +++ b/drivers/misc/mic/scif/scif_rma.c @@ -417,7 +417,7 @@ static int scif_create_remote_lookup(struct scif_dev *remote_dev, if (err) goto error_window; err = scif_map_page(&window->num_pages_lookup.lookup[j], - vmalloc_dma_phys ? + vmalloc_num_pages ? vmalloc_to_page(&window->num_pages[i]) : virt_to_page(&window->num_pages[i]), remote_dev); -- GitLab From fd6cc33d0775b0d902906d88dd05cc1a2a059f8d Mon Sep 17 00:00:00 2001 From: Todd Kjos Date: Tue, 6 Nov 2018 15:55:32 -0800 Subject: [PATCH 0307/1286] binder: fix race that allows malicious free of live buffer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7bada55ab50697861eee6bb7d60b41e68a961a9c upstream. Malicious code can attempt to free buffers using the BC_FREE_BUFFER ioctl to binder. There are protections against a user freeing a buffer while in use by the kernel, however there was a window where BC_FREE_BUFFER could be used to free a recently allocated buffer that was not completely initialized. This resulted in a use-after-free detected by KASAN with a malicious test program. This window is closed by setting the buffer's allow_user_free attribute to 0 when the buffer is allocated or when the user has previously freed it instead of waiting for the caller to set it. The problem was that when the struct buffer was recycled, allow_user_free was stale and set to 1 allowing a free to go through. Signed-off-by: Todd Kjos Acked-by: Arve Hjønnevåg Cc: stable # 4.14 Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder.c | 21 ++++++++++++--------- drivers/android/binder_alloc.c | 14 ++++++-------- drivers/android/binder_alloc.h | 3 +-- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/android/binder.c b/drivers/android/binder.c index a86c27948fca..96a0f940e54d 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -2918,7 +2918,6 @@ static void binder_transaction(struct binder_proc *proc, t->buffer = NULL; goto err_binder_alloc_buf_failed; } - t->buffer->allow_user_free = 0; t->buffer->debug_id = t->debug_id; t->buffer->transaction = t; t->buffer->target_node = target_node; @@ -3407,14 +3406,18 @@ static int binder_thread_write(struct binder_proc *proc, buffer = binder_alloc_prepare_to_free(&proc->alloc, data_ptr); - if (buffer == NULL) { - binder_user_error("%d:%d BC_FREE_BUFFER u%016llx no match\n", - proc->pid, thread->pid, (u64)data_ptr); - break; - } - if (!buffer->allow_user_free) { - binder_user_error("%d:%d BC_FREE_BUFFER u%016llx matched unreturned buffer\n", - proc->pid, thread->pid, (u64)data_ptr); + if (IS_ERR_OR_NULL(buffer)) { + if (PTR_ERR(buffer) == -EPERM) { + binder_user_error( + "%d:%d BC_FREE_BUFFER u%016llx matched unreturned or currently freeing buffer\n", + proc->pid, thread->pid, + (u64)data_ptr); + } else { + binder_user_error( + "%d:%d BC_FREE_BUFFER u%016llx no match\n", + proc->pid, thread->pid, + (u64)data_ptr); + } break; } binder_debug(BINDER_DEBUG_FREE_BUFFER, diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index 58e4658f9dd6..b9281f2725a6 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -149,14 +149,12 @@ static struct binder_buffer *binder_alloc_prepare_to_free_locked( else { /* * Guard against user threads attempting to - * free the buffer twice + * free the buffer when in use by kernel or + * after it's already been freed. */ - if (buffer->free_in_progress) { - pr_err("%d:%d FREE_BUFFER u%016llx user freed buffer twice\n", - alloc->pid, current->pid, (u64)user_ptr); - return NULL; - } - buffer->free_in_progress = 1; + if (!buffer->allow_user_free) + return ERR_PTR(-EPERM); + buffer->allow_user_free = 0; return buffer; } } @@ -486,7 +484,7 @@ struct binder_buffer *binder_alloc_new_buf_locked(struct binder_alloc *alloc, rb_erase(best_fit, &alloc->free_buffers); buffer->free = 0; - buffer->free_in_progress = 0; + buffer->allow_user_free = 0; binder_insert_allocated_buffer_locked(alloc, buffer); binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC, "%d: binder_alloc_buf size %zd got %pK\n", diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index 2dd33b6df104..a3ad7683b6f2 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -50,8 +50,7 @@ struct binder_buffer { unsigned free:1; unsigned allow_user_free:1; unsigned async_transaction:1; - unsigned free_in_progress:1; - unsigned debug_id:28; + unsigned debug_id:29; struct binder_transaction *transaction; -- GitLab From 14118df4e7b4738815f222f5b20fceb3957ab206 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 27 Jul 2018 19:45:36 +0200 Subject: [PATCH 0308/1286] libceph: weaken sizeof check in ceph_x_verify_authorizer_reply() commit f1d10e04637924f2b00a0fecdd2ca4565f5cfc3f upstream. Allow for extending ceph_x_authorize_reply in the future. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Greg Kroah-Hartman --- net/ceph/auth_x.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/ceph/auth_x.c b/net/ceph/auth_x.c index 10eb759bbcb4..2bf9d9f7ddf3 100644 --- a/net/ceph/auth_x.c +++ b/net/ceph/auth_x.c @@ -737,8 +737,10 @@ static int ceph_x_verify_authorizer_reply(struct ceph_auth_client *ac, ret = ceph_x_decrypt(&au->session_key, &p, p + CEPHX_AU_ENC_BUF_LEN); if (ret < 0) return ret; - if (ret != sizeof(*reply)) - return -EPERM; + if (ret < sizeof(*reply)) { + pr_err("bad size %d for ceph_x_authorize_reply\n", ret); + return -EINVAL; + } if (au->nonce + 1 != le64_to_cpu(reply->nonce_plus_one)) ret = -EPERM; -- GitLab From 0c5f2e899241aceab46e6dcba01c6fb2223bdeb5 Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 27 Jul 2018 19:40:30 +0200 Subject: [PATCH 0309/1286] libceph: check authorizer reply/challenge length before reading commit 130f52f2b203aa0aec179341916ffb2e905f3afd upstream. Avoid scribbling over memory if the received reply/challenge is larger than the buffer supplied with the authorizer. Signed-off-by: Ilya Dryomov Reviewed-by: Sage Weil Signed-off-by: Greg Kroah-Hartman --- net/ceph/messenger.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index ad33baa2008d..f864807284d4 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -1754,6 +1754,13 @@ static int read_partial_connect(struct ceph_connection *con) if (con->auth) { size = le32_to_cpu(con->in_reply.authorizer_len); + if (size > con->auth->authorizer_reply_buf_len) { + pr_err("authorizer reply too big: %d > %zu\n", size, + con->auth->authorizer_reply_buf_len); + ret = -EINVAL; + goto out; + } + end += size; ret = read_partial(con, end, size, con->auth->authorizer_reply_buf); -- GitLab From 862e7aaa90f63b1e3e3ab498dc3a3ac9a011b8d0 Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Thu, 27 Sep 2018 22:15:31 -0700 Subject: [PATCH 0310/1286] f2fs: fix missing up_read commit 89d13c38501df730cbb2e02c4499da1b5187119d upstream. This patch fixes missing up_read call. Fixes: c9b60788fc76 ("f2fs: fix to do sanity check with block address in main area") Cc: # 4.19+ Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Greg Kroah-Hartman --- fs/f2fs/node.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 6adb6c60f017..65de72d65562 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -1399,8 +1399,10 @@ static int __write_node_page(struct page *page, bool atomic, bool *submitted, } if (__is_valid_data_blkaddr(ni.blk_addr) && - !f2fs_is_valid_blkaddr(sbi, ni.blk_addr, DATA_GENERIC)) + !f2fs_is_valid_blkaddr(sbi, ni.blk_addr, DATA_GENERIC)) { + up_read(&sbi->node_write); goto redirty_out; + } if (atomic && !test_opt(sbi, NOBARRIER)) fio.op_flags |= REQ_PREFLUSH | REQ_FUA; -- GitLab From 7152401aeedd9685fcf1cb58138c868890d9164f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 5 Dec 2018 19:41:27 +0100 Subject: [PATCH 0311/1286] Linux 4.14.86 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 58a248264090..572bd98d2344 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 85 +SUBLEVEL = 86 EXTRAVERSION = NAME = Petit Gorille -- GitLab From f5ec9987bfbd1004b643e2c914306dc79ce40912 Mon Sep 17 00:00:00 2001 From: Xiongfeng Wang Date: Thu, 11 Jan 2018 17:22:29 +0800 Subject: [PATCH 0312/1286] Kbuild: suppress packed-not-aligned warning for default setting only commit 321cb0308a9e76841394b4bbab6a1107cfedbae0 upstream. gcc-8 reports many -Wpacked-not-aligned warnings. The below are some examples. ./include/linux/ceph/msgr.h:67:1: warning: alignment 1 of 'struct ceph_entity_addr' is less than 8 [-Wpacked-not-aligned] } __attribute__ ((packed)); ./include/linux/ceph/msgr.h:67:1: warning: alignment 1 of 'struct ceph_entity_addr' is less than 8 [-Wpacked-not-aligned] } __attribute__ ((packed)); ./include/linux/ceph/msgr.h:67:1: warning: alignment 1 of 'struct ceph_entity_addr' is less than 8 [-Wpacked-not-aligned] } __attribute__ ((packed)); This patch suppresses this kind of warnings for default setting. Signed-off-by: Xiongfeng Wang Signed-off-by: Masahiro Yamada Signed-off-by: Greg Kroah-Hartman --- scripts/Makefile.extrawarn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn index c6ebf4239e64..8d5357053f86 100644 --- a/scripts/Makefile.extrawarn +++ b/scripts/Makefile.extrawarn @@ -11,6 +11,8 @@ # are not supported by all versions of the compiler # ========================================================================== +KBUILD_CFLAGS += $(call cc-disable-warning, packed-not-aligned) + ifeq ("$(origin W)", "command line") export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) endif @@ -26,6 +28,7 @@ warning-1 += -Wold-style-definition warning-1 += $(call cc-option, -Wmissing-include-dirs) warning-1 += $(call cc-option, -Wunused-but-set-variable) warning-1 += $(call cc-option, -Wunused-const-variable) +warning-1 += $(call cc-option, -Wpacked-not-aligned) warning-1 += $(call cc-disable-warning, missing-field-initializers) warning-1 += $(call cc-disable-warning, sign-compare) -- GitLab From 9f8d10971a2395359751487c517bf33e5d8f9e43 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Fri, 31 Aug 2018 07:47:28 +1000 Subject: [PATCH 0313/1286] disable stringop truncation warnings for now commit 217c3e0196758662aa0429863b09d1c13da1c5d6 upstream. They are too noisy Signed-off-by: Stephen Rothwell Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 572bd98d2344..77ffc1dc4e79 100644 --- a/Makefile +++ b/Makefile @@ -803,6 +803,9 @@ KBUILD_CFLAGS += $(call cc-option,-Wdeclaration-after-statement,) # disable pointer signed / unsigned warnings in gcc 4.0 KBUILD_CFLAGS += $(call cc-disable-warning, pointer-sign) +# disable stringop warnings in gcc 8+ +KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation) + # disable invalid "can't wrap" optimizations for signed / pointers KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow) -- GitLab From 337f2837c5b29c1587dd7efc4befc9f6f84a2746 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 30 Nov 2018 12:13:15 -0800 Subject: [PATCH 0314/1286] test_hexdump: use memcpy instead of strncpy commit b1286ed7158e9b62787508066283ab0b8850b518 upstream. New versions of gcc reasonably warn about the odd pattern of strncpy(p, q, strlen(q)); which really doesn't make sense: the strncpy() ends up being just a slow and odd way to write memcpy() in this case. Apparently there was a patch for this floating around earlier, but it got lost. Acked-again-by: Andy Shevchenko Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- lib/test_hexdump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/test_hexdump.c b/lib/test_hexdump.c index 3f415d8101f3..1c3c513add77 100644 --- a/lib/test_hexdump.c +++ b/lib/test_hexdump.c @@ -81,7 +81,7 @@ static void __init test_hexdump_prepare_test(size_t len, int rowsize, const char *q = *result++; size_t amount = strlen(q); - strncpy(p, q, amount); + memcpy(p, q, amount); p += amount; *p++ = ' '; -- GitLab From af882cb0bcb5573014e2203dbfd67e2737bb10d3 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Sun, 1 Jul 2018 13:57:16 -0700 Subject: [PATCH 0315/1286] kobject: Replace strncpy with memcpy commit 77d2a24b6107bd9b3bf2403a65c1428a9da83dd0 upstream. gcc 8.1.0 complains: lib/kobject.c:128:3: warning: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length [-Wstringop-truncation] lib/kobject.c: In function 'kobject_get_path': lib/kobject.c:125:13: note: length computed here Using strncpy() is indeed less than perfect since the length of data to be copied has already been determined with strlen(). Replace strncpy() with memcpy() to address the warning and optimize the code a little. Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- lib/kobject.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/kobject.c b/lib/kobject.c index 34f847252c02..bbbb067de8ec 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -127,7 +127,7 @@ static void fill_kobj_path(struct kobject *kobj, char *path, int length) int cur = strlen(kobject_name(parent)); /* back up enough to print this name with '/' */ length -= cur; - strncpy(path + length, kobject_name(parent), cur); + memcpy(path + length, kobject_name(parent), cur); *(path + --length) = '/'; } -- GitLab From 23df63002205f17d307af118fe0025f6e49d389a Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Wed, 27 Jun 2018 14:59:00 +0200 Subject: [PATCH 0316/1286] ALSA: intel_hdmi: Use strlcpy() instead of strncpy() commit c288248f5b26cd5563112fcdc077bf44964a942d upstream. hdmi_lpe_audio_probe() copies the pcm name string via strncpy(), but as a gcc8 warning suggests, it misses a NUL terminator, and unlikely the expected result. Use the proper one, strlcpy() instead. Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/x86/intel_hdmi_audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c index 697872d8308e..8b7abbd69116 100644 --- a/sound/x86/intel_hdmi_audio.c +++ b/sound/x86/intel_hdmi_audio.c @@ -1839,7 +1839,7 @@ static int hdmi_lpe_audio_probe(struct platform_device *pdev) /* setup private data which can be retrieved when required */ pcm->private_data = ctx; pcm->info_flags = 0; - strncpy(pcm->name, card->shortname, strlen(card->shortname)); + strlcpy(pcm->name, card->shortname, strlen(card->shortname)); /* setup the ops for playabck */ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); -- GitLab From f5028606c29248d39c8fba26730517c7c624cdaa Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 30 Nov 2018 14:45:01 -0800 Subject: [PATCH 0317/1286] unifdef: use memcpy instead of strncpy commit 38c7b224ce22c25fed04007839edf974bd13439d upstream. New versions of gcc reasonably warn about the odd pattern of strncpy(p, q, strlen(q)); which really doesn't make sense: the strncpy() ends up being just a slow and odd way to write memcpy() in this case. There was a comment about _why_ the code used strncpy - to avoid the terminating NUL byte, but memcpy does the same and avoids the warning. Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- scripts/unifdef.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/unifdef.c b/scripts/unifdef.c index 7493c0ee51cc..db00e3e30a59 100644 --- a/scripts/unifdef.c +++ b/scripts/unifdef.c @@ -395,7 +395,7 @@ usage(void) * When we have processed a group that starts off with a known-false * #if/#elif sequence (which has therefore been deleted) followed by a * #elif that we don't understand and therefore must keep, we edit the - * latter into a #if to keep the nesting correct. We use strncpy() to + * latter into a #if to keep the nesting correct. We use memcpy() to * overwrite the 4 byte token "elif" with "if " without a '\0' byte. * * When we find a true #elif in a group, the following block will @@ -450,7 +450,7 @@ static void Idrop (void) { Fdrop(); ignoreon(); } static void Itrue (void) { Ftrue(); ignoreon(); } static void Ifalse(void) { Ffalse(); ignoreon(); } /* modify this line */ -static void Mpass (void) { strncpy(keyword, "if ", 4); Pelif(); } +static void Mpass (void) { memcpy(keyword, "if ", 4); Pelif(); } static void Mtrue (void) { keywordedit("else"); state(IS_TRUE_MIDDLE); } static void Melif (void) { keywordedit("endif"); state(IS_FALSE_TRAILER); } static void Melse (void) { keywordedit("endif"); state(IS_FALSE_ELSE); } -- GitLab From e26457da0cdb5498724fd46279057d49c95cbba6 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Sun, 1 Jul 2018 13:57:13 -0700 Subject: [PATCH 0318/1286] kernfs: Replace strncpy with memcpy commit 166126c1e54d927c2e8efa2702d420e0ce301fd9 upstream. gcc 8.1.0 complains: fs/kernfs/symlink.c:91:3: warning: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length fs/kernfs/symlink.c: In function 'kernfs_iop_get_link': fs/kernfs/symlink.c:88:14: note: length computed here Using strncpy() is indeed less than perfect since the length of data to be copied has already been determined with strlen(). Replace strncpy() with memcpy() to address the warning and optimize the code a little. Signed-off-by: Guenter Roeck Acked-by: Tejun Heo Signed-off-by: Greg Kroah-Hartman --- fs/kernfs/symlink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/kernfs/symlink.c b/fs/kernfs/symlink.c index 08ccabd7047f..5145ae2f0572 100644 --- a/fs/kernfs/symlink.c +++ b/fs/kernfs/symlink.c @@ -88,7 +88,7 @@ static int kernfs_get_target_path(struct kernfs_node *parent, int slen = strlen(kn->name); len -= slen; - strncpy(s + len, kn->name, slen); + memcpy(s + len, kn->name, slen); if (len) s[--len] = '/'; -- GitLab From bb1d0ac3ef02d0e3e893b75933e556e86c915cfe Mon Sep 17 00:00:00 2001 From: Sultan Alsawaf Date: Wed, 6 Jun 2018 15:56:54 -0700 Subject: [PATCH 0319/1286] ip_tunnel: Fix name string concatenate in __ip_tunnel_create() commit 000ade8016400d93b4d7c89970d96b8c14773d45 upstream. By passing a limit of 2 bytes to strncat, strncat is limited to writing fewer bytes than what it's supposed to append to the name here. Since the bounds are checked on the line above this, just remove the string bounds checks entirely since they're unneeded. Signed-off-by: Sultan Alsawaf Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/ip_tunnel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index 72eee34092ae..fabc299cb875 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -261,8 +261,8 @@ static struct net_device *__ip_tunnel_create(struct net *net, } else { if (strlen(ops->kind) > (IFNAMSIZ - 3)) goto failed; - strlcpy(name, ops->kind, IFNAMSIZ); - strncat(name, "%d", 2); + strcpy(name, ops->kind); + strcat(name, "%d"); } ASSERT_RTNL(); -- GitLab From 4e4b875eaf1e615cdaa789c22222565405349145 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 Sep 2017 09:47:26 +0200 Subject: [PATCH 0320/1286] drm: gma500: fix logic error commit 67a3b63a54cbe18944191f43d644686731cf30c7 upstream. gcc-8 points out a condition that almost certainly doesn't do what the author had in mind: drivers/gpu/drm/gma500/mdfld_intel_display.c: In function 'mdfldWaitForPipeEnable': drivers/gpu/drm/gma500/mdfld_intel_display.c:102:37: error: bitwise comparison always evaluates to false [-Werror=tautological-compare] This changes it to a simple bit mask operation to check whether the bit is set. Fixes: 026abc333205 ("gma500: initial medfield merge") Signed-off-by: Arnd Bergmann Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170905074741.435324-1-arnd@arndb.de Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/gma500/mdfld_intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/gma500/mdfld_intel_display.c b/drivers/gpu/drm/gma500/mdfld_intel_display.c index 531e4450c000..5c066448be5b 100644 --- a/drivers/gpu/drm/gma500/mdfld_intel_display.c +++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c @@ -99,7 +99,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe) /* Wait for for the pipe enable to take effect. */ for (count = 0; count < COUNT_MAX; count++) { temp = REG_READ(map->conf); - if ((temp & PIPEACONF_PIPE_STATE) == 1) + if (temp & PIPEACONF_PIPE_STATE) break; } } -- GitLab From 94d6d9e5f3c2532c1f13521a58ac9f120f30c4ba Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 4 Dec 2017 15:47:00 +0100 Subject: [PATCH 0321/1286] scsi: bfa: convert to strlcpy/strlcat commit 8c5a50e8e7ad812a62f7ccf28d9a5e74fddf3000 upstream. The bfa driver has a number of real issues with string termination that gcc-8 now points out: drivers/scsi/bfa/bfad_bsg.c: In function 'bfad_iocmd_port_get_attr': drivers/scsi/bfa/bfad_bsg.c:320:9: error: argument to 'sizeof' in 'strncpy' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c: In function 'bfa_fcs_fabric_psymb_init': drivers/scsi/bfa/bfa_fcs.c:775:9: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:781:9: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:788:9: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:801:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:808:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c: In function 'bfa_fcs_fabric_nsymb_init': drivers/scsi/bfa/bfa_fcs.c:837:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:844:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c:852:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs.c: In function 'bfa_fcs_fabric_psymb_init': drivers/scsi/bfa/bfa_fcs.c:778:2: error: 'strncat' output may be truncated copying 10 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs.c:784:2: error: 'strncat' output may be truncated copying 30 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs.c:803:3: error: 'strncat' output may be truncated copying 44 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs.c:811:3: error: 'strncat' output may be truncated copying 16 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs.c: In function 'bfa_fcs_fabric_nsymb_init': drivers/scsi/bfa/bfa_fcs.c:840:2: error: 'strncat' output may be truncated copying 10 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs.c:847:2: error: 'strncat' output may be truncated copying 30 bytes from a string of length 63 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c: In function 'bfa_fcs_fdmi_get_hbaattr': drivers/scsi/bfa/bfa_fcs_lport.c:2657:10: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs_lport.c:2659:11: error: argument to 'sizeof' in 'strncat' call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] drivers/scsi/bfa/bfa_fcs_lport.c: In function 'bfa_fcs_lport_ms_gmal_response': drivers/scsi/bfa/bfa_fcs_lport.c:3232:5: error: 'strncpy' output may be truncated copying 16 bytes from a string of length 247 [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c: In function 'bfa_fcs_lport_ns_send_rspn_id': drivers/scsi/bfa/bfa_fcs_lport.c:4670:3: error: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c:4682:3: error: 'strncat' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c: In function 'bfa_fcs_lport_ns_util_send_rspn_id': drivers/scsi/bfa/bfa_fcs_lport.c:5206:3: error: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c:5215:3: error: 'strncat' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcs_lport.c: In function 'bfa_fcs_fdmi_get_portattr': drivers/scsi/bfa/bfa_fcs_lport.c:2751:2: error: 'strncpy' specified bound 128 equals destination size [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcbuild.c: In function 'fc_rspnid_build': drivers/scsi/bfa/bfa_fcbuild.c:1254:2: error: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] drivers/scsi/bfa/bfa_fcbuild.c:1253:25: note: length computed here drivers/scsi/bfa/bfa_fcbuild.c: In function 'fc_rsnn_nn_build': drivers/scsi/bfa/bfa_fcbuild.c:1275:2: error: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length [-Werror=stringop-truncation] In most cases, this can be addressed by correctly calling strlcpy and strlcat instead of strncpy/strncat, with the size of the destination buffer as the last argument. For consistency, I'm changing the other callers of strncpy() in this driver the same way. Signed-off-by: Arnd Bergmann Reviewed-by: Johannes Thumshirn Acked-by: Sudarsana Kalluru Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/bfa/bfa_fcbuild.c | 8 ++-- drivers/scsi/bfa/bfa_fcs.c | 78 ++++++++++++++++---------------- drivers/scsi/bfa/bfa_fcs_lport.c | 62 ++++++++++--------------- drivers/scsi/bfa/bfa_ioc.c | 2 +- drivers/scsi/bfa/bfa_svc.c | 4 +- drivers/scsi/bfa/bfad.c | 20 ++++---- drivers/scsi/bfa/bfad_attr.c | 2 +- drivers/scsi/bfa/bfad_bsg.c | 6 +-- 8 files changed, 84 insertions(+), 98 deletions(-) diff --git a/drivers/scsi/bfa/bfa_fcbuild.c b/drivers/scsi/bfa/bfa_fcbuild.c index b8dadc9cc993..d3b00a475aeb 100644 --- a/drivers/scsi/bfa/bfa_fcbuild.c +++ b/drivers/scsi/bfa/bfa_fcbuild.c @@ -1250,8 +1250,8 @@ fc_rspnid_build(struct fchs_s *fchs, void *pyld, u32 s_id, u16 ox_id, memset(rspnid, 0, sizeof(struct fcgs_rspnid_req_s)); rspnid->dap = s_id; - rspnid->spn_len = (u8) strlen((char *)name); - strncpy((char *)rspnid->spn, (char *)name, rspnid->spn_len); + strlcpy(rspnid->spn, name, sizeof(rspnid->spn)); + rspnid->spn_len = (u8) strlen(rspnid->spn); return sizeof(struct fcgs_rspnid_req_s) + sizeof(struct ct_hdr_s); } @@ -1271,8 +1271,8 @@ fc_rsnn_nn_build(struct fchs_s *fchs, void *pyld, u32 s_id, memset(rsnn_nn, 0, sizeof(struct fcgs_rsnn_nn_req_s)); rsnn_nn->node_name = node_name; - rsnn_nn->snn_len = (u8) strlen((char *)name); - strncpy((char *)rsnn_nn->snn, (char *)name, rsnn_nn->snn_len); + strlcpy(rsnn_nn->snn, name, sizeof(rsnn_nn->snn)); + rsnn_nn->snn_len = (u8) strlen(rsnn_nn->snn); return sizeof(struct fcgs_rsnn_nn_req_s) + sizeof(struct ct_hdr_s); } diff --git a/drivers/scsi/bfa/bfa_fcs.c b/drivers/scsi/bfa/bfa_fcs.c index 4aa61e20e82d..932feb0ed4da 100644 --- a/drivers/scsi/bfa/bfa_fcs.c +++ b/drivers/scsi/bfa/bfa_fcs.c @@ -769,23 +769,23 @@ bfa_fcs_fabric_psymb_init(struct bfa_fcs_fabric_s *fabric) bfa_ioc_get_adapter_model(&fabric->fcs->bfa->ioc, model); /* Model name/number */ - strncpy((char *)&port_cfg->sym_name, model, - BFA_FCS_PORT_SYMBNAME_MODEL_SZ); - strncat((char *)&port_cfg->sym_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + strlcpy(port_cfg->sym_name.symname, model, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, + BFA_SYMNAME_MAXLEN); /* Driver Version */ - strncat((char *)&port_cfg->sym_name, (char *)driver_info->version, - BFA_FCS_PORT_SYMBNAME_VERSION_SZ); - strncat((char *)&port_cfg->sym_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + strlcat(port_cfg->sym_name.symname, driver_info->version, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, + BFA_SYMNAME_MAXLEN); /* Host machine name */ - strncat((char *)&port_cfg->sym_name, - (char *)driver_info->host_machine_name, - BFA_FCS_PORT_SYMBNAME_MACHINENAME_SZ); - strncat((char *)&port_cfg->sym_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + strlcat(port_cfg->sym_name.symname, + driver_info->host_machine_name, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, + BFA_SYMNAME_MAXLEN); /* * Host OS Info : @@ -793,24 +793,24 @@ bfa_fcs_fabric_psymb_init(struct bfa_fcs_fabric_s *fabric) * OS name string and instead copy the entire OS info string (64 bytes). */ if (driver_info->host_os_patch[0] == '\0') { - strncat((char *)&port_cfg->sym_name, - (char *)driver_info->host_os_name, - BFA_FCS_OS_STR_LEN); - strncat((char *)&port_cfg->sym_name, + strlcat(port_cfg->sym_name.symname, + driver_info->host_os_name, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + BFA_SYMNAME_MAXLEN); } else { - strncat((char *)&port_cfg->sym_name, - (char *)driver_info->host_os_name, - BFA_FCS_PORT_SYMBNAME_OSINFO_SZ); - strncat((char *)&port_cfg->sym_name, + strlcat(port_cfg->sym_name.symname, + driver_info->host_os_name, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + BFA_SYMNAME_MAXLEN); /* Append host OS Patch Info */ - strncat((char *)&port_cfg->sym_name, - (char *)driver_info->host_os_patch, - BFA_FCS_PORT_SYMBNAME_OSPATCH_SZ); + strlcat(port_cfg->sym_name.symname, + driver_info->host_os_patch, + BFA_SYMNAME_MAXLEN); } /* null terminate */ @@ -830,26 +830,26 @@ bfa_fcs_fabric_nsymb_init(struct bfa_fcs_fabric_s *fabric) bfa_ioc_get_adapter_model(&fabric->fcs->bfa->ioc, model); /* Model name/number */ - strncpy((char *)&port_cfg->node_sym_name, model, - BFA_FCS_PORT_SYMBNAME_MODEL_SZ); - strncat((char *)&port_cfg->node_sym_name, + strlcpy(port_cfg->node_sym_name.symname, model, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->node_sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + BFA_SYMNAME_MAXLEN); /* Driver Version */ - strncat((char *)&port_cfg->node_sym_name, (char *)driver_info->version, - BFA_FCS_PORT_SYMBNAME_VERSION_SZ); - strncat((char *)&port_cfg->node_sym_name, + strlcat(port_cfg->node_sym_name.symname, (char *)driver_info->version, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->node_sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + BFA_SYMNAME_MAXLEN); /* Host machine name */ - strncat((char *)&port_cfg->node_sym_name, - (char *)driver_info->host_machine_name, - BFA_FCS_PORT_SYMBNAME_MACHINENAME_SZ); - strncat((char *)&port_cfg->node_sym_name, + strlcat(port_cfg->node_sym_name.symname, + driver_info->host_machine_name, + BFA_SYMNAME_MAXLEN); + strlcat(port_cfg->node_sym_name.symname, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); + BFA_SYMNAME_MAXLEN); /* null terminate */ port_cfg->node_sym_name.symname[BFA_SYMNAME_MAXLEN - 1] = 0; diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index 638c0a2857f7..b4f2c1d8742e 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -2642,10 +2642,10 @@ bfa_fcs_fdmi_get_hbaattr(struct bfa_fcs_lport_fdmi_s *fdmi, bfa_ioc_get_adapter_fw_ver(&port->fcs->bfa->ioc, hba_attr->fw_version); - strncpy(hba_attr->driver_version, (char *)driver_info->version, + strlcpy(hba_attr->driver_version, (char *)driver_info->version, sizeof(hba_attr->driver_version)); - strncpy(hba_attr->os_name, driver_info->host_os_name, + strlcpy(hba_attr->os_name, driver_info->host_os_name, sizeof(hba_attr->os_name)); /* @@ -2653,23 +2653,23 @@ bfa_fcs_fdmi_get_hbaattr(struct bfa_fcs_lport_fdmi_s *fdmi, * to the os name along with a separator */ if (driver_info->host_os_patch[0] != '\0') { - strncat(hba_attr->os_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, - sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); - strncat(hba_attr->os_name, driver_info->host_os_patch, - sizeof(driver_info->host_os_patch)); + strlcat(hba_attr->os_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, + sizeof(hba_attr->os_name)); + strlcat(hba_attr->os_name, driver_info->host_os_patch, + sizeof(hba_attr->os_name)); } /* Retrieve the max frame size from the port attr */ bfa_fcs_fdmi_get_portattr(fdmi, &fcs_port_attr); hba_attr->max_ct_pyld = fcs_port_attr.max_frm_size; - strncpy(hba_attr->node_sym_name.symname, + strlcpy(hba_attr->node_sym_name.symname, port->port_cfg.node_sym_name.symname, BFA_SYMNAME_MAXLEN); strcpy(hba_attr->vendor_info, "QLogic"); hba_attr->num_ports = cpu_to_be32(bfa_ioc_get_nports(&port->fcs->bfa->ioc)); hba_attr->fabric_name = port->fabric->lps->pr_nwwn; - strncpy(hba_attr->bios_ver, hba_attr->option_rom_ver, BFA_VERSION_LEN); + strlcpy(hba_attr->bios_ver, hba_attr->option_rom_ver, BFA_VERSION_LEN); } @@ -2736,20 +2736,20 @@ bfa_fcs_fdmi_get_portattr(struct bfa_fcs_lport_fdmi_s *fdmi, /* * OS device Name */ - strncpy(port_attr->os_device_name, (char *)driver_info->os_device_name, + strlcpy(port_attr->os_device_name, driver_info->os_device_name, sizeof(port_attr->os_device_name)); /* * Host name */ - strncpy(port_attr->host_name, (char *)driver_info->host_machine_name, + strlcpy(port_attr->host_name, driver_info->host_machine_name, sizeof(port_attr->host_name)); port_attr->node_name = bfa_fcs_lport_get_nwwn(port); port_attr->port_name = bfa_fcs_lport_get_pwwn(port); - strncpy(port_attr->port_sym_name.symname, - (char *)&bfa_fcs_lport_get_psym_name(port), BFA_SYMNAME_MAXLEN); + strlcpy(port_attr->port_sym_name.symname, + bfa_fcs_lport_get_psym_name(port).symname, BFA_SYMNAME_MAXLEN); bfa_fcs_lport_get_attr(port, &lport_attr); port_attr->port_type = cpu_to_be32(lport_attr.port_type); port_attr->scos = pport_attr.cos_supported; @@ -3229,7 +3229,7 @@ bfa_fcs_lport_ms_gmal_response(void *fcsarg, struct bfa_fcxp_s *fcxp, rsp_str[gmal_entry->len-1] = 0; /* copy IP Address to fabric */ - strncpy(bfa_fcs_lport_get_fabric_ipaddr(port), + strlcpy(bfa_fcs_lport_get_fabric_ipaddr(port), gmal_entry->ip_addr, BFA_FCS_FABRIC_IPADDR_SZ); break; @@ -4667,21 +4667,13 @@ bfa_fcs_lport_ns_send_rspn_id(void *ns_cbarg, struct bfa_fcxp_s *fcxp_alloced) * to that of the base port. */ - strncpy((char *)psymbl, - (char *) & - (bfa_fcs_lport_get_psym_name + strlcpy(symbl, + (char *)&(bfa_fcs_lport_get_psym_name (bfa_fcs_get_base_port(port->fcs))), - strlen((char *) & - bfa_fcs_lport_get_psym_name(bfa_fcs_get_base_port - (port->fcs)))); - - /* Ensure we have a null terminating string. */ - ((char *)psymbl)[strlen((char *) & - bfa_fcs_lport_get_psym_name(bfa_fcs_get_base_port - (port->fcs)))] = 0; - strncat((char *)psymbl, - (char *) &(bfa_fcs_lport_get_psym_name(port)), - strlen((char *) &bfa_fcs_lport_get_psym_name(port))); + sizeof(symbl)); + + strlcat(symbl, (char *)&(bfa_fcs_lport_get_psym_name(port)), + sizeof(symbl)); } else { psymbl = (u8 *) &(bfa_fcs_lport_get_psym_name(port)); } @@ -5173,7 +5165,6 @@ bfa_fcs_lport_ns_util_send_rspn_id(void *cbarg, struct bfa_fcxp_s *fcxp_alloced) struct fchs_s fchs; struct bfa_fcxp_s *fcxp; u8 symbl[256]; - u8 *psymbl = &symbl[0]; int len; /* Avoid sending RSPN in the following states. */ @@ -5203,22 +5194,17 @@ bfa_fcs_lport_ns_util_send_rspn_id(void *cbarg, struct bfa_fcxp_s *fcxp_alloced) * For Vports, we append the vport's port symbolic name * to that of the base port. */ - strncpy((char *)psymbl, (char *)&(bfa_fcs_lport_get_psym_name + strlcpy(symbl, (char *)&(bfa_fcs_lport_get_psym_name (bfa_fcs_get_base_port(port->fcs))), - strlen((char *)&bfa_fcs_lport_get_psym_name( - bfa_fcs_get_base_port(port->fcs)))); - - /* Ensure we have a null terminating string. */ - ((char *)psymbl)[strlen((char *)&bfa_fcs_lport_get_psym_name( - bfa_fcs_get_base_port(port->fcs)))] = 0; + sizeof(symbl)); - strncat((char *)psymbl, + strlcat(symbl, (char *)&(bfa_fcs_lport_get_psym_name(port)), - strlen((char *)&bfa_fcs_lport_get_psym_name(port))); + sizeof(symbl)); } len = fc_rspnid_build(&fchs, bfa_fcxp_get_reqbuf(fcxp), - bfa_fcs_lport_get_fcid(port), 0, psymbl); + bfa_fcs_lport_get_fcid(port), 0, symbl); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, NULL, NULL, FC_MAX_PDUSZ, 0); diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 256f4afaccf9..a1a183ece093 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -2803,7 +2803,7 @@ void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc, char *manufacturer) { memset((void *)manufacturer, 0, BFA_ADAPTER_MFG_NAME_LEN); - strncpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN); + strlcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN); } void diff --git a/drivers/scsi/bfa/bfa_svc.c b/drivers/scsi/bfa/bfa_svc.c index e640223bab3c..7356fdec79f5 100644 --- a/drivers/scsi/bfa/bfa_svc.c +++ b/drivers/scsi/bfa/bfa_svc.c @@ -350,8 +350,8 @@ bfa_plog_str(struct bfa_plog_s *plog, enum bfa_plog_mid mid, lp.eid = event; lp.log_type = BFA_PL_LOG_TYPE_STRING; lp.misc = misc; - strncpy(lp.log_entry.string_log, log_str, - BFA_PL_STRING_LOG_SZ - 1); + strlcpy(lp.log_entry.string_log, log_str, + BFA_PL_STRING_LOG_SZ); lp.log_entry.string_log[BFA_PL_STRING_LOG_SZ - 1] = '\0'; bfa_plog_add(plog, &lp); } diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 5caf5f3ff642..ae37010af50f 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -983,20 +983,20 @@ bfad_start_ops(struct bfad_s *bfad) { /* Fill the driver_info info to fcs*/ memset(&driver_info, 0, sizeof(driver_info)); - strncpy(driver_info.version, BFAD_DRIVER_VERSION, - sizeof(driver_info.version) - 1); + strlcpy(driver_info.version, BFAD_DRIVER_VERSION, + sizeof(driver_info.version)); if (host_name) - strncpy(driver_info.host_machine_name, host_name, - sizeof(driver_info.host_machine_name) - 1); + strlcpy(driver_info.host_machine_name, host_name, + sizeof(driver_info.host_machine_name)); if (os_name) - strncpy(driver_info.host_os_name, os_name, - sizeof(driver_info.host_os_name) - 1); + strlcpy(driver_info.host_os_name, os_name, + sizeof(driver_info.host_os_name)); if (os_patch) - strncpy(driver_info.host_os_patch, os_patch, - sizeof(driver_info.host_os_patch) - 1); + strlcpy(driver_info.host_os_patch, os_patch, + sizeof(driver_info.host_os_patch)); - strncpy(driver_info.os_device_name, bfad->pci_name, - sizeof(driver_info.os_device_name) - 1); + strlcpy(driver_info.os_device_name, bfad->pci_name, + sizeof(driver_info.os_device_name)); /* FCS driver info init */ spin_lock_irqsave(&bfad->bfad_lock, flags); diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c index 13db3b7bc873..d0a504af5b4f 100644 --- a/drivers/scsi/bfa/bfad_attr.c +++ b/drivers/scsi/bfa/bfad_attr.c @@ -843,7 +843,7 @@ bfad_im_symbolic_name_show(struct device *dev, struct device_attribute *attr, char symname[BFA_SYMNAME_MAXLEN]; bfa_fcs_lport_get_attr(&bfad->bfa_fcs.fabric.bport, &port_attr); - strncpy(symname, port_attr.port_cfg.sym_name.symname, + strlcpy(symname, port_attr.port_cfg.sym_name.symname, BFA_SYMNAME_MAXLEN); return snprintf(buf, PAGE_SIZE, "%s\n", symname); } diff --git a/drivers/scsi/bfa/bfad_bsg.c b/drivers/scsi/bfa/bfad_bsg.c index 1aa46d0763a0..9081a5f93aae 100644 --- a/drivers/scsi/bfa/bfad_bsg.c +++ b/drivers/scsi/bfa/bfad_bsg.c @@ -127,7 +127,7 @@ bfad_iocmd_ioc_get_attr(struct bfad_s *bfad, void *cmd) /* fill in driver attr info */ strcpy(iocmd->ioc_attr.driver_attr.driver, BFAD_DRIVER_NAME); - strncpy(iocmd->ioc_attr.driver_attr.driver_ver, + strlcpy(iocmd->ioc_attr.driver_attr.driver_ver, BFAD_DRIVER_VERSION, BFA_VERSION_LEN); strcpy(iocmd->ioc_attr.driver_attr.fw_ver, iocmd->ioc_attr.adapter_attr.fw_ver); @@ -315,9 +315,9 @@ bfad_iocmd_port_get_attr(struct bfad_s *bfad, void *cmd) iocmd->attr.port_type = port_attr.port_type; iocmd->attr.loopback = port_attr.loopback; iocmd->attr.authfail = port_attr.authfail; - strncpy(iocmd->attr.port_symname.symname, + strlcpy(iocmd->attr.port_symname.symname, port_attr.port_cfg.sym_name.symname, - sizeof(port_attr.port_cfg.sym_name.symname)); + sizeof(iocmd->attr.port_symname.symname)); iocmd->status = BFA_STATUS_OK; return 0; -- GitLab From 46762a64c0b03fc9cab3406bf2b3bbea043cf6e8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 Sep 2017 09:33:32 +0200 Subject: [PATCH 0322/1286] staging: rts5208: fix gcc-8 logic error warning commit 58930cced012adb01bc78b3687049b17ef44d0a3 upstream. As gcc-8 points out, the bit mask check makes no sense here: drivers/staging/rts5208/sd.c: In function 'ext_sd_send_cmd_get_rsp': drivers/staging/rts5208/sd.c:4130:25: error: bitwise comparison always evaluates to true [-Werror=tautological-compare] However, the code is even more bogus, as we have already checked for the SD_RSP_TYPE_R0 case earlier in the function and returned success. As seen in the mmc/sd driver core, SD_RSP_TYPE_R0 means "no response" anyway, so checking for a particular response would not help either. This just removes the nonsensical code to get rid of the warning. Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rts5208/sd.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/staging/rts5208/sd.c b/drivers/staging/rts5208/sd.c index d98d5fe25a17..0421dd9277a8 100644 --- a/drivers/staging/rts5208/sd.c +++ b/drivers/staging/rts5208/sd.c @@ -4125,12 +4125,6 @@ int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg, rtsx_trace(chip); return STATUS_FAIL; } - - } else if (rsp_type == SD_RSP_TYPE_R0) { - if ((ptr[3] & 0x1E) != 0x03) { - rtsx_trace(chip); - return STATUS_FAIL; - } } } } -- GitLab From 184adf40d184ff2761923e7f2f64a12702843ad8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 2 Feb 2018 15:59:40 +0100 Subject: [PATCH 0323/1286] kdb: use memmove instead of overlapping memcpy commit 2cf2f0d5b91fd1b06a6ae260462fc7945ea84add upstream. gcc discovered that the memcpy() arguments in kdbnearsym() overlap, so we should really use memmove(), which is defined to handle that correctly: In function 'memcpy', inlined from 'kdbnearsym' at /git/arm-soc/kernel/debug/kdb/kdb_support.c:132:4: /git/arm-soc/include/linux/string.h:353:9: error: '__builtin_memcpy' accessing 792 bytes at offsets 0 and 8 overlaps 784 bytes at offset 8 [-Werror=restrict] return __builtin_memcpy(p, q, size); Signed-off-by: Arnd Bergmann Signed-off-by: Jason Wessel Signed-off-by: Greg Kroah-Hartman --- kernel/debug/kdb/kdb_support.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/debug/kdb/kdb_support.c b/kernel/debug/kdb/kdb_support.c index 014f6fbb3832..b14b0925c184 100644 --- a/kernel/debug/kdb/kdb_support.c +++ b/kernel/debug/kdb/kdb_support.c @@ -129,13 +129,13 @@ int kdbnearsym(unsigned long addr, kdb_symtab_t *symtab) } if (i >= ARRAY_SIZE(kdb_name_table)) { debug_kfree(kdb_name_table[0]); - memcpy(kdb_name_table, kdb_name_table+1, + memmove(kdb_name_table, kdb_name_table+1, sizeof(kdb_name_table[0]) * (ARRAY_SIZE(kdb_name_table)-1)); } else { debug_kfree(knt1); knt1 = kdb_name_table[i]; - memcpy(kdb_name_table+i, kdb_name_table+i+1, + memmove(kdb_name_table+i, kdb_name_table+i+1, sizeof(kdb_name_table[0]) * (ARRAY_SIZE(kdb_name_table)-i-1)); } -- GitLab From 48c11537ee6d6731d1e24343150e41057f593a8b Mon Sep 17 00:00:00 2001 From: Sagi Grimberg Date: Wed, 14 Nov 2018 10:17:01 -0800 Subject: [PATCH 0324/1286] iser: set sector for ambiguous mr status errors commit 24c3456c8d5ee6fc1933ca40f7b4406130682668 upstream. If for some reason we failed to query the mr status, we need to make sure to provide sufficient information for an ambiguous error (guard error on sector 0). Fixes: 0a7a08ad6f5f ("IB/iser: Implement check_protection") Cc: Reported-by: Dan Carpenter Signed-off-by: Sagi Grimberg Signed-off-by: Jason Gunthorpe Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/ulp/iser/iser_verbs.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c index 55a73b0ed4c6..e28a5d713d1a 100644 --- a/drivers/infiniband/ulp/iser/iser_verbs.c +++ b/drivers/infiniband/ulp/iser/iser_verbs.c @@ -1108,7 +1108,9 @@ u8 iser_check_task_pi_status(struct iscsi_iser_task *iser_task, IB_MR_CHECK_SIG_STATUS, &mr_status); if (ret) { pr_err("ib_check_mr_status failed, ret %d\n", ret); - goto err; + /* Not a lot we can do, return ambiguous guard error */ + *sector = 0; + return 0x1; } if (mr_status.fail_status & IB_MR_CHECK_SIG_STATUS) { @@ -1136,9 +1138,6 @@ u8 iser_check_task_pi_status(struct iscsi_iser_task *iser_task, } return 0; -err: - /* Not alot we can do here, return ambiguous guard error */ - return 0x1; } void iser_err_comp(struct ib_wc *wc, const char *type) -- GitLab From 8d3ab1ccc063e618ef1a2711e9da9ce9e7d27396 Mon Sep 17 00:00:00 2001 From: Andrea Parri Date: Thu, 22 Nov 2018 17:10:31 +0100 Subject: [PATCH 0325/1286] uprobes: Fix handle_swbp() vs. unregister() + register() race once more commit 09d3f015d1e1b4fee7e9bbdcf54201d239393391 upstream. Commit: 142b18ddc8143 ("uprobes: Fix handle_swbp() vs unregister() + register() race") added the UPROBE_COPY_INSN flag, and corresponding smp_wmb() and smp_rmb() memory barriers, to ensure that handle_swbp() uses fully-initialized uprobes only. However, the smp_rmb() is mis-placed: this barrier should be placed after handle_swbp() has tested for the flag, thus guaranteeing that (program-order) subsequent loads from the uprobe can see the initial stores performed by prepare_uprobe(). Move the smp_rmb() accordingly. Also amend the comments associated to the two memory barriers to indicate their actual locations. Signed-off-by: Andrea Parri Acked-by: Oleg Nesterov Cc: Alexander Shishkin Cc: Andrew Morton Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Paul E. McKenney Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: stable@kernel.org Fixes: 142b18ddc8143 ("uprobes: Fix handle_swbp() vs unregister() + register() race") Link: http://lkml.kernel.org/r/20181122161031.15179-1-andrea.parri@amarulasolutions.com Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- kernel/events/uprobes.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 267f6ef91d97..01941cffa9c2 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -616,7 +616,7 @@ static int prepare_uprobe(struct uprobe *uprobe, struct file *file, BUG_ON((uprobe->offset & ~PAGE_MASK) + UPROBE_SWBP_INSN_SIZE > PAGE_SIZE); - smp_wmb(); /* pairs with rmb() in find_active_uprobe() */ + smp_wmb(); /* pairs with the smp_rmb() in handle_swbp() */ set_bit(UPROBE_COPY_INSN, &uprobe->flags); out: @@ -1910,10 +1910,18 @@ static void handle_swbp(struct pt_regs *regs) * After we hit the bp, _unregister + _register can install the * new and not-yet-analyzed uprobe at the same address, restart. */ - smp_rmb(); /* pairs with wmb() in install_breakpoint() */ if (unlikely(!test_bit(UPROBE_COPY_INSN, &uprobe->flags))) goto out; + /* + * Pairs with the smp_wmb() in prepare_uprobe(). + * + * Guarantees that if we see the UPROBE_COPY_INSN bit set, then + * we must also see the stores to &uprobe->arch performed by the + * prepare_uprobe() call. + */ + smp_rmb(); + /* Tracing handlers use ->utask to communicate with fetch methods */ if (!get_utask()) goto out; -- GitLab From 9aab50aec56772ff6e1a2dead6097cf2921fe944 Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Mon, 26 Nov 2018 11:25:40 +0100 Subject: [PATCH 0326/1286] MIPS: ralink: Fix mt7620 nd_sd pinmux commit 7d35baa4e9ec4b717bc0e58a39cdb6a1c50f5465 upstream. In case the nd_sd group is set to the sd-card function, Pins 45 + 46 are configured as GPIOs. If they are blocked by the sd function, they can't be used as GPIOs. Reported-by: Kristian Evensen Signed-off-by: Mathias Kresin Signed-off-by: Paul Burton Fixes: f576fb6a0700 ("MIPS: ralink: cleanup the soc specific pinmux data") Patchwork: https://patchwork.linux-mips.org/patch/21220/ Cc: John Crispin Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: Greg Kroah-Hartman --- arch/mips/ralink/mt7620.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 41b71c4352c2..c1ce6f43642b 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -84,7 +84,7 @@ static struct rt2880_pmx_func pcie_rst_grp[] = { }; static struct rt2880_pmx_func nd_sd_grp[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), - FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15) + FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; static struct rt2880_pmx_group mt7620a_pinmux_data[] = { -- GitLab From d3c0999433352dacda6da37c237388bfa9bae1c2 Mon Sep 17 00:00:00 2001 From: "Dmitry V. Levin" Date: Wed, 21 Nov 2018 22:14:39 +0300 Subject: [PATCH 0327/1286] mips: fix mips_get_syscall_arg o32 check commit c50cbd85cd7027d32ac5945bb60217936b4f7eaf upstream. When checking for TIF_32BIT_REGS flag, mips_get_syscall_arg() should use the task specified as its argument instead of the current task. This potentially affects all syscall_get_arguments() users who specify tasks different from the current. Fixes: c0ff3c53d4f99 ("MIPS: Enable HAVE_ARCH_TRACEHOOK.") Signed-off-by: Dmitry V. Levin Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/21185/ Cc: Elvira Khabirova Cc: Ralf Baechle Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v3.13+ Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/syscall.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h index 7c713025b23f..53ee82b1efa7 100644 --- a/arch/mips/include/asm/syscall.h +++ b/arch/mips/include/asm/syscall.h @@ -51,7 +51,7 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg, #ifdef CONFIG_64BIT case 4: case 5: case 6: case 7: #ifdef CONFIG_MIPS32_O32 - if (test_thread_flag(TIF_32BIT_REGS)) + if (test_tsk_thread_flag(task, TIF_32BIT_REGS)) return get_user(*arg, (int *)usp + n); else #endif -- GitLab From 53f6341a937be3dad213f5f4b2e188012c024ed2 Mon Sep 17 00:00:00 2001 From: Michael Guralnik Date: Wed, 21 Nov 2018 15:03:54 +0200 Subject: [PATCH 0328/1286] IB/mlx5: Avoid load failure due to unknown link width commit db7a691a1551a748cb92d9c89c6b190ea87e28d5 upstream. If the firmware reports a connection width that is not 1x, 4x, 8x or 12x it causes the driver to fail during initialization. To prevent this failure every time a new width is introduced to the RDMA stack, we will set a default 4x width for these widths which ar unknown to the driver. This is needed to allow to run old kernels with new firmware. Cc: # 4.1 Fixes: 1b5daf11b015 ("IB/mlx5: Avoid using the MAD_IFC command under ISSI > 0 mode") Signed-off-by: Michael Guralnik Reviewed-by: Majd Dibbiny Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/mlx5/main.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index c3a4f5d92391..13a92062e9ca 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -869,31 +869,26 @@ enum mlx5_ib_width { MLX5_IB_WIDTH_12X = 1 << 4 }; -static int translate_active_width(struct ib_device *ibdev, u8 active_width, +static void translate_active_width(struct ib_device *ibdev, u8 active_width, u8 *ib_width) { struct mlx5_ib_dev *dev = to_mdev(ibdev); - int err = 0; - if (active_width & MLX5_IB_WIDTH_1X) { + if (active_width & MLX5_IB_WIDTH_1X) *ib_width = IB_WIDTH_1X; - } else if (active_width & MLX5_IB_WIDTH_2X) { - mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", - (int)active_width); - err = -EINVAL; - } else if (active_width & MLX5_IB_WIDTH_4X) { + else if (active_width & MLX5_IB_WIDTH_4X) *ib_width = IB_WIDTH_4X; - } else if (active_width & MLX5_IB_WIDTH_8X) { + else if (active_width & MLX5_IB_WIDTH_8X) *ib_width = IB_WIDTH_8X; - } else if (active_width & MLX5_IB_WIDTH_12X) { + else if (active_width & MLX5_IB_WIDTH_12X) *ib_width = IB_WIDTH_12X; - } else { - mlx5_ib_dbg(dev, "Invalid active_width %d\n", + else { + mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", (int)active_width); - err = -EINVAL; + *ib_width = IB_WIDTH_4X; } - return err; + return; } static int mlx5_mtu_to_ib_mtu(int mtu) @@ -1001,10 +996,8 @@ static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, if (err) goto out; - err = translate_active_width(ibdev, ib_link_width_oper, - &props->active_width); - if (err) - goto out; + translate_active_width(ibdev, ib_link_width_oper, &props->active_width); + err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); if (err) goto out; -- GitLab From 37b927309286a4e4f9bf13aa2f7dbdd001637346 Mon Sep 17 00:00:00 2001 From: Sam Bobroff Date: Mon, 5 Nov 2018 16:57:47 +1100 Subject: [PATCH 0329/1286] drm/ast: Fix incorrect free on ioregs commit dc25ab067645eabd037f1a23d49a666f9e0b8c68 upstream. If the platform has no IO space, ioregs is placed next to the already allocated regs. In this case, it should not be separately freed. This prevents a kernel warning from __vunmap "Trying to vfree() nonexistent vm area" when unloading the driver. Fixes: 0dd68309b9c5 ("drm/ast: Try to use MMIO registers when PIO isn't supported") Signed-off-by: Sam Bobroff Cc: Signed-off-by: Dave Airlie Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/ast/ast_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index dac355812adc..373700c05a00 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -583,7 +583,8 @@ void ast_driver_unload(struct drm_device *dev) drm_mode_config_cleanup(dev); ast_mm_fini(ast); - pci_iounmap(dev->pdev, ast->ioregs); + if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET) + pci_iounmap(dev->pdev, ast->ioregs); pci_iounmap(dev->pdev, ast->regs); kfree(ast); } -- GitLab From 4e97ad08e1e3f4e9dbd5884b1dd7c4fdbe038eb1 Mon Sep 17 00:00:00 2001 From: Sergio Correia Date: Thu, 22 Nov 2018 02:33:29 -0300 Subject: [PATCH 0330/1286] drm: set is_master to 0 upon drm_new_set_master() failure commit 23a336b34258aba3b50ea6863cca4e81b5ef6384 upstream. When drm_new_set_master() fails, set is_master to 0, to prevent a possible NULL pointer deref. Here is a problematic flow: we check is_master in drm_is_current_master(), then proceed to call drm_lease_owner() passing master. If we do not restore is_master status when drm_new_set_master() fails, we may have a situation in which is_master will be 1 and master itself, NULL, leading to the deref of a NULL pointer in drm_lease_owner(). This fixes the following OOPS, observed on an ArchLinux running a 4.19.2 kernel: [ 97.804282] BUG: unable to handle kernel NULL pointer dereference at 0000000000000080 [ 97.807224] PGD 0 P4D 0 [ 97.807224] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 97.807224] CPU: 0 PID: 1348 Comm: xfwm4 Tainted: P OE 4.19.2-arch1-1-ARCH #1 [ 97.807224] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./AB350 Pro4, BIOS P5.10 10/16/2018 [ 97.807224] RIP: 0010:drm_lease_owner+0xd/0x20 [drm] [ 97.807224] Code: 83 c4 18 5b 5d c3 b8 ea ff ff ff eb e2 b8 ed ff ff ff eb db e8 b4 ca 68 fb 0f 1f 40 00 0f 1f 44 00 00 48 89 f8 eb 03 48 89 d0 <48> 8b 90 80 00 00 00 48 85 d2 75 f1 c3 66 0f 1f 44 00 00 0f 1f 44 [ 97.807224] RSP: 0018:ffffb8cf08e07bb0 EFLAGS: 00010202 [ 97.807224] RAX: 0000000000000000 RBX: ffff9cf0f2586c00 RCX: ffff9cf0f2586c88 [ 97.807224] RDX: ffff9cf0ddbd8000 RSI: 0000000000000000 RDI: 0000000000000000 [ 97.807224] RBP: ffff9cf1040e9800 R08: 0000000000000000 R09: 0000000000000000 [ 97.807224] R10: ffffdeb30fd5d680 R11: ffffdeb30f5d6808 R12: ffff9cf1040e9888 [ 97.807224] R13: 0000000000000000 R14: dead000000000200 R15: ffff9cf0f2586cc8 [ 97.807224] FS: 00007f4145513180(0000) GS:ffff9cf10ea00000(0000) knlGS:0000000000000000 [ 97.807224] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 97.807224] CR2: 0000000000000080 CR3: 00000003d7548000 CR4: 00000000003406f0 [ 97.807224] Call Trace: [ 97.807224] drm_is_current_master+0x1a/0x30 [drm] [ 97.807224] drm_master_release+0x3e/0x130 [drm] [ 97.807224] drm_file_free.part.0+0x2be/0x2d0 [drm] [ 97.807224] drm_open+0x1ba/0x1e0 [drm] [ 97.807224] drm_stub_open+0xaf/0xe0 [drm] [ 97.807224] chrdev_open+0xa3/0x1b0 [ 97.807224] ? cdev_put.part.0+0x20/0x20 [ 97.807224] do_dentry_open+0x132/0x340 [ 97.807224] path_openat+0x2d1/0x14e0 [ 97.807224] ? mem_cgroup_commit_charge+0x7a/0x520 [ 97.807224] do_filp_open+0x93/0x100 [ 97.807224] ? __check_object_size+0x102/0x189 [ 97.807224] ? _raw_spin_unlock+0x16/0x30 [ 97.807224] do_sys_open+0x186/0x210 [ 97.807224] do_syscall_64+0x5b/0x170 [ 97.807224] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 97.807224] RIP: 0033:0x7f4147b07976 [ 97.807224] Code: 89 54 24 08 e8 7b f4 ff ff 8b 74 24 0c 48 8b 3c 24 41 89 c0 44 8b 54 24 08 b8 01 01 00 00 89 f2 48 89 fe bf 9c ff ff ff 0f 05 <48> 3d 00 f0 ff ff 77 30 44 89 c7 89 44 24 08 e8 a6 f4 ff ff 8b 44 [ 97.807224] RSP: 002b:00007ffcced96ca0 EFLAGS: 00000293 ORIG_RAX: 0000000000000101 [ 97.807224] RAX: ffffffffffffffda RBX: 00005619d5037f80 RCX: 00007f4147b07976 [ 97.807224] RDX: 0000000000000002 RSI: 00005619d46b969c RDI: 00000000ffffff9c [ 98.040039] RBP: 0000000000000024 R08: 0000000000000000 R09: 0000000000000000 [ 98.040039] R10: 0000000000000000 R11: 0000000000000293 R12: 0000000000000024 [ 98.040039] R13: 0000000000000012 R14: 00005619d5035950 R15: 0000000000000012 [ 98.040039] Modules linked in: nct6775 hwmon_vid algif_skcipher af_alg nls_iso8859_1 nls_cp437 vfat fat uvcvideo videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common arc4 videodev media snd_usb_audio snd_hda_codec_hdmi snd_usbmidi_lib snd_rawmidi snd_seq_device mousedev input_leds iwlmvm mac80211 snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec edac_mce_amd kvm_amd snd_hda_core kvm iwlwifi snd_hwdep r8169 wmi_bmof cfg80211 snd_pcm irqbypass snd_timer snd libphy soundcore pinctrl_amd rfkill pcspkr sp5100_tco evdev gpio_amdpt k10temp mac_hid i2c_piix4 wmi pcc_cpufreq acpi_cpufreq vboxnetflt(OE) vboxnetadp(OE) vboxpci(OE) vboxdrv(OE) msr sg crypto_user ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 fscrypto uas usb_storage dm_crypt hid_generic usbhid hid [ 98.040039] dm_mod raid1 md_mod sd_mod crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel pcbc ahci libahci aesni_intel aes_x86_64 libata crypto_simd cryptd glue_helper ccp xhci_pci rng_core scsi_mod xhci_hcd nvidia_drm(POE) drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm agpgart nvidia_uvm(POE) nvidia_modeset(POE) nvidia(POE) ipmi_devintf ipmi_msghandler [ 98.040039] CR2: 0000000000000080 [ 98.040039] ---[ end trace 3b65093b6fe62b2f ]--- [ 98.040039] RIP: 0010:drm_lease_owner+0xd/0x20 [drm] [ 98.040039] Code: 83 c4 18 5b 5d c3 b8 ea ff ff ff eb e2 b8 ed ff ff ff eb db e8 b4 ca 68 fb 0f 1f 40 00 0f 1f 44 00 00 48 89 f8 eb 03 48 89 d0 <48> 8b 90 80 00 00 00 48 85 d2 75 f1 c3 66 0f 1f 44 00 00 0f 1f 44 [ 98.040039] RSP: 0018:ffffb8cf08e07bb0 EFLAGS: 00010202 [ 98.040039] RAX: 0000000000000000 RBX: ffff9cf0f2586c00 RCX: ffff9cf0f2586c88 [ 98.040039] RDX: ffff9cf0ddbd8000 RSI: 0000000000000000 RDI: 0000000000000000 [ 98.040039] RBP: ffff9cf1040e9800 R08: 0000000000000000 R09: 0000000000000000 [ 98.040039] R10: ffffdeb30fd5d680 R11: ffffdeb30f5d6808 R12: ffff9cf1040e9888 [ 98.040039] R13: 0000000000000000 R14: dead000000000200 R15: ffff9cf0f2586cc8 [ 98.040039] FS: 00007f4145513180(0000) GS:ffff9cf10ea00000(0000) knlGS:0000000000000000 [ 98.040039] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 98.040039] CR2: 0000000000000080 CR3: 00000003d7548000 CR4: 00000000003406f0 Signed-off-by: Sergio Correia Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20181122053329.2692-1-sergio@correia.cc Signed-off-by: Sean Paul Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_auth.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index 7ff697389d74..fe85d041d0ba 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -133,6 +133,7 @@ static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv) lockdep_assert_held_once(&dev->master_mutex); + WARN_ON(fpriv->is_master); old_master = fpriv->master; fpriv->master = drm_master_create(dev); if (!fpriv->master) { @@ -161,6 +162,7 @@ static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv) /* drop references and restore old master on failure */ drm_master_put(&fpriv->master); fpriv->master = old_master; + fpriv->is_master = 0; return ret; } -- GitLab From 9576f5215818f54c299eb7880e396ad75fc777fc Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Sat, 24 Nov 2018 14:12:38 -0500 Subject: [PATCH 0331/1286] drm/meson: Enable fast_io in meson_dw_hdmi_regmap_config commit 995b278e4723b26f8ebf0e7c119286d16c712747 upstream. Seeing as we use this registermap in the context of our IRQ handlers, we need to be using spinlocks for reading/writing registers so that we can still read them from IRQ handlers without having to grab any mutexes and accidentally sleep. We don't currently do this, as pointed out by lockdep: [ 18.403770] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:908 [ 18.406744] in_atomic(): 1, irqs_disabled(): 128, pid: 68, name: kworker/u17:0 [ 18.413864] INFO: lockdep is turned off. [ 18.417675] irq event stamp: 12 [ 18.420778] hardirqs last enabled at (11): [] _raw_spin_unlock_irq+0x2c/0x60 [ 18.429510] hardirqs last disabled at (12): [] __schedule+0xc4/0xa60 [ 18.437345] softirqs last enabled at (0): [] copy_process.isra.4.part.5+0x4d8/0x1c50 [ 18.446684] softirqs last disabled at (0): [<0000000000000000>] (null) [ 18.453979] CPU: 0 PID: 68 Comm: kworker/u17:0 Tainted: G W O 4.20.0-rc3Lyude-Test+ #9 [ 18.469839] Hardware name: amlogic khadas-vim2/khadas-vim2, BIOS 2018.07-rc2-armbian 09/11/2018 [ 18.480037] Workqueue: hci0 hci_power_on [bluetooth] [ 18.487138] Call trace: [ 18.494192] dump_backtrace+0x0/0x1b8 [ 18.501280] show_stack+0x14/0x20 [ 18.508361] dump_stack+0xbc/0xf4 [ 18.515427] ___might_sleep+0x140/0x1d8 [ 18.522515] __might_sleep+0x50/0x88 [ 18.529582] __mutex_lock+0x60/0x870 [ 18.536621] mutex_lock_nested+0x1c/0x28 [ 18.543660] regmap_lock_mutex+0x10/0x18 [ 18.550696] regmap_read+0x38/0x70 [ 18.557727] dw_hdmi_hardirq+0x58/0x138 [dw_hdmi] [ 18.564804] __handle_irq_event_percpu+0xac/0x410 [ 18.571891] handle_irq_event_percpu+0x34/0x88 [ 18.578982] handle_irq_event+0x48/0x78 [ 18.586051] handle_fasteoi_irq+0xac/0x160 [ 18.593061] generic_handle_irq+0x24/0x38 [ 18.599989] __handle_domain_irq+0x60/0xb8 [ 18.606857] gic_handle_irq+0x50/0xa0 [ 18.613659] el1_irq+0xb4/0x130 [ 18.620394] debug_lockdep_rcu_enabled+0x2c/0x30 [ 18.627111] schedule+0x38/0xa0 [ 18.633781] schedule_timeout+0x3a8/0x510 [ 18.640389] wait_for_common+0x15c/0x180 [ 18.646905] wait_for_completion+0x14/0x20 [ 18.653319] mmc_wait_for_req_done+0x28/0x168 [ 18.659693] mmc_wait_for_req+0xa8/0xe8 [ 18.665978] mmc_wait_for_cmd+0x64/0x98 [ 18.672180] mmc_io_rw_direct_host+0x94/0x130 [ 18.678385] mmc_io_rw_direct+0x10/0x18 [ 18.684516] sdio_enable_func+0xe8/0x1d0 [ 18.690627] btsdio_open+0x24/0xc0 [btsdio] [ 18.696821] hci_dev_do_open+0x64/0x598 [bluetooth] [ 18.703025] hci_power_on+0x50/0x270 [bluetooth] [ 18.709163] process_one_work+0x2a0/0x6e0 [ 18.715252] worker_thread+0x40/0x448 [ 18.721310] kthread+0x12c/0x130 [ 18.727326] ret_from_fork+0x10/0x1c [ 18.735555] ------------[ cut here ]------------ [ 18.741430] do not call blocking ops when !TASK_RUNNING; state=2 set at [<000000006265ec59>] wait_for_common+0x140/0x180 [ 18.752417] WARNING: CPU: 0 PID: 68 at kernel/sched/core.c:6096 __might_sleep+0x7c/0x88 [ 18.760553] Modules linked in: dm_mirror dm_region_hash dm_log dm_mod btsdio bluetooth snd_soc_hdmi_codec dw_hdmi_i2s_audio ecdh_generic brcmfmac brcmutil cfg80211 rfkill ir_nec_decoder meson_dw_hdmi(O) dw_hdmi rc_geekbox meson_rng meson_ir ao_cec rng_core rc_core cec leds_pwm efivars nfsd ip_tables x_tables crc32_generic f2fs uas meson_gxbb_wdt pwm_meson efivarfs ipv6 [ 18.799469] CPU: 0 PID: 68 Comm: kworker/u17:0 Tainted: G W O 4.20.0-rc3Lyude-Test+ #9 [ 18.808858] Hardware name: amlogic khadas-vim2/khadas-vim2, BIOS 2018.07-rc2-armbian 09/11/2018 [ 18.818045] Workqueue: hci0 hci_power_on [bluetooth] [ 18.824088] pstate: 80000085 (Nzcv daIf -PAN -UAO) [ 18.829891] pc : __might_sleep+0x7c/0x88 [ 18.835722] lr : __might_sleep+0x7c/0x88 [ 18.841256] sp : ffff000008003cb0 [ 18.846751] x29: ffff000008003cb0 x28: 0000000000000000 [ 18.852269] x27: ffff00000938e000 x26: ffff800010283000 [ 18.857726] x25: ffff800010353280 x24: ffff00000868ef50 [ 18.863166] x23: 0000000000000000 x22: 0000000000000000 [ 18.868551] x21: 0000000000000000 x20: 000000000000038c [ 18.873850] x19: ffff000008cd08c0 x18: 0000000000000010 [ 18.879081] x17: ffff000008a68cb0 x16: 0000000000000000 [ 18.884197] x15: 0000000000aaaaaa x14: 0e200e200e200e20 [ 18.889239] x13: 0000000000000001 x12: 00000000ffffffff [ 18.894261] x11: ffff000008adfa48 x10: 0000000000000001 [ 18.899517] x9 : ffff0000092a0158 x8 : 0000000000000000 [ 18.904674] x7 : ffff00000812136c x6 : 0000000000000000 [ 18.909895] x5 : 0000000000000000 x4 : 0000000000000001 [ 18.915080] x3 : 0000000000000007 x2 : 0000000000000007 [ 18.920269] x1 : 99ab8e9ebb6c8500 x0 : 0000000000000000 [ 18.925443] Call trace: [ 18.929904] __might_sleep+0x7c/0x88 [ 18.934311] __mutex_lock+0x60/0x870 [ 18.938687] mutex_lock_nested+0x1c/0x28 [ 18.943076] regmap_lock_mutex+0x10/0x18 [ 18.947453] regmap_read+0x38/0x70 [ 18.951842] dw_hdmi_hardirq+0x58/0x138 [dw_hdmi] [ 18.956269] __handle_irq_event_percpu+0xac/0x410 [ 18.960712] handle_irq_event_percpu+0x34/0x88 [ 18.965176] handle_irq_event+0x48/0x78 [ 18.969612] handle_fasteoi_irq+0xac/0x160 [ 18.974058] generic_handle_irq+0x24/0x38 [ 18.978501] __handle_domain_irq+0x60/0xb8 [ 18.982938] gic_handle_irq+0x50/0xa0 [ 18.987351] el1_irq+0xb4/0x130 [ 18.991734] debug_lockdep_rcu_enabled+0x2c/0x30 [ 18.996180] schedule+0x38/0xa0 [ 19.000609] schedule_timeout+0x3a8/0x510 [ 19.005064] wait_for_common+0x15c/0x180 [ 19.009513] wait_for_completion+0x14/0x20 [ 19.013951] mmc_wait_for_req_done+0x28/0x168 [ 19.018402] mmc_wait_for_req+0xa8/0xe8 [ 19.022809] mmc_wait_for_cmd+0x64/0x98 [ 19.027177] mmc_io_rw_direct_host+0x94/0x130 [ 19.031563] mmc_io_rw_direct+0x10/0x18 [ 19.035922] sdio_enable_func+0xe8/0x1d0 [ 19.040294] btsdio_open+0x24/0xc0 [btsdio] [ 19.044742] hci_dev_do_open+0x64/0x598 [bluetooth] [ 19.049228] hci_power_on+0x50/0x270 [bluetooth] [ 19.053687] process_one_work+0x2a0/0x6e0 [ 19.058143] worker_thread+0x40/0x448 [ 19.062608] kthread+0x12c/0x130 [ 19.067064] ret_from_fork+0x10/0x1c [ 19.071513] irq event stamp: 12 [ 19.075937] hardirqs last enabled at (11): [] _raw_spin_unlock_irq+0x2c/0x60 [ 19.083560] hardirqs last disabled at (12): [] __schedule+0xc4/0xa60 [ 19.091401] softirqs last enabled at (0): [] copy_process.isra.4.part.5+0x4d8/0x1c50 [ 19.100801] softirqs last disabled at (0): [<0000000000000000>] (null) [ 19.108135] ---[ end trace 38c4920787b88c75 ]--- So, fix this by enabling the fast_io option in our regmap config so that regmap uses spinlocks for locking instead of mutexes. Signed-off-by: Lyude Paul Fixes: 3f68be7d8e96 ("drm/meson: Add support for HDMI encoder and DW-HDMI bridge + PHY") Cc: Daniel Vetter Cc: Neil Armstrong Cc: Carlo Caione Cc: Kevin Hilman Cc: dri-devel@lists.freedesktop.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: # v4.12+ Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20181124191238.28276-1-lyude@redhat.com Signed-off-by: Sean Paul Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index cef414466f9f..e5f7a7cf48fa 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -697,6 +697,7 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = { .reg_read = meson_dw_hdmi_reg_read, .reg_write = meson_dw_hdmi_reg_write, .max_register = 0x10000, + .fast_io = true, }; static bool meson_hdmi_connector_is_available(struct device *dev) -- GitLab From a88a1b3c215beee3f78ee9b8981518381fa073d6 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Sat, 24 Nov 2018 20:21:17 -0500 Subject: [PATCH 0332/1286] drm/meson: Fix OOB memory accesses in meson_viu_set_osd_lut() commit 97b2a3180a559a33852ac0cd77904166069484fd upstream. Currently on driver bringup with KASAN enabled, meson triggers an OOB memory access as shown below: [ 117.904528] ================================================================== [ 117.904560] BUG: KASAN: global-out-of-bounds in meson_viu_set_osd_lut+0x7a0/0x890 [ 117.904588] Read of size 4 at addr ffff20000a63ce24 by task systemd-udevd/498 [ 117.904601] [ 118.083372] CPU: 4 PID: 498 Comm: systemd-udevd Not tainted 4.20.0-rc3Lyude-Test+ #20 [ 118.091143] Hardware name: amlogic khadas-vim2/khadas-vim2, BIOS 2018.07-rc2-armbian 09/11/2018 [ 118.099768] Call trace: [ 118.102181] dump_backtrace+0x0/0x3e8 [ 118.105796] show_stack+0x14/0x20 [ 118.109083] dump_stack+0x130/0x1c4 [ 118.112539] print_address_description+0x60/0x25c [ 118.117214] kasan_report+0x1b4/0x368 [ 118.120851] __asan_report_load4_noabort+0x18/0x20 [ 118.125566] meson_viu_set_osd_lut+0x7a0/0x890 [ 118.129953] meson_viu_init+0x10c/0x290 [ 118.133741] meson_drv_bind_master+0x474/0x748 [ 118.138141] meson_drv_bind+0x10/0x18 [ 118.141760] try_to_bring_up_master+0x3d8/0x768 [ 118.146249] component_add+0x214/0x570 [ 118.149978] meson_dw_hdmi_probe+0x18/0x20 [meson_dw_hdmi] [ 118.155404] platform_drv_probe+0x98/0x138 [ 118.159455] really_probe+0x2a0/0xa70 [ 118.163070] driver_probe_device+0x1b4/0x2d8 [ 118.167299] __driver_attach+0x200/0x280 [ 118.171189] bus_for_each_dev+0x10c/0x1a8 [ 118.175144] driver_attach+0x38/0x50 [ 118.178681] bus_add_driver+0x330/0x608 [ 118.182471] driver_register+0x140/0x388 [ 118.186361] __platform_driver_register+0xc8/0x108 [ 118.191117] meson_dw_hdmi_platform_driver_init+0x1c/0x1000 [meson_dw_hdmi] [ 118.198022] do_one_initcall+0x12c/0x3bc [ 118.201883] do_init_module+0x1fc/0x638 [ 118.205673] load_module+0x4b4c/0x6808 [ 118.209387] __se_sys_init_module+0x2e8/0x3c0 [ 118.213699] __arm64_sys_init_module+0x68/0x98 [ 118.218100] el0_svc_common+0x104/0x210 [ 118.221893] el0_svc_handler+0x48/0xb8 [ 118.225594] el0_svc+0x8/0xc [ 118.228429] [ 118.229887] The buggy address belongs to the variable: [ 118.235007] eotf_33_linear_mapping+0x84/0xc0 [ 118.239301] [ 118.240752] Memory state around the buggy address: [ 118.245522] ffff20000a63cd00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 118.252695] ffff20000a63cd80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 118.259850] >ffff20000a63ce00: 00 00 00 00 04 fa fa fa fa fa fa fa 00 00 00 00 [ 118.267000] ^ [ 118.271222] ffff20000a63ce80: 00 fa fa fa fa fa fa fa 00 00 00 00 00 00 00 00 [ 118.278393] ffff20000a63cf00: 00 00 00 00 00 00 00 00 00 00 00 00 04 fa fa fa [ 118.285542] ================================================================== [ 118.292699] Disabling lock debugging due to kernel taint It seems that when looping through the OSD EOTF LUT maps, we use the same max iterator for OETF: 20. This is wrong though, since 20*2 is 40, which means that we'll stop out of bounds on the EOTF maps. But, this whole thing is already confusing enough to read through as-is, so let's just replace all of the hardcoded sizes with OSD_(OETF/EOTF)_LUT_SIZE / 2. Signed-off-by: Lyude Paul Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller") Cc: Neil Armstrong Cc: Maxime Ripard Cc: Carlo Caione Cc: Kevin Hilman Cc: dri-devel@lists.freedesktop.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: # v4.10+ Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20181125012117.31915-1-lyude@redhat.com Signed-off-by: Sean Paul Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/meson/meson_viu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index 6bcfa527c180..26a0857878bf 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -184,18 +184,18 @@ void meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel, if (lut_sel == VIU_LUT_OSD_OETF) { writel(0, priv->io_base + _REG(addr_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16), priv->io_base + _REG(data_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16), priv->io_base + _REG(data_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); @@ -211,18 +211,18 @@ void meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel, } else if (lut_sel == VIU_LUT_OSD_EOTF) { writel(0, priv->io_base + _REG(addr_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16), priv->io_base + _REG(data_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16), priv->io_base + _REG(data_port)); - for (i = 0; i < 20; i++) + for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); -- GitLab From 82c5a8c0debac552750a00b4fc7551c89c7b34b8 Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 30 Nov 2018 14:09:25 -0800 Subject: [PATCH 0333/1286] userfaultfd: use ENOENT instead of EFAULT if the atomic copy user fails commit 9e368259ad988356c4c95150fafd1a06af095d98 upstream. Patch series "userfaultfd shmem updates". Jann found two bugs in the userfaultfd shmem MAP_SHARED backend: the lack of the VM_MAYWRITE check and the lack of i_size checks. Then looking into the above we also fixed the MAP_PRIVATE case. Hugh by source review also found a data loss source if UFFDIO_COPY is used on shmem MAP_SHARED PROT_READ mappings (the production usages incidentally run with PROT_READ|PROT_WRITE, so the data loss couldn't happen in those production usages like with QEMU). The whole patchset is marked for stable. We verified QEMU postcopy live migration with guest running on shmem MAP_PRIVATE run as well as before after the fix of shmem MAP_PRIVATE. Regardless if it's shmem or hugetlbfs or MAP_PRIVATE or MAP_SHARED, QEMU unconditionally invokes a punch hole if the guest mapping is filebacked and a MADV_DONTNEED too (needed to get rid of the MAP_PRIVATE COWs and for the anon backend). This patch (of 5): We internally used EFAULT to communicate with the caller, switch to ENOENT, so EFAULT can be used as a non internal retval. Link: http://lkml.kernel.org/r/20181126173452.26955-2-aarcange@redhat.com Fixes: 4c27fe4c4c84 ("userfaultfd: shmem: add shmem_mcopy_atomic_pte for userfaultfd support") Signed-off-by: Andrea Arcangeli Reviewed-by: Mike Rapoport Reviewed-by: Hugh Dickins Cc: Mike Kravetz Cc: Jann Horn Cc: Peter Xu Cc: "Dr. David Alan Gilbert" Cc: Cc: stable@vger.kernel.org Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/hugetlb.c | 2 +- mm/shmem.c | 2 +- mm/userfaultfd.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/mm/hugetlb.c b/mm/hugetlb.c index f46040aed2da..224cdd953a79 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -4037,7 +4037,7 @@ int hugetlb_mcopy_atomic_pte(struct mm_struct *dst_mm, /* fallback to copy_from_user outside mmap_sem */ if (unlikely(ret)) { - ret = -EFAULT; + ret = -ENOENT; *pagep = page; /* don't free the page */ goto out; diff --git a/mm/shmem.c b/mm/shmem.c index ab7ff0aeae2d..9f856ecda73b 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2266,7 +2266,7 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, *pagep = page; shmem_inode_unacct_blocks(inode, 1); /* don't free the page */ - return -EFAULT; + return -ENOENT; } } else { /* mfill_zeropage_atomic */ clear_highpage(page); diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index 81192701964d..c63c0fc5ecfa 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -49,7 +49,7 @@ static int mcopy_atomic_pte(struct mm_struct *dst_mm, /* fallback to copy_from_user outside mmap_sem */ if (unlikely(ret)) { - ret = -EFAULT; + ret = -ENOENT; *pagep = page; /* don't free the page */ goto out; @@ -275,7 +275,7 @@ static __always_inline ssize_t __mcopy_atomic_hugetlb(struct mm_struct *dst_mm, cond_resched(); - if (unlikely(err == -EFAULT)) { + if (unlikely(err == -ENOENT)) { up_read(&dst_mm->mmap_sem); BUG_ON(!page); @@ -521,7 +521,7 @@ static __always_inline ssize_t __mcopy_atomic(struct mm_struct *dst_mm, src_addr, &page, zeropage); cond_resched(); - if (unlikely(err == -EFAULT)) { + if (unlikely(err == -ENOENT)) { void *page_kaddr; up_read(&dst_mm->mmap_sem); -- GitLab From 683b47330c498a7bb90b1e863f63c9b5035dbba9 Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 30 Nov 2018 14:09:28 -0800 Subject: [PATCH 0334/1286] userfaultfd: shmem: allocate anonymous memory for MAP_PRIVATE shmem commit 5b51072e97d587186c2f5390c8c9c1fb7e179505 upstream. Userfaultfd did not create private memory when UFFDIO_COPY was invoked on a MAP_PRIVATE shmem mapping. Instead it wrote to the shmem file, even when that had not been opened for writing. Though, fortunately, that could only happen where there was a hole in the file. Fix the shmem-backed implementation of UFFDIO_COPY to create private memory for MAP_PRIVATE mappings. The hugetlbfs-backed implementation was already correct. This change is visible to userland, if userfaultfd has been used in unintended ways: so it introduces a small risk of incompatibility, but is necessary in order to respect file permissions. An app that uses UFFDIO_COPY for anything like postcopy live migration won't notice the difference, and in fact it'll run faster because there will be no copy-on-write and memory waste in the tmpfs pagecache anymore. Userfaults on MAP_PRIVATE shmem keep triggering only on file holes like before. The real zeropage can also be built on a MAP_PRIVATE shmem mapping through UFFDIO_ZEROPAGE and that's safe because the zeropage pte is never dirty, in turn even an mprotect upgrading the vma permission from PROT_READ to PROT_READ|PROT_WRITE won't make the zeropage pte writable. Link: http://lkml.kernel.org/r/20181126173452.26955-3-aarcange@redhat.com Fixes: 4c27fe4c4c84 ("userfaultfd: shmem: add shmem_mcopy_atomic_pte for userfaultfd support") Signed-off-by: Andrea Arcangeli Reported-by: Mike Rapoport Reviewed-by: Hugh Dickins Cc: Cc: "Dr. David Alan Gilbert" Cc: Jann Horn Cc: Mike Kravetz Cc: Peter Xu Cc: stable@vger.kernel.org Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/userfaultfd.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index c63c0fc5ecfa..cb82e50becf7 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -381,7 +381,17 @@ static __always_inline ssize_t mfill_atomic_pte(struct mm_struct *dst_mm, { ssize_t err; - if (vma_is_anonymous(dst_vma)) { + /* + * The normal page fault path for a shmem will invoke the + * fault, fill the hole in the file and COW it right away. The + * result generates plain anonymous memory. So when we are + * asked to fill an hole in a MAP_PRIVATE shmem mapping, we'll + * generate anonymous memory directly without actually filling + * the hole. For the MAP_PRIVATE case the robustness check + * only happens in the pagetable (to verify it's still none) + * and not in the radix tree. + */ + if (!(dst_vma->vm_flags & VM_SHARED)) { if (!zeropage) err = mcopy_atomic_pte(dst_mm, dst_pmd, dst_vma, dst_addr, src_addr, page); @@ -480,7 +490,8 @@ static __always_inline ssize_t __mcopy_atomic(struct mm_struct *dst_mm, * dst_vma. */ err = -ENOMEM; - if (vma_is_anonymous(dst_vma) && unlikely(anon_vma_prepare(dst_vma))) + if (!(dst_vma->vm_flags & VM_SHARED) && + unlikely(anon_vma_prepare(dst_vma))) goto out_unlock; while (src_addr < src_start + len) { -- GitLab From af3edb30cddfcc1eace505af10d08826a9522dbe Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 30 Nov 2018 14:09:37 -0800 Subject: [PATCH 0335/1286] userfaultfd: shmem: add i_size checks commit e2a50c1f64145a04959df2442305d57307e5395a upstream. With MAP_SHARED: recheck the i_size after taking the PT lock, to serialize against truncate with the PT lock. Delete the page from the pagecache if the i_size_read check fails. With MAP_PRIVATE: check the i_size after the PT lock before mapping anonymous memory or zeropages into the MAP_PRIVATE shmem mapping. A mostly irrelevant cleanup: like we do the delete_from_page_cache() pagecache removal after dropping the PT lock, the PT lock is a spinlock so drop it before the sleepable page lock. Link: http://lkml.kernel.org/r/20181126173452.26955-5-aarcange@redhat.com Fixes: 4c27fe4c4c84 ("userfaultfd: shmem: add shmem_mcopy_atomic_pte for userfaultfd support") Signed-off-by: Andrea Arcangeli Reviewed-by: Mike Rapoport Reviewed-by: Hugh Dickins Reported-by: Jann Horn Cc: Cc: "Dr. David Alan Gilbert" Cc: Mike Kravetz Cc: Peter Xu Cc: stable@vger.kernel.org Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/shmem.c | 18 ++++++++++++++++-- mm/userfaultfd.c | 26 ++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/mm/shmem.c b/mm/shmem.c index 9f856ecda73b..581e7baf0478 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2244,6 +2244,7 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, struct page *page; pte_t _dst_pte, *dst_pte; int ret; + pgoff_t offset, max_off; ret = -ENOMEM; if (!shmem_inode_acct_block(inode, 1)) @@ -2281,6 +2282,12 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, __SetPageSwapBacked(page); __SetPageUptodate(page); + ret = -EFAULT; + offset = linear_page_index(dst_vma, dst_addr); + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + if (unlikely(offset >= max_off)) + goto out_release; + ret = mem_cgroup_try_charge(page, dst_mm, gfp, &memcg, false); if (ret) goto out_release; @@ -2299,8 +2306,14 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, if (dst_vma->vm_flags & VM_WRITE) _dst_pte = pte_mkwrite(pte_mkdirty(_dst_pte)); - ret = -EEXIST; dst_pte = pte_offset_map_lock(dst_mm, dst_pmd, dst_addr, &ptl); + + ret = -EFAULT; + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + if (unlikely(offset >= max_off)) + goto out_release_uncharge_unlock; + + ret = -EEXIST; if (!pte_none(*dst_pte)) goto out_release_uncharge_unlock; @@ -2318,13 +2331,14 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, /* No need to invalidate - it was non-present before */ update_mmu_cache(dst_vma, dst_addr, dst_pte); - unlock_page(page); pte_unmap_unlock(dst_pte, ptl); + unlock_page(page); ret = 0; out: return ret; out_release_uncharge_unlock: pte_unmap_unlock(dst_pte, ptl); + delete_from_page_cache(page); out_release_uncharge: mem_cgroup_cancel_charge(page, memcg, false); out_release: diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index cb82e50becf7..8da1cd8cea89 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -34,6 +34,8 @@ static int mcopy_atomic_pte(struct mm_struct *dst_mm, void *page_kaddr; int ret; struct page *page; + pgoff_t offset, max_off; + struct inode *inode; if (!*pagep) { ret = -ENOMEM; @@ -74,8 +76,17 @@ static int mcopy_atomic_pte(struct mm_struct *dst_mm, if (dst_vma->vm_flags & VM_WRITE) _dst_pte = pte_mkwrite(pte_mkdirty(_dst_pte)); - ret = -EEXIST; dst_pte = pte_offset_map_lock(dst_mm, dst_pmd, dst_addr, &ptl); + if (dst_vma->vm_file) { + /* the shmem MAP_PRIVATE case requires checking the i_size */ + inode = dst_vma->vm_file->f_inode; + offset = linear_page_index(dst_vma, dst_addr); + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + ret = -EFAULT; + if (unlikely(offset >= max_off)) + goto out_release_uncharge_unlock; + } + ret = -EEXIST; if (!pte_none(*dst_pte)) goto out_release_uncharge_unlock; @@ -109,11 +120,22 @@ static int mfill_zeropage_pte(struct mm_struct *dst_mm, pte_t _dst_pte, *dst_pte; spinlock_t *ptl; int ret; + pgoff_t offset, max_off; + struct inode *inode; _dst_pte = pte_mkspecial(pfn_pte(my_zero_pfn(dst_addr), dst_vma->vm_page_prot)); - ret = -EEXIST; dst_pte = pte_offset_map_lock(dst_mm, dst_pmd, dst_addr, &ptl); + if (dst_vma->vm_file) { + /* the shmem MAP_PRIVATE case requires checking the i_size */ + inode = dst_vma->vm_file->f_inode; + offset = linear_page_index(dst_vma, dst_addr); + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + ret = -EFAULT; + if (unlikely(offset >= max_off)) + goto out_unlock; + } + ret = -EEXIST; if (!pte_none(*dst_pte)) goto out_unlock; set_pte_at(dst_mm, dst_addr, dst_pte, _dst_pte); -- GitLab From 46466e23bc1bc262c28a020df982233c309ed958 Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 30 Nov 2018 14:09:43 -0800 Subject: [PATCH 0336/1286] userfaultfd: shmem: UFFDIO_COPY: set the page dirty if VM_WRITE is not set commit dcf7fe9d89763a28e0f43975b422ff141fe79e43 upstream. Set the page dirty if VM_WRITE is not set because in such case the pte won't be marked dirty and the page would be reclaimed without writepage (i.e. swapout in the shmem case). This was found by source review. Most apps (certainly including QEMU) only use UFFDIO_COPY on PROT_READ|PROT_WRITE mappings or the app can't modify the memory in the first place. This is for correctness and it could help the non cooperative use case to avoid unexpected data loss. Link: http://lkml.kernel.org/r/20181126173452.26955-6-aarcange@redhat.com Reviewed-by: Hugh Dickins Cc: stable@vger.kernel.org Fixes: 4c27fe4c4c84 ("userfaultfd: shmem: add shmem_mcopy_atomic_pte for userfaultfd support") Reported-by: Hugh Dickins Signed-off-by: Andrea Arcangeli Cc: "Dr. David Alan Gilbert" Cc: Jann Horn Cc: Mike Kravetz Cc: Mike Rapoport Cc: Peter Xu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- mm/shmem.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/mm/shmem.c b/mm/shmem.c index 581e7baf0478..6c10f1d92251 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2305,6 +2305,16 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, _dst_pte = mk_pte(page, dst_vma->vm_page_prot); if (dst_vma->vm_flags & VM_WRITE) _dst_pte = pte_mkwrite(pte_mkdirty(_dst_pte)); + else { + /* + * We don't set the pte dirty if the vma has no + * VM_WRITE permission, so mark the page dirty or it + * could be freed from under us. We could do it + * unconditionally before unlock_page(), but doing it + * only if VM_WRITE is not set is faster. + */ + set_page_dirty(page); + } dst_pte = pte_offset_map_lock(dst_mm, dst_pmd, dst_addr, &ptl); @@ -2338,6 +2348,7 @@ static int shmem_mfill_atomic_pte(struct mm_struct *dst_mm, return ret; out_release_uncharge_unlock: pte_unmap_unlock(dst_pte, ptl); + ClearPageDirty(page); delete_from_page_cache(page); out_release_uncharge: mem_cgroup_cancel_charge(page, memcg, false); -- GitLab From 6ea54af90988bf869e57265723c33af623b4abec Mon Sep 17 00:00:00 2001 From: Martin Wilck Date: Mon, 27 Nov 2017 23:47:35 +0100 Subject: [PATCH 0337/1286] scsi: scsi_devinfo: cleanly zero-pad devinfo strings commit 81df022b688d43d2a3667518b2f755d384397910 upstream. Cleanly fill memory for "vendor" and "model" with 0-bytes for the "compatible" case rather than adding only a single 0 byte. This simplifies the devinfo code a a bit, and avoids mistakes in other places of the code (not in current upstream, but we had one such mistake in the SUSE kernel). [mkp: applied by hand and added braces] Signed-off-by: Martin Wilck Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/scsi_devinfo.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index ea947a7c2596..6b594bc7d94a 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -34,7 +34,6 @@ struct scsi_dev_info_list_table { }; -static const char spaces[] = " "; /* 16 of them */ static unsigned scsi_default_dev_flags; static LIST_HEAD(scsi_dev_info_list); static char scsi_dev_flags[256]; @@ -296,20 +295,13 @@ static void scsi_strcpy_devinfo(char *name, char *to, size_t to_length, size_t from_length; from_length = strlen(from); - strncpy(to, from, min(to_length, from_length)); - if (from_length < to_length) { - if (compatible) { - /* - * NUL terminate the string if it is short. - */ - to[from_length] = '\0'; - } else { - /* - * space pad the string if it is short. - */ - strncpy(&to[from_length], spaces, - to_length - from_length); - } + /* this zero-pads the destination */ + strncpy(to, from, to_length); + if (from_length < to_length && !compatible) { + /* + * space pad the string if it is short. + */ + memset(&to[from_length], ' ', to_length - from_length); } if (from_length > to_length) printk(KERN_WARNING "%s: %s string '%s' is too long\n", -- GitLab From 705a2810a314ccf06fe6190ea555e586975f9b28 Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 30 Nov 2018 14:09:32 -0800 Subject: [PATCH 0338/1286] userfaultfd: shmem/hugetlbfs: only allow to register VM_MAYWRITE vmas commit 29ec90660d68bbdd69507c1c8b4e33aa299278b1 upstream. After the VMA to register the uffd onto is found, check that it has VM_MAYWRITE set before allowing registration. This way we inherit all common code checks before allowing to fill file holes in shmem and hugetlbfs with UFFDIO_COPY. The userfaultfd memory model is not applicable for readonly files unless it's a MAP_PRIVATE. Link: http://lkml.kernel.org/r/20181126173452.26955-4-aarcange@redhat.com Fixes: ff62a3421044 ("hugetlb: implement memfd sealing") Signed-off-by: Andrea Arcangeli Reviewed-by: Mike Rapoport Reviewed-by: Hugh Dickins Reported-by: Jann Horn Fixes: 4c27fe4c4c84 ("userfaultfd: shmem: add shmem_mcopy_atomic_pte for userfaultfd support") Cc: Cc: "Dr. David Alan Gilbert" Cc: Mike Kravetz Cc: Peter Xu Cc: stable@vger.kernel.org Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- fs/userfaultfd.c | 15 +++++++++++++++ mm/userfaultfd.c | 15 ++++++--------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c index 3eda623e4cb4..f92e1f2fc846 100644 --- a/fs/userfaultfd.c +++ b/fs/userfaultfd.c @@ -1362,6 +1362,19 @@ static int userfaultfd_register(struct userfaultfd_ctx *ctx, ret = -EINVAL; if (!vma_can_userfault(cur)) goto out_unlock; + + /* + * UFFDIO_COPY will fill file holes even without + * PROT_WRITE. This check enforces that if this is a + * MAP_SHARED, the process has write permission to the backing + * file. If VM_MAYWRITE is set it also enforces that on a + * MAP_SHARED vma: there is no F_WRITE_SEAL and no further + * F_WRITE_SEAL can be taken until the vma is destroyed. + */ + ret = -EPERM; + if (unlikely(!(cur->vm_flags & VM_MAYWRITE))) + goto out_unlock; + /* * If this vma contains ending address, and huge pages * check alignment. @@ -1407,6 +1420,7 @@ static int userfaultfd_register(struct userfaultfd_ctx *ctx, BUG_ON(!vma_can_userfault(vma)); BUG_ON(vma->vm_userfaultfd_ctx.ctx && vma->vm_userfaultfd_ctx.ctx != ctx); + WARN_ON(!(vma->vm_flags & VM_MAYWRITE)); /* * Nothing to do: this vma is already registered into this @@ -1553,6 +1567,7 @@ static int userfaultfd_unregister(struct userfaultfd_ctx *ctx, cond_resched(); BUG_ON(!vma_can_userfault(vma)); + WARN_ON(!(vma->vm_flags & VM_MAYWRITE)); /* * Nothing to do: this vma is already registered into this diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index 8da1cd8cea89..5d70fdbd8bc0 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -228,8 +228,9 @@ static __always_inline ssize_t __mcopy_atomic_hugetlb(struct mm_struct *dst_mm, if (!dst_vma || !is_vm_hugetlb_page(dst_vma)) goto out_unlock; /* - * Only allow __mcopy_atomic_hugetlb on userfaultfd - * registered ranges. + * Check the vma is registered in uffd, this is + * required to enforce the VM_MAYWRITE check done at + * uffd registration time. */ if (!dst_vma->vm_userfaultfd_ctx.ctx) goto out_unlock; @@ -472,13 +473,9 @@ static __always_inline ssize_t __mcopy_atomic(struct mm_struct *dst_mm, if (!dst_vma) goto out_unlock; /* - * Be strict and only allow __mcopy_atomic on userfaultfd - * registered ranges to prevent userland errors going - * unnoticed. As far as the VM consistency is concerned, it - * would be perfectly safe to remove this check, but there's - * no useful usage for __mcopy_atomic ouside of userfaultfd - * registered ranges. This is after all why these are ioctls - * belonging to the userfaultfd and not syscalls. + * Check the vma is registered in uffd, this is required to + * enforce the VM_MAYWRITE check done at uffd registration + * time. */ if (!dst_vma->vm_userfaultfd_ctx.ctx) goto out_unlock; -- GitLab From 6bf8c9fc962e5586397c9a3bbed9b806b1cdab55 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 26 Jul 2018 14:58:03 +0200 Subject: [PATCH 0339/1286] ALSA: trident: Suppress gcc string warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit d6b340d7cb33c816ef4abe8143764ec5ab14a5cc upstream. The meddlesome gcc warns about the possible shortname string in trident driver code: sound/pci/trident/trident.c: In function ‘snd_trident_probe’: sound/pci/trident/trident.c:126:2: warning: ‘strcat’ accessing 17 or more bytes at offsets 36 and 20 may overlap 1 byte at offset 36 [-Wrestrict] strcat(card->shortname, card->driver); It happens since gcc calculates the possible string size from card->driver, but this can't be true since we did set the string just before that, and they are much shorter. For shutting it up, use the exactly same string set to card->driver for strcat() to card->shortname, too. Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/trident/trident.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/trident/trident.c b/sound/pci/trident/trident.c index cedf13b64803..2f18b1cdc2cd 100644 --- a/sound/pci/trident/trident.c +++ b/sound/pci/trident/trident.c @@ -123,7 +123,7 @@ static int snd_trident_probe(struct pci_dev *pci, } else { strcpy(card->shortname, "Trident "); } - strcat(card->shortname, card->driver); + strcat(card->shortname, str); sprintf(card->longname, "%s PCI Audio at 0x%lx, irq %d", card->shortname, trident->port, trident->irq); -- GitLab From a293ef5e92b523f899d5d58bd9bfc26f2ea1ee3e Mon Sep 17 00:00:00 2001 From: Laura Abbott Date: Mon, 10 Sep 2018 16:20:14 -0700 Subject: [PATCH 0340/1286] kgdboc: Fix restrict error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 2dd453168643d9475028cd867c57e65956a0f7f9 upstream. There's an error when compiled with restrict: drivers/tty/serial/kgdboc.c: In function ‘configure_kgdboc’: drivers/tty/serial/kgdboc.c:137:2: error: ‘strcpy’ source argument is the same as destination [-Werror=restrict] strcpy(config, opt); ^~~~~~~~~~~~~~~~~~~ As the error implies, this is from trying to use config as both source and destination. Drop the call to the function where config is the argument since nothing else happens in the function. Signed-off-by: Laura Abbott Reviewed-by: Daniel Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/kgdboc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c index 2db68dfe497d..da020eea7bb5 100644 --- a/drivers/tty/serial/kgdboc.c +++ b/drivers/tty/serial/kgdboc.c @@ -162,15 +162,13 @@ static int configure_kgdboc(void) { struct tty_driver *p; int tty_line = 0; - int err; + int err = -ENODEV; char *cptr = config; struct console *cons; - err = kgdboc_option_setup(config); - if (err || !strlen(config) || isspace(config[0])) + if (!strlen(config) || isspace(config[0])) goto noconfig; - err = -ENODEV; kgdboc_io_ops.is_console = 0; kgdb_tty_driver = NULL; -- GitLab From e8693a9829d1135ff6da551023de0c707394733c Mon Sep 17 00:00:00 2001 From: Laura Abbott Date: Wed, 19 Sep 2018 18:59:01 -0700 Subject: [PATCH 0341/1286] kgdboc: Fix warning with module build commit 1cd25cbb2fedbc777f3a8c3cb1ba69b645aeaa64 upstream. After 2dd453168643 ("kgdboc: Fix restrict error"), kgdboc_option_setup is now only used when built in, resulting in a warning when compiled as a module: drivers/tty/serial/kgdboc.c:134:12: warning: 'kgdboc_option_setup' defined but not used [-Wunused-function] static int kgdboc_option_setup(char *opt) ^~~~~~~~~~~~~~~~~~~ Move the function under the appropriate ifdef for builtin only. Fixes: 2dd453168643 ("kgdboc: Fix restrict error") Reported-by: Stephen Rothwell Signed-off-by: Laura Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/kgdboc.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c index da020eea7bb5..c448225ef5ca 100644 --- a/drivers/tty/serial/kgdboc.c +++ b/drivers/tty/serial/kgdboc.c @@ -131,24 +131,6 @@ static void kgdboc_unregister_kbd(void) #define kgdboc_restore_input() #endif /* ! CONFIG_KDB_KEYBOARD */ -static int kgdboc_option_setup(char *opt) -{ - if (!opt) { - pr_err("kgdboc: config string not provided\n"); - return -EINVAL; - } - - if (strlen(opt) >= MAX_CONFIG_LEN) { - printk(KERN_ERR "kgdboc: config string too long\n"); - return -ENOSPC; - } - strcpy(config, opt); - - return 0; -} - -__setup("kgdboc=", kgdboc_option_setup); - static void cleanup_kgdboc(void) { if (kgdb_unregister_nmi_console()) @@ -316,6 +298,25 @@ static struct kgdb_io kgdboc_io_ops = { }; #ifdef CONFIG_KGDB_SERIAL_CONSOLE +static int kgdboc_option_setup(char *opt) +{ + if (!opt) { + pr_err("config string not provided\n"); + return -EINVAL; + } + + if (strlen(opt) >= MAX_CONFIG_LEN) { + pr_err("config string too long\n"); + return -ENOSPC; + } + strcpy(config, opt); + + return 0; +} + +__setup("kgdboc=", kgdboc_option_setup); + + /* This is only available if kgdboc is a built in for early debugging */ static int __init kgdboc_early_init(char *opt) { -- GitLab From b002e9dc214f0f917ce1b4df753c1da0b8a9ac84 Mon Sep 17 00:00:00 2001 From: Wei Wang Date: Mon, 12 Nov 2018 12:23:14 +0000 Subject: [PATCH 0342/1286] svm: Add mutex_lock to protect apic_access_page_done on AMD systems commit 30510387a5e45bfcf8190e03ec7aa15b295828e2 upstream. There is a race condition when accessing kvm->arch.apic_access_page_done. Due to it, x86_set_memory_region will fail when creating the second vcpu for a svm guest. Add a mutex_lock to serialize the accesses to apic_access_page_done. This lock is also used by vmx for the same purpose. Signed-off-by: Wei Wang Signed-off-by: Amadeusz Juskowiak Signed-off-by: Julian Stecklina Signed-off-by: Suravee Suthikulpanit Reviewed-by: Joerg Roedel Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/svm.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 17f08db34547..4dc79d139810 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1399,20 +1399,23 @@ static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, static int avic_init_access_page(struct kvm_vcpu *vcpu) { struct kvm *kvm = vcpu->kvm; - int ret; + int ret = 0; + mutex_lock(&kvm->slots_lock); if (kvm->arch.apic_access_page_done) - return 0; + goto out; - ret = x86_set_memory_region(kvm, - APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, - APIC_DEFAULT_PHYS_BASE, - PAGE_SIZE); + ret = __x86_set_memory_region(kvm, + APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, + APIC_DEFAULT_PHYS_BASE, + PAGE_SIZE); if (ret) - return ret; + goto out; kvm->arch.apic_access_page_done = true; - return 0; +out: + mutex_unlock(&kvm->slots_lock); + return ret; } static int avic_init_backing_page(struct kvm_vcpu *vcpu) -- GitLab From 84ee7f89237f096a6fd2906bb7d909d3ba8a0432 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Aug 2018 10:21:47 +0200 Subject: [PATCH 0343/1286] drm/msm: fix OF child-node lookup commit f9a7082327e26f54067a49cac2316d31e0cc8ba7 upstream. Use the new of_get_compatible_child() helper to lookup the legacy pwrlevels child node instead of using of_find_compatible_node(), which searches the entire tree from a given start node and thus can return an unrelated (i.e. non-child) node. This also addresses a potential use-after-free (e.g. after probe deferral) as the tree-wide helper drops a reference to its first argument (i.e. the probed device's node). While at it, also fix the related child-node reference leak. Fixes: e2af8b6b0ca1 ("drm/msm: gpu: Use OPP tables if we can") Cc: stable # 4.12 Cc: Jordan Crouse Cc: Rob Clark Cc: David Airlie Signed-off-by: Johan Hovold Signed-off-by: Rob Herring [ johan: backport to 4.14 ] Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c75c4df4bc39..2c379774d3f2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -223,8 +223,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev) struct device_node *child, *node; int ret; - node = of_find_compatible_node(dev->of_node, NULL, - "qcom,gpu-pwrlevels"); + node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); if (!node) { dev_err(dev, "Could not find the GPU powerlevels\n"); return -ENXIO; @@ -245,6 +244,8 @@ static int adreno_get_legacy_pwrlevels(struct device *dev) dev_pm_opp_add(dev, val, 0); } + of_node_put(node); + return 0; } -- GitLab From cf980cebed0313ef417ffa845fd92b7f00184e5e Mon Sep 17 00:00:00 2001 From: Cameron Gutman Date: Thu, 29 Nov 2018 10:09:33 -0800 Subject: [PATCH 0344/1286] Input: xpad - quirk all PDP Xbox One gamepads commit a6754fae1e66e9a40fed406290d7ca3f2b4d227c upstream. Since we continue to find tons of new variants [0,1,2,3,4,5,6] that need the PDP quirk, let's just quirk all devices from PDP. [0]: https://github.com/paroj/xpad/pull/104 [1]: https://github.com/paroj/xpad/pull/105 [2]: https://github.com/paroj/xpad/pull/108 [3]: https://github.com/paroj/xpad/pull/109 [4]: https://github.com/paroj/xpad/pull/112 [5]: https://github.com/paroj/xpad/pull/115 [6]: https://github.com/paroj/xpad/pull/116 Fixes: e5c9c6a885fa ("Input: xpad - add support for PDP Xbox One controllers") Cc: stable@vger.kernel.org Signed-off-by: Cameron Gutman Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/joystick/xpad.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 2e52015634f9..f55dcdf99bc5 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -483,18 +483,18 @@ static const u8 xboxone_hori_init[] = { }; /* - * This packet is required for some of the PDP pads to start + * This packet is required for most (all?) of the PDP pads to start * sending input reports. These pads include: (0x0e6f:0x02ab), - * (0x0e6f:0x02a4). + * (0x0e6f:0x02a4), (0x0e6f:0x02a6). */ static const u8 xboxone_pdp_init1[] = { 0x0a, 0x20, 0x00, 0x03, 0x00, 0x01, 0x14 }; /* - * This packet is required for some of the PDP pads to start + * This packet is required for most (all?) of the PDP pads to start * sending input reports. These pads include: (0x0e6f:0x02ab), - * (0x0e6f:0x02a4). + * (0x0e6f:0x02a4), (0x0e6f:0x02a6). */ static const u8 xboxone_pdp_init2[] = { 0x06, 0x20, 0x00, 0x02, 0x01, 0x00 @@ -530,12 +530,8 @@ static const struct xboxone_init_packet xboxone_init_packets[] = { XBOXONE_INIT_PKT(0x0e6f, 0x0165, xboxone_hori_init), XBOXONE_INIT_PKT(0x0f0d, 0x0067, xboxone_hori_init), XBOXONE_INIT_PKT(0x0000, 0x0000, xboxone_fw2015_init), - XBOXONE_INIT_PKT(0x0e6f, 0x02ab, xboxone_pdp_init1), - XBOXONE_INIT_PKT(0x0e6f, 0x02ab, xboxone_pdp_init2), - XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init1), - XBOXONE_INIT_PKT(0x0e6f, 0x02a4, xboxone_pdp_init2), - XBOXONE_INIT_PKT(0x0e6f, 0x02a6, xboxone_pdp_init1), - XBOXONE_INIT_PKT(0x0e6f, 0x02a6, xboxone_pdp_init2), + XBOXONE_INIT_PKT(0x0e6f, 0x0000, xboxone_pdp_init1), + XBOXONE_INIT_PKT(0x0e6f, 0x0000, xboxone_pdp_init2), XBOXONE_INIT_PKT(0x24c6, 0x541a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x542a, xboxone_rumblebegin_init), XBOXONE_INIT_PKT(0x24c6, 0x543a, xboxone_rumblebegin_init), -- GitLab From 6dc574d0cac6e71c404ea031a9b59b9e817e05b2 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Sat, 24 Nov 2018 23:28:10 -0800 Subject: [PATCH 0345/1286] Input: synaptics - add PNP ID for ThinkPad P50 to SMBus commit 9df39bedbf292680655c6a947c77d6562c693d4a upstream. Noticed the other day the trackpoint felt different on my P50, then realized it was because rmi4 wasn't loading for this machine automatically. Suspend/resume, hibernate, and everything else seem to work perfectly fine on here. Signed-off-by: Lyude Paul Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/synaptics.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index 6f36e2d01e2e..65c9095eb517 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -170,6 +170,7 @@ static const char * const smbus_pnp_ids[] = { "LEN0048", /* X1 Carbon 3 */ "LEN0046", /* X250 */ "LEN004a", /* W541 */ + "LEN005b", /* P50 */ "LEN0071", /* T480 */ "LEN0072", /* X1 Carbon Gen 5 (2017) - Elan/ALPS trackpoint */ "LEN0073", /* X1 Carbon G5 (Elantech) */ -- GitLab From 58a3a4e82dea339ef011ff2510c11e21bc53e418 Mon Sep 17 00:00:00 2001 From: Christian Hoff Date: Mon, 12 Nov 2018 11:11:29 -0800 Subject: [PATCH 0346/1286] Input: matrix_keypad - check for errors from of_get_named_gpio() commit d55bda1b3e7c5a87f10da54fdda866a9a9cef30b upstream. "of_get_named_gpio()" returns a negative error value if it fails and drivers should check for this. This missing check was now added to the matrix_keypad driver. In my case "of_get_named_gpio()" returned -EPROBE_DEFER because the referenced GPIOs belong to an I/O expander, which was not yet probed at the point in time when the matrix_keypad driver was loading. Because the driver did not check for errors from the "of_get_named_gpio()" routine, it was assuming that "-EPROBE_DEFER" is actually a GPIO number and continued as usual, which led to further errors like this later on: WARNING: CPU: 3 PID: 167 at drivers/gpio/gpiolib.c:114 gpio_to_desc+0xc8/0xd0 invalid GPIO -517 Note that the "GPIO number" -517 in the error message above is actually "-EPROBE_DEFER". As part of the patch a misleading error message "no platform data defined" was also removed. This does not lead to information loss because the other error paths in matrix_keypad_parse_dt() already print an error. Signed-off-by: Christian Hoff Suggested-by: Sebastian Reichel Reviewed-by: Sebastian Reichel Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/keyboard/matrix_keypad.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/input/keyboard/matrix_keypad.c b/drivers/input/keyboard/matrix_keypad.c index 41614c185918..782dda68d93a 100644 --- a/drivers/input/keyboard/matrix_keypad.c +++ b/drivers/input/keyboard/matrix_keypad.c @@ -407,7 +407,7 @@ matrix_keypad_parse_dt(struct device *dev) struct matrix_keypad_platform_data *pdata; struct device_node *np = dev->of_node; unsigned int *gpios; - int i, nrow, ncol; + int ret, i, nrow, ncol; if (!np) { dev_err(dev, "device lacks DT data\n"); @@ -452,12 +452,19 @@ matrix_keypad_parse_dt(struct device *dev) return ERR_PTR(-ENOMEM); } - for (i = 0; i < pdata->num_row_gpios; i++) - gpios[i] = of_get_named_gpio(np, "row-gpios", i); + for (i = 0; i < nrow; i++) { + ret = of_get_named_gpio(np, "row-gpios", i); + if (ret < 0) + return ERR_PTR(ret); + gpios[i] = ret; + } - for (i = 0; i < pdata->num_col_gpios; i++) - gpios[pdata->num_row_gpios + i] = - of_get_named_gpio(np, "col-gpios", i); + for (i = 0; i < ncol; i++) { + ret = of_get_named_gpio(np, "col-gpios", i); + if (ret < 0) + return ERR_PTR(ret); + gpios[nrow + i] = ret; + } pdata->row_gpios = gpios; pdata->col_gpios = &gpios[pdata->num_row_gpios]; @@ -484,10 +491,8 @@ static int matrix_keypad_probe(struct platform_device *pdev) pdata = dev_get_platdata(&pdev->dev); if (!pdata) { pdata = matrix_keypad_parse_dt(&pdev->dev); - if (IS_ERR(pdata)) { - dev_err(&pdev->dev, "no platform data defined\n"); + if (IS_ERR(pdata)) return PTR_ERR(pdata); - } } else if (!pdata->keymap_data) { dev_err(&pdev->dev, "no keymap data defined\n"); return -EINVAL; -- GitLab From 4121029c4311c4e6298fc601bcb6b7dd2167b415 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Mon, 12 Nov 2018 11:23:39 -0800 Subject: [PATCH 0347/1286] Input: cros_ec_keyb - fix button/switch capability reports commit ac5722c1643a2fb75224c79b578214956d34f989 upstream. The cros_ec_keyb_bs array lists buttons and switches together, expecting that its users will match the appropriate type and bit fields. But cros_ec_keyb_register_bs() only checks the 'bit' field, which causes misreported input capabilities in some cases. For example, tablets (e.g., Scarlet -- a.k.a. Acer Chromebook Tab 10) were reporting a SW_LID capability, because EC_MKBP_POWER_BUTTON and EC_MKBP_LID_OPEN happen to share the same bit. (This has comedic effect on a tablet, in which a power-management daemon then thinks this "lid" is closed, and so puts the system to sleep as soon as it boots!) To fix this, check both the 'ev_type' and 'bit' fields before reporting the capability. Tested with a lid (Kevin / Samsung Chromebook Plus) and without a lid (Scarlet / Acer Chromebook Tab 10). This error got introduced when porting the feature from the downstream Chromium OS kernel to be upstreamed. Fixes: cdd7950e7aa4 ("input: cros_ec_keyb: Add non-matrix buttons and switches") Cc: Signed-off-by: Brian Norris Reviewed-by: Heiko Stuebner Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/keyboard/cros_ec_keyb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/input/keyboard/cros_ec_keyb.c b/drivers/input/keyboard/cros_ec_keyb.c index 79eb29550c34..0993b3f12df6 100644 --- a/drivers/input/keyboard/cros_ec_keyb.c +++ b/drivers/input/keyboard/cros_ec_keyb.c @@ -506,7 +506,8 @@ static int cros_ec_keyb_register_bs(struct cros_ec_keyb *ckdev) for (i = 0; i < ARRAY_SIZE(cros_ec_keyb_bs); i++) { const struct cros_ec_bs_map *map = &cros_ec_keyb_bs[i]; - if (buttons & BIT(map->bit)) + if ((map->ev_type == EV_KEY && (buttons & BIT(map->bit))) || + (map->ev_type == EV_SW && (switches & BIT(map->bit)))) input_set_capability(idev, map->ev_type, map->code); } -- GitLab From 1151c098512f148f409a9e6ec25b486ba3a312bf Mon Sep 17 00:00:00 2001 From: Patrick Gaskin Date: Mon, 12 Nov 2018 11:12:24 -0800 Subject: [PATCH 0348/1286] Input: elan_i2c - add ELAN0620 to the ACPI table commit 3ed64da3b790be7c63601e8ca6341b7dff74a660 upstream. Add ELAN0620 to the ACPI table to support the elan touchpad in the Lenovo IdeaPad 130-15IKB. Signed-off-by: Patrick Gaskin Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/elan_i2c_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c index 766d30a7b085..e56223c6df8f 100644 --- a/drivers/input/mouse/elan_i2c_core.c +++ b/drivers/input/mouse/elan_i2c_core.c @@ -1264,6 +1264,7 @@ static const struct acpi_device_id elan_acpi_id[] = { { "ELAN0618", 0 }, { "ELAN061C", 0 }, { "ELAN061D", 0 }, + { "ELAN0620", 0 }, { "ELAN0622", 0 }, { "ELAN1000", 0 }, { } -- GitLab From ec2c95c56ba7689fd295acd6d43696846b38f4e1 Mon Sep 17 00:00:00 2001 From: Noah Westervelt Date: Thu, 29 Nov 2018 10:10:35 -0800 Subject: [PATCH 0349/1286] Input: elan_i2c - add ACPI ID for Lenovo IdeaPad 330-15ARR commit ad33429cd02565c28404bb16ae7a4c2bdfda6626 upstream. Add ELAN061E to the ACPI table to support Elan touchpad found in Lenovo IdeaPad 330-15ARR. Signed-off-by: Noah Westervelt Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/elan_i2c_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c index e56223c6df8f..5e20be31cd73 100644 --- a/drivers/input/mouse/elan_i2c_core.c +++ b/drivers/input/mouse/elan_i2c_core.c @@ -1264,6 +1264,7 @@ static const struct acpi_device_id elan_acpi_id[] = { { "ELAN0618", 0 }, { "ELAN061C", 0 }, { "ELAN061D", 0 }, + { "ELAN061E", 0 }, { "ELAN0620", 0 }, { "ELAN0622", 0 }, { "ELAN1000", 0 }, -- GitLab From 61ffe9b932037aabc00d51bc9095f4a20ea90d56 Mon Sep 17 00:00:00 2001 From: Adam Wong Date: Thu, 29 Nov 2018 10:04:35 -0800 Subject: [PATCH 0350/1286] Input: elan_i2c - add support for ELAN0621 touchpad commit bf87ade0dd7f8cf19dac4d3161d5e86abe0c062b upstream. Added the ability to detect the ELAN0621 touchpad found in some Lenovo laptops. Signed-off-by: Adam Wong Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/elan_i2c_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c index 5e20be31cd73..368871a398a5 100644 --- a/drivers/input/mouse/elan_i2c_core.c +++ b/drivers/input/mouse/elan_i2c_core.c @@ -1266,6 +1266,7 @@ static const struct acpi_device_id elan_acpi_id[] = { { "ELAN061D", 0 }, { "ELAN061E", 0 }, { "ELAN0620", 0 }, + { "ELAN0621", 0 }, { "ELAN0622", 0 }, { "ELAN1000", 0 }, { } -- GitLab From 1aadbb4a325b81989c9dd454c44b846d590cda49 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Fri, 23 Nov 2018 09:06:36 +0800 Subject: [PATCH 0351/1286] btrfs: tree-checker: Don't check max block group size as current max chunk size limit is unreliable commit 10950929e994c5ecee149ff0873388d3c98f12b5 upstream. [BUG] A completely valid btrfs will refuse to mount, with error message like: BTRFS critical (device sdb2): corrupt leaf: root=2 block=239681536 slot=172 \ bg_start=12018974720 bg_len=10888413184, invalid block group size, \ have 10888413184 expect (0, 10737418240] This has been reported several times as the 4.19 kernel is now being used. The filesystem refuses to mount, but is otherwise ok and booting 4.18 is a workaround. Btrfs check returns no error, and all kernels used on this fs is later than 2011, which should all have the 10G size limit commit. [CAUSE] For a 12 devices btrfs, we could allocate a chunk larger than 10G due to stripe stripe bump up. __btrfs_alloc_chunk() |- max_stripe_size = 1G |- max_chunk_size = 10G |- data_stripe = 11 |- if (1G * 11 > 10G) { stripe_size = 976128930; stripe_size = round_up(976128930, SZ_16M) = 989855744 However the final stripe_size (989855744) * 11 = 10888413184, which is still larger than 10G. [FIX] For the comprehensive check, we need to do the full check at chunk read time, and rely on bg <-> chunk mapping to do the check. We could just skip the length check for now. Fixes: fce466eab7ac ("btrfs: tree-checker: Verify block_group_item") Cc: stable@vger.kernel.org # v4.19+ Reported-by: Wang Yugui Signed-off-by: Qu Wenruo Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/tree-checker.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/fs/btrfs/tree-checker.c b/fs/btrfs/tree-checker.c index f206aec1525d..ebc882281b39 100644 --- a/fs/btrfs/tree-checker.c +++ b/fs/btrfs/tree-checker.c @@ -348,13 +348,11 @@ static int check_block_group_item(struct btrfs_fs_info *fs_info, /* * Here we don't really care about alignment since extent allocator can - * handle it. We care more about the size, as if one block group is - * larger than maximum size, it's must be some obvious corruption. + * handle it. We care more about the size. */ - if (key->offset > BTRFS_MAX_DATA_CHUNK_SIZE || key->offset == 0) { + if (key->offset == 0) { block_group_err(fs_info, leaf, slot, - "invalid block group size, have %llu expect (0, %llu]", - key->offset, BTRFS_MAX_DATA_CHUNK_SIZE); + "invalid block group size 0"); return -EUCLEAN; } -- GitLab From 335cbe4df8b0d14cd43f207932b33eb8c756beb2 Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Tue, 6 Nov 2018 16:40:20 +0200 Subject: [PATCH 0352/1286] btrfs: Always try all copies when reading extent buffers commit f8397d69daef06d358430d3054662fb597e37c00 upstream. When a metadata read is served the endio routine btree_readpage_end_io_hook is called which eventually runs the tree-checker. If tree-checker fails to validate the read eb then it sets EXTENT_BUFFER_CORRUPT flag. This leads to btree_read_extent_buffer_pages wrongly assuming that all available copies of this extent buffer are wrong and failing prematurely. Fix this modify btree_read_extent_buffer_pages to read all copies of the data. This failure was exhibitted in xfstests btrfs/124 which would spuriously fail its balance operations. The reason was that when balance was run following re-introduction of the missing raid1 disk __btrfs_map_block would map the read request to stripe 0, which corresponded to devid 2 (the disk which is being removed in the test): item 2 key (FIRST_CHUNK_TREE CHUNK_ITEM 3553624064) itemoff 15975 itemsize 112 length 1073741824 owner 2 stripe_len 65536 type DATA|RAID1 io_align 65536 io_width 65536 sector_size 4096 num_stripes 2 sub_stripes 1 stripe 0 devid 2 offset 2156920832 dev_uuid 8466c350-ed0c-4c3b-b17d-6379b445d5c8 stripe 1 devid 1 offset 3553624064 dev_uuid 1265d8db-5596-477e-af03-df08eb38d2ca This caused read requests for a checksum item that to be routed to the stale disk which triggered the aforementioned logic involving EXTENT_BUFFER_CORRUPT flag. This then triggered cascading failures of the balance operation. Fixes: a826d6dcb32d ("Btrfs: check items for correctness as we search") CC: stable@vger.kernel.org # 4.4+ Suggested-by: Qu Wenruo Reviewed-by: Qu Wenruo Signed-off-by: Nikolay Borisov Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/disk-io.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index e42673477c25..858d5812eb8f 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -451,9 +451,9 @@ static int btree_read_extent_buffer_pages(struct btrfs_fs_info *fs_info, int mirror_num = 0; int failed_mirror = 0; - clear_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags); io_tree = &BTRFS_I(fs_info->btree_inode)->io_tree; while (1) { + clear_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags); ret = read_extent_buffer_pages(io_tree, eb, WAIT_COMPLETE, btree_get_extent, mirror_num); if (!ret) { @@ -464,14 +464,6 @@ static int btree_read_extent_buffer_pages(struct btrfs_fs_info *fs_info, ret = -EIO; } - /* - * This buffer's crc is fine, but its contents are corrupted, so - * there is no reason to read the other copies, they won't be - * any less wrong. - */ - if (test_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags)) - break; - num_copies = btrfs_num_copies(fs_info, eb->start, eb->len); if (num_copies == 1) -- GitLab From f4069a6cf6faf910a90f469b72e27bc29e4beccd Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 30 Nov 2018 15:51:56 +0300 Subject: [PATCH 0353/1286] ARC: change defconfig defaults to ARCv2 commit b7cc40c32a8bfa6f2581a71747f6a7d491fe43ba upstream. Change the default defconfig (used with 'make defconfig') to the ARCv2 nsim_hs_defconfig, and also switch the default Kconfig ISA selection to ARCv2. This allows several default defconfigs (e.g. make defconfig, make allnoconfig, make tinyconfig) to all work with ARCv2 by default. Note since we change default architecture from ARCompact to ARCv2 it's required to explicitly mention architecture type in ARCompact defconfigs otherwise ARCv2 will be implied and binaries will be generated for ARCv2. Cc: # 4.4.x Signed-off-by: Kevin Hilman Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta Signed-off-by: Greg Kroah-Hartman --- arch/arc/Kconfig | 2 +- arch/arc/Makefile | 2 +- arch/arc/configs/axs101_defconfig | 1 + arch/arc/configs/nps_defconfig | 1 + arch/arc/configs/nsim_700_defconfig | 1 + arch/arc/configs/nsimosci_defconfig | 1 + arch/arc/configs/tb10x_defconfig | 1 + 7 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 8ff066090680..9d06c9478a0d 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -109,7 +109,7 @@ endmenu choice prompt "ARC Instruction Set" - default ISA_ARCOMPACT + default ISA_ARCV2 config ISA_ARCOMPACT bool "ARCompact ISA" diff --git a/arch/arc/Makefile b/arch/arc/Makefile index 7c6c97782022..2917f56f0ea4 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -6,7 +6,7 @@ # published by the Free Software Foundation. # -KBUILD_DEFCONFIG := nsim_700_defconfig +KBUILD_DEFCONFIG := nsim_hs_defconfig cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__ cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7 diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig index ece78630d711..77df85de1121 100644 --- a/arch/arc/configs/axs101_defconfig +++ b/arch/arc/configs/axs101_defconfig @@ -15,6 +15,7 @@ CONFIG_PERF_EVENTS=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set +CONFIG_ISA_ARCOMPACT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig index 7c9c706ae7f6..ba337d3d3a17 100644 --- a/arch/arc/configs/nps_defconfig +++ b/arch/arc/configs/nps_defconfig @@ -15,6 +15,7 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set +CONFIG_ISA_ARCOMPACT=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y diff --git a/arch/arc/configs/nsim_700_defconfig b/arch/arc/configs/nsim_700_defconfig index b1a78222699c..cdb06417d3d9 100644 --- a/arch/arc/configs/nsim_700_defconfig +++ b/arch/arc/configs/nsim_700_defconfig @@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set +CONFIG_ISA_ARCOMPACT=y CONFIG_KPROBES=y CONFIG_MODULES=y # CONFIG_LBDAF is not set diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig index 14377b8234f7..8cbcbc185359 100644 --- a/arch/arc/configs/nsimosci_defconfig +++ b/arch/arc/configs/nsimosci_defconfig @@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y CONFIG_PERF_EVENTS=y # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set +CONFIG_ISA_ARCOMPACT=y CONFIG_KPROBES=y CONFIG_MODULES=y # CONFIG_LBDAF is not set diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig index f30182549395..0130e29eeca1 100644 --- a/arch/arc/configs/tb10x_defconfig +++ b/arch/arc/configs/tb10x_defconfig @@ -19,6 +19,7 @@ CONFIG_KALLSYMS_ALL=y # CONFIG_AIO is not set CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set +CONFIG_ISA_ARCOMPACT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y -- GitLab From 097c13e1b78d48c1a3a75dbfabc10736863056a7 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 20 Nov 2018 13:30:19 +0300 Subject: [PATCH 0354/1286] arc: [devboards] Add support of NFSv3 ACL commit 6b04114f6fae5e84d33404c2970b1949c032546e upstream. By default NFSv3 doesn't support ACL (Access Control Lists) which might be quite convenient to have so that mounted NFS behaves exactly as any other local file-system. In particular missing support of ACL makes umask useless. This among other thigs fixes Glibc's "nptl/tst-umask1". Signed-off-by: Alexey Brodkin Cc: Cupertino Miranda Cc: stable@vger.kernel.org #4.14+ Signed-off-by: Vineet Gupta Signed-off-by: Greg Kroah-Hartman --- arch/arc/configs/axs101_defconfig | 1 + arch/arc/configs/axs103_defconfig | 1 + arch/arc/configs/axs103_smp_defconfig | 1 + arch/arc/configs/hsdk_defconfig | 1 + arch/arc/configs/nps_defconfig | 1 + arch/arc/configs/nsimosci_defconfig | 1 + arch/arc/configs/nsimosci_hs_defconfig | 1 + arch/arc/configs/nsimosci_hs_smp_defconfig | 1 + arch/arc/configs/vdk_hs38_defconfig | 1 + arch/arc/configs/vdk_hs38_smp_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig index 77df85de1121..5d5ba2104ba7 100644 --- a/arch/arc/configs/axs101_defconfig +++ b/arch/arc/configs/axs101_defconfig @@ -99,6 +99,7 @@ CONFIG_VFAT_FS=y CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig index 240c9251a7d4..0874db2d48a8 100644 --- a/arch/arc/configs/axs103_defconfig +++ b/arch/arc/configs/axs103_defconfig @@ -97,6 +97,7 @@ CONFIG_VFAT_FS=y CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig index af54b96abee0..cf5df0e1cb08 100644 --- a/arch/arc/configs/axs103_smp_defconfig +++ b/arch/arc/configs/axs103_smp_defconfig @@ -100,6 +100,7 @@ CONFIG_VFAT_FS=y CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig index 762b1fcd93dc..083560e9e571 100644 --- a/arch/arc/configs/hsdk_defconfig +++ b/arch/arc/configs/hsdk_defconfig @@ -66,6 +66,7 @@ CONFIG_EXT3_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig index ba337d3d3a17..9121c6ba15d0 100644 --- a/arch/arc/configs/nps_defconfig +++ b/arch/arc/configs/nps_defconfig @@ -75,6 +75,7 @@ CONFIG_PROC_KCORE=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y CONFIG_DEBUG_INFO=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig index 8cbcbc185359..c4577bd9196c 100644 --- a/arch/arc/configs/nsimosci_defconfig +++ b/arch/arc/configs/nsimosci_defconfig @@ -70,5 +70,6 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/arc/configs/nsimosci_hs_defconfig b/arch/arc/configs/nsimosci_hs_defconfig index 7e61c923a3cd..b20692c82d3c 100644 --- a/arch/arc/configs/nsimosci_hs_defconfig +++ b/arch/arc/configs/nsimosci_hs_defconfig @@ -68,5 +68,6 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/arc/configs/nsimosci_hs_smp_defconfig b/arch/arc/configs/nsimosci_hs_smp_defconfig index 299fbe8003b2..5ad4949af6d0 100644 --- a/arch/arc/configs/nsimosci_hs_smp_defconfig +++ b/arch/arc/configs/nsimosci_hs_smp_defconfig @@ -79,6 +79,7 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FTRACE=y diff --git a/arch/arc/configs/vdk_hs38_defconfig b/arch/arc/configs/vdk_hs38_defconfig index 4fcf4f2503f6..4587c9af5afe 100644 --- a/arch/arc/configs/vdk_hs38_defconfig +++ b/arch/arc/configs/vdk_hs38_defconfig @@ -88,6 +88,7 @@ CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig index 7b71464f6c2f..1855aa995bc9 100644 --- a/arch/arc/configs/vdk_hs38_smp_defconfig +++ b/arch/arc/configs/vdk_hs38_smp_defconfig @@ -92,6 +92,7 @@ CONFIG_NTFS_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y # CONFIG_ENABLE_WARN_DEPRECATED is not set -- GitLab From 99bfa7bc16c3b5c4bf06d3885e535060dd5cfeef Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Fri, 16 Nov 2018 13:43:17 +0100 Subject: [PATCH 0355/1286] udf: Allow mounting volumes with incorrect identification strings commit b54e41f5efcb4316b2f30b30c2535cc194270373 upstream. Commit c26f6c615788 ("udf: Fix conversion of 'dstring' fields to UTF8") started to be more strict when checking whether converted strings are properly formatted. Sudip reports that there are DVDs where the volume identification string is actually too long - UDF reports: [ 632.309320] UDF-fs: incorrect dstring lengths (32/32) during mount and fails the mount. This is mostly harmless failure as we don't need volume identification (and even less volume set identification) for anything. So just truncate the volume identification string if it is too long and replace it with 'Invalid' if we just cannot convert it for other reasons. This keeps slightly incorrect media still mountable. CC: stable@vger.kernel.org Fixes: c26f6c615788 ("udf: Fix conversion of 'dstring' fields to UTF8") Reported-and-tested-by: Sudip Mukherjee Signed-off-by: Jan Kara Signed-off-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- fs/udf/super.c | 16 ++++++++++------ fs/udf/unicode.c | 14 +++++++++++--- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/fs/udf/super.c b/fs/udf/super.c index 9b0d6562d0a1..242d960df9a1 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -922,16 +922,20 @@ static int udf_load_pvoldesc(struct super_block *sb, sector_t block) } ret = udf_dstrCS0toUTF8(outstr, 31, pvoldesc->volIdent, 32); - if (ret < 0) - goto out_bh; - - strncpy(UDF_SB(sb)->s_volume_ident, outstr, ret); + if (ret < 0) { + strcpy(UDF_SB(sb)->s_volume_ident, "InvalidName"); + pr_warn("incorrect volume identification, setting to " + "'InvalidName'\n"); + } else { + strncpy(UDF_SB(sb)->s_volume_ident, outstr, ret); + } udf_debug("volIdent[] = '%s'\n", UDF_SB(sb)->s_volume_ident); ret = udf_dstrCS0toUTF8(outstr, 127, pvoldesc->volSetIdent, 128); - if (ret < 0) + if (ret < 0) { + ret = 0; goto out_bh; - + } outstr[ret] = 0; udf_debug("volSetIdent[] = '%s'\n", outstr); diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c index 3a3be23689b3..61a1738895b7 100644 --- a/fs/udf/unicode.c +++ b/fs/udf/unicode.c @@ -341,6 +341,11 @@ static int udf_name_to_CS0(uint8_t *ocu, int ocu_max_len, return u_len; } +/* + * Convert CS0 dstring to output charset. Warning: This function may truncate + * input string if it is too long as it is used for informational strings only + * and it is better to truncate the string than to refuse mounting a media. + */ int udf_dstrCS0toUTF8(uint8_t *utf_o, int o_len, const uint8_t *ocu_i, int i_len) { @@ -349,9 +354,12 @@ int udf_dstrCS0toUTF8(uint8_t *utf_o, int o_len, if (i_len > 0) { s_len = ocu_i[i_len - 1]; if (s_len >= i_len) { - pr_err("incorrect dstring lengths (%d/%d)\n", - s_len, i_len); - return -EINVAL; + pr_warn("incorrect dstring lengths (%d/%d)," + " truncating\n", s_len, i_len); + s_len = i_len - 1; + /* 2-byte encoding? Need to round properly... */ + if (ocu_i[0] == 16) + s_len -= (s_len - 1) & 2; } } -- GitLab From b92cee8097d99ec641521975b5fa6eb907ab5361 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 29 Oct 2017 01:50:06 +0900 Subject: [PATCH 0356/1286] reset: make device_reset_optional() really optional commit 1554bbd4ad401b7f0f916c0891874111c10befe5 upstream. Commit bb475230b8e5 ("reset: make optional functions really optional") converted *_get_optional* functions, but device_reset_optional() was left behind. Convert it in the same way. Signed-off-by: Masahiro Yamada Signed-off-by: Philipp Zabel Cc: Dinh Nguyen Signed-off-by: Greg Kroah-Hartman --- drivers/reset/core.c | 9 +++++---- include/linux/reset.h | 28 +++++++++++++--------------- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/reset/core.c b/drivers/reset/core.c index 1d21c6f7d56c..da4292e9de97 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -566,17 +566,18 @@ EXPORT_SYMBOL_GPL(__devm_reset_control_get); * device_reset - find reset controller associated with the device * and perform reset * @dev: device to be reset by the controller + * @optional: whether it is optional to reset the device * - * Convenience wrapper for reset_control_get() and reset_control_reset(). + * Convenience wrapper for __reset_control_get() and reset_control_reset(). * This is useful for the common case of devices with single, dedicated reset * lines. */ -int device_reset(struct device *dev) +int __device_reset(struct device *dev, bool optional) { struct reset_control *rstc; int ret; - rstc = reset_control_get(dev, NULL); + rstc = __reset_control_get(dev, NULL, 0, 0, optional); if (IS_ERR(rstc)) return PTR_ERR(rstc); @@ -586,7 +587,7 @@ int device_reset(struct device *dev) return ret; } -EXPORT_SYMBOL_GPL(device_reset); +EXPORT_SYMBOL_GPL(__device_reset); /** * APIs to manage an array of reset controls. diff --git a/include/linux/reset.h b/include/linux/reset.h index 4c7871ddf3c6..b681019fc04c 100644 --- a/include/linux/reset.h +++ b/include/linux/reset.h @@ -20,22 +20,16 @@ struct reset_control *__reset_control_get(struct device *dev, const char *id, int index, bool shared, bool optional); void reset_control_put(struct reset_control *rstc); +int __device_reset(struct device *dev, bool optional); struct reset_control *__devm_reset_control_get(struct device *dev, const char *id, int index, bool shared, bool optional); -int __must_check device_reset(struct device *dev); - struct reset_control *devm_reset_control_array_get(struct device *dev, bool shared, bool optional); struct reset_control *of_reset_control_array_get(struct device_node *np, bool shared, bool optional); -static inline int device_reset_optional(struct device *dev) -{ - return device_reset(dev); -} - #else static inline int reset_control_reset(struct reset_control *rstc) @@ -62,15 +56,9 @@ static inline void reset_control_put(struct reset_control *rstc) { } -static inline int __must_check device_reset(struct device *dev) +static inline int __device_reset(struct device *dev, bool optional) { - WARN_ON(1); - return -ENOTSUPP; -} - -static inline int device_reset_optional(struct device *dev) -{ - return -ENOTSUPP; + return optional ? 0 : -ENOTSUPP; } static inline struct reset_control *__of_reset_control_get( @@ -109,6 +97,16 @@ of_reset_control_array_get(struct device_node *np, bool shared, bool optional) #endif /* CONFIG_RESET_CONTROLLER */ +static inline int __must_check device_reset(struct device *dev) +{ + return __device_reset(dev, false); +} + +static inline int device_reset_optional(struct device *dev) +{ + return __device_reset(dev, true); +} + /** * reset_control_get_exclusive - Lookup and obtain an exclusive reference * to a reset controller. -- GitLab From d2e29b46a9cf4e733e147442a20dbba376decc26 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 29 Oct 2017 01:50:07 +0900 Subject: [PATCH 0357/1286] reset: remove remaining WARN_ON() in commit bb6c7768385b200063a14d6615cc1246c3d00760 upstream. Commit bb475230b8e5 ("reset: make optional functions really optional") gave a new meaning to _get_optional variants. The differentiation by WARN_ON() is not needed any more. We already have inconsistency about this; (devm_)reset_control_get_exclusive() has WARN_ON() check, but of_reset_control_get_exclusive() does not. Signed-off-by: Masahiro Yamada Signed-off-by: Philipp Zabel Cc: Dinh Nguyen Signed-off-by: Greg Kroah-Hartman --- include/linux/reset.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/linux/reset.h b/include/linux/reset.h index b681019fc04c..ed6fb0290797 100644 --- a/include/linux/reset.h +++ b/include/linux/reset.h @@ -125,9 +125,6 @@ static inline int device_reset_optional(struct device *dev) static inline struct reset_control * __must_check reset_control_get_exclusive(struct device *dev, const char *id) { -#ifndef CONFIG_RESET_CONTROLLER - WARN_ON(1); -#endif return __reset_control_get(dev, id, 0, false, false); } @@ -273,9 +270,6 @@ static inline struct reset_control * __must_check devm_reset_control_get_exclusive(struct device *dev, const char *id) { -#ifndef CONFIG_RESET_CONTROLLER - WARN_ON(1); -#endif return __devm_reset_control_get(dev, id, 0, false, false); } -- GitLab From 60720df8bf43e8ca2ce1a17936904a52129c8471 Mon Sep 17 00:00:00 2001 From: Pavel Tikhomirov Date: Fri, 30 Nov 2018 14:09:00 -0800 Subject: [PATCH 0358/1286] mm: cleancache: fix corruption on missed inode invalidation commit 6ff38bd40230af35e446239396e5fc8ebd6a5248 upstream. If all pages are deleted from the mapping by memory reclaim and also moved to the cleancache: __delete_from_page_cache (no shadow case) unaccount_page_cache_page cleancache_put_page page_cache_delete mapping->nrpages -= nr (nrpages becomes 0) We don't clean the cleancache for an inode after final file truncation (removal). truncate_inode_pages_final check (nrpages || nrexceptional) is false no truncate_inode_pages no cleancache_invalidate_inode(mapping) These way when reading the new file created with same inode we may get these trash leftover pages from cleancache and see wrong data instead of the contents of the new file. Fix it by always doing truncate_inode_pages which is already ready for nrpages == 0 && nrexceptional == 0 case and just invalidates inode. [akpm@linux-foundation.org: add comment, per Jan] Link: http://lkml.kernel.org/r/20181112095734.17979-1-ptikhomirov@virtuozzo.com Fixes: commit 91b0abe36a7b ("mm + fs: store shadow entries in page cache") Signed-off-by: Pavel Tikhomirov Reviewed-by: Vasily Averin Reviewed-by: Andrey Ryabinin Reviewed-by: Jan Kara Cc: Johannes Weiner Cc: Mel Gorman Cc: Matthew Wilcox Cc: Andi Kleen Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Vasily Averin Signed-off-by: Greg Kroah-Hartman --- mm/truncate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/mm/truncate.c b/mm/truncate.c index 2330223841fb..d3a2737cc188 100644 --- a/mm/truncate.c +++ b/mm/truncate.c @@ -471,9 +471,13 @@ void truncate_inode_pages_final(struct address_space *mapping) */ spin_lock_irq(&mapping->tree_lock); spin_unlock_irq(&mapping->tree_lock); - - truncate_inode_pages(mapping, 0); } + + /* + * Cleancache needs notification even if there are no pages or shadow + * entries. + */ + truncate_inode_pages(mapping, 0); } EXPORT_SYMBOL(truncate_inode_pages_final); -- GitLab From 402519439ccb9410faf6287bf98f99817bd0c354 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Oct 2017 19:05:44 +0200 Subject: [PATCH 0359/1286] thermal/drivers/hisi: Remove the multiple sensors support commit ff4ec2997df8fe7cc40513dbe5f86d9f88fb6be7 upstream. By essence, the tsensor does not really support multiple sensor at the same time. It allows to set a sensor and use it to get the temperature, another sensor could be switched but with a delay of 3-5ms. It is difficult to read simultaneously several sensors without a big delay. Today, just one sensor is used, it is not necessary to deal with multiple sensors in the code. Remove them and if it is needed in the future add them on top of a code which will be clean up in the meantime. Signed-off-by: Daniel Lezcano Reviewed-by: Leo Yan Acked-by: Wangtao (Kevin, Kirin) Signed-off-by: Eduardo Valentin Signed-off-by: Rafael David Tinoco Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 75 +++++++++------------------------- 1 file changed, 19 insertions(+), 56 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index 6d8906d65476..aecbfe9fc8f2 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -40,6 +40,7 @@ #define HISI_TEMP_STEP (784) #define HISI_MAX_SENSORS 4 +#define HISI_DEFAULT_SENSOR 2 struct hisi_thermal_sensor { struct hisi_thermal_data *thermal; @@ -54,9 +55,8 @@ struct hisi_thermal_data { struct mutex thermal_lock; /* protects register data */ struct platform_device *pdev; struct clk *clk; - struct hisi_thermal_sensor sensors[HISI_MAX_SENSORS]; - - int irq, irq_bind_sensor; + struct hisi_thermal_sensor sensors; + int irq; bool irq_enabled; void __iomem *regs; @@ -133,7 +133,7 @@ static void hisi_thermal_enable_bind_irq_sensor mutex_lock(&data->thermal_lock); - sensor = &data->sensors[data->irq_bind_sensor]; + sensor = &data->sensors; /* setting the hdak time */ writel(0x0, data->regs + TEMP0_CFG); @@ -181,31 +181,8 @@ static int hisi_thermal_get_temp(void *_sensor, int *temp) struct hisi_thermal_sensor *sensor = _sensor; struct hisi_thermal_data *data = sensor->thermal; - int sensor_id = -1, i; - long max_temp = 0; - *temp = hisi_thermal_get_sensor_temp(data, sensor); - sensor->sensor_temp = *temp; - - for (i = 0; i < HISI_MAX_SENSORS; i++) { - if (!data->sensors[i].tzd) - continue; - - if (data->sensors[i].sensor_temp >= max_temp) { - max_temp = data->sensors[i].sensor_temp; - sensor_id = i; - } - } - - /* If no sensor has been enabled, then skip to enable irq */ - if (sensor_id == -1) - return 0; - - mutex_lock(&data->thermal_lock); - data->irq_bind_sensor = sensor_id; - mutex_unlock(&data->thermal_lock); - dev_dbg(&data->pdev->dev, "id=%d, irq=%d, temp=%d, thres=%d\n", sensor->id, data->irq_enabled, *temp, sensor->thres_temp); /* @@ -218,7 +195,7 @@ static int hisi_thermal_get_temp(void *_sensor, int *temp) return 0; } - if (max_temp < sensor->thres_temp) { + if (*temp < sensor->thres_temp) { data->irq_enabled = true; hisi_thermal_enable_bind_irq_sensor(data); enable_irq(data->irq); @@ -245,22 +222,16 @@ static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) { struct hisi_thermal_data *data = dev; struct hisi_thermal_sensor *sensor; - int i; mutex_lock(&data->thermal_lock); - sensor = &data->sensors[data->irq_bind_sensor]; + sensor = &data->sensors; dev_crit(&data->pdev->dev, "THERMAL ALARM: T > %d\n", sensor->thres_temp); mutex_unlock(&data->thermal_lock); - for (i = 0; i < HISI_MAX_SENSORS; i++) { - if (!data->sensors[i].tzd) - continue; - - thermal_zone_device_update(data->sensors[i].tzd, - THERMAL_EVENT_UNSPECIFIED); - } + thermal_zone_device_update(data->sensors.tzd, + THERMAL_EVENT_UNSPECIFIED); return IRQ_HANDLED; } @@ -317,7 +288,6 @@ static int hisi_thermal_probe(struct platform_device *pdev) { struct hisi_thermal_data *data; struct resource *res; - int i; int ret; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); @@ -359,14 +329,13 @@ static int hisi_thermal_probe(struct platform_device *pdev) hisi_thermal_enable_bind_irq_sensor(data); data->irq_enabled = true; - for (i = 0; i < HISI_MAX_SENSORS; ++i) { - ret = hisi_thermal_register_sensor(pdev, data, - &data->sensors[i], i); - if (ret) - dev_err(&pdev->dev, - "failed to register thermal sensor: %d\n", ret); - else - hisi_thermal_toggle_sensor(&data->sensors[i], true); + ret = hisi_thermal_register_sensor(pdev, data, + &data->sensors, + HISI_DEFAULT_SENSOR); + if (ret) { + dev_err(&pdev->dev, "failed to register thermal sensor: %d\n", + ret); + return ret; } ret = devm_request_threaded_irq(&pdev->dev, data->irq, @@ -378,6 +347,8 @@ static int hisi_thermal_probe(struct platform_device *pdev) return ret; } + hisi_thermal_toggle_sensor(&data->sensors, true); + enable_irq(data->irq); return 0; @@ -386,17 +357,9 @@ static int hisi_thermal_probe(struct platform_device *pdev) static int hisi_thermal_remove(struct platform_device *pdev) { struct hisi_thermal_data *data = platform_get_drvdata(pdev); - int i; - - for (i = 0; i < HISI_MAX_SENSORS; i++) { - struct hisi_thermal_sensor *sensor = &data->sensors[i]; - - if (!sensor->tzd) - continue; - - hisi_thermal_toggle_sensor(sensor, false); - } + struct hisi_thermal_sensor *sensor = &data->sensors; + hisi_thermal_toggle_sensor(sensor, false); hisi_thermal_disable_sensor(data); clk_disable_unprepare(data->clk); -- GitLab From e29649e49c81b1a1a78174f70c2e1ddf41f7832f Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Oct 2017 19:05:48 +0200 Subject: [PATCH 0360/1286] thermal/drivers/hisi: Remove pointless lock commit 2d4fa7b4c6f8080ced2e8237c9f46fb1fc110d64 upstream. The threaded interrupt inspect the sensors structure to look in the temp threshold field, but this field is read-only in all the code, except in the probe function before the threaded interrupt is set. In other words there is not race window in the threaded interrupt when reading the field value. Signed-off-by: Daniel Lezcano Reviewed-by: Leo Yan Signed-off-by: Eduardo Valentin Signed-off-by: Rafael David Tinoco Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index aecbfe9fc8f2..0c2966c285b1 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -221,14 +221,10 @@ static irqreturn_t hisi_thermal_alarm_irq(int irq, void *dev) static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) { struct hisi_thermal_data *data = dev; - struct hisi_thermal_sensor *sensor; - - mutex_lock(&data->thermal_lock); - sensor = &data->sensors; + struct hisi_thermal_sensor *sensor = &data->sensors; dev_crit(&data->pdev->dev, "THERMAL ALARM: T > %d\n", sensor->thres_temp); - mutex_unlock(&data->thermal_lock); thermal_zone_device_update(data->sensors.tzd, THERMAL_EVENT_UNSPECIFIED); -- GitLab From f7105bd03755272a0e434ddc54e3a78dae2ed0c6 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Oct 2017 19:05:49 +0200 Subject: [PATCH 0361/1286] thermal/drivers/hisi: Encapsulate register writes into helpers commit 1e11b014271ceccb5ea04ae58f4829ac8209a86d upstream. Hopefully, the function name can help to clarify the semantic of the operations when writing in the register. Signed-off-by: Daniel Lezcano Signed-off-by: Eduardo Valentin Signed-off-by: Rafael David Tinoco Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 92 ++++++++++++++++++++++++++-------- 1 file changed, 70 insertions(+), 22 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index 0c2966c285b1..a803043f37ae 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -26,6 +26,7 @@ #include "thermal_core.h" +#define TEMP0_LAG (0x0) #define TEMP0_TH (0x4) #define TEMP0_RST_TH (0x8) #define TEMP0_CFG (0xC) @@ -96,6 +97,56 @@ static inline long hisi_thermal_round_temp(int temp) hisi_thermal_temp_to_step(temp)); } +static inline void hisi_thermal_set_lag(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_LAG); +} + +static inline void hisi_thermal_alarm_clear(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_INT_CLR); +} + +static inline void hisi_thermal_alarm_enable(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_INT_EN); +} + +static inline void hisi_thermal_alarm_set(void __iomem *addr, int temp) +{ + writel(hisi_thermal_temp_to_step(temp) | 0x0FFFFFF00, addr + TEMP0_TH); +} + +static inline void hisi_thermal_reset_set(void __iomem *addr, int temp) +{ + writel(hisi_thermal_temp_to_step(temp), addr + TEMP0_RST_TH); +} + +static inline void hisi_thermal_reset_enable(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_RST_MSK); +} + +static inline void hisi_thermal_enable(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_EN); +} + +static inline void hisi_thermal_sensor_select(void __iomem *addr, int sensor) +{ + writel((sensor << 12), addr + TEMP0_CFG); +} + +static inline int hisi_thermal_get_temperature(void __iomem *addr) +{ + return hisi_thermal_step_to_temp(readl(addr + TEMP0_VALUE)); +} + +static inline void hisi_thermal_hdak_set(void __iomem *addr, int value) +{ + writel(value, addr + TEMP0_CFG); +} + static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data, struct hisi_thermal_sensor *sensor) { @@ -104,22 +155,21 @@ static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data, mutex_lock(&data->thermal_lock); /* disable interrupt */ - writel(0x0, data->regs + TEMP0_INT_EN); - writel(0x1, data->regs + TEMP0_INT_CLR); + hisi_thermal_alarm_enable(data->regs, 0); + hisi_thermal_alarm_clear(data->regs, 1); /* disable module firstly */ - writel(0x0, data->regs + TEMP0_EN); + hisi_thermal_enable(data->regs, 0); /* select sensor id */ - writel((sensor->id << 12), data->regs + TEMP0_CFG); + hisi_thermal_sensor_select(data->regs, sensor->id); /* enable module */ - writel(0x1, data->regs + TEMP0_EN); + hisi_thermal_enable(data->regs, 1); usleep_range(3000, 5000); - val = readl(data->regs + TEMP0_VALUE); - val = hisi_thermal_step_to_temp(val); + val = hisi_thermal_get_temperature(data->regs); mutex_unlock(&data->thermal_lock); @@ -136,28 +186,26 @@ static void hisi_thermal_enable_bind_irq_sensor sensor = &data->sensors; /* setting the hdak time */ - writel(0x0, data->regs + TEMP0_CFG); + hisi_thermal_hdak_set(data->regs, 0); /* disable module firstly */ - writel(0x0, data->regs + TEMP0_RST_MSK); - writel(0x0, data->regs + TEMP0_EN); + hisi_thermal_reset_enable(data->regs, 0); + hisi_thermal_enable(data->regs, 0); /* select sensor id */ - writel((sensor->id << 12), data->regs + TEMP0_CFG); + hisi_thermal_sensor_select(data->regs, sensor->id); /* enable for interrupt */ - writel(hisi_thermal_temp_to_step(sensor->thres_temp) | 0x0FFFFFF00, - data->regs + TEMP0_TH); + hisi_thermal_alarm_set(data->regs, sensor->thres_temp); - writel(hisi_thermal_temp_to_step(HISI_TEMP_RESET), - data->regs + TEMP0_RST_TH); + hisi_thermal_reset_set(data->regs, HISI_TEMP_RESET); /* enable module */ - writel(0x1, data->regs + TEMP0_RST_MSK); - writel(0x1, data->regs + TEMP0_EN); + hisi_thermal_reset_enable(data->regs, 1); + hisi_thermal_enable(data->regs, 1); - writel(0x0, data->regs + TEMP0_INT_CLR); - writel(0x1, data->regs + TEMP0_INT_EN); + hisi_thermal_alarm_clear(data->regs, 0); + hisi_thermal_alarm_enable(data->regs, 1); usleep_range(3000, 5000); @@ -169,9 +217,9 @@ static void hisi_thermal_disable_sensor(struct hisi_thermal_data *data) mutex_lock(&data->thermal_lock); /* disable sensor module */ - writel(0x0, data->regs + TEMP0_INT_EN); - writel(0x0, data->regs + TEMP0_RST_MSK); - writel(0x0, data->regs + TEMP0_EN); + hisi_thermal_enable(data->regs, 0); + hisi_thermal_alarm_enable(data->regs, 0); + hisi_thermal_reset_enable(data->regs, 0); mutex_unlock(&data->thermal_lock); } -- GitLab From aa6e035f259a5a4402a204565b7b2fb26bbeaaf2 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Oct 2017 19:05:50 +0200 Subject: [PATCH 0362/1286] thermal/drivers/hisi: Fix configuration register setting commit b424315a287c70eeb5f920f84c92492bd2f5658e upstream. The TEMP0_CFG configuration register contains different field to set up the temperature controller. However in the code, nothing prevents a setup to overwrite the previous one: eg. writing the hdak value overwrites the sensor selection, the sensor selection overwrites the hdak value. In order to prevent such thing, use a regmap-like mechanism by reading the value before, set the corresponding bits and write the result. Signed-off-by: Daniel Lezcano Signed-off-by: Eduardo Valentin Signed-off-by: Rafael David Tinoco Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index a803043f37ae..31b52ebf426f 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -30,6 +30,8 @@ #define TEMP0_TH (0x4) #define TEMP0_RST_TH (0x8) #define TEMP0_CFG (0xC) +#define TEMP0_CFG_SS_MSK (0xF000) +#define TEMP0_CFG_HDAK_MSK (0x30) #define TEMP0_EN (0x10) #define TEMP0_INT_EN (0x14) #define TEMP0_INT_CLR (0x18) @@ -132,19 +134,41 @@ static inline void hisi_thermal_enable(void __iomem *addr, int value) writel(value, addr + TEMP0_EN); } -static inline void hisi_thermal_sensor_select(void __iomem *addr, int sensor) +static inline int hisi_thermal_get_temperature(void __iomem *addr) { - writel((sensor << 12), addr + TEMP0_CFG); + return hisi_thermal_step_to_temp(readl(addr + TEMP0_VALUE)); } -static inline int hisi_thermal_get_temperature(void __iomem *addr) +/* + * Temperature configuration register - Sensor selection + * + * Bits [19:12] + * + * 0x0: local sensor (default) + * 0x1: remote sensor 1 (ACPU cluster 1) + * 0x2: remote sensor 2 (ACPU cluster 0) + * 0x3: remote sensor 3 (G3D) + */ +static inline void hisi_thermal_sensor_select(void __iomem *addr, int sensor) { - return hisi_thermal_step_to_temp(readl(addr + TEMP0_VALUE)); + writel((readl(addr + TEMP0_CFG) & ~TEMP0_CFG_SS_MSK) | + (sensor << 12), addr + TEMP0_CFG); } +/* + * Temperature configuration register - Hdak conversion polling interval + * + * Bits [5:4] + * + * 0x0 : 0.768 ms + * 0x1 : 6.144 ms + * 0x2 : 49.152 ms + * 0x3 : 393.216 ms + */ static inline void hisi_thermal_hdak_set(void __iomem *addr, int value) { - writel(value, addr + TEMP0_CFG); + writel((readl(addr + TEMP0_CFG) & ~TEMP0_CFG_HDAK_MSK) | + (value << 4), addr + TEMP0_CFG); } static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data, -- GitLab From dd9989eda8327d9894f8f2c4812ca7dd085fad51 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 19 Oct 2017 19:05:51 +0200 Subject: [PATCH 0363/1286] thermal/drivers/hisi: Remove costly sensor inspection commit 10d7e9a9181f4637640f388d334c6740c1b5d0e8 upstream. The sensor is all setup, bind, resetted, acked, etc... every single second. That was the way to workaround a problem with the interrupt bouncing again and again. With the following changes, we fix all in one: - Do the setup, one time, at probe time - Add the IRQF_ONESHOT, ack the interrupt in the threaded handler - Remove the interrupt handler - Set the correct value for the LAG register - Remove all the irq_enabled stuff in the code as the interruption handling is fixed - Remove the 3ms delay - Reorder the initialization routine to be in the right order It ends up to a nicer code and more efficient, the 3-5ms delay is removed from the get_temp() path. Signed-off-by: Daniel Lezcano Reviewed-by: Leo Yan Tested-by: Leo Yan Signed-off-by: Eduardo Valentin Signed-off-by: Rafael David Tinoco Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 203 +++++++++++++++------------------ 1 file changed, 93 insertions(+), 110 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index 31b52ebf426f..7c5d4647cb5e 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -41,6 +41,7 @@ #define HISI_TEMP_BASE (-60000) #define HISI_TEMP_RESET (100000) #define HISI_TEMP_STEP (784) +#define HISI_TEMP_LAG (3500) #define HISI_MAX_SENSORS 4 #define HISI_DEFAULT_SENSOR 2 @@ -60,8 +61,6 @@ struct hisi_thermal_data { struct clk *clk; struct hisi_thermal_sensor sensors; int irq; - bool irq_enabled; - void __iomem *regs; }; @@ -99,9 +98,40 @@ static inline long hisi_thermal_round_temp(int temp) hisi_thermal_temp_to_step(temp)); } +/* + * The lag register contains 5 bits encoding the temperature in steps. + * + * Each time the temperature crosses the threshold boundary, an + * interrupt is raised. It could be when the temperature is going + * above the threshold or below. However, if the temperature is + * fluctuating around this value due to the load, we can receive + * several interrupts which may not desired. + * + * We can setup a temperature representing the delta between the + * threshold and the current temperature when the temperature is + * decreasing. + * + * For instance: the lag register is 5°C, the threshold is 65°C, when + * the temperature reaches 65°C an interrupt is raised and when the + * temperature decrease to 65°C - 5°C another interrupt is raised. + * + * A very short lag can lead to an interrupt storm, a long lag + * increase the latency to react to the temperature changes. In our + * case, that is not really a problem as we are polling the + * temperature. + * + * [0:4] : lag register + * + * The temperature is coded in steps, cf. HISI_TEMP_STEP. + * + * Min : 0x00 : 0.0 °C + * Max : 0x1F : 24.3 °C + * + * The 'value' parameter is in milliCelsius. + */ static inline void hisi_thermal_set_lag(void __iomem *addr, int value) { - writel(value, addr + TEMP0_LAG); + writel((value / HISI_TEMP_STEP) & 0x1F, addr + TEMP0_LAG); } static inline void hisi_thermal_alarm_clear(void __iomem *addr, int value) @@ -171,71 +201,6 @@ static inline void hisi_thermal_hdak_set(void __iomem *addr, int value) (value << 4), addr + TEMP0_CFG); } -static long hisi_thermal_get_sensor_temp(struct hisi_thermal_data *data, - struct hisi_thermal_sensor *sensor) -{ - long val; - - mutex_lock(&data->thermal_lock); - - /* disable interrupt */ - hisi_thermal_alarm_enable(data->regs, 0); - hisi_thermal_alarm_clear(data->regs, 1); - - /* disable module firstly */ - hisi_thermal_enable(data->regs, 0); - - /* select sensor id */ - hisi_thermal_sensor_select(data->regs, sensor->id); - - /* enable module */ - hisi_thermal_enable(data->regs, 1); - - usleep_range(3000, 5000); - - val = hisi_thermal_get_temperature(data->regs); - - mutex_unlock(&data->thermal_lock); - - return val; -} - -static void hisi_thermal_enable_bind_irq_sensor - (struct hisi_thermal_data *data) -{ - struct hisi_thermal_sensor *sensor; - - mutex_lock(&data->thermal_lock); - - sensor = &data->sensors; - - /* setting the hdak time */ - hisi_thermal_hdak_set(data->regs, 0); - - /* disable module firstly */ - hisi_thermal_reset_enable(data->regs, 0); - hisi_thermal_enable(data->regs, 0); - - /* select sensor id */ - hisi_thermal_sensor_select(data->regs, sensor->id); - - /* enable for interrupt */ - hisi_thermal_alarm_set(data->regs, sensor->thres_temp); - - hisi_thermal_reset_set(data->regs, HISI_TEMP_RESET); - - /* enable module */ - hisi_thermal_reset_enable(data->regs, 1); - hisi_thermal_enable(data->regs, 1); - - hisi_thermal_alarm_clear(data->regs, 0); - hisi_thermal_alarm_enable(data->regs, 1); - - usleep_range(3000, 5000); - - mutex_unlock(&data->thermal_lock); -} - static void hisi_thermal_disable_sensor(struct hisi_thermal_data *data) { mutex_lock(&data->thermal_lock); @@ -253,25 +218,10 @@ static int hisi_thermal_get_temp(void *_sensor, int *temp) struct hisi_thermal_sensor *sensor = _sensor; struct hisi_thermal_data *data = sensor->thermal; - *temp = hisi_thermal_get_sensor_temp(data, sensor); - - dev_dbg(&data->pdev->dev, "id=%d, irq=%d, temp=%d, thres=%d\n", - sensor->id, data->irq_enabled, *temp, sensor->thres_temp); - /* - * Bind irq to sensor for two cases: - * Reenable alarm IRQ if temperature below threshold; - * if irq has been enabled, always set it; - */ - if (data->irq_enabled) { - hisi_thermal_enable_bind_irq_sensor(data); - return 0; - } + *temp = hisi_thermal_get_temperature(data->regs); - if (*temp < sensor->thres_temp) { - data->irq_enabled = true; - hisi_thermal_enable_bind_irq_sensor(data); - enable_irq(data->irq); - } + dev_dbg(&data->pdev->dev, "id=%d, temp=%d, thres=%d\n", + sensor->id, *temp, sensor->thres_temp); return 0; } @@ -280,26 +230,27 @@ static const struct thermal_zone_of_device_ops hisi_of_thermal_ops = { .get_temp = hisi_thermal_get_temp, }; -static irqreturn_t hisi_thermal_alarm_irq(int irq, void *dev) +static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) { struct hisi_thermal_data *data = dev; + struct hisi_thermal_sensor *sensor = &data->sensors; + int temp; - disable_irq_nosync(irq); - data->irq_enabled = false; + hisi_thermal_alarm_clear(data->regs, 1); - return IRQ_WAKE_THREAD; -} + temp = hisi_thermal_get_temperature(data->regs); -static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) -{ - struct hisi_thermal_data *data = dev; - struct hisi_thermal_sensor *sensor = &data->sensors; + if (temp >= sensor->thres_temp) { + dev_crit(&data->pdev->dev, "THERMAL ALARM: %d > %d\n", + temp, sensor->thres_temp); - dev_crit(&data->pdev->dev, "THERMAL ALARM: T > %d\n", - sensor->thres_temp); + thermal_zone_device_update(data->sensors.tzd, + THERMAL_EVENT_UNSPECIFIED); - thermal_zone_device_update(data->sensors.tzd, - THERMAL_EVENT_UNSPECIFIED); + } else if (temp < sensor->thres_temp) { + dev_crit(&data->pdev->dev, "THERMAL ALARM stopped: %d < %d\n", + temp, sensor->thres_temp); + } return IRQ_HANDLED; } @@ -352,6 +303,40 @@ static void hisi_thermal_toggle_sensor(struct hisi_thermal_sensor *sensor, on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); } +static int hisi_thermal_setup(struct hisi_thermal_data *data) +{ + struct hisi_thermal_sensor *sensor; + + sensor = &data->sensors; + + /* disable module firstly */ + hisi_thermal_reset_enable(data->regs, 0); + hisi_thermal_enable(data->regs, 0); + + /* select sensor id */ + hisi_thermal_sensor_select(data->regs, sensor->id); + + /* setting the hdak time */ + hisi_thermal_hdak_set(data->regs, 0); + + /* setting lag value between current temp and the threshold */ + hisi_thermal_set_lag(data->regs, HISI_TEMP_LAG); + + /* enable for interrupt */ + hisi_thermal_alarm_set(data->regs, sensor->thres_temp); + + hisi_thermal_reset_set(data->regs, HISI_TEMP_RESET); + + /* enable module */ + hisi_thermal_reset_enable(data->regs, 1); + hisi_thermal_enable(data->regs, 1); + + hisi_thermal_alarm_clear(data->regs, 0); + hisi_thermal_alarm_enable(data->regs, 1); + + return 0; +} + static int hisi_thermal_probe(struct platform_device *pdev) { struct hisi_thermal_data *data; @@ -394,9 +379,6 @@ static int hisi_thermal_probe(struct platform_device *pdev) return ret; } - hisi_thermal_enable_bind_irq_sensor(data); - data->irq_enabled = true; - ret = hisi_thermal_register_sensor(pdev, data, &data->sensors, HISI_DEFAULT_SENSOR); @@ -406,10 +388,15 @@ static int hisi_thermal_probe(struct platform_device *pdev) return ret; } - ret = devm_request_threaded_irq(&pdev->dev, data->irq, - hisi_thermal_alarm_irq, + ret = hisi_thermal_setup(data); + if (ret) { + dev_err(&pdev->dev, "Failed to setup the sensor: %d\n", ret); + return ret; + } + + ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL, hisi_thermal_alarm_irq_thread, - 0, "hisi_thermal", data); + IRQF_ONESHOT, "hisi_thermal", data); if (ret < 0) { dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret); return ret; @@ -417,8 +404,6 @@ static int hisi_thermal_probe(struct platform_device *pdev) hisi_thermal_toggle_sensor(&data->sensors, true); - enable_irq(data->irq); - return 0; } @@ -440,7 +425,6 @@ static int hisi_thermal_suspend(struct device *dev) struct hisi_thermal_data *data = dev_get_drvdata(dev); hisi_thermal_disable_sensor(data); - data->irq_enabled = false; clk_disable_unprepare(data->clk); @@ -456,8 +440,7 @@ static int hisi_thermal_resume(struct device *dev) if (ret) return ret; - data->irq_enabled = true; - hisi_thermal_enable_bind_irq_sensor(data); + hisi_thermal_setup(data); return 0; } -- GitLab From c29f9010a35604047f96a7e9d6cbabfa36d996d1 Mon Sep 17 00:00:00 2001 From: Roman Gushchin Date: Tue, 30 Oct 2018 17:48:25 +0000 Subject: [PATCH 0364/1286] mm: hide incomplete nr_indirectly_reclaimable in /proc/zoneinfo [fixed differently upstream, this is a work-around to resolve it for 4.14.y] Yongqin reported that /proc/zoneinfo format is broken in 4.14 due to commit 7aaf77272358 ("mm: don't show nr_indirectly_reclaimable in /proc/vmstat") Node 0, zone DMA per-node stats nr_inactive_anon 403 nr_active_anon 89123 nr_inactive_file 128887 nr_active_file 47377 nr_unevictable 2053 nr_slab_reclaimable 7510 nr_slab_unreclaimable 10775 nr_isolated_anon 0 nr_isolated_file 0 <...> nr_vmscan_write 0 nr_vmscan_immediate_reclaim 0 nr_dirtied 6022 nr_written 5985 74240 ^^^^^^^^^^ pages free 131656 The problem is caused by the nr_indirectly_reclaimable counter, which is hidden from the /proc/vmstat, but not from the /proc/zoneinfo. Let's fix this inconsistency and hide the counter from /proc/zoneinfo exactly as from /proc/vmstat. BTW, in 4.19+ the counter has been renamed and exported by the commit b29940c1abd7 ("mm: rename and change semantics of nr_indirectly_reclaimable_bytes"), so there is no such a problem anymore. Cc: # 4.14.x-4.18.x Fixes: 7aaf77272358 ("mm: don't show nr_indirectly_reclaimable in /proc/vmstat") Reported-by: Yongqin Liu Signed-off-by: Roman Gushchin Cc: Vlastimil Babka Cc: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- mm/vmstat.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/mm/vmstat.c b/mm/vmstat.c index 527ae727d547..6389e876c7a7 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1500,6 +1500,10 @@ static void zoneinfo_show_print(struct seq_file *m, pg_data_t *pgdat, if (is_zone_first_populated(pgdat, zone)) { seq_printf(m, "\n per-node stats"); for (i = 0; i < NR_VM_NODE_STAT_ITEMS; i++) { + /* Skip hidden vmstat items. */ + if (*vmstat_text[i + NR_VM_ZONE_STAT_ITEMS + + NR_VM_NUMA_STAT_ITEMS] == '\0') + continue; seq_printf(m, "\n %-12s %lu", vmstat_text[i + NR_VM_ZONE_STAT_ITEMS + NR_VM_NUMA_STAT_ITEMS], -- GitLab From 02dc68829e5f2a9b48829725f332200ac3b051c2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 2 Feb 2018 16:44:47 +0100 Subject: [PATCH 0365/1286] net: qed: use correct strncpy() size commit 11f711081af0eb54190dc0de96ba4a9cd494666b upstream. passing the strlen() of the source string as the destination length is pointless, and gcc-8 now warns about it: drivers/net/ethernet/qlogic/qed/qed_debug.c: In function 'qed_grc_dump': include/linux/string.h:253: error: 'strncpy' specified bound depends on the length of the source argument [-Werror=stringop-overflow=] This changes qed_grc_dump_big_ram() to instead uses the length of the destination buffer, and use strscpy() to guarantee nul-termination. Signed-off-by: Arnd Bergmann Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/qlogic/qed/qed_debug.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c index 03c3cf77aaff..99f32202a85c 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_debug.c +++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c @@ -3590,10 +3590,8 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, total_blocks = big_ram->num_of_blocks[dev_data->chip_id]; ram_size = total_blocks * BIG_RAM_BLOCK_SIZE_DWORDS; - strncpy(type_name, big_ram->instance_name, - strlen(big_ram->instance_name)); - strncpy(mem_name, big_ram->instance_name, - strlen(big_ram->instance_name)); + strscpy(type_name, big_ram->instance_name, sizeof(type_name)); + strscpy(mem_name, big_ram->instance_name, sizeof(mem_name)); /* Dump memory header */ offset += qed_grc_dump_mem_hdr(p_hwfn, -- GitLab From 88b58409f82e98d28f90328fa9ab98e0de479a0c Mon Sep 17 00:00:00 2001 From: Guoqing Jiang Date: Fri, 19 Oct 2018 12:08:22 +0800 Subject: [PATCH 0366/1286] tipc: use destination length for copy string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 29e270fc32192e7729057963ae7120663856c93e upstream. Got below warning with gcc 8.2 compiler. net/tipc/topsrv.c: In function ‘tipc_topsrv_start’: net/tipc/topsrv.c:660:2: warning: ‘strncpy’ specified bound depends on the length of the source argument [-Wstringop-overflow=] strncpy(srv->name, name, strlen(name) + 1); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ net/tipc/topsrv.c:660:27: note: length computed here strncpy(srv->name, name, strlen(name) + 1); ^~~~~~~~~~~~ So change it to correct length and use strscpy. Signed-off-by: Guoqing Jiang Acked-by: Ying Xue Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/tipc/subscr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tipc/subscr.c b/net/tipc/subscr.c index be3d9e3183dc..959c9aea3d1a 100644 --- a/net/tipc/subscr.c +++ b/net/tipc/subscr.c @@ -375,7 +375,7 @@ int tipc_topsrv_start(struct net *net) topsrv->tipc_conn_new = tipc_subscrb_connect_cb; topsrv->tipc_conn_release = tipc_subscrb_release_cb; - strncpy(topsrv->name, name, strlen(name) + 1); + strscpy(topsrv->name, name, sizeof(topsrv->name)); tn->topsrv = topsrv; atomic_set(&tn->subscription_count, 0); -- GitLab From ca48e5e30b75a28c12c43c7428c95735e4885e6b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 8 Dec 2018 13:03:41 +0100 Subject: [PATCH 0367/1286] Linux 4.14.87 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 77ffc1dc4e79..322484348f3e 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 86 +SUBLEVEL = 87 EXTRAVERSION = NAME = Petit Gorille -- GitLab From 408d8698c68f82d579a80690783acef3f929577d Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Thu, 1 Nov 2018 17:33:12 -0700 Subject: [PATCH 0368/1286] block, ice, cfq: support back/front merges and update req->__dun <4>[136765.870673] c6 4967 ------------[ cut here ]------------ <4>[136765.870717] c6 4967 WARNING: at block/blk-core.c:1534 <4>[136765.871328] c6 4967 [] bio_attempt_front_merge+0x23c/0x280 <4>[136765.871335] c6 4967 [] blk_queue_bio+0x314/0xaa8 <4>[136765.871344] c6 4967 [] generic_make_request+0xfc/0x330 <4>[136765.871351] c6 4967 [] submit_bio+0x15c/0x2dc <4>[136765.871362] c6 4967 [] __submit_bio+0x46c/0x4e0 <4>[136765.871371] c6 4967 [] f2fs_mpage_readpages+0x57c/0x7e4 Assuming that this encrypted bio is mergeable, blk_queue_bio() blk_attempt_plug_merge() = false, given by blk_try_merge()=ELEVATOR_NO_MERGE el_ret = elv_merge() if (q->last_merge) elv_bio_merge_ok() = true blk_try_merge() = ELEVATOR_NO_MERGE; } __rq = elv_rqhash_find(); if (__rq = false && elv_bio_merge_ok() = true) e->type->ops.elevator_merge_fn() -- cfq_merge() elv_bio_merge_ok() = true return ELEVATOR_FRONT_MERGE if (el_ret == ELEVATOR_FRONT_MERGE) bio_attempt_front_merge() WARN_ON(dun exists) So, it should update req->__dun having correct ICE configuration. Bug: 118824609 Bug: 119454809 Change-Id: Ic79f9474b56b2b911c9083c3a80f3e686bb432bd Signed-off-by: Jaegeuk Kim [stummala@codeaurora.org: Fix merge conflicts] Signed-off-by: Sahitya Tummala --- block/blk-core.c | 5 ++++- block/blk-merge.c | 24 ++++++++++++++---------- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/block/blk-core.c b/block/blk-core.c index e57aed3f6211..f53f1b5dec09 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -1432,6 +1432,9 @@ static struct request *blk_old_get_request(struct request_queue *q, /* q->queue_lock is unlocked at this point */ rq->__data_len = 0; rq->__sector = (sector_t) -1; +#ifdef CONFIG_PFK + rq->__dun = 0; +#endif rq->bio = rq->biotail = NULL; return rq; } @@ -1656,7 +1659,7 @@ bool bio_attempt_front_merge(struct request_queue *q, struct request *req, req->bio = bio; #ifdef CONFIG_PFK - WARN_ON(req->__dun || bio->bi_iter.bi_dun); + req->__dun = bio->bi_iter.bi_dun; #endif req->__sector = bio->bi_iter.bi_sector; req->__data_len += bio->bi_iter.bi_size; diff --git a/block/blk-merge.c b/block/blk-merge.c index 079a3cf533f9..f5910ebea08f 100644 --- a/block/blk-merge.c +++ b/block/blk-merge.c @@ -505,6 +505,8 @@ int ll_back_merge_fn(struct request_queue *q, struct request *req, if (blk_integrity_rq(req) && integrity_req_gap_back_merge(req, bio)) return 0; + if (blk_try_merge(req, bio) != ELEVATOR_BACK_MERGE) + return 0; if (blk_rq_sectors(req) + bio_sectors(bio) > blk_rq_get_max_sectors(req, blk_rq_pos(req))) { req_set_nomerge(q, req); @@ -527,6 +529,8 @@ int ll_front_merge_fn(struct request_queue *q, struct request *req, if (blk_integrity_rq(req) && integrity_req_gap_front_merge(req, bio)) return 0; + if (blk_try_merge(req, bio) != ELEVATOR_FRONT_MERGE) + return 0; if (blk_rq_sectors(req) + bio_sectors(bio) > blk_rq_get_max_sectors(req, bio->bi_iter.bi_sector)) { req_set_nomerge(q, req); @@ -837,24 +841,24 @@ bool blk_rq_merge_ok(struct request *rq, struct bio *bio) if (rq->write_hint != bio->bi_write_hint) return false; - if (crypto_not_mergeable(rq->bio, bio)) - return false; - return true; } enum elv_merge blk_try_merge(struct request *rq, struct bio *bio) { -#ifdef CONFIG_PFK - if (blk_rq_dun(rq) || bio_dun(bio)) - return ELEVATOR_NO_MERGE; -#endif if (req_op(rq) == REQ_OP_DISCARD && - queue_max_discard_segments(rq->q) > 1) + queue_max_discard_segments(rq->q) > 1) { return ELEVATOR_DISCARD_MERGE; - else if (blk_rq_pos(rq) + blk_rq_sectors(rq) == bio->bi_iter.bi_sector) + } else if (blk_rq_pos(rq) + blk_rq_sectors(rq) == + bio->bi_iter.bi_sector) { + if (crypto_not_mergeable(rq->bio, bio)) + return ELEVATOR_NO_MERGE; return ELEVATOR_BACK_MERGE; - else if (blk_rq_pos(rq) - bio_sectors(bio) == bio->bi_iter.bi_sector) + } else if (blk_rq_pos(rq) - bio_sectors(bio) == + bio->bi_iter.bi_sector) { + if (crypto_not_mergeable(bio, rq->bio)) + return ELEVATOR_NO_MERGE; return ELEVATOR_FRONT_MERGE; + } return ELEVATOR_NO_MERGE; } -- GitLab From f44902577d62bf9bd3ff94da18711dfa2f2cbac6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 12 Dec 2018 19:39:05 +0100 Subject: [PATCH 0369/1286] ANDROID: revert all remaining hisi_thermal.c changes hisi_thermal.c changes do not belong in the android-common tree, as there is a separate tree just for this board. Revert the remaining changes here as it is causing build and merge issues. Reported-by: Todd Kjos Cc: Daniel Lezcano Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/hisi_thermal.c | 464 ++++++++++----------------------- 1 file changed, 135 insertions(+), 329 deletions(-) diff --git a/drivers/thermal/hisi_thermal.c b/drivers/thermal/hisi_thermal.c index 2d5e9990a552..7c5d4647cb5e 100644 --- a/drivers/thermal/hisi_thermal.c +++ b/drivers/thermal/hisi_thermal.c @@ -23,103 +23,79 @@ #include #include #include -#include #include "thermal_core.h" -#define HI6220_TEMP0_LAG (0x0) -#define HI6220_TEMP0_TH (0x4) -#define HI6220_TEMP0_RST_TH (0x8) -#define HI6220_TEMP0_CFG (0xC) -#define HI6220_TEMP0_CFG_SS_MSK (0xF000) -#define HI6220_TEMP0_CFG_HDAK_MSK (0x30) -#define HI6220_TEMP0_EN (0x10) -#define HI6220_TEMP0_INT_EN (0x14) -#define HI6220_TEMP0_INT_CLR (0x18) -#define HI6220_TEMP0_RST_MSK (0x1C) -#define HI6220_TEMP0_VALUE (0x28) - -#define HI3660_OFFSET(chan) ((chan) * 0x40) -#define HI3660_TEMP(chan) (HI3660_OFFSET(chan) + 0x1C) -#define HI3660_TH(chan) (HI3660_OFFSET(chan) + 0x20) -#define HI3660_LAG(chan) (HI3660_OFFSET(chan) + 0x28) -#define HI3660_INT_EN(chan) (HI3660_OFFSET(chan) + 0x2C) -#define HI3660_INT_CLR(chan) (HI3660_OFFSET(chan) + 0x30) - -#define HI6220_TEMP_BASE (-60000) -#define HI6220_TEMP_RESET (100000) -#define HI6220_TEMP_STEP (785) -#define HI6220_TEMP_LAG (3500) - -#define HI3660_TEMP_BASE (-63780) -#define HI3660_TEMP_STEP (205) -#define HI3660_TEMP_LAG (4000) - -#define HI6220_DEFAULT_SENSOR 2 -#define HI3660_DEFAULT_SENSOR 1 +#define TEMP0_LAG (0x0) +#define TEMP0_TH (0x4) +#define TEMP0_RST_TH (0x8) +#define TEMP0_CFG (0xC) +#define TEMP0_CFG_SS_MSK (0xF000) +#define TEMP0_CFG_HDAK_MSK (0x30) +#define TEMP0_EN (0x10) +#define TEMP0_INT_EN (0x14) +#define TEMP0_INT_CLR (0x18) +#define TEMP0_RST_MSK (0x1C) +#define TEMP0_VALUE (0x28) + +#define HISI_TEMP_BASE (-60000) +#define HISI_TEMP_RESET (100000) +#define HISI_TEMP_STEP (784) +#define HISI_TEMP_LAG (3500) + +#define HISI_MAX_SENSORS 4 +#define HISI_DEFAULT_SENSOR 2 struct hisi_thermal_sensor { + struct hisi_thermal_data *thermal; struct thermal_zone_device *tzd; + + long sensor_temp; uint32_t id; uint32_t thres_temp; }; struct hisi_thermal_data { - int (*get_temp)(struct hisi_thermal_data *data); - int (*enable_sensor)(struct hisi_thermal_data *data); - int (*disable_sensor)(struct hisi_thermal_data *data); - int (*irq_handler)(struct hisi_thermal_data *data); + struct mutex thermal_lock; /* protects register data */ struct platform_device *pdev; struct clk *clk; - struct hisi_thermal_sensor sensor; - void __iomem *regs; + struct hisi_thermal_sensor sensors; int irq; + void __iomem *regs; }; /* * The temperature computation on the tsensor is as follow: * Unit: millidegree Celsius - * Step: 200/255 (0.7843) + * Step: 255/200 (0.7843) * Temperature base: -60°C * - * The register is programmed in temperature steps, every step is 785 + * The register is programmed in temperature steps, every step is 784 * millidegree and begins at -60 000 m°C * * The temperature from the steps: * - * Temp = TempBase + (steps x 785) + * Temp = TempBase + (steps x 784) * * and the steps from the temperature: * - * steps = (Temp - TempBase) / 785 + * steps = (Temp - TempBase) / 784 * */ -static inline int hi6220_thermal_step_to_temp(int step) +static inline int hisi_thermal_step_to_temp(int step) { - return HI6220_TEMP_BASE + (step * HI6220_TEMP_STEP); + return HISI_TEMP_BASE + (step * HISI_TEMP_STEP); } -static inline int hi6220_thermal_temp_to_step(int temp) +static inline long hisi_thermal_temp_to_step(long temp) { - return DIV_ROUND_UP(temp - HI6220_TEMP_BASE, HI6220_TEMP_STEP); + return (temp - HISI_TEMP_BASE) / HISI_TEMP_STEP; } -/* - * for Hi3660, - * Step: 189/922 (0.205) - * Temperature base: -63.780°C - * - * The register is programmed in temperature steps, every step is 205 - * millidegree and begins at -63 780 m°C - */ -static inline int hi3660_thermal_step_to_temp(int step) +static inline long hisi_thermal_round_temp(int temp) { - return HI3660_TEMP_BASE + step * HI3660_TEMP_STEP; -} - -static inline int hi3660_thermal_temp_to_step(int temp) -{ - return DIV_ROUND_UP(temp - HI3660_TEMP_BASE, HI3660_TEMP_STEP); + return hisi_thermal_step_to_temp( + hisi_thermal_temp_to_step(temp)); } /* @@ -146,92 +122,51 @@ static inline int hi3660_thermal_temp_to_step(int temp) * * [0:4] : lag register * - * The temperature is coded in steps, cf. HI6220_TEMP_STEP. + * The temperature is coded in steps, cf. HISI_TEMP_STEP. * * Min : 0x00 : 0.0 °C * Max : 0x1F : 24.3 °C * * The 'value' parameter is in milliCelsius. */ -static inline void hi6220_thermal_set_lag(void __iomem *addr, int value) +static inline void hisi_thermal_set_lag(void __iomem *addr, int value) { - writel(DIV_ROUND_UP(value, HI6220_TEMP_STEP) & 0x1F, - addr + HI6220_TEMP0_LAG); + writel((value / HISI_TEMP_STEP) & 0x1F, addr + TEMP0_LAG); } -static inline void hi6220_thermal_alarm_clear(void __iomem *addr, int value) +static inline void hisi_thermal_alarm_clear(void __iomem *addr, int value) { - writel(value, addr + HI6220_TEMP0_INT_CLR); + writel(value, addr + TEMP0_INT_CLR); } -static inline void hi6220_thermal_alarm_enable(void __iomem *addr, int value) +static inline void hisi_thermal_alarm_enable(void __iomem *addr, int value) { - writel(value, addr + HI6220_TEMP0_INT_EN); + writel(value, addr + TEMP0_INT_EN); } -static inline void hi6220_thermal_alarm_set(void __iomem *addr, int temp) +static inline void hisi_thermal_alarm_set(void __iomem *addr, int temp) { - writel(hi6220_thermal_temp_to_step(temp) | 0x0FFFFFF00, - addr + HI6220_TEMP0_TH); + writel(hisi_thermal_temp_to_step(temp) | 0x0FFFFFF00, addr + TEMP0_TH); } -static inline void hi6220_thermal_reset_set(void __iomem *addr, int temp) +static inline void hisi_thermal_reset_set(void __iomem *addr, int temp) { - writel(hi6220_thermal_temp_to_step(temp), addr + HI6220_TEMP0_RST_TH); + writel(hisi_thermal_temp_to_step(temp), addr + TEMP0_RST_TH); } -static inline void hi6220_thermal_reset_enable(void __iomem *addr, int value) +static inline void hisi_thermal_reset_enable(void __iomem *addr, int value) { - writel(value, addr + HI6220_TEMP0_RST_MSK); + writel(value, addr + TEMP0_RST_MSK); } -static inline void hi6220_thermal_enable(void __iomem *addr, int value) +static inline void hisi_thermal_enable(void __iomem *addr, int value) { - writel(value, addr + HI6220_TEMP0_EN); + writel(value, addr + TEMP0_EN); } -static inline int hi6220_thermal_get_temperature(void __iomem *addr) +static inline int hisi_thermal_get_temperature(void __iomem *addr) { - return hi6220_thermal_step_to_temp(readl(addr + HI6220_TEMP0_VALUE)); -} - -/* - * [0:6] lag register - * - * The temperature is coded in steps, cf. HI3660_TEMP_STEP. - * - * Min : 0x00 : 0.0 °C - * Max : 0x7F : 26.0 °C - * - */ -static inline void hi3660_thermal_set_lag(void __iomem *addr, - int id, int value) -{ - writel(DIV_ROUND_UP(value, HI3660_TEMP_STEP) & 0x7F, - addr + HI3660_LAG(id)); -} - -static inline void hi3660_thermal_alarm_clear(void __iomem *addr, - int id, int value) -{ - writel(value, addr + HI3660_INT_CLR(id)); -} - -static inline void hi3660_thermal_alarm_enable(void __iomem *addr, - int id, int value) -{ - writel(value, addr + HI3660_INT_EN(id)); -} - -static inline void hi3660_thermal_alarm_set(void __iomem *addr, - int id, int value) -{ - writel(value, addr + HI3660_TH(id)); -} - -static inline int hi3660_thermal_get_temperature(void __iomem *addr, int id) -{ - return hi3660_thermal_step_to_temp(readl(addr + HI3660_TEMP(id))); + return hisi_thermal_step_to_temp(readl(addr + TEMP0_VALUE)); } /* @@ -244,10 +179,10 @@ static inline int hi3660_thermal_get_temperature(void __iomem *addr, int id) * 0x2: remote sensor 2 (ACPU cluster 0) * 0x3: remote sensor 3 (G3D) */ -static inline void hi6220_thermal_sensor_select(void __iomem *addr, int sensor) +static inline void hisi_thermal_sensor_select(void __iomem *addr, int sensor) { - writel((readl(addr + HI6220_TEMP0_CFG) & ~HI6220_TEMP0_CFG_SS_MSK) | - (sensor << 12), addr + HI6220_TEMP0_CFG); + writel((readl(addr + TEMP0_CFG) & ~TEMP0_CFG_SS_MSK) | + (sensor << 12), addr + TEMP0_CFG); } /* @@ -260,182 +195,30 @@ static inline void hi6220_thermal_sensor_select(void __iomem *addr, int sensor) * 0x2 : 49.152 ms * 0x3 : 393.216 ms */ -static inline void hi6220_thermal_hdak_set(void __iomem *addr, int value) -{ - writel((readl(addr + HI6220_TEMP0_CFG) & ~HI6220_TEMP0_CFG_HDAK_MSK) | - (value << 4), addr + HI6220_TEMP0_CFG); -} - -static int hi6220_thermal_irq_handler(struct hisi_thermal_data *data) -{ - hi6220_thermal_alarm_clear(data->regs, 1); - return 0; -} - -static int hi3660_thermal_irq_handler(struct hisi_thermal_data *data) -{ - hi3660_thermal_alarm_clear(data->regs, data->sensor.id, 1); - return 0; -} - -static int hi6220_thermal_get_temp(struct hisi_thermal_data *data) +static inline void hisi_thermal_hdak_set(void __iomem *addr, int value) { - return hi6220_thermal_get_temperature(data->regs); + writel((readl(addr + TEMP0_CFG) & ~TEMP0_CFG_HDAK_MSK) | + (value << 4), addr + TEMP0_CFG); } -static int hi3660_thermal_get_temp(struct hisi_thermal_data *data) +static void hisi_thermal_disable_sensor(struct hisi_thermal_data *data) { - return hi3660_thermal_get_temperature(data->regs, data->sensor.id); -} + mutex_lock(&data->thermal_lock); -static int hi6220_thermal_disable_sensor(struct hisi_thermal_data *data) -{ /* disable sensor module */ - hi6220_thermal_enable(data->regs, 0); - hi6220_thermal_alarm_enable(data->regs, 0); - hi6220_thermal_reset_enable(data->regs, 0); - - clk_disable_unprepare(data->clk); - - return 0; -} - -static int hi3660_thermal_disable_sensor(struct hisi_thermal_data *data) -{ - /* disable sensor module */ - hi3660_thermal_alarm_enable(data->regs, data->sensor.id, 0); - return 0; -} - -static int hi6220_thermal_enable_sensor(struct hisi_thermal_data *data) -{ - struct hisi_thermal_sensor *sensor = &data->sensor; - int ret; - - /* enable clock for tsensor */ - ret = clk_prepare_enable(data->clk); - if (ret) - return ret; - - /* disable module firstly */ - hi6220_thermal_reset_enable(data->regs, 0); - hi6220_thermal_enable(data->regs, 0); - - /* select sensor id */ - hi6220_thermal_sensor_select(data->regs, sensor->id); - - /* setting the hdak time */ - hi6220_thermal_hdak_set(data->regs, 0); - - /* setting lag value between current temp and the threshold */ - hi6220_thermal_set_lag(data->regs, HI6220_TEMP_LAG); - - /* enable for interrupt */ - hi6220_thermal_alarm_set(data->regs, sensor->thres_temp); - - hi6220_thermal_reset_set(data->regs, HI6220_TEMP_RESET); - - /* enable module */ - hi6220_thermal_reset_enable(data->regs, 1); - hi6220_thermal_enable(data->regs, 1); - - hi6220_thermal_alarm_clear(data->regs, 0); - hi6220_thermal_alarm_enable(data->regs, 1); - - return 0; -} - -static int hi3660_thermal_enable_sensor(struct hisi_thermal_data *data) -{ - unsigned int value; - struct hisi_thermal_sensor *sensor = &data->sensor; - - /* disable interrupt */ - hi3660_thermal_alarm_enable(data->regs, sensor->id, 0); - - /* setting lag value between current temp and the threshold */ - hi3660_thermal_set_lag(data->regs, sensor->id, HI3660_TEMP_LAG); - - /* set interrupt threshold */ - value = hi3660_thermal_temp_to_step(sensor->thres_temp); - hi3660_thermal_alarm_set(data->regs, sensor->id, value); - - /* enable interrupt */ - hi3660_thermal_alarm_clear(data->regs, sensor->id, 1); - hi3660_thermal_alarm_enable(data->regs, sensor->id, 1); - - return 0; -} - -static int hi6220_thermal_probe(struct hisi_thermal_data *data) -{ - struct platform_device *pdev = data->pdev; - struct device *dev = &pdev->dev; - struct resource *res; - int ret; - - data->get_temp = hi6220_thermal_get_temp; - data->enable_sensor = hi6220_thermal_enable_sensor; - data->disable_sensor = hi6220_thermal_disable_sensor; - data->irq_handler = hi6220_thermal_irq_handler; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(data->regs)) { - dev_err(dev, "failed to get io address\n"); - return PTR_ERR(data->regs); - } - - data->clk = devm_clk_get(dev, "thermal_clk"); - if (IS_ERR(data->clk)) { - ret = PTR_ERR(data->clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "failed to get thermal clk: %d\n", ret); - return ret; - } - - data->irq = platform_get_irq(pdev, 0); - if (data->irq < 0) - return data->irq; - - data->sensor.id = HI6220_DEFAULT_SENSOR; - - return 0; -} - -static int hi3660_thermal_probe(struct hisi_thermal_data *data) -{ - struct platform_device *pdev = data->pdev; - struct device *dev = &pdev->dev; - struct resource *res; - - data->get_temp = hi3660_thermal_get_temp; - data->enable_sensor = hi3660_thermal_enable_sensor; - data->disable_sensor = hi3660_thermal_disable_sensor; - data->irq_handler = hi3660_thermal_irq_handler; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(data->regs)) { - dev_err(dev, "failed to get io address\n"); - return PTR_ERR(data->regs); - } - - data->irq = platform_get_irq(pdev, 0); - if (data->irq < 0) - return data->irq; - - data->sensor.id = HI3660_DEFAULT_SENSOR; + hisi_thermal_enable(data->regs, 0); + hisi_thermal_alarm_enable(data->regs, 0); + hisi_thermal_reset_enable(data->regs, 0); - return 0; + mutex_unlock(&data->thermal_lock); } -static int hisi_thermal_get_temp(void *__data, int *temp) +static int hisi_thermal_get_temp(void *_sensor, int *temp) { - struct hisi_thermal_data *data = __data; - struct hisi_thermal_sensor *sensor = &data->sensor; + struct hisi_thermal_sensor *sensor = _sensor; + struct hisi_thermal_data *data = sensor->thermal; - *temp = data->get_temp(data); + *temp = hisi_thermal_get_temperature(data->regs); dev_dbg(&data->pdev->dev, "id=%d, temp=%d, thres=%d\n", sensor->id, *temp, sensor->thres_temp); @@ -450,12 +233,12 @@ static const struct thermal_zone_of_device_ops hisi_of_thermal_ops = { static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) { struct hisi_thermal_data *data = dev; - struct hisi_thermal_sensor *sensor = &data->sensor; - int temp = 0; + struct hisi_thermal_sensor *sensor = &data->sensors; + int temp; - data->irq_handler(data); + hisi_thermal_alarm_clear(data->regs, 1); - hisi_thermal_get_temp(data, &temp); + temp = hisi_thermal_get_temperature(data->regs); if (temp >= sensor->thres_temp) { dev_crit(&data->pdev->dev, "THERMAL ALARM: %d > %d\n", @@ -474,14 +257,17 @@ static irqreturn_t hisi_thermal_alarm_irq_thread(int irq, void *dev) static int hisi_thermal_register_sensor(struct platform_device *pdev, struct hisi_thermal_data *data, - struct hisi_thermal_sensor *sensor) + struct hisi_thermal_sensor *sensor, + int index) { int ret, i; const struct thermal_trip *trip; + sensor->id = index; + sensor->thermal = data; + sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, - sensor->id, data, - &hisi_of_thermal_ops); + sensor->id, sensor, &hisi_of_thermal_ops); if (IS_ERR(sensor->tzd)) { ret = PTR_ERR(sensor->tzd); sensor->tzd = NULL; @@ -494,7 +280,7 @@ static int hisi_thermal_register_sensor(struct platform_device *pdev, for (i = 0; i < of_thermal_get_ntrips(sensor->tzd); i++) { if (trip[i].type == THERMAL_TRIP_PASSIVE) { - sensor->thres_temp = trip[i].temperature; + sensor->thres_temp = hisi_thermal_round_temp(trip[i].temperature); break; } } @@ -503,14 +289,7 @@ static int hisi_thermal_register_sensor(struct platform_device *pdev, } static const struct of_device_id of_hisi_thermal_match[] = { - { - .compatible = "hisilicon,tsensor", - .data = hi6220_thermal_probe - }, - { - .compatible = "hisilicon,hi3660-tsensor", - .data = hi3660_thermal_probe - }, + { .compatible = "hisilicon,tsensor" }, { /* end */ } }; MODULE_DEVICE_TABLE(of, of_hisi_thermal_match); @@ -561,51 +340,69 @@ static int hisi_thermal_setup(struct hisi_thermal_data *data) static int hisi_thermal_probe(struct platform_device *pdev) { struct hisi_thermal_data *data; - int const (*platform_probe)(struct hisi_thermal_data *); - struct device *dev = &pdev->dev; + struct resource *res; int ret; - data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; + mutex_init(&data->thermal_lock); data->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->regs)) { + dev_err(&pdev->dev, "failed to get io address\n"); + return PTR_ERR(data->regs); + } + + data->irq = platform_get_irq(pdev, 0); + if (data->irq < 0) + return data->irq; + platform_set_drvdata(pdev, data); - platform_probe = of_device_get_match_data(dev); - if (!platform_probe) { - dev_err(dev, "failed to get probe func\n"); - return -EINVAL; + data->clk = devm_clk_get(&pdev->dev, "thermal_clk"); + if (IS_ERR(data->clk)) { + ret = PTR_ERR(data->clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to get thermal clk: %d\n", ret); + return ret; } - ret = platform_probe(data); - if (ret) + /* enable clock for thermal */ + ret = clk_prepare_enable(data->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable thermal clk: %d\n", ret); return ret; + } ret = hisi_thermal_register_sensor(pdev, data, - &data->sensor); + &data->sensors, + HISI_DEFAULT_SENSOR); if (ret) { - dev_err(dev, "failed to register thermal sensor: %d\n", ret); + dev_err(&pdev->dev, "failed to register thermal sensor: %d\n", + ret); return ret; } - ret = data->enable_sensor(data); + ret = hisi_thermal_setup(data); if (ret) { - dev_err(dev, "Failed to setup the sensor: %d\n", ret); + dev_err(&pdev->dev, "Failed to setup the sensor: %d\n", ret); return ret; } - if (data->irq) { - ret = devm_request_threaded_irq(dev, data->irq, NULL, - hisi_thermal_alarm_irq_thread, - IRQF_ONESHOT, "hisi_thermal", data); - if (ret < 0) { - dev_err(dev, "failed to request alarm irq: %d\n", ret); - return ret; - } + ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL, + hisi_thermal_alarm_irq_thread, + IRQF_ONESHOT, "hisi_thermal", data); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret); + return ret; } - hisi_thermal_toggle_sensor(&data->sensor, true); + hisi_thermal_toggle_sensor(&data->sensors, true); return 0; } @@ -613,11 +410,11 @@ static int hisi_thermal_probe(struct platform_device *pdev) static int hisi_thermal_remove(struct platform_device *pdev) { struct hisi_thermal_data *data = platform_get_drvdata(pdev); - struct hisi_thermal_sensor *sensor = &data->sensor; + struct hisi_thermal_sensor *sensor = &data->sensors; hisi_thermal_toggle_sensor(sensor, false); - - data->disable_sensor(data); + hisi_thermal_disable_sensor(data); + clk_disable_unprepare(data->clk); return 0; } @@ -627,7 +424,9 @@ static int hisi_thermal_suspend(struct device *dev) { struct hisi_thermal_data *data = dev_get_drvdata(dev); - data->disable_sensor(data); + hisi_thermal_disable_sensor(data); + + clk_disable_unprepare(data->clk); return 0; } @@ -635,8 +434,15 @@ static int hisi_thermal_suspend(struct device *dev) static int hisi_thermal_resume(struct device *dev) { struct hisi_thermal_data *data = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(data->clk); + if (ret) + return ret; - return data->enable_sensor(data); + hisi_thermal_setup(data); + + return 0; } #endif -- GitLab From 531a2feb5c807d126c9bd4db8c864738c7c39e1c Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Tue, 11 Dec 2018 10:37:52 -0800 Subject: [PATCH 0370/1286] msm: camera: reqmgr: Hold device lock while retrieving session info There is a possibility for destroy session and link to occur concurrently, if this does we end up using a freed pointer while linking. Avoid this by increasing the scope of the device lock. Change-Id: I6ffb2d0633455a838cca9194e4717d82a9647183 Signed-off-by: Karthik Anantha Ram --- .../media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c index a0481e635c01..439a9ef392d4 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c @@ -2536,16 +2536,17 @@ int cam_req_mgr_link(struct cam_req_mgr_link_info *link_info) return -EINVAL; } + mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(link_info->session_hdl); if (!cam_session) { CAM_DBG(CAM_CRM, "NULL pointer"); + mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } - mutex_lock(&g_crm_core_dev->crm_lock); - /* Allocate link struct and map it with session's request queue */ link = __cam_req_mgr_reserve_link(cam_session); if (!link) { -- GitLab From 7bce8bc4803f819760871bd0e933fa8847be1291 Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 12 Dec 2018 17:57:43 -0800 Subject: [PATCH 0371/1286] ARM: dts: msm: specify ADC channel for TEMP_ALARM device on PMXPRAIRIE PMIC Specify the PMIC DIE_TEMP ADC channel for the TEMP_ALARM PMIC peripheral device found in the PMXPRAIRIE PMIC. This ensures that clients can read the exact die temperature of this PMIC at runtime instead of relying upon a very coarse estimate based upon the over-temperature stage. Change-Id: I2813d2c6b11825b8a8b685dbcf3051841b65031c Signed-off-by: David Collins --- arch/arm64/boot/dts/qcom/pmxprairie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmxprairie.dtsi b/arch/arm64/boot/dts/qcom/pmxprairie.dtsi index 099801c6ea80..c978e3049738 100644 --- a/arch/arm64/boot/dts/qcom/pmxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/pmxprairie.dtsi @@ -58,6 +58,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmxprairie_vadc ADC_DIE_TEMP>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; qcom,temperature-threshold-set = <1>; }; -- GitLab From bcdfccfd8dee5f024b618a3ec4df17fab1296658 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 9 Oct 2018 07:49:49 -0400 Subject: [PATCH 0372/1286] media: omap3isp: Unregister media device as first [ Upstream commit 30efae3d789cd0714ef795545a46749236e29558 ] While there are issues related to object lifetime management, unregister the media device first when the driver is being unbound. This is slightly safer. Signed-off-by: Sakari Ailus Reviewed-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/platform/omap3isp/isp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 6e6e978263b0..c834fea5f9b0 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -1592,6 +1592,8 @@ static void isp_pm_complete(struct device *dev) static void isp_unregister_entities(struct isp_device *isp) { + media_device_unregister(&isp->media_dev); + omap3isp_csi2_unregister_entities(&isp->isp_csi2a); omap3isp_ccp2_unregister_entities(&isp->isp_ccp2); omap3isp_ccdc_unregister_entities(&isp->isp_ccdc); @@ -1602,7 +1604,6 @@ static void isp_unregister_entities(struct isp_device *isp) omap3isp_stat_unregister_entities(&isp->isp_hist); v4l2_device_unregister(&isp->v4l2_dev); - media_device_unregister(&isp->media_dev); media_device_cleanup(&isp->media_dev); } -- GitLab From df11500b9dbf1bb3dd752f11be62a1cad22ca16d Mon Sep 17 00:00:00 2001 From: Lu Baolu Date: Mon, 5 Nov 2018 10:18:58 +0800 Subject: [PATCH 0373/1286] iommu/vt-d: Fix NULL pointer dereference in prq_event_thread() [ Upstream commit 19ed3e2dd8549c1a34914e8dad01b64e7837645a ] When handling page request without pasid event, go to "no_pasid" branch instead of "bad_req". Otherwise, a NULL pointer deference will happen there. Cc: Ashok Raj Cc: Jacob Pan Cc: Sohil Mehta Signed-off-by: Lu Baolu Fixes: a222a7f0bb6c9 'iommu/vt-d: Implement page request handling' Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/intel-svm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index d7def26ccf79..f5573bb9f450 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -589,7 +589,7 @@ static irqreturn_t prq_event_thread(int irq, void *d) pr_err("%s: Page request without PASID: %08llx %08llx\n", iommu->name, ((unsigned long long *)req)[0], ((unsigned long long *)req)[1]); - goto bad_req; + goto no_pasid; } if (!svm || svm->pasid != req->pasid) { -- GitLab From 8fa55f1d1859a6b0d2e6c1606b6d8fa1a9ef63d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 26 Oct 2018 12:50:39 +0200 Subject: [PATCH 0374/1286] brcmutil: really fix decoding channel info for 160 MHz bandwidth MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3401d42c7ea2d064d15c66698ff8eb96553179ce ] Previous commit /adding/ support for 160 MHz chanspecs was incomplete. It didn't set bandwidth info and didn't extract control channel info. As the result it was also using uninitialized "sb" var. This change has been tested for two chanspecs found to be reported by some devices/firmwares: 1) 60/160 (0xee32) Before: chnum:50 control_ch_num:36 After: chnum:50 control_ch_num:60 2) 120/160 (0xed72) Before: chnum:114 control_ch_num:100 After: chnum:114 control_ch_num:120 Fixes: 330994e8e8ec ("brcmfmac: fix for proper support of 160MHz bandwidth") Signed-off-by: Rafał Miłecki Signed-off-by: Kalle Valo Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c b/drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c index e7584b842dce..eb5db94f5745 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmutil/d11.c @@ -193,6 +193,9 @@ static void brcmu_d11ac_decchspec(struct brcmu_chan *ch) } break; case BRCMU_CHSPEC_D11AC_BW_160: + ch->bw = BRCMU_CHAN_BW_160; + ch->sb = brcmu_maskget16(ch->chspec, BRCMU_CHSPEC_D11AC_SB_MASK, + BRCMU_CHSPEC_D11AC_SB_SHIFT); switch (ch->sb) { case BRCMU_CHAN_SB_LLL: ch->control_ch_num -= CH_70MHZ_APART; -- GitLab From b65fa7b581f8a50ef147055006a7aa28ddb1086d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 7 Nov 2018 14:18:50 +0100 Subject: [PATCH 0375/1286] iommu/ipmmu-vmsa: Fix crash on early domain free [ Upstream commit e5b78f2e349eef5d4fca5dc1cf5a3b4b2cc27abd ] If iommu_ops.add_device() fails, iommu_ops.domain_free() is still called, leading to a crash, as the domain was only partially initialized: ipmmu-vmsa e67b0000.mmu: Cannot accommodate DMA translation for IOMMU page tables sata_rcar ee300000.sata: Unable to initialize IPMMU context iommu: Failed to add device ee300000.sata to group 0: -22 Unable to handle kernel NULL pointer dereference at virtual address 0000000000000038 ... Call trace: ipmmu_domain_free+0x1c/0xa0 iommu_group_release+0x48/0x68 kobject_put+0x74/0xe8 kobject_del.part.0+0x3c/0x50 kobject_put+0x60/0xe8 iommu_group_get_for_dev+0xa8/0x1f0 ipmmu_add_device+0x1c/0x40 of_iommu_configure+0x118/0x190 Fix this by checking if the domain's context already exists, before trying to destroy it. Signed-off-by: Geert Uytterhoeven Reviewed-by: Robin Murphy Fixes: d25a2a16f0889 ('iommu: Add driver for Renesas VMSA-compatible IPMMU') Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/ipmmu-vmsa.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 5d0ba5f644c4..777aff1f549f 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -424,6 +424,9 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) { + if (!domain->mmu) + return; + /* * Disable the context. Flush the TLB as required when modifying the * context registers. -- GitLab From c6b578b1b4a7c56b469e16e6afd3ec478e1872c3 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 10 Sep 2018 11:43:13 +0100 Subject: [PATCH 0376/1286] can: rcar_can: Fix erroneous registration [ Upstream commit 68c8d209cd4337da4fa04c672f0b62bb735969bc ] Assigning 2 to "renesas,can-clock-select" tricks the driver into registering the CAN interface, even though we don't want that. This patch improves one of the checks to prevent that from happening. Fixes: 862e2b6af9413b43 ("can: rcar_can: support all input clocks") Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Simon Horman Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/rcar/rcar_can.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c index 11662f479e76..771a46083739 100644 --- a/drivers/net/can/rcar/rcar_can.c +++ b/drivers/net/can/rcar/rcar_can.c @@ -24,6 +24,9 @@ #define RCAR_CAN_DRV_NAME "rcar_can" +#define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ + BIT(CLKR_CLKEXT)) + /* Mailbox configuration: * mailbox 60 - 63 - Rx FIFO mailboxes * mailbox 56 - 59 - Tx FIFO mailboxes @@ -789,7 +792,7 @@ static int rcar_can_probe(struct platform_device *pdev) goto fail_clk; } - if (clock_select >= ARRAY_SIZE(clock_names)) { + if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { err = -EINVAL; dev_err(&pdev->dev, "invalid CAN clock selected\n"); goto fail_clk; -- GitLab From 58e0bc43507120ce1185268f588b191c2f5f4df4 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 19 Oct 2018 13:58:01 +0100 Subject: [PATCH 0377/1286] test_firmware: fix error return getting clobbered [ Upstream commit 8bb0a88600f0267cfcc245d34f8c4abe8c282713 ] In the case where eq->fw->size > PAGE_SIZE the error return rc is being set to EINVAL however this is being overwritten to rc = req->fw->size because the error exit path via label 'out' is not being taken. Fix this by adding the jump to the error exit path 'out'. Detected by CoverityScan, CID#1453465 ("Unused value") Fixes: c92316bf8e94 ("test_firmware: add batched firmware tests") Signed-off-by: Colin Ian King Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- lib/test_firmware.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/test_firmware.c b/lib/test_firmware.c index e7008688769b..71d371f97138 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -838,6 +838,7 @@ static ssize_t read_firmware_show(struct device *dev, if (req->fw->size > PAGE_SIZE) { pr_err("Testing interface must use PAGE_SIZE firmware for now\n"); rc = -EINVAL; + goto out; } memcpy(buf, req->fw->data, req->fw->size); -- GitLab From a1270af9b1a0d3ba66ac3425771767e677d2fd0d Mon Sep 17 00:00:00 2001 From: Benson Leung Date: Thu, 8 Nov 2018 15:59:21 -0800 Subject: [PATCH 0378/1286] HID: input: Ignore battery reported by Symbol DS4308 [ Upstream commit 0fd791841a6d67af1155a9c3de54dea51220721e ] The Motorola/Zebra Symbol DS4308-HD is a handheld USB barcode scanner which does not have a battery, but reports one anyway that always has capacity 2. Let's apply the IGNORE quirk to prevent it from being treated like a power supply so that userspaces don't get confused that this accessory is almost out of power and warn the user that they need to charge their wired barcode scanner. Reported here: https://bugs.chromium.org/p/chromium/issues/detail?id=804720 Signed-off-by: Benson Leung Reviewed-by: Benjamin Tissoires Signed-off-by: Benjamin Tissoires Signed-off-by: Sasha Levin --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-input.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 3fc8c0d67592..87904d2adadb 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -1001,6 +1001,7 @@ #define USB_VENDOR_ID_SYMBOL 0x05e0 #define USB_DEVICE_ID_SYMBOL_SCANNER_1 0x0800 #define USB_DEVICE_ID_SYMBOL_SCANNER_2 0x1300 +#define USB_DEVICE_ID_SYMBOL_SCANNER_3 0x1200 #define USB_VENDOR_ID_SYNAPTICS 0x06cb #define USB_DEVICE_ID_SYNAPTICS_TP 0x0001 diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index bb984cc9753b..d146a9b545ee 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -325,6 +325,9 @@ static const struct hid_device_id hid_battery_quirks[] = { { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084), HID_BATTERY_QUIRK_IGNORE }, + { HID_USB_DEVICE(USB_VENDOR_ID_SYMBOL, + USB_DEVICE_ID_SYMBOL_SCANNER_3), + HID_BATTERY_QUIRK_IGNORE }, {} }; -- GitLab From 94f748fd4ed3ac4c90990413681e703444c26225 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Tue, 30 Oct 2018 12:17:10 +0100 Subject: [PATCH 0379/1286] batman-adv: Use explicit tvlv padding for ELP packets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f4156f9656feac21f4de712fac94fae964c5d402 ] The announcement messages of batman-adv COMPAT_VERSION 15 have the possibility to announce additional information via a dynamic TVLV part. This part is optional for the ELP packets and currently not parsed by the Linux implementation. Still out-of-tree versions are using it to transport things like neighbor hashes to optimize the rebroadcast behavior. Since the ELP broadcast packets are smaller than the minimal ethernet packet, it often has to be padded. This is often done (as specified in RFC894) with octets of zero and thus work perfectly fine with the TVLV part (making it a zero length and thus empty). But not all ethernet compatible hardware seems to follow this advice. To avoid ambiguous situations when parsing the TVLV header, just force the 4 bytes (TVLV length + padding) after the required ELP header to zero. Fixes: d6f94d91f766 ("batman-adv: ELP - adding basic infrastructure") Reported-by: Linus Lüssing Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Sasha Levin --- net/batman-adv/bat_v_elp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/batman-adv/bat_v_elp.c b/net/batman-adv/bat_v_elp.c index e92dfedccc16..fbc132f4670e 100644 --- a/net/batman-adv/bat_v_elp.c +++ b/net/batman-adv/bat_v_elp.c @@ -338,19 +338,21 @@ static void batadv_v_elp_periodic_work(struct work_struct *work) */ int batadv_v_elp_iface_enable(struct batadv_hard_iface *hard_iface) { + static const size_t tvlv_padding = sizeof(__be32); struct batadv_elp_packet *elp_packet; unsigned char *elp_buff; u32 random_seqno; size_t size; int res = -ENOMEM; - size = ETH_HLEN + NET_IP_ALIGN + BATADV_ELP_HLEN; + size = ETH_HLEN + NET_IP_ALIGN + BATADV_ELP_HLEN + tvlv_padding; hard_iface->bat_v.elp_skb = dev_alloc_skb(size); if (!hard_iface->bat_v.elp_skb) goto out; skb_reserve(hard_iface->bat_v.elp_skb, ETH_HLEN + NET_IP_ALIGN); - elp_buff = skb_put_zero(hard_iface->bat_v.elp_skb, BATADV_ELP_HLEN); + elp_buff = skb_put_zero(hard_iface->bat_v.elp_skb, + BATADV_ELP_HLEN + tvlv_padding); elp_packet = (struct batadv_elp_packet *)elp_buff; elp_packet->packet_type = BATADV_ELP; -- GitLab From 2761d3237145412c1405b204f152b796bf9df4a2 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Wed, 7 Nov 2018 23:09:12 +0100 Subject: [PATCH 0380/1286] batman-adv: Expand merged fragment buffer for full packet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d7d8bbb40a5b1f682ee6589e212934f4c6b8ad60 ] The complete size ("total_size") of the fragmented packet is stored in the fragment header and in the size of the fragment chain. When the fragments are ready for merge, the skbuff's tail of the first fragment is expanded to have enough room after the data pointer for at least total_size. This means that it gets expanded by total_size - first_skb->len. But this is ignoring the fact that after expanding the buffer, the fragment header is pulled by from this buffer. Assuming that the tailroom of the buffer was already 0, the buffer after the data pointer of the skbuff is now only total_size - len(fragment_header) large. When the merge function is then processing the remaining fragments, the code to copy the data over to the merged skbuff will cause an skb_over_panic when it tries to actually put enough data to fill the total_size bytes of the packet. The size of the skb_pull must therefore also be taken into account when the buffer's tailroom is expanded. Fixes: 610bfc6bc99b ("batman-adv: Receive fragmented packets and merge") Reported-by: Martin Weinelt Co-authored-by: Linus Lüssing Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Sasha Levin --- net/batman-adv/fragmentation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/batman-adv/fragmentation.c b/net/batman-adv/fragmentation.c index b6abd19ab23e..c6d37d22bd12 100644 --- a/net/batman-adv/fragmentation.c +++ b/net/batman-adv/fragmentation.c @@ -274,7 +274,7 @@ batadv_frag_merge_packets(struct hlist_head *chain) kfree(entry); packet = (struct batadv_frag_packet *)skb_out->data; - size = ntohs(packet->total_size); + size = ntohs(packet->total_size) + hdr_size; /* Make room for the rest of the fragments. */ if (pskb_expand_head(skb_out, 0, size - skb_out->len, GFP_ATOMIC) < 0) { -- GitLab From 41cb057690134a335b689be7e8db6d46db54a8ed Mon Sep 17 00:00:00 2001 From: Filippo Sironi Date: Mon, 12 Nov 2018 12:26:30 +0000 Subject: [PATCH 0381/1286] amd/iommu: Fix Guest Virtual APIC Log Tail Address Register [ Upstream commit ab99be4683d9db33b100497d463274ebd23bd67e ] This register should have been programmed with the physical address of the memory location containing the shadow tail pointer for the guest virtual APIC log instead of the base address. Fixes: 8bda0cfbdc1a ('iommu/amd: Detect and initialize guest vAPIC log') Signed-off-by: Filippo Sironi Signed-off-by: Wei Wang Signed-off-by: Suravee Suthikulpanit Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/amd_iommu_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 6fe2d0346073..b97984a5ddad 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -796,7 +796,8 @@ static int iommu_init_ga_log(struct amd_iommu *iommu) entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, &entry, sizeof(entry)); - entry = (iommu_virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL; + entry = (iommu_virt_to_phys(iommu->ga_log_tail) & + (BIT_ULL(52)-1)) & ~7ULL; memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, &entry, sizeof(entry)); writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); -- GitLab From fd358f42a60d85798b6d4715cd936b438fa2cc3e Mon Sep 17 00:00:00 2001 From: Sudarsana Reddy Kalluru Date: Sun, 11 Nov 2018 18:27:34 -0800 Subject: [PATCH 0382/1286] bnx2x: Assign unique DMAE channel number for FW DMAE transactions. [ Upstream commit 77e461d14ed141253573eeeb4d34eccc51e38328 ] Driver assigns DMAE channel 0 for FW as part of START_RAMROD command. FW uses this channel for DMAE operations (e.g., TIME_SYNC implementation). Driver also uses the same channel 0 for DMAE operations for some of the PFs (e.g., PF0 on Port0). This could lead to concurrent access to the DMAE channel by FW and driver which is not legal. Hence need to assign unique DMAE id for FW. Currently following DMAE channels are used by the clients, MFW - OCBB/OCSD functionality uses DMAE channel 14/15 Driver 0-3 and 8-11 (for PF dmae operations) 4 and 12 (for stats requests) Assigning unique dmae_id '13' to the FW. Changes from previous version: ------------------------------ v2: Incorporated the review comments. Signed-off-by: Sudarsana Reddy Kalluru Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 7 +++++++ drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h index 828e2e56b75e..1b7f4342dab9 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h @@ -2187,6 +2187,13 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ E1HVN_MAX) +/* Following is the DMAE channel number allocation for the clients. + * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively. + * Driver: 0-3 and 8-11 (for PF dmae operations) + * 4 and 12 (for stats requests) + */ +#define BNX2X_FW_DMAE_C 13 /* Channel for FW DMAE operations */ + /* PCIE link and speed */ #define PCICFG_LINK_WIDTH 0x1f00000 #define PCICFG_LINK_WIDTH_SHIFT 20 diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c index 8baf9d3eb4b1..453bfd83a070 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c @@ -6149,6 +6149,7 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp, rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag); rdata->path_id = BP_PATH(bp); rdata->network_cos_mode = start_params->network_cos_mode; + rdata->dmae_cmd_id = BNX2X_FW_DMAE_C; rdata->vxlan_dst_port = cpu_to_le16(start_params->vxlan_dst_port); rdata->geneve_dst_port = cpu_to_le16(start_params->geneve_dst_port); -- GitLab From 0f1c847db352a87f9974aa1869ca3e6f26b621f7 Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Mon, 12 Nov 2018 12:50:20 +0200 Subject: [PATCH 0383/1286] qed: Fix PTT leak in qed_drain() [ Upstream commit 9aaa4e8ba12972d674caeefbc5f88d83235dd697 ] Release PTT before entering error flow. Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_main.c b/drivers/net/ethernet/qlogic/qed/qed_main.c index 954f7ce4cf28..ecc2d4296526 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_main.c +++ b/drivers/net/ethernet/qlogic/qed/qed_main.c @@ -1561,9 +1561,9 @@ static int qed_drain(struct qed_dev *cdev) return -EBUSY; } rc = qed_mcp_drain(hwfn, ptt); + qed_ptt_release(hwfn, ptt); if (rc) return rc; - qed_ptt_release(hwfn, ptt); } return 0; -- GitLab From 93663e617b8fdcaceb6f407af6e494df2d5c7067 Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Mon, 12 Nov 2018 12:50:23 +0200 Subject: [PATCH 0384/1286] qed: Fix reading wrong value in loop condition [ Upstream commit ed4eac20dcffdad47709422e0cb925981b056668 ] The value of "sb_index" is written by the hardware. Reading its value and writing it to "index" must finish before checking the loop condition. Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_int.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c index 719cdbfe1695..7746417130bd 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_int.c +++ b/drivers/net/ethernet/qlogic/qed/qed_int.c @@ -992,6 +992,8 @@ static int qed_int_attentions(struct qed_hwfn *p_hwfn) */ do { index = p_sb_attn->sb_index; + /* finish reading index before the loop condition */ + dma_rmb(); attn_bits = le32_to_cpu(p_sb_attn->atten_bits); attn_acks = le32_to_cpu(p_sb_attn->atten_ack); } while (index != p_sb_attn->sb_index); -- GitLab From 65d9e9821b86155dc810ff08c12cc29c7fabbca9 Mon Sep 17 00:00:00 2001 From: Shen Jing Date: Thu, 1 Nov 2018 15:35:17 +0530 Subject: [PATCH 0385/1286] Revert "usb: gadget: ffs: Fix BUG when userland exits with submitted AIO transfers" [ Upstream commit a9c859033f6ec772f8e3228c343bb1321584ae0e ] This reverts commit b4194da3f9087dd38d91b40f9bec42d59ce589a8 since it causes list corruption followed by kernel panic: Workqueue: adb ffs_aio_cancel_worker RIP: 0010:__list_add_valid+0x4d/0x70 Call Trace: insert_work+0x47/0xb0 __queue_work+0xf6/0x400 queue_work_on+0x65/0x70 dwc3_gadget_giveback+0x44/0x50 [dwc3] dwc3_gadget_ep_dequeue+0x83/0x2d0 [dwc3] ? finish_wait+0x80/0x80 usb_ep_dequeue+0x1e/0x90 process_one_work+0x18c/0x3b0 worker_thread+0x3c/0x390 ? process_one_work+0x3b0/0x3b0 kthread+0x11e/0x140 ? kthread_create_worker_on_cpu+0x70/0x70 ret_from_fork+0x3a/0x50 This issue is seen with warm reboot stability testing. Signed-off-by: Shen Jing Signed-off-by: Saranya Gopal Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/f_fs.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 17467545391b..52e6897fa35a 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -219,7 +219,6 @@ struct ffs_io_data { struct mm_struct *mm; struct work_struct work; - struct work_struct cancellation_work; struct usb_ep *ep; struct usb_request *req; @@ -1074,31 +1073,22 @@ ffs_epfile_open(struct inode *inode, struct file *file) return 0; } -static void ffs_aio_cancel_worker(struct work_struct *work) -{ - struct ffs_io_data *io_data = container_of(work, struct ffs_io_data, - cancellation_work); - - ENTER(); - - usb_ep_dequeue(io_data->ep, io_data->req); -} - static int ffs_aio_cancel(struct kiocb *kiocb) { struct ffs_io_data *io_data = kiocb->private; - struct ffs_data *ffs = io_data->ffs; + struct ffs_epfile *epfile = kiocb->ki_filp->private_data; int value; ENTER(); - if (likely(io_data && io_data->ep && io_data->req)) { - INIT_WORK(&io_data->cancellation_work, ffs_aio_cancel_worker); - queue_work(ffs->io_completion_wq, &io_data->cancellation_work); - value = -EINPROGRESS; - } else { + spin_lock_irq(&epfile->ffs->eps_lock); + + if (likely(io_data && io_data->ep && io_data->req)) + value = usb_ep_dequeue(io_data->ep, io_data->req); + else value = -EINVAL; - } + + spin_unlock_irq(&epfile->ffs->eps_lock); return value; } -- GitLab From 471b2b9c525424e5213b4d6084ed1d12758ce8c8 Mon Sep 17 00:00:00 2001 From: Jack Morgenstein Date: Thu, 15 Nov 2018 18:05:13 +0200 Subject: [PATCH 0386/1286] net/mlx4_core: Zero out lkey field in SW2HW_MPT fw command [ Upstream commit bd85fbc2038a1bbe84990b23ff69b6fc81a32b2c ] When re-registering a user mr, the mpt information for the existing mr when running SRIOV is obtained via the QUERY_MPT fw command. The returned information includes the mpt's lkey. This retrieved mpt information is used to move the mpt back to hardware ownership in the rereg flow (via the SW2HW_MPT fw command when running SRIOV). The fw API spec states that for SW2HW_MPT, the lkey field must be zero. Any ConnectX-3 PF driver which checks for strict spec adherence will return failure for SW2HW_MPT if the lkey field is not zero (although the fw in practice ignores this field for SW2HW_MPT). Thus, in order to conform to the fw API spec, set the lkey field to zero before invoking SW2HW_MPT when running SRIOV. Fixes: e630664c8383 ("mlx4_core: Add helper functions to support MR re-registration") Signed-off-by: Jack Morgenstein Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx4/mr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx4/mr.c b/drivers/net/ethernet/mellanox/mlx4/mr.c index c7c0764991c9..20043f82c1d8 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mr.c +++ b/drivers/net/ethernet/mellanox/mlx4/mr.c @@ -363,6 +363,7 @@ int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, buf); + (*mpt_entry)->lkey = 0; err = mlx4_SW2HW_MPT(dev, mailbox, key); } -- GitLab From e6e5d3dda0ea79e4c9a52ed2031ed832713f3e99 Mon Sep 17 00:00:00 2001 From: Tariq Toukan Date: Thu, 15 Nov 2018 18:05:14 +0200 Subject: [PATCH 0387/1286] net/mlx4_core: Fix uninitialized variable compilation warning [ Upstream commit 3ea7e7ea53c9f6ee41cb69a29c375fe9dd9a56a7 ] Initialize the uid variable to zero to avoid the compilation warning. Fixes: 7a89399ffad7 ("net/mlx4: Add mlx4_bitmap zone allocator") Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx4/alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/alloc.c b/drivers/net/ethernet/mellanox/mlx4/alloc.c index 6dabd983e7e0..94f4dc4a77e9 100644 --- a/drivers/net/ethernet/mellanox/mlx4/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx4/alloc.c @@ -337,7 +337,7 @@ void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc) static u32 __mlx4_alloc_from_zone(struct mlx4_zone_entry *zone, int count, int align, u32 skip_mask, u32 *puid) { - u32 uid; + u32 uid = 0; u32 res; struct mlx4_zone_allocator *zone_alloc = zone->allocator; struct mlx4_zone_entry *curr_node; -- GitLab From 934f4965b46b99885e31b89fbf3240cb034c0959 Mon Sep 17 00:00:00 2001 From: Aya Levin Date: Thu, 15 Nov 2018 18:05:15 +0200 Subject: [PATCH 0388/1286] net/mlx4: Fix UBSAN warning of signed integer overflow [ Upstream commit a463146e67c848cbab5ce706d6528281b7cded08 ] UBSAN: Undefined behavior in drivers/net/ethernet/mellanox/mlx4/resource_tracker.c:626:29 signed integer overflow: 1802201963 + 1802201963 cannot be represented in type 'int' The union of res_reserved and res_port_rsvd[MLX4_MAX_PORTS] monitors granting of reserved resources. The grant operation is calculated and protected, thus both members of the union cannot be negative. Changed type of res_reserved and of res_port_rsvd[MLX4_MAX_PORTS] from signed int to unsigned int, allowing large value. Fixes: 5a0d0a6161ae ("mlx4: Structures and init/teardown for VF resource quotas") Signed-off-by: Aya Levin Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx4/mlx4.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4.h b/drivers/net/ethernet/mellanox/mlx4/mlx4.h index c68da1986e51..aaeb446bba62 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4.h @@ -541,8 +541,8 @@ struct slave_list { struct resource_allocator { spinlock_t alloc_lock; /* protect quotas */ union { - int res_reserved; - int res_port_rsvd[MLX4_MAX_PORTS]; + unsigned int res_reserved; + unsigned int res_port_rsvd[MLX4_MAX_PORTS]; }; union { int res_free; -- GitLab From 6c65ce92019b50861cd0b1763da8ea8217d6a420 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 8 Nov 2018 17:52:53 +0100 Subject: [PATCH 0389/1286] gpio: mockup: fix indicated direction [ Upstream commit bff466bac59994cfcceabe4d0be5fdc1c20cd5b8 ] Commit 3edfb7bd76bd ("gpiolib: Show correct direction from the beginning") fixed an existing issue but broke libgpiod tests by changing the default direction of dummy lines to output. We don't break user-space so make gpio-mockup behave as before. Signed-off-by: Bartosz Golaszewski Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/gpio/gpio-mockup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c index 9532d86a82f7..d99c8d8da9a0 100644 --- a/drivers/gpio/gpio-mockup.c +++ b/drivers/gpio/gpio-mockup.c @@ -35,8 +35,8 @@ #define GPIO_MOCKUP_MAX_RANGES (GPIO_MOCKUP_MAX_GC * 2) enum { - GPIO_MOCKUP_DIR_OUT = 0, - GPIO_MOCKUP_DIR_IN = 1, + GPIO_MOCKUP_DIR_IN = 0, + GPIO_MOCKUP_DIR_OUT = 1, }; /* @@ -112,7 +112,7 @@ static int gpio_mockup_get_direction(struct gpio_chip *gc, unsigned int offset) { struct gpio_mockup_chip *chip = gpiochip_get_data(gc); - return chip->lines[offset].dir; + return !chip->lines[offset].dir; } static int gpio_mockup_name_lines(struct device *dev, -- GitLab From 60adf764a94f393d9ec56e05d976987d4d3cfdd3 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Fri, 16 Nov 2018 19:43:27 -0800 Subject: [PATCH 0390/1286] mtd: rawnand: qcom: Namespace prefix some commands [ Upstream commit 33bf5519ae5dd356b182a94e3622f42860274a38 ] PAGE_READ is used by RISC-V arch code included through mm headers, and it makes sense to bring in a prefix on these in the driver. drivers/mtd/nand/raw/qcom_nandc.c:153: warning: "PAGE_READ" redefined #define PAGE_READ 0x2 In file included from include/linux/memremap.h:7, from include/linux/mm.h:27, from include/linux/scatterlist.h:8, from include/linux/dma-mapping.h:11, from drivers/mtd/nand/raw/qcom_nandc.c:17: arch/riscv/include/asm/pgtable.h:48: note: this is the location of the previous definition Caught by riscv allmodconfig. Signed-off-by: Olof Johansson Reviewed-by: Miquel Raynal Signed-off-by: Boris Brezillon Signed-off-by: Sasha Levin --- drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c index b49ca02b399d..09d5f7df6023 100644 --- a/drivers/mtd/nand/qcom_nandc.c +++ b/drivers/mtd/nand/qcom_nandc.c @@ -149,15 +149,15 @@ #define NAND_VERSION_MINOR_SHIFT 16 /* NAND OP_CMDs */ -#define PAGE_READ 0x2 -#define PAGE_READ_WITH_ECC 0x3 -#define PAGE_READ_WITH_ECC_SPARE 0x4 -#define PROGRAM_PAGE 0x6 -#define PAGE_PROGRAM_WITH_ECC 0x7 -#define PROGRAM_PAGE_SPARE 0x9 -#define BLOCK_ERASE 0xa -#define FETCH_ID 0xb -#define RESET_DEVICE 0xd +#define OP_PAGE_READ 0x2 +#define OP_PAGE_READ_WITH_ECC 0x3 +#define OP_PAGE_READ_WITH_ECC_SPARE 0x4 +#define OP_PROGRAM_PAGE 0x6 +#define OP_PAGE_PROGRAM_WITH_ECC 0x7 +#define OP_PROGRAM_PAGE_SPARE 0x9 +#define OP_BLOCK_ERASE 0xa +#define OP_FETCH_ID 0xb +#define OP_RESET_DEVICE 0xd /* Default Value for NAND_DEV_CMD_VLD */ #define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ @@ -629,11 +629,11 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read) if (read) { if (host->use_ecc) - cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; + cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; else - cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; + cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE; } else { - cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; + cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; } if (host->use_ecc) { @@ -1030,7 +1030,7 @@ static int nandc_param(struct qcom_nand_host *host) * in use. we configure the controller to perform a raw read of 512 * bytes to read onfi params */ - nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE); + nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE); nandc_set_reg(nandc, NAND_ADDR0, 0); nandc_set_reg(nandc, NAND_ADDR1, 0); nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE @@ -1084,7 +1084,7 @@ static int erase_block(struct qcom_nand_host *host, int page_addr) struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); nandc_set_reg(nandc, NAND_FLASH_CMD, - BLOCK_ERASE | PAGE_ACC | LAST_PAGE); + OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE); nandc_set_reg(nandc, NAND_ADDR0, page_addr); nandc_set_reg(nandc, NAND_ADDR1, 0); nandc_set_reg(nandc, NAND_DEV0_CFG0, @@ -1115,7 +1115,7 @@ static int read_id(struct qcom_nand_host *host, int column) if (column == -1) return 0; - nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID); + nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID); nandc_set_reg(nandc, NAND_ADDR0, column); nandc_set_reg(nandc, NAND_ADDR1, 0); nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, @@ -1136,7 +1136,7 @@ static int reset(struct qcom_nand_host *host) struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE); + nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE); nandc_set_reg(nandc, NAND_EXEC_CMD, 1); write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); -- GitLab From 16f2433ede2374060ccb79767fcd3a69cde2a22f Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Wed, 14 Nov 2018 05:35:20 +0000 Subject: [PATCH 0391/1286] HID: multitouch: Add pointstick support for Cirque Touchpad [ Upstream commit 12d43aacf9a74d0eb66fd0ea54ebeb79ca28940f ] Cirque Touchpad/Pointstick combo is similar to Alps devices, it requires MT_CLS_WIN_8_DUAL to expose its pointstick as a mouse. Signed-off-by: Kai-Heng Feng Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/hid-ids.h | 3 +++ drivers/hid/hid-multitouch.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 87904d2adadb..fcc688df694c 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -266,6 +266,9 @@ #define USB_VENDOR_ID_CIDC 0x1677 +#define I2C_VENDOR_ID_CIRQUE 0x0488 +#define I2C_PRODUCT_ID_CIRQUE_121F 0x121F + #define USB_VENDOR_ID_CJTOUCH 0x24b8 #define USB_DEVICE_ID_CJTOUCH_MULTI_TOUCH_0020 0x0020 #define USB_DEVICE_ID_CJTOUCH_MULTI_TOUCH_0040 0x0040 diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c index c3b9bd5dba75..07d92d4a9f7c 100644 --- a/drivers/hid/hid-multitouch.c +++ b/drivers/hid/hid-multitouch.c @@ -1474,6 +1474,12 @@ static const struct hid_device_id mt_devices[] = { MT_USB_DEVICE(USB_VENDOR_ID_CHUNGHWAT, USB_DEVICE_ID_CHUNGHWAT_MULTITOUCH) }, + /* Cirque devices */ + { .driver_data = MT_CLS_WIN_8_DUAL, + HID_DEVICE(BUS_I2C, HID_GROUP_MULTITOUCH_WIN_8, + I2C_VENDOR_ID_CIRQUE, + I2C_PRODUCT_ID_CIRQUE_121F) }, + /* CJTouch panels */ { .driver_data = MT_CLS_NSMU, MT_USB_DEVICE(USB_VENDOR_ID_CJTOUCH, -- GitLab From 4b4c6714a19792f616fc03696594dafbb5a9b9a1 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Fri, 16 Nov 2018 08:25:49 -0600 Subject: [PATCH 0392/1286] mtd: spi-nor: Fix Cadence QSPI page fault kernel panic [ Upstream commit a6a66f80c85e8e20573ca03fabf32445954a88d5 ] The current Cadence QSPI driver caused a kernel panic sporadically when writing to QSPI. The problem was caused by writing more bytes than needed because the QSPI operated on 4 bytes at a time. [ 11.202044] Unable to handle kernel paging request at virtual address bffd3000 [ 11.209254] pgd = e463054d [ 11.211948] [bffd3000] *pgd=2fffb811, *pte=00000000, *ppte=00000000 [ 11.218202] Internal error: Oops: 7 [#1] SMP ARM [ 11.222797] Modules linked in: [ 11.225844] CPU: 1 PID: 1317 Comm: systemd-hwdb Not tainted 4.17.7-d0c45cd44a8f [ 11.235796] Hardware name: Altera SOCFPGA Arria10 [ 11.240487] PC is at __raw_writesl+0x70/0xd4 [ 11.244741] LR is at cqspi_write+0x1a0/0x2cc On a page boundary limit the number of bytes copied from the tx buffer to remain within the page. This patch uses a temporary buffer to hold the 4 bytes to write and then copies only the bytes required from the tx buffer. Reported-by: Adrian Amborzewicz Signed-off-by: Thor Thayer Signed-off-by: Boris Brezillon Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/cadence-quadspi.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 8d89204b90d2..f22dd34f4f83 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -625,9 +625,23 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, reg_base + CQSPI_REG_INDIRECTWR); while (remaining > 0) { + size_t write_words, mod_bytes; + write_bytes = remaining > page_size ? page_size : remaining; - iowrite32_rep(cqspi->ahb_base, txbuf, - DIV_ROUND_UP(write_bytes, 4)); + write_words = write_bytes / 4; + mod_bytes = write_bytes % 4; + /* Write 4 bytes at a time then single bytes. */ + if (write_words) { + iowrite32_rep(cqspi->ahb_base, txbuf, write_words); + txbuf += (write_words * 4); + } + if (mod_bytes) { + unsigned int temp = 0xFFFFFFFF; + + memcpy(&temp, txbuf, mod_bytes); + iowrite32(temp, cqspi->ahb_base); + txbuf += mod_bytes; + } ret = wait_for_completion_timeout(&cqspi->transfer_complete, msecs_to_jiffies @@ -638,7 +652,6 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, goto failwr; } - txbuf += write_bytes; remaining -= write_bytes; if (remaining > 0) -- GitLab From 9dded0ffdeb7fa10698d534978892b406b60c91e Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Mon, 19 Nov 2018 16:28:30 +0200 Subject: [PATCH 0393/1286] qed: Fix bitmap_weight() check [ Upstream commit 276d43f0ae963312c0cd0e2b9a85fd11ac65dfcc ] Fix the condition which verifies that only one flag is set. The API bitmap_weight() should receive size in bits instead of bytes. Fixes: b5a9ee7cf3be ("qed: Revise QM cofiguration") Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_dev.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c index ef2374699726..a51cd1028ecb 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dev.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c @@ -440,8 +440,11 @@ static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, struct qed_qm_info *qm_info = &p_hwfn->qm_info; /* Can't have multiple flags set here */ - if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1) + if (bitmap_weight((unsigned long *)&pq_flags, + sizeof(pq_flags) * BITS_PER_BYTE) > 1) { + DP_ERR(p_hwfn, "requested multiple pq flags 0x%x\n", pq_flags); goto err; + } switch (pq_flags) { case PQ_FLAGS_RLS: -- GitLab From f7a6fd087a300dabc4dbde84b1f2d4d0ac5173e0 Mon Sep 17 00:00:00 2001 From: Denis Bolotin Date: Mon, 19 Nov 2018 16:28:31 +0200 Subject: [PATCH 0394/1286] qed: Fix QM getters to always return a valid pq [ Upstream commit eb62cca9bee842e5b23bd0ddfb1f271ca95e8759 ] The getter callers doesn't know the valid Physical Queues (PQ) values. This patch makes sure that a valid PQ will always be returned. The patch consists of 3 fixes: - When qed_init_qm_get_idx_from_flags() receives a disabled flag, it returned PQ 0, which can potentially be another function's pq. Verify that flag is enabled, otherwise return default start_pq. - When qed_init_qm_get_idx_from_flags() receives an unknown flag, it returned NULL and could lead to a segmentation fault. Return default start_pq instead. - A modulo operation was added to MCOS/VFS PQ getters to make sure the PQ returned is in range of the required flag. Fixes: b5a9ee7cf3be ("qed: Revise QM cofiguration") Signed-off-by: Denis Bolotin Signed-off-by: Michal Kalderon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_dev.c | 24 +++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c index a51cd1028ecb..16953c4ebd71 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dev.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c @@ -446,6 +446,11 @@ static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, goto err; } + if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) { + DP_ERR(p_hwfn, "pq flag 0x%x is not set\n", pq_flags); + goto err; + } + switch (pq_flags) { case PQ_FLAGS_RLS: return &qm_info->first_rl_pq; @@ -468,8 +473,7 @@ static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, } err: - DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); - return NULL; + return &qm_info->start_pq; } /* save pq index in qm info */ @@ -493,20 +497,32 @@ u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) { u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); + if (max_tc == 0) { + DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", + PQ_FLAGS_MCOS); + return p_hwfn->qm_info.start_pq; + } + if (tc > max_tc) DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); - return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; + return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); } u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) { u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); + if (max_vf == 0) { + DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", + PQ_FLAGS_VFS); + return p_hwfn->qm_info.start_pq; + } + if (vf > max_vf) DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); - return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; + return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); } u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl) -- GitLab From d0decb8d7cbb225336e043a63e9a8c72498834fd Mon Sep 17 00:00:00 2001 From: Vincent Chen Date: Wed, 21 Nov 2018 09:38:11 +0800 Subject: [PATCH 0395/1286] net: faraday: ftmac100: remove netif_running(netdev) check before disabling interrupts [ Upstream commit 426a593e641ebf0d9288f0a2fcab644a86820220 ] In the original ftmac100_interrupt(), the interrupts are only disabled when the condition "netif_running(netdev)" is true. However, this condition causes kerenl hang in the following case. When the user requests to disable the network device, kernel will clear the bit __LINK_STATE_START from the dev->state and then call the driver's ndo_stop function. Network device interrupts are not blocked during this process. If an interrupt occurs between clearing __LINK_STATE_START and stopping network device, kernel cannot disable the interrupts due to the condition "netif_running(netdev)" in the ISR. Hence, kernel will hang due to the continuous interruption of the network device. In order to solve the above problem, the interrupts of the network device should always be disabled in the ISR without being restricted by the condition "netif_running(netdev)". [V2] Remove unnecessary curly braces. Signed-off-by: Vincent Chen Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/faraday/ftmac100.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftmac100.c b/drivers/net/ethernet/faraday/ftmac100.c index 66928a922824..415fd93e9930 100644 --- a/drivers/net/ethernet/faraday/ftmac100.c +++ b/drivers/net/ethernet/faraday/ftmac100.c @@ -870,11 +870,10 @@ static irqreturn_t ftmac100_interrupt(int irq, void *dev_id) struct net_device *netdev = dev_id; struct ftmac100 *priv = netdev_priv(netdev); - if (likely(netif_running(netdev))) { - /* Disable interrupts for polling */ - ftmac100_disable_all_int(priv); + /* Disable interrupts for polling */ + ftmac100_disable_all_int(priv); + if (likely(netif_running(netdev))) napi_schedule(&priv->napi); - } return IRQ_HANDLED; } -- GitLab From 84f49bb07f9d8f48891976229a6eaed9e1a4d6ca Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Wed, 21 Nov 2018 17:53:47 +0800 Subject: [PATCH 0396/1286] iommu/vt-d: Use memunmap to free memremap [ Upstream commit 829383e183728dec7ed9150b949cd6de64127809 ] memunmap() should be used to free the return of memremap(), not iounmap(). Fixes: dfddb969edf0 ('iommu/vt-d: Switch from ioremap_cache to memremap') Signed-off-by: Pan Bian Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/intel-iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index aaf3fed97477..e86c1c8ec7f6 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -3086,7 +3086,7 @@ static int copy_context_table(struct intel_iommu *iommu, } if (old_ce) - iounmap(old_ce); + memunmap(old_ce); ret = 0; if (devfn < 0x80) -- GitLab From dab45f4d03f01e8d6612803518c225bf859f796c Mon Sep 17 00:00:00 2001 From: Tigran Mkrtchyan Date: Wed, 21 Nov 2018 12:25:41 +0100 Subject: [PATCH 0397/1286] flexfiles: use per-mirror specified stateid for IO [ Upstream commit bb21ce0ad227b69ec0f83279297ee44232105d96 ] rfc8435 says: For tight coupling, ffds_stateid provides the stateid to be used by the client to access the file. However current implementation replaces per-mirror provided stateid with by open or lock stateid. Ensure that per-mirror stateid is used by ff_layout_write_prepare_v4 and nfs4_ff_layout_prepare_ds. Signed-off-by: Tigran Mkrtchyan Signed-off-by: Rick Macklem Signed-off-by: Trond Myklebust Signed-off-by: Sasha Levin --- fs/nfs/flexfilelayout/flexfilelayout.c | 21 +++++++++------------ fs/nfs/flexfilelayout/flexfilelayout.h | 4 ++++ fs/nfs/flexfilelayout/flexfilelayoutdev.c | 19 +++++++++++++++++++ 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c index b0fa83a60754..13612a848378 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.c +++ b/fs/nfs/flexfilelayout/flexfilelayout.c @@ -1365,12 +1365,7 @@ static void ff_layout_read_prepare_v4(struct rpc_task *task, void *data) task)) return; - if (ff_layout_read_prepare_common(task, hdr)) - return; - - if (nfs4_set_rw_stateid(&hdr->args.stateid, hdr->args.context, - hdr->args.lock_context, FMODE_READ) == -EIO) - rpc_exit(task, -EIO); /* lost lock, terminate I/O */ + ff_layout_read_prepare_common(task, hdr); } static void ff_layout_read_call_done(struct rpc_task *task, void *data) @@ -1539,12 +1534,7 @@ static void ff_layout_write_prepare_v4(struct rpc_task *task, void *data) task)) return; - if (ff_layout_write_prepare_common(task, hdr)) - return; - - if (nfs4_set_rw_stateid(&hdr->args.stateid, hdr->args.context, - hdr->args.lock_context, FMODE_WRITE) == -EIO) - rpc_exit(task, -EIO); /* lost lock, terminate I/O */ + ff_layout_write_prepare_common(task, hdr); } static void ff_layout_write_call_done(struct rpc_task *task, void *data) @@ -1734,6 +1724,10 @@ ff_layout_read_pagelist(struct nfs_pgio_header *hdr) fh = nfs4_ff_layout_select_ds_fh(lseg, idx); if (fh) hdr->args.fh = fh; + + if (!nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) + goto out_failed; + /* * Note that if we ever decide to split across DSes, * then we may need to handle dense-like offsets. @@ -1796,6 +1790,9 @@ ff_layout_write_pagelist(struct nfs_pgio_header *hdr, int sync) if (fh) hdr->args.fh = fh; + if (!nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) + goto out_failed; + /* * Note that if we ever decide to split across DSes, * then we may need to handle dense-like offsets. diff --git a/fs/nfs/flexfilelayout/flexfilelayout.h b/fs/nfs/flexfilelayout/flexfilelayout.h index 679cb087ef3f..d6515f1584f3 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.h +++ b/fs/nfs/flexfilelayout/flexfilelayout.h @@ -214,6 +214,10 @@ unsigned int ff_layout_fetch_ds_ioerr(struct pnfs_layout_hdr *lo, unsigned int maxnum); struct nfs_fh * nfs4_ff_layout_select_ds_fh(struct pnfs_layout_segment *lseg, u32 mirror_idx); +int +nfs4_ff_layout_select_ds_stateid(struct pnfs_layout_segment *lseg, + u32 mirror_idx, + nfs4_stateid *stateid); struct nfs4_pnfs_ds * nfs4_ff_layout_prepare_ds(struct pnfs_layout_segment *lseg, u32 ds_idx, diff --git a/fs/nfs/flexfilelayout/flexfilelayoutdev.c b/fs/nfs/flexfilelayout/flexfilelayoutdev.c index d62279d3fc5d..9f69e83810ca 100644 --- a/fs/nfs/flexfilelayout/flexfilelayoutdev.c +++ b/fs/nfs/flexfilelayout/flexfilelayoutdev.c @@ -369,6 +369,25 @@ nfs4_ff_layout_select_ds_fh(struct pnfs_layout_segment *lseg, u32 mirror_idx) return fh; } +int +nfs4_ff_layout_select_ds_stateid(struct pnfs_layout_segment *lseg, + u32 mirror_idx, + nfs4_stateid *stateid) +{ + struct nfs4_ff_layout_mirror *mirror = FF_LAYOUT_COMP(lseg, mirror_idx); + + if (!ff_layout_mirror_valid(lseg, mirror, false)) { + pr_err_ratelimited("NFS: %s: No data server for mirror offset index %d\n", + __func__, mirror_idx); + goto out; + } + + nfs4_stateid_copy(stateid, &mirror->stateid); + return 1; +out: + return 0; +} + /** * nfs4_ff_layout_prepare_ds - prepare a DS connection for an RPC call * @lseg: the layout segment we're operating on -- GitLab From 1c1fbd4d2e9200f4b8a69d2b517e5708b0965a68 Mon Sep 17 00:00:00 2001 From: Thomas Falcon Date: Wed, 21 Nov 2018 11:17:58 -0600 Subject: [PATCH 0398/1286] ibmvnic: Fix RX queue buffer cleanup [ Upstream commit b7cdec3d699db2e5985ad39de0f25d3b6111928e ] The wrong index is used when cleaning up RX buffer objects during release of RX queues. Update to use the correct index counter. Signed-off-by: Thomas Falcon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/ibm/ibmvnic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c index 5c7134ccc1fd..14c53ed5cca6 100644 --- a/drivers/net/ethernet/ibm/ibmvnic.c +++ b/drivers/net/ethernet/ibm/ibmvnic.c @@ -457,8 +457,8 @@ static void release_rx_pools(struct ibmvnic_adapter *adapter) for (j = 0; j < rx_pool->size; j++) { if (rx_pool->rx_buff[j].skb) { - dev_kfree_skb_any(rx_pool->rx_buff[i].skb); - rx_pool->rx_buff[i].skb = NULL; + dev_kfree_skb_any(rx_pool->rx_buff[j].skb); + rx_pool->rx_buff[j].skb = NULL; } } -- GitLab From 63e307e81cffa11dbc8b513ee2b951ffa59fc61c Mon Sep 17 00:00:00 2001 From: Hangbin Liu Date: Thu, 22 Nov 2018 16:15:28 +0800 Subject: [PATCH 0399/1286] team: no need to do team_notify_peers or team_mcast_rejoin when disabling port [ Upstream commit 5ed9dc99107144f83b6c1bb52a69b58875baf540 ] team_notify_peers() will send ARP and NA to notify peers. team_mcast_rejoin() will send multicast join group message to notify peers. We should do this when enabling/changed to a new port. But it doesn't make sense to do it when a port is disabled. On the other hand, when we set mcast_rejoin_count to 2, and do a failover, team_port_disable() will increase mcast_rejoin.count_pending to 2 and then team_port_enable() will increase mcast_rejoin.count_pending to 4. We will send 4 mcast rejoin messages at latest, which will make user confused. The same with notify_peers.count. Fix it by deleting team_notify_peers() and team_mcast_rejoin() in team_port_disable(). Reported-by: Liang Li Fixes: fc423ff00df3a ("team: add peer notification") Fixes: 492b200efdd20 ("team: add support for sending multicast rejoins") Signed-off-by: Hangbin Liu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/team/team.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index 817451a1efd6..bd455a6cc82c 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -989,8 +989,6 @@ static void team_port_disable(struct team *team, team->en_port_count--; team_queue_override_port_del(team, port); team_adjust_ops(team); - team_notify_peers(team); - team_mcast_rejoin(team); team_lower_state_changed(port); } -- GitLab From ccbffb5d7dc88b7e7eecf504d8fa2a271f10ee16 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Thu, 22 Nov 2018 07:34:41 -0500 Subject: [PATCH 0400/1286] net: amd: add missing of_node_put() [ Upstream commit c44c749d3b6fdfca39002e7e48e03fe9f9fe37a3 ] of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. This place doesn't do that, so fix it. Signed-off-by: Yangtao Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/amd/sunlance.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/amd/sunlance.c b/drivers/net/ethernet/amd/sunlance.c index 291ca5187f12..9845e07d40cd 100644 --- a/drivers/net/ethernet/amd/sunlance.c +++ b/drivers/net/ethernet/amd/sunlance.c @@ -1418,7 +1418,7 @@ static int sparc_lance_probe_one(struct platform_device *op, prop = of_get_property(nd, "tpe-link-test?", NULL); if (!prop) - goto no_link_test; + goto node_put; if (strcmp(prop, "true")) { printk(KERN_NOTICE "SunLance: warning: overriding option " @@ -1427,6 +1427,8 @@ static int sparc_lance_probe_one(struct platform_device *op, "to ecd@skynet.be\n"); auxio_set_lte(AUXIO_LTE_ON); } +node_put: + of_node_put(nd); no_link_test: lp->auto_select = 1; lp->tpe = 0; -- GitLab From 4515bbc4e284066d4e2f4a66eccf13813f6e7206 Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Wed, 15 Nov 2017 17:38:37 -0800 Subject: [PATCH 0401/1286] mm: don't warn about allocations which stall for too long [ Upstream commit 400e22499dd92613821374c8c6c88c7225359980 ] Commit 63f53dea0c98 ("mm: warn about allocations which stall for too long") was a great step for reducing possibility of silent hang up problem caused by memory allocation stalls. But this commit reverts it, for it is possible to trigger OOM lockup and/or soft lockups when many threads concurrently called warn_alloc() (in order to warn about memory allocation stalls) due to current implementation of printk(), and it is difficult to obtain useful information due to limitation of synchronous warning approach. Current printk() implementation flushes all pending logs using the context of a thread which called console_unlock(). printk() should be able to flush all pending logs eventually unless somebody continues appending to printk() buffer. Since warn_alloc() started appending to printk() buffer while waiting for oom_kill_process() to make forward progress when oom_kill_process() is processing pending logs, it became possible for warn_alloc() to force oom_kill_process() loop inside printk(). As a result, warn_alloc() significantly increased possibility of preventing oom_kill_process() from making forward progress. ---------- Pseudo code start ---------- Before warn_alloc() was introduced: retry: if (mutex_trylock(&oom_lock)) { while (atomic_read(&printk_pending_logs) > 0) { atomic_dec(&printk_pending_logs); print_one_log(); } // Send SIGKILL here. mutex_unlock(&oom_lock) } goto retry; After warn_alloc() was introduced: retry: if (mutex_trylock(&oom_lock)) { while (atomic_read(&printk_pending_logs) > 0) { atomic_dec(&printk_pending_logs); print_one_log(); } // Send SIGKILL here. mutex_unlock(&oom_lock) } else if (waited_for_10seconds()) { atomic_inc(&printk_pending_logs); } goto retry; ---------- Pseudo code end ---------- Although waited_for_10seconds() becomes true once per 10 seconds, unbounded number of threads can call waited_for_10seconds() at the same time. Also, since threads doing waited_for_10seconds() keep doing almost busy loop, the thread doing print_one_log() can use little CPU resource. Therefore, this situation can be simplified like ---------- Pseudo code start ---------- retry: if (mutex_trylock(&oom_lock)) { while (atomic_read(&printk_pending_logs) > 0) { atomic_dec(&printk_pending_logs); print_one_log(); } // Send SIGKILL here. mutex_unlock(&oom_lock) } else { atomic_inc(&printk_pending_logs); } goto retry; ---------- Pseudo code end ---------- when printk() is called faster than print_one_log() can process a log. One of possible mitigation would be to introduce a new lock in order to make sure that no other series of printk() (either oom_kill_process() or warn_alloc()) can append to printk() buffer when one series of printk() (either oom_kill_process() or warn_alloc()) is already in progress. Such serialization will also help obtaining kernel messages in readable form. ---------- Pseudo code start ---------- retry: if (mutex_trylock(&oom_lock)) { mutex_lock(&oom_printk_lock); while (atomic_read(&printk_pending_logs) > 0) { atomic_dec(&printk_pending_logs); print_one_log(); } // Send SIGKILL here. mutex_unlock(&oom_printk_lock); mutex_unlock(&oom_lock) } else { if (mutex_trylock(&oom_printk_lock)) { atomic_inc(&printk_pending_logs); mutex_unlock(&oom_printk_lock); } } goto retry; ---------- Pseudo code end ---------- But this commit does not go that direction, for we don't want to introduce a new lock dependency, and we unlikely be able to obtain useful information even if we serialized oom_kill_process() and warn_alloc(). Synchronous approach is prone to unexpected results (e.g. too late [1], too frequent [2], overlooked [3]). As far as I know, warn_alloc() never helped with providing information other than "something is going wrong". I want to consider asynchronous approach which can obtain information during stalls with possibly relevant threads (e.g. the owner of oom_lock and kswapd-like threads) and serve as a trigger for actions (e.g. turn on/off tracepoints, ask libvirt daemon to take a memory dump of stalling KVM guest for diagnostic purpose). This commit temporarily loses ability to report e.g. OOM lockup due to unable to invoke the OOM killer due to !__GFP_FS allocation request. But asynchronous approach will be able to detect such situation and emit warning. Thus, let's remove warn_alloc(). [1] https://bugzilla.kernel.org/show_bug.cgi?id=192981 [2] http://lkml.kernel.org/r/CAM_iQpWuPVGc2ky8M-9yukECtS+zKjiDasNymX7rMcBjBFyM_A@mail.gmail.com [3] commit db73ee0d46379922 ("mm, vmscan: do not loop on too_many_isolated for ever")) Link: http://lkml.kernel.org/r/1509017339-4802-1-git-send-email-penguin-kernel@I-love.SAKURA.ne.jp Signed-off-by: Tetsuo Handa Reported-by: Cong Wang Reported-by: yuwang.yuwang Reported-by: Johannes Weiner Acked-by: Michal Hocko Acked-by: Johannes Weiner Cc: Vlastimil Babka Cc: Mel Gorman Cc: Dave Hansen Cc: Sergey Senozhatsky Cc: Petr Mladek Cc: Steven Rostedt Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/page_alloc.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 2074f424dabf..6be91a1a00d9 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -3862,8 +3862,6 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int order, enum compact_result compact_result; int compaction_retries; int no_progress_loops; - unsigned long alloc_start = jiffies; - unsigned int stall_timeout = 10 * HZ; unsigned int cpuset_mems_cookie; int reserve_flags; @@ -3983,14 +3981,6 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int order, if (!can_direct_reclaim) goto nopage; - /* Make sure we know about allocations which stall for too long */ - if (time_after(jiffies, alloc_start + stall_timeout)) { - warn_alloc(gfp_mask & ~__GFP_NOWARN, ac->nodemask, - "page allocation stalls for %ums, order:%u", - jiffies_to_msecs(jiffies-alloc_start), order); - stall_timeout += 10 * HZ; - } - /* Avoid recursion of direct reclaim */ if (current->flags & PF_MEMALLOC) goto nopage; -- GitLab From d2afd22aff69bc448b1defc06fcd311479f336f5 Mon Sep 17 00:00:00 2001 From: Harry Pan Date: Thu, 29 Nov 2018 00:40:41 +0800 Subject: [PATCH 0402/1286] usb: quirk: add no-LPM quirk on SanDisk Ultra Flair device commit 2f2dde6ba89b1ef1fe23c1138131b315d9aa4019 upstream. Some lower volume SanDisk Ultra Flair in 16GB, which the VID:PID is in 0781:5591, will aggressively request LPM of U1/U2 during runtime, when using this thumb drive as the OS installation key we found the device will generate failure during U1 exit path making it dropped from the USB bus, this causes a corrupted installation in system at the end. i.e., [ 166.918296] hub 2-0:1.0: state 7 ports 7 chg 0000 evt 0004 [ 166.918327] usb usb2-port2: link state change [ 166.918337] usb usb2-port2: do warm reset [ 166.970039] usb usb2-port2: not warm reset yet, waiting 50ms [ 167.022040] usb usb2-port2: not warm reset yet, waiting 200ms [ 167.276043] usb usb2-port2: status 02c0, change 0041, 5.0 Gb/s [ 167.276050] usb 2-2: USB disconnect, device number 2 [ 167.276058] usb 2-2: unregistering device [ 167.276060] usb 2-2: unregistering interface 2-2:1.0 [ 167.276170] xhci_hcd 0000:00:15.0: shutdown urb ffffa3c7cc695cc0 ep1in-bulk [ 167.284055] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK [ 167.284064] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 00 33 04 90 00 01 00 00 ... Analyzed the USB trace in the link layer we realized it is because of the 6-ms timer of tRecoveryConfigurationTimeout which documented on the USB 3.2 Revision 1.0, the section 7.5.10.4.2 of "Exit from Recovery.Configuration"; device initiates U1 exit -> Recovery.Active -> Recovery.Configuration, then the host timer timeout makes the link transits to eSS.Inactive -> Rx.Detect follows by a Warm Reset. Interestingly, the other higher volume of SanDisk Ultra Flair sharing the same VID:PID, such as 64GB, would not request LPM during runtime, it sticks at U0 always, thus disabling LPM does not affect those thumb drives at all. The same odd occures in SanDisk Ultra Fit 16GB, VID:PID in 0781:5583. Signed-off-by: Harry Pan Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 808437c5ec49..cf378b1ed373 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -188,6 +188,10 @@ static const struct usb_device_id usb_quirk_list[] = { /* Midiman M-Audio Keystation 88es */ { USB_DEVICE(0x0763, 0x0192), .driver_info = USB_QUIRK_RESET_RESUME }, + /* SanDisk Ultra Fit and Ultra Flair */ + { USB_DEVICE(0x0781, 0x5583), .driver_info = USB_QUIRK_NO_LPM }, + { USB_DEVICE(0x0781, 0x5591), .driver_info = USB_QUIRK_NO_LPM }, + /* M-Systems Flash Disk Pioneers */ { USB_DEVICE(0x08ec, 0x1000), .driver_info = USB_QUIRK_RESET_RESUME }, -- GitLab From 810487aa9d483262044c41fc1973c7abd95e1d86 Mon Sep 17 00:00:00 2001 From: Alexander Theissen Date: Tue, 4 Dec 2018 23:43:35 +0100 Subject: [PATCH 0403/1286] usb: appledisplay: Add 27" Apple Cinema Display commit d7859905301880ad3e16272399d26900af3ac496 upstream. Add another Apple Cinema Display to the list of supported displays. Signed-off-by: Alexander Theissen Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/misc/appledisplay.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/misc/appledisplay.c b/drivers/usb/misc/appledisplay.c index 288fe3e69d52..03be7c75c5be 100644 --- a/drivers/usb/misc/appledisplay.c +++ b/drivers/usb/misc/appledisplay.c @@ -64,6 +64,7 @@ static const struct usb_device_id appledisplay_table[] = { { APPLEDISPLAY_DEVICE(0x921c) }, { APPLEDISPLAY_DEVICE(0x921d) }, { APPLEDISPLAY_DEVICE(0x9222) }, + { APPLEDISPLAY_DEVICE(0x9226) }, { APPLEDISPLAY_DEVICE(0x9236) }, /* Terminating entry */ -- GitLab From 7b6e85da8d94948201abb8d576d485892a6a878f Mon Sep 17 00:00:00 2001 From: Mathias Payer Date: Wed, 5 Dec 2018 21:19:59 +0100 Subject: [PATCH 0404/1286] USB: check usb_get_extra_descriptor for proper size commit 704620afc70cf47abb9d6a1a57f3825d2bca49cf upstream. When reading an extra descriptor, we need to properly check the minimum and maximum size allowed, to prevent from invalid data being sent by a device. Reported-by: Hui Peng Reported-by: Mathias Payer Co-developed-by: Linus Torvalds Signed-off-by: Hui Peng Signed-off-by: Mathias Payer Signed-off-by: Linus Torvalds Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hub.c | 2 +- drivers/usb/core/usb.c | 6 +++--- drivers/usb/host/hwa-hc.c | 2 +- include/linux/usb.h | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 638dc6f66d70..a073cb5be013 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -2231,7 +2231,7 @@ static int usb_enumerate_device_otg(struct usb_device *udev) /* descriptor may appear anywhere in config */ err = __usb_get_extra_descriptor(udev->rawdescriptors[0], le16_to_cpu(udev->config[0].desc.wTotalLength), - USB_DT_OTG, (void **) &desc); + USB_DT_OTG, (void **) &desc, sizeof(*desc)); if (err || !(desc->bmAttributes & USB_OTG_HNP)) return 0; diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index f8b50eaf6d1e..7a4e3da549fe 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -833,14 +833,14 @@ EXPORT_SYMBOL_GPL(usb_get_current_frame_number); */ int __usb_get_extra_descriptor(char *buffer, unsigned size, - unsigned char type, void **ptr) + unsigned char type, void **ptr, size_t minsize) { struct usb_descriptor_header *header; while (size >= sizeof(struct usb_descriptor_header)) { header = (struct usb_descriptor_header *)buffer; - if (header->bLength < 2) { + if (header->bLength < 2 || header->bLength > size) { printk(KERN_ERR "%s: bogus descriptor, type %d length %d\n", usbcore_name, @@ -849,7 +849,7 @@ int __usb_get_extra_descriptor(char *buffer, unsigned size, return -1; } - if (header->bDescriptorType == type) { + if (header->bDescriptorType == type && header->bLength >= minsize) { *ptr = header; return 0; } diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c index da3b18038d23..216069c396a0 100644 --- a/drivers/usb/host/hwa-hc.c +++ b/drivers/usb/host/hwa-hc.c @@ -654,7 +654,7 @@ static int hwahc_security_create(struct hwahc *hwahc) top = itr + itr_size; result = __usb_get_extra_descriptor(usb_dev->rawdescriptors[index], le16_to_cpu(usb_dev->actconfig->desc.wTotalLength), - USB_DT_SECURITY, (void **) &secd); + USB_DT_SECURITY, (void **) &secd, sizeof(*secd)); if (result == -1) { dev_warn(dev, "BUG? WUSB host has no security descriptors\n"); return 0; diff --git a/include/linux/usb.h b/include/linux/usb.h index 4192a1755ccb..8c7ba40cf021 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -407,11 +407,11 @@ struct usb_host_bos { }; int __usb_get_extra_descriptor(char *buffer, unsigned size, - unsigned char type, void **ptr); + unsigned char type, void **ptr, size_t min); #define usb_get_extra_descriptor(ifpoint, type, ptr) \ __usb_get_extra_descriptor((ifpoint)->extra, \ (ifpoint)->extralen, \ - type, (void **)ptr) + type, (void **)ptr, sizeof(**(ptr))) /* ----------------------------------------------------------------------- */ -- GitLab From 19f74e45746253cafb8cb1e773041e7cadbac622 Mon Sep 17 00:00:00 2001 From: Hui Peng Date: Mon, 3 Dec 2018 16:09:34 +0100 Subject: [PATCH 0405/1286] ALSA: usb-audio: Fix UAF decrement if card has no live interfaces in card.c commit 5f8cf712582617d523120df67d392059eaf2fc4b upstream. If a USB sound card reports 0 interfaces, an error condition is triggered and the function usb_audio_probe errors out. In the error path, there was a use-after-free vulnerability where the memory object of the card was first freed, followed by a decrement of the number of active chips. Moving the decrement above the atomic_dec fixes the UAF. [ The original problem was introduced in 3.1 kernel, while it was developed in a different form. The Fixes tag below indicates the original commit but it doesn't mean that the patch is applicable cleanly. -- tiwai ] Fixes: 362e4e49abe5 ("ALSA: usb-audio - clear chip->probing on error exit") Reported-by: Hui Peng Reported-by: Mathias Payer Signed-off-by: Hui Peng Signed-off-by: Mathias Payer Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/usb/card.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sound/usb/card.c b/sound/usb/card.c index 23d1d23aefec..4169c71f8a32 100644 --- a/sound/usb/card.c +++ b/sound/usb/card.c @@ -644,9 +644,12 @@ static int usb_audio_probe(struct usb_interface *intf, __error: if (chip) { + /* chip->active is inside the chip->card object, + * decrement before memory is possibly returned. + */ + atomic_dec(&chip->active); if (!chip->num_interfaces) snd_card_free(chip->card); - atomic_dec(&chip->active); } mutex_unlock(®ister_mutex); return err; -- GitLab From 0618c71c73caa194f4d9ac2d42551ad6df047103 Mon Sep 17 00:00:00 2001 From: Kai-Heng Feng Date: Thu, 29 Nov 2018 08:57:37 +0000 Subject: [PATCH 0406/1286] ALSA: hda: Add support for AMD Stoney Ridge commit 3deef52ce10514ccdebba8e8ab85f9cebd0eb3f7 upstream. It's similar to other AMD audio devices, it also supports D3, which can save some power drain. Signed-off-by: Kai-Heng Feng Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/hda_intel.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 4e38905bc47d..d8e80b6f5a6b 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -2513,6 +2513,10 @@ static const struct pci_device_id azx_ids[] = { /* AMD Hudson */ { PCI_DEVICE(0x1022, 0x780d), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, + /* AMD Stoney */ + { PCI_DEVICE(0x1022, 0x157a), + .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | + AZX_DCAPS_PM_RUNTIME }, /* AMD Raven */ { PCI_DEVICE(0x1022, 0x15e3), .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | -- GitLab From 108ab9eafbbeffa17431cb1acd7a930d23bfd197 Mon Sep 17 00:00:00 2001 From: Chanho Min Date: Mon, 26 Nov 2018 14:36:37 +0900 Subject: [PATCH 0407/1286] ALSA: pcm: Fix starvation on down_write_nonblock() commit b888a5f713e4d17faaaff24316585a4eb07f35b7 upstream. Commit 67ec1072b053 ("ALSA: pcm: Fix rwsem deadlock for non-atomic PCM stream") fixes deadlock for non-atomic PCM stream. But, This patch causes antother stuck. If writer is RT thread and reader is a normal thread, the reader thread will be difficult to get scheduled. It may not give chance to release readlocks and writer gets stuck for a long time if they are pinned to single cpu. The deadlock described in the previous commit is because the linux rwsem queues like a FIFO. So, we might need non-FIFO writelock, not non-block one. My suggestion is that the writer gives reader a chance to be scheduled by using the minimum msleep() instaed of spinning without blocking by writer. Also, The *_nonblock may be changed to *_nonfifo appropriately to this concept. In terms of performance, when trylock is failed, this minimum periodic msleep will have the same performance as the tick-based schedule()/wake_up_q(). [ Although this has a fairly high performance penalty, the relevant code path became already rare due to the previous commit ("ALSA: pcm: Call snd_pcm_unlink() conditionally at closing"). That is, now this unconditional msleep appears only when using linked streams, and this must be a rare case. So we accept this as a quick workaround until finding a more suitable one -- tiwai ] Fixes: 67ec1072b053 ("ALSA: pcm: Fix rwsem deadlock for non-atomic PCM stream") Suggested-by: Wonmin Jung Signed-off-by: Chanho Min Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_native.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index ab3bf36786b6..30784bd1c5af 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "pcm_local.h" @@ -91,12 +92,12 @@ static DECLARE_RWSEM(snd_pcm_link_rwsem); * and this may lead to a deadlock when the code path takes read sem * twice (e.g. one in snd_pcm_action_nonatomic() and another in * snd_pcm_stream_lock()). As a (suboptimal) workaround, let writer to - * spin until it gets the lock. + * sleep until all the readers are completed without blocking by writer. */ -static inline void down_write_nonblock(struct rw_semaphore *lock) +static inline void down_write_nonfifo(struct rw_semaphore *lock) { while (!down_write_trylock(lock)) - cond_resched(); + msleep(1); } /** @@ -1935,7 +1936,7 @@ static int snd_pcm_link(struct snd_pcm_substream *substream, int fd) res = -ENOMEM; goto _nolock; } - down_write_nonblock(&snd_pcm_link_rwsem); + down_write_nonfifo(&snd_pcm_link_rwsem); write_lock_irq(&snd_pcm_link_rwlock); if (substream->runtime->status->state == SNDRV_PCM_STATE_OPEN || substream->runtime->status->state != substream1->runtime->status->state || @@ -1982,7 +1983,7 @@ static int snd_pcm_unlink(struct snd_pcm_substream *substream) struct snd_pcm_substream *s; int res = 0; - down_write_nonblock(&snd_pcm_link_rwsem); + down_write_nonfifo(&snd_pcm_link_rwsem); write_lock_irq(&snd_pcm_link_rwlock); if (!snd_pcm_stream_linked(substream)) { res = -EALREADY; -- GitLab From cabb9539dc1741b2a5bf6077a4aac8156f07a1c8 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 29 Nov 2018 08:02:49 +0100 Subject: [PATCH 0408/1286] ALSA: pcm: Call snd_pcm_unlink() conditionally at closing commit b51abed8355e5556886623b2772fa6b7598d2282 upstream. Currently the PCM core calls snd_pcm_unlink() always unconditionally at closing a stream. However, since snd_pcm_unlink() invokes the global rwsem down, the lock can be easily contended. More badly, when a thread runs in a high priority RT-FIFO, it may stall at spinning. Basically the call of snd_pcm_unlink() is required only for the linked streams that are already rare occasion. For normal use cases, this code path is fairly superfluous. As an optimization (and also as a workaround for the RT problem above in normal situations without linked streams), this patch adds a check before calling snd_pcm_unlink() and calls it only when needed. Reported-by: Chanho Min Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_native.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 30784bd1c5af..966ac384c3f4 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -2338,7 +2338,8 @@ int snd_pcm_hw_constraints_complete(struct snd_pcm_substream *substream) static void pcm_release_private(struct snd_pcm_substream *substream) { - snd_pcm_unlink(substream); + if (snd_pcm_stream_linked(substream)) + snd_pcm_unlink(substream); } void snd_pcm_release_substream(struct snd_pcm_substream *substream) -- GitLab From 7852f54f08a0a7222235561fc57ccd83f1c358d4 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 29 Nov 2018 12:05:19 +0100 Subject: [PATCH 0409/1286] ALSA: pcm: Fix interval evaluation with openmin/max commit 5363857b916c1f48027e9b96ee8be8376bf20811 upstream. As addressed in alsa-lib (commit b420056604f0), we need to fix the case where the evaluation of PCM interval "(x x+1]" leading to -EINVAL. After applying rules, such an interval may be translated as "(x x+1)". Fixes: ff2d6acdf6f1 ("ALSA: pcm: Fix snd_interval_refine first/last with open min/max") Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- include/sound/pcm_params.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/sound/pcm_params.h b/include/sound/pcm_params.h index c704357775fc..2af7bb3ee57d 100644 --- a/include/sound/pcm_params.h +++ b/include/sound/pcm_params.h @@ -247,11 +247,13 @@ static inline int snd_interval_empty(const struct snd_interval *i) static inline int snd_interval_single(const struct snd_interval *i) { return (i->min == i->max || - (i->min + 1 == i->max && i->openmax)); + (i->min + 1 == i->max && (i->openmin || i->openmax))); } static inline int snd_interval_value(const struct snd_interval *i) { + if (i->openmin && !i->openmax) + return i->max; return i->min; } -- GitLab From 01a02e66228b69b497136168716cb1ba2b5ebd73 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 3 Dec 2018 10:44:15 +0100 Subject: [PATCH 0410/1286] ALSA: hda/realtek - Fix speaker output regression on Thinkpad T570 commit 54947cd64c1b8290f64bb2958e343c07270e3a58 upstream. We've got a regression report for some Thinkpad models (at least T570s) which shows the too low speaker output volume. The bisection leaded to the commit 61fcf8ece9b6 ("ALSA: hda/realtek - Enable Thinkpad Dock device for ALC298 platform"), and it's basically adding the two pin configurations for the dock, and looks harmless. The real culprit seems, though, that the DAC assignment for the speaker pin is implicitly assumed on these devices, i.e. pin NID 0x14 to be coupled with DAC NID 0x03. When more pins are configured by the commit above, the auto-parser changes the DAC assignment, and this resulted in the regression. As a workaround, just provide the fixed pin / DAC mapping table for this Thinkpad fixup function. It's no generic solution, but the problem itself is pretty much device-specific, so must be good enough. Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1554304 Fixes: 61fcf8ece9b6 ("ALSA: hda/realtek - Enable Thinkpad Dock device for ALC298 platform") Cc: Reported-and-tested-by: Jeremy Cline Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 66b0a124beae..f6136f041a81 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -4863,9 +4863,18 @@ static void alc_fixup_tpt470_dock(struct hda_codec *codec, { 0x19, 0x21a11010 }, /* dock mic */ { } }; + /* Assure the speaker pin to be coupled with DAC NID 0x03; otherwise + * the speaker output becomes too low by some reason on Thinkpads with + * ALC298 codec + */ + static hda_nid_t preferred_pairs[] = { + 0x14, 0x03, 0x17, 0x02, 0x21, 0x02, + 0 + }; struct alc_spec *spec = codec->spec; if (action == HDA_FIXUP_ACT_PRE_PROBE) { + spec->gen.preferred_dacs = preferred_pairs; spec->parse_flags = HDA_PINCFG_NO_HP_FIXUP; snd_hda_apply_pincfgs(codec, pincfgs); } else if (action == HDA_FIXUP_ACT_INIT) { -- GitLab From 73f6d525be2cded3bd3dd3bcfcfffec548a79e94 Mon Sep 17 00:00:00 2001 From: Halil Pasic Date: Wed, 26 Sep 2018 18:48:29 +0200 Subject: [PATCH 0411/1286] virtio/s390: avoid race on vcdev->config commit 2448a299ec416a80f699940a86f4a6d9a4f643b1 upstream. Currently we have a race on vcdev->config in virtio_ccw_get_config() and in virtio_ccw_set_config(). This normally does not cause problems, as these are usually infrequent operations. However, for some devices writing to/reading from the config space can be triggered through sysfs attributes. For these, userspace can force the race by increasing the frequency. Signed-off-by: Halil Pasic Cc: stable@vger.kernel.org Message-Id: <20180925121309.58524-2-pasic@linux.ibm.com> Signed-off-by: Cornelia Huck Signed-off-by: Michael S. Tsirkin Signed-off-by: Greg Kroah-Hartman --- drivers/s390/virtio/virtio_ccw.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c index b18fe2014cf2..3a1b553e7653 100644 --- a/drivers/s390/virtio/virtio_ccw.c +++ b/drivers/s390/virtio/virtio_ccw.c @@ -831,6 +831,7 @@ static void virtio_ccw_get_config(struct virtio_device *vdev, int ret; struct ccw1 *ccw; void *config_area; + unsigned long flags; ccw = kzalloc(sizeof(*ccw), GFP_DMA | GFP_KERNEL); if (!ccw) @@ -849,11 +850,13 @@ static void virtio_ccw_get_config(struct virtio_device *vdev, if (ret) goto out_free; + spin_lock_irqsave(&vcdev->lock, flags); memcpy(vcdev->config, config_area, offset + len); - if (buf) - memcpy(buf, &vcdev->config[offset], len); if (vcdev->config_ready < offset + len) vcdev->config_ready = offset + len; + spin_unlock_irqrestore(&vcdev->lock, flags); + if (buf) + memcpy(buf, config_area + offset, len); out_free: kfree(config_area); @@ -867,6 +870,7 @@ static void virtio_ccw_set_config(struct virtio_device *vdev, struct virtio_ccw_device *vcdev = to_vc_device(vdev); struct ccw1 *ccw; void *config_area; + unsigned long flags; ccw = kzalloc(sizeof(*ccw), GFP_DMA | GFP_KERNEL); if (!ccw) @@ -879,9 +883,11 @@ static void virtio_ccw_set_config(struct virtio_device *vdev, /* Make sure we don't overwrite fields. */ if (vcdev->config_ready < offset) virtio_ccw_get_config(vdev, 0, NULL, offset); + spin_lock_irqsave(&vcdev->lock, flags); memcpy(&vcdev->config[offset], buf, len); /* Write the config area to the host. */ memcpy(config_area, vcdev->config, sizeof(vcdev->config)); + spin_unlock_irqrestore(&vcdev->lock, flags); ccw->cmd_code = CCW_CMD_WRITE_CONF; ccw->flags = 0; ccw->count = offset + len; -- GitLab From 52b993b4c4c2a88b62601b0cc0662a564e1d65dc Mon Sep 17 00:00:00 2001 From: Halil Pasic Date: Wed, 26 Sep 2018 18:48:30 +0200 Subject: [PATCH 0412/1286] virtio/s390: fix race in ccw_io_helper() commit 78b1a52e05c9db11d293342e8d6d8a230a04b4e7 upstream. While ccw_io_helper() seems like intended to be exclusive in a sense that it is supposed to facilitate I/O for at most one thread at any given time, there is actually nothing ensuring that threads won't pile up at vcdev->wait_q. If they do, all threads get woken up and see the status that belongs to some other request than their own. This can lead to bugs. For an example see: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1788432 This race normally does not cause any problems. The operations provided by struct virtio_config_ops are usually invoked in a well defined sequence, normally don't fail, and are normally used quite infrequent too. Yet, if some of the these operations are directly triggered via sysfs attributes, like in the case described by the referenced bug, userspace is given an opportunity to force races by increasing the frequency of the given operations. Let us fix the problem by ensuring, that for each device, we finish processing the previous request before starting with a new one. Signed-off-by: Halil Pasic Reported-by: Colin Ian King Cc: stable@vger.kernel.org Message-Id: <20180925121309.58524-3-pasic@linux.ibm.com> Signed-off-by: Cornelia Huck Signed-off-by: Michael S. Tsirkin Signed-off-by: Greg Kroah-Hartman --- drivers/s390/virtio/virtio_ccw.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c index 3a1b553e7653..0847d05e138b 100644 --- a/drivers/s390/virtio/virtio_ccw.c +++ b/drivers/s390/virtio/virtio_ccw.c @@ -59,6 +59,7 @@ struct virtio_ccw_device { unsigned int revision; /* Transport revision */ wait_queue_head_t wait_q; spinlock_t lock; + struct mutex io_lock; /* Serializes I/O requests */ struct list_head virtqueues; unsigned long indicators; unsigned long indicators2; @@ -299,6 +300,7 @@ static int ccw_io_helper(struct virtio_ccw_device *vcdev, unsigned long flags; int flag = intparm & VIRTIO_CCW_INTPARM_MASK; + mutex_lock(&vcdev->io_lock); do { spin_lock_irqsave(get_ccwdev_lock(vcdev->cdev), flags); ret = ccw_device_start(vcdev->cdev, ccw, intparm, 0, 0); @@ -311,7 +313,9 @@ static int ccw_io_helper(struct virtio_ccw_device *vcdev, cpu_relax(); } while (ret == -EBUSY); wait_event(vcdev->wait_q, doing_io(vcdev, flag) == 0); - return ret ? ret : vcdev->err; + ret = ret ? ret : vcdev->err; + mutex_unlock(&vcdev->io_lock); + return ret; } static void virtio_ccw_drop_indicator(struct virtio_ccw_device *vcdev, @@ -1256,6 +1260,7 @@ static int virtio_ccw_online(struct ccw_device *cdev) init_waitqueue_head(&vcdev->wait_q); INIT_LIST_HEAD(&vcdev->virtqueues); spin_lock_init(&vcdev->lock); + mutex_init(&vcdev->io_lock); spin_lock_irqsave(get_ccwdev_lock(cdev), flags); dev_set_drvdata(&cdev->dev, vcdev); -- GitLab From f15c072d6576c5e2b693c22e39ccc9103c952078 Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Mon, 5 Nov 2018 10:35:47 +0000 Subject: [PATCH 0413/1286] vhost/vsock: fix use-after-free in network stack callers commit 834e772c8db0c6a275d75315d90aba4ebbb1e249 upstream. If the network stack calls .send_pkt()/.cancel_pkt() during .release(), a struct vhost_vsock use-after-free is possible. This occurs because .release() does not wait for other CPUs to stop using struct vhost_vsock. Switch to an RCU-enabled hashtable (indexed by guest CID) so that .release() can wait for other CPUs by calling synchronize_rcu(). This also eliminates vhost_vsock_lock acquisition in the data path so it could have a positive effect on performance. This is CVE-2018-14625 "kernel: use-after-free Read in vhost_transport_send_pkt". Cc: stable@vger.kernel.org Reported-and-tested-by: syzbot+bd391451452fb0b93039@syzkaller.appspotmail.com Reported-by: syzbot+e3e074963495f92a89ed@syzkaller.appspotmail.com Reported-by: syzbot+d5a0a170c5069658b141@syzkaller.appspotmail.com Signed-off-by: Stefan Hajnoczi Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang Signed-off-by: Greg Kroah-Hartman --- drivers/vhost/vsock.c | 57 +++++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c index c9de9c41aa97..b044a0800805 100644 --- a/drivers/vhost/vsock.c +++ b/drivers/vhost/vsock.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "vhost.h" @@ -27,14 +28,14 @@ enum { /* Used to track all the vhost_vsock instances on the system. */ static DEFINE_SPINLOCK(vhost_vsock_lock); -static LIST_HEAD(vhost_vsock_list); +static DEFINE_READ_MOSTLY_HASHTABLE(vhost_vsock_hash, 8); struct vhost_vsock { struct vhost_dev dev; struct vhost_virtqueue vqs[2]; - /* Link to global vhost_vsock_list, protected by vhost_vsock_lock */ - struct list_head list; + /* Link to global vhost_vsock_hash, writes use vhost_vsock_lock */ + struct hlist_node hash; struct vhost_work send_pkt_work; spinlock_t send_pkt_list_lock; @@ -50,11 +51,14 @@ static u32 vhost_transport_get_local_cid(void) return VHOST_VSOCK_DEFAULT_HOST_CID; } -static struct vhost_vsock *__vhost_vsock_get(u32 guest_cid) +/* Callers that dereference the return value must hold vhost_vsock_lock or the + * RCU read lock. + */ +static struct vhost_vsock *vhost_vsock_get(u32 guest_cid) { struct vhost_vsock *vsock; - list_for_each_entry(vsock, &vhost_vsock_list, list) { + hash_for_each_possible_rcu(vhost_vsock_hash, vsock, hash, guest_cid) { u32 other_cid = vsock->guest_cid; /* Skip instances that have no CID yet */ @@ -69,17 +73,6 @@ static struct vhost_vsock *__vhost_vsock_get(u32 guest_cid) return NULL; } -static struct vhost_vsock *vhost_vsock_get(u32 guest_cid) -{ - struct vhost_vsock *vsock; - - spin_lock_bh(&vhost_vsock_lock); - vsock = __vhost_vsock_get(guest_cid); - spin_unlock_bh(&vhost_vsock_lock); - - return vsock; -} - static void vhost_transport_do_send_pkt(struct vhost_vsock *vsock, struct vhost_virtqueue *vq) @@ -210,9 +203,12 @@ vhost_transport_send_pkt(struct virtio_vsock_pkt *pkt) struct vhost_vsock *vsock; int len = pkt->len; + rcu_read_lock(); + /* Find the vhost_vsock according to guest context id */ vsock = vhost_vsock_get(le64_to_cpu(pkt->hdr.dst_cid)); if (!vsock) { + rcu_read_unlock(); virtio_transport_free_pkt(pkt); return -ENODEV; } @@ -225,6 +221,8 @@ vhost_transport_send_pkt(struct virtio_vsock_pkt *pkt) spin_unlock_bh(&vsock->send_pkt_list_lock); vhost_work_queue(&vsock->dev, &vsock->send_pkt_work); + + rcu_read_unlock(); return len; } @@ -234,12 +232,15 @@ vhost_transport_cancel_pkt(struct vsock_sock *vsk) struct vhost_vsock *vsock; struct virtio_vsock_pkt *pkt, *n; int cnt = 0; + int ret = -ENODEV; LIST_HEAD(freeme); + rcu_read_lock(); + /* Find the vhost_vsock according to guest context id */ vsock = vhost_vsock_get(vsk->remote_addr.svm_cid); if (!vsock) - return -ENODEV; + goto out; spin_lock_bh(&vsock->send_pkt_list_lock); list_for_each_entry_safe(pkt, n, &vsock->send_pkt_list, list) { @@ -265,7 +266,10 @@ vhost_transport_cancel_pkt(struct vsock_sock *vsk) vhost_poll_queue(&tx_vq->poll); } - return 0; + ret = 0; +out: + rcu_read_unlock(); + return ret; } static struct virtio_vsock_pkt * @@ -531,10 +535,6 @@ static int vhost_vsock_dev_open(struct inode *inode, struct file *file) spin_lock_init(&vsock->send_pkt_list_lock); INIT_LIST_HEAD(&vsock->send_pkt_list); vhost_work_init(&vsock->send_pkt_work, vhost_transport_send_pkt_work); - - spin_lock_bh(&vhost_vsock_lock); - list_add_tail(&vsock->list, &vhost_vsock_list); - spin_unlock_bh(&vhost_vsock_lock); return 0; out: @@ -575,9 +575,13 @@ static int vhost_vsock_dev_release(struct inode *inode, struct file *file) struct vhost_vsock *vsock = file->private_data; spin_lock_bh(&vhost_vsock_lock); - list_del(&vsock->list); + if (vsock->guest_cid) + hash_del_rcu(&vsock->hash); spin_unlock_bh(&vhost_vsock_lock); + /* Wait for other CPUs to finish using vsock */ + synchronize_rcu(); + /* Iterating over all connections for all CIDs to find orphans is * inefficient. Room for improvement here. */ vsock_for_each_connected_socket(vhost_vsock_reset_orphans); @@ -618,12 +622,17 @@ static int vhost_vsock_set_cid(struct vhost_vsock *vsock, u64 guest_cid) /* Refuse if CID is already in use */ spin_lock_bh(&vhost_vsock_lock); - other = __vhost_vsock_get(guest_cid); + other = vhost_vsock_get(guest_cid); if (other && other != vsock) { spin_unlock_bh(&vhost_vsock_lock); return -EADDRINUSE; } + + if (vsock->guest_cid) + hash_del_rcu(&vsock->hash); + vsock->guest_cid = guest_cid; + hash_add_rcu(vhost_vsock_hash, &vsock->hash, guest_cid); spin_unlock_bh(&vhost_vsock_lock); return 0; -- GitLab From e3dccb527cfc97c4027824b6104635714ae14f47 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Fri, 30 Nov 2018 15:39:57 -0500 Subject: [PATCH 0414/1286] SUNRPC: Fix leak of krb5p encode pages commit 8dae5398ab1ac107b1517e8195ed043d5f422bd0 upstream. call_encode can be invoked more than once per RPC call. Ensure that each call to gss_wrap_req_priv does not overwrite pointers to previously allocated memory. Signed-off-by: Chuck Lever Cc: stable@kernel.org Signed-off-by: Trond Myklebust Signed-off-by: Greg Kroah-Hartman --- net/sunrpc/auth_gss/auth_gss.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/sunrpc/auth_gss/auth_gss.c b/net/sunrpc/auth_gss/auth_gss.c index 9463af4b32e8..1281b967dbf9 100644 --- a/net/sunrpc/auth_gss/auth_gss.c +++ b/net/sunrpc/auth_gss/auth_gss.c @@ -1736,6 +1736,7 @@ priv_release_snd_buf(struct rpc_rqst *rqstp) for (i=0; i < rqstp->rq_enc_pages_num; i++) __free_page(rqstp->rq_enc_pages[i]); kfree(rqstp->rq_enc_pages); + rqstp->rq_release_snd_buf = NULL; } static int @@ -1744,6 +1745,9 @@ alloc_enc_pages(struct rpc_rqst *rqstp) struct xdr_buf *snd_buf = &rqstp->rq_snd_buf; int first, last, i; + if (rqstp->rq_release_snd_buf) + rqstp->rq_release_snd_buf(rqstp); + if (snd_buf->page_len == 0) { rqstp->rq_enc_pages_num = 0; return 0; -- GitLab From bc3d506a116f1a00dba4a380ff511007c71e4db9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 5 Dec 2018 18:33:59 +0200 Subject: [PATCH 0415/1286] dmaengine: dw: Fix FIFO size for Intel Merrifield commit ffe843b18211301ad25893eba09f402c19d12304 upstream. Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller, i.e. 512 bytes instead of 1024. Fix this by partitioning it as 64 bytes per channel. Note, in the future we might switch to 'fifo-size' property instead of hard coded value. Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware") Signed-off-by: Andy Shevchenko Cc: stable@vger.kernel.org Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/dw/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index f43e6dafe446..0f389e008ce6 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1064,12 +1064,12 @@ static void dwc_issue_pending(struct dma_chan *chan) /* * Program FIFO size of channels. * - * By default full FIFO (1024 bytes) is assigned to channel 0. Here we + * By default full FIFO (512 bytes) is assigned to channel 0. Here we * slice FIFO on equal parts between channels. */ static void idma32_fifo_partition(struct dw_dma *dw) { - u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) | + u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) | IDMA32C_FP_UPDATE; u64 fifo_partition = 0; @@ -1082,7 +1082,7 @@ static void idma32_fifo_partition(struct dw_dma *dw) /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */ fifo_partition |= value << 32; - /* Program FIFO Partition registers - 128 bytes for each channel */ + /* Program FIFO Partition registers - 64 bytes per channel */ idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); } -- GitLab From e47a6e68c3bbfebb6d6f336d92884df37b722e4b Mon Sep 17 00:00:00 2001 From: Bin Liu Date: Mon, 12 Nov 2018 09:43:22 -0600 Subject: [PATCH 0416/1286] dmaengine: cppi41: delete channel from pending list when stop channel commit 59861547ec9a9736e7882f6fb0c096a720ff811a upstream. The driver defines three states for a cppi channel. - idle: .chan_busy == 0 && not in .pending list - pending: .chan_busy == 0 && in .pending list - busy: .chan_busy == 1 && not in .pending list There are cases in which the cppi channel could be in the pending state when cppi41_dma_issue_pending() is called after cppi41_runtime_suspend() is called. cppi41_stop_chan() has a bug for these cases to set channels to idle state. It only checks the .chan_busy flag, but not the .pending list, then later when cppi41_runtime_resume() is called the channels in .pending list will be transitioned to busy state. Removing channels from the .pending list solves the problem. Fixes: 975faaeb9985 ("dma: cppi41: start tear down only if channel is busy") Cc: stable@vger.kernel.org # v3.15+ Signed-off-by: Bin Liu Reviewed-by: Peter Ujfalusi Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/cppi41.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c index f7e965f63274..ddd4a3932127 100644 --- a/drivers/dma/cppi41.c +++ b/drivers/dma/cppi41.c @@ -723,8 +723,22 @@ static int cppi41_stop_chan(struct dma_chan *chan) desc_phys = lower_32_bits(c->desc_phys); desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc); - if (!cdd->chan_busy[desc_num]) + if (!cdd->chan_busy[desc_num]) { + struct cppi41_channel *cc, *_ct; + + /* + * channels might still be in the pendling list if + * cppi41_dma_issue_pending() is called after + * cppi41_runtime_suspend() is called + */ + list_for_each_entry_safe(cc, _ct, &cdd->pending, node) { + if (cc != c) + continue; + list_del(&cc->node); + break; + } return 0; + } ret = cppi41_tear_down_chan(c); if (ret) -- GitLab From f9e0bc710347fadad55910846ee36f0681d0dca8 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 30 Oct 2018 22:12:56 +0100 Subject: [PATCH 0417/1286] ARM: 8806/1: kprobes: Fix false positive with FORTIFY_SOURCE commit e46daee53bb50bde38805f1823a182979724c229 upstream. The arm compiler internally interprets an inline assembly label as an unsigned long value, not a pointer. As a result, under CONFIG_FORTIFY_SOURCE, the address of a label has a size of 4 bytes, which was tripping the runtime checks. Instead, we can just cast the label (as done with the size calculations earlier). Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1639397 Reported-by: William Cohen Fixes: 6974f0c4555e ("include/linux/string.h: add the option of fortified string.h functions") Cc: stable@vger.kernel.org Acked-by: Laura Abbott Acked-by: Masami Hiramatsu Tested-by: William Cohen Signed-off-by: Kees Cook Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman --- arch/arm/probes/kprobes/opt-arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c index b2aa9b32bff2..2c118a6ab358 100644 --- a/arch/arm/probes/kprobes/opt-arm.c +++ b/arch/arm/probes/kprobes/opt-arm.c @@ -247,7 +247,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *or } /* Copy arch-dep-instance from template. */ - memcpy(code, &optprobe_template_entry, + memcpy(code, (unsigned char *)optprobe_template_entry, TMPL_END_IDX * sizeof(kprobe_opcode_t)); /* Adjust buffer according to instruction. */ -- GitLab From 3ff0131284e94ddac80520fa549d55a4294776cb Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 5 Dec 2018 14:22:38 +0200 Subject: [PATCH 0418/1286] xhci: workaround CSS timeout on AMD SNPS 3.0 xHC commit a7d57abcc8a5bdeb53bbf8e87558e8e0a2c2a29d upstream. Occasionally AMD SNPS 3.0 xHC does not respond to CSS when set, also it does not flag anything on SRE and HCE to point the internal xHC errors on USBSTS register. This stalls the entire system wide suspend and there is no point in stalling just because of xHC CSS is not responding. To work around this problem, if the xHC does not flag anything on SRE and HCE, we can skip the CSS timeout and allow the system to continue the suspend. Once the system resume happens we can internally reset the controller using XHCI_RESET_ON_RESUME quirk Signed-off-by: Shyam Sundar S K Signed-off-by: Sandeep Singh cc: Nehal Shah Cc: Tested-by: Kai-Heng Feng Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-pci.c | 4 ++++ drivers/usb/host/xhci.c | 26 ++++++++++++++++++++++---- drivers/usb/host/xhci.h | 3 +++ 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 4b07b6859b4c..0fbc549cc55c 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -144,6 +144,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) pdev->device == 0x43bb)) xhci->quirks |= XHCI_SUSPEND_DELAY; + if (pdev->vendor == PCI_VENDOR_ID_AMD && + (pdev->device == 0x15e0 || pdev->device == 0x15e1)) + xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; + if (pdev->vendor == PCI_VENDOR_ID_AMD) xhci->quirks |= XHCI_TRUST_TX_LENGTH; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index faf048682194..155b36265f7a 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -918,6 +918,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) unsigned int delay = XHCI_MAX_HALT_USEC; struct usb_hcd *hcd = xhci_to_hcd(xhci); u32 command; + u32 res; if (!hcd->state) return 0; @@ -969,11 +970,28 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) command = readl(&xhci->op_regs->command); command |= CMD_CSS; writel(command, &xhci->op_regs->command); + xhci->broken_suspend = 0; if (xhci_handshake(&xhci->op_regs->status, STS_SAVE, 0, 10 * 1000)) { - xhci_warn(xhci, "WARN: xHC save state timeout\n"); - spin_unlock_irq(&xhci->lock); - return -ETIMEDOUT; + /* + * AMD SNPS xHC 3.0 occasionally does not clear the + * SSS bit of USBSTS and when driver tries to poll + * to see if the xHC clears BIT(8) which never happens + * and driver assumes that controller is not responding + * and times out. To workaround this, its good to check + * if SRE and HCE bits are not set (as per xhci + * Section 5.4.2) and bypass the timeout. + */ + res = readl(&xhci->op_regs->status); + if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) && + (((res & STS_SRE) == 0) && + ((res & STS_HCE) == 0))) { + xhci->broken_suspend = 1; + } else { + xhci_warn(xhci, "WARN: xHC save state timeout\n"); + spin_unlock_irq(&xhci->lock); + return -ETIMEDOUT; + } } spin_unlock_irq(&xhci->lock); @@ -1026,7 +1044,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); spin_lock_irq(&xhci->lock); - if (xhci->quirks & XHCI_RESET_ON_RESUME) + if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend) hibernated = true; if (!hibernated) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 74ba20556020..1ccff2d9dee9 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1839,6 +1839,7 @@ struct xhci_hcd { #define XHCI_SUSPEND_DELAY BIT_ULL(30) #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) +#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) unsigned int num_active_eps; unsigned int limit_active_eps; @@ -1870,6 +1871,8 @@ struct xhci_hcd { /* platform-specific data -- must come last */ unsigned long priv[0] __aligned(sizeof(s64)); + /* Broken Suspend flag for SNPS Suspend resume issue */ + u8 broken_suspend; }; /* Platform specific overrides to generic XHCI hc_driver ops */ -- GitLab From cacfa255bee4fd7137939411b05a0527475a19ec Mon Sep 17 00:00:00 2001 From: Mathias Nyman Date: Wed, 5 Dec 2018 14:22:39 +0200 Subject: [PATCH 0419/1286] xhci: Prevent U1/U2 link pm states if exit latency is too long commit 0472bf06c6fd33c1a18aaead4c8f91e5a03d8d7b upstream. Don't allow USB3 U1 or U2 if the latency to wake up from the U-state reaches the service interval for a periodic endpoint. This is according to xhci 1.1 specification section 4.23.5.2 extra note: "Software shall ensure that a device is prevented from entering a U-state where its worst case exit latency approaches the ESIT." Allowing too long exit latencies for periodic endpoint confuses xHC internal scheduling, and new devices may fail to enumerate with a "Not enough bandwidth for new device state" error from the host. Cc: Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 155b36265f7a..930eecd86429 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -4381,6 +4381,14 @@ static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, { unsigned long long timeout_ns; + /* Prevent U1 if service interval is shorter than U1 exit latency */ + if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) { + if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) { + dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n"); + return USB3_LPM_DISABLED; + } + } + if (xhci->quirks & XHCI_INTEL_HOST) timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); else @@ -4437,6 +4445,14 @@ static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, { unsigned long long timeout_ns; + /* Prevent U2 if service interval is shorter than U2 exit latency */ + if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) { + if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) { + dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n"); + return USB3_LPM_DISABLED; + } + } + if (xhci->quirks & XHCI_INTEL_HOST) timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); else -- GitLab From 38fce19d4d7bc8acfa183ee2918758d279a69c9a Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Mon, 10 Dec 2018 17:00:50 +0000 Subject: [PATCH 0420/1286] f2fs: fix to do sanity check with block address in main area v2 commit 91291e9998d208370eb8156c760691b873bd7522 upstream. This patch adds f2fs_is_valid_blkaddr() in below functions to do sanity check with block address to avoid pentential panic: - f2fs_grab_read_bio() - __written_first_block() https://bugzilla.kernel.org/show_bug.cgi?id=200465 - Reproduce - POC (poc.c) #define _GNU_SOURCE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static void activity(char *mpoint) { char *xattr; int err; err = asprintf(&xattr, "%s/foo/bar/xattr", mpoint); char buf2[113]; memset(buf2, 0, sizeof(buf2)); listxattr(xattr, buf2, sizeof(buf2)); } int main(int argc, char *argv[]) { activity(argv[1]); return 0; } - kernel message [ 844.718738] F2FS-fs (loop0): Mounted with checkpoint version = 2 [ 846.430929] F2FS-fs (loop0): access invalid blkaddr:1024 [ 846.431058] WARNING: CPU: 1 PID: 1249 at fs/f2fs/checkpoint.c:154 f2fs_is_valid_blkaddr+0x10f/0x160 [ 846.431059] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer snd input_leds joydev soundcore serio_raw i2c_piix4 mac_hid ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi autofs4 raid10 raid456 libcrc32c async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq raid1 raid0 multipath linear qxl ttm crct10dif_pclmul crc32_pclmul drm_kms_helper ghash_clmulni_intel syscopyarea sysfillrect sysimgblt fb_sys_fops pcbc drm 8139too aesni_intel 8139cp floppy psmouse mii aes_x86_64 crypto_simd pata_acpi cryptd glue_helper [ 846.431310] CPU: 1 PID: 1249 Comm: a.out Not tainted 4.18.0-rc3+ #1 [ 846.431312] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 846.431315] RIP: 0010:f2fs_is_valid_blkaddr+0x10f/0x160 [ 846.431316] Code: 00 eb ed 31 c0 83 fa 05 75 ae 48 83 ec 08 48 8b 3f 89 f1 48 c7 c2 fc 0b 0f 8b 48 c7 c6 8b d7 09 8b 88 44 24 07 e8 61 8b ff ff <0f> 0b 0f b6 44 24 07 48 83 c4 08 eb 81 4c 8b 47 10 8b 8f 38 04 00 [ 846.431347] RSP: 0018:ffff961c414a7bc0 EFLAGS: 00010282 [ 846.431349] RAX: 0000000000000000 RBX: ffffc5f787b8ea80 RCX: 0000000000000000 [ 846.431350] RDX: 0000000000000000 RSI: ffff89dfffd165d8 RDI: ffff89dfffd165d8 [ 846.431351] RBP: ffff961c414a7c20 R08: 0000000000000001 R09: 0000000000000248 [ 846.431353] R10: 0000000000000000 R11: 0000000000000248 R12: 0000000000000007 [ 846.431369] R13: ffff89dff5492800 R14: ffff89dfae3aa000 R15: ffff89dff4ff88d0 [ 846.431372] FS: 00007f882e2fb700(0000) GS:ffff89dfffd00000(0000) knlGS:0000000000000000 [ 846.431373] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.431374] CR2: 0000000001a88008 CR3: 00000001eb572000 CR4: 00000000000006e0 [ 846.431384] Call Trace: [ 846.431426] f2fs_iget+0x6f4/0xe70 [ 846.431430] ? f2fs_find_entry+0x71/0x90 [ 846.431432] f2fs_lookup+0x1aa/0x390 [ 846.431452] __lookup_slow+0x97/0x150 [ 846.431459] lookup_slow+0x35/0x50 [ 846.431462] walk_component+0x1c6/0x470 [ 846.431479] ? memcg_kmem_charge_memcg+0x70/0x90 [ 846.431488] ? page_add_file_rmap+0x13/0x200 [ 846.431491] path_lookupat+0x76/0x230 [ 846.431501] ? __alloc_pages_nodemask+0xfc/0x280 [ 846.431504] filename_lookup+0xb8/0x1a0 [ 846.431534] ? _cond_resched+0x16/0x40 [ 846.431541] ? kmem_cache_alloc+0x160/0x1d0 [ 846.431549] ? path_listxattr+0x41/0xa0 [ 846.431551] path_listxattr+0x41/0xa0 [ 846.431570] do_syscall_64+0x55/0x100 [ 846.431583] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 846.431607] RIP: 0033:0x7f882de1c0d7 [ 846.431607] Code: f0 ff ff 73 01 c3 48 8b 0d be dd 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 b8 c2 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 91 dd 2b 00 f7 d8 64 89 01 48 [ 846.431639] RSP: 002b:00007ffe8e66c238 EFLAGS: 00000202 ORIG_RAX: 00000000000000c2 [ 846.431641] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f882de1c0d7 [ 846.431642] RDX: 0000000000000071 RSI: 00007ffe8e66c280 RDI: 0000000001a880c0 [ 846.431643] RBP: 00007ffe8e66c300 R08: 0000000001a88010 R09: 0000000000000000 [ 846.431645] R10: 00000000000001ab R11: 0000000000000202 R12: 0000000000400550 [ 846.431646] R13: 00007ffe8e66c400 R14: 0000000000000000 R15: 0000000000000000 [ 846.431648] ---[ end trace abca54df39d14f5c ]--- [ 846.431651] F2FS-fs (loop0): invalid blkaddr: 1024, type: 5, run fsck to fix. [ 846.431762] WARNING: CPU: 1 PID: 1249 at fs/f2fs/f2fs.h:2697 f2fs_iget+0xd17/0xe70 [ 846.431763] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer snd input_leds joydev soundcore serio_raw i2c_piix4 mac_hid ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi autofs4 raid10 raid456 libcrc32c async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq raid1 raid0 multipath linear qxl ttm crct10dif_pclmul crc32_pclmul drm_kms_helper ghash_clmulni_intel syscopyarea sysfillrect sysimgblt fb_sys_fops pcbc drm 8139too aesni_intel 8139cp floppy psmouse mii aes_x86_64 crypto_simd pata_acpi cryptd glue_helper [ 846.431797] CPU: 1 PID: 1249 Comm: a.out Tainted: G W 4.18.0-rc3+ #1 [ 846.431798] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 846.431800] RIP: 0010:f2fs_iget+0xd17/0xe70 [ 846.431801] Code: ff ff 48 63 d8 e9 e1 f6 ff ff 48 8b 45 c8 41 b8 05 00 00 00 48 c7 c2 d8 e8 0e 8b 48 c7 c6 1d b0 0a 8b 48 8b 38 e8 f9 b4 00 00 <0f> 0b 48 8b 45 c8 f0 80 48 48 04 e9 d8 f9 ff ff 0f 0b 48 8b 43 18 [ 846.431832] RSP: 0018:ffff961c414a7bd0 EFLAGS: 00010282 [ 846.431834] RAX: 0000000000000000 RBX: ffffc5f787b8ea80 RCX: 0000000000000006 [ 846.431835] RDX: 0000000000000000 RSI: 0000000000000096 RDI: ffff89dfffd165d0 [ 846.431836] RBP: ffff961c414a7c20 R08: 0000000000000000 R09: 0000000000000273 [ 846.431837] R10: 0000000000000000 R11: ffff89dfad50ca60 R12: 0000000000000007 [ 846.431838] R13: ffff89dff5492800 R14: ffff89dfae3aa000 R15: ffff89dff4ff88d0 [ 846.431840] FS: 00007f882e2fb700(0000) GS:ffff89dfffd00000(0000) knlGS:0000000000000000 [ 846.431841] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.431842] CR2: 0000000001a88008 CR3: 00000001eb572000 CR4: 00000000000006e0 [ 846.431846] Call Trace: [ 846.431850] ? f2fs_find_entry+0x71/0x90 [ 846.431853] f2fs_lookup+0x1aa/0x390 [ 846.431856] __lookup_slow+0x97/0x150 [ 846.431858] lookup_slow+0x35/0x50 [ 846.431874] walk_component+0x1c6/0x470 [ 846.431878] ? memcg_kmem_charge_memcg+0x70/0x90 [ 846.431880] ? page_add_file_rmap+0x13/0x200 [ 846.431882] path_lookupat+0x76/0x230 [ 846.431884] ? __alloc_pages_nodemask+0xfc/0x280 [ 846.431886] filename_lookup+0xb8/0x1a0 [ 846.431890] ? _cond_resched+0x16/0x40 [ 846.431891] ? kmem_cache_alloc+0x160/0x1d0 [ 846.431894] ? path_listxattr+0x41/0xa0 [ 846.431896] path_listxattr+0x41/0xa0 [ 846.431898] do_syscall_64+0x55/0x100 [ 846.431901] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 846.431902] RIP: 0033:0x7f882de1c0d7 [ 846.431903] Code: f0 ff ff 73 01 c3 48 8b 0d be dd 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 b8 c2 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 91 dd 2b 00 f7 d8 64 89 01 48 [ 846.431934] RSP: 002b:00007ffe8e66c238 EFLAGS: 00000202 ORIG_RAX: 00000000000000c2 [ 846.431936] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f882de1c0d7 [ 846.431937] RDX: 0000000000000071 RSI: 00007ffe8e66c280 RDI: 0000000001a880c0 [ 846.431939] RBP: 00007ffe8e66c300 R08: 0000000001a88010 R09: 0000000000000000 [ 846.431940] R10: 00000000000001ab R11: 0000000000000202 R12: 0000000000400550 [ 846.431941] R13: 00007ffe8e66c400 R14: 0000000000000000 R15: 0000000000000000 [ 846.431943] ---[ end trace abca54df39d14f5d ]--- [ 846.432033] F2FS-fs (loop0): access invalid blkaddr:1024 [ 846.432051] WARNING: CPU: 1 PID: 1249 at fs/f2fs/checkpoint.c:154 f2fs_is_valid_blkaddr+0x10f/0x160 [ 846.432051] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer snd input_leds joydev soundcore serio_raw i2c_piix4 mac_hid ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi autofs4 raid10 raid456 libcrc32c async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq raid1 raid0 multipath linear qxl ttm crct10dif_pclmul crc32_pclmul drm_kms_helper ghash_clmulni_intel syscopyarea sysfillrect sysimgblt fb_sys_fops pcbc drm 8139too aesni_intel 8139cp floppy psmouse mii aes_x86_64 crypto_simd pata_acpi cryptd glue_helper [ 846.432085] CPU: 1 PID: 1249 Comm: a.out Tainted: G W 4.18.0-rc3+ #1 [ 846.432086] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 846.432089] RIP: 0010:f2fs_is_valid_blkaddr+0x10f/0x160 [ 846.432089] Code: 00 eb ed 31 c0 83 fa 05 75 ae 48 83 ec 08 48 8b 3f 89 f1 48 c7 c2 fc 0b 0f 8b 48 c7 c6 8b d7 09 8b 88 44 24 07 e8 61 8b ff ff <0f> 0b 0f b6 44 24 07 48 83 c4 08 eb 81 4c 8b 47 10 8b 8f 38 04 00 [ 846.432120] RSP: 0018:ffff961c414a7900 EFLAGS: 00010286 [ 846.432122] RAX: 0000000000000000 RBX: 0000000000000400 RCX: 0000000000000006 [ 846.432123] RDX: 0000000000000000 RSI: 0000000000000096 RDI: ffff89dfffd165d0 [ 846.432124] RBP: ffff89dff5492800 R08: 0000000000000001 R09: 000000000000029d [ 846.432125] R10: ffff961c414a7820 R11: 000000000000029d R12: 0000000000000400 [ 846.432126] R13: 0000000000000000 R14: ffff89dff4ff88d0 R15: 0000000000000000 [ 846.432128] FS: 00007f882e2fb700(0000) GS:ffff89dfffd00000(0000) knlGS:0000000000000000 [ 846.432130] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.432131] CR2: 0000000001a88008 CR3: 00000001eb572000 CR4: 00000000000006e0 [ 846.432135] Call Trace: [ 846.432151] f2fs_wait_on_block_writeback+0x20/0x110 [ 846.432158] f2fs_grab_read_bio+0xbc/0xe0 [ 846.432161] f2fs_submit_page_read+0x21/0x280 [ 846.432163] f2fs_get_read_data_page+0xb7/0x3c0 [ 846.432165] f2fs_get_lock_data_page+0x29/0x1e0 [ 846.432167] f2fs_get_new_data_page+0x148/0x550 [ 846.432170] f2fs_add_regular_entry+0x1d2/0x550 [ 846.432178] ? __switch_to+0x12f/0x460 [ 846.432181] f2fs_add_dentry+0x6a/0xd0 [ 846.432184] f2fs_do_add_link+0xe9/0x140 [ 846.432186] __recover_dot_dentries+0x260/0x280 [ 846.432189] f2fs_lookup+0x343/0x390 [ 846.432193] __lookup_slow+0x97/0x150 [ 846.432195] lookup_slow+0x35/0x50 [ 846.432208] walk_component+0x1c6/0x470 [ 846.432212] ? memcg_kmem_charge_memcg+0x70/0x90 [ 846.432215] ? page_add_file_rmap+0x13/0x200 [ 846.432217] path_lookupat+0x76/0x230 [ 846.432219] ? __alloc_pages_nodemask+0xfc/0x280 [ 846.432221] filename_lookup+0xb8/0x1a0 [ 846.432224] ? _cond_resched+0x16/0x40 [ 846.432226] ? kmem_cache_alloc+0x160/0x1d0 [ 846.432228] ? path_listxattr+0x41/0xa0 [ 846.432230] path_listxattr+0x41/0xa0 [ 846.432233] do_syscall_64+0x55/0x100 [ 846.432235] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 846.432237] RIP: 0033:0x7f882de1c0d7 [ 846.432237] Code: f0 ff ff 73 01 c3 48 8b 0d be dd 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 b8 c2 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 91 dd 2b 00 f7 d8 64 89 01 48 [ 846.432269] RSP: 002b:00007ffe8e66c238 EFLAGS: 00000202 ORIG_RAX: 00000000000000c2 [ 846.432271] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f882de1c0d7 [ 846.432272] RDX: 0000000000000071 RSI: 00007ffe8e66c280 RDI: 0000000001a880c0 [ 846.432273] RBP: 00007ffe8e66c300 R08: 0000000001a88010 R09: 0000000000000000 [ 846.432274] R10: 00000000000001ab R11: 0000000000000202 R12: 0000000000400550 [ 846.432275] R13: 00007ffe8e66c400 R14: 0000000000000000 R15: 0000000000000000 [ 846.432277] ---[ end trace abca54df39d14f5e ]--- [ 846.432279] F2FS-fs (loop0): invalid blkaddr: 1024, type: 5, run fsck to fix. [ 846.432376] WARNING: CPU: 1 PID: 1249 at fs/f2fs/f2fs.h:2697 f2fs_wait_on_block_writeback+0xb1/0x110 [ 846.432376] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer snd input_leds joydev soundcore serio_raw i2c_piix4 mac_hid ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi autofs4 raid10 raid456 libcrc32c async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq raid1 raid0 multipath linear qxl ttm crct10dif_pclmul crc32_pclmul drm_kms_helper ghash_clmulni_intel syscopyarea sysfillrect sysimgblt fb_sys_fops pcbc drm 8139too aesni_intel 8139cp floppy psmouse mii aes_x86_64 crypto_simd pata_acpi cryptd glue_helper [ 846.432410] CPU: 1 PID: 1249 Comm: a.out Tainted: G W 4.18.0-rc3+ #1 [ 846.432411] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 846.432413] RIP: 0010:f2fs_wait_on_block_writeback+0xb1/0x110 [ 846.432414] Code: 66 90 f0 ff 4b 34 74 59 5b 5d c3 48 8b 7d 00 41 b8 05 00 00 00 89 d9 48 c7 c2 d8 e8 0e 8b 48 c7 c6 1d b0 0a 8b e8 df bc fd ff <0f> 0b f0 80 4d 48 04 e9 67 ff ff ff 48 8b 03 48 c1 e8 37 83 e0 07 [ 846.432445] RSP: 0018:ffff961c414a7910 EFLAGS: 00010286 [ 846.432447] RAX: 0000000000000000 RBX: 0000000000000400 RCX: 0000000000000006 [ 846.432448] RDX: 0000000000000000 RSI: 0000000000000092 RDI: ffff89dfffd165d0 [ 846.432449] RBP: ffff89dff5492800 R08: 0000000000000000 R09: 00000000000002d1 [ 846.432450] R10: ffff961c414a7820 R11: ffff89dfad50cf80 R12: 0000000000000400 [ 846.432451] R13: 0000000000000000 R14: ffff89dff4ff88d0 R15: 0000000000000000 [ 846.432453] FS: 00007f882e2fb700(0000) GS:ffff89dfffd00000(0000) knlGS:0000000000000000 [ 846.432454] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.432455] CR2: 0000000001a88008 CR3: 00000001eb572000 CR4: 00000000000006e0 [ 846.432459] Call Trace: [ 846.432463] f2fs_grab_read_bio+0xbc/0xe0 [ 846.432464] f2fs_submit_page_read+0x21/0x280 [ 846.432466] f2fs_get_read_data_page+0xb7/0x3c0 [ 846.432468] f2fs_get_lock_data_page+0x29/0x1e0 [ 846.432470] f2fs_get_new_data_page+0x148/0x550 [ 846.432473] f2fs_add_regular_entry+0x1d2/0x550 [ 846.432475] ? __switch_to+0x12f/0x460 [ 846.432477] f2fs_add_dentry+0x6a/0xd0 [ 846.432480] f2fs_do_add_link+0xe9/0x140 [ 846.432483] __recover_dot_dentries+0x260/0x280 [ 846.432485] f2fs_lookup+0x343/0x390 [ 846.432488] __lookup_slow+0x97/0x150 [ 846.432490] lookup_slow+0x35/0x50 [ 846.432505] walk_component+0x1c6/0x470 [ 846.432509] ? memcg_kmem_charge_memcg+0x70/0x90 [ 846.432511] ? page_add_file_rmap+0x13/0x200 [ 846.432513] path_lookupat+0x76/0x230 [ 846.432515] ? __alloc_pages_nodemask+0xfc/0x280 [ 846.432517] filename_lookup+0xb8/0x1a0 [ 846.432520] ? _cond_resched+0x16/0x40 [ 846.432522] ? kmem_cache_alloc+0x160/0x1d0 [ 846.432525] ? path_listxattr+0x41/0xa0 [ 846.432526] path_listxattr+0x41/0xa0 [ 846.432529] do_syscall_64+0x55/0x100 [ 846.432531] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 846.432533] RIP: 0033:0x7f882de1c0d7 [ 846.432533] Code: f0 ff ff 73 01 c3 48 8b 0d be dd 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 b8 c2 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 91 dd 2b 00 f7 d8 64 89 01 48 [ 846.432565] RSP: 002b:00007ffe8e66c238 EFLAGS: 00000202 ORIG_RAX: 00000000000000c2 [ 846.432567] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f882de1c0d7 [ 846.432568] RDX: 0000000000000071 RSI: 00007ffe8e66c280 RDI: 0000000001a880c0 [ 846.432569] RBP: 00007ffe8e66c300 R08: 0000000001a88010 R09: 0000000000000000 [ 846.432570] R10: 00000000000001ab R11: 0000000000000202 R12: 0000000000400550 [ 846.432571] R13: 00007ffe8e66c400 R14: 0000000000000000 R15: 0000000000000000 [ 846.432573] ---[ end trace abca54df39d14f5f ]--- [ 846.434280] BUG: unable to handle kernel NULL pointer dereference at 0000000000000008 [ 846.434424] PGD 80000001ebd3a067 P4D 80000001ebd3a067 PUD 1eb1ae067 PMD 0 [ 846.434551] Oops: 0000 [#1] SMP PTI [ 846.434697] CPU: 0 PID: 44 Comm: kworker/u5:0 Tainted: G W 4.18.0-rc3+ #1 [ 846.434805] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 846.435000] Workqueue: fscrypt_read_queue decrypt_work [ 846.435174] RIP: 0010:fscrypt_do_page_crypto+0x6e/0x2d0 [ 846.435351] Code: 00 65 48 8b 04 25 28 00 00 00 48 89 84 24 88 00 00 00 31 c0 e8 43 c2 e0 ff 49 8b 86 48 02 00 00 85 ed c7 44 24 70 00 00 00 00 <48> 8b 58 08 0f 84 14 02 00 00 48 8b 78 10 48 8b 0c 24 48 c7 84 24 [ 846.435696] RSP: 0018:ffff961c40f9bd60 EFLAGS: 00010206 [ 846.435870] RAX: 0000000000000000 RBX: ffffc5f787719b80 RCX: ffffc5f787719b80 [ 846.436051] RDX: ffffffff8b9f4b88 RSI: ffffffff8b0ae622 RDI: ffff961c40f9bdb8 [ 846.436261] RBP: 0000000000001000 R08: ffffc5f787719b80 R09: 0000000000001000 [ 846.436433] R10: 0000000000000018 R11: fefefefefefefeff R12: ffffc5f787719b80 [ 846.436562] R13: ffffc5f787719b80 R14: ffff89dff4ff88d0 R15: 0ffff89dfaddee60 [ 846.436658] FS: 0000000000000000(0000) GS:ffff89dfffc00000(0000) knlGS:0000000000000000 [ 846.436758] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.436898] CR2: 0000000000000008 CR3: 00000001eddd0000 CR4: 00000000000006f0 [ 846.437001] Call Trace: [ 846.437181] ? check_preempt_wakeup+0xf2/0x230 [ 846.437276] ? check_preempt_curr+0x7c/0x90 [ 846.437370] fscrypt_decrypt_page+0x48/0x4d [ 846.437466] __fscrypt_decrypt_bio+0x5b/0x90 [ 846.437542] decrypt_work+0x12/0x20 [ 846.437651] process_one_work+0x15e/0x3d0 [ 846.437740] worker_thread+0x4c/0x440 [ 846.437848] kthread+0xf8/0x130 [ 846.437938] ? rescuer_thread+0x350/0x350 [ 846.438022] ? kthread_associate_blkcg+0x90/0x90 [ 846.438117] ret_from_fork+0x35/0x40 [ 846.438201] Modules linked in: snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_timer snd input_leds joydev soundcore serio_raw i2c_piix4 mac_hid ib_iser rdma_cm iw_cm ib_cm ib_core configfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi autofs4 raid10 raid456 libcrc32c async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq raid1 raid0 multipath linear qxl ttm crct10dif_pclmul crc32_pclmul drm_kms_helper ghash_clmulni_intel syscopyarea sysfillrect sysimgblt fb_sys_fops pcbc drm 8139too aesni_intel 8139cp floppy psmouse mii aes_x86_64 crypto_simd pata_acpi cryptd glue_helper [ 846.438653] CR2: 0000000000000008 [ 846.438713] ---[ end trace abca54df39d14f60 ]--- [ 846.438796] RIP: 0010:fscrypt_do_page_crypto+0x6e/0x2d0 [ 846.438844] Code: 00 65 48 8b 04 25 28 00 00 00 48 89 84 24 88 00 00 00 31 c0 e8 43 c2 e0 ff 49 8b 86 48 02 00 00 85 ed c7 44 24 70 00 00 00 00 <48> 8b 58 08 0f 84 14 02 00 00 48 8b 78 10 48 8b 0c 24 48 c7 84 24 [ 846.439084] RSP: 0018:ffff961c40f9bd60 EFLAGS: 00010206 [ 846.439176] RAX: 0000000000000000 RBX: ffffc5f787719b80 RCX: ffffc5f787719b80 [ 846.440927] RDX: ffffffff8b9f4b88 RSI: ffffffff8b0ae622 RDI: ffff961c40f9bdb8 [ 846.442083] RBP: 0000000000001000 R08: ffffc5f787719b80 R09: 0000000000001000 [ 846.443284] R10: 0000000000000018 R11: fefefefefefefeff R12: ffffc5f787719b80 [ 846.444448] R13: ffffc5f787719b80 R14: ffff89dff4ff88d0 R15: 0ffff89dfaddee60 [ 846.445558] FS: 0000000000000000(0000) GS:ffff89dfffc00000(0000) knlGS:0000000000000000 [ 846.446687] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 846.447796] CR2: 0000000000000008 CR3: 00000001eddd0000 CR4: 00000000000006f0 - Location https://elixir.bootlin.com/linux/v4.18-rc4/source/fs/crypto/crypto.c#L149 struct crypto_skcipher *tfm = ci->ci_ctfm; Here ci can be NULL Note that this issue maybe require CONFIG_F2FS_FS_ENCRYPTION=y to reproduce. Reported-by Wen Xu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim [bwh: Backported to 4.14: adjust context] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- fs/f2fs/data.c | 3 +++ fs/f2fs/inode.c | 18 +++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 8f6e7c3a10f8..c68b319b07aa 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -468,6 +468,9 @@ static struct bio *f2fs_grab_read_bio(struct inode *inode, block_t blkaddr, struct fscrypt_ctx *ctx = NULL; struct bio *bio; + if (!f2fs_is_valid_blkaddr(sbi, blkaddr, DATA_GENERIC)) + return ERR_PTR(-EFAULT); + if (f2fs_encrypted_file(inode)) { ctx = fscrypt_get_ctx(inode, GFP_NOFS); if (IS_ERR(ctx)) diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 9a40724dbaa6..50818b519df8 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -62,14 +62,16 @@ static void __get_inode_rdev(struct inode *inode, struct f2fs_inode *ri) } } -static bool __written_first_block(struct f2fs_sb_info *sbi, +static int __written_first_block(struct f2fs_sb_info *sbi, struct f2fs_inode *ri) { block_t addr = le32_to_cpu(ri->i_addr[offset_in_addr(ri)]); - if (is_valid_data_blkaddr(sbi, addr)) - return true; - return false; + if (!__is_valid_data_blkaddr(addr)) + return 1; + if (!f2fs_is_valid_blkaddr(sbi, addr, DATA_GENERIC)) + return -EFAULT; + return 0; } static void __set_inode_rdev(struct inode *inode, struct f2fs_inode *ri) @@ -253,6 +255,7 @@ static int do_read_inode(struct inode *inode) struct page *node_page; struct f2fs_inode *ri; projid_t i_projid; + int err; /* Check if ino is within scope */ if (check_nid_range(sbi, inode->i_ino)) @@ -307,7 +310,12 @@ static int do_read_inode(struct inode *inode) /* get rdev by using inline_info */ __get_inode_rdev(inode, ri); - if (__written_first_block(sbi, ri)) + err = __written_first_block(sbi, ri); + if (err < 0) { + f2fs_put_page(node_page, 1); + return err; + } + if (!err) set_inode_flag(inode, FI_FIRST_BLOCK_WRITTEN); if (!need_inode_block_update(sbi, inode->i_ino)) -- GitLab From f2a4f7622d052eb987e8693633468c239c13575a Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Mon, 10 Dec 2018 18:14:58 +0000 Subject: [PATCH 0421/1286] swiotlb: clean up reporting commit 7d63fb3af87aa67aa7d24466e792f9d7c57d8e79 upstream. This removes needless use of '%p', and refactors the printk calls to use pr_*() helpers instead. Signed-off-by: Kees Cook Reviewed-by: Konrad Rzeszutek Wilk Signed-off-by: Christoph Hellwig [bwh: Backported to 4.14: - Adjust filename - Remove "swiotlb: " prefix from an additional log message] Signed-off-by: Ben Hutchings Signed-off-by: Sasha Levin --- lib/swiotlb.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/lib/swiotlb.c b/lib/swiotlb.c index 20df2fd9b150..b4c768de3344 100644 --- a/lib/swiotlb.c +++ b/lib/swiotlb.c @@ -17,6 +17,8 @@ * 08/12/11 beckyb Add highmem support */ +#define pr_fmt(fmt) "software IO TLB: " fmt + #include #include #include @@ -177,20 +179,16 @@ static bool no_iotlb_memory; void swiotlb_print_info(void) { unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; - unsigned char *vstart, *vend; if (no_iotlb_memory) { - pr_warn("software IO TLB: No low mem\n"); + pr_warn("No low mem\n"); return; } - vstart = phys_to_virt(io_tlb_start); - vend = phys_to_virt(io_tlb_end); - - printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", + pr_info("mapped [mem %#010llx-%#010llx] (%luMB)\n", (unsigned long long)io_tlb_start, (unsigned long long)io_tlb_end, - bytes >> 20, vstart, vend - 1); + bytes >> 20); } /* @@ -290,7 +288,7 @@ swiotlb_init(int verbose) if (io_tlb_start) memblock_free_early(io_tlb_start, PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); - pr_warn("Cannot allocate SWIOTLB buffer"); + pr_warn("Cannot allocate buffer"); no_iotlb_memory = true; } @@ -332,8 +330,8 @@ swiotlb_late_init_with_default_size(size_t default_size) return -ENOMEM; } if (order != get_order(bytes)) { - printk(KERN_WARNING "Warning: only able to allocate %ld MB " - "for software IO TLB\n", (PAGE_SIZE << order) >> 20); + pr_warn("only able to allocate %ld MB\n", + (PAGE_SIZE << order) >> 20); io_tlb_nslabs = SLABS_PER_PAGE << order; } rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); @@ -770,7 +768,7 @@ swiotlb_alloc_coherent(struct device *hwdev, size_t size, err_warn: if (warn && printk_ratelimit()) { - pr_warn("swiotlb: coherent allocation failed for device %s size=%zu\n", + pr_warn("coherent allocation failed for device %s size=%zu\n", dev_name(hwdev), size); dump_stack(); } -- GitLab From b4e4b85708bb31df79d6fc77661bb171e07e0868 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 11 Dec 2018 13:50:37 +0100 Subject: [PATCH 0422/1286] Staging: lustre: remove two build warnings [for older kernels only, lustre has been removed from upstream] When someone writes: strncpy(dest, source, sizeof(source)); they really are just doing the same thing as: strcpy(dest, source); but somehow they feel better because they are now using the "safe" version of the string functions. Cargo-cult programming at its finest... gcc-8 rightfully warns you about doing foolish things like this. Now that the stable kernels are all starting to be built using gcc-8, let's get rid of this warning so that we do not have to gaze at this horror. To dropt the warning, just convert the code to using strcpy() so that if someone really wants to audit this code and find all of the obvious problems, it will be easier to do so. Signed-off-by: Greg Kroah-Hartman --- drivers/staging/lustre/lnet/lnet/config.c | 3 +-- drivers/staging/lustre/lustre/lmv/lmv_obd.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/staging/lustre/lnet/lnet/config.c b/drivers/staging/lustre/lnet/lnet/config.c index 26841a7b6213..99b400c4190f 100644 --- a/drivers/staging/lustre/lnet/lnet/config.c +++ b/drivers/staging/lustre/lnet/lnet/config.c @@ -354,8 +354,7 @@ lnet_parse_networks(struct list_head *nilist, char *networks) CERROR("Can't allocate net interface name\n"); goto failed; } - strncpy(ni->ni_interfaces[niface], iface, - strlen(iface)); + strcpy(ni->ni_interfaces[niface], iface); niface++; iface = comma; } while (iface); diff --git a/drivers/staging/lustre/lustre/lmv/lmv_obd.c b/drivers/staging/lustre/lustre/lmv/lmv_obd.c index c2aadb2d1fea..fa46fe9e1bd9 100644 --- a/drivers/staging/lustre/lustre/lmv/lmv_obd.c +++ b/drivers/staging/lustre/lustre/lmv/lmv_obd.c @@ -645,7 +645,7 @@ static int lmv_fid2path(struct obd_export *exp, int len, void *karg, memmove(ptr + strlen(gf->gf_path) + 1, ptr, strlen(ori_gf->gf_path)); - strncpy(ptr, gf->gf_path, strlen(gf->gf_path)); + strcpy(ptr, gf->gf_path); ptr += strlen(gf->gf_path); *ptr = '/'; } -- GitLab From a604686c468dc0ab9492dbeaa1722cc3878b0582 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 11 Dec 2018 13:50:55 +0100 Subject: [PATCH 0423/1286] staging: atomisp: remove "fun" strncpy warning [for older kernels only, atomisp has been removed from upstream] gcc-8 rightfully warns that this instance of strncpy is just copying from the source, to the same source, for a few bytes. Meaning this call does nothing. As the author of the code obviously meant it to do something, but this code must be working properly, just replace the call to the kernel internal strscpy() which gcc doesn't know about, so the warning goes away. As this driver was deleted from newer kernel versions, none of this really matters but now at least we do not have to worry about a build warning in the stable trees. Signed-off-by: Greg Kroah-Hartman --- .../pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c index 0fa7cb2423d8..0320c089f688 100644 --- a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c @@ -2860,9 +2860,7 @@ ia_css_debug_pipe_graph_dump_stage( if (l <= ENABLE_LINE_MAX_LENGTH) { /* It fits on one line, copy string and init */ /* other helper strings with empty string */ - strcpy_s(enable_info, - sizeof(enable_info), - ei); + strscpy(enable_info, ei, sizeof(enable_info)); } else { /* Too big for one line, find last comma */ p = ENABLE_LINE_MAX_LENGTH; -- GitLab From b505b9b09e531cfe9bfcb602ed9407d8bd902ad4 Mon Sep 17 00:00:00 2001 From: Paulo Alcantara Date: Thu, 15 Nov 2018 15:20:52 +0100 Subject: [PATCH 0424/1286] cifs: Fix separator when building path from dentry commit c988de29ca161823db6a7125e803d597ef75b49c upstream. Make sure to use the CIFS_DIR_SEP(cifs_sb) as path separator for prefixpath too. Fixes a bug with smb1 UNIX extensions. Fixes: a6b5058fafdf ("fs/cifs: make share unaccessible at root level mountable") Signed-off-by: Paulo Alcantara Reviewed-by: Aurelien Aptel Signed-off-by: Steve French CC: Stable Signed-off-by: Greg Kroah-Hartman --- fs/cifs/dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c index 925844343038..ca98afda3cdb 100644 --- a/fs/cifs/dir.c +++ b/fs/cifs/dir.c @@ -174,7 +174,7 @@ build_path_from_dentry_optional_prefix(struct dentry *direntry, bool prefix) cifs_dbg(FYI, "using cifs_sb prepath <%s>\n", cifs_sb->prepath); memcpy(full_path+dfsplen+1, cifs_sb->prepath, pplen-1); - full_path[dfsplen] = '\\'; + full_path[dfsplen] = dirsep; for (i = 0; i < pplen-1; i++) if (full_path[dfsplen+1+i] == '/') full_path[dfsplen+1+i] = CIFS_DIR_SEP(cifs_sb); -- GitLab From 948ef68099ebe26a52749ad031febb15b4c5dac7 Mon Sep 17 00:00:00 2001 From: Young Xiao Date: Wed, 28 Nov 2018 08:06:53 +0000 Subject: [PATCH 0425/1286] staging: rtl8712: Fix possible buffer overrun commit 300cd664865bed5d50ae0a42fb4e3a6f415e8a10 upstream. In commit 8b7a13c3f404 ("staging: r8712u: Fix possible buffer overrun") we fix a potential off by one by making the limit smaller. The better fix is to make the buffer larger. This makes it match up with the similar code in other drivers. Fixes: 8b7a13c3f404 ("staging: r8712u: Fix possible buffer overrun") Signed-off-by: Young Xiao Cc: stable Reviewed-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8712/mlme_linux.c | 2 +- drivers/staging/rtl8712/rtl871x_mlme.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8712/mlme_linux.c b/drivers/staging/rtl8712/mlme_linux.c index a077069d6227..7e367452c339 100644 --- a/drivers/staging/rtl8712/mlme_linux.c +++ b/drivers/staging/rtl8712/mlme_linux.c @@ -158,7 +158,7 @@ void r8712_report_sec_ie(struct _adapter *adapter, u8 authmode, u8 *sec_ie) p = buff; p += sprintf(p, "ASSOCINFO(ReqIEs="); len = sec_ie[1] + 2; - len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX - 1; + len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX; for (i = 0; i < len; i++) p += sprintf(p, "%02x", sec_ie[i]); p += sprintf(p, ")"); diff --git a/drivers/staging/rtl8712/rtl871x_mlme.c b/drivers/staging/rtl8712/rtl871x_mlme.c index bf1ac22bae1c..98c7e8b229d1 100644 --- a/drivers/staging/rtl8712/rtl871x_mlme.c +++ b/drivers/staging/rtl8712/rtl871x_mlme.c @@ -1361,7 +1361,7 @@ sint r8712_restruct_sec_ie(struct _adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) { u8 authmode = 0, match; - u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; + u8 sec_ie[IW_CUSTOM_MAX], uncst_oui[4], bkup_ie[255]; u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; uint ielength, cnt, remove_cnt; int iEntry; -- GitLab From c33e7a5a3714250ca452ef8353c91cf7ad411ac6 Mon Sep 17 00:00:00 2001 From: Young Xiao Date: Tue, 27 Nov 2018 09:12:20 +0000 Subject: [PATCH 0426/1286] Revert commit ef9209b642f "staging: rtl8723bs: Fix indenting errors and an off-by-one mistake in core/rtw_mlme_ext.c" commit 87e4a5405f087427fbf8b437d2796283dce2b38f upstream. pstapriv->max_num_sta is always <= NUM_STA, since max_num_sta is either set in _rtw_init_sta_priv() or rtw_set_beacon(). Fixes: ef9209b642f1 ("staging: rtl8723bs: Fix indenting errors and an off-by-one mistake in core/rtw_mlme_ext.c") Signed-off-by: Young Xiao Reviewed-by: Dan Carpenter Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8723bs/core/rtw_mlme_ext.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c b/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c index b6d137f505e1..111752f0bc27 100644 --- a/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c +++ b/drivers/staging/rtl8723bs/core/rtw_mlme_ext.c @@ -1574,7 +1574,7 @@ unsigned int OnAssocReq(struct adapter *padapter, union recv_frame *precv_frame) if (pstat->aid > 0) { DBG_871X(" old AID %d\n", pstat->aid); } else { - for (pstat->aid = 1; pstat->aid < NUM_STA; pstat->aid++) + for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) if (pstapriv->sta_aid[pstat->aid - 1] == NULL) break; -- GitLab From 99e6900dfa125ef5062e7b0595f6ce5eb75a6d2c Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Thu, 22 Nov 2018 17:53:00 +0800 Subject: [PATCH 0427/1286] drm/amdgpu: update mc firmware image for polaris12 variants commit d7fd67653f847327e545bdb198b901ee124afd7c upstream. Some new variants require updated firmware. Signed-off-by: Junwei Zhang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 3b3326daf32b..b3de9334ed48 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -52,6 +52,7 @@ MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -226,6 +227,15 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) break; case CHIP_POLARIS12: chip_name = "polaris12"; + if (((adev->pdev->device == 0x6987) && + ((adev->pdev->revision == 0xc0) || + (adev->pdev->revision == 0xc3))) || + ((adev->pdev->device == 0x6981) && + ((adev->pdev->revision == 0x00) || + (adev->pdev->revision == 0x01) || + (adev->pdev->revision == 0x10)))) { + chip_name = "polaris12_k"; + } break; case CHIP_FIJI: case CHIP_CARRIZO: -- GitLab From eff5e74f7b680d51c9cd9a087f18ce99788b2aba Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Nov 2018 23:25:41 -0500 Subject: [PATCH 0428/1286] drm/amdgpu/gmc8: update MC firmware for polaris MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit a81a7c9c9ea3042ab02d66ac35def74abf091c15 upstream. Some variants require different MC firmware images. Acked-by: Christian König Reviewed-by: Junwei Zhang Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 29 ++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index b3de9334ed48..0f5dc97ae920 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -52,6 +52,8 @@ MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); static const u32 golden_settings_tonga_a11[] = @@ -220,22 +222,39 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) chip_name = "tonga"; break; case CHIP_POLARIS11: - chip_name = "polaris11"; + if (((adev->pdev->device == 0x67ef) && + ((adev->pdev->revision == 0xe0) || + (adev->pdev->revision == 0xe5))) || + ((adev->pdev->device == 0x67ff) && + ((adev->pdev->revision == 0xcf) || + (adev->pdev->revision == 0xef) || + (adev->pdev->revision == 0xff)))) + chip_name = "polaris11_k"; + else if ((adev->pdev->device == 0x67ef) && + (adev->pdev->revision == 0xe2)) + chip_name = "polaris11_k"; + else + chip_name = "polaris11"; break; case CHIP_POLARIS10: - chip_name = "polaris10"; + if ((adev->pdev->device == 0x67df) && + ((adev->pdev->revision == 0xe1) || + (adev->pdev->revision == 0xf7))) + chip_name = "polaris10_k"; + else + chip_name = "polaris10"; break; case CHIP_POLARIS12: - chip_name = "polaris12"; if (((adev->pdev->device == 0x6987) && ((adev->pdev->revision == 0xc0) || (adev->pdev->revision == 0xc3))) || ((adev->pdev->device == 0x6981) && ((adev->pdev->revision == 0x00) || (adev->pdev->revision == 0x01) || - (adev->pdev->revision == 0x10)))) { + (adev->pdev->revision == 0x10)))) chip_name = "polaris12_k"; - } + else + chip_name = "polaris12"; break; case CHIP_FIJI: case CHIP_CARRIZO: -- GitLab From c1063941e7360e1a5c998c58de789d5de267175b Mon Sep 17 00:00:00 2001 From: Dexuan Cui Date: Mon, 3 Dec 2018 00:54:35 +0000 Subject: [PATCH 0429/1286] Drivers: hv: vmbus: Offload the handling of channels to two workqueues commit 37c2578c0c40e286bc0d30bdc05290b2058cf66e upstream. vmbus_process_offer() mustn't call channel->sc_creation_callback() directly for sub-channels, because sc_creation_callback() -> vmbus_open() may never get the host's response to the OPEN_CHANNEL message (the host may rescind a channel at any time, e.g. in the case of hot removing a NIC), and vmbus_onoffer_rescind() may not wake up the vmbus_open() as it's blocked due to a non-zero vmbus_connection.offer_in_progress, and finally we have a deadlock. The above is also true for primary channels, if the related device drivers use sync probing mode by default. And, usually the handling of primary channels and sub-channels can depend on each other, so we should offload them to different workqueues to avoid possible deadlock, e.g. in sync-probing mode, NIC1's netvsc_subchan_work() can race with NIC2's netvsc_probe() -> rtnl_lock(), and causes deadlock: the former gets the rtnl_lock and waits for all the sub-channels to appear, but the latter can't get the rtnl_lock and this blocks the handling of sub-channels. The patch can fix the multiple-NIC deadlock described above for v3.x kernels (e.g. RHEL 7.x) which don't support async-probing of devices, and v4.4, v4.9, v4.14 and v4.18 which support async-probing but don't enable async-probing for Hyper-V drivers (yet). The patch can also fix the hang issue in sub-channel's handling described above for all versions of kernels, including v4.19 and v4.20-rc4. So actually the patch should be applied to all the existing kernels, not only the kernels that have 8195b1396ec8. Fixes: 8195b1396ec8 ("hv_netvsc: fix deadlock on hotplug") Cc: stable@vger.kernel.org Cc: Stephen Hemminger Cc: K. Y. Srinivasan Cc: Haiyang Zhang Signed-off-by: Dexuan Cui Signed-off-by: K. Y. Srinivasan Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel_mgmt.c | 185 +++++++++++++++++++++++++------------- drivers/hv/connection.c | 24 ++++- drivers/hv/hyperv_vmbus.h | 7 ++ include/linux/hyperv.h | 7 ++ 4 files changed, 160 insertions(+), 63 deletions(-) diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index 752c52f7353d..43eaf54736f4 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -444,61 +444,16 @@ void vmbus_free_channels(void) } } -/* - * vmbus_process_offer - Process the offer by creating a channel/device - * associated with this offer - */ -static void vmbus_process_offer(struct vmbus_channel *newchannel) +/* Note: the function can run concurrently for primary/sub channels. */ +static void vmbus_add_channel_work(struct work_struct *work) { - struct vmbus_channel *channel; - bool fnew = true; + struct vmbus_channel *newchannel = + container_of(work, struct vmbus_channel, add_channel_work); + struct vmbus_channel *primary_channel = newchannel->primary_channel; unsigned long flags; u16 dev_type; int ret; - /* Make sure this is a new offer */ - mutex_lock(&vmbus_connection.channel_mutex); - - /* - * Now that we have acquired the channel_mutex, - * we can release the potentially racing rescind thread. - */ - atomic_dec(&vmbus_connection.offer_in_progress); - - list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) { - if (!uuid_le_cmp(channel->offermsg.offer.if_type, - newchannel->offermsg.offer.if_type) && - !uuid_le_cmp(channel->offermsg.offer.if_instance, - newchannel->offermsg.offer.if_instance)) { - fnew = false; - break; - } - } - - if (fnew) - list_add_tail(&newchannel->listentry, - &vmbus_connection.chn_list); - - mutex_unlock(&vmbus_connection.channel_mutex); - - if (!fnew) { - /* - * Check to see if this is a sub-channel. - */ - if (newchannel->offermsg.offer.sub_channel_index != 0) { - /* - * Process the sub-channel. - */ - newchannel->primary_channel = channel; - spin_lock_irqsave(&channel->lock, flags); - list_add_tail(&newchannel->sc_list, &channel->sc_list); - channel->num_sc++; - spin_unlock_irqrestore(&channel->lock, flags); - } else { - goto err_free_chan; - } - } - dev_type = hv_get_dev_type(newchannel); init_vp_index(newchannel, dev_type); @@ -516,21 +471,22 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) /* * This state is used to indicate a successful open * so that when we do close the channel normally, we - * can cleanup properly + * can cleanup properly. */ newchannel->state = CHANNEL_OPEN_STATE; - if (!fnew) { - if (channel->sc_creation_callback != NULL) - channel->sc_creation_callback(newchannel); + if (primary_channel != NULL) { + /* newchannel is a sub-channel. */ + + if (primary_channel->sc_creation_callback != NULL) + primary_channel->sc_creation_callback(newchannel); + newchannel->probe_done = true; return; } /* - * Start the process of binding this offer to the driver - * We need to set the DeviceObject field before calling - * vmbus_child_dev_add() + * Start the process of binding the primary channel to the driver */ newchannel->device_obj = vmbus_device_create( &newchannel->offermsg.offer.if_type, @@ -559,13 +515,28 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) err_deq_chan: mutex_lock(&vmbus_connection.channel_mutex); - list_del(&newchannel->listentry); + + /* + * We need to set the flag, otherwise + * vmbus_onoffer_rescind() can be blocked. + */ + newchannel->probe_done = true; + + if (primary_channel == NULL) { + list_del(&newchannel->listentry); + } else { + spin_lock_irqsave(&primary_channel->lock, flags); + list_del(&newchannel->sc_list); + spin_unlock_irqrestore(&primary_channel->lock, flags); + } + mutex_unlock(&vmbus_connection.channel_mutex); if (newchannel->target_cpu != get_cpu()) { put_cpu(); smp_call_function_single(newchannel->target_cpu, - percpu_channel_deq, newchannel, true); + percpu_channel_deq, + newchannel, true); } else { percpu_channel_deq(newchannel); put_cpu(); @@ -573,14 +544,104 @@ static void vmbus_process_offer(struct vmbus_channel *newchannel) vmbus_release_relid(newchannel->offermsg.child_relid); -err_free_chan: free_channel(newchannel); } +/* + * vmbus_process_offer - Process the offer by creating a channel/device + * associated with this offer + */ +static void vmbus_process_offer(struct vmbus_channel *newchannel) +{ + struct vmbus_channel *channel; + struct workqueue_struct *wq; + unsigned long flags; + bool fnew = true; + + mutex_lock(&vmbus_connection.channel_mutex); + + /* + * Now that we have acquired the channel_mutex, + * we can release the potentially racing rescind thread. + */ + atomic_dec(&vmbus_connection.offer_in_progress); + + list_for_each_entry(channel, &vmbus_connection.chn_list, listentry) { + if (!uuid_le_cmp(channel->offermsg.offer.if_type, + newchannel->offermsg.offer.if_type) && + !uuid_le_cmp(channel->offermsg.offer.if_instance, + newchannel->offermsg.offer.if_instance)) { + fnew = false; + break; + } + } + + if (fnew) + list_add_tail(&newchannel->listentry, + &vmbus_connection.chn_list); + else { + /* + * Check to see if this is a valid sub-channel. + */ + if (newchannel->offermsg.offer.sub_channel_index == 0) { + mutex_unlock(&vmbus_connection.channel_mutex); + /* + * Don't call free_channel(), because newchannel->kobj + * is not initialized yet. + */ + kfree(newchannel); + WARN_ON_ONCE(1); + return; + } + /* + * Process the sub-channel. + */ + newchannel->primary_channel = channel; + spin_lock_irqsave(&channel->lock, flags); + list_add_tail(&newchannel->sc_list, &channel->sc_list); + spin_unlock_irqrestore(&channel->lock, flags); + } + + mutex_unlock(&vmbus_connection.channel_mutex); + + /* + * vmbus_process_offer() mustn't call channel->sc_creation_callback() + * directly for sub-channels, because sc_creation_callback() -> + * vmbus_open() may never get the host's response to the + * OPEN_CHANNEL message (the host may rescind a channel at any time, + * e.g. in the case of hot removing a NIC), and vmbus_onoffer_rescind() + * may not wake up the vmbus_open() as it's blocked due to a non-zero + * vmbus_connection.offer_in_progress, and finally we have a deadlock. + * + * The above is also true for primary channels, if the related device + * drivers use sync probing mode by default. + * + * And, usually the handling of primary channels and sub-channels can + * depend on each other, so we should offload them to different + * workqueues to avoid possible deadlock, e.g. in sync-probing mode, + * NIC1's netvsc_subchan_work() can race with NIC2's netvsc_probe() -> + * rtnl_lock(), and causes deadlock: the former gets the rtnl_lock + * and waits for all the sub-channels to appear, but the latter + * can't get the rtnl_lock and this blocks the handling of + * sub-channels. + */ + INIT_WORK(&newchannel->add_channel_work, vmbus_add_channel_work); + wq = fnew ? vmbus_connection.handle_primary_chan_wq : + vmbus_connection.handle_sub_chan_wq; + queue_work(wq, &newchannel->add_channel_work); +} + /* * We use this state to statically distribute the channel interrupt load. */ static int next_numa_node_id; +/* + * init_vp_index() accesses global variables like next_numa_node_id, and + * it can run concurrently for primary channels and sub-channels: see + * vmbus_process_offer(), so we need the lock to protect the global + * variables. + */ +static DEFINE_SPINLOCK(bind_channel_to_cpu_lock); /* * Starting with Win8, we can statically distribute the incoming @@ -618,6 +679,8 @@ static void init_vp_index(struct vmbus_channel *channel, u16 dev_type) return; } + spin_lock(&bind_channel_to_cpu_lock); + /* * Based on the channel affinity policy, we will assign the NUMA * nodes. @@ -700,6 +763,8 @@ static void init_vp_index(struct vmbus_channel *channel, u16 dev_type) channel->target_cpu = cur_cpu; channel->target_vp = hv_cpu_number_to_vp_number(cur_cpu); + spin_unlock(&bind_channel_to_cpu_lock); + free_cpumask_var(available_mask); } diff --git a/drivers/hv/connection.c b/drivers/hv/connection.c index 5449fc59b7f5..4b1b70751be3 100644 --- a/drivers/hv/connection.c +++ b/drivers/hv/connection.c @@ -161,6 +161,20 @@ int vmbus_connect(void) goto cleanup; } + vmbus_connection.handle_primary_chan_wq = + create_workqueue("hv_pri_chan"); + if (!vmbus_connection.handle_primary_chan_wq) { + ret = -ENOMEM; + goto cleanup; + } + + vmbus_connection.handle_sub_chan_wq = + create_workqueue("hv_sub_chan"); + if (!vmbus_connection.handle_sub_chan_wq) { + ret = -ENOMEM; + goto cleanup; + } + INIT_LIST_HEAD(&vmbus_connection.chn_msg_list); spin_lock_init(&vmbus_connection.channelmsg_lock); @@ -251,10 +265,14 @@ void vmbus_disconnect(void) */ vmbus_initiate_unload(false); - if (vmbus_connection.work_queue) { - drain_workqueue(vmbus_connection.work_queue); + if (vmbus_connection.handle_sub_chan_wq) + destroy_workqueue(vmbus_connection.handle_sub_chan_wq); + + if (vmbus_connection.handle_primary_chan_wq) + destroy_workqueue(vmbus_connection.handle_primary_chan_wq); + + if (vmbus_connection.work_queue) destroy_workqueue(vmbus_connection.work_queue); - } if (vmbus_connection.int_page) { free_pages((unsigned long)vmbus_connection.int_page, 0); diff --git a/drivers/hv/hyperv_vmbus.h b/drivers/hv/hyperv_vmbus.h index 49569f8fe038..a166de6efd99 100644 --- a/drivers/hv/hyperv_vmbus.h +++ b/drivers/hv/hyperv_vmbus.h @@ -327,7 +327,14 @@ struct vmbus_connection { struct list_head chn_list; struct mutex channel_mutex; + /* + * An offer message is handled first on the work_queue, and then + * is further handled on handle_primary_chan_wq or + * handle_sub_chan_wq. + */ struct workqueue_struct *work_queue; + struct workqueue_struct *handle_primary_chan_wq; + struct workqueue_struct *handle_sub_chan_wq; }; diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index 0c51f753652d..d1324d3c72b0 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -869,6 +869,13 @@ struct vmbus_channel { bool probe_done; + /* + * We must offload the handling of the primary/sub channels + * from the single-threaded vmbus_connection.work_queue to + * two different workqueue, otherwise we can block + * vmbus_connection.work_queue and hang: see vmbus_process_offer(). + */ + struct work_struct add_channel_work; }; static inline bool is_hvsock_channel(const struct vmbus_channel *c) -- GitLab From 4f50d3a08df40a3ad261b8527345df92c9f1a731 Mon Sep 17 00:00:00 2001 From: Peter Shih Date: Tue, 27 Nov 2018 12:49:50 +0800 Subject: [PATCH 0430/1286] tty: serial: 8250_mtk: always resume the device in probe. commit 100bc3e2bebf95506da57cbdf5f26b25f6da4c81 upstream. serial8250_register_8250_port calls uart_config_port, which calls config_port on the port before it tries to power on the port. So we need the port to be on before calling serial8250_register_8250_port. Change the code to always do a runtime resume in probe before registering port, and always do a runtime suspend in remove. This basically reverts the change in commit 68e5fc4a255a ("tty: serial: 8250_mtk: use pm_runtime callbacks for enabling"), but still use pm_runtime callbacks. Fixes: 68e5fc4a255a ("tty: serial: 8250_mtk: use pm_runtime callbacks for enabling") Signed-off-by: Peter Shih Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_mtk.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c index fb45770d47aa..fa909fa3c4cd 100644 --- a/drivers/tty/serial/8250/8250_mtk.c +++ b/drivers/tty/serial/8250/8250_mtk.c @@ -222,17 +222,17 @@ static int mtk8250_probe(struct platform_device *pdev) platform_set_drvdata(pdev, data); - pm_runtime_enable(&pdev->dev); - if (!pm_runtime_enabled(&pdev->dev)) { - err = mtk8250_runtime_resume(&pdev->dev); - if (err) - return err; - } + err = mtk8250_runtime_resume(&pdev->dev); + if (err) + return err; data->line = serial8250_register_8250_port(&uart); if (data->line < 0) return data->line; + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + return 0; } @@ -243,13 +243,11 @@ static int mtk8250_remove(struct platform_device *pdev) pm_runtime_get_sync(&pdev->dev); serial8250_unregister_port(data->line); + mtk8250_runtime_suspend(&pdev->dev); pm_runtime_disable(&pdev->dev); pm_runtime_put_noidle(&pdev->dev); - if (!pm_runtime_status_suspended(&pdev->dev)) - mtk8250_runtime_suspend(&pdev->dev); - return 0; } -- GitLab From e4c3cc6b08087550e7f000bd7510ccb9a887c543 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Thu, 22 Nov 2018 18:23:47 +0900 Subject: [PATCH 0431/1286] tty: do not set TTY_IO_ERROR flag if console port commit 2a48602615e0a2f563549c7d5c8d507f904cf96e upstream. Since Commit 761ed4a94582 ('tty: serial_core: convert uart_close to use tty_port_close') and Commit 4dda864d7307 ('tty: serial_core: Fix serial console crash on port shutdown), a serial port which is used as console can be stuck when logging out if there is a remained process. After logged out, agetty will try to grab the serial port but it will be failed because the previous process did not release the port correctly. To fix this, TTY_IO_ERROR bit should not be enabled of tty_port_close if the port is console port. Reproduce step: - Run background processes from serial console $ while true; do sleep 10; done & - Log out $ logout -> Stuck - Read journal log by journalctl | tail Jan 28 16:07:01 ubuntu systemd[1]: Stopped Serial Getty on ttyAMA0. Jan 28 16:07:01 ubuntu systemd[1]: Started Serial Getty on ttyAMA0. Jan 28 16:07:02 ubuntu agetty[1643]: /dev/ttyAMA0: not a tty Fixes: 761ed4a94582 ("tty: serial_core: convert uart_close to use tty_port_close") Cc: Geert Uytterhoeven Cc: Rob Herring Cc: Jiri Slaby Signed-off-by: Chanho Park Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/tty/tty_port.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/tty_port.c b/drivers/tty/tty_port.c index 6b137194069f..c93a33701d32 100644 --- a/drivers/tty/tty_port.c +++ b/drivers/tty/tty_port.c @@ -639,7 +639,8 @@ void tty_port_close(struct tty_port *port, struct tty_struct *tty, if (tty_port_close_start(port, tty, filp) == 0) return; tty_port_shutdown(port, tty); - set_bit(TTY_IO_ERROR, &tty->flags); + if (!port->console) + set_bit(TTY_IO_ERROR, &tty->flags); tty_port_close_end(port, tty); tty_port_tty_set(port, NULL); } -- GitLab From b919b4842b42a148ad12754019c58cfc939ae955 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Wed, 17 Oct 2018 23:08:38 +0800 Subject: [PATCH 0432/1286] kgdboc: fix KASAN global-out-of-bounds bug in param_set_kgdboc_var() commit dada6a43b0402eba438a17ac86fdc64ac56a4607 upstream. This patch is trying to fix KE issue due to "BUG: KASAN: global-out-of-bounds in param_set_kgdboc_var+0x194/0x198" reported by Syzkaller scan." [26364:syz-executor0][name:report8t]BUG: KASAN: global-out-of-bounds in param_set_kgdboc_var+0x194/0x198 [26364:syz-executor0][name:report&]Read of size 1 at addr ffffff900e44f95f by task syz-executor0/26364 [26364:syz-executor0][name:report&] [26364:syz-executor0]CPU: 7 PID: 26364 Comm: syz-executor0 Tainted: G W 0 [26364:syz-executor0]Call trace: [26364:syz-executor0][] dump_bacIctrace+Ox0/0x470 [26364:syz-executor0][] show_stack+0x20/0x30 [26364:syz-executor0][] dump_stack+Oxd8/0x128 [26364:syz-executor0][] print_address_description +0x80/0x4a8 [26364:syz-executor0][] kasan_report+Ox178/0x390 [26364:syz-executor0][] _asan_report_loadi_noabort+Ox18/0x20 [26364:syz-executor0][] param_set_kgdboc_var+Ox194/0x198 [26364:syz-executor0][] param_attr_store+Ox14c/0x270 [26364:syz-executor0][] module_attr_store+0x60/0x90 [26364:syz-executor0][] sysfs_kl_write+Ox100/0x158 [26364:syz-executor0][] kernfs_fop_write+0x27c/0x3a8 [26364:syz-executor0][] do_loop_readv_writev+0x114/0x1b0 [26364:syz-executor0][] do_readv_writev+0x4f8/0x5e0 [26364:syz-executor0][] vfs_writev+0x7c/Oxb8 [26364:syz-executor0][] SyS_writev+Oxcc/0x208 [26364:syz-executor0][] elO_svc_naked +0x24/0x28 [26364:syz-executor0][name:report&] [26364:syz-executor0][name:report&]The buggy address belongs to the variable: [26364:syz-executor0][name:report&] kgdb_tty_line+Ox3f/0x40 [26364:syz-executor0][name:report&] [26364:syz-executor0][name:report&]Memory state around the buggy address: [26364:syz-executor0] ffffff900e44f800: 00 00 00 00 00 04 fa fa fa fa fa fa 00 fa fa fa [26364:syz-executor0] ffffff900e44f880: fa fa fa fa 00 fa fa fa fa fa fa fa 00 fa fa fa [26364:syz-executor0]> ffffff900e44f900: fa fa fa fa 04 fa fa fa fa fa fa fa 00 00 00 00 [26364:syz-executor0][name:report&] ^ [26364:syz-executor0] ffffff900e44f980: 00 fa fa fa fa fa fa fa 04 fa fa fa fa fa fa fa [26364:syz-executor0] ffffff900e44fa00: 04 fa fa fa fa fa fa fa 00 fa fa fa fa fa fa fa [26364:syz-executor0][name:report&] [26364:syz-executor0][name:panic&]Disabling lock debugging due to kernel taint [26364:syz-executor0]------------[cut here]------------ After checking the source code, we've found there might be an out-of-bounds access to "config[len - 1]" array when the variable "len" is zero. Signed-off-by: Macpaul Lin Acked-by: Daniel Thompson Cc: stable Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/kgdboc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c index c448225ef5ca..f2b0d8cee8ef 100644 --- a/drivers/tty/serial/kgdboc.c +++ b/drivers/tty/serial/kgdboc.c @@ -232,7 +232,7 @@ static void kgdboc_put_char(u8 chr) static int param_set_kgdboc_var(const char *kmessage, struct kernel_param *kp) { - int len = strlen(kmessage); + size_t len = strlen(kmessage); if (len >= MAX_CONFIG_LEN) { printk(KERN_ERR "kgdboc: config string too long\n"); @@ -254,7 +254,7 @@ static int param_set_kgdboc_var(const char *kmessage, struct kernel_param *kp) strcpy(config, kmessage); /* Chop out \n char as a result of echo */ - if (config[len - 1] == '\n') + if (len && config[len - 1] == '\n') config[len - 1] = '\0'; if (configured == 1) -- GitLab From 4794d94b44c4903514a878b9097e99417a5e6dbe Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 24 Nov 2018 10:47:04 -0800 Subject: [PATCH 0433/1286] libnvdimm, pfn: Pad pfn namespaces relative to other regions commit ae86cbfef3818300f1972e52f67a93211acb0e24 upstream. Commit cfe30b872058 "libnvdimm, pmem: adjust for section collisions with 'System RAM'" enabled Linux to workaround occasions where platform firmware arranges for "System RAM" and "Persistent Memory" to collide within a single section boundary. Unfortunately, as reported in this issue [1], platform firmware can inflict the same collision between persistent memory regions. The approach of interrogating iomem_resource does not work in this case because platform firmware may merge multiple regions into a single iomem_resource range. Instead provide a method to interrogate regions that share the same parent bus. This is a stop-gap until the core-MM can grow support for hotplug on sub-section boundaries. [1]: https://github.com/pmem/ndctl/issues/76 Fixes: cfe30b872058 ("libnvdimm, pmem: adjust for section collisions with...") Cc: Reported-by: Patrick Geary Tested-by: Patrick Geary Reviewed-by: Vishal Verma Signed-off-by: Dan Williams Signed-off-by: Greg Kroah-Hartman --- drivers/nvdimm/nd-core.h | 2 ++ drivers/nvdimm/pfn_devs.c | 64 +++++++++++++++++++++--------------- drivers/nvdimm/region_devs.c | 41 +++++++++++++++++++++++ 3 files changed, 80 insertions(+), 27 deletions(-) diff --git a/drivers/nvdimm/nd-core.h b/drivers/nvdimm/nd-core.h index 86bc19ae30da..f7b0c39ac339 100644 --- a/drivers/nvdimm/nd-core.h +++ b/drivers/nvdimm/nd-core.h @@ -105,6 +105,8 @@ resource_size_t nd_pmem_available_dpa(struct nd_region *nd_region, struct nd_mapping *nd_mapping, resource_size_t *overlap); resource_size_t nd_blk_available_dpa(struct nd_region *nd_region); resource_size_t nd_region_available_dpa(struct nd_region *nd_region); +int nd_region_conflict(struct nd_region *nd_region, resource_size_t start, + resource_size_t size); resource_size_t nvdimm_allocated_dpa(struct nvdimm_drvdata *ndd, struct nd_label_id *label_id); int alias_dpa_busy(struct device *dev, void *data); diff --git a/drivers/nvdimm/pfn_devs.c b/drivers/nvdimm/pfn_devs.c index 2adada1a5855..6d38191ff0da 100644 --- a/drivers/nvdimm/pfn_devs.c +++ b/drivers/nvdimm/pfn_devs.c @@ -589,14 +589,47 @@ static u64 phys_pmem_align_down(struct nd_pfn *nd_pfn, u64 phys) ALIGN_DOWN(phys, nd_pfn->align)); } +/* + * Check if pmem collides with 'System RAM', or other regions when + * section aligned. Trim it accordingly. + */ +static void trim_pfn_device(struct nd_pfn *nd_pfn, u32 *start_pad, u32 *end_trunc) +{ + struct nd_namespace_common *ndns = nd_pfn->ndns; + struct nd_namespace_io *nsio = to_nd_namespace_io(&ndns->dev); + struct nd_region *nd_region = to_nd_region(nd_pfn->dev.parent); + const resource_size_t start = nsio->res.start; + const resource_size_t end = start + resource_size(&nsio->res); + resource_size_t adjust, size; + + *start_pad = 0; + *end_trunc = 0; + + adjust = start - PHYS_SECTION_ALIGN_DOWN(start); + size = resource_size(&nsio->res) + adjust; + if (region_intersects(start - adjust, size, IORESOURCE_SYSTEM_RAM, + IORES_DESC_NONE) == REGION_MIXED + || nd_region_conflict(nd_region, start - adjust, size)) + *start_pad = PHYS_SECTION_ALIGN_UP(start) - start; + + /* Now check that end of the range does not collide. */ + adjust = PHYS_SECTION_ALIGN_UP(end) - end; + size = resource_size(&nsio->res) + adjust; + if (region_intersects(start, size, IORESOURCE_SYSTEM_RAM, + IORES_DESC_NONE) == REGION_MIXED + || !IS_ALIGNED(end, nd_pfn->align) + || nd_region_conflict(nd_region, start, size + adjust)) + *end_trunc = end - phys_pmem_align_down(nd_pfn, end); +} + static int nd_pfn_init(struct nd_pfn *nd_pfn) { u32 dax_label_reserve = is_nd_dax(&nd_pfn->dev) ? SZ_128K : 0; struct nd_namespace_common *ndns = nd_pfn->ndns; - u32 start_pad = 0, end_trunc = 0; + struct nd_namespace_io *nsio = to_nd_namespace_io(&ndns->dev); resource_size_t start, size; - struct nd_namespace_io *nsio; struct nd_region *nd_region; + u32 start_pad, end_trunc; struct nd_pfn_sb *pfn_sb; unsigned long npfns; phys_addr_t offset; @@ -628,30 +661,7 @@ static int nd_pfn_init(struct nd_pfn *nd_pfn) memset(pfn_sb, 0, sizeof(*pfn_sb)); - /* - * Check if pmem collides with 'System RAM' when section aligned and - * trim it accordingly - */ - nsio = to_nd_namespace_io(&ndns->dev); - start = PHYS_SECTION_ALIGN_DOWN(nsio->res.start); - size = resource_size(&nsio->res); - if (region_intersects(start, size, IORESOURCE_SYSTEM_RAM, - IORES_DESC_NONE) == REGION_MIXED) { - start = nsio->res.start; - start_pad = PHYS_SECTION_ALIGN_UP(start) - start; - } - - start = nsio->res.start; - size = PHYS_SECTION_ALIGN_UP(start + size) - start; - if (region_intersects(start, size, IORESOURCE_SYSTEM_RAM, - IORES_DESC_NONE) == REGION_MIXED - || !IS_ALIGNED(start + resource_size(&nsio->res), - nd_pfn->align)) { - size = resource_size(&nsio->res); - end_trunc = start + size - phys_pmem_align_down(nd_pfn, - start + size); - } - + trim_pfn_device(nd_pfn, &start_pad, &end_trunc); if (start_pad + end_trunc) dev_info(&nd_pfn->dev, "%s alignment collision, truncate %d bytes\n", dev_name(&ndns->dev), start_pad + end_trunc); @@ -662,7 +672,7 @@ static int nd_pfn_init(struct nd_pfn *nd_pfn) * implementation will limit the pfns advertised through * ->direct_access() to those that are included in the memmap. */ - start += start_pad; + start = nsio->res.start + start_pad; size = resource_size(&nsio->res); npfns = PFN_SECTION_ALIGN_UP((size - start_pad - end_trunc - SZ_8K) / PAGE_SIZE); diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index 050deb56ee62..708043d20d0d 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -1112,6 +1112,47 @@ int nvdimm_has_cache(struct nd_region *nd_region) } EXPORT_SYMBOL_GPL(nvdimm_has_cache); +struct conflict_context { + struct nd_region *nd_region; + resource_size_t start, size; +}; + +static int region_conflict(struct device *dev, void *data) +{ + struct nd_region *nd_region; + struct conflict_context *ctx = data; + resource_size_t res_end, region_end, region_start; + + if (!is_memory(dev)) + return 0; + + nd_region = to_nd_region(dev); + if (nd_region == ctx->nd_region) + return 0; + + res_end = ctx->start + ctx->size; + region_start = nd_region->ndr_start; + region_end = region_start + nd_region->ndr_size; + if (ctx->start >= region_start && ctx->start < region_end) + return -EBUSY; + if (res_end > region_start && res_end <= region_end) + return -EBUSY; + return 0; +} + +int nd_region_conflict(struct nd_region *nd_region, resource_size_t start, + resource_size_t size) +{ + struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(&nd_region->dev); + struct conflict_context ctx = { + .nd_region = nd_region, + .start = start, + .size = size, + }; + + return device_for_each_child(&nvdimm_bus->dev, &ctx, region_conflict); +} + void __exit nd_region_devs_exit(void) { ida_destroy(®ion_ida); -- GitLab From 199a81acf2bb66b5a640e6484aacd87bdd2a4854 Mon Sep 17 00:00:00 2001 From: Vasyl Vavrychuk Date: Thu, 18 Oct 2018 01:02:12 +0300 Subject: [PATCH 0434/1286] mac80211_hwsim: Timer should be initialized before device registered commit a1881c9b8a1edef0a5ae1d5c1b61406fe3402114 upstream. Otherwise if network manager starts configuring Wi-Fi interface immidiatelly after getting notification of its creation, we will get NULL pointer dereference: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [] hrtimer_active+0x28/0x50 ... Call Trace: [] ? hrtimer_try_to_cancel+0x27/0x110 [] ? hrtimer_cancel+0x15/0x20 [] ? mac80211_hwsim_config+0x140/0x1c0 [mac80211_hwsim] Cc: stable@vger.kernel.org Signed-off-by: Vasyl Vavrychuk Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/mac80211_hwsim.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 477f9f2f6626..670224be3c8b 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -2698,6 +2698,10 @@ static int mac80211_hwsim_new_radio(struct genl_info *info, wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); + tasklet_hrtimer_init(&data->beacon_timer, + mac80211_hwsim_beacon, + CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + err = ieee80211_register_hw(hw); if (err < 0) { printk(KERN_DEBUG "mac80211_hwsim: ieee80211_register_hw failed (%d)\n", @@ -2722,10 +2726,6 @@ static int mac80211_hwsim_new_radio(struct genl_info *info, data->debugfs, data, &hwsim_simulate_radar); - tasklet_hrtimer_init(&data->beacon_timer, - mac80211_hwsim_beacon, - CLOCK_MONOTONIC, HRTIMER_MODE_ABS); - spin_lock_bh(&hwsim_radio_lock); list_add_tail(&data->list, &hwsim_radios); spin_unlock_bh(&hwsim_radio_lock); -- GitLab From 9e82abdd0c0341b880f510fc8b19464410912069 Mon Sep 17 00:00:00 2001 From: Ben Greear Date: Tue, 23 Oct 2018 13:36:52 -0700 Subject: [PATCH 0435/1286] mac80211: Clear beacon_int in ieee80211_do_stop commit 5c21e8100dfd57c806e833ae905e26efbb87840f upstream. This fixes stale beacon-int values that would keep a netdev from going up. To reproduce: Create two VAP on one radio. vap1 has beacon-int 100, start it. vap2 has beacon-int 240, start it (and it will fail because beacon-int mismatch). reconfigure vap2 to have beacon-int 100 and start it. It will fail because the stale beacon-int 240 will be used in the ifup path and hostapd never gets a chance to set the new beacon interval. Cc: stable@vger.kernel.org Signed-off-by: Ben Greear Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/mac80211/iface.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c index e4912858b72c..222c063244f5 100644 --- a/net/mac80211/iface.c +++ b/net/mac80211/iface.c @@ -1032,6 +1032,8 @@ static void ieee80211_do_stop(struct ieee80211_sub_if_data *sdata, if (local->open_count == 0) ieee80211_clear_tx_pending(local); + sdata->vif.bss_conf.beacon_int = 0; + /* * If the interface goes down while suspended, presumably because * the device was unplugged and that happens before our resume, -- GitLab From a2c934fbbd43b5c349157c05374b9598f53a65f1 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 13 Nov 2018 20:32:13 +0100 Subject: [PATCH 0436/1286] mac80211: ignore tx status for PS stations in ieee80211_tx_status_ext commit a317e65face482371de30246b6494feb093ff7f9 upstream. Make it behave like regular ieee80211_tx_status calls, except for the lack of filtered frame processing. This fixes spurious low-ack triggered disconnections with powersave clients connected to an AP. Fixes: f027c2aca0cf4 ("mac80211: add ieee80211_tx_status_noskb") Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/mac80211/status.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/mac80211/status.c b/net/mac80211/status.c index bdf131ed5ce8..35912270087c 100644 --- a/net/mac80211/status.c +++ b/net/mac80211/status.c @@ -953,6 +953,8 @@ void ieee80211_tx_status_ext(struct ieee80211_hw *hw, /* Track when last TDLS packet was ACKed */ if (test_sta_flag(sta, WLAN_STA_TDLS_PEER_AUTH)) sta->status_stats.last_tdls_pkt_time = jiffies; + } else if (test_sta_flag(sta, WLAN_STA_PS_STA)) { + return; } else { ieee80211_lost_packet(sta, info); } -- GitLab From bbc4242a9c2e3c97a5a8e7822b9c27915599f0c4 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 28 Nov 2018 22:39:16 +0100 Subject: [PATCH 0437/1286] mac80211: fix reordering of buffered broadcast packets commit 9ec1190d065998650fd9260dea8cf3e1f56c0e8c upstream. If the buffered broadcast queue contains packets, letting new packets bypass that queue can lead to heavy reordering, since the driver is probably throttling transmission of buffered multicast packets after beacons. Keep buffering packets until the buffer has been cleared (and no client is in powersave mode). Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/mac80211/tx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index a17a56032a21..6b9bf9c027a2 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c @@ -435,8 +435,8 @@ ieee80211_tx_h_multicast_ps_buf(struct ieee80211_tx_data *tx) if (ieee80211_hw_check(&tx->local->hw, QUEUE_CONTROL)) info->hw_queue = tx->sdata->vif.cab_queue; - /* no stations in PS mode */ - if (!atomic_read(&ps->num_sta_ps)) + /* no stations in PS mode and no buffered packets */ + if (!atomic_read(&ps->num_sta_ps) && skb_queue_empty(&ps->bc_buf)) return TX_CONTINUE; info->flags |= IEEE80211_TX_CTL_SEND_AFTER_DTIM; -- GitLab From 7b6d932725ec18c1d84892b73c9da4d624939955 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Mon, 3 Dec 2018 21:16:07 +0200 Subject: [PATCH 0438/1286] mac80211: ignore NullFunc frames in the duplicate detection commit 990d71846a0b7281bd933c34d734e6afc7408e7e upstream. NullFunc packets should never be duplicate just like QoS-NullFunc packets. We saw a client that enters / exits power save with NullFunc frames (and not with QoS-NullFunc) despite the fact that the association supports HT. This specific client also re-uses a non-zero sequence number for different NullFunc frames. At some point, the client had to send a retransmission of the NullFunc frame and we dropped it, leading to a misalignment in the power save state. Fix this by never consider a NullFunc frame as duplicate, just like we do for QoS NullFunc frames. This fixes https://bugzilla.kernel.org/show_bug.cgi?id=201449 CC: Signed-off-by: Emmanuel Grumbach Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/mac80211/rx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index dddd498e1338..9e19ddbcb06e 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c @@ -1254,6 +1254,7 @@ ieee80211_rx_h_check_dup(struct ieee80211_rx_data *rx) return RX_CONTINUE; if (ieee80211_is_ctl(hdr->frame_control) || + ieee80211_is_nullfunc(hdr->frame_control) || ieee80211_is_qos_nullfunc(hdr->frame_control) || is_multicast_ether_addr(hdr->addr1)) return RX_CONTINUE; -- GitLab From 1bb538a39cf959009d4e424ea4e590a1f58b2ed6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 13 Dec 2018 09:18:54 +0100 Subject: [PATCH 0439/1286] Linux 4.14.88 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 322484348f3e..3fdee40861a1 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 87 +SUBLEVEL = 88 EXTRAVERSION = NAME = Petit Gorille -- GitLab From a5551d2b06c491f2b78687f2ad6f707e4f98eb5f Mon Sep 17 00:00:00 2001 From: Liam Mark Date: Mon, 10 Dec 2018 10:26:17 -0800 Subject: [PATCH 0440/1286] Revert "pagemap.h: Allow readahead Movable allocations from CMA region" This reverts commit aae482fcb11e ("pagemap.h: Allow readahead Movable allocations from CMA region") This change was added in order to improve the memory utilization of the Movable zone in targets with large Movable zones. Unfortunately it was found that adding file cache pages to the Movable zone can sometimes significantly reduce the memory headroom of the device. What can happen is that when the system gets under memory pressure it runs kswapd, which uses a gfp mask of GFP_KERNEL. When the low memory killer shrinker is called on behalf of kswapd with a gfp mask of GFP_KERNEL it will ignore all free and reclaimable memory, such as the file cache pages, that are located in the Movable zone. This can cause the low memory killer to kill applications prematurely. There are potential changes which could be made to optimize the system to address the issue described above, however these changes are intrusive and potentially risky. Since we aren't currently running with a large Movable zone and because we don't want to introduce any potentially risky changes this late in the development cycle revert this change for now. If in the future we want to re-visit improving the utilization of the Movable zone we can pull this change back in and attempt to optimize the memory reclaim framework to avoid the issues described above. Change-Id: Icaeea4db60a8d538348a63b76b5e176ba69dfd0d Signed-off-by: Liam Mark --- include/linux/pagemap.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h index eb69f32542ba..51a9a0af3281 100644 --- a/include/linux/pagemap.h +++ b/include/linux/pagemap.h @@ -239,13 +239,8 @@ static inline struct page *page_cache_alloc_cold(struct address_space *x) static inline gfp_t readahead_gfp_mask(struct address_space *x) { - gfp_t gfp_mask = mapping_gfp_mask(x) | - __GFP_COLD | __GFP_NORETRY | __GFP_NOWARN; - - if (gfp_mask & __GFP_MOVABLE) - gfp_mask |= __GFP_CMA; - - return gfp_mask; + return mapping_gfp_mask(x) | + __GFP_COLD | __GFP_NORETRY | __GFP_NOWARN; } typedef int filler_t(struct file *, struct page *); -- GitLab From 313a025f2d0b45a7d74e7b273923942415c413ca Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 3 Dec 2018 10:58:20 -0700 Subject: [PATCH 0441/1286] msm: kgsl: Try to improve coresight register accesses Instead of having if / else statements scattered throughout the coresight driver to access GX or CX register banks use function hooks in the target specific coresight structs. This helps streamline the code and cut down on the decision points at the cost of just a bit more infrastructure on the target side. Change-Id: Ic0dedbada9d1632d220d0dfb186ccd0adff6be91 Signed-off-by: Jordan Crouse --- drivers/gpu/msm/adreno.h | 16 +++++++--- drivers/gpu/msm/adreno_a3xx.c | 2 ++ drivers/gpu/msm/adreno_a4xx.c | 2 ++ drivers/gpu/msm/adreno_a5xx.c | 2 ++ drivers/gpu/msm/adreno_a6xx.c | 4 +++ drivers/gpu/msm/adreno_coresight.c | 47 +++++++++--------------------- 6 files changed, 35 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 5cf6ec541c1c..c51c19f8b3ca 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -868,16 +868,24 @@ ssize_t adreno_coresight_store_register(struct device *dev, /** * struct adreno_coresight - GPU specific coresight definition - * @registers - Array of GPU specific registers to configure trace bus output - * @count - Number of registers in the array - * @groups - Pointer to an attribute list of control files - * @atid - The unique ATID value of the coresight device + * @registers: Array of GPU specific registers to configure trace bus output + * @count: Number of registers in the array + * @groups: Pointer to an attribute list of control files + * @atid: The unique ATID value of the coresight device + * @read: a function pointer to the appropriate register read function for this + * device + * @write: a function pointer to the appropriate register write function for + * this device */ struct adreno_coresight { struct adreno_coresight_register *registers; unsigned int count; const struct attribute_group **groups; unsigned int atid; + void (*read)(struct kgsl_device *device, + unsigned int offsetwords, unsigned int *value); + void (*write)(struct kgsl_device *device, + unsigned int offsetwords, unsigned int value); }; diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c index 25909776d4b0..ae5c055e9ae6 100644 --- a/drivers/gpu/msm/adreno_a3xx.c +++ b/drivers/gpu/msm/adreno_a3xx.c @@ -1467,6 +1467,8 @@ static struct adreno_coresight a3xx_coresight = { .registers = a3xx_coresight_registers, .count = ARRAY_SIZE(a3xx_coresight_registers), .groups = a3xx_coresight_groups, + .read = kgsl_regread, + .write = kgsl_regwrite, }; static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = { diff --git a/drivers/gpu/msm/adreno_a4xx.c b/drivers/gpu/msm/adreno_a4xx.c index 432e98dbed94..931551f4776c 100644 --- a/drivers/gpu/msm/adreno_a4xx.c +++ b/drivers/gpu/msm/adreno_a4xx.c @@ -1680,6 +1680,8 @@ static struct adreno_coresight a4xx_coresight = { .registers = a4xx_coresight_registers, .count = ARRAY_SIZE(a4xx_coresight_registers), .groups = a4xx_coresight_groups, + .read = kgsl_regread, + .write = kgsl_regwrite, }; static void a4xx_preempt_callback(struct adreno_device *adreno_dev, int bit) diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 44a7c39f7e13..032cd3498655 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -3596,6 +3596,8 @@ static struct adreno_coresight a5xx_coresight = { .registers = a5xx_coresight_registers, .count = ARRAY_SIZE(a5xx_coresight_registers), .groups = a5xx_coresight_groups, + .read = kgsl_regread, + .write = kgsl_regwrite, }; struct adreno_gpudev adreno_a5xx_gpudev = { diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index b20595a8e584..cc1ea393a3af 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -2190,12 +2190,16 @@ static struct adreno_coresight a6xx_coresight = { .registers = a6xx_coresight_regs, .count = ARRAY_SIZE(a6xx_coresight_regs), .groups = a6xx_coresight_groups, + .read = kgsl_regread, + .write = kgsl_regwrite, }; static struct adreno_coresight a6xx_coresight_cx = { .registers = a6xx_coresight_regs_cx, .count = ARRAY_SIZE(a6xx_coresight_regs_cx), .groups = a6xx_coresight_groups_cx, + .read = adreno_cx_dbgc_regread, + .write = adreno_cx_dbgc_regwrite, }; static struct adreno_perfcount_register a6xx_perfcounters_cp[] = { diff --git a/drivers/gpu/msm/adreno_coresight.c b/drivers/gpu/msm/adreno_coresight.c index ef482a26f2a5..5eff50df196f 100644 --- a/drivers/gpu/msm/adreno_coresight.c +++ b/drivers/gpu/msm/adreno_coresight.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -175,14 +175,9 @@ static void adreno_coresight_disable(struct coresight_device *csdev, mutex_lock(&device->mutex); if (!kgsl_active_count_get(device)) { - if (cs_id == GPU_CORESIGHT_GX) - for (i = 0; i < coresight->count; i++) - kgsl_regwrite(device, - coresight->registers[i].offset, 0); - else if (cs_id == GPU_CORESIGHT_CX) - for (i = 0; i < coresight->count; i++) - adreno_cx_dbgc_regwrite(device, - coresight->registers[i].offset, 0); + for (i = 0; i < coresight->count; i++) + coresight->write(device, + coresight->registers[i].offset, 0); kgsl_active_count_put(device); } @@ -210,25 +205,15 @@ static int _adreno_coresight_get_and_clear(struct adreno_device *adreno_dev, return -ENODEV; kgsl_pre_hwaccess(device); + /* * Save the current value of each coresight register * and then clear each register */ - if (cs_id == GPU_CORESIGHT_GX) { - for (i = 0; i < coresight->count; i++) { - kgsl_regread(device, coresight->registers[i].offset, - &coresight->registers[i].value); - kgsl_regwrite(device, coresight->registers[i].offset, - 0); - } - } else if (cs_id == GPU_CORESIGHT_CX) { - for (i = 0; i < coresight->count; i++) { - adreno_cx_dbgc_regread(device, - coresight->registers[i].offset, - &coresight->registers[i].value); - adreno_cx_dbgc_regwrite(device, - coresight->registers[i].offset, 0); - } + for (i = 0; i < coresight->count; i++) { + coresight->read(device, coresight->registers[i].offset, + &coresight->registers[i].value); + coresight->write(device, coresight->registers[i].offset, 0); } return 0; @@ -244,16 +229,10 @@ static int _adreno_coresight_set(struct adreno_device *adreno_dev, int cs_id) if (coresight == NULL) return -ENODEV; - if (cs_id == GPU_CORESIGHT_GX) { - for (i = 0; i < coresight->count; i++) - kgsl_regwrite(device, coresight->registers[i].offset, - coresight->registers[i].value); - } else if (cs_id == GPU_CORESIGHT_CX) { - for (i = 0; i < coresight->count; i++) - adreno_cx_dbgc_regwrite(device, - coresight->registers[i].offset, - coresight->registers[i].value); - } + for (i = 0; i < coresight->count; i++) + coresight->write(device, coresight->registers[i].offset, + coresight->registers[i].value); + return 0; } /** -- GitLab From 75e5937f9ab77062654ba34951db69f6041f54f1 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 26 Nov 2018 16:14:07 -0800 Subject: [PATCH 0442/1286] dt-bindings: msi: add Synopsys devicetree entry To use Synopsys MSI, users must add qcom,snps to MSI devicetree node, otherwise QGIC MSI will be supported. Change-Id: I5aed9412387c0eb5d9c56bc739fedf156a14f958 Signed-off-by: Tony Truong --- .../devicetree/bindings/pci/msm_pcie_msi.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/msm_pcie_msi.txt b/Documentation/devicetree/bindings/pci/msm_pcie_msi.txt index 032db9379152..8150ab8f2065 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie_msi.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie_msi.txt @@ -26,9 +26,15 @@ Value type: Definition: Array of tuples which describe interrupt lines for PCIe MSI +-qcom,snps: + Usage: optional + Value type: + Definition: Set if interrupt controller is Synopsys instead of QGIC + ======= Example ======= +/* QGIC */ pci_msi: qcom,pci_msi { compatible = "qcom,pci-msi"; msi-controller; @@ -67,3 +73,13 @@ pci_msi: qcom,pci_msi { , ; }; + +/* Synopsys */ +pci_msi: qcom,pci_msi { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; +}; -- GitLab From 7391e889fa2b6dec42f01ec917fc73cf0a72855e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 15 Nov 2018 16:51:16 -0800 Subject: [PATCH 0443/1286] msm: msi: add Synopsys MSI support In addition to QGIC MSI, Synopsys PCIe core support MSI internally. Add the support to configure, enable, and maintain interrupts for Synopsys MSI. Change-Id: Ie5ab408123d12e8ee4ad3685d9a5bfb537e2e879 Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm-msi.c | 235 +++++++++++++++++++++++++++------ include/linux/msm_pcie.h | 5 + 2 files changed, 198 insertions(+), 42 deletions(-) diff --git a/drivers/pci/host/pci-msm-msi.c b/drivers/pci/host/pci-msm-msi.c index f98a06911496..16713d122b85 100644 --- a/drivers/pci/host/pci-msm-msi.c +++ b/drivers/pci/host/pci-msm-msi.c @@ -24,23 +24,52 @@ #include #include #include +#include + +#define PCIE_MSI_CTRL_BASE (0x820) +#define PCIE_MSI_CTRL_ADDR_OFFS (PCIE_MSI_CTRL_BASE) +#define PCIE_MSI_CTRL_UPPER_ADDR_OFFS (PCIE_MSI_CTRL_BASE + 0x4) +#define PCIE_MSI_CTRL_INT_N_EN_OFFS(n) (PCIE_MSI_CTRL_BASE + 0x8 + 0xc * n) +#define PCIE_MSI_CTRL_INT_N_STATUS_OFFS(n) (PCIE_MSI_CTRL_BASE + 0x10 + 0xc * n) + +#define MSI_IRQ_NR_GRP (1) +#define MSI_IRQ_PER_GRP (32) + +enum msi_type { + MSM_MSI_TYPE_QCOM, + MSM_MSI_TYPE_SNPS, +}; struct msm_msi_irq { + struct msm_msi_client *client; unsigned int hwirq; /* MSI controller hwirq */ unsigned int virq; /* MSI controller virq */ + u32 pos; /* position in MSI bitmap */ +}; + +struct msm_msi_grp { + /* registers for SNPS only */ + void __iomem *int_en_reg; + void __iomem *int_status_reg; + + struct msm_msi_irq irqs[MSI_IRQ_PER_GRP]; }; struct msm_msi { struct list_head clients; struct device *dev; struct device_node *of_node; - int nr_irqs; - struct msm_msi_irq *irqs; + int nr_hwirqs; + int nr_virqs; + int nr_grps; + struct msm_msi_grp *grps; unsigned long *bitmap; /* tracks used/unused MSI */ struct mutex mutex; /* mutex for modifying MSI client list and bitmap */ struct irq_domain *inner_domain; /* parent domain; gen irq related */ struct irq_domain *msi_domain; /* child domain; pci related */ phys_addr_t msi_addr; + enum msi_type type; + void __iomem *pcie_cfg; }; /* structure for each client of MSI controller */ @@ -52,7 +81,33 @@ struct msm_msi_client { dma_addr_t msi_addr; }; -static void msm_msi_handler(struct irq_desc *desc) +static void msm_msi_snps_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct msm_msi *msi; + struct msm_msi_grp *msi_grp; + unsigned long val = 0; + u32 index; + int i; + + chained_irq_enter(chip, desc); + + msi = irq_desc_get_handler_data(desc); + + for (i = 0; i < msi->nr_grps; i++) { + msi_grp = &msi->grps[i]; + val = readl_relaxed(msi_grp->int_status_reg); + writel_relaxed(val, msi_grp->int_status_reg); + + for (index = 0; val; index++, val >>= 1) + if (val & 0x1) + generic_handle_irq(msi_grp->irqs[index].virq); + } + + chained_irq_exit(chip, desc); +} + +static void msm_msi_qgic_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct msm_msi *msi; @@ -86,12 +141,21 @@ static int msm_msi_domain_prepare(struct irq_domain *domain, struct device *dev, client->msi = msi; client->dev = dev; - client->msi_addr = dma_map_resource(client->dev, msi->msi_addr, - PAGE_SIZE, DMA_FROM_DEVICE, 0); - if (dma_mapping_error(client->dev, client->msi_addr)) { - dev_err(msi->dev, "MSI: failed to map msi address\n"); - client->msi_addr = 0; - return -ENOMEM; + client->msi_addr = msi->msi_addr; + + /* + * Accesses to QGIC MSI doorbell register goes through PCIe SMMU and + * needs to be mapped. Synopsys MSI doorbell is within the PCIe core + * and does not need to be mapped. + */ + if (msi->type == MSM_MSI_TYPE_QCOM) { + client->msi_addr = dma_map_resource(client->dev, msi->msi_addr, + PAGE_SIZE, DMA_FROM_DEVICE, 0); + if (dma_mapping_error(client->dev, client->msi_addr)) { + dev_err(msi->dev, "MSI: failed to map msi address\n"); + client->msi_addr = 0; + return -ENOMEM; + } } mutex_lock(&msi->mutex); @@ -127,7 +191,7 @@ void msm_msi_domain_finish(msi_alloc_info_t *arg, int retval) if (!client) return; - if (client->msi_addr) + if ((msi->type == MSM_MSI_TYPE_QCOM) && client->msi_addr) dma_unmap_resource(client->dev, client->msi_addr, PAGE_SIZE, DMA_FROM_DEVICE, 0); @@ -168,8 +232,10 @@ static int msm_msi_irq_set_affinity(struct irq_data *data, static void msm_msi_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct msm_msi_client *client = irq_data_get_irq_chip_data(data); + struct msm_msi_irq *msi_irq = irq_data_get_irq_chip_data(data); struct irq_data *parent_data = irq_get_irq_data(irqd_to_hwirq(data)); + struct msm_msi_client *client = msi_irq->client; + struct msm_msi *msi = client->msi; if (!parent_data) return; @@ -177,8 +243,8 @@ static void msm_msi_irq_compose_msi_msg(struct irq_data *data, msg->address_lo = lower_32_bits(client->msi_addr); msg->address_hi = upper_32_bits(client->msi_addr); - /* GIC HW IRQ */ - msg->data = irqd_to_hwirq(parent_data); + msg->data = (msi->type == MSM_MSI_TYPE_QCOM) ? + irqd_to_hwirq(parent_data) : msi_irq->pos; } static struct irq_chip msm_msi_bottom_irq_chip = { @@ -211,9 +277,9 @@ static int msm_msi_irq_domain_alloc(struct irq_domain *domain, goto out; } - pos = bitmap_find_next_zero_area(msi->bitmap, msi->nr_irqs, 0, + pos = bitmap_find_next_zero_area(msi->bitmap, msi->nr_virqs, 0, nr_irqs, 0); - if (pos < msi->nr_irqs) { + if (pos < msi->nr_virqs) { bitmap_set(msi->bitmap, pos, nr_irqs); } else { ret = -ENOSPC; @@ -221,15 +287,19 @@ static int msm_msi_irq_domain_alloc(struct irq_domain *domain, } for (i = 0; i < nr_irqs; i++) { - msi->irqs[pos].virq = virq + i; - irq_domain_set_info(domain, msi->irqs[pos].virq, - msi->irqs[pos].hwirq, - &msm_msi_bottom_irq_chip, client, + u32 grp = pos / MSI_IRQ_PER_GRP; + u32 index = pos % MSI_IRQ_PER_GRP; + struct msm_msi_irq *msi_irq = &msi->grps[grp].irqs[index]; + + msi_irq->virq = virq + i; + msi_irq->client = client; + irq_domain_set_info(domain, msi_irq->virq, + msi_irq->hwirq, + &msm_msi_bottom_irq_chip, msi_irq, handle_simple_irq, NULL, NULL); client->nr_irqs++; pos++; } - out: mutex_unlock(&msi->mutex); return ret; @@ -239,27 +309,26 @@ static void msm_msi_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *data = irq_domain_get_irq_data(domain, virq); + struct msm_msi_irq *msi_irq; struct msm_msi_client *client; struct msm_msi *msi; - int i; if (!data) return; - client = irq_data_get_irq_chip_data(data); + msi_irq = irq_data_get_irq_chip_data(data); + client = msi_irq->client; msi = client->msi; mutex_lock(&msi->mutex); - for (i = 0; i < nr_irqs; i++) - if (msi->irqs[i].virq == virq) - break; - bitmap_clear(msi->bitmap, i, nr_irqs); + bitmap_clear(msi->bitmap, msi_irq->pos, nr_irqs); client->nr_irqs -= nr_irqs; if (!client->nr_irqs) { - dma_unmap_resource(client->dev, client->msi_addr, PAGE_SIZE, - DMA_FROM_DEVICE, 0); + if (msi->type == MSM_MSI_TYPE_QCOM) + dma_unmap_resource(client->dev, client->msi_addr, + PAGE_SIZE, DMA_FROM_DEVICE, 0); list_del(&client->node); devm_kfree(msi->dev, client); } @@ -276,7 +345,7 @@ static const struct irq_domain_ops msi_domain_ops = { static int msm_msi_alloc_domains(struct msm_msi *msi) { - msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_irqs, + msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_virqs, &msi_domain_ops, msi); if (!msi->inner_domain) { dev_err(msi->dev, "MSI: failed to create IRQ domain\n"); @@ -296,12 +365,36 @@ static int msm_msi_alloc_domains(struct msm_msi *msi) return 0; } +/* configure Synopsys PCIe MSI registers */ +void msm_msi_config(struct irq_domain *domain) +{ + struct msm_msi *msi; + int i; + + msi = domain->parent->host_data; + if (msi->type == MSM_MSI_TYPE_QCOM) + return; + + /* program MSI termination address */ + writel_relaxed(msi->msi_addr, msi->pcie_cfg + PCIE_MSI_CTRL_ADDR_OFFS); + writel_relaxed(0, msi->pcie_cfg + PCIE_MSI_CTRL_UPPER_ADDR_OFFS); + + /* enable all interrupts for each group */ + for (i = 0; i < msi->nr_grps; i++) + writel_relaxed(~0, msi->grps[i].int_en_reg); +} +EXPORT_SYMBOL(msm_msi_config); + int msm_msi_init(struct device *dev) { int i, ret; struct msm_msi *msi; struct device_node *of_node; const __be32 *prop_val; + struct resource *res; + void (*msi_handler)(struct irq_desc *); + u32 grp; + u32 index; if (!dev->of_node) { dev_err(dev, "MSI: missing DT node\n"); @@ -343,18 +436,46 @@ int msm_msi_init(struct device *dev) return -EINVAL; } - msi->nr_irqs = of_irq_count(msi->of_node); - if (!msi->nr_irqs) { + msi->type = of_property_read_bool(msi->of_node, "qcom,snps") ? + MSM_MSI_TYPE_SNPS : MSM_MSI_TYPE_QCOM; + dev_info(msi->dev, "MSI: %s controller is present\n", + msi->type == MSM_MSI_TYPE_SNPS ? "synopsys" : "qgic"); + + msi->nr_hwirqs = of_irq_count(msi->of_node); + if (!msi->nr_hwirqs) { dev_err(msi->dev, "MSI: found no MSI interrupts\n"); return -ENODEV; } - msi->irqs = devm_kcalloc(msi->dev, msi->nr_irqs, - sizeof(*msi->irqs), GFP_KERNEL); - if (!msi->irqs) + if (msi->type == MSM_MSI_TYPE_SNPS) { + res = platform_get_resource_byname(to_platform_device(dev), + IORESOURCE_MEM, "dm_core"); + if (!res) { + dev_err(msi->dev, + "MSI: failed to get PCIe register base\n"); + return -ENODEV; + } + + msi->pcie_cfg = devm_ioremap(msi->dev, res->start, + resource_size(res)); + if (!msi->pcie_cfg) + return -ENOMEM; + + msi->nr_virqs = MSI_IRQ_NR_GRP * MSI_IRQ_PER_GRP; + msi->nr_grps = MSI_IRQ_NR_GRP; + msi_handler = msm_msi_snps_handler; + } else { + msi->nr_virqs = msi->nr_hwirqs; + msi->nr_grps = 1; + msi_handler = msm_msi_qgic_handler; + } + + msi->grps = devm_kcalloc(msi->dev, msi->nr_grps, + sizeof(*msi->grps), GFP_KERNEL); + if (!msi->grps) return -ENOMEM; - msi->bitmap = devm_kcalloc(msi->dev, BITS_TO_LONGS(msi->nr_irqs), + msi->bitmap = devm_kcalloc(msi->dev, BITS_TO_LONGS(msi->nr_virqs), sizeof(*msi->bitmap), GFP_KERNEL); if (!msi->bitmap) return -ENOMEM; @@ -365,8 +486,9 @@ int msm_msi_init(struct device *dev) return ret; } - for (i = 0; i < msi->nr_irqs; i++) { + for (i = 0; i < msi->nr_hwirqs; i++) { unsigned int irq = irq_of_parse_and_map(msi->of_node, i); + struct msm_msi_irq *msi_irq; if (!irq) { dev_err(msi->dev, @@ -375,18 +497,47 @@ int msm_msi_init(struct device *dev) goto free_irqs; } - msi->irqs[i].hwirq = irq; - irq_set_chained_handler_and_data(msi->irqs[i].hwirq, - msm_msi_handler, msi); + grp = i / MSI_IRQ_PER_GRP; + index = i % MSI_IRQ_PER_GRP; + msi_irq = &msi->grps[grp].irqs[index]; + + msi_irq->pos = i; + msi_irq->hwirq = irq; + + irq_set_chained_handler_and_data(irq, msi_handler, msi); + } + + if (msi->type == MSM_MSI_TYPE_SNPS) { + for (i = 0; i < msi->nr_virqs; i++) { + struct msm_msi_grp *msi_grp; + + grp = i / MSI_IRQ_PER_GRP; + index = i % MSI_IRQ_PER_GRP; + msi_grp = &msi->grps[grp]; + + msi_grp->irqs[index].pos = i; + msi_grp->irqs[index].hwirq = msi_grp->irqs[0].hwirq; + msi_grp->int_en_reg = msi->pcie_cfg + + PCIE_MSI_CTRL_INT_N_EN_OFFS(grp); + msi_grp->int_status_reg = msi->pcie_cfg + + PCIE_MSI_CTRL_INT_N_STATUS_OFFS(grp); + } } + msm_msi_config(msi->msi_domain); + return 0; free_irqs: for (--i; i >= 0; i--) { - irq_set_chained_handler_and_data(msi->irqs[i].hwirq, - NULL, NULL); - irq_dispose_mapping(msi->irqs[i].hwirq); + u32 hwirq; + + grp = i / MSI_IRQ_PER_GRP; + index = i % MSI_IRQ_PER_GRP; + hwirq = msi->grps[grp].irqs[index].hwirq; + + irq_set_chained_handler_and_data(hwirq, NULL, NULL); + irq_dispose_mapping(hwirq); } irq_domain_remove(msi->msi_domain); diff --git a/include/linux/msm_pcie.h b/include/linux/msm_pcie.h index 19880936d7a5..5d351c5cd2d5 100644 --- a/include/linux/msm_pcie.h +++ b/include/linux/msm_pcie.h @@ -60,8 +60,13 @@ struct msm_pcie_register_event { }; #ifdef CONFIG_PCI_MSM_MSI +void msm_msi_config(struct irq_domain *domain); int msm_msi_init(struct device *dev); #else +static inline void msm_msi_config(struct irq_domain *domain) +{ +} + static inline int msm_msi_init(struct device *dev) { return -EINVAL; -- GitLab From 5f8ce96722d24ad0461e22cdb91eee58a7e2e31b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Nov 2018 16:14:32 -0800 Subject: [PATCH 0444/1286] msm: pcie: move Synopsys MSI support to MSI controller Remove all Synopsys MSI code in PCIe root complex driver and call MSI driver to configure and enable the interrupts. Change-Id: Id7bfef638f08eb266c108e7bb9c752633c3dca0f Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm.c | 314 +------------------------------------ 1 file changed, 7 insertions(+), 307 deletions(-) diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index a98907bab2a4..3f7c537245a5 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include #include @@ -192,8 +191,6 @@ #define MAX_DEVICE_NUM 20 #define MAX_SHORT_BDF_NUM 16 #define PCIE_TLP_RD_SIZE 0x5 -#define PCIE_MSI_NR_IRQS 256 -#define MSM_PCIE_MAX_MSI 32 #define PCIE_LOG_PAGES (50) #define PCIE_CONF_SPACE_DW 1024 #define PCIE_CLEAR 0xDEADBEEF @@ -202,14 +199,6 @@ #define MSM_PCIE_MAX_RESET 5 #define MSM_PCIE_MAX_PIPE_RESET 1 -#define MSM_PCIE_MSI_PHY 0xa0000000 -#define PCIE20_MSI_CTRL_ADDR (0x820) -#define PCIE20_MSI_CTRL_UPPER_ADDR (0x824) -#define PCIE20_MSI_CTRL_INTR_EN (0x828) -#define PCIE20_MSI_CTRL_INTR_MASK (0x82C) -#define PCIE20_MSI_CTRL_INTR_STATUS (0x830) -#define PCIE20_MSI_CTRL_MAX 8 - /* PM control options */ #define PM_IRQ 0x1 #define PM_CLK 0x2 @@ -307,7 +296,6 @@ enum msm_pcie_res { }; enum msm_pcie_irq { - MSM_PCIE_INT_MSI, MSM_PCIE_INT_A, MSM_PCIE_INT_B, MSM_PCIE_INT_C, @@ -572,8 +560,6 @@ struct msm_pcie_dev_t { struct mutex setup_lock; struct irq_domain *irq_domain; - DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_NR_IRQS); - bool use_msi; enum msm_pcie_link_status link_status; bool user_suspend; @@ -872,7 +858,6 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { /* irqs */ static const struct msm_pcie_irq_info_t msm_pcie_irq_info[MSM_PCIE_MAX_IRQ] = { - {"int_msi", 0}, {"int_a", 0}, {"int_b", 0}, {"int_c", 0}, @@ -1186,8 +1171,6 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) ? "enabled" : "disabled"); PCIE_DBG_FS(dev, "cfg_access is %s allowed\n", dev->cfg_access ? "" : "not"); - PCIE_DBG_FS(dev, "use_msi is %d\n", - dev->use_msi); PCIE_DBG_FS(dev, "use_pinctrl is %d\n", dev->use_pinctrl); PCIE_DBG_FS(dev, "use_19p2mhz_aux_clk is %d\n", @@ -3367,24 +3350,6 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) } } -static void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev) -{ - int i; - - PCIE_DBG(dev, "RC%d\n", dev->rc_idx); - - /* program MSI controller and enable all interrupts */ - writel_relaxed(MSM_PCIE_MSI_PHY, dev->dm_core + PCIE20_MSI_CTRL_ADDR); - writel_relaxed(0, dev->dm_core + PCIE20_MSI_CTRL_UPPER_ADDR); - - for (i = 0; i < PCIE20_MSI_CTRL_MAX; i++) - writel_relaxed(~0, dev->dm_core + - PCIE20_MSI_CTRL_INTR_EN + (i * 12)); - - /* ensure that hardware is configured before proceeding */ - wmb(); -} - static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, struct platform_device *pdev) { @@ -3868,22 +3833,10 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) writel_relaxed(dev->slv_addr_space_size, dev->parf + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); - if (dev->use_msi) { - PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx); - val = dev->wr_halt_size ? dev->wr_halt_size : - readl_relaxed(dev->parf + - PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); - - msm_pcie_write_reg(dev->parf, - PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, - BIT(31) | val); - - PCIE_DBG(dev, - "RC%d: PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT: 0x%x.\n", - dev->rc_idx, - readl_relaxed(dev->parf + - PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT)); - } + val = dev->wr_halt_size ? dev->wr_halt_size : + readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, + BIT(31) | val); /* init PCIe PHY */ pcie_phy_init(dev); @@ -4044,11 +3997,10 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) goto link_fail; } - if (!IS_ENABLED(CONFIG_PCI_MSM_MSI)) - msm_pcie_config_msi_controller(dev); - - if (dev->enumerated) + if (dev->enumerated) { + msm_msi_config(dev_get_msi_domain(&dev->dev->dev)); msm_pcie_config_link_pm(dev, true); + } goto out; @@ -4822,39 +4774,6 @@ static irqreturn_t handle_linkdown_irq(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t handle_msi_irq(int irq, void *data) -{ - int i, j; - unsigned long val; - struct msm_pcie_dev_t *dev = data; - void __iomem *ctrl_status; - - PCIE_DUMP(dev, "irq: %d\n", irq); - - /* - * check for set bits, clear it by setting that bit - * and trigger corresponding irq - */ - for (i = 0; i < PCIE20_MSI_CTRL_MAX; i++) { - ctrl_status = dev->dm_core + - PCIE20_MSI_CTRL_INTR_STATUS + (i * 12); - - val = readl_relaxed(ctrl_status); - while (val) { - j = find_first_bit(&val, 32); - writel_relaxed(BIT(j), ctrl_status); - /* ensure that interrupt is cleared (acked) */ - wmb(); - generic_handle_irq( - irq_find_mapping(dev->irq_domain, (j + (32*i))) - ); - val = readl_relaxed(ctrl_status); - } - } - - return IRQ_HANDLED; -} - static irqreturn_t handle_global_irq(int irq, void *data) { int i; @@ -4914,192 +4833,9 @@ static irqreturn_t handle_global_irq(int irq, void *data) return IRQ_HANDLED; } -static void msm_pcie_destroy_irq(struct msi_desc *entry, unsigned int irq) -{ - int pos; - struct msm_pcie_dev_t *dev; - struct pci_dev *pdev = msi_desc_to_pci_dev(entry); - - if (!pdev) { - pr_err("PCIe: pci device is null. IRQ:%d\n", irq); - return; - } - - dev = PCIE_BUS_PRIV_DATA(pdev->bus); - if (!dev) { - pr_err("PCIe: could not find RC. IRQ:%d\n", irq); - return; - } - - PCIE_DBG(dev, "destroy default MSI irq %d\n", irq); - pos = irq - irq_find_mapping(dev->irq_domain, 0); - - PCIE_DBG(dev, "RC%d\n", dev->rc_idx); - - PCIE_DBG(dev, "Before clear_bit pos:%d msi_irq_in_use:%ld\n", - pos, *dev->msi_irq_in_use); - clear_bit(pos, dev->msi_irq_in_use); - PCIE_DBG(dev, "After clear_bit pos:%d msi_irq_in_use:%ld\n", - pos, *dev->msi_irq_in_use); -} - -/* hookup to linux pci msi framework */ -void arch_teardown_msi_irq(unsigned int irq) -{ - struct msi_desc *entry = irq_get_msi_desc(irq); - - PCIE_GEN_DBG("irq %d deallocated\n", irq); - - if (entry) - msm_pcie_destroy_irq(entry, irq); -} - -void arch_teardown_msi_irqs(struct pci_dev *dev) -{ - struct msi_desc *entry; - struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); - - PCIE_DBG(pcie_dev, "RC:%d EP: vendor_id:0x%x device_id:0x%x\n", - pcie_dev->rc_idx, dev->vendor, dev->device); - - pcie_dev->use_msi = false; - - list_for_each_entry(entry, &dev->dev.msi_list, list) { - int i, nvec; - - if (entry->irq == 0) - continue; - nvec = 1 << entry->msi_attrib.multiple; - for (i = 0; i < nvec; i++) - msm_pcie_destroy_irq(entry, entry->irq + i); - } -} - -static void msm_pcie_msi_nop(struct irq_data *d) -{ -} - -static struct irq_chip pcie_msi_chip = { - .name = "msm-pcie-msi", - .irq_ack = msm_pcie_msi_nop, - .irq_enable = unmask_msi_irq, - .irq_disable = mask_msi_irq, - .irq_mask = mask_msi_irq, - .irq_unmask = unmask_msi_irq, -}; - -static int msm_pcie_create_irq(struct msm_pcie_dev_t *dev) -{ - int irq, pos; - - PCIE_DBG(dev, "RC%d\n", dev->rc_idx); - -again: - pos = find_first_zero_bit(dev->msi_irq_in_use, PCIE_MSI_NR_IRQS); - - if (pos >= PCIE_MSI_NR_IRQS) - return -ENOSPC; - - PCIE_DBG(dev, "pos:%d msi_irq_in_use:%ld\n", pos, *dev->msi_irq_in_use); - - if (test_and_set_bit(pos, dev->msi_irq_in_use)) - goto again; - else - PCIE_DBG(dev, "test_and_set_bit is successful pos=%d\n", pos); - - irq = irq_create_mapping(dev->irq_domain, pos); - if (!irq) - return -EINVAL; - - return irq; -} - -static int arch_setup_msi_irq_default(struct pci_dev *pdev, - struct msi_desc *desc, int nvec) -{ - int irq; - struct msi_msg msg; - struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev->bus); - - PCIE_DBG(dev, "RC%d\n", dev->rc_idx); - - irq = msm_pcie_create_irq(dev); - - PCIE_DBG(dev, "IRQ %d is allocated.\n", irq); - - if (irq < 0) - return irq; - - PCIE_DBG(dev, "irq %d allocated\n", irq); - - irq_set_chip_data(irq, pdev); - irq_set_msi_desc(irq, desc); - - /* write msi vector and data */ - msg.address_hi = 0; - msg.address_lo = MSM_PCIE_MSI_PHY; - msg.data = irq - irq_find_mapping(dev->irq_domain, 0); - write_msi_msg(irq, &msg); - - return 0; -} - -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -{ - struct msm_pcie_dev_t *dev = PCIE_BUS_PRIV_DATA(pdev->bus); - - PCIE_DBG(dev, "RC%d\n", dev->rc_idx); - - return arch_setup_msi_irq_default(pdev, desc, 1); -} - -int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) -{ - struct msi_desc *entry; - int ret; - struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus); - - PCIE_DBG(pcie_dev, "RC%d\n", pcie_dev->rc_idx); - - if (type != PCI_CAP_ID_MSI || nvec > 32) - return -ENOSPC; - - PCIE_DBG(pcie_dev, "nvec = %d\n", nvec); - - list_for_each_entry(entry, &dev->dev.msi_list, list) { - entry->msi_attrib.multiple = - __ilog2_u32(__roundup_pow_of_two(nvec)); - - ret = arch_setup_msi_irq_default(dev, entry, nvec); - - PCIE_DBG(pcie_dev, "ret from msi_irq: %d\n", ret); - - if (ret < 0) - return ret; - if (ret > 0) - return -ENOSPC; - } - - pcie_dev->use_msi = true; - - return 0; -} - -static int msm_pcie_msi_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) -{ - irq_set_chip_and_handler (irq, &pcie_msi_chip, handle_simple_irq); - return 0; -} - -static const struct irq_domain_ops msm_pcie_msi_ops = { - .map = msm_pcie_msi_map, -}; - static int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) { int rc; - int msi_start = 0; struct device *pdev = &dev->pdev->dev; PCIE_DBG(dev, "RC%d\n", dev->rc_idx); @@ -5125,22 +4861,6 @@ static int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) } } - /* register handler for physical MSI interrupt line */ - if (dev->irq[MSM_PCIE_INT_MSI].num) { - rc = devm_request_irq(pdev, - dev->irq[MSM_PCIE_INT_MSI].num, - handle_msi_irq, - IRQF_TRIGGER_RISING, - dev->irq[MSM_PCIE_INT_MSI].name, - dev); - if (rc) { - PCIE_ERR(dev, - "PCIe: RC%d: Unable to request MSI interrupt\n", - dev->rc_idx); - return rc; - } - } - /* register handler for AER interrupt */ if (dev->irq[MSM_PCIE_INT_PLS_ERR].num) { rc = devm_request_irq(pdev, @@ -5214,25 +4934,6 @@ static int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev) } } - /* Create a virtual domain of interrupts */ - if (!IS_ENABLED(CONFIG_PCI_MSM_MSI)) { - dev->irq_domain = irq_domain_add_linear(dev->pdev->dev.of_node, - PCIE_MSI_NR_IRQS, &msm_pcie_msi_ops, dev); - - if (!dev->irq_domain) { - PCIE_ERR(dev, - "PCIe: RC%d: Unable to initialize irq domain\n", - dev->rc_idx); - - if (dev->wake_n) - disable_irq(dev->wake_n); - - return PTR_ERR(dev->irq_domain); - } - - msi_start = irq_create_mapping(dev->irq_domain, 0); - } - return 0; } @@ -5957,7 +5658,6 @@ static int msm_pcie_probe(struct platform_device *pdev) if (msm_pcie_invert_aer_support) msm_pcie_dev[rc_idx].aer_enable = false; msm_pcie_dev[rc_idx].power_on = false; - msm_pcie_dev[rc_idx].use_msi = false; msm_pcie_dev[rc_idx].use_pinctrl = false; msm_pcie_dev[rc_idx].linkdown_panic = false; msm_pcie_dev[rc_idx].bridge_found = false; -- GitLab From c4bd329649f197e709d95bc64c6f5155616d9e5e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 14 Dec 2018 17:54:28 -0800 Subject: [PATCH 0445/1286] dt-bindings: pcie: remove MSI related entries PCIe root complex driver does not manage MSI anymore. Remove all MSI related entries. Change-Id: I1ae2ec6c61ea2e146c4fc29a5407cd9b264fd856 Signed-off-by: Tony Truong --- .../devicetree/bindings/pci/msm_pcie.txt | 26 ++++--------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 6722acb358d0..da1519fa3b62 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -21,20 +21,12 @@ Required properties: For PCIe device node, it should define 12 mappings for the corresponding PCIe interrupts supporting the specification. - interrupt-names: indicates interrupts passed to driver by name. - Should be "int_msi", "int_a", "int_b", "int_c", "int_d", + Should be "int_a", "int_b", "int_c", "int_d", "int_pls_pme", "int_pme_legacy", "int_pls_err", "int_aer_legacy", "int_pls_link_up", - "int_pls_link_down", "int_bridge_flush_n", - "msi_0", "msi_1", "msi_2", "msi_3", - "msi_4", "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", "msi_11", - "msi_12", "msi_13", "msi_14", "msi_15", - "msi_16", "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", "msi_22", "msi_23", - "msi_24", "msi_25", "msi_26", "msi_27", - "msi_28", "msi_29", "msi_30", "msi_31" + "int_pls_link_down", "int_bridge_flush_n" These correspond to the standard PCIe specification to support - MSIs, virtual IRQ's (INT#), link state notifications. + virtual IRQ's (INT#), link state notifications. - perst-gpio: PERST GPIO specified by PCIe spec. - wake-gpio: WAKE GPIO specified by PCIe spec. - phy-status-offset: Offset from PCIe PHY base to check if PCIe PHY is up. @@ -221,18 +213,10 @@ Example: 0x0 0x0 0x0 41 &intc 0 477 0 0x0 0x0 0x0 42 &intc 0 478 0 0x0 0x0 0x0 43 &intc 0 479 0>; - interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d", + interrupt-names = int_a", "int_b", "int_c", "int_d", "int_pls_pme", "int_pme_legacy", "int_pls_err", "int_aer_legacy", "int_pls_link_up", - "int_pls_link_down", "int_bridge_flush_n", - "msi_0", "msi_1", "msi_2", "msi_3", - "msi_4", "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", "msi_11", - "msi_12", "msi_13", "msi_14", "msi_15", - "msi_16", "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", "msi_22", "msi_23", - "msi_24", "msi_25", "msi_26", "msi_27", - "msi_28", "msi_29", "msi_30", "msi_31"; + "int_pls_link_down", "int_bridge_flush_n"; qcom,phy-sequence = <0x804 0x01 0x00 0x034 0x14 0x00 -- GitLab From de3ee4878ec9d725fb833f86975d584651ca2fa4 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 27 Nov 2018 16:16:45 -0800 Subject: [PATCH 0446/1286] ARM: dts: msm: remove Synopsys MSI IRQ from PCIe nodes for sm8150 To support Synopsys MSI, its IRQ should be managed by MSI controller instead of PCIe root complex. Remove Synopsys MSI from PCIe nodes for sm8150. Change-Id: Ib7a840b63031a00f003a9990fb1379f9b1d67139 Signed-off-by: Tony Truong --- arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi | 30 +++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index ae72261ef2ab..0066be6ccd29 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -35,17 +35,16 @@ ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; interrupt-parent = <&pcie0>; - interrupts = <0 1 2 3 4 5>; - interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d", + interrupts = <0 1 2 3 4>; + interrupt-names = "int_a", "int_b", "int_c", "int_d", "int_global_int"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 141 0 - 0 0 0 1 &intc 0 149 0 - 0 0 0 2 &intc 0 150 0 - 0 0 0 3 &intc 0 151 0 - 0 0 0 4 &intc 0 152 0 - 0 0 0 5 &intc 0 140 0>; + interrupt-map = <0 0 0 0 &intc 0 149 0 + 0 0 0 1 &intc 0 150 0 + 0 0 0 2 &intc 0 151 0 + 0 0 0 3 &intc 0 152 0 + 0 0 0 4 &intc 0 140 0>; qcom,phy-sequence = <0x0840 0x03 0x0 0x0094 0x08 0x0 @@ -302,17 +301,16 @@ ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; interrupt-parent = <&pcie1>; - interrupts = <0 1 2 3 4 5>; - interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d", + interrupts = <0 1 2 3 4>; + interrupt-names = "int_a", "int_b", "int_c", "int_d", "int_global_int"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 307 0 - 0 0 0 1 &intc 0 434 0 - 0 0 0 2 &intc 0 435 0 - 0 0 0 3 &intc 0 438 0 - 0 0 0 4 &intc 0 439 0 - 0 0 0 5 &intc 0 306 0>; + interrupt-map = <0 0 0 0 &intc 0 434 0 + 0 0 0 1 &intc 0 435 0 + 0 0 0 2 &intc 0 438 0 + 0 0 0 3 &intc 0 439 0 + 0 0 0 4 &intc 0 306 0>; qcom,phy-sequence = <0x0a40 0x03 0x0 0x0010 0x00 0x0 -- GitLab From da4b692991fc0f4ac74cb1546f52e67a8fe54801 Mon Sep 17 00:00:00 2001 From: Jiri Wiesner Date: Wed, 5 Dec 2018 16:55:29 +0100 Subject: [PATCH 0447/1286] ipv4: ipv6: netfilter: Adjust the frag mem limit when truesize changes [ Upstream commit ebaf39e6032faf77218220707fc3fa22487784e0 ] The *_frag_reasm() functions are susceptible to miscalculating the byte count of packet fragments in case the truesize of a head buffer changes. The truesize member may be changed by the call to skb_unclone(), leaving the fragment memory limit counter unbalanced even if all fragments are processed. This miscalculation goes unnoticed as long as the network namespace which holds the counter is not destroyed. Should an attempt be made to destroy a network namespace that holds an unbalanced fragment memory limit counter the cleanup of the namespace never finishes. The thread handling the cleanup gets stuck in inet_frags_exit_net() waiting for the percpu counter to reach zero. The thread is usually in running state with a stacktrace similar to: PID: 1073 TASK: ffff880626711440 CPU: 1 COMMAND: "kworker/u48:4" #5 [ffff880621563d48] _raw_spin_lock at ffffffff815f5480 #6 [ffff880621563d48] inet_evict_bucket at ffffffff8158020b #7 [ffff880621563d80] inet_frags_exit_net at ffffffff8158051c #8 [ffff880621563db0] ops_exit_list at ffffffff814f5856 #9 [ffff880621563dd8] cleanup_net at ffffffff814f67c0 #10 [ffff880621563e38] process_one_work at ffffffff81096f14 It is not possible to create new network namespaces, and processes that call unshare() end up being stuck in uninterruptible sleep state waiting to acquire the net_mutex. The bug was observed in the IPv6 netfilter code by Per Sundstrom. I thank him for his analysis of the problem. The parts of this patch that apply to IPv4 and IPv6 fragment reassembly are preemptive measures. Signed-off-by: Jiri Wiesner Reported-by: Per Sundstrom Acked-by: Peter Oskolkov Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/ip_fragment.c | 7 +++++++ net/ipv6/netfilter/nf_conntrack_reasm.c | 8 +++++++- net/ipv6/reassembly.c | 8 +++++++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c index cb8fa5d7afe1..f686d7761acb 100644 --- a/net/ipv4/ip_fragment.c +++ b/net/ipv4/ip_fragment.c @@ -513,6 +513,7 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *skb, struct rb_node *rbn; int len; int ihlen; + int delta; int err; u8 ecn; @@ -554,10 +555,16 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *skb, if (len > 65535) goto out_oversize; + delta = - head->truesize; + /* Head of list must not be cloned. */ if (skb_unclone(head, GFP_ATOMIC)) goto out_nomem; + delta += head->truesize; + if (delta) + add_frag_mem_limit(qp->q.net, delta); + /* If the first fragment is fragmented itself, we split * it to two chunks: the first with data and paged part * and the second, holding only fragments. */ diff --git a/net/ipv6/netfilter/nf_conntrack_reasm.c b/net/ipv6/netfilter/nf_conntrack_reasm.c index 611d406c4656..237fb04c6716 100644 --- a/net/ipv6/netfilter/nf_conntrack_reasm.c +++ b/net/ipv6/netfilter/nf_conntrack_reasm.c @@ -349,7 +349,7 @@ static bool nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev, struct net_device *dev) { struct sk_buff *fp, *head = fq->q.fragments; - int payload_len; + int payload_len, delta; u8 ecn; inet_frag_kill(&fq->q); @@ -371,10 +371,16 @@ nf_ct_frag6_reasm(struct frag_queue *fq, struct sk_buff *prev, struct net_devic return false; } + delta = - head->truesize; + /* Head of list must not be cloned. */ if (skb_unclone(head, GFP_ATOMIC)) return false; + delta += head->truesize; + if (delta) + add_frag_mem_limit(fq->q.net, delta); + /* If the first fragment is fragmented itself, we split * it to two chunks: the first with data and paged part * and the second, holding only fragments. */ diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c index ede0061b6f5d..2a8c680b67cd 100644 --- a/net/ipv6/reassembly.c +++ b/net/ipv6/reassembly.c @@ -348,7 +348,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, { struct net *net = container_of(fq->q.net, struct net, ipv6.frags); struct sk_buff *fp, *head = fq->q.fragments; - int payload_len; + int payload_len, delta; unsigned int nhoff; int sum_truesize; u8 ecn; @@ -389,10 +389,16 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, if (payload_len > IPV6_MAXPLEN) goto out_oversize; + delta = - head->truesize; + /* Head of list must not be cloned. */ if (skb_unclone(head, GFP_ATOMIC)) goto out_oom; + delta += head->truesize; + if (delta) + add_frag_mem_limit(fq->q.net, delta); + /* If the first fragment is fragmented itself, we split * it to two chunks: the first with data and paged part * and the second, holding only fragments. */ -- GitLab From ece6a4b7efa8ec7764bda17ad37f46be5e141d16 Mon Sep 17 00:00:00 2001 From: Stefano Brivio Date: Thu, 6 Dec 2018 19:30:36 +0100 Subject: [PATCH 0448/1286] ipv6: Check available headroom in ip6_xmit() even without options [ Upstream commit 66033f47ca60294a95fc85ec3a3cc909dab7b765 ] Even if we send an IPv6 packet without options, MAX_HEADER might not be enough to account for the additional headroom required by alignment of hardware headers. On a configuration without HYPERV_NET, WLAN, AX25, and with IPV6_TUNNEL, sending short SCTP packets over IPv4 over L2TP over IPv6, we start with 100 bytes of allocated headroom in sctp_packet_transmit(), end up with 54 bytes after l2tp_xmit_skb(), and 14 bytes in ip6_finish_output2(). Those would be enough to append our 14 bytes header, but we're going to align that to 16 bytes, and write 2 bytes out of the allocated slab in neigh_hh_output(). KASan says: [ 264.967848] ================================================================== [ 264.967861] BUG: KASAN: slab-out-of-bounds in ip6_finish_output2+0x1aec/0x1c70 [ 264.967866] Write of size 16 at addr 000000006af1c7fe by task netperf/6201 [ 264.967870] [ 264.967876] CPU: 0 PID: 6201 Comm: netperf Not tainted 4.20.0-rc4+ #1 [ 264.967881] Hardware name: IBM 2827 H43 400 (z/VM 6.4.0) [ 264.967887] Call Trace: [ 264.967896] ([<00000000001347d6>] show_stack+0x56/0xa0) [ 264.967903] [<00000000017e379c>] dump_stack+0x23c/0x290 [ 264.967912] [<00000000007bc594>] print_address_description+0xf4/0x290 [ 264.967919] [<00000000007bc8fc>] kasan_report+0x13c/0x240 [ 264.967927] [<000000000162f5e4>] ip6_finish_output2+0x1aec/0x1c70 [ 264.967935] [<000000000163f890>] ip6_finish_output+0x430/0x7f0 [ 264.967943] [<000000000163fe44>] ip6_output+0x1f4/0x580 [ 264.967953] [<000000000163882a>] ip6_xmit+0xfea/0x1ce8 [ 264.967963] [<00000000017396e2>] inet6_csk_xmit+0x282/0x3f8 [ 264.968033] [<000003ff805fb0ba>] l2tp_xmit_skb+0xe02/0x13e0 [l2tp_core] [ 264.968037] [<000003ff80631192>] l2tp_eth_dev_xmit+0xda/0x150 [l2tp_eth] [ 264.968041] [<0000000001220020>] dev_hard_start_xmit+0x268/0x928 [ 264.968069] [<0000000001330e8e>] sch_direct_xmit+0x7ae/0x1350 [ 264.968071] [<000000000122359c>] __dev_queue_xmit+0x2b7c/0x3478 [ 264.968075] [<00000000013d2862>] ip_finish_output2+0xce2/0x11a0 [ 264.968078] [<00000000013d9b14>] ip_finish_output+0x56c/0x8c8 [ 264.968081] [<00000000013ddd1e>] ip_output+0x226/0x4c0 [ 264.968083] [<00000000013dbd6c>] __ip_queue_xmit+0x894/0x1938 [ 264.968100] [<000003ff80bc3a5c>] sctp_packet_transmit+0x29d4/0x3648 [sctp] [ 264.968116] [<000003ff80b7bf68>] sctp_outq_flush_ctrl.constprop.5+0x8d0/0xe50 [sctp] [ 264.968131] [<000003ff80b7c716>] sctp_outq_flush+0x22e/0x7d8 [sctp] [ 264.968146] [<000003ff80b35c68>] sctp_cmd_interpreter.isra.16+0x530/0x6800 [sctp] [ 264.968161] [<000003ff80b3410a>] sctp_do_sm+0x222/0x648 [sctp] [ 264.968177] [<000003ff80bbddac>] sctp_primitive_ASSOCIATE+0xbc/0xf8 [sctp] [ 264.968192] [<000003ff80b93328>] __sctp_connect+0x830/0xc20 [sctp] [ 264.968208] [<000003ff80bb11ce>] sctp_inet_connect+0x2e6/0x378 [sctp] [ 264.968212] [<0000000001197942>] __sys_connect+0x21a/0x450 [ 264.968215] [<000000000119aff8>] sys_socketcall+0x3d0/0xb08 [ 264.968218] [<000000000184ea7a>] system_call+0x2a2/0x2c0 [...] Just like ip_finish_output2() does for IPv4, check that we have enough headroom in ip6_xmit(), and reallocate it if we don't. This issue is older than git history. Reported-by: Jianlin Shi Signed-off-by: Stefano Brivio Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv6/ip6_output.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 9ab1e0fcbc13..7ca8264cbdf9 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -195,37 +195,37 @@ int ip6_xmit(const struct sock *sk, struct sk_buff *skb, struct flowi6 *fl6, const struct ipv6_pinfo *np = inet6_sk(sk); struct in6_addr *first_hop = &fl6->daddr; struct dst_entry *dst = skb_dst(skb); + unsigned int head_room; struct ipv6hdr *hdr; u8 proto = fl6->flowi6_proto; int seg_len = skb->len; int hlimit = -1; u32 mtu; - if (opt) { - unsigned int head_room; + head_room = sizeof(struct ipv6hdr) + LL_RESERVED_SPACE(dst->dev); + if (opt) + head_room += opt->opt_nflen + opt->opt_flen; - /* First: exthdrs may take lots of space (~8K for now) - MAX_HEADER is not enough. - */ - head_room = opt->opt_nflen + opt->opt_flen; - seg_len += head_room; - head_room += sizeof(struct ipv6hdr) + LL_RESERVED_SPACE(dst->dev); - - if (skb_headroom(skb) < head_room) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, head_room); - if (!skb2) { - IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), - IPSTATS_MIB_OUTDISCARDS); - kfree_skb(skb); - return -ENOBUFS; - } - if (skb->sk) - skb_set_owner_w(skb2, skb->sk); - consume_skb(skb); - skb = skb2; + if (unlikely(skb_headroom(skb) < head_room)) { + struct sk_buff *skb2 = skb_realloc_headroom(skb, head_room); + if (!skb2) { + IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), + IPSTATS_MIB_OUTDISCARDS); + kfree_skb(skb); + return -ENOBUFS; } + if (skb->sk) + skb_set_owner_w(skb2, skb->sk); + consume_skb(skb); + skb = skb2; + } + + if (opt) { + seg_len += opt->opt_nflen + opt->opt_flen; + if (opt->opt_flen) ipv6_push_frag_opts(skb, opt, &proto); + if (opt->opt_nflen) ipv6_push_nfrag_opts(skb, opt, &proto, &first_hop, &fl6->saddr); -- GitLab From 9380dc7c5101c0ac539c282babd5d3c91394b94a Mon Sep 17 00:00:00 2001 From: Stefano Brivio Date: Thu, 6 Dec 2018 19:30:37 +0100 Subject: [PATCH 0449/1286] neighbour: Avoid writing before skb->head in neigh_hh_output() [ Upstream commit e6ac64d4c4d095085d7dd71cbd05704ac99829b2 ] While skb_push() makes the kernel panic if the skb headroom is less than the unaligned hardware header size, it will proceed normally in case we copy more than that because of alignment, and we'll silently corrupt adjacent slabs. In the case fixed by the previous patch, "ipv6: Check available headroom in ip6_xmit() even without options", we end up in neigh_hh_output() with 14 bytes headroom, 14 bytes hardware header and write 16 bytes, starting 2 bytes before the allocated buffer. Always check we're not writing before skb->head and, if the headroom is not enough, warn and drop the packet. v2: - instead of panicking with BUG_ON(), WARN_ON_ONCE() and drop the packet (Eric Dumazet) - if we avoid the panic, though, we need to explicitly check the headroom before the memcpy(), otherwise we'll have corrupted slabs on a running kernel, after we warn - use __skb_push() instead of skb_push(), as the headroom check is already implemented here explicitly (Eric Dumazet) Signed-off-by: Stefano Brivio Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- include/net/neighbour.h | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/include/net/neighbour.h b/include/net/neighbour.h index a964366a7ef5..393099b1901a 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -452,6 +452,7 @@ static inline int neigh_hh_bridge(struct hh_cache *hh, struct sk_buff *skb) static inline int neigh_hh_output(const struct hh_cache *hh, struct sk_buff *skb) { + unsigned int hh_alen = 0; unsigned int seq; unsigned int hh_len; @@ -459,16 +460,33 @@ static inline int neigh_hh_output(const struct hh_cache *hh, struct sk_buff *skb seq = read_seqbegin(&hh->hh_lock); hh_len = hh->hh_len; if (likely(hh_len <= HH_DATA_MOD)) { - /* this is inlined by gcc */ - memcpy(skb->data - HH_DATA_MOD, hh->hh_data, HH_DATA_MOD); + hh_alen = HH_DATA_MOD; + + /* skb_push() would proceed silently if we have room for + * the unaligned size but not for the aligned size: + * check headroom explicitly. + */ + if (likely(skb_headroom(skb) >= HH_DATA_MOD)) { + /* this is inlined by gcc */ + memcpy(skb->data - HH_DATA_MOD, hh->hh_data, + HH_DATA_MOD); + } } else { - unsigned int hh_alen = HH_DATA_ALIGN(hh_len); + hh_alen = HH_DATA_ALIGN(hh_len); - memcpy(skb->data - hh_alen, hh->hh_data, hh_alen); + if (likely(skb_headroom(skb) >= hh_alen)) { + memcpy(skb->data - hh_alen, hh->hh_data, + hh_alen); + } } } while (read_seqretry(&hh->hh_lock, seq)); - skb_push(skb, hh_len); + if (WARN_ON_ONCE(skb_headroom(skb) < hh_alen)) { + kfree_skb(skb); + return NET_XMIT_DROP; + } + + __skb_push(skb, hh_len); return dev_queue_xmit(skb); } -- GitLab From 25f111f2432d69a5014503dc27cf729d6adea285 Mon Sep 17 00:00:00 2001 From: Shmulik Ladkani Date: Fri, 7 Dec 2018 09:50:17 +0200 Subject: [PATCH 0450/1286] ipv6: sr: properly initialize flowi6 prior passing to ip6_route_output [ Upstream commit 1b4e5ad5d6b9f15cd0b5121f86d4719165958417 ] In 'seg6_output', stack variable 'struct flowi6 fl6' was missing initialization. Fixes: 6c8702c60b88 ("ipv6: sr: add support for SRH encapsulation and injection with lwtunnels") Signed-off-by: Shmulik Ladkani Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv6/seg6_iptunnel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv6/seg6_iptunnel.c b/net/ipv6/seg6_iptunnel.c index bf4763fd68c2..cf9342bfe95a 100644 --- a/net/ipv6/seg6_iptunnel.c +++ b/net/ipv6/seg6_iptunnel.c @@ -327,6 +327,7 @@ static int seg6_output(struct net *net, struct sock *sk, struct sk_buff *skb) struct ipv6hdr *hdr = ipv6_hdr(skb); struct flowi6 fl6; + memset(&fl6, 0, sizeof(fl6)); fl6.daddr = hdr->daddr; fl6.saddr = hdr->saddr; fl6.flowlabel = ip6_flowinfo(hdr); -- GitLab From 4c65c73cf124dedd9bb64374851f7466d5704750 Mon Sep 17 00:00:00 2001 From: Su Yanjun Date: Mon, 3 Dec 2018 15:33:07 +0800 Subject: [PATCH 0451/1286] net: 8139cp: fix a BUG triggered by changing mtu with network traffic [ Upstream commit a5d4a89245ead1f37ed135213653c5beebea4237 ] When changing mtu many times with traffic, a bug is triggered: [ 1035.684037] kernel BUG at lib/dynamic_queue_limits.c:26! [ 1035.684042] invalid opcode: 0000 [#1] SMP [ 1035.684049] Modules linked in: loop binfmt_misc 8139cp(OE) macsec tcp_diag udp_diag inet_diag unix_diag af_packet_diag netlink_diag tcp_lp fuse uinput xt_CHECKSUM iptable_mangle ipt_MASQUERADE nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack ipt_REJECT nf_reject_ipv4 tun bridge stp llc ebtable_filter ebtables ip6table_filter devlink ip6_tables iptable_filter sunrpc snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep ppdev snd_seq iosf_mbi crc32_pclmul parport_pc snd_seq_device ghash_clmulni_intel parport snd_pcm aesni_intel joydev lrw snd_timer virtio_balloon sg gf128mul glue_helper ablk_helper cryptd snd soundcore i2c_piix4 pcspkr ip_tables xfs libcrc32c sr_mod sd_mod cdrom crc_t10dif crct10dif_generic ata_generic [ 1035.684102] pata_acpi virtio_console qxl drm_kms_helper syscopyarea sysfillrect sysimgblt floppy fb_sys_fops crct10dif_pclmul crct10dif_common ttm crc32c_intel serio_raw ata_piix drm libata 8139too virtio_pci drm_panel_orientation_quirks virtio_ring virtio mii dm_mirror dm_region_hash dm_log dm_mod [last unloaded: 8139cp] [ 1035.684132] CPU: 9 PID: 25140 Comm: if-mtu-change Kdump: loaded Tainted: G OE ------------ T 3.10.0-957.el7.x86_64 #1 [ 1035.684134] Hardware name: Red Hat KVM, BIOS 0.5.1 01/01/2011 [ 1035.684136] task: ffff8f59b1f5a080 ti: ffff8f5a2e32c000 task.ti: ffff8f5a2e32c000 [ 1035.684149] RIP: 0010:[] [] dql_completed+0x180/0x190 [ 1035.684162] RSP: 0000:ffff8f5a75483e50 EFLAGS: 00010093 [ 1035.684162] RAX: 00000000000000c2 RBX: ffff8f5a6f91c000 RCX: 0000000000000000 [ 1035.684162] RDX: 0000000000000000 RSI: 0000000000000184 RDI: ffff8f599fea3ec0 [ 1035.684162] RBP: ffff8f5a75483ea8 R08: 00000000000000c2 R09: 0000000000000000 [ 1035.684162] R10: 00000000000616ef R11: ffff8f5a75483b56 R12: ffff8f599fea3e00 [ 1035.684162] R13: 0000000000000001 R14: 0000000000000000 R15: 0000000000000184 [ 1035.684162] FS: 00007fa8434de740(0000) GS:ffff8f5a75480000(0000) knlGS:0000000000000000 [ 1035.684162] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1035.684162] CR2: 00000000004305d0 CR3: 000000024eb66000 CR4: 00000000001406e0 [ 1035.684162] Call Trace: [ 1035.684162] [ 1035.684162] [] ? cp_interrupt+0x478/0x580 [8139cp] [ 1035.684162] [] __handle_irq_event_percpu+0x44/0x1c0 [ 1035.684162] [] handle_irq_event_percpu+0x32/0x80 [ 1035.684162] [] handle_irq_event+0x3c/0x60 [ 1035.684162] [] handle_fasteoi_irq+0x59/0x110 [ 1035.684162] [] handle_irq+0xe4/0x1a0 [ 1035.684162] [] do_IRQ+0x4d/0xf0 [ 1035.684162] [] common_interrupt+0x162/0x162 [ 1035.684162] [ 1035.684162] [] ? __wake_up_bit+0x24/0x70 [ 1035.684162] [] ? do_set_pte+0xd5/0x120 [ 1035.684162] [] unlock_page+0x2b/0x30 [ 1035.684162] [] do_read_fault.isra.61+0x139/0x1b0 [ 1035.684162] [] handle_pte_fault+0x2f4/0xd10 [ 1035.684162] [] handle_mm_fault+0x39d/0x9b0 [ 1035.684162] [] __do_page_fault+0x203/0x500 [ 1035.684162] [] trace_do_page_fault+0x56/0x150 [ 1035.684162] [] do_async_page_fault+0x22/0xf0 [ 1035.684162] [] async_page_fault+0x28/0x30 [ 1035.684162] Code: 54 c7 47 54 ff ff ff ff 44 0f 49 ce 48 8b 35 48 2f 9c 00 48 89 77 58 e9 fe fe ff ff 0f 1f 80 00 00 00 00 41 89 d1 e9 ef fe ff ff <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 55 8d 42 ff 48 [ 1035.684162] RIP [] dql_completed+0x180/0x190 [ 1035.684162] RSP It's not the same as in 7fe0ee09 patch described. As 8139cp uses shared irq mode, other device irq will trigger cp_interrupt to execute. cp_change_mtu -> cp_close -> cp_open In cp_close routine just before free_irq(), some interrupt may occur. In my environment, cp_interrupt exectutes and IntrStatus is 0x4, exactly TxOk. That will cause cp_tx to wake device queue. As device queue is started, cp_start_xmit and cp_open will run at same time which will cause kernel BUG. For example: [#] for tx descriptor At start: [#][#][#] num_queued=3 After cp_init_hw->cp_start_hw->netdev_reset_queue: [#][#][#] num_queued=0 When 8139cp starts to work then cp_tx will check num_queued mismatchs the complete_bytes. The patch will check IntrMask before check IntrStatus in cp_interrupt. When 8139cp interrupt is disabled, just return. Signed-off-by: Su Yanjun Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/realtek/8139cp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c index e7ab23e87de2..d1e88712a275 100644 --- a/drivers/net/ethernet/realtek/8139cp.c +++ b/drivers/net/ethernet/realtek/8139cp.c @@ -571,6 +571,7 @@ static irqreturn_t cp_interrupt (int irq, void *dev_instance) struct cp_private *cp; int handled = 0; u16 status; + u16 mask; if (unlikely(dev == NULL)) return IRQ_NONE; @@ -578,6 +579,10 @@ static irqreturn_t cp_interrupt (int irq, void *dev_instance) spin_lock(&cp->lock); + mask = cpr16(IntrMask); + if (!mask) + goto out_unlock; + status = cpr16(IntrStatus); if (!status || (status == 0xFFFF)) goto out_unlock; -- GitLab From 76f67ede4df921f5e4f0c02129a6407c977cab57 Mon Sep 17 00:00:00 2001 From: Tarick Bedeir Date: Fri, 7 Dec 2018 00:30:26 -0800 Subject: [PATCH 0452/1286] net/mlx4_core: Correctly set PFC param if global pause is turned off. [ Upstream commit bd5122cd1e0644d8bd8dd84517c932773e999766 ] rx_ppp and tx_ppp can be set between 0 and 255, so don't clamp to 1. Fixes: 6e8814ceb7e8 ("net/mlx4_en: Fix mixed PFC and Global pause user control requests") Signed-off-by: Tarick Bedeir Reviewed-by: Eran Ben Elisha Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/mellanox/mlx4/en_ethtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c index 5fe56dc4cfae..5363cee88a0a 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c @@ -1070,8 +1070,8 @@ static int mlx4_en_set_pauseparam(struct net_device *dev, tx_pause = !!(pause->tx_pause); rx_pause = !!(pause->rx_pause); - rx_ppp = priv->prof->rx_ppp && !(tx_pause || rx_pause); - tx_ppp = priv->prof->tx_ppp && !(tx_pause || rx_pause); + rx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->rx_ppp; + tx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->tx_ppp; err = mlx4_SET_PORT_general(mdev->dev, priv->port, priv->rx_skb_size + ETH_FCS_LEN, -- GitLab From 583e170ce81654554243790ac2e340ebe2180d14 Mon Sep 17 00:00:00 2001 From: Eran Ben Elisha Date: Sun, 2 Dec 2018 14:34:36 +0200 Subject: [PATCH 0453/1286] net/mlx4_en: Change min MTU size to ETH_MIN_MTU [ Upstream commit 24be19e47779d604d1492c114459dca9a92acf78 ] NIC driver minimal MTU size shall be set to ETH_MIN_MTU, as defined in the RFC791 and in the network stack. Remove old mlx4_en only define for it, which was set to wrong value. Fixes: b80f71f5816f ("ethernet/mellanox: use core min/max MTU checking") Signed-off-by: Eran Ben Elisha Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/mellanox/mlx4/en_netdev.c | 4 ++-- drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index faa4bd21f148..0fb85d71c11b 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -3505,8 +3505,8 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; } - /* MTU range: 46 - hw-specific max */ - dev->min_mtu = MLX4_EN_MIN_MTU; + /* MTU range: 68 - hw-specific max */ + dev->min_mtu = ETH_MIN_MTU; dev->max_mtu = priv->max_mtu; mdev->pndev[port] = dev; diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h index 09f4764a3f39..bdd87438a354 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h @@ -157,7 +157,6 @@ #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) -#define MLX4_EN_MIN_MTU 46 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). */ -- GitLab From e44c8cbd09da1c3a9f2c752492b8efa3a53487f9 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Mon, 3 Dec 2018 08:19:33 +0100 Subject: [PATCH 0454/1286] net: phy: don't allow __set_phy_supported to add unsupported modes [ Upstream commit d2a36971ef595069b7a600d1144c2e0881a930a1 ] Currently __set_phy_supported allows to add modes w/o checking whether the PHY supports them. This is wrong, it should never add modes but only remove modes we don't want to support. The commit marked as fixed didn't do anything wrong, it just copied existing functionality to the helper which is being fixed now. Fixes: f3a6bd393c2c ("phylib: Add phy_set_max_speed helper") Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/phy/phy_device.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index fe76e2c4022a..5b56a86e88ff 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1703,20 +1703,17 @@ EXPORT_SYMBOL(genphy_loopback); static int __set_phy_supported(struct phy_device *phydev, u32 max_speed) { - phydev->supported &= ~(PHY_1000BT_FEATURES | PHY_100BT_FEATURES | - PHY_10BT_FEATURES); - switch (max_speed) { - default: - return -ENOTSUPP; - case SPEED_1000: - phydev->supported |= PHY_1000BT_FEATURES; + case SPEED_10: + phydev->supported &= ~PHY_100BT_FEATURES; /* fall through */ case SPEED_100: - phydev->supported |= PHY_100BT_FEATURES; - /* fall through */ - case SPEED_10: - phydev->supported |= PHY_10BT_FEATURES; + phydev->supported &= ~PHY_1000BT_FEATURES; + break; + case SPEED_1000: + break; + default: + return -ENOTSUPP; } return 0; -- GitLab From 56ed9f33e03f0a4070a8f3aba9d1ccc443d180a8 Mon Sep 17 00:00:00 2001 From: Christoph Paasch Date: Thu, 29 Nov 2018 16:01:04 -0800 Subject: [PATCH 0455/1286] net: Prevent invalid access to skb->prev in __qdisc_drop_all [ Upstream commit 9410d386d0a829ace9558336263086c2fbbe8aed ] __qdisc_drop_all() accesses skb->prev to get to the tail of the segment-list. With commit 68d2f84a1368 ("net: gro: properly remove skb from list") the skb-list handling has been changed to set skb->next to NULL and set the list-poison on skb->prev. With that change, __qdisc_drop_all() will panic when it tries to dereference skb->prev. Since commit 992cba7e276d ("net: Add and use skb_list_del_init().") __list_del_entry is used, leaving skb->prev unchanged (thus, pointing to the list-head if it's the first skb of the list). This will make __qdisc_drop_all modify the next-pointer of the list-head and result in a panic later on: [ 34.501053] general protection fault: 0000 [#1] SMP KASAN PTI [ 34.501968] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 4.20.0-rc2.mptcp #108 [ 34.502887] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 0.5.1 01/01/2011 [ 34.504074] RIP: 0010:dev_gro_receive+0x343/0x1f90 [ 34.504751] Code: e0 48 c1 e8 03 42 80 3c 30 00 0f 85 4a 1c 00 00 4d 8b 24 24 4c 39 65 d0 0f 84 0a 04 00 00 49 8d 7c 24 38 48 89 f8 48 c1 e8 03 <42> 0f b6 04 30 84 c0 74 08 3c 04 [ 34.507060] RSP: 0018:ffff8883af507930 EFLAGS: 00010202 [ 34.507761] RAX: 0000000000000007 RBX: ffff8883970b2c80 RCX: 1ffff11072e165a6 [ 34.508640] RDX: 1ffff11075867008 RSI: ffff8883ac338040 RDI: 0000000000000038 [ 34.509493] RBP: ffff8883af5079d0 R08: ffff8883970b2d40 R09: 0000000000000062 [ 34.510346] R10: 0000000000000034 R11: 0000000000000000 R12: 0000000000000000 [ 34.511215] R13: 0000000000000000 R14: dffffc0000000000 R15: ffff8883ac338008 [ 34.512082] FS: 0000000000000000(0000) GS:ffff8883af500000(0000) knlGS:0000000000000000 [ 34.513036] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 34.513741] CR2: 000055ccc3e9d020 CR3: 00000003abf32000 CR4: 00000000000006e0 [ 34.514593] Call Trace: [ 34.514893] [ 34.515157] napi_gro_receive+0x93/0x150 [ 34.515632] receive_buf+0x893/0x3700 [ 34.516094] ? __netif_receive_skb+0x1f/0x1a0 [ 34.516629] ? virtnet_probe+0x1b40/0x1b40 [ 34.517153] ? __stable_node_chain+0x4d0/0x850 [ 34.517684] ? kfree+0x9a/0x180 [ 34.518067] ? __kasan_slab_free+0x171/0x190 [ 34.518582] ? detach_buf+0x1df/0x650 [ 34.519061] ? lapic_next_event+0x5a/0x90 [ 34.519539] ? virtqueue_get_buf_ctx+0x280/0x7f0 [ 34.520093] virtnet_poll+0x2df/0xd60 [ 34.520533] ? receive_buf+0x3700/0x3700 [ 34.521027] ? qdisc_watchdog_schedule_ns+0xd5/0x140 [ 34.521631] ? htb_dequeue+0x1817/0x25f0 [ 34.522107] ? sch_direct_xmit+0x142/0xf30 [ 34.522595] ? virtqueue_napi_schedule+0x26/0x30 [ 34.523155] net_rx_action+0x2f6/0xc50 [ 34.523601] ? napi_complete_done+0x2f0/0x2f0 [ 34.524126] ? kasan_check_read+0x11/0x20 [ 34.524608] ? _raw_spin_lock+0x7d/0xd0 [ 34.525070] ? _raw_spin_lock_bh+0xd0/0xd0 [ 34.525563] ? kvm_guest_apic_eoi_write+0x6b/0x80 [ 34.526130] ? apic_ack_irq+0x9e/0xe0 [ 34.526567] __do_softirq+0x188/0x4b5 [ 34.527015] irq_exit+0x151/0x180 [ 34.527417] do_IRQ+0xdb/0x150 [ 34.527783] common_interrupt+0xf/0xf [ 34.528223] This patch makes sure that skb->prev is set to NULL when entering netem_enqueue. Cc: Prashant Bhole Cc: Tyler Hicks Cc: Eric Dumazet Fixes: 68d2f84a1368 ("net: gro: properly remove skb from list") Suggested-by: Eric Dumazet Signed-off-by: Christoph Paasch Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_netem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index 3d325b840802..3f4f0b946798 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -436,6 +436,9 @@ static int netem_enqueue(struct sk_buff *skb, struct Qdisc *sch, int count = 1; int rc = NET_XMIT_SUCCESS; + /* Do not fool qdisc_drop_all() */ + skb->prev = NULL; + /* Random duplication */ if (q->duplicate && q->duplicate >= get_crandom(&q->dup_cor)) ++count; -- GitLab From 22fa15e6f5b7b0cdf5ccd6beb5e2bf48aa6ac306 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 4 Dec 2018 09:40:35 -0800 Subject: [PATCH 0456/1286] rtnetlink: ndo_dflt_fdb_dump() only work for ARPHRD_ETHER devices [ Upstream commit 688838934c231bb08f46db687e57f6d8bf82709c ] kmsan was able to trigger a kernel-infoleak using a gre device [1] nlmsg_populate_fdb_fill() has a hard coded assumption that dev->addr_len is ETH_ALEN, as normally guaranteed for ARPHRD_ETHER devices. A similar issue was fixed recently in commit da71577545a5 ("rtnetlink: Disallow FDB configuration for non-Ethernet device") [1] BUG: KMSAN: kernel-infoleak in copyout lib/iov_iter.c:143 [inline] BUG: KMSAN: kernel-infoleak in _copy_to_iter+0x4c0/0x2700 lib/iov_iter.c:576 CPU: 0 PID: 6697 Comm: syz-executor310 Not tainted 4.20.0-rc3+ #95 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x32d/0x480 lib/dump_stack.c:113 kmsan_report+0x12c/0x290 mm/kmsan/kmsan.c:683 kmsan_internal_check_memory+0x32a/0xa50 mm/kmsan/kmsan.c:743 kmsan_copy_to_user+0x78/0xd0 mm/kmsan/kmsan_hooks.c:634 copyout lib/iov_iter.c:143 [inline] _copy_to_iter+0x4c0/0x2700 lib/iov_iter.c:576 copy_to_iter include/linux/uio.h:143 [inline] skb_copy_datagram_iter+0x4e2/0x1070 net/core/datagram.c:431 skb_copy_datagram_msg include/linux/skbuff.h:3316 [inline] netlink_recvmsg+0x6f9/0x19d0 net/netlink/af_netlink.c:1975 sock_recvmsg_nosec net/socket.c:794 [inline] sock_recvmsg+0x1d1/0x230 net/socket.c:801 ___sys_recvmsg+0x444/0xae0 net/socket.c:2278 __sys_recvmsg net/socket.c:2327 [inline] __do_sys_recvmsg net/socket.c:2337 [inline] __se_sys_recvmsg+0x2fa/0x450 net/socket.c:2334 __x64_sys_recvmsg+0x4a/0x70 net/socket.c:2334 do_syscall_64+0xcf/0x110 arch/x86/entry/common.c:291 entry_SYSCALL_64_after_hwframe+0x63/0xe7 RIP: 0033:0x441119 Code: 18 89 d0 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 0f 83 db 0a fc ff c3 66 2e 0f 1f 84 00 00 00 00 RSP: 002b:00007fffc7f008a8 EFLAGS: 00000207 ORIG_RAX: 000000000000002f RAX: ffffffffffffffda RBX: 00000000004002c8 RCX: 0000000000441119 RDX: 0000000000000040 RSI: 00000000200005c0 RDI: 0000000000000003 RBP: 00000000006cc018 R08: 0000000000000100 R09: 0000000000000100 R10: 0000000000000100 R11: 0000000000000207 R12: 0000000000402080 R13: 0000000000402110 R14: 0000000000000000 R15: 0000000000000000 Uninit was stored to memory at: kmsan_save_stack_with_flags mm/kmsan/kmsan.c:246 [inline] kmsan_save_stack mm/kmsan/kmsan.c:261 [inline] kmsan_internal_chain_origin+0x13d/0x240 mm/kmsan/kmsan.c:469 kmsan_memcpy_memmove_metadata+0x1a9/0xf70 mm/kmsan/kmsan.c:344 kmsan_memcpy_metadata+0xb/0x10 mm/kmsan/kmsan.c:362 __msan_memcpy+0x61/0x70 mm/kmsan/kmsan_instr.c:162 __nla_put lib/nlattr.c:744 [inline] nla_put+0x20a/0x2d0 lib/nlattr.c:802 nlmsg_populate_fdb_fill+0x444/0x810 net/core/rtnetlink.c:3466 nlmsg_populate_fdb net/core/rtnetlink.c:3775 [inline] ndo_dflt_fdb_dump+0x73a/0x960 net/core/rtnetlink.c:3807 rtnl_fdb_dump+0x1318/0x1cb0 net/core/rtnetlink.c:3979 netlink_dump+0xc79/0x1c90 net/netlink/af_netlink.c:2244 __netlink_dump_start+0x10c4/0x11d0 net/netlink/af_netlink.c:2352 netlink_dump_start include/linux/netlink.h:216 [inline] rtnetlink_rcv_msg+0x141b/0x1540 net/core/rtnetlink.c:4910 netlink_rcv_skb+0x394/0x640 net/netlink/af_netlink.c:2477 rtnetlink_rcv+0x50/0x60 net/core/rtnetlink.c:4965 netlink_unicast_kernel net/netlink/af_netlink.c:1310 [inline] netlink_unicast+0x1699/0x1740 net/netlink/af_netlink.c:1336 netlink_sendmsg+0x13c7/0x1440 net/netlink/af_netlink.c:1917 sock_sendmsg_nosec net/socket.c:621 [inline] sock_sendmsg net/socket.c:631 [inline] ___sys_sendmsg+0xe3b/0x1240 net/socket.c:2116 __sys_sendmsg net/socket.c:2154 [inline] __do_sys_sendmsg net/socket.c:2163 [inline] __se_sys_sendmsg+0x305/0x460 net/socket.c:2161 __x64_sys_sendmsg+0x4a/0x70 net/socket.c:2161 do_syscall_64+0xcf/0x110 arch/x86/entry/common.c:291 entry_SYSCALL_64_after_hwframe+0x63/0xe7 Uninit was created at: kmsan_save_stack_with_flags mm/kmsan/kmsan.c:246 [inline] kmsan_internal_poison_shadow+0x6d/0x130 mm/kmsan/kmsan.c:170 kmsan_kmalloc+0xa1/0x100 mm/kmsan/kmsan_hooks.c:186 __kmalloc+0x14c/0x4d0 mm/slub.c:3825 kmalloc include/linux/slab.h:551 [inline] __hw_addr_create_ex net/core/dev_addr_lists.c:34 [inline] __hw_addr_add_ex net/core/dev_addr_lists.c:80 [inline] __dev_mc_add+0x357/0x8a0 net/core/dev_addr_lists.c:670 dev_mc_add+0x6d/0x80 net/core/dev_addr_lists.c:687 ip_mc_filter_add net/ipv4/igmp.c:1128 [inline] igmp_group_added+0x4d4/0xb80 net/ipv4/igmp.c:1311 __ip_mc_inc_group+0xea9/0xf70 net/ipv4/igmp.c:1444 ip_mc_inc_group net/ipv4/igmp.c:1453 [inline] ip_mc_up+0x1c3/0x400 net/ipv4/igmp.c:1775 inetdev_event+0x1d03/0x1d80 net/ipv4/devinet.c:1522 notifier_call_chain kernel/notifier.c:93 [inline] __raw_notifier_call_chain kernel/notifier.c:394 [inline] raw_notifier_call_chain+0x13d/0x240 kernel/notifier.c:401 __dev_notify_flags+0x3da/0x860 net/core/dev.c:1733 dev_change_flags+0x1ac/0x230 net/core/dev.c:7569 do_setlink+0x165f/0x5ea0 net/core/rtnetlink.c:2492 rtnl_newlink+0x2ad7/0x35a0 net/core/rtnetlink.c:3111 rtnetlink_rcv_msg+0x1148/0x1540 net/core/rtnetlink.c:4947 netlink_rcv_skb+0x394/0x640 net/netlink/af_netlink.c:2477 rtnetlink_rcv+0x50/0x60 net/core/rtnetlink.c:4965 netlink_unicast_kernel net/netlink/af_netlink.c:1310 [inline] netlink_unicast+0x1699/0x1740 net/netlink/af_netlink.c:1336 netlink_sendmsg+0x13c7/0x1440 net/netlink/af_netlink.c:1917 sock_sendmsg_nosec net/socket.c:621 [inline] sock_sendmsg net/socket.c:631 [inline] ___sys_sendmsg+0xe3b/0x1240 net/socket.c:2116 __sys_sendmsg net/socket.c:2154 [inline] __do_sys_sendmsg net/socket.c:2163 [inline] __se_sys_sendmsg+0x305/0x460 net/socket.c:2161 __x64_sys_sendmsg+0x4a/0x70 net/socket.c:2161 do_syscall_64+0xcf/0x110 arch/x86/entry/common.c:291 entry_SYSCALL_64_after_hwframe+0x63/0xe7 Bytes 36-37 of 105 are uninitialized Memory access of size 105 starts at ffff88819686c000 Data copied to user address 0000000020000380 Fixes: d83b06036048 ("net: add fdb generic dump routine") Signed-off-by: Eric Dumazet Cc: John Fastabend Cc: Ido Schimmel Cc: David Ahern Reviewed-by: Ido Schimmel Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/core/rtnetlink.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index c392a77ff788..925af6b43017 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -3280,6 +3280,9 @@ int ndo_dflt_fdb_dump(struct sk_buff *skb, { int err; + if (dev->type != ARPHRD_ETHER) + return -EINVAL; + netif_addr_lock_bh(dev); err = nlmsg_populate_fdb(skb, cb, dev, idx, &dev->uc); if (err) -- GitLab From 862b5ab951551cd14ee13c8ab0bde21b63b93bd6 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 1 Dec 2018 01:36:59 +0800 Subject: [PATCH 0457/1286] sctp: kfree_rcu asoc [ Upstream commit fb6df5a6234c38a9c551559506a49a677ac6f07a ] In sctp_hash_transport/sctp_epaddr_lookup_transport, it dereferences a transport's asoc under rcu_read_lock while asoc is freed not after a grace period, which leads to a use-after-free panic. This patch fixes it by calling kfree_rcu to make asoc be freed after a grace period. Note that only the asoc's memory is delayed to free in the patch, it won't cause sk to linger longer. Thanks Neil and Marcelo to make this clear. Fixes: 7fda702f9315 ("sctp: use new rhlist interface on sctp transport rhashtable") Fixes: cd2b70875058 ("sctp: check duplicate node before inserting a new transport") Reported-by: syzbot+0b05d8aa7cb185107483@syzkaller.appspotmail.com Reported-by: syzbot+aad231d51b1923158444@syzkaller.appspotmail.com Suggested-by: Neil Horman Signed-off-by: Xin Long Acked-by: Marcelo Ricardo Leitner Acked-by: Neil Horman Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- include/net/sctp/structs.h | 2 ++ net/sctp/associola.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 8e1e1dc490fd..94c775773f58 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -1902,6 +1902,8 @@ struct sctp_association { __u64 abandoned_unsent[SCTP_PR_INDEX(MAX) + 1]; __u64 abandoned_sent[SCTP_PR_INDEX(MAX) + 1]; + + struct rcu_head rcu; }; diff --git a/net/sctp/associola.c b/net/sctp/associola.c index 4982b31fec8e..23fec3817e0c 100644 --- a/net/sctp/associola.c +++ b/net/sctp/associola.c @@ -432,7 +432,7 @@ static void sctp_association_destroy(struct sctp_association *asoc) WARN_ON(atomic_read(&asoc->rmem_alloc)); - kfree(asoc); + kfree_rcu(asoc, rcu); SCTP_DBG_OBJCNT_DEC(assoc); } -- GitLab From 5567e5fefaa904d051ce03a330183125f92d2d37 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 5 Dec 2018 14:24:31 -0800 Subject: [PATCH 0458/1286] tcp: Do not underestimate rwnd_limited [ Upstream commit 41727549de3e7281feb174d568c6e46823db8684 ] If available rwnd is too small, tcp_tso_should_defer() can decide it is worth waiting before splitting a TSO packet. This really means we are rwnd limited. Fixes: 5615f88614a4 ("tcp: instrument how long TCP is limited by receive window") Signed-off-by: Eric Dumazet Acked-by: Soheil Hassas Yeganeh Reviewed-by: Yuchung Cheng Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp_output.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index b2ead31afcba..12cd64382768 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -2328,8 +2328,11 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle, } else { if (!push_one && tcp_tso_should_defer(sk, skb, &is_cwnd_limited, - max_segs)) + max_segs)) { + if (!is_cwnd_limited) + is_rwnd_limited = true; break; + } } limit = mss_now; -- GitLab From 6293016fbd9ba1b5ecc7d1afe67fb359d4c05512 Mon Sep 17 00:00:00 2001 From: Yuchung Cheng Date: Wed, 5 Dec 2018 14:38:38 -0800 Subject: [PATCH 0459/1286] tcp: fix NULL ref in tail loss probe [ Upstream commit b2b7af861122a0c0f6260155c29a1b2e594cd5b5 ] TCP loss probe timer may fire when the retranmission queue is empty but has a non-zero tp->packets_out counter. tcp_send_loss_probe will call tcp_rearm_rto which triggers NULL pointer reference by fetching the retranmission queue head in its sub-routines. Add a more detailed warning to help catch the root cause of the inflight accounting inconsistency. Reported-by: Rafael Tinoco Signed-off-by: Yuchung Cheng Signed-off-by: Eric Dumazet Signed-off-by: Neal Cardwell Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp_output.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 12cd64382768..1b31b0a1c7fa 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -2476,14 +2476,18 @@ void tcp_send_loss_probe(struct sock *sk) skb = tcp_write_queue_tail(sk); } + if (unlikely(!skb)) { + WARN_ONCE(tp->packets_out, + "invalid inflight: %u state %u cwnd %u mss %d\n", + tp->packets_out, sk->sk_state, tp->snd_cwnd, mss); + inet_csk(sk)->icsk_pending = 0; + return; + } + /* At most one outstanding TLP retransmission. */ if (tp->tlp_high_seq) goto rearm_timer; - /* Retransmit last segment. */ - if (WARN_ON(!skb)) - goto rearm_timer; - if (skb_still_in_host_queue(sk, skb)) goto rearm_timer; -- GitLab From 1d2cda4e8ffef837ff0f780633d536eb233a14d5 Mon Sep 17 00:00:00 2001 From: Nicolas Dichtel Date: Thu, 29 Nov 2018 14:45:39 +0100 Subject: [PATCH 0460/1286] tun: forbid iface creation with rtnl ops [ Upstream commit 35b827b6d06199841a83839e8bb69c0cd13a28be ] It's not supported right now (the goal of the initial patch was to support 'ip link del' only). Before the patch: $ ip link add foo type tun [ 239.632660] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [snip] [ 239.636410] RIP: 0010:register_netdevice+0x8e/0x3a0 This panic occurs because dev->netdev_ops is not set by tun_setup(). But to have something usable, it will require more than just setting netdev_ops. Fixes: f019a7a594d9 ("tun: Implement ip link del tunXXX") CC: Eric W. Biederman Signed-off-by: Nicolas Dichtel Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/tun.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 0a008d136aae..2956bb6cda72 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1818,9 +1818,9 @@ static void tun_setup(struct net_device *dev) static int tun_validate(struct nlattr *tb[], struct nlattr *data[], struct netlink_ext_ack *extack) { - if (!data) - return 0; - return -EINVAL; + NL_SET_ERR_MSG(extack, + "tun/tap creation via rtnetlink is not supported."); + return -EOPNOTSUPP; } static struct rtnl_link_ops tun_link_ops __read_mostly = { -- GitLab From 520e8609ecf23a3a3ac4ba88f084cb11d00f082f Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 29 Nov 2018 13:53:16 +0800 Subject: [PATCH 0461/1286] virtio-net: keep vnet header zeroed after processing XDP [ Upstream commit 436c9453a1ac0944b82870ef2e0d9be956b396d9 ] We copy vnet header unconditionally in page_to_skb() this is wrong since XDP may modify the packet data. So let's keep a zeroed vnet header for not confusing the conversion between vnet header and skb metadata. In the future, we should able to detect whether or not the packet was modified and keep using the vnet header when packet was not touched. Fixes: f600b6905015 ("virtio_net: Add XDP support") Reported-by: Pavel Popa Signed-off-by: Jason Wang Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/virtio_net.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 0e8e3be50332..215696f21d67 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -309,7 +309,8 @@ static unsigned int mergeable_ctx_to_truesize(void *mrg_ctx) static struct sk_buff *page_to_skb(struct virtnet_info *vi, struct receive_queue *rq, struct page *page, unsigned int offset, - unsigned int len, unsigned int truesize) + unsigned int len, unsigned int truesize, + bool hdr_valid) { struct sk_buff *skb; struct virtio_net_hdr_mrg_rxbuf *hdr; @@ -331,7 +332,8 @@ static struct sk_buff *page_to_skb(struct virtnet_info *vi, else hdr_padded_len = sizeof(struct padded_vnet_hdr); - memcpy(hdr, p, hdr_len); + if (hdr_valid) + memcpy(hdr, p, hdr_len); len -= hdr_len; offset += hdr_padded_len; @@ -594,7 +596,8 @@ static struct sk_buff *receive_big(struct net_device *dev, unsigned int len) { struct page *page = buf; - struct sk_buff *skb = page_to_skb(vi, rq, page, 0, len, PAGE_SIZE); + struct sk_buff *skb = page_to_skb(vi, rq, page, 0, len, + PAGE_SIZE, true); if (unlikely(!skb)) goto err; @@ -678,7 +681,8 @@ static struct sk_buff *receive_mergeable(struct net_device *dev, rcu_read_unlock(); put_page(page); head_skb = page_to_skb(vi, rq, xdp_page, - offset, len, PAGE_SIZE); + offset, len, + PAGE_SIZE, false); ewma_pkt_len_add(&rq->mrg_avg_pkt_len, len); return head_skb; } @@ -712,7 +716,7 @@ static struct sk_buff *receive_mergeable(struct net_device *dev, goto err_skb; } - head_skb = page_to_skb(vi, rq, page, offset, len, truesize); + head_skb = page_to_skb(vi, rq, page, offset, len, truesize, !xdp_prog); curr_skb = head_skb; if (unlikely(!curr_skb)) -- GitLab From 635e16fc7402e663c03f45e92df5aa6acdf079fc Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 17 Oct 2018 17:54:00 -0700 Subject: [PATCH 0462/1286] ARM: OMAP2+: prm44xx: Fix section annotation on omap44xx_prm_enable_io_wakeup [ Upstream commit eef3dc34a1e0b01d53328b88c25237bcc7323777 ] When building the kernel with Clang, the following section mismatch warning appears: WARNING: vmlinux.o(.text+0x38b3c): Section mismatch in reference from the function omap44xx_prm_late_init() to the function .init.text:omap44xx_prm_enable_io_wakeup() The function omap44xx_prm_late_init() references the function __init omap44xx_prm_enable_io_wakeup(). This is often because omap44xx_prm_late_init lacks a __init annotation or the annotation of omap44xx_prm_enable_io_wakeup is wrong. Remove the __init annotation from omap44xx_prm_enable_io_wakeup so there is no more mismatch. Signed-off-by: Nathan Chancellor Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/mach-omap2/prm44xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 1c0c1663f078..5affa9f5300b 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -344,7 +344,7 @@ static void omap44xx_prm_reconfigure_io_chain(void) * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and * omap44xx_prm_reconfigure_io_chain() must be called. No return value. */ -static void __init omap44xx_prm_enable_io_wakeup(void) +static void omap44xx_prm_enable_io_wakeup(void) { s32 inst = omap4_prmst_get_prm_dev_inst(); -- GitLab From b34888a95334876d971199f94a0f44e818b4a396 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 31 Oct 2018 00:48:12 +0000 Subject: [PATCH 0463/1286] ASoC: rsnd: fixup clock start checker [ Upstream commit 3ee9a76a8c5a10e1bfb04b81db767c6d562ddaf3 ] commit 4d230d12710646 ("ASoC: rsnd: fixup not to call clk_get/set under non-atomic") fixuped clock start timing. But it exchanged clock start checker from ssi->usrcnt to ssi->rate. Current rsnd_ssi_master_clk_start() is called from .prepare, but some player (for example GStreamer) might calls it many times. In such case, the checker might returns error even though it was not error. It should check ssi->usrcnt instead of ssi->rate. This patch fixup it. Without this patch, GStreamer can't switch 48kHz / 44.1kHz. Reported-by: Yusuke Goda Signed-off-by: Kuninori Morimoto Tested-by: Yusuke Goda Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/sh/rcar/ssi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c index 34223c8c28a8..0db2791f7035 100644 --- a/sound/soc/sh/rcar/ssi.c +++ b/sound/soc/sh/rcar/ssi.c @@ -280,7 +280,7 @@ static int rsnd_ssi_master_clk_start(struct rsnd_mod *mod, if (rsnd_ssi_is_multi_slave(mod, io)) return 0; - if (ssi->rate) { + if (ssi->usrcnt > 1) { if (ssi->rate != rate) { dev_err(dev, "SSI parent/child should use same rate\n"); return -EINVAL; -- GitLab From f55ad8d2a215da47b4f1a265a4b1b850ba7167a1 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 17 Oct 2018 10:15:34 +0200 Subject: [PATCH 0464/1286] staging: rtl8723bs: Fix the return value in case of error in 'rtw_wx_read32()' [ Upstream commit c3e43d8b958bd6849817393483e805d8638a8ab7 ] We return 0 unconditionally in 'rtw_wx_read32()'. However, 'ret' is set to some error codes in several error handling paths. Return 'ret' instead to propagate the error code. Fixes: 554c0a3abf216 ("staging: Add rtl8723bs sdio wifi driver") Signed-off-by: Christophe JAILLET Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/staging/rtl8723bs/os_dep/ioctl_linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c index d5e5f830f2a1..1b61da61690b 100644 --- a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c +++ b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c @@ -2383,7 +2383,7 @@ static int rtw_wx_read32(struct net_device *dev, exit: kfree(ptmp); - return 0; + return ret; } static int rtw_wx_write32(struct net_device *dev, -- GitLab From 5b2afd6261aeaf17da4953e07b731ca71bcabd17 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 Oct 2018 15:29:27 -0500 Subject: [PATCH 0465/1286] ARM: dts: logicpd-somlv: Fix interrupt on mmc3_dat1 [ Upstream commit 3d8b804bc528d3720ec0c39c212af92dafaf6e84 ] The interrupt on mmc3_dat1 is wrong which prevents this from appearing in /proc/interrupts. Fixes: ab8dd3aed011 ("ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV") #Kernel 4.9+ Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/boot/dts/logicpd-som-lv.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index c335b923753a..a7883676f675 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -123,7 +123,7 @@ }; &mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; + interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; pinctrl-0 = <&mmc3_pins &wl127x_gpio>; pinctrl-names = "default"; vmmc-supply = <&wl12xx_vmmc>; -- GitLab From 21ffeda14e83665ccd350005e3d51fdb0793d248 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Wed, 7 Nov 2018 22:30:31 +0100 Subject: [PATCH 0466/1286] ARM: OMAP1: ams-delta: Fix possible use of uninitialized field [ Upstream commit cec83ff1241ec98113a19385ea9e9cfa9aa4125b ] While playing with initialization order of modem device, it has been discovered that under some circumstances (early console init, I believe) its .pm() callback may be called before the uart_port->private_data pointer is initialized from plat_serial8250_port->private_data, resulting in NULL pointer dereference. Fix it by checking for uninitialized pointer before using it in modem_pm(). Fixes: aabf31737a6a ("ARM: OMAP1: ams-delta: update the modem to use regulator API") Signed-off-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/mach-omap1/board-ams-delta.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 6cbc69c92913..4174fa86bfb1 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -512,6 +512,9 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old) struct modem_private_data *priv = port->private_data; int ret; + if (!priv) + return; + if (IS_ERR(priv->regulator)) return; -- GitLab From 2ac368e8d504d66c315483b16cb9a3750b4cfb15 Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Sat, 10 Nov 2018 04:13:24 +0000 Subject: [PATCH 0467/1286] sysv: return 'err' instead of 0 in __sysv_write_inode [ Upstream commit c4b7d1ba7d263b74bb72e9325262a67139605cde ] Fixes gcc '-Wunused-but-set-variable' warning: fs/sysv/inode.c: In function '__sysv_write_inode': fs/sysv/inode.c:239:6: warning: variable 'err' set but not used [-Wunused-but-set-variable] __sysv_write_inode should return 'err' instead of 0 Fixes: 05459ca81ac3 ("repair sysv_write_inode(), switch sysv to simple_fsync()") Signed-off-by: YueHaibing Signed-off-by: Al Viro Signed-off-by: Sasha Levin --- fs/sysv/inode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/sysv/inode.c b/fs/sysv/inode.c index 3c47b7d5d4cf..9e0874d1524c 100644 --- a/fs/sysv/inode.c +++ b/fs/sysv/inode.c @@ -275,7 +275,7 @@ static int __sysv_write_inode(struct inode *inode, int wait) } } brelse(bh); - return 0; + return err; } int sysv_write_inode(struct inode *inode, struct writeback_control *wbc) -- GitLab From cae5446b33f65162fe21fdb633a63619633e7ea1 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Wed, 31 Oct 2018 18:26:21 +0100 Subject: [PATCH 0468/1286] selftests: add script to stress-test nft packet path vs. control plane [ Upstream commit 25d8bcedbf4329895dbaf9dd67baa6f18dad918c ] Start flood ping for each cpu while loading/flushing rulesets to make sure we do not access already-free'd rules from nf_tables evaluation loop. Also add this to TARGETS so 'make run_tests' in selftest dir runs it automatically. This would have caught the bug fixed in previous change ("netfilter: nf_tables: do not skip inactive chains during generation update") sooner. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- tools/testing/selftests/Makefile | 1 + tools/testing/selftests/netfilter/Makefile | 6 ++ tools/testing/selftests/netfilter/config | 2 + .../selftests/netfilter/nft_trans_stress.sh | 78 +++++++++++++++++++ 4 files changed, 87 insertions(+) create mode 100644 tools/testing/selftests/netfilter/Makefile create mode 100644 tools/testing/selftests/netfilter/config create mode 100755 tools/testing/selftests/netfilter/nft_trans_stress.sh diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index ea300e7818a7..10b89f5b9af7 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -20,6 +20,7 @@ TARGETS += memory-hotplug TARGETS += mount TARGETS += mqueue TARGETS += net +TARGETS += netfilter TARGETS += nsfs TARGETS += powerpc TARGETS += pstore diff --git a/tools/testing/selftests/netfilter/Makefile b/tools/testing/selftests/netfilter/Makefile new file mode 100644 index 000000000000..47ed6cef93fb --- /dev/null +++ b/tools/testing/selftests/netfilter/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for netfilter selftests + +TEST_PROGS := nft_trans_stress.sh + +include ../lib.mk diff --git a/tools/testing/selftests/netfilter/config b/tools/testing/selftests/netfilter/config new file mode 100644 index 000000000000..1017313e41a8 --- /dev/null +++ b/tools/testing/selftests/netfilter/config @@ -0,0 +1,2 @@ +CONFIG_NET_NS=y +NF_TABLES_INET=y diff --git a/tools/testing/selftests/netfilter/nft_trans_stress.sh b/tools/testing/selftests/netfilter/nft_trans_stress.sh new file mode 100755 index 000000000000..f1affd12c4b1 --- /dev/null +++ b/tools/testing/selftests/netfilter/nft_trans_stress.sh @@ -0,0 +1,78 @@ +#!/bin/bash +# +# This test is for stress-testing the nf_tables config plane path vs. +# packet path processing: Make sure we never release rules that are +# still visible to other cpus. +# +# set -e + +# Kselftest framework requirement - SKIP code is 4. +ksft_skip=4 + +testns=testns1 +tables="foo bar baz quux" + +nft --version > /dev/null 2>&1 +if [ $? -ne 0 ];then + echo "SKIP: Could not run test without nft tool" + exit $ksft_skip +fi + +ip -Version > /dev/null 2>&1 +if [ $? -ne 0 ];then + echo "SKIP: Could not run test without ip tool" + exit $ksft_skip +fi + +tmp=$(mktemp) + +for table in $tables; do + echo add table inet "$table" >> "$tmp" + echo flush table inet "$table" >> "$tmp" + + echo "add chain inet $table INPUT { type filter hook input priority 0; }" >> "$tmp" + echo "add chain inet $table OUTPUT { type filter hook output priority 0; }" >> "$tmp" + for c in $(seq 1 400); do + chain=$(printf "chain%03u" "$c") + echo "add chain inet $table $chain" >> "$tmp" + done + + for c in $(seq 1 400); do + chain=$(printf "chain%03u" "$c") + for BASE in INPUT OUTPUT; do + echo "add rule inet $table $BASE counter jump $chain" >> "$tmp" + done + echo "add rule inet $table $chain counter return" >> "$tmp" + done +done + +ip netns add "$testns" +ip -netns "$testns" link set lo up + +lscpu | grep ^CPU\(s\): | ( read cpu cpunum ; +cpunum=$((cpunum-1)) +for i in $(seq 0 $cpunum);do + mask=$(printf 0x%x $((1<<$i))) + ip netns exec "$testns" taskset $mask ping -4 127.0.0.1 -fq > /dev/null & + ip netns exec "$testns" taskset $mask ping -6 ::1 -fq > /dev/null & +done) + +sleep 1 + +for i in $(seq 1 10) ; do ip netns exec "$testns" nft -f "$tmp" & done + +for table in $tables;do + randsleep=$((RANDOM%10)) + sleep $randsleep + ip netns exec "$testns" nft delete table inet $table 2>/dev/null +done + +randsleep=$((RANDOM%10)) +sleep $randsleep + +pkill -9 ping + +wait + +rm -f "$tmp" +ip netns del "$testns" -- GitLab From 38e22947994de227bc1ac57ec82314c24a605605 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Mon, 12 Nov 2018 22:43:45 +0100 Subject: [PATCH 0469/1286] netfilter: nf_tables: fix use-after-free when deleting compat expressions [ Upstream commit 29e3880109e357fdc607b4393f8308cef6af9413 ] nft_compat ops do not have static storage duration, unlike all other expressions. When nf_tables_expr_destroy() returns, expr->ops might have been free'd already, so we need to store next address before calling expression destructor. For same reason, we can't deref match pointer after nft_xt_put(). This can be easily reproduced by adding msleep() before nft_match_destroy() returns. Fixes: 0ca743a55991 ("netfilter: nf_tables: add compatibility layer for x_tables") Reported-by: Pablo Neira Ayuso Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 5 +++-- net/netfilter/nft_compat.c | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 3ae365f92bff..ea1e57daf50e 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2252,7 +2252,7 @@ static int nf_tables_getrule(struct net *net, struct sock *nlsk, static void nf_tables_rule_destroy(const struct nft_ctx *ctx, struct nft_rule *rule) { - struct nft_expr *expr; + struct nft_expr *expr, *next; /* * Careful: some expressions might not be initialized in case this @@ -2260,8 +2260,9 @@ static void nf_tables_rule_destroy(const struct nft_ctx *ctx, */ expr = nft_expr_first(rule); while (expr != nft_expr_last(rule) && expr->ops) { + next = nft_expr_next(expr); nf_tables_expr_destroy(ctx, expr); - expr = nft_expr_next(expr); + expr = next; } kfree(rule); } diff --git a/net/netfilter/nft_compat.c b/net/netfilter/nft_compat.c index 6da1cec1494a..7533c2fd6b76 100644 --- a/net/netfilter/nft_compat.c +++ b/net/netfilter/nft_compat.c @@ -497,6 +497,7 @@ __nft_match_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr, void *info) { struct xt_match *match = expr->ops->data; + struct module *me = match->me; struct xt_mtdtor_param par; par.net = ctx->net; @@ -507,7 +508,7 @@ __nft_match_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr, par.match->destroy(&par); if (nft_xt_put(container_of(expr->ops, struct nft_xt, ops))) - module_put(match->me); + module_put(me); } static void -- GitLab From de2324a00979257c7fff8cf9f2bdc3023957fef8 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Fri, 9 Nov 2018 16:42:14 -0800 Subject: [PATCH 0470/1286] hwmon (ina2xx) Fix NULL id pointer in probe() [ Upstream commit 70df9ebbd82c794ddfbb49d45b337f18d5588dc2 ] When using DT configurations, the id pointer might turn out to be NULL. Then the driver encounters NULL pointer access: Unable to handle kernel read from unreadable memory at vaddr 00000018 [...] PC is at ina2xx_probe+0x114/0x200 LR is at ina2xx_probe+0x10c/0x200 [...] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b The reason is that i2c core returns the id pointer by matching id_table with client->name, while the client->name is actually using the name from the first string in the DT compatible list, not the best one. So i2c core would fail to match the id_table if the best matched compatible string isn't the first one, and then would return a NULL id pointer. This probably should be fixed in i2c core. But it doesn't hurt to make the driver robust. So this patch fixes it by using the "chip" that's added to unify both DT and non-DT configurations. Additionally, since id pointer could be null, so as id->name: ina2xx 10-0047: power monitor (null) (Rshunt = 1000 uOhm) ina2xx 10-0048: power monitor (null) (Rshunt = 10000 uOhm) So this patch also fixes NULL name pointer, using client->name to play safe and to align with hwmon->name. Fixes: bd0ddd4d0883 ("hwmon: (ina2xx) Add OF device ID table") Signed-off-by: Nicolin Chen Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/ina2xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index 71d3445ba869..c2252cf452f5 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -491,7 +491,7 @@ static int ina2xx_probe(struct i2c_client *client, } data->groups[group++] = &ina2xx_group; - if (id->driver_data == ina226) + if (chip == ina226) data->groups[group++] = &ina226_group; hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name, @@ -500,7 +500,7 @@ static int ina2xx_probe(struct i2c_client *client, return PTR_ERR(hwmon_dev); dev_info(dev, "power monitor %s (Rshunt = %li uOhm)\n", - id->name, data->rshunt); + client->name, data->rshunt); return 0; } -- GitLab From 5391e32b9d0692abb1996ba3c3fdf2e0c97b72e4 Mon Sep 17 00:00:00 2001 From: Richard Fitzgerald Date: Mon, 12 Nov 2018 13:36:38 +0000 Subject: [PATCH 0471/1286] ASoC: wm_adsp: Fix dma-unsafe read of scratch registers [ Upstream commit 20e00db2f59bdddf8a8e241473ef8be94631d3ae ] Stack memory isn't DMA-safe so it isn't safe to use either regmap_raw_read or regmap_bulk_read to read into stack memory. The two functions to read the scratch registers were using stack memory and regmap_raw_read. It's not worth allocating memory just for this trivial read, and it isn't time-critical. A simple regmap_read for each register is sufficient. Signed-off-by: Richard Fitzgerald Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/wm_adsp.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 989d093abda7..67330b6ab204 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -787,38 +787,41 @@ static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) { - u16 scratch[4]; + unsigned int scratch[4]; + unsigned int addr = dsp->base + ADSP2_SCRATCH0; + unsigned int i; int ret; - ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0, - scratch, sizeof(scratch)); - if (ret) { - adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); - return; + for (i = 0; i < ARRAY_SIZE(scratch); ++i) { + ret = regmap_read(dsp->regmap, addr + i, &scratch[i]); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); + return; + } } adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", - be16_to_cpu(scratch[0]), - be16_to_cpu(scratch[1]), - be16_to_cpu(scratch[2]), - be16_to_cpu(scratch[3])); + scratch[0], scratch[1], scratch[2], scratch[3]); } static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) { - u32 scratch[2]; + unsigned int scratch[2]; int ret; - ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1, - scratch, sizeof(scratch)); - + ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1, + &scratch[0]); if (ret) { - adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + adsp_err(dsp, "Failed to read SCRATCH0_1: %d\n", ret); return; } - scratch[0] = be32_to_cpu(scratch[0]); - scratch[1] = be32_to_cpu(scratch[1]); + ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH2_3, + &scratch[1]); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH2_3: %d\n", ret); + return; + } adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", scratch[0] & 0xFFFF, -- GitLab From 250dea0dfb12e2803d6de0105fae7177e4bd1b80 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Tue, 13 Nov 2018 15:38:22 +0000 Subject: [PATCH 0472/1286] s390/cpum_cf: Reject request for sampling in event initialization [ Upstream commit 613a41b0d16e617f46776a93b975a1eeea96417c ] On s390 command perf top fails [root@s35lp76 perf] # ./perf top -F100000 --stdio Error: cycles: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat' [root@s35lp76 perf] # Using event -e rb0000 works as designed. Event rb0000 is the event number of the sampling facility for basic sampling. During system start up the following PMUs are installed in the kernel's PMU list (from head to tail): cpum_cf --> s390 PMU counter facility device driver cpum_sf --> s390 PMU sampling facility device driver uprobe kprobe tracepoint task_clock cpu_clock Perf top executes following functions and calls perf_event_open(2) system call with different parameters many times: cmd_top --> __cmd_top --> perf_evlist__add_default --> __perf_evlist__add_default --> perf_evlist__new_cycles (creates event type:0 (HW) config 0 (CPU_CYCLES) --> perf_event_attr__set_max_precise_ip Uses perf_event_open(2) to detect correct precise_ip level. Fails 3 times on s390 which is ok. Then functions cmd_top --> __cmd_top --> perf_top__start_counters -->perf_evlist__config --> perf_can_comm_exec --> perf_probe_api This functions test support for the following events: "cycles:u", "instructions:u", "cpu-clock:u" using --> perf_do_probe_api --> perf_event_open_cloexec Test the close on exec flag support with perf_event_open(2). perf_do_probe_api returns true if the event is supported. The function returns true because event cpu-clock is supported by the PMU cpu_clock. This is achieved by many calls to perf_event_open(2). Function perf_top__start_counters now calls perf_evsel__open() for every event, which is the default event cpu_cycles (config:0) and type HARDWARE (type:0) which a predfined frequence of 4000. Given the above order of the PMU list, the PMU cpum_cf gets called first and returns 0, which indicates support for this sampling. The event is fully allocated in the function perf_event_open (file kernel/event/core.c near line 10521 and the following check fails: event = perf_event_alloc(&attr, cpu, task, group_leader, NULL, NULL, NULL, cgroup_fd); if (IS_ERR(event)) { err = PTR_ERR(event); goto err_cred; } if (is_sampling_event(event)) { if (event->pmu->capabilities & PERF_PMU_CAP_NO_INTERRUPT) { err = -EOPNOTSUPP; goto err_alloc; } } The check for the interrupt capabilities fails and the system call perf_event_open() returns -EOPNOTSUPP (-95). Add a check to return -ENODEV when sampling is requested in PMU cpum_cf. This allows common kernel code in the perf_event_open() system call to test the next PMU in above list. Fixes: 97b1198fece0 (" "s390, perf: Use common PMU interrupt disabled code") Signed-off-by: Thomas Richter Reviewed-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky Signed-off-by: Sasha Levin --- arch/s390/kernel/perf_cpum_cf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 61e91fee8467..edf6a61f0a64 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -349,6 +349,8 @@ static int __hw_perf_event_init(struct perf_event *event) break; case PERF_TYPE_HARDWARE: + if (is_sampling_event(event)) /* No sampling support */ + return -ENOENT; ev = attr->config; /* Count user space (problem-state) only */ if (!attr->exclude_user && attr->exclude_kernel) { -- GitLab From fd2c1ba142277bfd6f3488e6105c9eb643246ddc Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Tue, 13 Nov 2018 19:48:54 -0800 Subject: [PATCH 0473/1286] hwmon: (ina2xx) Fix current value calculation [ Upstream commit 38cd989ee38c16388cde89db5b734f9d55b905f9 ] The current register (04h) has a sign bit at MSB. The comments for this calculation also mention that it's a signed register. However, the regval is unsigned type so result of calculation turns out to be an incorrect value when current is negative. This patch simply fixes this by adding a casting to s16. Fixes: 5d389b125186c ("hwmon: (ina2xx) Make calibration register value fixed") Signed-off-by: Nicolin Chen Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/ina2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index c2252cf452f5..07ee19573b3f 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -274,7 +274,7 @@ static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, break; case INA2XX_CURRENT: /* signed register, result in mA */ - val = regval * data->current_lsb_uA; + val = (s16)regval * data->current_lsb_uA; val = DIV_ROUND_CLOSEST(val, 1000); break; case INA2XX_CALIBRATION: -- GitLab From b65b4228bdaa8e9d67d10a9206f84df9a20c292d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Nov 2018 14:58:20 +0200 Subject: [PATCH 0474/1286] ASoC: omap-abe-twl6040: Fix missing audio card caused by deferred probing [ Upstream commit 76836fd354922ebe4798a64fda01f8dc6a8b0984 ] The machine driver fails to probe in next-20181113 with: [ 2.539093] omap-abe-twl6040 sound: ASoC: CODEC DAI twl6040-legacy not registered [ 2.546630] omap-abe-twl6040 sound: devm_snd_soc_register_card() failed: -517 ... [ 3.693206] omap-abe-twl6040 sound: ASoC: Both platform name/of_node are set for TWL6040 [ 3.701446] omap-abe-twl6040 sound: ASoC: failed to init link TWL6040 [ 3.708007] omap-abe-twl6040 sound: devm_snd_soc_register_card() failed: -22 [ 3.715148] omap-abe-twl6040: probe of sound failed with error -22 Bisect pointed to a merge commit: first bad commit: [0f688ab20a540aafa984c5dbd68a71debebf4d7f] Merge remote-tracking branch 'net-next/master' and a diff between a working kernel does not reveal anything which would explain the change in behavior. Further investigation showed that on the second try of loading fails because the dai_link->platform is no longer NULL and it might be pointing to uninitialized memory. The fix is to move the snd_soc_dai_link and snd_soc_card inside of the abe_twl6040 struct, which is dynamically allocated every time the driver probes. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/omap/omap-abe-twl6040.c | 67 +++++++++++++------------------ 1 file changed, 29 insertions(+), 38 deletions(-) diff --git a/sound/soc/omap/omap-abe-twl6040.c b/sound/soc/omap/omap-abe-twl6040.c index 614b18d2f631..6fd143799534 100644 --- a/sound/soc/omap/omap-abe-twl6040.c +++ b/sound/soc/omap/omap-abe-twl6040.c @@ -36,6 +36,8 @@ #include "../codecs/twl6040.h" struct abe_twl6040 { + struct snd_soc_card card; + struct snd_soc_dai_link dai_links[2]; int jack_detection; /* board can detect jack events */ int mclk_freq; /* MCLK frequency speed for twl6040 */ }; @@ -208,40 +210,10 @@ static int omap_abe_dmic_init(struct snd_soc_pcm_runtime *rtd) ARRAY_SIZE(dmic_audio_map)); } -/* Digital audio interface glue - connects codec <--> CPU */ -static struct snd_soc_dai_link abe_twl6040_dai_links[] = { - { - .name = "TWL6040", - .stream_name = "TWL6040", - .codec_dai_name = "twl6040-legacy", - .codec_name = "twl6040-codec", - .init = omap_abe_twl6040_init, - .ops = &omap_abe_ops, - }, - { - .name = "DMIC", - .stream_name = "DMIC Capture", - .codec_dai_name = "dmic-hifi", - .codec_name = "dmic-codec", - .init = omap_abe_dmic_init, - .ops = &omap_abe_dmic_ops, - }, -}; - -/* Audio machine driver */ -static struct snd_soc_card omap_abe_card = { - .owner = THIS_MODULE, - - .dapm_widgets = twl6040_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(twl6040_dapm_widgets), - .dapm_routes = audio_map, - .num_dapm_routes = ARRAY_SIZE(audio_map), -}; - static int omap_abe_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - struct snd_soc_card *card = &omap_abe_card; + struct snd_soc_card *card; struct device_node *dai_node; struct abe_twl6040 *priv; int num_links = 0; @@ -252,12 +224,18 @@ static int omap_abe_probe(struct platform_device *pdev) return -ENODEV; } - card->dev = &pdev->dev; - priv = devm_kzalloc(&pdev->dev, sizeof(struct abe_twl6040), GFP_KERNEL); if (priv == NULL) return -ENOMEM; + card = &priv->card; + card->dev = &pdev->dev; + card->owner = THIS_MODULE; + card->dapm_widgets = twl6040_dapm_widgets; + card->num_dapm_widgets = ARRAY_SIZE(twl6040_dapm_widgets); + card->dapm_routes = audio_map; + card->num_dapm_routes = ARRAY_SIZE(audio_map); + if (snd_soc_of_parse_card_name(card, "ti,model")) { dev_err(&pdev->dev, "Card name is not provided\n"); return -ENODEV; @@ -274,14 +252,27 @@ static int omap_abe_probe(struct platform_device *pdev) dev_err(&pdev->dev, "McPDM node is not provided\n"); return -EINVAL; } - abe_twl6040_dai_links[0].cpu_of_node = dai_node; - abe_twl6040_dai_links[0].platform_of_node = dai_node; + + priv->dai_links[0].name = "DMIC"; + priv->dai_links[0].stream_name = "TWL6040"; + priv->dai_links[0].cpu_of_node = dai_node; + priv->dai_links[0].platform_of_node = dai_node; + priv->dai_links[0].codec_dai_name = "twl6040-legacy"; + priv->dai_links[0].codec_name = "twl6040-codec"; + priv->dai_links[0].init = omap_abe_twl6040_init; + priv->dai_links[0].ops = &omap_abe_ops; dai_node = of_parse_phandle(node, "ti,dmic", 0); if (dai_node) { num_links = 2; - abe_twl6040_dai_links[1].cpu_of_node = dai_node; - abe_twl6040_dai_links[1].platform_of_node = dai_node; + priv->dai_links[1].name = "TWL6040"; + priv->dai_links[1].stream_name = "DMIC Capture"; + priv->dai_links[1].cpu_of_node = dai_node; + priv->dai_links[1].platform_of_node = dai_node; + priv->dai_links[1].codec_dai_name = "dmic-hifi"; + priv->dai_links[1].codec_name = "dmic-codec"; + priv->dai_links[1].init = omap_abe_dmic_init; + priv->dai_links[1].ops = &omap_abe_dmic_ops; } else { num_links = 1; } @@ -300,7 +291,7 @@ static int omap_abe_probe(struct platform_device *pdev) return -ENODEV; } - card->dai_link = abe_twl6040_dai_links; + card->dai_link = priv->dai_links; card->num_links = num_links; snd_soc_card_set_drvdata(card, priv); -- GitLab From 55b648d1d624b9beced6384c8e2895b35dc69878 Mon Sep 17 00:00:00 2001 From: Tzung-Bi Shih Date: Wed, 14 Nov 2018 17:06:13 +0800 Subject: [PATCH 0475/1286] ASoC: dapm: Recalculate audio map forcely when card instantiated [ Upstream commit 882eab6c28d23a970ae73b7eb831b169a672d456 ] Audio map are possible in wrong state before card->instantiated has been set to true. Imaging the following examples: time 1: at the beginning in:-1 in:-1 in:-1 in:-1 out:-1 out:-1 out:-1 out:-1 SIGGEN A B Spk time 2: after someone called snd_soc_dapm_new_widgets() (e.g. create_fill_widget_route_map() in sound/soc/codecs/hdac_hdmi.c) in:1 in:0 in:0 in:0 out:0 out:0 out:0 out:1 SIGGEN A B Spk time 3: routes added in:1 in:0 in:0 in:0 out:0 out:0 out:0 out:1 SIGGEN -----> A -----> B ---> Spk In the end, the path should be powered on but it did not. At time 3, "in" of SIGGEN and "out" of Spk did not propagate to their neighbors because snd_soc_dapm_add_path() will not invalidate the paths if the card has not instantiated (i.e. card->instantiated is false). To correct the state of audio map, recalculate the whole map forcely. Signed-off-by: Tzung-Bi Shih Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/soc-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index fee4b0ef5566..42c2a3065b77 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -2307,6 +2307,7 @@ static int snd_soc_instantiate_card(struct snd_soc_card *card) } card->instantiated = 1; + dapm_mark_endpoints_dirty(card); snd_soc_dapm_sync(&card->dapm); mutex_unlock(&card->mutex); mutex_unlock(&client_mutex); -- GitLab From aa17c9c00ce006de2dd7b0eabed9e45b48d3d044 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2018 15:20:05 +0100 Subject: [PATCH 0476/1286] iio/hid-sensors: Fix IIO_CHAN_INFO_RAW returning wrong values for signed numbers [ Upstream commit 0145b50566e7de5637e80ecba96c7f0e6fff1aad ] Before this commit sensor_hub_input_attr_get_raw_value() failed to take the signedness of 16 and 8 bit values into account, returning e.g. 65436 instead of -100 for the z-axis reading of an accelerometer. This commit adds a new is_signed parameter to the function and makes all callers pass the appropriate value for this. While at it, this commit also fixes up some neighboring lines where statements were needlessly split over 2 lines to improve readability. Signed-off-by: Hans de Goede Acked-by: Srinivas Pandruvada Acked-by: Benjamin Tissoires Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/hid/hid-sensor-custom.c | 2 +- drivers/hid/hid-sensor-hub.c | 13 ++++++++++--- drivers/iio/accel/hid-sensor-accel-3d.c | 5 ++++- drivers/iio/gyro/hid-sensor-gyro-3d.c | 5 ++++- drivers/iio/humidity/hid-sensor-humidity.c | 3 ++- drivers/iio/light/hid-sensor-als.c | 8 +++++--- drivers/iio/light/hid-sensor-prox.c | 8 +++++--- drivers/iio/magnetometer/hid-sensor-magn-3d.c | 8 +++++--- drivers/iio/orientation/hid-sensor-incl-3d.c | 8 +++++--- drivers/iio/pressure/hid-sensor-press.c | 8 +++++--- drivers/iio/temperature/hid-sensor-temperature.c | 3 ++- drivers/rtc/rtc-hid-sensor-time.c | 2 +- include/linux/hid-sensor-hub.h | 4 +++- 13 files changed, 52 insertions(+), 25 deletions(-) diff --git a/drivers/hid/hid-sensor-custom.c b/drivers/hid/hid-sensor-custom.c index 0bcf041368c7..574126b649e9 100644 --- a/drivers/hid/hid-sensor-custom.c +++ b/drivers/hid/hid-sensor-custom.c @@ -358,7 +358,7 @@ static ssize_t show_value(struct device *dev, struct device_attribute *attr, sensor_inst->hsdev, sensor_inst->hsdev->usage, usage, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, false); } else if (!strncmp(name, "units", strlen("units"))) value = sensor_inst->fields[field_index].attribute.units; else if (!strncmp(name, "unit-expo", strlen("unit-expo"))) diff --git a/drivers/hid/hid-sensor-hub.c b/drivers/hid/hid-sensor-hub.c index faba542d1b07..b5bd5cb7d532 100644 --- a/drivers/hid/hid-sensor-hub.c +++ b/drivers/hid/hid-sensor-hub.c @@ -299,7 +299,8 @@ EXPORT_SYMBOL_GPL(sensor_hub_get_feature); int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev, u32 usage_id, u32 attr_usage_id, u32 report_id, - enum sensor_hub_read_flags flag) + enum sensor_hub_read_flags flag, + bool is_signed) { struct sensor_hub_data *data = hid_get_drvdata(hsdev->hdev); unsigned long flags; @@ -331,10 +332,16 @@ int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev, &hsdev->pending.ready, HZ*5); switch (hsdev->pending.raw_size) { case 1: - ret_val = *(u8 *)hsdev->pending.raw_data; + if (is_signed) + ret_val = *(s8 *)hsdev->pending.raw_data; + else + ret_val = *(u8 *)hsdev->pending.raw_data; break; case 2: - ret_val = *(u16 *)hsdev->pending.raw_data; + if (is_signed) + ret_val = *(s16 *)hsdev->pending.raw_data; + else + ret_val = *(u16 *)hsdev->pending.raw_data; break; case 4: ret_val = *(u32 *)hsdev->pending.raw_data; diff --git a/drivers/iio/accel/hid-sensor-accel-3d.c b/drivers/iio/accel/hid-sensor-accel-3d.c index 2238a26aba63..f573d9c61fc3 100644 --- a/drivers/iio/accel/hid-sensor-accel-3d.c +++ b/drivers/iio/accel/hid-sensor-accel-3d.c @@ -149,6 +149,7 @@ static int accel_3d_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; struct hid_sensor_hub_device *hsdev = accel_state->common_attributes.hsdev; @@ -158,12 +159,14 @@ static int accel_3d_read_raw(struct iio_dev *indio_dev, case 0: hid_sensor_power_state(&accel_state->common_attributes, true); report_id = accel_state->accel[chan->scan_index].report_id; + min = accel_state->accel[chan->scan_index].logical_minimum; address = accel_3d_addresses[chan->scan_index]; if (report_id >= 0) *val = sensor_hub_input_attr_get_raw_value( accel_state->common_attributes.hsdev, hsdev->usage, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); else { *val = 0; hid_sensor_power_state(&accel_state->common_attributes, diff --git a/drivers/iio/gyro/hid-sensor-gyro-3d.c b/drivers/iio/gyro/hid-sensor-gyro-3d.c index c67ce2ac4715..d9192eb41131 100644 --- a/drivers/iio/gyro/hid-sensor-gyro-3d.c +++ b/drivers/iio/gyro/hid-sensor-gyro-3d.c @@ -111,6 +111,7 @@ static int gyro_3d_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; @@ -118,13 +119,15 @@ static int gyro_3d_read_raw(struct iio_dev *indio_dev, case 0: hid_sensor_power_state(&gyro_state->common_attributes, true); report_id = gyro_state->gyro[chan->scan_index].report_id; + min = gyro_state->gyro[chan->scan_index].logical_minimum; address = gyro_3d_addresses[chan->scan_index]; if (report_id >= 0) *val = sensor_hub_input_attr_get_raw_value( gyro_state->common_attributes.hsdev, HID_USAGE_SENSOR_GYRO_3D, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); else { *val = 0; hid_sensor_power_state(&gyro_state->common_attributes, diff --git a/drivers/iio/humidity/hid-sensor-humidity.c b/drivers/iio/humidity/hid-sensor-humidity.c index 6e09c1acfe51..e53914d51ec3 100644 --- a/drivers/iio/humidity/hid-sensor-humidity.c +++ b/drivers/iio/humidity/hid-sensor-humidity.c @@ -75,7 +75,8 @@ static int humidity_read_raw(struct iio_dev *indio_dev, HID_USAGE_SENSOR_HUMIDITY, HID_USAGE_SENSOR_ATMOSPHERIC_HUMIDITY, humid_st->humidity_attr.report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + humid_st->humidity_attr.logical_minimum < 0); hid_sensor_power_state(&humid_st->common_attributes, false); return IIO_VAL_INT; diff --git a/drivers/iio/light/hid-sensor-als.c b/drivers/iio/light/hid-sensor-als.c index 059d964772c7..95ca86f50434 100644 --- a/drivers/iio/light/hid-sensor-als.c +++ b/drivers/iio/light/hid-sensor-als.c @@ -93,6 +93,7 @@ static int als_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; @@ -102,8 +103,8 @@ static int als_read_raw(struct iio_dev *indio_dev, case CHANNEL_SCAN_INDEX_INTENSITY: case CHANNEL_SCAN_INDEX_ILLUM: report_id = als_state->als_illum.report_id; - address = - HID_USAGE_SENSOR_LIGHT_ILLUM; + min = als_state->als_illum.logical_minimum; + address = HID_USAGE_SENSOR_LIGHT_ILLUM; break; default: report_id = -1; @@ -116,7 +117,8 @@ static int als_read_raw(struct iio_dev *indio_dev, als_state->common_attributes.hsdev, HID_USAGE_SENSOR_ALS, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); hid_sensor_power_state(&als_state->common_attributes, false); } else { diff --git a/drivers/iio/light/hid-sensor-prox.c b/drivers/iio/light/hid-sensor-prox.c index 73fced8a63b7..8c017abc4ee2 100644 --- a/drivers/iio/light/hid-sensor-prox.c +++ b/drivers/iio/light/hid-sensor-prox.c @@ -73,6 +73,7 @@ static int prox_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; @@ -81,8 +82,8 @@ static int prox_read_raw(struct iio_dev *indio_dev, switch (chan->scan_index) { case CHANNEL_SCAN_INDEX_PRESENCE: report_id = prox_state->prox_attr.report_id; - address = - HID_USAGE_SENSOR_HUMAN_PRESENCE; + min = prox_state->prox_attr.logical_minimum; + address = HID_USAGE_SENSOR_HUMAN_PRESENCE; break; default: report_id = -1; @@ -95,7 +96,8 @@ static int prox_read_raw(struct iio_dev *indio_dev, prox_state->common_attributes.hsdev, HID_USAGE_SENSOR_PROX, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); hid_sensor_power_state(&prox_state->common_attributes, false); } else { diff --git a/drivers/iio/magnetometer/hid-sensor-magn-3d.c b/drivers/iio/magnetometer/hid-sensor-magn-3d.c index 0e791b02ed4a..b495107bd173 100644 --- a/drivers/iio/magnetometer/hid-sensor-magn-3d.c +++ b/drivers/iio/magnetometer/hid-sensor-magn-3d.c @@ -163,21 +163,23 @@ static int magn_3d_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; switch (mask) { case 0: hid_sensor_power_state(&magn_state->magn_flux_attributes, true); - report_id = - magn_state->magn[chan->address].report_id; + report_id = magn_state->magn[chan->address].report_id; + min = magn_state->magn[chan->address].logical_minimum; address = magn_3d_addresses[chan->address]; if (report_id >= 0) *val = sensor_hub_input_attr_get_raw_value( magn_state->magn_flux_attributes.hsdev, HID_USAGE_SENSOR_COMPASS_3D, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); else { *val = 0; hid_sensor_power_state( diff --git a/drivers/iio/orientation/hid-sensor-incl-3d.c b/drivers/iio/orientation/hid-sensor-incl-3d.c index fd1b3696ee42..16c744bef021 100644 --- a/drivers/iio/orientation/hid-sensor-incl-3d.c +++ b/drivers/iio/orientation/hid-sensor-incl-3d.c @@ -111,21 +111,23 @@ static int incl_3d_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; switch (mask) { case IIO_CHAN_INFO_RAW: hid_sensor_power_state(&incl_state->common_attributes, true); - report_id = - incl_state->incl[chan->scan_index].report_id; + report_id = incl_state->incl[chan->scan_index].report_id; + min = incl_state->incl[chan->scan_index].logical_minimum; address = incl_3d_addresses[chan->scan_index]; if (report_id >= 0) *val = sensor_hub_input_attr_get_raw_value( incl_state->common_attributes.hsdev, HID_USAGE_SENSOR_INCLINOMETER_3D, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); else { hid_sensor_power_state(&incl_state->common_attributes, false); diff --git a/drivers/iio/pressure/hid-sensor-press.c b/drivers/iio/pressure/hid-sensor-press.c index 6848d8c80eff..1c49ef78f888 100644 --- a/drivers/iio/pressure/hid-sensor-press.c +++ b/drivers/iio/pressure/hid-sensor-press.c @@ -77,6 +77,7 @@ static int press_read_raw(struct iio_dev *indio_dev, int report_id = -1; u32 address; int ret_type; + s32 min; *val = 0; *val2 = 0; @@ -85,8 +86,8 @@ static int press_read_raw(struct iio_dev *indio_dev, switch (chan->scan_index) { case CHANNEL_SCAN_INDEX_PRESSURE: report_id = press_state->press_attr.report_id; - address = - HID_USAGE_SENSOR_ATMOSPHERIC_PRESSURE; + min = press_state->press_attr.logical_minimum; + address = HID_USAGE_SENSOR_ATMOSPHERIC_PRESSURE; break; default: report_id = -1; @@ -99,7 +100,8 @@ static int press_read_raw(struct iio_dev *indio_dev, press_state->common_attributes.hsdev, HID_USAGE_SENSOR_PRESSURE, address, report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + min < 0); hid_sensor_power_state(&press_state->common_attributes, false); } else { diff --git a/drivers/iio/temperature/hid-sensor-temperature.c b/drivers/iio/temperature/hid-sensor-temperature.c index c01efeca4002..6ed5cd5742f1 100644 --- a/drivers/iio/temperature/hid-sensor-temperature.c +++ b/drivers/iio/temperature/hid-sensor-temperature.c @@ -76,7 +76,8 @@ static int temperature_read_raw(struct iio_dev *indio_dev, HID_USAGE_SENSOR_TEMPERATURE, HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE, temp_st->temperature_attr.report_id, - SENSOR_HUB_SYNC); + SENSOR_HUB_SYNC, + temp_st->temperature_attr.logical_minimum < 0); hid_sensor_power_state( &temp_st->common_attributes, false); diff --git a/drivers/rtc/rtc-hid-sensor-time.c b/drivers/rtc/rtc-hid-sensor-time.c index 2751dba850c6..3e1abb455472 100644 --- a/drivers/rtc/rtc-hid-sensor-time.c +++ b/drivers/rtc/rtc-hid-sensor-time.c @@ -213,7 +213,7 @@ static int hid_rtc_read_time(struct device *dev, struct rtc_time *tm) /* get a report with all values through requesting one value */ sensor_hub_input_attr_get_raw_value(time_state->common_attributes.hsdev, HID_USAGE_SENSOR_TIME, hid_time_addresses[0], - time_state->info[0].report_id, SENSOR_HUB_SYNC); + time_state->info[0].report_id, SENSOR_HUB_SYNC, false); /* wait for all values (event) */ ret = wait_for_completion_killable_timeout( &time_state->comp_last_time, HZ*6); diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h index fc7aae64dcde..000de6da3b1b 100644 --- a/include/linux/hid-sensor-hub.h +++ b/include/linux/hid-sensor-hub.h @@ -177,6 +177,7 @@ int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev, * @attr_usage_id: Attribute usage id as per spec * @report_id: Report id to look for * @flag: Synchronous or asynchronous read +* @is_signed: If true then fields < 32 bits will be sign-extended * * Issues a synchronous or asynchronous read request for an input attribute. * Returns data upto 32 bits. @@ -190,7 +191,8 @@ enum sensor_hub_read_flags { int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev, u32 usage_id, u32 attr_usage_id, u32 report_id, - enum sensor_hub_read_flags flag + enum sensor_hub_read_flags flag, + bool is_signed ); /** -- GitLab From f500a4ef7e5d7feddee380edfb1a1d91fc8fa627 Mon Sep 17 00:00:00 2001 From: Taehee Yoo Date: Fri, 16 Nov 2018 21:32:35 +0900 Subject: [PATCH 0477/1286] netfilter: xt_hashlimit: fix a possible memory leak in htable_create() [ Upstream commit b4e955e9f372035361fbc6f07b21fe2cc6a5be4a ] In the htable_create(), hinfo is allocated by vmalloc() So that if error occurred, hinfo should be freed. Fixes: 11d5f15723c9 ("netfilter: xt_hashlimit: Create revision 2 to support higher pps rates") Signed-off-by: Taehee Yoo Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/xt_hashlimit.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/net/netfilter/xt_hashlimit.c b/net/netfilter/xt_hashlimit.c index 0c034597b9b8..fe8e8a1622b5 100644 --- a/net/netfilter/xt_hashlimit.c +++ b/net/netfilter/xt_hashlimit.c @@ -295,9 +295,10 @@ static int htable_create(struct net *net, struct hashlimit_cfg3 *cfg, /* copy match config into hashtable config */ ret = cfg_copy(&hinfo->cfg, (void *)cfg, 3); - - if (ret) + if (ret) { + vfree(hinfo); return ret; + } hinfo->cfg.size = size; if (hinfo->cfg.max == 0) @@ -814,7 +815,6 @@ hashlimit_mt_v1(const struct sk_buff *skb, struct xt_action_param *par) int ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 1); - if (ret) return ret; @@ -830,7 +830,6 @@ hashlimit_mt_v2(const struct sk_buff *skb, struct xt_action_param *par) int ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 2); - if (ret) return ret; @@ -920,7 +919,6 @@ static int hashlimit_mt_check_v1(const struct xt_mtchk_param *par) return ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 1); - if (ret) return ret; @@ -939,7 +937,6 @@ static int hashlimit_mt_check_v2(const struct xt_mtchk_param *par) return ret; ret = cfg_copy(&cfg, (void *)&info->cfg, 2); - if (ret) return ret; -- GitLab From ca0bcef7c60ba2cb12ca99e706adc3f024a4f8a7 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Thu, 15 Nov 2018 10:44:57 +0800 Subject: [PATCH 0478/1286] hwmon: (w83795) temp4_type has writable permission [ Upstream commit 09aaf6813cfca4c18034fda7a43e68763f34abb1 ] Both datasheet and comments of store_temp_mode() tell us that temp1~4_type is writable, so fix it. Signed-off-by: Yao Wang Signed-off-by: Huacai Chen Fixes: 39deb6993e7c (" hwmon: (w83795) Simplify temperature sensor type handling") Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/w83795.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/w83795.c b/drivers/hwmon/w83795.c index 49276bbdac3d..1bb80f992aa8 100644 --- a/drivers/hwmon/w83795.c +++ b/drivers/hwmon/w83795.c @@ -1691,7 +1691,7 @@ store_sf_setup(struct device *dev, struct device_attribute *attr, * somewhere else in the code */ #define SENSOR_ATTR_TEMP(index) { \ - SENSOR_ATTR_2(temp##index##_type, S_IRUGO | (index < 4 ? S_IWUSR : 0), \ + SENSOR_ATTR_2(temp##index##_type, S_IRUGO | (index < 5 ? S_IWUSR : 0), \ show_temp_mode, store_temp_mode, NOT_USED, index - 1), \ SENSOR_ATTR_2(temp##index##_input, S_IRUGO, show_temp, \ NULL, TEMP_READ, index - 1), \ -- GitLab From d36cc6073623904cfc937c649370b56bc0e7dd88 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Thu, 1 Nov 2018 18:00:01 +0100 Subject: [PATCH 0479/1286] perf tools: Restore proper cwd on return from mnt namespace [ Upstream commit b01c1f69c8660eaeab7d365cd570103c5c073a02 ] When reporting on 'record' server we try to retrieve/use the mnt namespace of the profiled tasks. We use following API with cookie to hold the return namespace, roughly: nsinfo__mountns_enter(struct nsinfo *nsi, struct nscookie *nc) setns(newns, 0); ... new ns related open.. ... nsinfo__mountns_exit(struct nscookie *nc) setns(nc->oldns) Once finished we setns to old namespace, which also sets the current working directory (cwd) to "/", trashing the cwd we had. This is mostly fine, because we use absolute paths almost everywhere, but it screws up 'perf diff': # perf diff failed to open perf.data: No such file or directory (try 'perf record' first) ... Adding the current working directory to be part of the cookie and restoring it in the nsinfo__mountns_exit call. Signed-off-by: Jiri Olsa Cc: Alexander Shishkin Cc: Krister Johansen Cc: Namhyung Kim Cc: Peter Zijlstra Fixes: 843ff37bb59e ("perf symbols: Find symbols in different mount namespace") Link: http://lkml.kernel.org/r/20181101170001.30019-1-jolsa@kernel.org [ No need to check for NULL args for free(), use zfree() for struct members ] Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/namespaces.c | 17 +++++++++++++++-- tools/perf/util/namespaces.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index 1ef0049860a8..eadc7ddacbf6 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -17,6 +17,7 @@ #include #include #include +#include struct namespaces *namespaces__new(struct namespaces_event *event) { @@ -185,6 +186,7 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, char curpath[PATH_MAX]; int oldns = -1; int newns = -1; + char *oldcwd = NULL; if (nc == NULL) return; @@ -198,9 +200,13 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, if (snprintf(curpath, PATH_MAX, "/proc/self/ns/mnt") >= PATH_MAX) return; + oldcwd = get_current_dir_name(); + if (!oldcwd) + return; + oldns = open(curpath, O_RDONLY); if (oldns < 0) - return; + goto errout; newns = open(nsi->mntns_path, O_RDONLY); if (newns < 0) @@ -209,11 +215,13 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, if (setns(newns, CLONE_NEWNS) < 0) goto errout; + nc->oldcwd = oldcwd; nc->oldns = oldns; nc->newns = newns; return; errout: + free(oldcwd); if (oldns > -1) close(oldns); if (newns > -1) @@ -222,11 +230,16 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, void nsinfo__mountns_exit(struct nscookie *nc) { - if (nc == NULL || nc->oldns == -1 || nc->newns == -1) + if (nc == NULL || nc->oldns == -1 || nc->newns == -1 || !nc->oldcwd) return; setns(nc->oldns, CLONE_NEWNS); + if (nc->oldcwd) { + WARN_ON_ONCE(chdir(nc->oldcwd)); + zfree(&nc->oldcwd); + } + if (nc->oldns > -1) { close(nc->oldns); nc->oldns = -1; diff --git a/tools/perf/util/namespaces.h b/tools/perf/util/namespaces.h index 05d82601c9a6..23584a6dd048 100644 --- a/tools/perf/util/namespaces.h +++ b/tools/perf/util/namespaces.h @@ -36,6 +36,7 @@ struct nsinfo { struct nscookie { int oldns; int newns; + char *oldcwd; }; int nsinfo__init(struct nsinfo *nsi); -- GitLab From 7d14117bd218a81f9f174af94b7c4f26aca16ad3 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Mon, 5 Nov 2018 18:11:36 +0000 Subject: [PATCH 0480/1286] PCI: imx6: Fix link training status detection in link up check [ Upstream commit 68bc10bf992180f269816ff3d22eb30383138577 ] This bug was introduced in the interaction for two commits on either branch of the merge commit 562df5c8521e ("Merge branch 'pci/host-designware' into next"). Commit 4d107d3b5a68 ("PCI: imx6: Move link up check into imx6_pcie_wait_for_link()"), changed imx6_pcie_wait_for_link() to poll the link status register directly, checking for link up and not training, and made imx6_pcie_link_up() only check the link up bit (once, not a polling loop). While commit 886bc5ceb5cc ("PCI: designware: Add generic dw_pcie_wait_for_link()"), replaced the loop in imx6_pcie_wait_for_link() with a call to a new dwc core function, which polled imx6_pcie_link_up(), which still checked both link up and not training in a loop. When these two commits were merged, the version of imx6_pcie_wait_for_link() from 886bc5ceb5cc was kept, which eliminated the link training check placed there by 4d107d3b5a68. However, the version of imx6_pcie_link_up() from 4d107d3b5a68 was kept, which eliminated the link training check that had been there and was moved to imx6_pcie_wait_for_link(). The result was the link training check got lost for the imx6 driver. Eliminate imx6_pcie_link_up() so that the default handler, dw_pcie_link_up(), is used instead. The default handler has the correct code, which checks for link up and also that it still is not training, fixing the regression. Fixes: 562df5c8521e ("Merge branch 'pci/host-designware' into next") Signed-off-by: Trent Piepho [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: Lorenzo Pieralisi Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Joao Pinto Cc: Lorenzo Pieralisi Cc: Richard Zhu Signed-off-by: Sasha Levin --- drivers/pci/dwc/pci-imx6.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index b73483534a5b..1f1069b70e45 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -83,8 +83,6 @@ struct imx6_pcie { #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) -#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) -#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -653,12 +651,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp) return 0; } -static int imx6_pcie_link_up(struct dw_pcie *pci) -{ - return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) & - PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; -} - static const struct dw_pcie_host_ops imx6_pcie_host_ops = { .host_init = imx6_pcie_host_init, }; @@ -701,7 +693,7 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, } static const struct dw_pcie_ops dw_pcie_ops = { - .link_up = imx6_pcie_link_up, + /* No special ops needed, but pcie-designware still expects this struct */ }; static int imx6_pcie_probe(struct platform_device *pdev) -- GitLab From de21975e71fe3fbb96b42fe6155d8a74fc74e4ca Mon Sep 17 00:00:00 2001 From: Artem Savkov Date: Tue, 20 Nov 2018 11:52:15 -0600 Subject: [PATCH 0481/1286] objtool: Fix double-free in .cold detection error path [ Upstream commit 0b9301fb632f7111a3293a30cc5b20f1b82ed08d ] If read_symbols() fails during second list traversal (the one dealing with ".cold" subfunctions) it frees the symbol, but never deletes it from the list/hash_table resulting in symbol being freed again in elf_close(). Fix it by just returning an error, leaving cleanup to elf_close(). Signed-off-by: Artem Savkov Signed-off-by: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 13810435b9a7 ("objtool: Support GCC 8's cold subfunctions") Link: http://lkml.kernel.org/r/beac5a9b7da9e8be90223459dcbe07766ae437dd.1542736240.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- tools/objtool/elf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c index 0d1acb704f64..3616d626991e 100644 --- a/tools/objtool/elf.c +++ b/tools/objtool/elf.c @@ -312,7 +312,7 @@ static int read_symbols(struct elf *elf) if (!pfunc) { WARN("%s(): can't find parent function", sym->name); - goto err; + return -1; } sym->pfunc = pfunc; -- GitLab From 5ce4164fff6735d7f26b3e465deb7133cea558e9 Mon Sep 17 00:00:00 2001 From: Artem Savkov Date: Tue, 20 Nov 2018 11:52:16 -0600 Subject: [PATCH 0482/1286] objtool: Fix segfault in .cold detection with -ffunction-sections [ Upstream commit 22566c1603030f0a036ad564634b064ad1a55db2 ] Because find_symbol_by_name() traverses the same lists as read_symbols(), changing sym->name in place without copying it affects the result of find_symbol_by_name(). In the case where a ".cold" function precedes its parent in sec->symbol_list, it can result in a function being considered a parent of itself. This leads to function length being set to 0 and other consequent side-effects including a segfault in add_switch_table(). The effects of this bug are only visible when building with -ffunction-sections in KCFLAGS. Fix by copying the search string instead of modifying it in place. Signed-off-by: Artem Savkov Signed-off-by: Josh Poimboeuf Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 13810435b9a7 ("objtool: Support GCC 8's cold subfunctions") Link: http://lkml.kernel.org/r/910abd6b5a4945130fd44f787c24e07b9e07c8da.1542736240.git.jpoimboe@redhat.com Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- tools/objtool/elf.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c index 3616d626991e..dd4ed7c3c062 100644 --- a/tools/objtool/elf.c +++ b/tools/objtool/elf.c @@ -31,6 +31,8 @@ #include "elf.h" #include "warn.h" +#define MAX_NAME_LEN 128 + struct section *find_section_by_name(struct elf *elf, const char *name) { struct section *sec; @@ -298,6 +300,8 @@ static int read_symbols(struct elf *elf) /* Create parent/child links for any cold subfunctions */ list_for_each_entry(sec, &elf->sections, list) { list_for_each_entry(sym, &sec->symbol_list, list) { + char pname[MAX_NAME_LEN + 1]; + size_t pnamelen; if (sym->type != STT_FUNC) continue; sym->pfunc = sym->cfunc = sym; @@ -305,9 +309,16 @@ static int read_symbols(struct elf *elf) if (!coldstr) continue; - coldstr[0] = '\0'; - pfunc = find_symbol_by_name(elf, sym->name); - coldstr[0] = '.'; + pnamelen = coldstr - sym->name; + if (pnamelen > MAX_NAME_LEN) { + WARN("%s(): parent function name exceeds maximum length of %d characters", + sym->name, MAX_NAME_LEN); + return -1; + } + + strncpy(pname, sym->name, pnamelen); + pname[pnamelen] = '\0'; + pfunc = find_symbol_by_name(elf, pname); if (!pfunc) { WARN("%s(): can't find parent function", -- GitLab From b254f11cc9304b757357460643003ea7087e6c5c Mon Sep 17 00:00:00 2001 From: Romain Izard Date: Tue, 20 Nov 2018 17:57:37 +0100 Subject: [PATCH 0483/1286] ARM: dts: at91: sama5d2: use the divided clock for SMC [ Upstream commit 4ab7ca092c3c7ac8b16aa28eba723a8868f82f14 ] The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two different clocks for the peripherals in the SoC. The Static Memory controller is connected to the divided master clock. Unfortunately, the device tree does not correctly show this and uses the master clock directly. This clock is then used by the code for the NAND controller to calculate the timings for the controller, and we end up with slow NAND Flash access. Fix the device tree, and the performance of Flash access is improved. Signed-off-by: Romain Izard Signed-off-by: Alexandre Belloni Signed-off-by: Sasha Levin --- arch/arm/boot/dts/sama5d2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index b1a26b42d190..a8e4b89097d9 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -308,7 +308,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&h32ck>; status = "disabled"; nand_controller: nand-controller { -- GitLab From 67080eb258b4329ff55eefcd11bdee295ce905e5 Mon Sep 17 00:00:00 2001 From: Robbie Ko Date: Wed, 14 Nov 2018 18:32:37 +0000 Subject: [PATCH 0484/1286] Btrfs: send, fix infinite loop due to directory rename dependencies [ Upstream commit a4390aee72713d9e73f1132bcdeb17d72fbbf974 ] When doing an incremental send, due to the need of delaying directory move (rename) operations we can end up in infinite loop at apply_children_dir_moves(). An example scenario that triggers this problem is described below, where directory names correspond to the numbers of their respective inodes. Parent snapshot: . |--- 261/ |--- 271/ |--- 266/ |--- 259/ |--- 260/ | |--- 267 | |--- 264/ | |--- 258/ | |--- 257/ | |--- 265/ |--- 268/ |--- 269/ | |--- 262/ | |--- 270/ |--- 272/ | |--- 263/ | |--- 275/ | |--- 274/ |--- 273/ Send snapshot: . |-- 275/ |-- 274/ |-- 273/ |-- 262/ |-- 269/ |-- 258/ |-- 271/ |-- 268/ |-- 267/ |-- 270/ |-- 259/ | |-- 265/ | |-- 272/ |-- 257/ |-- 260/ |-- 264/ |-- 263/ |-- 261/ |-- 266/ When processing inode 257 we delay its move (rename) operation because its new parent in the send snapshot, inode 272, was not yet processed. Then when processing inode 272, we delay the move operation for that inode because inode 274 is its ancestor in the send snapshot. Finally we delay the move operation for inode 274 when processing it because inode 275 is its new parent in the send snapshot and was not yet moved. When finishing processing inode 275, we start to do the move operations that were previously delayed (at apply_children_dir_moves()), resulting in the following iterations: 1) We issue the move operation for inode 274; 2) Because inode 262 depended on the move operation of inode 274 (it was delayed because 274 is its ancestor in the send snapshot), we issue the move operation for inode 262; 3) We issue the move operation for inode 272, because it was delayed by inode 274 too (ancestor of 272 in the send snapshot); 4) We issue the move operation for inode 269 (it was delayed by 262); 5) We issue the move operation for inode 257 (it was delayed by 272); 6) We issue the move operation for inode 260 (it was delayed by 272); 7) We issue the move operation for inode 258 (it was delayed by 269); 8) We issue the move operation for inode 264 (it was delayed by 257); 9) We issue the move operation for inode 271 (it was delayed by 258); 10) We issue the move operation for inode 263 (it was delayed by 264); 11) We issue the move operation for inode 268 (it was delayed by 271); 12) We verify if we can issue the move operation for inode 270 (it was delayed by 271). We detect a path loop in the current state, because inode 267 needs to be moved first before we can issue the move operation for inode 270. So we delay again the move operation for inode 270, this time we will attempt to do it after inode 267 is moved; 13) We issue the move operation for inode 261 (it was delayed by 263); 14) We verify if we can issue the move operation for inode 266 (it was delayed by 263). We detect a path loop in the current state, because inode 270 needs to be moved first before we can issue the move operation for inode 266. So we delay again the move operation for inode 266, this time we will attempt to do it after inode 270 is moved (its move operation was delayed in step 12); 15) We issue the move operation for inode 267 (it was delayed by 268); 16) We verify if we can issue the move operation for inode 266 (it was delayed by 270). We detect a path loop in the current state, because inode 270 needs to be moved first before we can issue the move operation for inode 266. So we delay again the move operation for inode 266, this time we will attempt to do it after inode 270 is moved (its move operation was delayed in step 12). So here we added again the same delayed move operation that we added in step 14; 17) We attempt again to see if we can issue the move operation for inode 266, and as in step 16, we realize we can not due to a path loop in the current state due to a dependency on inode 270. Again we delay inode's 266 rename to happen after inode's 270 move operation, adding the same dependency to the empty stack that we did in steps 14 and 16. The next iteration will pick the same move dependency on the stack (the only entry) and realize again there is still a path loop and then again the same dependency to the stack, over and over, resulting in an infinite loop. So fix this by preventing adding the same move dependency entries to the stack by removing each pending move record from the red black tree of pending moves. This way the next call to get_pending_dir_moves() will not return anything for the current parent inode. A test case for fstests, with this reproducer, follows soon. Signed-off-by: Robbie Ko Reviewed-by: Filipe Manana [Wrote changelog with example and more clear explanation] Signed-off-by: Filipe Manana Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/send.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/send.c b/fs/btrfs/send.c index baf5a4cd7ffc..3f22af96d63b 100644 --- a/fs/btrfs/send.c +++ b/fs/btrfs/send.c @@ -3354,7 +3354,8 @@ static void free_pending_move(struct send_ctx *sctx, struct pending_dir_move *m) kfree(m); } -static void tail_append_pending_moves(struct pending_dir_move *moves, +static void tail_append_pending_moves(struct send_ctx *sctx, + struct pending_dir_move *moves, struct list_head *stack) { if (list_empty(&moves->list)) { @@ -3365,6 +3366,10 @@ static void tail_append_pending_moves(struct pending_dir_move *moves, list_add_tail(&moves->list, stack); list_splice_tail(&list, stack); } + if (!RB_EMPTY_NODE(&moves->node)) { + rb_erase(&moves->node, &sctx->pending_dir_moves); + RB_CLEAR_NODE(&moves->node); + } } static int apply_children_dir_moves(struct send_ctx *sctx) @@ -3379,7 +3384,7 @@ static int apply_children_dir_moves(struct send_ctx *sctx) return 0; INIT_LIST_HEAD(&stack); - tail_append_pending_moves(pm, &stack); + tail_append_pending_moves(sctx, pm, &stack); while (!list_empty(&stack)) { pm = list_first_entry(&stack, struct pending_dir_move, list); @@ -3390,7 +3395,7 @@ static int apply_children_dir_moves(struct send_ctx *sctx) goto out; pm = get_pending_dir_moves(sctx, parent_ino); if (pm) - tail_append_pending_moves(pm, &stack); + tail_append_pending_moves(sctx, pm, &stack); } return 0; -- GitLab From 9692eefbee777b18e22998f0dc2852cf8f34174e Mon Sep 17 00:00:00 2001 From: Majd Dibbiny Date: Mon, 5 Nov 2018 08:07:37 +0200 Subject: [PATCH 0485/1286] RDMA/mlx5: Fix fence type for IB_WR_LOCAL_INV WR [ Upstream commit 074fca3a18e7e1e0d4d7dcc9d7badc43b90232f4 ] Currently, for IB_WR_LOCAL_INV WR, when the next fence is None, the current fence will be SMALL instead of Normal Fence. Without this patch krping doesn't work on CX-5 devices and throws following error: The error messages are from CX5 driver are: (from server side) [ 710.434014] mlx5_0:dump_cqe:278:(pid 2712): dump error cqe [ 710.434016] 00000000 00000000 00000000 00000000 [ 710.434016] 00000000 00000000 00000000 00000000 [ 710.434017] 00000000 00000000 00000000 00000000 [ 710.434018] 00000000 93003204 100000b8 000524d2 [ 710.434019] krping: cq completion failed with wr_id 0 status 4 opcode 128 vender_err 32 Fixed the logic to set the correct fence type. Fixes: 6e8484c5cf07 ("RDMA/mlx5: set UMR wqe fence according to HCA cap") Signed-off-by: Majd Dibbiny Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/hw/mlx5/qp.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index dfc190055167..964c3a0bbf16 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3928,17 +3928,18 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, goto out; } - if (wr->opcode == IB_WR_LOCAL_INV || - wr->opcode == IB_WR_REG_MR) { + if (wr->opcode == IB_WR_REG_MR) { fence = dev->umr_fence; next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; - } else if (wr->send_flags & IB_SEND_FENCE) { - if (qp->next_fence) - fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; - else - fence = MLX5_FENCE_MODE_FENCE; - } else { - fence = qp->next_fence; + } else { + if (wr->send_flags & IB_SEND_FENCE) { + if (qp->next_fence) + fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; + else + fence = MLX5_FENCE_MODE_FENCE; + } else { + fence = qp->next_fence; + } } switch (ibqp->qp_type) { -- GitLab From a625d3e3ce05d05f8f2e1e5d4546d12c94feec4d Mon Sep 17 00:00:00 2001 From: Kamal Heib Date: Thu, 15 Nov 2018 09:49:38 -0800 Subject: [PATCH 0486/1286] RDMA/rdmavt: Fix rvt_create_ah function signature [ Upstream commit 4f32fb921b153ae9ea280e02a3e91509fffc03d3 ] rdmavt uses a crazy system that looses the type checking when assinging functions to struct ib_device function pointers. Because of this the signature to this function was not changed when the below commit revised things. Fix the signature so we are not calling a function pointer with a mismatched signature. Fixes: 477864c8fcd9 ("IB/core: Let create_ah return extended response to user") Signed-off-by: Kamal Heib Reviewed-by: Dennis Dalessandro Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/sw/rdmavt/ah.c | 4 +++- drivers/infiniband/sw/rdmavt/ah.h | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/sw/rdmavt/ah.c b/drivers/infiniband/sw/rdmavt/ah.c index ba3639a0d77c..48ea5b8207f0 100644 --- a/drivers/infiniband/sw/rdmavt/ah.c +++ b/drivers/infiniband/sw/rdmavt/ah.c @@ -91,13 +91,15 @@ EXPORT_SYMBOL(rvt_check_ah); * rvt_create_ah - create an address handle * @pd: the protection domain * @ah_attr: the attributes of the AH + * @udata: pointer to user's input output buffer information. * * This may be called from interrupt context. * * Return: newly allocated ah */ struct ib_ah *rvt_create_ah(struct ib_pd *pd, - struct rdma_ah_attr *ah_attr) + struct rdma_ah_attr *ah_attr, + struct ib_udata *udata) { struct rvt_ah *ah; struct rvt_dev_info *dev = ib_to_rvt(pd->device); diff --git a/drivers/infiniband/sw/rdmavt/ah.h b/drivers/infiniband/sw/rdmavt/ah.h index 16105af99189..25271b48a683 100644 --- a/drivers/infiniband/sw/rdmavt/ah.h +++ b/drivers/infiniband/sw/rdmavt/ah.h @@ -51,7 +51,8 @@ #include struct ib_ah *rvt_create_ah(struct ib_pd *pd, - struct rdma_ah_attr *ah_attr); + struct rdma_ah_attr *ah_attr, + struct ib_udata *udata); int rvt_destroy_ah(struct ib_ah *ibah); int rvt_modify_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); int rvt_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); -- GitLab From 4a3fa2a5fed133fd2f26e5f37acdb23ad6e0900c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Nov 2018 13:06:21 +0200 Subject: [PATCH 0487/1286] ASoC: omap-mcbsp: Fix latency value calculation for pm_qos [ Upstream commit dd2f52d8991af9fe0928d59ec502ba52be7bc38d ] The latency number is in usec for the pm_qos. Correct the calculation to give us the time in usec Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/omap/omap-mcbsp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 6b40bdbef336..47c2ed5ca492 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -308,9 +308,9 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, pkt_size = channels; } - latency = ((((buffer_size - pkt_size) / channels) * 1000) - / (params->rate_num / params->rate_den)); - + latency = (buffer_size - pkt_size) / channels; + latency = latency * USEC_PER_SEC / + (params->rate_num / params->rate_den); mcbsp->latency[substream->stream] = latency; omap_mcbsp_set_threshold(substream, pkt_size); -- GitLab From 997a8d6c47fae788131e3b113841169d89ecf803 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Nov 2018 13:06:22 +0200 Subject: [PATCH 0488/1286] ASoC: omap-mcpdm: Add pm_qos handling to avoid under/overruns with CPU_IDLE [ Upstream commit 373a500e34aea97971c9d71e45edad458d3da98f ] We need to block sleep states which would require longer time to leave than the time the DMA must react to the DMA request in order to keep the FIFO serviced without under of overrun. Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/omap/omap-mcpdm.c | 43 ++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c index 64609c77a79d..44ffeb71cd1d 100644 --- a/sound/soc/omap/omap-mcpdm.c +++ b/sound/soc/omap/omap-mcpdm.c @@ -54,6 +54,8 @@ struct omap_mcpdm { unsigned long phys_base; void __iomem *io_base; int irq; + struct pm_qos_request pm_qos_req; + int latency[2]; struct mutex mutex; @@ -277,6 +279,9 @@ static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); + int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; + int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; mutex_lock(&mcpdm->mutex); @@ -289,6 +294,14 @@ static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, } } + if (mcpdm->latency[stream2]) + pm_qos_update_request(&mcpdm->pm_qos_req, + mcpdm->latency[stream2]); + else if (mcpdm->latency[stream1]) + pm_qos_remove_request(&mcpdm->pm_qos_req); + + mcpdm->latency[stream1] = 0; + mutex_unlock(&mcpdm->mutex); } @@ -300,7 +313,7 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, int stream = substream->stream; struct snd_dmaengine_dai_dma_data *dma_data; u32 threshold; - int channels; + int channels, latency; int link_mask = 0; channels = params_channels(params); @@ -340,14 +353,25 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, dma_data->maxburst = (MCPDM_DN_THRES_MAX - threshold) * channels; + latency = threshold; } else { /* If playback is not running assume a stereo stream to come */ if (!mcpdm->config[!stream].link_mask) mcpdm->config[!stream].link_mask = (0x3 << 3); dma_data->maxburst = threshold * channels; + latency = (MCPDM_DN_THRES_MAX - threshold); } + /* + * The DMA must act to a DMA request within latency time (usec) to avoid + * under/overflow + */ + mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params); + + if (!mcpdm->latency[stream]) + mcpdm->latency[stream] = 10; + /* Check if we need to restart McPDM with this stream */ if (mcpdm->config[stream].link_mask && mcpdm->config[stream].link_mask != link_mask) @@ -362,6 +386,20 @@ static int omap_mcpdm_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req; + int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); + int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; + int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; + int latency = mcpdm->latency[stream2]; + + /* Prevent omap hardware from hitting off between FIFO fills */ + if (!latency || mcpdm->latency[stream1] < latency) + latency = mcpdm->latency[stream1]; + + if (pm_qos_request_active(pm_qos_req)) + pm_qos_update_request(pm_qos_req, latency); + else if (latency) + pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency); if (!omap_mcpdm_active(mcpdm)) { omap_mcpdm_start(mcpdm); @@ -423,6 +461,9 @@ static int omap_mcpdm_remove(struct snd_soc_dai *dai) free_irq(mcpdm->irq, (void *)mcpdm); pm_runtime_disable(mcpdm->dev); + if (pm_qos_request_active(&mcpdm->pm_qos_req)) + pm_qos_remove_request(&mcpdm->pm_qos_req); + return 0; } -- GitLab From bdafd18e24c8fcf704950dc48849e271cceee19f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Nov 2018 13:06:23 +0200 Subject: [PATCH 0489/1286] ASoC: omap-dmic: Add pm_qos handling to avoid overruns with CPU_IDLE [ Upstream commit ffdcc3638c58d55a6fa68b6e5dfd4fb4109652eb ] We need to block sleep states which would require longer time to leave than the time the DMA must react to the DMA request in order to keep the FIFO serviced without overrun. Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/omap/omap-dmic.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/soc/omap/omap-dmic.c b/sound/soc/omap/omap-dmic.c index 09db2aec12a3..776e809a8aab 100644 --- a/sound/soc/omap/omap-dmic.c +++ b/sound/soc/omap/omap-dmic.c @@ -48,6 +48,8 @@ struct omap_dmic { struct device *dev; void __iomem *io_base; struct clk *fclk; + struct pm_qos_request pm_qos_req; + int latency; int fclk_freq; int out_freq; int clk_div; @@ -124,6 +126,8 @@ static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream, mutex_lock(&dmic->mutex); + pm_qos_remove_request(&dmic->pm_qos_req); + if (!dai->active) dmic->active = 0; @@ -226,6 +230,8 @@ static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream, /* packet size is threshold * channels */ dma_data = snd_soc_dai_get_dma_data(dai, substream); dma_data->maxburst = dmic->threshold * channels; + dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC / + params_rate(params); return 0; } @@ -236,6 +242,9 @@ static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream, struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); u32 ctrl; + if (pm_qos_request_active(&dmic->pm_qos_req)) + pm_qos_update_request(&dmic->pm_qos_req, dmic->latency); + /* Configure uplink threshold */ omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold); -- GitLab From 42cb0b9efc9e18e8b81e9a296082381fc8b70071 Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Fri, 23 Nov 2018 15:56:33 +0800 Subject: [PATCH 0490/1286] exportfs: do not read dentry after free [ Upstream commit 2084ac6c505a58f7efdec13eba633c6aaa085ca5 ] The function dentry_connected calls dput(dentry) to drop the previously acquired reference to dentry. In this case, dentry can be released. After that, IS_ROOT(dentry) checks the condition (dentry == dentry->d_parent), which may result in a use-after-free bug. This patch directly compares dentry with its parent obtained before dropping the reference. Fixes: a056cc8934c("exportfs: stop retrying once we race with rename/remove") Signed-off-by: Pan Bian Signed-off-by: Al Viro Signed-off-by: Sasha Levin --- fs/exportfs/expfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/exportfs/expfs.c b/fs/exportfs/expfs.c index 329a5d103846..c22cc9d2a5c9 100644 --- a/fs/exportfs/expfs.c +++ b/fs/exportfs/expfs.c @@ -77,7 +77,7 @@ static bool dentry_connected(struct dentry *dentry) struct dentry *parent = dget_parent(dentry); dput(dentry); - if (IS_ROOT(dentry)) { + if (dentry == parent) { dput(parent); return false; } -- GitLab From 9209043b29881a7ede5e34610c4feadd29e59e40 Mon Sep 17 00:00:00 2001 From: Martynas Pumputis Date: Fri, 23 Nov 2018 17:43:26 +0100 Subject: [PATCH 0491/1286] bpf: fix check of allowed specifiers in bpf_trace_printk [ Upstream commit 1efb6ee3edea57f57f9fb05dba8dcb3f7333f61f ] A format string consisting of "%p" or "%s" followed by an invalid specifier (e.g. "%p%\n" or "%s%") could pass the check which would make format_decode (lib/vsprintf.c) to warn. Fixes: 9c959c863f82 ("tracing: Allow BPF programs to call bpf_trace_printk()") Reported-by: syzbot+1ec5c5ec949c4adaa0c4@syzkaller.appspotmail.com Signed-off-by: Martynas Pumputis Signed-off-by: Daniel Borkmann Signed-off-by: Sasha Levin --- kernel/trace/bpf_trace.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 6350f64d5aa4..f9dd8fd055a6 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -161,11 +161,13 @@ BPF_CALL_5(bpf_trace_printk, char *, fmt, u32, fmt_size, u64, arg1, i++; } else if (fmt[i] == 'p' || fmt[i] == 's') { mod[fmt_cnt]++; - i++; - if (!isspace(fmt[i]) && !ispunct(fmt[i]) && fmt[i] != 0) + /* disallow any further format extensions */ + if (fmt[i + 1] != 0 && + !isspace(fmt[i + 1]) && + !ispunct(fmt[i + 1])) return -EINVAL; fmt_cnt++; - if (fmt[i - 1] == 's') { + if (fmt[i] == 's') { if (str_seen) /* allow only one '%s' per fmt string */ return -EINVAL; -- GitLab From 57dea3802f389e38b4e3f4d439e0540f00359205 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Thu, 15 Nov 2018 15:14:30 +0800 Subject: [PATCH 0492/1286] ipvs: call ip_vs_dst_notifier earlier than ipv6_dev_notf [ Upstream commit 2a31e4bd9ad255ee40809b5c798c4b1c2b09703b ] ip_vs_dst_event is supposed to clean up all dst used in ipvs' destinations when a net dev is going down. But it works only when the dst's dev is the same as the dev from the event. Now with the same priority but late registration, ip_vs_dst_notifier is always called later than ipv6_dev_notf where the dst's dev is set to lo for NETDEV_DOWN event. As the dst's dev lo is not the same as the dev from the event in ip_vs_dst_event, ip_vs_dst_notifier doesn't actually work. Also as these dst have to wait for dest_trash_timer to clean them up. It would cause some non-permanent kernel warnings: unregister_netdevice: waiting for br0 to become free. Usage count = 3 To fix it, call ip_vs_dst_notifier earlier than ipv6_dev_notf by increasing its priority to ADDRCONF_NOTIFY_PRIORITY + 5. Note that for ipv4 route fib_netdev_notifier doesn't set dst's dev to lo in NETDEV_DOWN event, so this fix is only needed when IP_VS_IPV6 is defined. Fixes: 7a4f0761fce3 ("IPVS: init and cleanup restructuring") Reported-by: Li Shuang Signed-off-by: Xin Long Acked-by: Julian Anastasov Acked-by: Simon Horman Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/ipvs/ip_vs_ctl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index 327ebe786eeb..2f45c3ce77ef 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -4012,6 +4012,9 @@ static void __net_exit ip_vs_control_net_cleanup_sysctl(struct netns_ipvs *ipvs) static struct notifier_block ip_vs_dst_notifier = { .notifier_call = ip_vs_dst_event, +#ifdef CONFIG_IP_VS_IPV6 + .priority = ADDRCONF_NOTIFY_PRIORITY + 5, +#endif }; int __net_init ip_vs_control_net_init(struct netns_ipvs *ipvs) -- GitLab From 11f8633c5a334850e9171f4808f20f5a2039060e Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 25 Nov 2018 00:17:04 +0200 Subject: [PATCH 0493/1286] USB: omap_udc: use devm_request_irq() [ Upstream commit 286afdde1640d8ea8916a0f05e811441fbbf4b9d ] The current code fails to release the third irq on the error path (observed by reading the code), and we get also multiple WARNs with failing gadget drivers due to duplicate IRQ releases. Fix by using devm_request_irq(). Signed-off-by: Aaro Koskinen Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/omap_udc.c | 37 +++++++++---------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index f05ba6825bfe..e515c85ef0c5 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2886,8 +2886,8 @@ static int omap_udc_probe(struct platform_device *pdev) udc->clr_halt = UDC_RESET_EP; /* USB general purpose IRQ: ep0, state changes, dma, etc */ - status = request_irq(pdev->resource[1].start, omap_udc_irq, - 0, driver_name, udc); + status = devm_request_irq(&pdev->dev, pdev->resource[1].start, + omap_udc_irq, 0, driver_name, udc); if (status != 0) { ERR("can't get irq %d, err %d\n", (int) pdev->resource[1].start, status); @@ -2895,20 +2895,20 @@ static int omap_udc_probe(struct platform_device *pdev) } /* USB "non-iso" IRQ (PIO for all but ep0) */ - status = request_irq(pdev->resource[2].start, omap_udc_pio_irq, - 0, "omap_udc pio", udc); + status = devm_request_irq(&pdev->dev, pdev->resource[2].start, + omap_udc_pio_irq, 0, "omap_udc pio", udc); if (status != 0) { ERR("can't get irq %d, err %d\n", (int) pdev->resource[2].start, status); - goto cleanup2; + goto cleanup1; } #ifdef USE_ISO - status = request_irq(pdev->resource[3].start, omap_udc_iso_irq, - 0, "omap_udc iso", udc); + status = devm_request_irq(&pdev->dev, pdev->resource[3].start, + omap_udc_iso_irq, 0, "omap_udc iso", udc); if (status != 0) { ERR("can't get irq %d, err %d\n", (int) pdev->resource[3].start, status); - goto cleanup3; + goto cleanup1; } #endif if (cpu_is_omap16xx() || cpu_is_omap7xx()) { @@ -2921,22 +2921,11 @@ static int omap_udc_probe(struct platform_device *pdev) create_proc_file(); status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget, omap_udc_release); - if (status) - goto cleanup4; - - return 0; + if (!status) + return 0; -cleanup4: remove_proc_file(); -#ifdef USE_ISO -cleanup3: - free_irq(pdev->resource[2].start, udc); -#endif - -cleanup2: - free_irq(pdev->resource[1].start, udc); - cleanup1: kfree(udc); udc = NULL; @@ -2980,12 +2969,6 @@ static int omap_udc_remove(struct platform_device *pdev) remove_proc_file(); -#ifdef USE_ISO - free_irq(pdev->resource[3].start, udc); -#endif - free_irq(pdev->resource[2].start, udc); - free_irq(pdev->resource[1].start, udc); - if (udc->dc_clk) { if (udc->clk_requested) omap_udc_enable_clock(0); -- GitLab From 09eb2b90d9e00acf0aa314f59b69de3b0037bb21 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 25 Nov 2018 00:17:05 +0200 Subject: [PATCH 0494/1286] USB: omap_udc: fix crashes on probe error and module removal [ Upstream commit 99f700366fcea1aa2fa3c49c99f371670c3c62f8 ] We currently crash if usb_add_gadget_udc_release() fails, since the udc->done is not initialized until in the remove function. Furthermore, on module removal the udc data is accessed although the release function is already triggered by usb_del_gadget_udc() early in the function. Fix by rewriting the release and remove functions, basically moving all the cleanup into the release function, and doing the completion only in the module removal case. The patch fixes omap_udc module probe with a failing gadged, and also allows the removal of omap_udc. Tested by running "modprobe omap_udc; modprobe -r omap_udc" in a loop. Signed-off-by: Aaro Koskinen Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/omap_udc.c | 50 ++++++++++++------------------- 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index e515c85ef0c5..d45dc14ef0a2 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2612,9 +2612,22 @@ omap_ep_setup(char *name, u8 addr, u8 type, static void omap_udc_release(struct device *dev) { - complete(udc->done); + pullup_disable(udc); + if (!IS_ERR_OR_NULL(udc->transceiver)) { + usb_put_phy(udc->transceiver); + udc->transceiver = NULL; + } + omap_writew(0, UDC_SYSCON1); + remove_proc_file(); + if (udc->dc_clk) { + if (udc->clk_requested) + omap_udc_enable_clock(0); + clk_put(udc->hhc_clk); + clk_put(udc->dc_clk); + } + if (udc->done) + complete(udc->done); kfree(udc); - udc = NULL; } static int @@ -2919,12 +2932,8 @@ static int omap_udc_probe(struct platform_device *pdev) } create_proc_file(); - status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget, - omap_udc_release); - if (!status) - return 0; - - remove_proc_file(); + return usb_add_gadget_udc_release(&pdev->dev, &udc->gadget, + omap_udc_release); cleanup1: kfree(udc); @@ -2951,36 +2960,15 @@ static int omap_udc_remove(struct platform_device *pdev) { DECLARE_COMPLETION_ONSTACK(done); - if (!udc) - return -ENODEV; - - usb_del_gadget_udc(&udc->gadget); - if (udc->driver) - return -EBUSY; - udc->done = &done; - pullup_disable(udc); - if (!IS_ERR_OR_NULL(udc->transceiver)) { - usb_put_phy(udc->transceiver); - udc->transceiver = NULL; - } - omap_writew(0, UDC_SYSCON1); - - remove_proc_file(); + usb_del_gadget_udc(&udc->gadget); - if (udc->dc_clk) { - if (udc->clk_requested) - omap_udc_enable_clock(0); - clk_put(udc->hhc_clk); - clk_put(udc->dc_clk); - } + wait_for_completion(&done); release_mem_region(pdev->resource[0].start, pdev->resource[0].end - pdev->resource[0].start + 1); - wait_for_completion(&done); - return 0; } -- GitLab From e68f6cb901194b9aa662dbe65b69486c32e58615 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 25 Nov 2018 00:17:06 +0200 Subject: [PATCH 0495/1286] USB: omap_udc: fix omap_udc_start() on 15xx machines [ Upstream commit 6ca6695f576b8453fe68865e84d25946d63b10ad ] On OMAP 15xx machines there are no transceivers, and omap_udc_start() always fails as it forgot to adjust the default return value. Signed-off-by: Aaro Koskinen Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/omap_udc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index d45dc14ef0a2..9060b3af27ff 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2045,7 +2045,7 @@ static inline int machine_without_vbus_sense(void) static int omap_udc_start(struct usb_gadget *g, struct usb_gadget_driver *driver) { - int status = -ENODEV; + int status; struct omap_ep *ep; unsigned long flags; @@ -2083,6 +2083,7 @@ static int omap_udc_start(struct usb_gadget *g, goto done; } } else { + status = 0; if (can_pullup(udc)) pullup_enable(udc); else -- GitLab From 72c982a3b1dddf68c3d5e259447994fdbf23b75a Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 25 Nov 2018 00:17:07 +0200 Subject: [PATCH 0496/1286] USB: omap_udc: fix USB gadget functionality on Palm Tungsten E [ Upstream commit 2c2322fbcab8102b8cadc09d66714700a2da42c2 ] On Palm TE nothing happens when you try to use gadget drivers and plug the USB cable. Fix by adding the board to the vbus sense quirk list. Signed-off-by: Aaro Koskinen Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/omap_udc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index 9060b3af27ff..c8facc8aa87e 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2037,6 +2037,7 @@ static inline int machine_without_vbus_sense(void) { return machine_is_omap_innovator() || machine_is_omap_osk() + || machine_is_omap_palmte() || machine_is_sx1() /* No known omap7xx boards with vbus sense */ || cpu_is_omap7xx(); -- GitLab From ca993dead6b5ca2181185064502ea6b22797a857 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 25 Nov 2018 00:17:08 +0200 Subject: [PATCH 0497/1286] USB: omap_udc: fix rejection of out transfers when DMA is used [ Upstream commit 069caf5950dfa75d0526cd89c439ff9d9d3136d8 ] Commit 387f869d2579 ("usb: gadget: u_ether: conditionally align transfer size") started aligning transfer size only if requested, breaking omap_udc DMA mode. Set quirk_ep_out_aligned_size to restore the old behaviour. Fixes: 387f869d2579 ("usb: gadget: u_ether: conditionally align transfer size") Signed-off-by: Aaro Koskinen Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/omap_udc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index c8facc8aa87e..ee0b87a0773c 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2661,6 +2661,7 @@ omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv) udc->gadget.speed = USB_SPEED_UNKNOWN; udc->gadget.max_speed = USB_SPEED_FULL; udc->gadget.name = driver_name; + udc->gadget.quirk_ep_out_aligned_size = 1; udc->transceiver = xceiv; /* ep0 is special; put it right after the SETUP buffer */ -- GitLab From f47b8824a83057e9f63d39df86332ffeb703311f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 21 Nov 2018 13:39:29 +0400 Subject: [PATCH 0498/1286] drm/meson: add support for 1080p25 mode [ Upstream commit 31e1ab494559fb46de304cc6c2aed1528f94b298 ] This essential mode for PAL users is missing, so add it. Fixes: 335e3713afb87 ("drm/meson: Add support for HDMI venc modes and settings") Signed-off-by: Christian Hewitt Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/1542793169-13008-1-git-send-email-christianshewitt@gmail.com Signed-off-by: Sean Paul Signed-off-by: Sasha Levin --- drivers/gpu/drm/meson/meson_venc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 9509017dbded..d5dfe7045cc6 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -714,6 +714,7 @@ struct meson_hdmi_venc_vic_mode { { 5, &meson_hdmi_encp_mode_1080i60 }, { 20, &meson_hdmi_encp_mode_1080i50 }, { 32, &meson_hdmi_encp_mode_1080p24 }, + { 33, &meson_hdmi_encp_mode_1080p50 }, { 34, &meson_hdmi_encp_mode_1080p30 }, { 31, &meson_hdmi_encp_mode_1080p50 }, { 16, &meson_hdmi_encp_mode_1080p60 }, -- GitLab From 97f048033a07b199b98d5e8f10f1022f10d42ed4 Mon Sep 17 00:00:00 2001 From: Alin Nastac Date: Wed, 21 Nov 2018 14:00:30 +0100 Subject: [PATCH 0499/1286] netfilter: ipv6: Preserve link scope traffic original oif [ Upstream commit 508b09046c0f21678652fb66fd1e9959d55591d2 ] When ip6_route_me_harder is invoked, it resets outgoing interface of: - link-local scoped packets sent by neighbor discovery - multicast packets sent by MLD host - multicast packets send by MLD proxy daemon that sets outgoing interface through IPV6_PKTINFO ipi6_ifindex Link-local and multicast packets must keep their original oif after ip6_route_me_harder is called. Signed-off-by: Alin Nastac Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/ipv6/netfilter.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv6/netfilter.c b/net/ipv6/netfilter.c index 9bf260459f83..1f8b1a433b5d 100644 --- a/net/ipv6/netfilter.c +++ b/net/ipv6/netfilter.c @@ -25,7 +25,8 @@ int ip6_route_me_harder(struct net *net, struct sk_buff *skb) unsigned int hh_len; struct dst_entry *dst; struct flowi6 fl6 = { - .flowi6_oif = sk ? sk->sk_bound_dev_if : 0, + .flowi6_oif = sk && sk->sk_bound_dev_if ? sk->sk_bound_dev_if : + rt6_need_strict(&iph->daddr) ? skb_dst(skb)->dev->ifindex : 0, .flowi6_mark = skb->mark, .flowi6_uid = sock_net_uid(net, sk), .daddr = iph->daddr, -- GitLab From 8f859b2729e980d511f29a68c3474aa27ead72b7 Mon Sep 17 00:00:00 2001 From: Artemy Kovalyov Date: Sun, 25 Nov 2018 20:34:26 +0200 Subject: [PATCH 0500/1286] IB/mlx5: Fix page fault handling for MW [ Upstream commit 75b7b86bdb0df37e08e44b6c1f99010967f81944 ] Memory windows are implemented with an indirect MKey, when a page fault event comes for a MW Mkey we need to find the MR at the end of the list of the indirect MKeys by iterating on all items from the first to the last. The offset calculated during this process has to be zeroed after the first iteration or the next iteration will start from a wrong address, resulting incorrect ODP faulting behavior. Fixes: db570d7deafb ("IB/mlx5: Add ODP support to MW") Signed-off-by: Artemy Kovalyov Signed-off-by: Moni Shoua Signed-off-by: Leon Romanovsky Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/hw/mlx5/odp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/odp.c index 3d701c7a4c91..1ed94b6c0b0a 100644 --- a/drivers/infiniband/hw/mlx5/odp.c +++ b/drivers/infiniband/hw/mlx5/odp.c @@ -723,6 +723,7 @@ static int pagefault_single_data_segment(struct mlx5_ib_dev *dev, head = frame; bcnt -= frame->bcnt; + offset = 0; } break; -- GitLab From bb3f86913bdad19cc9a0d0165ddd373ff8c930f7 Mon Sep 17 00:00:00 2001 From: Yi Wang Date: Thu, 8 Nov 2018 16:48:36 +0800 Subject: [PATCH 0501/1286] KVM: x86: fix empty-body warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 354cb410d87314e2eda344feea84809e4261570a ] We get the following warnings about empty statements when building with 'W=1': arch/x86/kvm/lapic.c:632:53: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] arch/x86/kvm/lapic.c:1907:42: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] arch/x86/kvm/lapic.c:1936:65: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] arch/x86/kvm/lapic.c:1975:44: warning: suggest braces around empty body in an ‘if’ statement [-Wempty-body] Rework the debug helper macro to get rid of these warnings. Signed-off-by: Yi Wang Signed-off-by: Paolo Bonzini Signed-off-by: Sasha Levin --- arch/x86/kvm/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 13dfb55b84db..f7c34184342a 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -55,7 +55,7 @@ #define PRIo64 "o" /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ -#define apic_debug(fmt, arg...) +#define apic_debug(fmt, arg...) do {} while (0) /* 14 is the version for Xeon and Pentium 8.4.8*/ #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) -- GitLab From 7fdd58deeae47d51ce528ef3bfd1f638f3c399be Mon Sep 17 00:00:00 2001 From: Yi Wang Date: Thu, 8 Nov 2018 11:22:21 +0800 Subject: [PATCH 0502/1286] x86/kvm/vmx: fix old-style function declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 1e4329ee2c52692ea42cc677fb2133519718b34a ] The inline keyword which is not at the beginning of the function declaration may trigger the following build warnings, so let's fix it: arch/x86/kvm/vmx.c:1309:1: warning: ‘inline’ is not at beginning of declaration [-Wold-style-declaration] arch/x86/kvm/vmx.c:5947:1: warning: ‘inline’ is not at beginning of declaration [-Wold-style-declaration] arch/x86/kvm/vmx.c:5985:1: warning: ‘inline’ is not at beginning of declaration [-Wold-style-declaration] arch/x86/kvm/vmx.c:6023:1: warning: ‘inline’ is not at beginning of declaration [-Wold-style-declaration] Signed-off-by: Yi Wang Signed-off-by: Paolo Bonzini Signed-off-by: Sasha Levin --- arch/x86/kvm/vmx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index ec588cf4fe95..4353580b659a 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -1089,7 +1089,7 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, u16 error_code); static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); -static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, +static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type); static DEFINE_PER_CPU(struct vmcs *, vmxarea); @@ -5227,7 +5227,7 @@ static void free_vpid(int vpid) spin_unlock(&vmx_vpid_lock); } -static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, +static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type) { int f = sizeof(unsigned long); @@ -5262,7 +5262,7 @@ static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bit } } -static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, +static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type) { int f = sizeof(unsigned long); @@ -5297,7 +5297,7 @@ static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitm } } -static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap, +static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, u32 msr, int type, bool value) { if (value) -- GitLab From ff791c9ec159ce294f949505bd0fe77881e67e02 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Mon, 26 Nov 2018 15:07:16 +0100 Subject: [PATCH 0503/1286] net: thunderx: fix NULL pointer dereference in nic_remove [ Upstream commit 24a6d2dd263bc910de018c78d1148b3e33b94512 ] Fix a possible NULL pointer dereference in nic_remove routine removing the nicpf module if nic_probe fails. The issue can be triggered with the following reproducer: $rmmod nicvf $rmmod nicpf [ 521.412008] Unable to handle kernel access to user memory outside uaccess routines at virtual address 0000000000000014 [ 521.422777] Mem abort info: [ 521.425561] ESR = 0x96000004 [ 521.428624] Exception class = DABT (current EL), IL = 32 bits [ 521.434535] SET = 0, FnV = 0 [ 521.437579] EA = 0, S1PTW = 0 [ 521.440730] Data abort info: [ 521.443603] ISV = 0, ISS = 0x00000004 [ 521.447431] CM = 0, WnR = 0 [ 521.450417] user pgtable: 4k pages, 48-bit VAs, pgdp = 0000000072a3da42 [ 521.457022] [0000000000000014] pgd=0000000000000000 [ 521.461916] Internal error: Oops: 96000004 [#1] SMP [ 521.511801] Hardware name: GIGABYTE H270-T70/MT70-HD0, BIOS T49 02/02/2018 [ 521.518664] pstate: 80400005 (Nzcv daif +PAN -UAO) [ 521.523451] pc : nic_remove+0x24/0x88 [nicpf] [ 521.527808] lr : pci_device_remove+0x48/0xd8 [ 521.532066] sp : ffff000013433cc0 [ 521.535370] x29: ffff000013433cc0 x28: ffff810f6ac50000 [ 521.540672] x27: 0000000000000000 x26: 0000000000000000 [ 521.545974] x25: 0000000056000000 x24: 0000000000000015 [ 521.551274] x23: ffff8007ff89a110 x22: ffff000001667070 [ 521.556576] x21: ffff8007ffb170b0 x20: ffff8007ffb17000 [ 521.561877] x19: 0000000000000000 x18: 0000000000000025 [ 521.567178] x17: 0000000000000000 x16: 000000000000010ffc33ff98 x8 : 0000000000000000 [ 521.593683] x7 : 0000000000000000 x6 : 0000000000000001 [ 521.598983] x5 : 0000000000000002 x4 : 0000000000000003 [ 521.604284] x3 : ffff8007ffb17184 x2 : ffff8007ffb17184 [ 521.609585] x1 : ffff000001662118 x0 : ffff000008557be0 [ 521.614887] Process rmmod (pid: 1897, stack limit = 0x00000000859535c3) [ 521.621490] Call trace: [ 521.623928] nic_remove+0x24/0x88 [nicpf] [ 521.627927] pci_device_remove+0x48/0xd8 [ 521.631847] device_release_driver_internal+0x1b0/0x248 [ 521.637062] driver_detach+0x50/0xc0 [ 521.640628] bus_remove_driver+0x60/0x100 [ 521.644627] driver_unregister+0x34/0x60 [ 521.648538] pci_unregister_driver+0x24/0xd8 [ 521.652798] nic_cleanup_module+0x14/0x111c [nicpf] [ 521.657672] __arm64_sys_delete_module+0x150/0x218 [ 521.662460] el0_svc_handler+0x94/0x110 [ 521.666287] el0_svc+0x8/0xc [ 521.669160] Code: aa1e03e0 9102c295 d503201f f9404eb3 (b9401660) Fixes: 4863dea3fab0 ("net: Adding support for Cavium ThunderX network controller") Signed-off-by: Lorenzo Bianconi Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/cavium/thunder/nic_main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/cavium/thunder/nic_main.c b/drivers/net/ethernet/cavium/thunder/nic_main.c index fb770b0182d3..d89ec4724efd 100644 --- a/drivers/net/ethernet/cavium/thunder/nic_main.c +++ b/drivers/net/ethernet/cavium/thunder/nic_main.c @@ -1376,6 +1376,9 @@ static void nic_remove(struct pci_dev *pdev) { struct nicpf *nic = pci_get_drvdata(pdev); + if (!nic) + return; + if (nic->flags & NIC_SRIOV_ENABLED) pci_disable_sriov(pdev); -- GitLab From b641ee14cfc1fe4d665e8bca98de1d00ed043ba9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 19 Nov 2018 16:49:05 +0100 Subject: [PATCH 0504/1286] usb: gadget: u_ether: fix unsafe list iteration [ Upstream commit c9287fa657b3328b4549c0ab39ea7f197a3d6a50 ] list_for_each_entry_safe() is not safe for deleting entries from the list if the spin lock, which protects it, is released and reacquired during the list iteration. Fix this issue by replacing this construction with a simple check if list is empty and removing the first entry in each iteration. This is almost equivalent to a revert of the commit mentioned in the Fixes: tag. This patch fixes following issue: --->8--- Unable to handle kernel NULL pointer dereference at virtual address 00000104 pgd = (ptrval) [00000104] *pgd=00000000 Internal error: Oops: 817 [#1] PREEMPT SMP ARM Modules linked in: CPU: 1 PID: 84 Comm: kworker/1:1 Not tainted 4.20.0-rc2-next-20181114-00009-g8266b35ec404 #1061 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events eth_work PC is at rx_fill+0x60/0xac LR is at _raw_spin_lock_irqsave+0x50/0x5c pc : [] lr : [] psr: 80000093 sp : ee7fbee8 ip : 00000100 fp : 00000000 r10: 006000c0 r9 : c10b0ab0 r8 : ee7eb5c0 r7 : ee7eb614 r6 : ee7eb5ec r5 : 000000dc r4 : ee12ac00 r3 : ee12ac24 r2 : 00000200 r1 : 60000013 r0 : ee7eb5ec Flags: Nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none Control: 10c5387d Table: 6d5dc04a DAC: 00000051 Process kworker/1:1 (pid: 84, stack limit = 0x(ptrval)) Stack: (0xee7fbee8 to 0xee7fc000) ... [] (rx_fill) from [] (process_one_work+0x200/0x738) [] (process_one_work) from [] (worker_thread+0x2c/0x4c8) [] (worker_thread) from [] (kthread+0x128/0x164) [] (kthread) from [] (ret_from_fork+0x14/0x20) Exception stack(0xee7fbfb0 to 0xee7fbff8) ... ---[ end trace 64480bc835eba7d6 ]--- Fixes: fea14e68ff5e ("usb: gadget: u_ether: use better list accessors") Signed-off-by: Marek Szyprowski Signed-off-by: Felipe Balbi Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/u_ether.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c index bdbc3fdc7c4f..3a0e4f5d7b83 100644 --- a/drivers/usb/gadget/function/u_ether.c +++ b/drivers/usb/gadget/function/u_ether.c @@ -405,12 +405,12 @@ static int alloc_requests(struct eth_dev *dev, struct gether *link, unsigned n) static void rx_fill(struct eth_dev *dev, gfp_t gfp_flags) { struct usb_request *req; - struct usb_request *tmp; unsigned long flags; /* fill unused rxq slots with some skb */ spin_lock_irqsave(&dev->req_lock, flags); - list_for_each_entry_safe(req, tmp, &dev->rx_reqs, list) { + while (!list_empty(&dev->rx_reqs)) { + req = list_first_entry(&dev->rx_reqs, struct usb_request, list); list_del_init(&req->list); spin_unlock_irqrestore(&dev->req_lock, flags); @@ -1125,7 +1125,6 @@ void gether_disconnect(struct gether *link) { struct eth_dev *dev = link->ioport; struct usb_request *req; - struct usb_request *tmp; WARN_ON(!dev); if (!dev) @@ -1142,7 +1141,8 @@ void gether_disconnect(struct gether *link) */ usb_ep_disable(link->in_ep); spin_lock(&dev->req_lock); - list_for_each_entry_safe(req, tmp, &dev->tx_reqs, list) { + while (!list_empty(&dev->tx_reqs)) { + req = list_first_entry(&dev->tx_reqs, struct usb_request, list); list_del(&req->list); spin_unlock(&dev->req_lock); @@ -1154,7 +1154,8 @@ void gether_disconnect(struct gether *link) usb_ep_disable(link->out_ep); spin_lock(&dev->req_lock); - list_for_each_entry_safe(req, tmp, &dev->rx_reqs, list) { + while (!list_empty(&dev->rx_reqs)) { + req = list_first_entry(&dev->rx_reqs, struct usb_request, list); list_del(&req->list); spin_unlock(&dev->req_lock); -- GitLab From 397727e77f2f32af322f850b457c1503acdff220 Mon Sep 17 00:00:00 2001 From: Taehee Yoo Date: Wed, 28 Nov 2018 11:27:28 +0900 Subject: [PATCH 0505/1286] netfilter: nf_tables: deactivate expressions in rule replecement routine [ Upstream commit ca08987885a147643817d02bf260bc4756ce8cd4 ] There is no expression deactivation call from the rule replacement path, hence, chain counter is not decremented. A few steps to reproduce the problem: %nft add table ip filter %nft add chain ip filter c1 %nft add chain ip filter c1 %nft add rule ip filter c1 jump c2 %nft replace rule ip filter c1 handle 3 accept %nft flush ruleset expression means immediate NFT_JUMP to chain c2. Reference count of chain c2 is increased when the rule is added. When rule is deleted or replaced, the reference counter of c2 should be decreased via nft_rule_expr_deactivate() which calls nft_immediate_deactivate(). Splat looks like: [ 214.396453] WARNING: CPU: 1 PID: 21 at net/netfilter/nf_tables_api.c:1432 nf_tables_chain_destroy.isra.38+0x2f9/0x3a0 [nf_tables] [ 214.398983] Modules linked in: nf_tables nfnetlink [ 214.398983] CPU: 1 PID: 21 Comm: kworker/1:1 Not tainted 4.20.0-rc2+ #44 [ 214.398983] Workqueue: events nf_tables_trans_destroy_work [nf_tables] [ 214.398983] RIP: 0010:nf_tables_chain_destroy.isra.38+0x2f9/0x3a0 [nf_tables] [ 214.398983] Code: 00 00 00 fc ff df 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 8e 00 00 00 48 8b 7b 58 e8 e1 2c 4e c6 48 89 df e8 d9 2c 4e c6 eb 9a <0f> 0b eb 96 0f 0b e9 7e fe ff ff e8 a7 7e 4e c6 e9 a4 fe ff ff e8 [ 214.398983] RSP: 0018:ffff8881152874e8 EFLAGS: 00010202 [ 214.398983] RAX: 0000000000000001 RBX: ffff88810ef9fc28 RCX: ffff8881152876f0 [ 214.398983] RDX: dffffc0000000000 RSI: 1ffff11022a50ede RDI: ffff88810ef9fc78 [ 214.398983] RBP: 1ffff11022a50e9d R08: 0000000080000000 R09: 0000000000000000 [ 214.398983] R10: 0000000000000000 R11: 0000000000000000 R12: 1ffff11022a50eba [ 214.398983] R13: ffff888114446e08 R14: ffff8881152876f0 R15: ffffed1022a50ed6 [ 214.398983] FS: 0000000000000000(0000) GS:ffff888116400000(0000) knlGS:0000000000000000 [ 214.398983] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 214.398983] CR2: 00007fab9bb5f868 CR3: 000000012aa16000 CR4: 00000000001006e0 [ 214.398983] Call Trace: [ 214.398983] ? nf_tables_table_destroy.isra.37+0x100/0x100 [nf_tables] [ 214.398983] ? __kasan_slab_free+0x145/0x180 [ 214.398983] ? nf_tables_trans_destroy_work+0x439/0x830 [nf_tables] [ 214.398983] ? kfree+0xdb/0x280 [ 214.398983] nf_tables_trans_destroy_work+0x5f5/0x830 [nf_tables] [ ... ] Fixes: bb7b40aecbf7 ("netfilter: nf_tables: bogus EBUSY in chain deletions") Reported by: Christoph Anton Mitterer Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=914505 Link: https://bugzilla.kernel.org/show_bug.cgi?id=201791 Signed-off-by: Taehee Yoo Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index ea1e57daf50e..623ec29ade26 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2400,21 +2400,14 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, } if (nlh->nlmsg_flags & NLM_F_REPLACE) { - if (!nft_is_active_next(net, old_rule)) { - err = -ENOENT; - goto err2; - } - trans = nft_trans_rule_add(&ctx, NFT_MSG_DELRULE, - old_rule); + trans = nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule); if (trans == NULL) { err = -ENOMEM; goto err2; } - nft_deactivate_next(net, old_rule); - chain->use--; - - if (nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule) == NULL) { - err = -ENOMEM; + err = nft_delrule(&ctx, old_rule); + if (err < 0) { + nft_trans_destroy(trans); goto err2; } -- GitLab From 7b99a0d73be5fdbbdb0a0eef7de211f6359fc210 Mon Sep 17 00:00:00 2001 From: Kiran Kumar Modukuri Date: Mon, 24 Sep 2018 12:02:39 +1000 Subject: [PATCH 0506/1286] cachefiles: Fix page leak in cachefiles_read_backing_file while vmscan is active [ Upstream commit 9a24ce5b66f9c8190d63b15f4473600db4935f1f ] [Description] In a heavily loaded system where the system pagecache is nearing memory limits and fscache is enabled, pages can be leaked by fscache while trying read pages from cachefiles backend. This can happen because two applications can be reading same page from a single mount, two threads can be trying to read the backing page at same time. This results in one of the threads finding that a page for the backing file or netfs file is already in the radix tree. During the error handling cachefiles does not clean up the reference on backing page, leading to page leak. [Fix] The fix is straightforward, to decrement the reference when error is encountered. [dhowells: Note that I've removed the clearance and put of newpage as they aren't attested in the commit message and don't appear to actually achieve anything since a new page is only allocated is newpage!=NULL and any residual new page is cleared before returning.] [Testing] I have tested the fix using following method for 12+ hrs. 1) mkdir -p /mnt/nfs ; mount -o vers=3,fsc :/export /mnt/nfs 2) create 10000 files of 2.8MB in a NFS mount. 3) start a thread to simulate heavy VM presssure (while true ; do echo 3 > /proc/sys/vm/drop_caches ; sleep 1 ; done)& 4) start multiple parallel reader for data set at same time find /mnt/nfs -type f | xargs -P 80 cat > /dev/null & find /mnt/nfs -type f | xargs -P 80 cat > /dev/null & find /mnt/nfs -type f | xargs -P 80 cat > /dev/null & .. .. find /mnt/nfs -type f | xargs -P 80 cat > /dev/null & find /mnt/nfs -type f | xargs -P 80 cat > /dev/null & 5) finally check using cat /proc/fs/fscache/stats | grep -i pages ; free -h , cat /proc/meminfo and page-types -r -b lru to ensure all pages are freed. Reviewed-by: Daniel Axtens Signed-off-by: Shantanu Goel Signed-off-by: Kiran Kumar Modukuri [dja: forward ported to current upstream] Signed-off-by: Daniel Axtens Signed-off-by: David Howells Signed-off-by: Sasha Levin --- fs/cachefiles/rdwr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fs/cachefiles/rdwr.c b/fs/cachefiles/rdwr.c index 199eb396a1bb..54379cf7db7f 100644 --- a/fs/cachefiles/rdwr.c +++ b/fs/cachefiles/rdwr.c @@ -537,7 +537,10 @@ static int cachefiles_read_backing_file(struct cachefiles_object *object, netpage->index, cachefiles_gfp); if (ret < 0) { if (ret == -EEXIST) { + put_page(backpage); + backpage = NULL; put_page(netpage); + netpage = NULL; fscache_retrieval_complete(op, 1); continue; } @@ -610,7 +613,10 @@ static int cachefiles_read_backing_file(struct cachefiles_object *object, netpage->index, cachefiles_gfp); if (ret < 0) { if (ret == -EEXIST) { + put_page(backpage); + backpage = NULL; put_page(netpage); + netpage = NULL; fscache_retrieval_complete(op, 1); continue; } -- GitLab From 9966f78ab603ee58909f411c8b034cef4d1b76ae Mon Sep 17 00:00:00 2001 From: Yunjian Wang Date: Tue, 6 Nov 2018 16:27:12 +0800 Subject: [PATCH 0507/1286] igb: fix uninitialized variables [ Upstream commit e4c39f7926b4de355f7df75651d75003806aae09 ] This patch fixes the variable 'phy_word' may be used uninitialized. Signed-off-by: Yunjian Wang Tested-by: Aaron Brown Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/e1000_i210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c index 07d48f2e3369..6766081f5ab9 100644 --- a/drivers/net/ethernet/intel/igb/e1000_i210.c +++ b/drivers/net/ethernet/intel/igb/e1000_i210.c @@ -862,6 +862,7 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw) nvm_word = E1000_INVM_DEFAULT_AL; tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL; igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, E1000_PHY_PLL_FREQ_PAGE); + phy_word = E1000_PHY_PLL_UNCONF; for (i = 0; i < E1000_MAX_PLL_TRIES; i++) { /* check current state directly from internal PHY */ igb_read_phy_reg_82580(hw, E1000_PHY_PLL_FREQ_REG, &phy_word); -- GitLab From 689dee4b72ff02c5e96afee94bac903b7bab5ed0 Mon Sep 17 00:00:00 2001 From: Josh Elsasser Date: Sat, 24 Nov 2018 12:57:33 -0800 Subject: [PATCH 0508/1286] ixgbe: recognize 1000BaseLX SFP modules as 1Gbps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit a8bf879af7b1999eba36303ce9cc60e0e7dd816c ] Add the two 1000BaseLX enum values to the X550's check for 1Gbps modules, allowing the core driver code to establish a link over this SFP type. This is done by the out-of-tree driver but the fix wasn't in mainline. Fixes: e23f33367882 ("ixgbe: Fix 1G and 10G link stability for X550EM_x SFP+”) Fixes: 6a14ee0cfb19 ("ixgbe: Add X550 support function pointers") Signed-off-by: Josh Elsasser Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c index cf6a245db6d5..a37c951b0753 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c @@ -2257,7 +2257,9 @@ static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, *autoneg = false; if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || - hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { + hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || + hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || + hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { *speed = IXGBE_LINK_SPEED_1GB_FULL; return 0; } -- GitLab From 8a69edb8f7db6908910334399a9829f98163252e Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Wed, 28 Nov 2018 15:30:24 +0800 Subject: [PATCH 0509/1286] net: hisilicon: remove unexpected free_netdev [ Upstream commit c758940158bf29fe14e9d0f89d5848f227b48134 ] The net device ndev is freed via free_netdev when failing to register the device. The control flow then jumps to the error handling code block. ndev is used and freed again. Resulting in a use-after-free bug. Signed-off-by: Pan Bian Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/hisilicon/hip04_eth.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hip04_eth.c b/drivers/net/ethernet/hisilicon/hip04_eth.c index 0cec06bec63e..c27054b8ce81 100644 --- a/drivers/net/ethernet/hisilicon/hip04_eth.c +++ b/drivers/net/ethernet/hisilicon/hip04_eth.c @@ -914,10 +914,8 @@ static int hip04_mac_probe(struct platform_device *pdev) } ret = register_netdev(ndev); - if (ret) { - free_netdev(ndev); + if (ret) goto alloc_fail; - } return 0; -- GitLab From cc92ade5f498bb56f2316588c954d7371849b27b Mon Sep 17 00:00:00 2001 From: shaoyunl Date: Thu, 22 Nov 2018 11:45:24 -0500 Subject: [PATCH 0510/1286] drm/amdgpu: Add delay after enable RLC ucode [ Upstream commit ad97d9de45835b6a0f71983b0ae0cffd7306730a ] Driver shouldn't try to access any GFX registers until RLC is idle. During the test, it took 12 seconds for RLC to clear the BUSY bit in RLC_GPM_STAT register which is un-acceptable for driver. As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK cycles to finish its critical section. In a lowest 300M enginer clock setting(default from vbios), 50 us delay is enough. This commit fix the hang when RLC introduce the work around for XGMI which requires more cycles to setup more registers than normal Signed-off-by: shaoyunl Acked-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3981915e2311..b2eecfc9042e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1992,12 +1992,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) #endif WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); + udelay(50); /* carrizo do enable cp interrupt after cp inited */ - if (!(adev->flags & AMD_IS_APU)) + if (!(adev->flags & AMD_IS_APU)) { gfx_v9_0_enable_gui_idle_interrupt(adev, true); - - udelay(50); + udelay(50); + } #ifdef AMDGPU_RLC_DEBUG_RETRY /* RLC_GPM_GENERAL_6 : RLC Ucode version */ -- GitLab From 6ee9b4deecb18d75a533821864beb6fe598be4fa Mon Sep 17 00:00:00 2001 From: "Y.C. Chen" Date: Thu, 22 Nov 2018 11:56:28 +0800 Subject: [PATCH 0511/1286] drm/ast: fixed reading monitor EDID not stable issue [ Upstream commit 300625620314194d9e6d4f6dda71f2dc9cf62d9f ] v1: over-sample data to increase the stability with some specific monitors v2: refine to avoid infinite loop v3: remove un-necessary "volatile" declaration [airlied: fix two checkpatch warnings] Signed-off-by: Y.C. Chen Signed-off-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/1542858988-1127-1-git-send-email-yc_chen@aspeedtech.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/ast/ast_mode.c | 36 ++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index fae1176b2472..343867b182dd 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -973,9 +973,21 @@ static int get_clock(void *i2c_priv) { struct ast_i2c_chan *i2c = i2c_priv; struct ast_private *ast = i2c->dev->dev_private; - uint32_t val; + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); - val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4; return val & 1 ? 1 : 0; } @@ -983,9 +995,21 @@ static int get_data(void *i2c_priv) { struct ast_i2c_chan *i2c = i2c_priv; struct ast_private *ast = i2c->dev->dev_private; - uint32_t val; + uint32_t val, val2, count, pass; + + count = 0; + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + do { + val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + if (val == val2) { + pass++; + } else { + pass = 0; + val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01; + } + } while ((pass < 5) && (count++ < 0x10000)); - val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5; return val & 1 ? 1 : 0; } @@ -998,7 +1022,7 @@ static void set_clock(void *i2c_priv, int clock) for (i = 0; i < 0x10000; i++) { ujcrb7 = ((clock & 0x01) ? 0 : 1); - ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01); if (ujcrb7 == jtemp) break; @@ -1014,7 +1038,7 @@ static void set_data(void *i2c_priv, int data) for (i = 0; i < 0x10000; i++) { ujcrb7 = ((data & 0x01) ? 0 : 1) << 2; - ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7); + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04); if (ujcrb7 == jtemp) break; -- GitLab From f02e0d5fb6695f69c51c38ef5567a5940791521f Mon Sep 17 00:00:00 2001 From: Srikanth Boddepalli Date: Tue, 27 Nov 2018 19:53:27 +0530 Subject: [PATCH 0512/1286] xen: xlate_mmu: add missing header to fix 'W=1' warning [ Upstream commit 72791ac854fea36034fa7976b748fde585008e78 ] Add a missing header otherwise compiler warns about missed prototype: drivers/xen/xlate_mmu.c:183:5: warning: no previous prototype for 'xen_xlate_unmap_gfn_range?' [-Wmissing-prototypes] int xen_xlate_unmap_gfn_range(struct vm_area_struct *vma, ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Srikanth Boddepalli Reviewed-by: Boris Ostrovsky Reviewed-by: Joey Pabalinas Signed-off-by: Juergen Gross Signed-off-by: Sasha Levin --- drivers/xen/xlate_mmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/xen/xlate_mmu.c b/drivers/xen/xlate_mmu.c index 23f1387b3ef7..e7df65d32c91 100644 --- a/drivers/xen/xlate_mmu.c +++ b/drivers/xen/xlate_mmu.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include -- GitLab From b9c242b4fad864505f679db31531903d1b3779e9 Mon Sep 17 00:00:00 2001 From: Igor Druzhinin Date: Tue, 27 Nov 2018 20:58:21 +0000 Subject: [PATCH 0513/1286] Revert "xen/balloon: Mark unallocated host memory as UNUSABLE" [ Upstream commit 123664101aa2156d05251704fc63f9bcbf77741a ] This reverts commit b3cf8528bb21febb650a7ecbf080d0647be40b9f. That commit unintentionally broke Xen balloon memory hotplug with "hotplug_unpopulated" set to 1. As long as "System RAM" resource got assigned under a new "Unusable memory" resource in IO/Mem tree any attempt to online this memory would fail due to general kernel restrictions on having "System RAM" resources as 1st level only. The original issue that commit has tried to workaround fa564ad96366 ("x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f)") also got amended by the following 03a551734 ("x86/PCI: Move and shrink AMD 64-bit window to avoid conflict") which made the original fix to Xen ballooning unnecessary. Signed-off-by: Igor Druzhinin Reviewed-by: Boris Ostrovsky Signed-off-by: Juergen Gross Signed-off-by: Sasha Levin --- arch/x86/xen/enlighten.c | 78 ---------------------------------------- arch/x86/xen/setup.c | 6 ++-- drivers/xen/balloon.c | 65 +++++---------------------------- include/xen/balloon.h | 5 --- 4 files changed, 13 insertions(+), 141 deletions(-) diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index df208af3cd74..515d5e4414c2 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -7,7 +7,6 @@ #include #include -#include #include #include @@ -336,80 +335,3 @@ void xen_arch_unregister_cpu(int num) } EXPORT_SYMBOL(xen_arch_unregister_cpu); #endif - -#ifdef CONFIG_XEN_BALLOON_MEMORY_HOTPLUG -void __init arch_xen_balloon_init(struct resource *hostmem_resource) -{ - struct xen_memory_map memmap; - int rc; - unsigned int i, last_guest_ram; - phys_addr_t max_addr = PFN_PHYS(max_pfn); - struct e820_table *xen_e820_table; - const struct e820_entry *entry; - struct resource *res; - - if (!xen_initial_domain()) - return; - - xen_e820_table = kmalloc(sizeof(*xen_e820_table), GFP_KERNEL); - if (!xen_e820_table) - return; - - memmap.nr_entries = ARRAY_SIZE(xen_e820_table->entries); - set_xen_guest_handle(memmap.buffer, xen_e820_table->entries); - rc = HYPERVISOR_memory_op(XENMEM_machine_memory_map, &memmap); - if (rc) { - pr_warn("%s: Can't read host e820 (%d)\n", __func__, rc); - goto out; - } - - last_guest_ram = 0; - for (i = 0; i < memmap.nr_entries; i++) { - if (xen_e820_table->entries[i].addr >= max_addr) - break; - if (xen_e820_table->entries[i].type == E820_TYPE_RAM) - last_guest_ram = i; - } - - entry = &xen_e820_table->entries[last_guest_ram]; - if (max_addr >= entry->addr + entry->size) - goto out; /* No unallocated host RAM. */ - - hostmem_resource->start = max_addr; - hostmem_resource->end = entry->addr + entry->size; - - /* - * Mark non-RAM regions between the end of dom0 RAM and end of host RAM - * as unavailable. The rest of that region can be used for hotplug-based - * ballooning. - */ - for (; i < memmap.nr_entries; i++) { - entry = &xen_e820_table->entries[i]; - - if (entry->type == E820_TYPE_RAM) - continue; - - if (entry->addr >= hostmem_resource->end) - break; - - res = kzalloc(sizeof(*res), GFP_KERNEL); - if (!res) - goto out; - - res->name = "Unavailable host RAM"; - res->start = entry->addr; - res->end = (entry->addr + entry->size < hostmem_resource->end) ? - entry->addr + entry->size : hostmem_resource->end; - rc = insert_resource(hostmem_resource, res); - if (rc) { - pr_warn("%s: Can't insert [%llx - %llx) (%d)\n", - __func__, res->start, res->end, rc); - kfree(res); - goto out; - } - } - - out: - kfree(xen_e820_table); -} -#endif /* CONFIG_XEN_BALLOON_MEMORY_HOTPLUG */ diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index 6e0d2086eacb..c114ca767b3b 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -808,6 +808,7 @@ char * __init xen_memory_setup(void) addr = xen_e820_table.entries[0].addr; size = xen_e820_table.entries[0].size; while (i < xen_e820_table.nr_entries) { + bool discard = false; chunk_size = size; type = xen_e820_table.entries[i].type; @@ -823,10 +824,11 @@ char * __init xen_memory_setup(void) xen_add_extra_mem(pfn_s, n_pfns); xen_max_p2m_pfn = pfn_s + n_pfns; } else - type = E820_TYPE_UNUSABLE; + discard = true; } - xen_align_and_add_e820_region(addr, chunk_size, type); + if (!discard) + xen_align_and_add_e820_region(addr, chunk_size, type); addr += chunk_size; size -= chunk_size; diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c index 065f0b607373..f77e499afddd 100644 --- a/drivers/xen/balloon.c +++ b/drivers/xen/balloon.c @@ -257,25 +257,10 @@ static void release_memory_resource(struct resource *resource) kfree(resource); } -/* - * Host memory not allocated to dom0. We can use this range for hotplug-based - * ballooning. - * - * It's a type-less resource. Setting IORESOURCE_MEM will make resource - * management algorithms (arch_remove_reservations()) look into guest e820, - * which we don't want. - */ -static struct resource hostmem_resource = { - .name = "Host RAM", -}; - -void __attribute__((weak)) __init arch_xen_balloon_init(struct resource *res) -{} - static struct resource *additional_memory_resource(phys_addr_t size) { - struct resource *res, *res_hostmem; - int ret = -ENOMEM; + struct resource *res; + int ret; res = kzalloc(sizeof(*res), GFP_KERNEL); if (!res) @@ -284,42 +269,13 @@ static struct resource *additional_memory_resource(phys_addr_t size) res->name = "System RAM"; res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; - res_hostmem = kzalloc(sizeof(*res), GFP_KERNEL); - if (res_hostmem) { - /* Try to grab a range from hostmem */ - res_hostmem->name = "Host memory"; - ret = allocate_resource(&hostmem_resource, res_hostmem, - size, 0, -1, - PAGES_PER_SECTION * PAGE_SIZE, NULL, NULL); - } - - if (!ret) { - /* - * Insert this resource into iomem. Because hostmem_resource - * tracks portion of guest e820 marked as UNUSABLE noone else - * should try to use it. - */ - res->start = res_hostmem->start; - res->end = res_hostmem->end; - ret = insert_resource(&iomem_resource, res); - if (ret < 0) { - pr_err("Can't insert iomem_resource [%llx - %llx]\n", - res->start, res->end); - release_memory_resource(res_hostmem); - res_hostmem = NULL; - res->start = res->end = 0; - } - } - - if (ret) { - ret = allocate_resource(&iomem_resource, res, - size, 0, -1, - PAGES_PER_SECTION * PAGE_SIZE, NULL, NULL); - if (ret < 0) { - pr_err("Cannot allocate new System RAM resource\n"); - kfree(res); - return NULL; - } + ret = allocate_resource(&iomem_resource, res, + size, 0, -1, + PAGES_PER_SECTION * PAGE_SIZE, NULL, NULL); + if (ret < 0) { + pr_err("Cannot allocate new System RAM resource\n"); + kfree(res); + return NULL; } #ifdef CONFIG_SPARSEMEM @@ -331,7 +287,6 @@ static struct resource *additional_memory_resource(phys_addr_t size) pr_err("New System RAM resource outside addressable RAM (%lu > %lu)\n", pfn, limit); release_memory_resource(res); - release_memory_resource(res_hostmem); return NULL; } } @@ -810,8 +765,6 @@ static int __init balloon_init(void) set_online_page_callback(&xen_online_page); register_memory_notifier(&xen_memory_nb); register_sysctl_table(xen_root); - - arch_xen_balloon_init(&hostmem_resource); #endif #ifdef CONFIG_XEN_PV diff --git a/include/xen/balloon.h b/include/xen/balloon.h index 61f410fd74e4..4914b93a23f2 100644 --- a/include/xen/balloon.h +++ b/include/xen/balloon.h @@ -44,8 +44,3 @@ static inline void xen_balloon_init(void) { } #endif - -#ifdef CONFIG_XEN_BALLOON_MEMORY_HOTPLUG -struct resource; -void arch_xen_balloon_init(struct resource *hostmem_resource); -#endif -- GitLab From b718d6bede4bd6c8c6faac1369567f3d7587d4c1 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 1 Nov 2018 16:17:22 -0700 Subject: [PATCH 0514/1286] pstore/ram: Correctly calculate usable PRZ bytes [ Upstream commit 89d328f637b9904b6d4c9af73c8a608b8dd4d6f8 ] The actual number of bytes stored in a PRZ is smaller than the bytes requested by platform data, since there is a header on each PRZ. Additionally, if ECC is enabled, there are trailing bytes used as well. Normally this mismatch doesn't matter since PRZs are circular buffers and the leading "overflow" bytes are just thrown away. However, in the case of a compressed record, this rather badly corrupts the results. This corruption was visible with "ramoops.mem_size=204800 ramoops.ecc=1". Any stored crashes would not be uncompressable (producing a pstorefs "dmesg-*.enc.z" file), and triggering errors at boot: [ 2.790759] pstore: crypto_comp_decompress failed, ret = -22! Backporting this depends on commit 70ad35db3321 ("pstore: Convert console write to use ->write_buf") Reported-by: Joel Fernandes Fixes: b0aad7a99c1d ("pstore: Add compression support to pstore") Signed-off-by: Kees Cook Reviewed-by: Joel Fernandes (Google) Signed-off-by: Sasha Levin --- fs/pstore/ram.c | 15 ++++++--------- include/linux/pstore.h | 5 ++++- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c index 7125b398d312..9f7e546d7050 100644 --- a/fs/pstore/ram.c +++ b/fs/pstore/ram.c @@ -804,17 +804,14 @@ static int ramoops_probe(struct platform_device *pdev) cxt->pstore.data = cxt; /* - * Console can handle any buffer size, so prefer LOG_LINE_MAX. If we - * have to handle dumps, we must have at least record_size buffer. And - * for ftrace, bufsize is irrelevant (if bufsize is 0, buf will be - * ZERO_SIZE_PTR). + * Since bufsize is only used for dmesg crash dumps, it + * must match the size of the dprz record (after PRZ header + * and ECC bytes have been accounted for). */ - if (cxt->console_size) - cxt->pstore.bufsize = 1024; /* LOG_LINE_MAX */ - cxt->pstore.bufsize = max(cxt->record_size, cxt->pstore.bufsize); - cxt->pstore.buf = kmalloc(cxt->pstore.bufsize, GFP_KERNEL); + cxt->pstore.bufsize = cxt->dprzs[0]->buffer_size; + cxt->pstore.buf = kzalloc(cxt->pstore.bufsize, GFP_KERNEL); if (!cxt->pstore.buf) { - pr_err("cannot allocate pstore buffer\n"); + pr_err("cannot allocate pstore crash dump buffer\n"); err = -ENOMEM; goto fail_clear; } diff --git a/include/linux/pstore.h b/include/linux/pstore.h index 61f806a7fe29..170bb981d2fd 100644 --- a/include/linux/pstore.h +++ b/include/linux/pstore.h @@ -90,7 +90,10 @@ struct pstore_record { * * @buf_lock: spinlock to serialize access to @buf * @buf: preallocated crash dump buffer - * @bufsize: size of @buf available for crash dump writes + * @bufsize: size of @buf available for crash dump bytes (must match + * smallest number of bytes available for writing to a + * backend entry, since compressed bytes don't take kindly + * to being truncated) * * @read_mutex: serializes @open, @read, @close, and @erase callbacks * @flags: bitfield of frontends the backend can accept writes for -- GitLab From 38026d1afcc1153aa6efebaeac7fc2a31c2779d0 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Fri, 26 Oct 2018 17:16:29 +1100 Subject: [PATCH 0515/1286] fscache: fix race between enablement and dropping of object [ Upstream commit c5a94f434c82529afda290df3235e4d85873c5b4 ] It was observed that a process blocked indefintely in __fscache_read_or_alloc_page(), waiting for FSCACHE_COOKIE_LOOKING_UP to be cleared via fscache_wait_for_deferred_lookup(). At this time, ->backing_objects was empty, which would normaly prevent __fscache_read_or_alloc_page() from getting to the point of waiting. This implies that ->backing_objects was cleared *after* __fscache_read_or_alloc_page was was entered. When an object is "killed" and then "dropped", FSCACHE_COOKIE_LOOKING_UP is cleared in fscache_lookup_failure(), then KILL_OBJECT and DROP_OBJECT are "called" and only in DROP_OBJECT is ->backing_objects cleared. This leaves a window where something else can set FSCACHE_COOKIE_LOOKING_UP and __fscache_read_or_alloc_page() can start waiting, before ->backing_objects is cleared There is some uncertainty in this analysis, but it seems to be fit the observations. Adding the wake in this patch will be handled correctly by __fscache_read_or_alloc_page(), as it checks if ->backing_objects is empty again, after waiting. Customer which reported the hang, also report that the hang cannot be reproduced with this fix. The backtrace for the blocked process looked like: PID: 29360 TASK: ffff881ff2ac0f80 CPU: 3 COMMAND: "zsh" #0 [ffff881ff43efbf8] schedule at ffffffff815e56f1 #1 [ffff881ff43efc58] bit_wait at ffffffff815e64ed #2 [ffff881ff43efc68] __wait_on_bit at ffffffff815e61b8 #3 [ffff881ff43efca0] out_of_line_wait_on_bit at ffffffff815e625e #4 [ffff881ff43efd08] fscache_wait_for_deferred_lookup at ffffffffa04f2e8f [fscache] #5 [ffff881ff43efd18] __fscache_read_or_alloc_page at ffffffffa04f2ffe [fscache] #6 [ffff881ff43efd58] __nfs_readpage_from_fscache at ffffffffa0679668 [nfs] #7 [ffff881ff43efd78] nfs_readpage at ffffffffa067092b [nfs] #8 [ffff881ff43efda0] generic_file_read_iter at ffffffff81187a73 #9 [ffff881ff43efe50] nfs_file_read at ffffffffa066544b [nfs] #10 [ffff881ff43efe70] __vfs_read at ffffffff811fc756 #11 [ffff881ff43efee8] vfs_read at ffffffff811fccfa #12 [ffff881ff43eff18] sys_read at ffffffff811fda62 #13 [ffff881ff43eff50] entry_SYSCALL_64_fastpath at ffffffff815e986e Signed-off-by: NeilBrown Signed-off-by: David Howells Signed-off-by: Sasha Levin --- fs/fscache/object.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/fscache/object.c b/fs/fscache/object.c index 7a182c87f378..ab1d7f35f6c2 100644 --- a/fs/fscache/object.c +++ b/fs/fscache/object.c @@ -715,6 +715,9 @@ static const struct fscache_state *fscache_drop_object(struct fscache_object *ob if (awaken) wake_up_bit(&cookie->flags, FSCACHE_COOKIE_INVALIDATING); + if (test_and_clear_bit(FSCACHE_COOKIE_LOOKING_UP, &cookie->flags)) + wake_up_bit(&cookie->flags, FSCACHE_COOKIE_LOOKING_UP); + /* Prevent a race with our last child, which has to signal EV_CLEARED * before dropping our spinlock. -- GitLab From 0859bb2526fb3725d2b53142e67be38e12fca72b Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 17 Jul 2018 09:53:42 +0100 Subject: [PATCH 0516/1286] fscache, cachefiles: remove redundant variable 'cache' [ Upstream commit 31ffa563833576bd49a8bf53120568312755e6e2 ] Variable 'cache' is being assigned but is never used hence it is redundant and can be removed. Cleans up clang warning: warning: variable 'cache' set but not used [-Wunused-but-set-variable] Signed-off-by: Colin Ian King Signed-off-by: David Howells Signed-off-by: Sasha Levin --- fs/cachefiles/rdwr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/fs/cachefiles/rdwr.c b/fs/cachefiles/rdwr.c index 54379cf7db7f..5e9176ec0d3a 100644 --- a/fs/cachefiles/rdwr.c +++ b/fs/cachefiles/rdwr.c @@ -969,11 +969,8 @@ int cachefiles_write_page(struct fscache_storage *op, struct page *page) void cachefiles_uncache_page(struct fscache_object *_object, struct page *page) { struct cachefiles_object *object; - struct cachefiles_cache *cache; object = container_of(_object, struct cachefiles_object, fscache); - cache = container_of(object->fscache.cache, - struct cachefiles_cache, cache); _enter("%p,{%lu}", object, page->index); -- GitLab From 9407fd14d0ee929ea21571055ccf4361b6e2323a Mon Sep 17 00:00:00 2001 From: Sagi Grimberg Date: Wed, 21 Nov 2018 15:17:37 -0800 Subject: [PATCH 0517/1286] nvme: flush namespace scanning work just before removing namespaces [ Upstream commit f6c8e432cb0479255322c5d0335b9f1699a0270c ] nvme_stop_ctrl can be called also for reset flow and there is no need to flush the scan_work as namespaces are not being removed. This can cause deadlock in rdma, fc and loop drivers since nvme_stop_ctrl barriers before controller teardown (and specifically I/O cancellation of the scan_work itself) takes place, but the scan_work will be blocked anyways so there is no need to flush it. Instead, move scan_work flush to nvme_remove_namespaces() where it really needs to flush. Reported-by: Ming Lei Signed-off-by: Sagi Grimberg Reviewed-by: Keith Busch Reviewed by: James Smart Tested-by: Ewan D. Milne Signed-off-by: Christoph Hellwig Signed-off-by: Sasha Levin --- drivers/nvme/host/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index 3a63d58d2ca9..65f3f1a34b6b 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2572,6 +2572,9 @@ void nvme_remove_namespaces(struct nvme_ctrl *ctrl) { struct nvme_ns *ns, *next; + /* prevent racing with ns scanning */ + flush_work(&ctrl->scan_work); + /* * The dead states indicates the controller was not gracefully * disconnected. In that case, we won't be able to flush any data while @@ -2743,7 +2746,6 @@ void nvme_stop_ctrl(struct nvme_ctrl *ctrl) { nvme_stop_keep_alive(ctrl); flush_work(&ctrl->async_event_work); - flush_work(&ctrl->scan_work); cancel_work_sync(&ctrl->fw_act_work); } EXPORT_SYMBOL_GPL(nvme_stop_ctrl); -- GitLab From 8e3f3c06be02aaf0b09f11eafc3e2f567bdbd6d2 Mon Sep 17 00:00:00 2001 From: Lorenzo Pieralisi Date: Thu, 29 Nov 2018 09:55:59 +0000 Subject: [PATCH 0518/1286] ACPI/IORT: Fix iort_get_platform_device_domain() uninitialized pointer value [ Upstream commit ea2412dc21cc790335d319181dddc43682aef164 ] Running the Clang static analyzer on IORT code detected the following error: Logic error: Branch condition evaluates to a garbage value in iort_get_platform_device_domain() If the named component associated with a given device has no IORT mappings, iort_get_platform_device_domain() exits its MSI mapping loop with msi_parent pointer containing garbage, which can lead to erroneous code path execution. Initialize the msi_parent pointer, fixing the bug. Fixes: d4f54a186667 ("ACPI: platform: setup MSI domain for ACPI based platform device") Reported-by: Patrick Bellasi Reviewed-by: Hanjun Guo Acked-by: Will Deacon Cc: Sudeep Holla Cc: "Rafael J. Wysocki" Signed-off-by: Lorenzo Pieralisi Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- drivers/acpi/arm64/iort.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index de56394dd161..ca414910710e 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -547,7 +547,7 @@ struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id) */ static struct irq_domain *iort_get_platform_device_domain(struct device *dev) { - struct acpi_iort_node *node, *msi_parent; + struct acpi_iort_node *node, *msi_parent = NULL; struct fwnode_handle *iort_fwnode; struct acpi_iort_its_group *its; int i; -- GitLab From df2055c0eb8af72790060d6797cac9be56622412 Mon Sep 17 00:00:00 2001 From: Larry Chen Date: Fri, 30 Nov 2018 14:08:56 -0800 Subject: [PATCH 0519/1286] ocfs2: fix deadlock caused by ocfs2_defrag_extent() [ Upstream commit e21e57445a64598b29a6f629688f9b9a39e7242a ] ocfs2_defrag_extent may fall into deadlock. ocfs2_ioctl_move_extents ocfs2_ioctl_move_extents ocfs2_move_extents ocfs2_defrag_extent ocfs2_lock_allocators_move_extents ocfs2_reserve_clusters inode_lock GLOBAL_BITMAP_SYSTEM_INODE __ocfs2_flush_truncate_log inode_lock GLOBAL_BITMAP_SYSTEM_INODE As backtrace shows above, ocfs2_reserve_clusters() will call inode_lock against the global bitmap if local allocator has not sufficient cluters. Once global bitmap could meet the demand, ocfs2_reserve_cluster will return success with global bitmap locked. After ocfs2_reserve_cluster(), if truncate log is full, __ocfs2_flush_truncate_log() will definitely fall into deadlock because it needs to inode_lock global bitmap, which has already been locked. To fix this bug, we could remove from ocfs2_lock_allocators_move_extents() the code which intends to lock global allocator, and put the removed code after __ocfs2_flush_truncate_log(). ocfs2_lock_allocators_move_extents() is referred by 2 places, one is here, the other does not need the data allocator context, which means this patch does not affect the caller so far. Link: http://lkml.kernel.org/r/20181101071422.14470-1-lchen@suse.com Signed-off-by: Larry Chen Reviewed-by: Changwei Ge Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Joseph Qi Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/ocfs2/move_extents.c | 47 +++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/fs/ocfs2/move_extents.c b/fs/ocfs2/move_extents.c index 7eb3b0a6347e..f55f82ca3425 100644 --- a/fs/ocfs2/move_extents.c +++ b/fs/ocfs2/move_extents.c @@ -156,18 +156,14 @@ static int __ocfs2_move_extent(handle_t *handle, } /* - * lock allocators, and reserving appropriate number of bits for - * meta blocks and data clusters. - * - * in some cases, we don't need to reserve clusters, just let data_ac - * be NULL. + * lock allocator, and reserve appropriate number of bits for + * meta blocks. */ -static int ocfs2_lock_allocators_move_extents(struct inode *inode, +static int ocfs2_lock_meta_allocator_move_extents(struct inode *inode, struct ocfs2_extent_tree *et, u32 clusters_to_move, u32 extents_to_split, struct ocfs2_alloc_context **meta_ac, - struct ocfs2_alloc_context **data_ac, int extra_blocks, int *credits) { @@ -192,13 +188,6 @@ static int ocfs2_lock_allocators_move_extents(struct inode *inode, goto out; } - if (data_ac) { - ret = ocfs2_reserve_clusters(osb, clusters_to_move, data_ac); - if (ret) { - mlog_errno(ret); - goto out; - } - } *credits += ocfs2_calc_extend_credits(osb->sb, et->et_root_el); @@ -257,10 +246,10 @@ static int ocfs2_defrag_extent(struct ocfs2_move_extents_context *context, } } - ret = ocfs2_lock_allocators_move_extents(inode, &context->et, *len, 1, - &context->meta_ac, - &context->data_ac, - extra_blocks, &credits); + ret = ocfs2_lock_meta_allocator_move_extents(inode, &context->et, + *len, 1, + &context->meta_ac, + extra_blocks, &credits); if (ret) { mlog_errno(ret); goto out; @@ -283,6 +272,21 @@ static int ocfs2_defrag_extent(struct ocfs2_move_extents_context *context, } } + /* + * Make sure ocfs2_reserve_cluster is called after + * __ocfs2_flush_truncate_log, otherwise, dead lock may happen. + * + * If ocfs2_reserve_cluster is called + * before __ocfs2_flush_truncate_log, dead lock on global bitmap + * may happen. + * + */ + ret = ocfs2_reserve_clusters(osb, *len, &context->data_ac); + if (ret) { + mlog_errno(ret); + goto out_unlock_mutex; + } + handle = ocfs2_start_trans(osb, credits); if (IS_ERR(handle)) { ret = PTR_ERR(handle); @@ -600,9 +604,10 @@ static int ocfs2_move_extent(struct ocfs2_move_extents_context *context, } } - ret = ocfs2_lock_allocators_move_extents(inode, &context->et, len, 1, - &context->meta_ac, - NULL, extra_blocks, &credits); + ret = ocfs2_lock_meta_allocator_move_extents(inode, &context->et, + len, 1, + &context->meta_ac, + extra_blocks, &credits); if (ret) { mlog_errno(ret); goto out; -- GitLab From c7aafad098b066ceee0d6a3b2ba63573ef09dc38 Mon Sep 17 00:00:00 2001 From: Wei Yang Date: Fri, 30 Nov 2018 14:09:07 -0800 Subject: [PATCH 0520/1286] mm/page_alloc.c: fix calculation of pgdat->nr_zones [ Upstream commit 8f416836c0d50b198cad1225132e5abebf8980dc ] init_currently_empty_zone() will adjust pgdat->nr_zones and set it to 'zone_idx(zone) + 1' unconditionally. This is correct in the normal case, while not exact in hot-plug situation. This function is used in two places: * free_area_init_core() * move_pfn_range_to_zone() In the first case, we are sure zone index increase monotonically. While in the second one, this is under users control. One way to reproduce this is: ---------------------------- 1. create a virtual machine with empty node1 -m 4G,slots=32,maxmem=32G \ -smp 4,maxcpus=8 \ -numa node,nodeid=0,mem=4G,cpus=0-3 \ -numa node,nodeid=1,mem=0G,cpus=4-7 2. hot-add cpu 3-7 cpu-add [3-7] 2. hot-add memory to nod1 object_add memory-backend-ram,id=ram0,size=1G device_add pc-dimm,id=dimm0,memdev=ram0,node=1 3. online memory with following order echo online_movable > memory47/state echo online > memory40/state After this, node1 will have its nr_zones equals to (ZONE_NORMAL + 1) instead of (ZONE_MOVABLE + 1). Michal said: "Having an incorrect nr_zones might result in all sorts of problems which would be quite hard to debug (e.g. reclaim not considering the movable zone). I do not expect many users would suffer from this it but still this is trivial and obviously right thing to do so backporting to the stable tree shouldn't be harmful (last famous words)" Link: http://lkml.kernel.org/r/20181117022022.9956-1-richard.weiyang@gmail.com Fixes: f1dd2cd13c4b ("mm, memory_hotplug: do not associate hotadded memory to zones until online") Signed-off-by: Wei Yang Acked-by: Michal Hocko Reviewed-by: Oscar Salvador Cc: Anshuman Khandual Cc: Dave Hansen Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- mm/page_alloc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 6be91a1a00d9..a2f365f40433 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -5544,8 +5544,10 @@ void __meminit init_currently_empty_zone(struct zone *zone, unsigned long size) { struct pglist_data *pgdat = zone->zone_pgdat; + int zone_idx = zone_idx(zone) + 1; - pgdat->nr_zones = zone_idx(zone) + 1; + if (zone_idx > pgdat->nr_zones) + pgdat->nr_zones = zone_idx; zone->zone_start_pfn = zone_start_pfn; -- GitLab From 5ee5fa61d04e2bd8ab004f307bd6ad0808482746 Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Fri, 30 Nov 2018 14:09:14 -0800 Subject: [PATCH 0521/1286] hfs: do not free node before using [ Upstream commit ce96a407adef126870b3f4a1b73529dd8aa80f49 ] hfs_bmap_free() frees the node via hfs_bnode_put(node). However, it then reads node->this when dumping error message on an error path, which may result in a use-after-free bug. This patch frees the node only when it is never again used. Link: http://lkml.kernel.org/r/1542963889-128825-1-git-send-email-bianpan2016@163.com Fixes: a1185ffa2fc ("HFS rewrite") Signed-off-by: Pan Bian Reviewed-by: Andrew Morton Cc: Joe Perches Cc: Ernesto A. Fernandez Cc: Viacheslav Dubeyko Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/hfs/btree.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/hfs/btree.c b/fs/hfs/btree.c index 374b5688e29e..9bdff5e40626 100644 --- a/fs/hfs/btree.c +++ b/fs/hfs/btree.c @@ -329,13 +329,14 @@ void hfs_bmap_free(struct hfs_bnode *node) nidx -= len * 8; i = node->next; - hfs_bnode_put(node); if (!i) { /* panic */; pr_crit("unable to free bnode %u. bmap not found!\n", node->this); + hfs_bnode_put(node); return; } + hfs_bnode_put(node); node = hfs_bnode_find(tree, i); if (IS_ERR(node)) return; -- GitLab From 95c8714e3fa0bee316600c46fd007fec2750206b Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Fri, 30 Nov 2018 14:09:18 -0800 Subject: [PATCH 0522/1286] hfsplus: do not free node before using [ Upstream commit c7d7d620dcbd2a1c595092280ca943f2fced7bbd ] hfs_bmap_free() frees node via hfs_bnode_put(node). However it then reads node->this when dumping error message on an error path, which may result in a use-after-free bug. This patch frees node only when it is never used. Link: http://lkml.kernel.org/r/1543053441-66942-1-git-send-email-bianpan2016@163.com Signed-off-by: Pan Bian Reviewed-by: Andrew Morton Cc: Ernesto A. Fernandez Cc: Joe Perches Cc: Viacheslav Dubeyko Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/hfsplus/btree.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/hfsplus/btree.c b/fs/hfsplus/btree.c index de14b2b6881b..3de3bc4918b5 100644 --- a/fs/hfsplus/btree.c +++ b/fs/hfsplus/btree.c @@ -454,14 +454,15 @@ void hfs_bmap_free(struct hfs_bnode *node) nidx -= len * 8; i = node->next; - hfs_bnode_put(node); if (!i) { /* panic */; pr_crit("unable to free bnode %u. " "bmap not found!\n", node->this); + hfs_bnode_put(node); return; } + hfs_bnode_put(node); node = hfs_bnode_find(tree, i); if (IS_ERR(node)) return; -- GitLab From 225b11374625aa4827fc1ee0b810c27dfe851809 Mon Sep 17 00:00:00 2001 From: Qian Cai Date: Fri, 30 Nov 2018 14:09:48 -0800 Subject: [PATCH 0523/1286] debugobjects: avoid recursive calls with kmemleak [ Upstream commit 8de456cf87ba863e028c4dd01bae44255ce3d835 ] CONFIG_DEBUG_OBJECTS_RCU_HEAD does not play well with kmemleak due to recursive calls. fill_pool kmemleak_ignore make_black_object put_object __call_rcu (kernel/rcu/tree.c) debug_rcu_head_queue debug_object_activate debug_object_init fill_pool kmemleak_ignore make_black_object ... So add SLAB_NOLEAKTRACE to kmem_cache_create() to not register newly allocated debug objects at all. Link: http://lkml.kernel.org/r/20181126165343.2339-1-cai@gmx.us Signed-off-by: Qian Cai Suggested-by: Catalin Marinas Acked-by: Waiman Long Acked-by: Catalin Marinas Cc: Thomas Gleixner Cc: Yang Shi Cc: Arnd Bergmann Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- lib/debugobjects.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 99308479b1c8..bacb00a9cd9f 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -111,7 +111,6 @@ static void fill_pool(void) if (!new) return; - kmemleak_ignore(new); raw_spin_lock_irqsave(&pool_lock, flags); hlist_add_head(&new->node, &obj_pool); debug_objects_allocated++; @@ -1085,7 +1084,6 @@ static int __init debug_objects_replace_static_objects(void) obj = kmem_cache_zalloc(obj_cache, GFP_KERNEL); if (!obj) goto free; - kmemleak_ignore(obj); hlist_add_head(&obj->node, &objects); } @@ -1141,7 +1139,8 @@ void __init debug_objects_mem_init(void) obj_cache = kmem_cache_create("debug_objects_cache", sizeof (struct debug_obj), 0, - SLAB_DEBUG_OBJECTS, NULL); + SLAB_DEBUG_OBJECTS | SLAB_NOLEAKTRACE, + NULL); if (!obj_cache || debug_objects_replace_static_objects()) { debug_objects_enabled = 0; -- GitLab From 56926f913bf8284f0d33d79cdf0421f0caec8a1f Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Fri, 30 Nov 2018 14:10:54 -0800 Subject: [PATCH 0524/1286] ocfs2: fix potential use after free [ Upstream commit 164f7e586739d07eb56af6f6d66acebb11f315c8 ] ocfs2_get_dentry() calls iput(inode) to drop the reference count of inode, and if the reference count hits 0, inode is freed. However, in this function, it then reads inode->i_generation, which may result in a use after free bug. Move the put operation later. Link: http://lkml.kernel.org/r/1543109237-110227-1-git-send-email-bianpan2016@163.com Fixes: 781f200cb7a("ocfs2: Remove masklog ML_EXPORT.") Signed-off-by: Pan Bian Reviewed-by: Andrew Morton Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Joseph Qi Cc: Changwei Ge Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- fs/ocfs2/export.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ocfs2/export.c b/fs/ocfs2/export.c index 9f88188060db..4bf8d5854b27 100644 --- a/fs/ocfs2/export.c +++ b/fs/ocfs2/export.c @@ -125,10 +125,10 @@ static struct dentry *ocfs2_get_dentry(struct super_block *sb, check_gen: if (handle->ih_generation != inode->i_generation) { - iput(inode); trace_ocfs2_get_dentry_generation((unsigned long long)blkno, handle->ih_generation, inode->i_generation); + iput(inode); result = ERR_PTR(-ESTALE); goto bail; } -- GitLab From 62582f67ff7617313b27b897ed02b569b712dcac Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Thu, 13 Dec 2018 09:24:35 -0500 Subject: [PATCH 0525/1286] Revert "printk: Never set console_may_schedule in console_trylock()" This reverts commit c9b8d580b3fb0ab65d37c372aef19a318fda3199. This is just a technical revert to make the printk fix apply cleanly, this patch will be re-picked in about 3 commits. --- kernel/printk/printk.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index a9cf2e15f6a3..7161312593dd 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -1762,12 +1762,6 @@ asmlinkage int vprintk_emit(int facility, int level, /* If called from the scheduler, we can not call up(). */ if (!in_sched) { - /* - * Disable preemption to avoid being preempted while holding - * console_sem which would prevent anyone from printing to - * console - */ - preempt_disable(); /* * Try to acquire and then immediately release the console * semaphore. The release will print out buffers and wake up @@ -1775,7 +1769,6 @@ asmlinkage int vprintk_emit(int facility, int level, */ if (console_trylock()) console_unlock(); - preempt_enable(); } return printed_len; @@ -2090,7 +2083,20 @@ int console_trylock(void) return 0; } console_locked = 1; - console_may_schedule = 0; + /* + * When PREEMPT_COUNT disabled we can't reliably detect if it's + * safe to schedule (e.g. calling printk while holding a spin_lock), + * because preempt_disable()/preempt_enable() are just barriers there + * and preempt_count() is always 0. + * + * RCU read sections have a separate preemption counter when + * PREEMPT_RCU enabled thus we must take extra care and check + * rcu_preempt_depth(), otherwise RCU read sections modify + * preempt_count(). + */ + console_may_schedule = !oops_in_progress && + preemptible() && + !rcu_preempt_depth(); return 1; } EXPORT_SYMBOL(console_trylock); -- GitLab From 594231141b003939444a1202a02992b3d0adb23e Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Wed, 10 Jan 2018 14:24:17 +0100 Subject: [PATCH 0526/1286] printk: Add console owner and waiter logic to load balance console writes [ Upstream commit dbdda842fe96f8932bae554f0adf463c27c42bc7 ] This patch implements what I discussed in Kernel Summit. I added lockdep annotation (hopefully correctly), and it hasn't had any splats (since I fixed some bugs in the first iterations). It did catch problems when I had the owner covering too much. But now that the owner is only set when actively calling the consoles, lockdep has stayed quiet. Here's the design again: I added a "console_owner" which is set to a task that is actively writing to the consoles. It is *not* the same as the owner of the console_lock. It is only set when doing the calls to the console functions. It is protected by a console_owner_lock which is a raw spin lock. There is a console_waiter. This is set when there is an active console owner that is not current, and waiter is not set. This too is protected by console_owner_lock. In printk() when it tries to write to the consoles, we have: if (console_trylock()) console_unlock(); Now I added an else, which will check if there is an active owner, and no current waiter. If that is the case, then console_waiter is set, and the task goes into a spin until it is no longer set. When the active console owner finishes writing the current message to the consoles, it grabs the console_owner_lock and sees if there is a waiter, and clears console_owner. If there is a waiter, then it breaks out of the loop, clears the waiter flag (because that will release the waiter from its spin), and exits. Note, it does *not* release the console semaphore. Because it is a semaphore, there is no owner. Another task may release it. This means that the waiter is guaranteed to be the new console owner! Which it becomes. Then the waiter calls console_unlock() and continues to write to the consoles. If another task comes along and does a printk() it too can become the new waiter, and we wash rinse and repeat! By Petr Mladek about possible new deadlocks: The thing is that we move console_sem only to printk() call that normally calls console_unlock() as well. It means that the transferred owner should not bring new type of dependencies. As Steven said somewhere: "If there is a deadlock, it was there even before." We could look at it from this side. The possible deadlock would look like: CPU0 CPU1 console_unlock() console_owner = current; spin_lockA() printk() spin = true; while (...) call_console_drivers() spin_lockA() This would be a deadlock. CPU0 would wait for the lock A. While CPU1 would own the lockA and would wait for CPU0 to finish calling the console drivers and pass the console_sem owner. But if the above is true than the following scenario was already possible before: CPU0 spin_lockA() printk() console_unlock() call_console_drivers() spin_lockA() By other words, this deadlock was there even before. Such deadlocks are prevented by using printk_deferred() in the sections guarded by the lock A. By Steven Rostedt: To demonstrate the issue, this module has been shown to lock up a system with 4 CPUs and a slow console (like a serial console). It is also able to lock up a 8 CPU system with only a fast (VGA) console, by passing in "loops=100". The changes in this commit prevent this module from locking up the system. #include #include #include #include #include #include static bool stop_testing; static unsigned int loops = 1; static void preempt_printk_workfn(struct work_struct *work) { int i; while (!READ_ONCE(stop_testing)) { for (i = 0; i < loops && !READ_ONCE(stop_testing); i++) { preempt_disable(); pr_emerg("%5d%-75s\n", smp_processor_id(), " XXX NOPREEMPT"); preempt_enable(); } msleep(1); } } static struct work_struct __percpu *works; static void finish(void) { int cpu; WRITE_ONCE(stop_testing, true); for_each_online_cpu(cpu) flush_work(per_cpu_ptr(works, cpu)); free_percpu(works); } static int __init test_init(void) { int cpu; works = alloc_percpu(struct work_struct); if (!works) return -ENOMEM; /* * This is just a test module. This will break if you * do any CPU hot plugging between loading and * unloading the module. */ for_each_online_cpu(cpu) { struct work_struct *work = per_cpu_ptr(works, cpu); INIT_WORK(work, &preempt_printk_workfn); schedule_work_on(cpu, work); } return 0; } static void __exit test_exit(void) { finish(); } module_param(loops, uint, 0); module_init(test_init); module_exit(test_exit); MODULE_LICENSE("GPL"); Link: http://lkml.kernel.org/r/20180110132418.7080-2-pmladek@suse.com Cc: akpm@linux-foundation.org Cc: linux-mm@kvack.org Cc: Cong Wang Cc: Dave Hansen Cc: Johannes Weiner Cc: Mel Gorman Cc: Michal Hocko Cc: Vlastimil Babka Cc: Peter Zijlstra Cc: Linus Torvalds Cc: Jan Kara Cc: Mathieu Desnoyers Cc: Tetsuo Handa Cc: Byungchul Park Cc: Tejun Heo Cc: Pavel Machek Cc: linux-kernel@vger.kernel.org Signed-off-by: Steven Rostedt (VMware) [pmladek@suse.com: Commit message about possible deadlocks] Acked-by: Sergey Senozhatsky Signed-off-by: Petr Mladek Signed-off-by: Sasha Levin --- kernel/printk/printk.c | 108 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 107 insertions(+), 1 deletion(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 7161312593dd..b88b402444d6 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -86,8 +86,15 @@ EXPORT_SYMBOL_GPL(console_drivers); static struct lockdep_map console_lock_dep_map = { .name = "console_lock" }; +static struct lockdep_map console_owner_dep_map = { + .name = "console_owner" +}; #endif +static DEFINE_RAW_SPINLOCK(console_owner_lock); +static struct task_struct *console_owner; +static bool console_waiter; + enum devkmsg_log_bits { __DEVKMSG_LOG_BIT_ON = 0, __DEVKMSG_LOG_BIT_OFF, @@ -1767,8 +1774,56 @@ asmlinkage int vprintk_emit(int facility, int level, * semaphore. The release will print out buffers and wake up * /dev/kmsg and syslog() users. */ - if (console_trylock()) + if (console_trylock()) { console_unlock(); + } else { + struct task_struct *owner = NULL; + bool waiter; + bool spin = false; + + printk_safe_enter_irqsave(flags); + + raw_spin_lock(&console_owner_lock); + owner = READ_ONCE(console_owner); + waiter = READ_ONCE(console_waiter); + if (!waiter && owner && owner != current) { + WRITE_ONCE(console_waiter, true); + spin = true; + } + raw_spin_unlock(&console_owner_lock); + + /* + * If there is an active printk() writing to the + * consoles, instead of having it write our data too, + * see if we can offload that load from the active + * printer, and do some printing ourselves. + * Go into a spin only if there isn't already a waiter + * spinning, and there is an active printer, and + * that active printer isn't us (recursive printk?). + */ + if (spin) { + /* We spin waiting for the owner to release us */ + spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); + /* Owner will clear console_waiter on hand off */ + while (READ_ONCE(console_waiter)) + cpu_relax(); + + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + printk_safe_exit_irqrestore(flags); + + /* + * The owner passed the console lock to us. + * Since we did not spin on console lock, annotate + * this as a trylock. Otherwise lockdep will + * complain. + */ + mutex_acquire(&console_lock_dep_map, 0, 1, _THIS_IP_); + console_unlock(); + printk_safe_enter_irqsave(flags); + } + printk_safe_exit_irqrestore(flags); + + } } return printed_len; @@ -2155,6 +2210,7 @@ void console_unlock(void) static u64 seen_seq; unsigned long flags; bool wake_klogd = false; + bool waiter = false; bool do_cond_resched, retry; if (console_suspended) { @@ -2243,14 +2299,64 @@ void console_unlock(void) console_seq++; raw_spin_unlock(&logbuf_lock); + /* + * While actively printing out messages, if another printk() + * were to occur on another CPU, it may wait for this one to + * finish. This task can not be preempted if there is a + * waiter waiting to take over. + */ + raw_spin_lock(&console_owner_lock); + console_owner = current; + raw_spin_unlock(&console_owner_lock); + + /* The waiter may spin on us after setting console_owner */ + spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); + stop_critical_timings(); /* don't trace print latency */ call_console_drivers(ext_text, ext_len, text, len); start_critical_timings(); + + raw_spin_lock(&console_owner_lock); + waiter = READ_ONCE(console_waiter); + console_owner = NULL; + raw_spin_unlock(&console_owner_lock); + + /* + * If there is a waiter waiting for us, then pass the + * rest of the work load over to that waiter. + */ + if (waiter) + break; + + /* There was no waiter, and nothing will spin on us here */ + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + printk_safe_exit_irqrestore(flags); if (do_cond_resched) cond_resched(); } + + /* + * If there is an active waiter waiting on the console_lock. + * Pass off the printing to the waiter, and the waiter + * will continue printing on its CPU, and when all writing + * has finished, the last printer will wake up klogd. + */ + if (waiter) { + WRITE_ONCE(console_waiter, false); + /* The waiter is now free to continue */ + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + /* + * Hand off console_lock to waiter. The waiter will perform + * the up(). After this, the waiter is the console_lock owner. + */ + mutex_release(&console_lock_dep_map, 1, _THIS_IP_); + printk_safe_exit_irqrestore(flags); + /* Note, if waiter is set, logbuf_lock is not held */ + return; + } + console_locked = 0; /* Release the exclusive_console once it is used */ -- GitLab From ef433725f5f054e44c11d40f2d80f35824351697 Mon Sep 17 00:00:00 2001 From: Petr Mladek Date: Fri, 12 Jan 2018 17:08:37 +0100 Subject: [PATCH 0527/1286] printk: Hide console waiter logic into helpers [ Upstream commit c162d5b4338d72deed61aa65ed0f2f4ba2bbc8ab ] The commit ("printk: Add console owner and waiter logic to load balance console writes") made vprintk_emit() and console_unlock() even more complicated. This patch extracts the new code into 3 helper functions. They should help to keep it rather self-contained. It will be easier to use and maintain. This patch just shuffles the existing code. It does not change the functionality. Link: http://lkml.kernel.org/r/20180112160837.GD24497@linux.suse Cc: akpm@linux-foundation.org Cc: linux-mm@kvack.org Cc: Cong Wang Cc: Dave Hansen Cc: Johannes Weiner Cc: Mel Gorman Cc: Michal Hocko Cc: Vlastimil Babka Cc: Peter Zijlstra Cc: Linus Torvalds Cc: Jan Kara Cc: Mathieu Desnoyers Cc: Tetsuo Handa Cc: rostedt@home.goodmis.org Cc: Byungchul Park Cc: Tejun Heo Cc: Pavel Machek Cc: linux-kernel@vger.kernel.org Reviewed-by: Steven Rostedt (VMware) Acked-by: Sergey Senozhatsky Signed-off-by: Petr Mladek Signed-off-by: Sasha Levin --- kernel/printk/printk.c | 245 +++++++++++++++++++++++++---------------- 1 file changed, 148 insertions(+), 97 deletions(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index b88b402444d6..2d1c2700bd85 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -86,15 +86,8 @@ EXPORT_SYMBOL_GPL(console_drivers); static struct lockdep_map console_lock_dep_map = { .name = "console_lock" }; -static struct lockdep_map console_owner_dep_map = { - .name = "console_owner" -}; #endif -static DEFINE_RAW_SPINLOCK(console_owner_lock); -static struct task_struct *console_owner; -static bool console_waiter; - enum devkmsg_log_bits { __DEVKMSG_LOG_BIT_ON = 0, __DEVKMSG_LOG_BIT_OFF, @@ -1555,6 +1548,146 @@ SYSCALL_DEFINE3(syslog, int, type, char __user *, buf, int, len) return do_syslog(type, buf, len, SYSLOG_FROM_READER); } +/* + * Special console_lock variants that help to reduce the risk of soft-lockups. + * They allow to pass console_lock to another printk() call using a busy wait. + */ + +#ifdef CONFIG_LOCKDEP +static struct lockdep_map console_owner_dep_map = { + .name = "console_owner" +}; +#endif + +static DEFINE_RAW_SPINLOCK(console_owner_lock); +static struct task_struct *console_owner; +static bool console_waiter; + +/** + * console_lock_spinning_enable - mark beginning of code where another + * thread might safely busy wait + * + * This basically converts console_lock into a spinlock. This marks + * the section where the console_lock owner can not sleep, because + * there may be a waiter spinning (like a spinlock). Also it must be + * ready to hand over the lock at the end of the section. + */ +static void console_lock_spinning_enable(void) +{ + raw_spin_lock(&console_owner_lock); + console_owner = current; + raw_spin_unlock(&console_owner_lock); + + /* The waiter may spin on us after setting console_owner */ + spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); +} + +/** + * console_lock_spinning_disable_and_check - mark end of code where another + * thread was able to busy wait and check if there is a waiter + * + * This is called at the end of the section where spinning is allowed. + * It has two functions. First, it is a signal that it is no longer + * safe to start busy waiting for the lock. Second, it checks if + * there is a busy waiter and passes the lock rights to her. + * + * Important: Callers lose the lock if there was a busy waiter. + * They must not touch items synchronized by console_lock + * in this case. + * + * Return: 1 if the lock rights were passed, 0 otherwise. + */ +static int console_lock_spinning_disable_and_check(void) +{ + int waiter; + + raw_spin_lock(&console_owner_lock); + waiter = READ_ONCE(console_waiter); + console_owner = NULL; + raw_spin_unlock(&console_owner_lock); + + if (!waiter) { + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + return 0; + } + + /* The waiter is now free to continue */ + WRITE_ONCE(console_waiter, false); + + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + + /* + * Hand off console_lock to waiter. The waiter will perform + * the up(). After this, the waiter is the console_lock owner. + */ + mutex_release(&console_lock_dep_map, 1, _THIS_IP_); + return 1; +} + +/** + * console_trylock_spinning - try to get console_lock by busy waiting + * + * This allows to busy wait for the console_lock when the current + * owner is running in specially marked sections. It means that + * the current owner is running and cannot reschedule until it + * is ready to lose the lock. + * + * Return: 1 if we got the lock, 0 othrewise + */ +static int console_trylock_spinning(void) +{ + struct task_struct *owner = NULL; + bool waiter; + bool spin = false; + unsigned long flags; + + if (console_trylock()) + return 1; + + printk_safe_enter_irqsave(flags); + + raw_spin_lock(&console_owner_lock); + owner = READ_ONCE(console_owner); + waiter = READ_ONCE(console_waiter); + if (!waiter && owner && owner != current) { + WRITE_ONCE(console_waiter, true); + spin = true; + } + raw_spin_unlock(&console_owner_lock); + + /* + * If there is an active printk() writing to the + * consoles, instead of having it write our data too, + * see if we can offload that load from the active + * printer, and do some printing ourselves. + * Go into a spin only if there isn't already a waiter + * spinning, and there is an active printer, and + * that active printer isn't us (recursive printk?). + */ + if (!spin) { + printk_safe_exit_irqrestore(flags); + return 0; + } + + /* We spin waiting for the owner to release us */ + spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); + /* Owner will clear console_waiter on hand off */ + while (READ_ONCE(console_waiter)) + cpu_relax(); + spin_release(&console_owner_dep_map, 1, _THIS_IP_); + + printk_safe_exit_irqrestore(flags); + /* + * The owner passed the console lock to us. + * Since we did not spin on console lock, annotate + * this as a trylock. Otherwise lockdep will + * complain. + */ + mutex_acquire(&console_lock_dep_map, 0, 1, _THIS_IP_); + + return 1; +} + /* * Call the console drivers, asking them to write out * log_buf[start] to log_buf[end - 1]. @@ -1774,56 +1907,8 @@ asmlinkage int vprintk_emit(int facility, int level, * semaphore. The release will print out buffers and wake up * /dev/kmsg and syslog() users. */ - if (console_trylock()) { + if (console_trylock_spinning()) console_unlock(); - } else { - struct task_struct *owner = NULL; - bool waiter; - bool spin = false; - - printk_safe_enter_irqsave(flags); - - raw_spin_lock(&console_owner_lock); - owner = READ_ONCE(console_owner); - waiter = READ_ONCE(console_waiter); - if (!waiter && owner && owner != current) { - WRITE_ONCE(console_waiter, true); - spin = true; - } - raw_spin_unlock(&console_owner_lock); - - /* - * If there is an active printk() writing to the - * consoles, instead of having it write our data too, - * see if we can offload that load from the active - * printer, and do some printing ourselves. - * Go into a spin only if there isn't already a waiter - * spinning, and there is an active printer, and - * that active printer isn't us (recursive printk?). - */ - if (spin) { - /* We spin waiting for the owner to release us */ - spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); - /* Owner will clear console_waiter on hand off */ - while (READ_ONCE(console_waiter)) - cpu_relax(); - - spin_release(&console_owner_dep_map, 1, _THIS_IP_); - printk_safe_exit_irqrestore(flags); - - /* - * The owner passed the console lock to us. - * Since we did not spin on console lock, annotate - * this as a trylock. Otherwise lockdep will - * complain. - */ - mutex_acquire(&console_lock_dep_map, 0, 1, _THIS_IP_); - console_unlock(); - printk_safe_enter_irqsave(flags); - } - printk_safe_exit_irqrestore(flags); - - } } return printed_len; @@ -1924,6 +2009,8 @@ static ssize_t msg_print_ext_header(char *buf, size_t size, static ssize_t msg_print_ext_body(char *buf, size_t size, char *dict, size_t dict_len, char *text, size_t text_len) { return 0; } +static void console_lock_spinning_enable(void) { } +static int console_lock_spinning_disable_and_check(void) { return 0; } static void call_console_drivers(const char *ext_text, size_t ext_len, const char *text, size_t len) {} static size_t msg_print_text(const struct printk_log *msg, @@ -2210,7 +2297,6 @@ void console_unlock(void) static u64 seen_seq; unsigned long flags; bool wake_klogd = false; - bool waiter = false; bool do_cond_resched, retry; if (console_suspended) { @@ -2305,31 +2391,16 @@ void console_unlock(void) * finish. This task can not be preempted if there is a * waiter waiting to take over. */ - raw_spin_lock(&console_owner_lock); - console_owner = current; - raw_spin_unlock(&console_owner_lock); - - /* The waiter may spin on us after setting console_owner */ - spin_acquire(&console_owner_dep_map, 0, 0, _THIS_IP_); + console_lock_spinning_enable(); stop_critical_timings(); /* don't trace print latency */ call_console_drivers(ext_text, ext_len, text, len); start_critical_timings(); - raw_spin_lock(&console_owner_lock); - waiter = READ_ONCE(console_waiter); - console_owner = NULL; - raw_spin_unlock(&console_owner_lock); - - /* - * If there is a waiter waiting for us, then pass the - * rest of the work load over to that waiter. - */ - if (waiter) - break; - - /* There was no waiter, and nothing will spin on us here */ - spin_release(&console_owner_dep_map, 1, _THIS_IP_); + if (console_lock_spinning_disable_and_check()) { + printk_safe_exit_irqrestore(flags); + return; + } printk_safe_exit_irqrestore(flags); @@ -2337,26 +2408,6 @@ void console_unlock(void) cond_resched(); } - /* - * If there is an active waiter waiting on the console_lock. - * Pass off the printing to the waiter, and the waiter - * will continue printing on its CPU, and when all writing - * has finished, the last printer will wake up klogd. - */ - if (waiter) { - WRITE_ONCE(console_waiter, false); - /* The waiter is now free to continue */ - spin_release(&console_owner_dep_map, 1, _THIS_IP_); - /* - * Hand off console_lock to waiter. The waiter will perform - * the up(). After this, the waiter is the console_lock owner. - */ - mutex_release(&console_lock_dep_map, 1, _THIS_IP_); - printk_safe_exit_irqrestore(flags); - /* Note, if waiter is set, logbuf_lock is not held */ - return; - } - console_locked = 0; /* Release the exclusive_console once it is used */ -- GitLab From 08b7a8f880a27631e25e23ac2569f7c2d166469e Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Tue, 16 Jan 2018 13:47:16 +0900 Subject: [PATCH 0528/1286] printk: Never set console_may_schedule in console_trylock() [ Upstream commit fd5f7cde1b85d4c8e09ca46ce948e008a2377f64 ] This patch, basically, reverts commit 6b97a20d3a79 ("printk: set may_schedule for some of console_trylock() callers"). That commit was a mistake, it introduced a big dependency on the scheduler, by enabling preemption under console_sem in printk()->console_unlock() path, which is rather too critical. The patch did not significantly reduce the possibilities of printk() lockups, but made it possible to stall printk(), as has been reported by Tetsuo Handa [1]. Another issues is that preemption under console_sem also messes up with Steven Rostedt's hand off scheme, by making it possible to sleep with console_sem both in console_unlock() and in vprintk_emit(), after acquiring the console_sem ownership (anywhere between printk_safe_exit_irqrestore() in console_trylock_spinning() and printk_safe_enter_irqsave() in console_unlock()). This makes hand off less likely and, at the same time, may result in a significant amount of pending logbuf messages. Preempted console_sem owner makes it impossible for other CPUs to emit logbuf messages, but does not make it impossible for other CPUs to append new messages to the logbuf. Reinstate the old behavior and make printk() non-preemptible. Should any printk() lockup reports arrive they must be handled in a different way. [1] http://lkml.kernel.org/r/201603022101.CAH73907.OVOOMFHFFtQJSL%20()%20I-love%20!%20SAKURA%20!%20ne%20!%20jp Fixes: 6b97a20d3a79 ("printk: set may_schedule for some of console_trylock() callers") Link: http://lkml.kernel.org/r/20180116044716.GE6607@jagdpanzerIV To: Tetsuo Handa Cc: Sergey Senozhatsky Cc: Tejun Heo Cc: akpm@linux-foundation.org Cc: linux-mm@kvack.org Cc: Cong Wang Cc: Dave Hansen Cc: Johannes Weiner Cc: Mel Gorman Cc: Michal Hocko Cc: Vlastimil Babka Cc: Peter Zijlstra Cc: Linus Torvalds Cc: Jan Kara Cc: Mathieu Desnoyers Cc: Byungchul Park Cc: Pavel Machek Cc: linux-kernel@vger.kernel.org Signed-off-by: Sergey Senozhatsky Reported-by: Tetsuo Handa Reviewed-by: Steven Rostedt (VMware) Signed-off-by: Petr Mladek Signed-off-by: Sasha Levin --- kernel/printk/printk.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 2d1c2700bd85..2f654a79f80b 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -1902,6 +1902,12 @@ asmlinkage int vprintk_emit(int facility, int level, /* If called from the scheduler, we can not call up(). */ if (!in_sched) { + /* + * Disable preemption to avoid being preempted while holding + * console_sem which would prevent anyone from printing to + * console + */ + preempt_disable(); /* * Try to acquire and then immediately release the console * semaphore. The release will print out buffers and wake up @@ -1909,6 +1915,7 @@ asmlinkage int vprintk_emit(int facility, int level, */ if (console_trylock_spinning()) console_unlock(); + preempt_enable(); } return printed_len; @@ -2225,20 +2232,7 @@ int console_trylock(void) return 0; } console_locked = 1; - /* - * When PREEMPT_COUNT disabled we can't reliably detect if it's - * safe to schedule (e.g. calling printk while holding a spin_lock), - * because preempt_disable()/preempt_enable() are just barriers there - * and preempt_count() is always 0. - * - * RCU read sections have a separate preemption counter when - * PREEMPT_RCU enabled thus we must take extra care and check - * rcu_preempt_depth(), otherwise RCU read sections modify - * preempt_count(). - */ - console_may_schedule = !oops_in_progress && - preemptible() && - !rcu_preempt_depth(); + console_may_schedule = 0; return 1; } EXPORT_SYMBOL(console_trylock); -- GitLab From 16c9a316f21f1bcde5ce0633848d61699d63bad3 Mon Sep 17 00:00:00 2001 From: Petr Mladek Date: Mon, 26 Feb 2018 15:44:20 +0100 Subject: [PATCH 0529/1286] printk: Wake klogd when passing console_lock owner [ Upstream commit c14376de3a1befa70d9811ca2872d47367b48767 ] wake_klogd is a local variable in console_unlock(). The information is lost when the console_lock owner using the busy wait added by the commit dbdda842fe96f8932 ("printk: Add console owner and waiter logic to load balance console writes"). The following race is possible: CPU0 CPU1 console_unlock() for (;;) /* calling console for last message */ printk() log_store() log_next_seq++; /* see new message */ if (seen_seq != log_next_seq) { wake_klogd = true; seen_seq = log_next_seq; } console_lock_spinning_enable(); if (console_trylock_spinning()) /* spinning */ if (console_lock_spinning_disable_and_check()) { printk_safe_exit_irqrestore(flags); return; console_unlock() if (seen_seq != log_next_seq) { /* already seen */ /* nothing to do */ Result: Nobody would wakeup klogd. One solution would be to make a global variable from wake_klogd. But then we would need to manipulate it under a lock or so. This patch wakes klogd also when console_lock is passed to the spinning waiter. It looks like the right way to go. Also userspace should have a chance to see and store any "flood" of messages. Note that the very late klogd wake up was a historic solution. It made sense on single CPU systems or when sys_syslog() operations were synchronized using the big kernel lock like in v2.1.113. But it is questionable these days. Fixes: dbdda842fe96f8932 ("printk: Add console owner and waiter logic to load balance console writes") Link: http://lkml.kernel.org/r/20180226155734.dzwg3aovqnwtvkoy@pathway.suse.cz Cc: Steven Rostedt Cc: linux-kernel@vger.kernel.org Cc: Tejun Heo Suggested-by: Sergey Senozhatsky Reviewed-by: Sergey Senozhatsky Signed-off-by: Petr Mladek Signed-off-by: Sasha Levin --- kernel/printk/printk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 2f654a79f80b..2e2c86dd226f 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -2393,7 +2393,7 @@ void console_unlock(void) if (console_lock_spinning_disable_and_check()) { printk_safe_exit_irqrestore(flags); - return; + goto out; } printk_safe_exit_irqrestore(flags); @@ -2426,6 +2426,7 @@ void console_unlock(void) if (retry && console_trylock()) goto again; +out: if (wake_klogd) wake_up_klogd(); } -- GitLab From 891e5a89f0faf42766eefd476285d4779fd31a21 Mon Sep 17 00:00:00 2001 From: Davidlohr Bueso Date: Fri, 17 Nov 2017 15:28:27 -0800 Subject: [PATCH 0530/1286] lib/rbtree-test: lower default params commit 0b548e33e6cb2bff240fdaf1783783be15c29080 upstream. Fengguang reported soft lockups while running the rbtree and interval tree test modules. The logic for these tests all occur in init phase, and we currently are pounding with the default values for number of nodes and number of iterations of each test. Reduce the latter by two orders of magnitude. This does not influence the value of the tests in that one thousand times by default is enough to get the picture. Link: http://lkml.kernel.org/r/20171109161715.xai2dtwqw2frhkcm@linux-n805 Signed-off-by: Davidlohr Bueso Reported-by: Fengguang Wu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Cc: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- lib/interval_tree_test.c | 4 ++-- lib/rbtree_test.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/interval_tree_test.c b/lib/interval_tree_test.c index 0e343fd29570..835242e74aaa 100644 --- a/lib/interval_tree_test.c +++ b/lib/interval_tree_test.c @@ -11,10 +11,10 @@ MODULE_PARM_DESC(name, msg); __param(int, nnodes, 100, "Number of nodes in the interval tree"); -__param(int, perf_loops, 100000, "Number of iterations modifying the tree"); +__param(int, perf_loops, 1000, "Number of iterations modifying the tree"); __param(int, nsearches, 100, "Number of searches to the interval tree"); -__param(int, search_loops, 10000, "Number of iterations searching the tree"); +__param(int, search_loops, 1000, "Number of iterations searching the tree"); __param(bool, search_all, false, "Searches will iterate all nodes in the tree"); __param(uint, max_endpoint, ~0, "Largest value for the interval's endpoint"); diff --git a/lib/rbtree_test.c b/lib/rbtree_test.c index 191a238e5a9d..7d36c1e27ff6 100644 --- a/lib/rbtree_test.c +++ b/lib/rbtree_test.c @@ -11,7 +11,7 @@ MODULE_PARM_DESC(name, msg); __param(int, nnodes, 100, "Number of nodes in the rb-tree"); -__param(int, perf_loops, 100000, "Number of iterations modifying the rb-tree"); +__param(int, perf_loops, 1000, "Number of iterations modifying the rb-tree"); __param(int, check_loops, 100, "Number of iterations modifying and verifying the rb-tree"); struct test_node { -- GitLab From 5d2cc520d1f1ed929ef1f6b7ad57ddde9c42b651 Mon Sep 17 00:00:00 2001 From: Tigran Mkrtchyan Date: Mon, 26 Nov 2018 18:35:14 +0100 Subject: [PATCH 0531/1286] flexfiles: enforce per-mirror stateid only for v4 DSes commit 320f35b7bf8cccf1997ca3126843535e1b95e9c4 upstream. Since commit bb21ce0ad227 we always enforce per-mirror stateid. However, this makes sense only for v4+ servers. Signed-off-by: Tigran Mkrtchyan Signed-off-by: Trond Myklebust Signed-off-by: Greg Kroah-Hartman --- fs/nfs/flexfilelayout/flexfilelayout.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c index 13612a848378..8dbde5ded042 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.c +++ b/fs/nfs/flexfilelayout/flexfilelayout.c @@ -1725,7 +1725,8 @@ ff_layout_read_pagelist(struct nfs_pgio_header *hdr) if (fh) hdr->args.fh = fh; - if (!nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) + if (vers == 4 && + !nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) goto out_failed; /* @@ -1790,7 +1791,8 @@ ff_layout_write_pagelist(struct nfs_pgio_header *hdr, int sync) if (fh) hdr->args.fh = fh; - if (!nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) + if (vers == 4 && + !nfs4_ff_layout_select_ds_stateid(lseg, idx, &hdr->args.stateid)) goto out_failed; /* -- GitLab From 16906e5ad4cc0439d03dc294c0251f4c875ccef2 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Sun, 1 Jul 2018 13:57:24 -0700 Subject: [PATCH 0532/1286] staging: speakup: Replace strncpy with memcpy commit fd29edc7232bc19f969e8f463138afc5472b3d5f upstream. gcc 8.1.0 generates the following warnings. drivers/staging/speakup/kobjects.c: In function 'punc_store': drivers/staging/speakup/kobjects.c:522:2: warning: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length drivers/staging/speakup/kobjects.c:504:6: note: length computed here drivers/staging/speakup/kobjects.c: In function 'synth_store': drivers/staging/speakup/kobjects.c:391:2: warning: 'strncpy' output truncated before terminating nul copying as many bytes from a string as its length drivers/staging/speakup/kobjects.c:388:8: note: length computed here Using strncpy() is indeed less than perfect since the length of data to be copied has already been determined with strlen(). Replace strncpy() with memcpy() to address the warning and optimize the code a little. Signed-off-by: Guenter Roeck Reviewed-by: Samuel Thibault Signed-off-by: Greg Kroah-Hartman --- drivers/staging/speakup/kobjects.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/speakup/kobjects.c b/drivers/staging/speakup/kobjects.c index ca85476e3ff7..23256bbdba51 100644 --- a/drivers/staging/speakup/kobjects.c +++ b/drivers/staging/speakup/kobjects.c @@ -387,7 +387,7 @@ static ssize_t synth_store(struct kobject *kobj, struct kobj_attribute *attr, len = strlen(buf); if (len < 2 || len > 9) return -EINVAL; - strncpy(new_synth_name, buf, len); + memcpy(new_synth_name, buf, len); if (new_synth_name[len - 1] == '\n') len--; new_synth_name[len] = '\0'; @@ -518,7 +518,7 @@ static ssize_t punc_store(struct kobject *kobj, struct kobj_attribute *attr, return -EINVAL; } - strncpy(punc_buf, buf, x); + memcpy(punc_buf, buf, x); while (x && punc_buf[x - 1] == '\n') x--; -- GitLab From 62711dc6898b3186a8a3501e4a3829add8624b3f Mon Sep 17 00:00:00 2001 From: Takashi Sakamoto Date: Sun, 9 Dec 2018 17:04:19 +0900 Subject: [PATCH 0533/1286] ALSA: fireface: fix reference to wrong register for clock configuration commit fa9c98e4b975bb3192ed6af09d9fa282ed3cd8a0 upstream. In an initial commit, 'SYNC_STATUS' register is referred to get clock configuration, however this is wrong, according to my local note at hand for reverse-engineering about packet dump. It should be 'CLOCK_CONFIG' register. Actually, ff400_dump_clock_config() is correctly programmed. This commit fixes the bug. Cc: # v4.12+ Fixes: 76fdb3a9e13a ('ALSA: fireface: add support for Fireface 400') Signed-off-by: Takashi Sakamoto Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/firewire/fireface/ff-protocol-ff400.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/firewire/fireface/ff-protocol-ff400.c b/sound/firewire/fireface/ff-protocol-ff400.c index 9f5036442ab9..b47954a6b8ab 100644 --- a/sound/firewire/fireface/ff-protocol-ff400.c +++ b/sound/firewire/fireface/ff-protocol-ff400.c @@ -30,7 +30,7 @@ static int ff400_get_clock(struct snd_ff *ff, unsigned int *rate, int err; err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST, - FF400_SYNC_STATUS, ®, sizeof(reg), 0); + FF400_CLOCK_CONFIG, ®, sizeof(reg), 0); if (err < 0) return err; data = le32_to_cpu(reg); -- GitLab From d655a1a6684e0d6cc2429caeb4c5dd0fed4efb79 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Fri, 7 Dec 2018 15:14:59 +0800 Subject: [PATCH 0534/1286] ALSA: hda/realtek - Fixed headphone issue for ALC700 commit bde1a7459623a66c2abec4d0a841e4b06cc88d9a upstream. If it plugged headphone or headset into the jack, then do the reboot, it will have a chance to cause headphone no sound. It just need to run the headphone mode procedure after boot time. The issue will be fixed. It also suitable for ALC234 ALC274 and ALC294. Signed-off-by: Kailang Yang Cc: Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index f6136f041a81..31c91e0a815e 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -6965,6 +6965,37 @@ static void alc269_fill_coef(struct hda_codec *codec) alc_update_coef_idx(codec, 0x4, 0, 1<<11); } +static void alc294_hp_init(struct hda_codec *codec) +{ + struct alc_spec *spec = codec->spec; + hda_nid_t hp_pin = spec->gen.autocfg.hp_pins[0]; + int i, val; + + if (!hp_pin) + return; + + snd_hda_codec_write(codec, hp_pin, 0, + AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE); + + msleep(100); + + snd_hda_codec_write(codec, hp_pin, 0, + AC_VERB_SET_PIN_WIDGET_CONTROL, 0x0); + + alc_update_coef_idx(codec, 0x6f, 0x000f, 0);/* Set HP depop to manual mode */ + alc_update_coefex_idx(codec, 0x58, 0x00, 0x8000, 0x8000); /* HP depop procedure start */ + + /* Wait for depop procedure finish */ + val = alc_read_coefex_idx(codec, 0x58, 0x01); + for (i = 0; i < 20 && val & 0x0080; i++) { + msleep(50); + val = alc_read_coefex_idx(codec, 0x58, 0x01); + } + /* Set HP depop to auto mode */ + alc_update_coef_idx(codec, 0x6f, 0x000f, 0x000b); + msleep(50); +} + /* */ static int patch_alc269(struct hda_codec *codec) @@ -7101,6 +7132,7 @@ static int patch_alc269(struct hda_codec *codec) spec->codec_variant = ALC269_TYPE_ALC294; spec->gen.mixer_nid = 0; /* ALC2x4 does not have any loopback mixer path */ alc_update_coef_idx(codec, 0x6b, 0x0018, (1<<4) | (1<<3)); /* UAJ MIC Vref control by verb */ + alc294_hp_init(codec); break; case 0x10ec0300: spec->codec_variant = ALC269_TYPE_ALC300; @@ -7112,6 +7144,7 @@ static int patch_alc269(struct hda_codec *codec) spec->codec_variant = ALC269_TYPE_ALC700; spec->gen.mixer_nid = 0; /* ALC700 does not have any loopback mixer path */ alc_update_coef_idx(codec, 0x4a, 1 << 15, 0); /* Combo jack auto trigger control */ + alc294_hp_init(codec); break; } -- GitLab From 01a166012cd16b9ce147744c514f228df6cf495e Mon Sep 17 00:00:00 2001 From: Piotr Stankiewicz Date: Wed, 28 Nov 2018 06:44:46 -0800 Subject: [PATCH 0535/1286] IB/hfi1: Fix an out-of-bounds access in get_hw_stats commit 36d842194a57f1b21fbc6a6875f2fa2f9a7f8679 upstream. When running with KASAN, the following trace is produced: [ 62.535888] ================================================================== [ 62.544930] BUG: KASAN: slab-out-of-bounds in gut_hw_stats+0x122/0x230 [hfi1] [ 62.553856] Write of size 8 at addr ffff88080e8d6330 by task kworker/0:1/14 [ 62.565333] CPU: 0 PID: 14 Comm: kworker/0:1 Not tainted 4.19.0-test-build-kasan+ #8 [ 62.575087] Hardware name: Intel Corporation S2600KPR/S2600KPR, BIOS SE5C610.86B.01.01.0019.101220160604 10/12/2016 [ 62.587951] Workqueue: events work_for_cpu_fn [ 62.594050] Call Trace: [ 62.598023] dump_stack+0xc6/0x14c [ 62.603089] ? dump_stack_print_info.cold.1+0x2f/0x2f [ 62.610041] ? kmsg_dump_rewind_nolock+0x59/0x59 [ 62.616615] ? get_hw_stats+0x122/0x230 [hfi1] [ 62.622985] print_address_description+0x6c/0x23c [ 62.629744] ? get_hw_stats+0x122/0x230 [hfi1] [ 62.636108] kasan_report.cold.6+0x241/0x308 [ 62.642365] get_hw_stats+0x122/0x230 [hfi1] [ 62.648703] ? hfi1_alloc_rn+0x40/0x40 [hfi1] [ 62.655088] ? __kmalloc+0x110/0x240 [ 62.660695] ? hfi1_alloc_rn+0x40/0x40 [hfi1] [ 62.667142] setup_hw_stats+0xd8/0x430 [ib_core] [ 62.673972] ? show_hfi+0x50/0x50 [hfi1] [ 62.680026] ib_device_register_sysfs+0x165/0x180 [ib_core] [ 62.687995] ib_register_device+0x5a2/0xa10 [ib_core] [ 62.695340] ? show_hfi+0x50/0x50 [hfi1] [ 62.701421] ? ib_unregister_device+0x2e0/0x2e0 [ib_core] [ 62.709222] ? __vmalloc_node_range+0x2d0/0x380 [ 62.716131] ? rvt_driver_mr_init+0x11f/0x2d0 [rdmavt] [ 62.723735] ? vmalloc_node+0x5c/0x70 [ 62.729697] ? rvt_driver_mr_init+0x11f/0x2d0 [rdmavt] [ 62.737347] ? rvt_driver_mr_init+0x1f5/0x2d0 [rdmavt] [ 62.744998] ? __rvt_alloc_mr+0x110/0x110 [rdmavt] [ 62.752315] ? rvt_rc_error+0x140/0x140 [rdmavt] [ 62.759434] ? rvt_vma_open+0x30/0x30 [rdmavt] [ 62.766364] ? mutex_unlock+0x1d/0x40 [ 62.772445] ? kmem_cache_create_usercopy+0x15d/0x230 [ 62.780115] rvt_register_device+0x1f6/0x360 [rdmavt] [ 62.787823] ? rvt_get_port_immutable+0x180/0x180 [rdmavt] [ 62.796058] ? __get_txreq+0x400/0x400 [hfi1] [ 62.802969] ? memcpy+0x34/0x50 [ 62.808611] hfi1_register_ib_device+0xde6/0xeb0 [hfi1] [ 62.816601] ? hfi1_get_npkeys+0x10/0x10 [hfi1] [ 62.823760] ? hfi1_init+0x89f/0x9a0 [hfi1] [ 62.830469] ? hfi1_setup_eagerbufs+0xad0/0xad0 [hfi1] [ 62.838204] ? pcie_capability_clear_and_set_word+0xcd/0xe0 [ 62.846429] ? pcie_capability_read_word+0xd0/0xd0 [ 62.853791] ? hfi1_pcie_init+0x187/0x4b0 [hfi1] [ 62.860958] init_one+0x67f/0xae0 [hfi1] [ 62.867301] ? hfi1_init+0x9a0/0x9a0 [hfi1] [ 62.873876] ? wait_woken+0x130/0x130 [ 62.879860] ? read_word_at_a_time+0xe/0x20 [ 62.886329] ? strscpy+0x14b/0x280 [ 62.891998] ? hfi1_init+0x9a0/0x9a0 [hfi1] [ 62.898405] local_pci_probe+0x70/0xd0 [ 62.904295] ? pci_device_shutdown+0x90/0x90 [ 62.910833] work_for_cpu_fn+0x29/0x40 [ 62.916750] process_one_work+0x584/0x960 [ 62.922974] ? rcu_work_rcufn+0x40/0x40 [ 62.928991] ? __schedule+0x396/0xdc0 [ 62.934806] ? __sched_text_start+0x8/0x8 [ 62.941020] ? pick_next_task_fair+0x68b/0xc60 [ 62.947674] ? run_rebalance_domains+0x260/0x260 [ 62.954471] ? __list_add_valid+0x29/0xa0 [ 62.960607] ? move_linked_works+0x1c7/0x230 [ 62.967077] ? trace_event_raw_event_workqueue_execute_start+0x140/0x140 [ 62.976248] ? mutex_lock+0xa6/0x100 [ 62.982029] ? __mutex_lock_slowpath+0x10/0x10 [ 62.988795] ? __switch_to+0x37a/0x710 [ 62.994731] worker_thread+0x62e/0x9d0 [ 63.000602] ? max_active_store+0xf0/0xf0 [ 63.006828] ? __switch_to_asm+0x40/0x70 [ 63.012932] ? __switch_to_asm+0x34/0x70 [ 63.019013] ? __switch_to_asm+0x40/0x70 [ 63.025042] ? __switch_to_asm+0x34/0x70 [ 63.031030] ? __switch_to_asm+0x40/0x70 [ 63.037006] ? __schedule+0x396/0xdc0 [ 63.042660] ? kmem_cache_alloc_trace+0xf3/0x1f0 [ 63.049323] ? kthread+0x59/0x1d0 [ 63.054594] ? ret_from_fork+0x35/0x40 [ 63.060257] ? __sched_text_start+0x8/0x8 [ 63.066212] ? schedule+0xcf/0x250 [ 63.071529] ? __wake_up_common+0x110/0x350 [ 63.077794] ? __schedule+0xdc0/0xdc0 [ 63.083348] ? wait_woken+0x130/0x130 [ 63.088963] ? finish_task_switch+0x1f1/0x520 [ 63.095258] ? kasan_unpoison_shadow+0x30/0x40 [ 63.101792] ? __init_waitqueue_head+0xa0/0xd0 [ 63.108183] ? replenish_dl_entity.cold.60+0x18/0x18 [ 63.115151] ? _raw_spin_lock_irqsave+0x25/0x50 [ 63.121754] ? max_active_store+0xf0/0xf0 [ 63.127753] kthread+0x1ae/0x1d0 [ 63.132894] ? kthread_bind+0x30/0x30 [ 63.138422] ret_from_fork+0x35/0x40 [ 63.146973] Allocated by task 14: [ 63.152077] kasan_kmalloc+0xbf/0xe0 [ 63.157471] __kmalloc+0x110/0x240 [ 63.162804] init_cntrs+0x34d/0xdf0 [hfi1] [ 63.168883] hfi1_init_dd+0x29a3/0x2f90 [hfi1] [ 63.175244] init_one+0x551/0xae0 [hfi1] [ 63.181065] local_pci_probe+0x70/0xd0 [ 63.186759] work_for_cpu_fn+0x29/0x40 [ 63.192310] process_one_work+0x584/0x960 [ 63.198163] worker_thread+0x62e/0x9d0 [ 63.203843] kthread+0x1ae/0x1d0 [ 63.208874] ret_from_fork+0x35/0x40 [ 63.217203] Freed by task 1: [ 63.221844] __kasan_slab_free+0x12e/0x180 [ 63.227844] kfree+0x92/0x1a0 [ 63.232570] single_release+0x3a/0x60 [ 63.238024] __fput+0x1d9/0x480 [ 63.242911] task_work_run+0x139/0x190 [ 63.248440] exit_to_usermode_loop+0x191/0x1a0 [ 63.254814] do_syscall_64+0x301/0x330 [ 63.260283] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 63.270199] The buggy address belongs to the object at ffff88080e8d5500 which belongs to the cache kmalloc-4096 of size 4096 [ 63.287247] The buggy address is located 3632 bytes inside of 4096-byte region [ffff88080e8d5500, ffff88080e8d6500) [ 63.303564] The buggy address belongs to the page: [ 63.310447] page:ffffea00203a3400 count:1 mapcount:0 mapping:ffff88081380e840 index:0x0 compound_mapcount: 0 [ 63.323102] flags: 0x2fffff80008100(slab|head) [ 63.329775] raw: 002fffff80008100 0000000000000000 0000000100000001 ffff88081380e840 [ 63.340175] raw: 0000000000000000 0000000000070007 00000001ffffffff 0000000000000000 [ 63.350564] page dumped because: kasan: bad access detected [ 63.361974] Memory state around the buggy address: [ 63.369137] ffff88080e8d6200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 63.379082] ffff88080e8d6280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 63.389032] >ffff88080e8d6300: 00 00 00 00 00 00 fc fc fc fc fc fc fc fc fc fc [ 63.398944] ^ [ 63.406141] ffff88080e8d6380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 63.416109] ffff88080e8d6400: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 63.426099] ================================================================== The trace happens because get_hw_stats() assumes there is room in the memory allocated in init_cntrs() to accommodate the driver counters. Unfortunately, that routine only allocated space for the device counters. Fix by insuring the allocation has room for the additional driver counters. Cc: # v4.14+ Fixes: b7481944b06e9 ("IB/hfi1: Show statistics counters under IB stats interface") Reviewed-by: Mike Marciniczyn Reviewed-by: Mike Ruhl Signed-off-by: Piotr Stankiewicz Signed-off-by: Dennis Dalessandro Signed-off-by: Doug Ledford Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/hfi1/chip.c | 3 ++- drivers/infiniband/hw/hfi1/hfi.h | 2 ++ drivers/infiniband/hw/hfi1/verbs.c | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c index f9faacce9250..db33ad985a12 100644 --- a/drivers/infiniband/hw/hfi1/chip.c +++ b/drivers/infiniband/hw/hfi1/chip.c @@ -12449,7 +12449,8 @@ static int init_cntrs(struct hfi1_devdata *dd) } /* allocate space for the counter values */ - dd->cntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL); + dd->cntrs = kcalloc(dd->ndevcntrs + num_driver_cntrs, sizeof(u64), + GFP_KERNEL); if (!dd->cntrs) goto bail; diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h index 13a7bcaa58e6..ee2859dcceab 100644 --- a/drivers/infiniband/hw/hfi1/hfi.h +++ b/drivers/infiniband/hw/hfi1/hfi.h @@ -152,6 +152,8 @@ struct hfi1_ib_stats { extern struct hfi1_ib_stats hfi1_stats; extern const struct pci_error_handlers hfi1_pci_err_handler; +extern int num_driver_cntrs; + /* * First-cut criterion for "device is active" is * two thousand dwords combined Tx, Rx traffic per diff --git a/drivers/infiniband/hw/hfi1/verbs.c b/drivers/infiniband/hw/hfi1/verbs.c index 63d404a6752a..12cf0f7ca7bb 100644 --- a/drivers/infiniband/hw/hfi1/verbs.c +++ b/drivers/infiniband/hw/hfi1/verbs.c @@ -1693,7 +1693,7 @@ static const char * const driver_cntr_names[] = { static DEFINE_MUTEX(cntr_names_lock); /* protects the *_cntr_names bufers */ static const char **dev_cntr_names; static const char **port_cntr_names; -static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names); +int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names); static int num_dev_cntrs; static int num_port_cntrs; static int cntr_names_initialized; -- GitLab From 4465b31b75490c038777cfccfbdf2ba8e9e5286a Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 6 Dec 2018 09:58:24 -0800 Subject: [PATCH 0536/1286] tcp: lack of available data can also cause TSO defer commit f9bfe4e6a9d08d405fe7b081ee9a13e649c97ecf upstream. tcp_tso_should_defer() can return true in three different cases : 1) We are cwnd-limited 2) We are rwnd-limited 3) We are application limited. Neal pointed out that my recent fix went too far, since it assumed that if we were not in 1) case, we must be rwnd-limited Fix this by properly populating the is_cwnd_limited and is_rwnd_limited booleans. After this change, we can finally move the silly check for FIN flag only for the application-limited case. The same move for EOR bit will be handled in net-next, since commit 1c09f7d073b1 ("tcp: do not try to defer skbs with eor mark (MSG_EOR)") is scheduled for linux-4.21 Tested by running 200 concurrent netperf -t TCP_RR -- -r 60000,100 and checking none of them was rwnd_limited in the chrono_stat output from "ss -ti" command. Fixes: 41727549de3e ("tcp: Do not underestimate rwnd_limited") Signed-off-by: Eric Dumazet Suggested-by: Neal Cardwell Reviewed-by: Neal Cardwell Acked-by: Soheil Hassas Yeganeh Reviewed-by: Yuchung Cheng Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp_output.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 1b31b0a1c7fa..24bad638c2ec 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -1885,7 +1885,9 @@ static int tso_fragment(struct sock *sk, struct sk_buff *skb, unsigned int len, * This algorithm is from John Heffner. */ static bool tcp_tso_should_defer(struct sock *sk, struct sk_buff *skb, - bool *is_cwnd_limited, u32 max_segs) + bool *is_cwnd_limited, + bool *is_rwnd_limited, + u32 max_segs) { const struct inet_connection_sock *icsk = inet_csk(sk); u32 age, send_win, cong_win, limit, in_flight; @@ -1893,9 +1895,6 @@ static bool tcp_tso_should_defer(struct sock *sk, struct sk_buff *skb, struct sk_buff *head; int win_divisor; - if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) - goto send_now; - if (icsk->icsk_ca_state >= TCP_CA_Recovery) goto send_now; @@ -1951,10 +1950,27 @@ static bool tcp_tso_should_defer(struct sock *sk, struct sk_buff *skb, if (age < (tp->srtt_us >> 4)) goto send_now; - /* Ok, it looks like it is advisable to defer. */ + /* Ok, it looks like it is advisable to defer. + * Three cases are tracked : + * 1) We are cwnd-limited + * 2) We are rwnd-limited + * 3) We are application limited. + */ + if (cong_win < send_win) { + if (cong_win <= skb->len) { + *is_cwnd_limited = true; + return true; + } + } else { + if (send_win <= skb->len) { + *is_rwnd_limited = true; + return true; + } + } - if (cong_win < send_win && cong_win <= skb->len) - *is_cwnd_limited = true; + /* If this packet won't get more data, do not wait. */ + if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) + goto send_now; return true; @@ -2328,11 +2344,8 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle, } else { if (!push_one && tcp_tso_should_defer(sk, skb, &is_cwnd_limited, - max_segs)) { - if (!is_cwnd_limited) - is_rwnd_limited = true; + &is_rwnd_limited, max_segs)) break; - } } limit = mss_now; -- GitLab From 3beeb2615681fe87f4e6291ade669d50c27ce59a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 17 Dec 2018 09:28:56 +0100 Subject: [PATCH 0537/1286] Linux 4.14.89 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3fdee40861a1..b83477be8d0c 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 88 +SUBLEVEL = 89 EXTRAVERSION = NAME = Petit Gorille -- GitLab From de86a908fe4cf683d870c93915a0455670f45e15 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Mon, 3 Dec 2018 00:46:34 +0530 Subject: [PATCH 0538/1286] msm: vidc: Ensure validity of shared Q indices Video driver and firmware communicates over shared queue. The queue header has the indices which synchronizes the read and write between the driver and firmware modules. This change ensures that the indices are within the valid range before accessing them. CRs-fixed: 2345481 Change-Id: I8da6bb4218a5b8ec0e2e2c7b87f6cc9eec21bd16 Signed-off-by: Vikash Garodia --- drivers/media/platform/msm/vidc/venus_hfi.c | 66 ++++++++++++++------- 1 file changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c index cc2a406ba380..4c2f883e9986 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.c +++ b/drivers/media/platform/msm/vidc/venus_hfi.c @@ -567,7 +567,7 @@ static int __write_queue(struct vidc_iface_q_info *qinfo, u8 *packet, { struct hfi_queue_header *queue; u32 packet_size_in_words, new_write_idx; - u32 empty_space, read_idx; + u32 empty_space, read_idx, write_idx; u32 *write_ptr; if (!qinfo || !packet) { @@ -590,16 +590,18 @@ static int __write_queue(struct vidc_iface_q_info *qinfo, u8 *packet, } packet_size_in_words = (*(u32 *)packet) >> 2; - if (!packet_size_in_words) { - dprintk(VIDC_ERR, "Zero packet size\n"); + if (!packet_size_in_words || packet_size_in_words > + qinfo->q_array.mem_size>>2) { + dprintk(VIDC_ERR, "Invalid packet size\n"); return -ENODATA; } read_idx = queue->qhdr_read_idx; + write_idx = queue->qhdr_write_idx; - empty_space = (queue->qhdr_write_idx >= read_idx) ? - (queue->qhdr_q_size - (queue->qhdr_write_idx - read_idx)) : - (read_idx - queue->qhdr_write_idx); + empty_space = (write_idx >= read_idx) ? + ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) : + (read_idx - write_idx); if (empty_space <= packet_size_in_words) { queue->qhdr_tx_req = 1; dprintk(VIDC_ERR, "Insufficient size (%d) to write (%d)\n", @@ -609,13 +611,20 @@ static int __write_queue(struct vidc_iface_q_info *qinfo, u8 *packet, queue->qhdr_tx_req = 0; - new_write_idx = (queue->qhdr_write_idx + packet_size_in_words); + new_write_idx = write_idx + packet_size_in_words; write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) + - (queue->qhdr_write_idx << 2)); - if (new_write_idx < queue->qhdr_q_size) { + (write_idx << 2)); + if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr || + write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr + + qinfo->q_array.mem_size)) { + dprintk(VIDC_ERR, "Invalid write index"); + return -ENODATA; + } + + if (new_write_idx < (qinfo->q_array.mem_size >> 2)) { memcpy(write_ptr, packet, packet_size_in_words << 2); } else { - new_write_idx -= queue->qhdr_q_size; + new_write_idx -= qinfo->q_array.mem_size >> 2; memcpy(write_ptr, packet, (packet_size_in_words - new_write_idx) << 2); memcpy((void *)qinfo->q_array.align_virtual_addr, @@ -711,7 +720,8 @@ static int __read_queue(struct vidc_iface_q_info *qinfo, u8 *packet, u32 packet_size_in_words, new_read_idx; u32 *read_ptr; u32 receive_request = 0; - int rc = 0; + u32 read_idx, write_idx; + int rc = 0; if (!qinfo || !packet || !pb_tx_req_is_set) { dprintk(VIDC_ERR, "Invalid Params\n"); @@ -744,7 +754,10 @@ static int __read_queue(struct vidc_iface_q_info *qinfo, u8 *packet, if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q) receive_request = 1; - if (queue->qhdr_read_idx == queue->qhdr_write_idx) { + read_idx = queue->qhdr_read_idx; + write_idx = queue->qhdr_write_idx; + + if (read_idx == write_idx) { queue->qhdr_rx_req = receive_request; /* * mb() to ensure qhdr is updated in main memory @@ -761,21 +774,28 @@ static int __read_queue(struct vidc_iface_q_info *qinfo, u8 *packet, } read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) + - (queue->qhdr_read_idx << 2)); + (read_idx << 2)); + if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr || + read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr + + qinfo->q_array.mem_size - sizeof(*read_ptr))) { + dprintk(VIDC_ERR, "Invalid read index\n"); + return -ENODATA; + } + packet_size_in_words = (*read_ptr) >> 2; if (!packet_size_in_words) { dprintk(VIDC_ERR, "Zero packet size\n"); return -ENODATA; } - new_read_idx = queue->qhdr_read_idx + packet_size_in_words; - if (((packet_size_in_words << 2) <= VIDC_IFACEQ_VAR_HUGE_PKT_SIZE) - && queue->qhdr_read_idx <= queue->qhdr_q_size) { - if (new_read_idx < queue->qhdr_q_size) { + new_read_idx = read_idx + packet_size_in_words; + if (((packet_size_in_words << 2) <= VIDC_IFACEQ_VAR_HUGE_PKT_SIZE) && + read_idx <= (qinfo->q_array.mem_size >> 2)) { + if (new_read_idx < (qinfo->q_array.mem_size >> 2)) { memcpy(packet, read_ptr, packet_size_in_words << 2); } else { - new_read_idx -= queue->qhdr_q_size; + new_read_idx -= (qinfo->q_array.mem_size >> 2); memcpy(packet, read_ptr, (packet_size_in_words - new_read_idx) << 2); memcpy(packet + ((packet_size_in_words - @@ -786,18 +806,18 @@ static int __read_queue(struct vidc_iface_q_info *qinfo, u8 *packet, } else { dprintk(VIDC_WARN, "BAD packet received, read_idx: %#x, pkt_size: %d\n", - queue->qhdr_read_idx, packet_size_in_words << 2); + read_idx, packet_size_in_words << 2); dprintk(VIDC_WARN, "Dropping this packet\n"); - new_read_idx = queue->qhdr_write_idx; + new_read_idx = write_idx; rc = -ENODATA; } - queue->qhdr_read_idx = new_read_idx; - - if (queue->qhdr_read_idx != queue->qhdr_write_idx) + if (new_read_idx != write_idx) queue->qhdr_rx_req = 0; else queue->qhdr_rx_req = receive_request; + + queue->qhdr_read_idx = new_read_idx; /* * mb() to ensure qhdr is updated in main memory * so that venus reads the updated header values -- GitLab From cf1061970eff246ae7233c8d59ce4002d4aee856 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 18 Dec 2018 14:10:31 -0800 Subject: [PATCH 0539/1286] ARM: dts: msm: Update USB QMP PHY configuration on sdxprairie This change updates USB QMP PHY configuration on sdxprairie to allow USB Gen1 and Gen2 functionality. Change-Id: Ibed99c13213ab7813b1e31f78231b49be62aedf5 Signed-off-by: Mayank Rana --- arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi | 40 ++++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index e493952c7047..40c5f674c719 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -191,7 +191,6 @@ USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0 USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0 - USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 @@ -200,12 +199,13 @@ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0 USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0 + USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x8c 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xef 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xff 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x3f 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xff 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xbc 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0 @@ -219,9 +219,9 @@ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0 @@ -232,30 +232,30 @@ USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0 USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0 USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 - USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0 - USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0 - USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 - USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x00 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 - USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0 - USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x05 0 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0 + USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x00 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x20 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x60 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x60 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x17 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0 USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0 - USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0 USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0 - USB3_UNI_PCS_CDR_RESET_TIME 0x0f 0 USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 - USB3_UNI_PCS_EQ_CONFIG1 0x4b 0 - USB3_UNI_PCS_EQ_CONFIG5 0x10 0 + USB3_UNI_PCS_EQ_CONFIG1 0x0d 0 USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x02 0 0xffffffff 0xffffffff 0x00>; qcom,qmp-phy-reg-offset = -- GitLab From c1808ae5035f5a24737755f7c429950e5aef41ec Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 18 Dec 2018 15:01:28 -0800 Subject: [PATCH 0540/1286] usb: phy: Don't program REXT if it is not present On some platform, external REXT is not present. Hence add optional qcom,no-rext-present property to avoid selecting it using USB_PHY_RUTNE_SEL register from phy driver. Change-Id: I1c334d52dd85044dfcaf22473608b58074bcac2e Signed-off-by: Mayank Rana --- .../devicetree/bindings/usb/qcom,msm-phy.txt | 2 ++ drivers/usb/phy/phy-msm-snps-hs.c | 12 ++++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt index 8e22fcc7e1e7..15bbf8a9f5a1 100644 --- a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt +++ b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt @@ -31,6 +31,8 @@ Optional properties: - reg: Address and length of the register set for the device Optional regs are: "phy_rcal_reg": register address for efuse used for rext calibration + - qcom,no-rext-present: Set only if external REXT is not present. Default value + is present. Example: hsphy@f9200000 { diff --git a/drivers/usb/phy/phy-msm-snps-hs.c b/drivers/usb/phy/phy-msm-snps-hs.c index d76c143a929f..e741dc8209c5 100644 --- a/drivers/usb/phy/phy-msm-snps-hs.c +++ b/drivers/usb/phy/phy-msm-snps-hs.c @@ -106,6 +106,7 @@ struct msm_hsphy { bool suspended; bool cable_connected; bool dpdm_enable; + bool no_rext_present; int *param_override_seq; int param_override_seq_cnt; @@ -466,8 +467,12 @@ static int msm_hsphy_init(struct usb_phy *uphy) phy->rcal_mask, phy->phy_rcal_reg, rcal_code); } - /* Use external resistor for tuning if efuse is not programmed */ - if (!rcal_code) + /* + * Use external resistor value only if: + * a. It is present and + * b. efuse is not programmed. + */ + if (!phy->no_rext_present && !rcal_code) msm_usb_write_readback(phy->base, USB2PHY_USB_PHY_RTUNE_SEL, RTUNE_SEL, RTUNE_SEL); @@ -792,6 +797,9 @@ static int msm_hsphy_probe(struct platform_device *pdev) } } + phy->no_rext_present = of_property_read_bool(dev->of_node, + "qcom,no-rext-present"); + phy->param_override_seq_cnt = of_property_count_elems_of_size( dev->of_node, "qcom,param-override-seq", -- GitLab From 10d3e5cdcb881c5abcb5d556d8e1cda3fe53931d Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 18 Dec 2018 15:04:11 -0800 Subject: [PATCH 0541/1286] ARM: dts: msm: Set qcom,no-rext-present on sdxprairie On sdxprairie, there is no external REXT present with USB highspeed phy. Hence set qcom,no-rext-present property to avoid selecting REXT. Change-Id: I6107de0a9cec8bc01cc8cfd8e18101c942117698 Signed-off-by: Mayank Rana --- arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index 40c5f674c719..77ccb8fe15d5 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -143,6 +143,7 @@ resets = <&clock_gcc GCC_QUSB2PHY_BCR>; reset-names = "phy_reset"; + qcom,no-rext-present; }; usb_qmp_phy: ssphy@ff6000 { -- GitLab From af4ffeee77ec4a9842f0390a75e7d0af3bf3d746 Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Wed, 19 Dec 2018 11:38:16 +0530 Subject: [PATCH 0542/1286] defconfig: msm: Add ARMV8 deprecated call support for QCS405 Add config ARMV8_deprecated for emulation of calls SWAP, CP15 barrier and SETEND emulation. Change-Id: I1ee939be7cd1cf9fb7766f2880c24b807ca1766c Signed-off-by: Archit Saxena --- arch/arm64/configs/vendor/qcs405-perf_defconfig | 4 ++++ arch/arm64/configs/vendor/qcs405_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index f2fa37e3d825..cfe03262d8d4 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -44,6 +44,10 @@ CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_SECCOMP=y # CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y CONFIG_ARM64_SW_TTBR0_PAN=y CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set diff --git a/arch/arm64/configs/vendor/qcs405_defconfig b/arch/arm64/configs/vendor/qcs405_defconfig index f98496149b6f..0f1bdb8c40a6 100644 --- a/arch/arm64/configs/vendor/qcs405_defconfig +++ b/arch/arm64/configs/vendor/qcs405_defconfig @@ -47,6 +47,10 @@ CONFIG_CMA_DEBUGFS=y CONFIG_ZSMALLOC=y CONFIG_SECCOMP=y # CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y CONFIG_ARM64_SW_TTBR0_PAN=y CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -- GitLab From 6d4d0bf336a61909a87db65f32ceff037c9ee22c Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 18 Dec 2018 12:03:25 +0530 Subject: [PATCH 0543/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: I22994886e3a6128e9235e3cf698b0bb405275194 Signed-off-by: Pavankumar Kondeti --- include/trace/events/walt.h | 12 ++++++------ kernel/sched/boost.c | 14 +++++--------- kernel/sched/sched.h | 1 - kernel/sched/walt.c | 30 +++--------------------------- kernel/sched/walt.h | 7 ++++++- 5 files changed, 20 insertions(+), 44 deletions(-) diff --git a/include/trace/events/walt.h b/include/trace/events/walt.h index 0dd4f22edf90..0f7a9ed14dc5 100644 --- a/include/trace/events/walt.h +++ b/include/trace/events/walt.h @@ -528,11 +528,11 @@ DEFINE_EVENT(sched_cpu_load, sched_cpu_load_lb, TRACE_EVENT(sched_load_to_gov, TP_PROTO(struct rq *rq, u64 aggr_grp_load, u32 tt_load, - u64 freq_aggr_thresh, u64 load, int policy, + int freq_aggr, u64 load, int policy, int big_task_rotation, unsigned int sysctl_sched_little_cluster_coloc_fmin_khz, u64 coloc_boost_load), - TP_ARGS(rq, aggr_grp_load, tt_load, freq_aggr_thresh, load, policy, + TP_ARGS(rq, aggr_grp_load, tt_load, freq_aggr, load, policy, big_task_rotation, sysctl_sched_little_cluster_coloc_fmin_khz, coloc_boost_load), @@ -541,7 +541,7 @@ TRACE_EVENT(sched_load_to_gov, __field( int, policy ) __field( int, ed_task_pid ) __field( u64, aggr_grp_load ) - __field( u64, freq_aggr_thresh ) + __field( int, freq_aggr ) __field( u64, tt_load ) __field( u64, rq_ps ) __field( u64, grp_rq_ps ) @@ -560,7 +560,7 @@ TRACE_EVENT(sched_load_to_gov, __entry->policy = policy; __entry->ed_task_pid = rq->ed_task ? rq->ed_task->pid : -1; __entry->aggr_grp_load = aggr_grp_load; - __entry->freq_aggr_thresh = freq_aggr_thresh; + __entry->freq_aggr = freq_aggr; __entry->tt_load = tt_load; __entry->rq_ps = rq->prev_runnable_sum; __entry->grp_rq_ps = rq->grp_time.prev_runnable_sum; @@ -574,9 +574,9 @@ TRACE_EVENT(sched_load_to_gov, __entry->coloc_boost_load = coloc_boost_load; ), - TP_printk("cpu=%d policy=%d ed_task_pid=%d aggr_grp_load=%llu freq_aggr_thresh=%llu tt_load=%llu rq_ps=%llu grp_rq_ps=%llu nt_ps=%llu grp_nt_ps=%llu pl=%llu load=%llu big_task_rotation=%d sysctl_sched_little_cluster_coloc_fmin_khz=%u coloc_boost_load=%llu", + TP_printk("cpu=%d policy=%d ed_task_pid=%d aggr_grp_load=%llu freq_aggr=%d tt_load=%llu rq_ps=%llu grp_rq_ps=%llu nt_ps=%llu grp_nt_ps=%llu pl=%llu load=%llu big_task_rotation=%d sysctl_sched_little_cluster_coloc_fmin_khz=%u coloc_boost_load=%llu", __entry->cpu, __entry->policy, __entry->ed_task_pid, - __entry->aggr_grp_load, __entry->freq_aggr_thresh, + __entry->aggr_grp_load, __entry->freq_aggr, __entry->tt_load, __entry->rq_ps, __entry->grp_rq_ps, __entry->nt_ps, __entry->grp_nt_ps, __entry->pl, __entry->load, __entry->big_task_rotation, diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index 8216954b57be..1a9fc36a957b 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -11,6 +11,7 @@ */ #include "sched.h" +#include "walt.h" #include #include #include @@ -26,7 +27,6 @@ unsigned int sysctl_sched_boost; static enum sched_boost_policy boost_policy; static enum sched_boost_policy boost_policy_dt = SCHED_BOOST_NONE; static DEFINE_MUTEX(boost_mutex); -static unsigned int freq_aggr_threshold_backup; static int boost_refcount[MAX_NUM_BOOST_TYPE]; static inline void boost_kick(int cpu) @@ -122,8 +122,7 @@ static void _sched_set_boost(int type) boost_refcount[CONSERVATIVE_BOOST] = 0; } if (boost_refcount[RESTRAINED_BOOST] > 0) { - update_freq_aggregate_threshold( - freq_aggr_threshold_backup); + walt_enable_frequency_aggregation(false); boost_refcount[RESTRAINED_BOOST] = 0; } break; @@ -148,10 +147,8 @@ static void _sched_set_boost(int type) case RESTRAINED_BOOST: boost_refcount[RESTRAINED_BOOST]++; - if (boost_refcount[RESTRAINED_BOOST] == 1) { - freq_aggr_threshold_backup = - update_freq_aggregate_threshold(1); - } + if (boost_refcount[RESTRAINED_BOOST] == 1) + walt_enable_frequency_aggregation(true); break; case FULL_THROTTLE_BOOST_DISABLE: @@ -177,8 +174,7 @@ static void _sched_set_boost(int type) if (boost_refcount[RESTRAINED_BOOST] >= 1) { boost_refcount[RESTRAINED_BOOST]--; if (!boost_refcount[RESTRAINED_BOOST]) - update_freq_aggregate_threshold( - freq_aggr_threshold_backup); + walt_enable_frequency_aggregation(false); } break; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 1a8ff01be17c..5419af9477ed 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2603,7 +2603,6 @@ extern int update_preferred_cluster(struct related_thread_group *grp, struct task_struct *p, u32 old_load); extern void set_preferred_cluster(struct related_thread_group *grp); extern void add_new_task_to_grp(struct task_struct *new); -extern unsigned int update_freq_aggregate_threshold(unsigned int threshold); #define NO_BOOST 0 #define FULL_THROTTLE_BOOST 1 diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c index ad929ceca406..6d9beac026e2 100644 --- a/kernel/sched/walt.c +++ b/kernel/sched/walt.c @@ -303,7 +303,7 @@ void fixup_walt_sched_stats_common(struct rq *rq, struct task_struct *p, * C1 busy time = 5 + 5 + 6 = 16ms * */ -__read_mostly int sched_freq_aggregate_threshold; +__read_mostly bool sched_freq_aggr_en; static u64 update_window_start(struct rq *rq, u64 wallclock, int event) @@ -506,7 +506,6 @@ static u32 top_task_load(struct rq *rq) u64 freq_policy_load(struct rq *rq) { unsigned int reporting_policy = sysctl_sched_freq_reporting_policy; - int freq_aggr_thresh = sched_freq_aggregate_threshold; struct sched_cluster *cluster = rq->cluster; u64 aggr_grp_load = cluster->aggr_grp_load; u64 load, tt_load = 0; @@ -517,7 +516,7 @@ u64 freq_policy_load(struct rq *rq) goto done; } - if (aggr_grp_load > freq_aggr_thresh) + if (sched_freq_aggr_en) load = rq->prev_runnable_sum + aggr_grp_load; else load = rq->prev_runnable_sum + rq->grp_time.prev_runnable_sum; @@ -540,7 +539,7 @@ u64 freq_policy_load(struct rq *rq) } done: - trace_sched_load_to_gov(rq, aggr_grp_load, tt_load, freq_aggr_thresh, + trace_sched_load_to_gov(rq, aggr_grp_load, tt_load, sched_freq_aggr_en, load, reporting_policy, walt_rotation_enabled, sysctl_sched_little_cluster_coloc_fmin_khz, coloc_boost_load); @@ -2505,15 +2504,10 @@ static void transfer_busy_time(struct rq *rq, struct related_thread_group *grp, */ unsigned int __read_mostly sysctl_sched_enable_thread_grouping; -/* Maximum allowed threshold before freq aggregation must be enabled */ -#define MAX_FREQ_AGGR_THRESH 1000 - struct related_thread_group *related_thread_groups[MAX_NUM_CGROUP_COLOC_ID]; static LIST_HEAD(active_related_thread_groups); DEFINE_RWLOCK(related_thread_group_lock); -unsigned int __read_mostly sysctl_sched_freq_aggregate_threshold_pct; - /* * Task groups whose aggregate demand on a cpu is more than * sched_group_upmigrate need to be up-migrated if possible. @@ -2665,23 +2659,6 @@ DEFINE_MUTEX(policy_mutex); #define pct_to_real(tunable) \ (div64_u64((u64)tunable * (u64)max_task_load(), 100)) -unsigned int update_freq_aggregate_threshold(unsigned int threshold) -{ - unsigned int old_threshold; - - mutex_lock(&policy_mutex); - - old_threshold = sysctl_sched_freq_aggregate_threshold_pct; - - sysctl_sched_freq_aggregate_threshold_pct = threshold; - sched_freq_aggregate_threshold = - pct_to_real(sysctl_sched_freq_aggregate_threshold_pct); - - mutex_unlock(&policy_mutex); - - return old_threshold; -} - #define ADD_TASK 0 #define REM_TASK 1 @@ -2912,7 +2889,6 @@ static int __init create_default_coloc_group(void) list_add(&grp->list, &active_related_thread_groups); write_unlock_irqrestore(&related_thread_group_lock, flags); - update_freq_aggregate_threshold(MAX_FREQ_AGGR_THRESH); return 0; } late_initcall(create_default_coloc_group); diff --git a/kernel/sched/walt.h b/kernel/sched/walt.h index 663334d61c48..a500d280dcde 100644 --- a/kernel/sched/walt.h +++ b/kernel/sched/walt.h @@ -47,7 +47,6 @@ extern struct mutex cluster_lock; extern rwlock_t related_thread_group_lock; extern __read_mostly unsigned int sched_ravg_hist_size; extern __read_mostly unsigned int sched_freq_aggregate; -extern __read_mostly int sched_freq_aggregate_threshold; extern __read_mostly unsigned int sched_window_stats_policy; extern __read_mostly unsigned int sched_group_upmigrate; extern __read_mostly unsigned int sched_group_downmigrate; @@ -306,6 +305,12 @@ extern void walt_rotation_checkpoint(int nr_big); extern unsigned int walt_rotation_enabled; extern unsigned int walt_get_default_coloc_group_load(void); +extern __read_mostly bool sched_freq_aggr_en; +static inline void walt_enable_frequency_aggregation(bool enable) +{ + sched_freq_aggr_en = enable; +} + #else /* CONFIG_SCHED_WALT */ static inline void walt_sched_init_rq(struct rq *rq) { } -- GitLab From 963db96893befd4eeada492cc9fca4031479b8b0 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 18 Dec 2018 13:04:11 +0530 Subject: [PATCH 0544/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: Ia43c01e7e368186399b9d021a6761545c7da0c18 Signed-off-by: Pavankumar Kondeti --- kernel/sched/boost.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index 1a9fc36a957b..51f0b07e46fb 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -115,6 +115,7 @@ static void _sched_set_boost(int type) case NO_BOOST: /* All boost clear */ if (boost_refcount[FULL_THROTTLE_BOOST] > 0) { core_ctl_set_boost(false); + walt_enable_frequency_aggregation(false); boost_refcount[FULL_THROTTLE_BOOST] = 0; } if (boost_refcount[CONSERVATIVE_BOOST] > 0) { @@ -133,6 +134,8 @@ static void _sched_set_boost(int type) core_ctl_set_boost(true); restore_cgroup_boost_settings(); boost_kick_cpus(); + if (!boost_refcount[RESTRAINED_BOOST]) + walt_enable_frequency_aggregation(true); } break; @@ -147,7 +150,8 @@ static void _sched_set_boost(int type) case RESTRAINED_BOOST: boost_refcount[RESTRAINED_BOOST]++; - if (boost_refcount[RESTRAINED_BOOST] == 1) + if (boost_refcount[RESTRAINED_BOOST] == 1 && + !boost_refcount[FULL_THROTTLE_BOOST]) walt_enable_frequency_aggregation(true); break; @@ -158,6 +162,9 @@ static void _sched_set_boost(int type) core_ctl_set_boost(false); if (boost_refcount[CONSERVATIVE_BOOST] >= 1) update_cgroup_boost_settings(); + if (!boost_refcount[RESTRAINED_BOOST]) + walt_enable_frequency_aggregation( + false); } } break; @@ -173,7 +180,8 @@ static void _sched_set_boost(int type) case RESTRAINED_BOOST_DISABLE: if (boost_refcount[RESTRAINED_BOOST] >= 1) { boost_refcount[RESTRAINED_BOOST]--; - if (!boost_refcount[RESTRAINED_BOOST]) + if (!boost_refcount[RESTRAINED_BOOST] && + !boost_refcount[FULL_THROTTLE_BOOST]) walt_enable_frequency_aggregation(false); } break; -- GitLab From e0dc2f1be74e74dd3043accda01120dbffe0c6b9 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 19 Dec 2018 15:35:56 -0800 Subject: [PATCH 0545/1286] ARM: dts: msm: Update charger configuration for sdxprairie CDP Update PM8150B charger device configuration for sdxprairie CDP to make it work like batteryless platform. Change-Id: I9d5d5a271a32c66b3a4b4d74fbfb19b374698fbc Signed-off-by: Subbaraman Narayanamurthy --- arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi index 9bb23c612b2a..070e18434f8e 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi @@ -172,3 +172,13 @@ thermal-governor = "user_space"; }; }; + +&pm8150b_charger { + qcom,batteryless-platform; + io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp"; +}; -- GitLab From dde4d2621f18caec8aeb7f956ae82fef33596502 Mon Sep 17 00:00:00 2001 From: Terence Ho Date: Wed, 19 Dec 2018 18:37:02 -0500 Subject: [PATCH 0546/1286] msm: ais: resync with camera kernel Resync with camera kernel for baseline development. Change-Id: I46d0a0c271c4a49d7a423e8bbe2232b7ae2c8358 Signed-off-by: Terence Ho --- .../media/platform/msm/ais/cam_cdm/cam_cdm.h | 4 +- .../msm/ais/cam_cdm/cam_cdm_intf_api.h | 6 +- .../msm/ais/cam_cdm/cam_cdm_virtual_core.c | 5 +- .../platform/msm/ais/cam_core/cam_context.c | 44 +- .../platform/msm/ais/cam_core/cam_context.h | 2 + .../msm/ais/cam_core/cam_context_utils.c | 108 ++- .../msm/ais/cam_core/cam_context_utils.h | 2 + .../msm/ais/cam_core/cam_hw_mgr_intf.h | 57 +- .../platform/msm/ais/cam_core/cam_node.c | 30 +- .../platform/msm/ais/cam_cpas/cam_cpas_hw.h | 2 +- .../platform/msm/ais/cam_cpas/cam_cpas_intf.c | 4 +- .../ais/cam_cpas/cpas_top/cam_cpastop_hw.c | 11 +- .../ais/cam_cpas/cpas_top/cam_cpastop_hw.h | 19 + .../ais/cam_cpas/cpas_top/cpastop_v175_120.h | 730 ++++++++++++++++++ .../msm/ais/cam_cpas/include/cam_cpas_api.h | 8 + .../msm/ais/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 48 +- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c | 21 +- .../msm/ais/cam_icp/cam_icp_context.c | 25 +- .../msm/ais/cam_icp/fw_inc/hfi_intf.h | 8 +- .../msm/ais/cam_icp/fw_inc/hfi_session_defs.h | 41 + drivers/media/platform/msm/ais/cam_icp/hfi.c | 11 +- .../msm/ais/cam_icp/icp_hw/a5_hw/a5_core.c | 2 +- .../msm/ais/cam_icp/icp_hw/a5_hw/a5_core.h | 2 +- .../msm/ais/cam_icp/icp_hw/bps_hw/bps_core.c | 2 +- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 515 +++++++++--- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h | 16 +- .../msm/ais/cam_icp/icp_hw/ipe_hw/ipe_core.c | 2 +- .../media/platform/msm/ais/cam_isp/Makefile | 1 + .../msm/ais/cam_isp/cam_isp_context.c | 349 ++++++--- .../platform/msm/ais/cam_isp/cam_isp_dev.c | 2 + .../ais/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 303 +++++--- .../hw_utils/cam_isp_packet_parser.c | 17 +- .../irq_controller/cam_irq_controller.c | 2 +- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 4 +- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 106 ++- .../isp_hw/ife_csid_hw/cam_ife_csid_core.h | 3 + .../isp_hw/ife_csid_hw/cam_ife_csid_soc.c | 25 +- .../isp_hw/ife_csid_hw/cam_ife_csid_soc.h | 16 +- .../isp_hw/include/cam_ife_csid_hw_intf.h | 10 + .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 1 + .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 7 + .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c | 2 + .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c | 24 +- .../vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c | 13 - .../vfe_hw/vfe_top/cam_vfe_camif_ver2.c | 39 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c | 27 +- .../ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 75 +- .../ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h | 4 +- .../msm/ais/cam_lrme/cam_lrme_context.c | 2 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 17 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h | 6 +- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c | 21 +- .../msm/ais/cam_req_mgr/cam_mem_mgr.c | 180 +++-- .../msm/ais/cam_req_mgr/cam_mem_mgr.h | 2 +- .../msm/ais/cam_req_mgr/cam_mem_mgr_api.h | 17 +- .../msm/ais/cam_req_mgr/cam_req_mgr_core.c | 163 +++- .../msm/ais/cam_req_mgr/cam_req_mgr_core.h | 23 +- .../msm/ais/cam_req_mgr/cam_req_mgr_dev.c | 37 +- .../ais/cam_req_mgr/cam_req_mgr_interface.h | 2 + .../msm/ais/cam_req_mgr/cam_req_mgr_workq.c | 3 +- .../cam_actuator/cam_actuator_core.c | 111 ++- .../cam_actuator/cam_actuator_dev.c | 4 + .../cam_actuator/cam_actuator_dev.h | 2 + .../cam_sensor_module/cam_cci/cam_cci_core.c | 23 +- .../cam_sensor_module/cam_cci/cam_cci_dev.c | 67 +- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 2 + .../cam_csiphy/cam_csiphy_core.c | 47 +- .../cam_csiphy/cam_csiphy_soc.c | 17 + .../cam_csiphy/cam_csiphy_soc.h | 1 + .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 399 ++++++++++ .../cam_csiphy/include/cam_csiphy_2_0_hwreg.h | 2 + .../cam_eeprom/cam_eeprom_core.c | 85 +- .../cam_flash/cam_flash_core.c | 179 +++-- .../cam_flash/cam_flash_dev.c | 25 +- .../cam_flash/cam_flash_dev.h | 4 +- .../cam_sensor_module/cam_ois/cam_ois_core.c | 75 +- .../cam_res_mgr/cam_res_mgr.c | 12 +- .../cam_sensor/cam_sensor_core.c | 153 +++- .../cam_sensor/cam_sensor_dev.c | 4 + .../cam_sensor/cam_sensor_dev.h | 4 + .../cam_sensor_utils/cam_sensor_util.c | 43 +- .../platform/msm/ais/cam_smmu/cam_smmu_api.c | 41 +- .../platform/msm/ais/cam_smmu/cam_smmu_api.h | 5 +- .../platform/msm/ais/cam_sync/cam_sync.c | 36 +- .../platform/msm/ais/cam_sync/cam_sync_util.c | 6 +- .../msm/ais/cam_utils/cam_common_util.h | 6 + .../msm/ais/cam_utils/cam_packet_util.c | 39 +- 87 files changed, 3646 insertions(+), 974 deletions(-) create mode 100644 drivers/media/platform/msm/ais/cam_cpas/cpas_top/cpastop_v175_120.h create mode 100644 drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h diff --git a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm.h b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm.h index def321d7f825..ff8be3570bc5 100644 --- a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm.h +++ b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm.h @@ -195,11 +195,11 @@ struct cam_cdm_hw_intf_cmd_submit_bl { struct cam_cdm_bl_request *data; }; -/* struct cam_cdm_hw_mem - CDM hw memory.struct */ +/* struct cam_cdm_hw_mem - CDM hw memory struct */ struct cam_cdm_hw_mem { int32_t handle; uint32_t vaddr; - uint64_t kmdvaddr; + uintptr_t kmdvaddr; size_t size; }; diff --git a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_intf_api.h b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_intf_api.h index 2b00a87544fa..6aa6e6d2bc4c 100644 --- a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_intf_api.h @@ -105,10 +105,10 @@ struct cam_cdm_bl_cmd { union { int32_t mem_handle; uint32_t *hw_iova; - void *kernel_iova; + uintptr_t kernel_iova; } bl_addr; - uint32_t offset; - uint32_t len; + uint32_t offset; + uint32_t len; }; /** diff --git a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_virtual_core.c b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_virtual_core.c index 504436784d93..9021ecabb27c 100644 --- a/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_virtual_core.c +++ b/drivers/media/platform/msm/ais/cam_cdm/cam_cdm_virtual_core.c @@ -87,7 +87,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, mutex_lock(&client->lock); for (i = 0; i < req->data->cmd_arrary_count ; i++) { - uint64_t vaddr_ptr = 0; + uintptr_t vaddr_ptr = 0; size_t len = 0; if ((!cdm_cmd->cmd[i].len) && @@ -106,8 +106,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, } else if (req->data->type == CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA) { rc = 0; - vaddr_ptr = - (uint64_t)cdm_cmd->cmd[i].bl_addr.kernel_iova; + vaddr_ptr = cdm_cmd->cmd[i].bl_addr.kernel_iova; len = cdm_cmd->cmd[i].offset + cdm_cmd->cmd[i].len; } else { CAM_ERR(CAM_CDM, diff --git a/drivers/media/platform/msm/ais/cam_core/cam_context.c b/drivers/media/platform/msm/ais/cam_core/cam_context.c index 24e93f0ad445..081a96d311e3 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_context.c +++ b/drivers/media/platform/msm/ais/cam_core/cam_context.c @@ -42,25 +42,32 @@ static int cam_context_handle_hw_event(void *context, uint32_t evt_id, int cam_context_shutdown(struct cam_context *ctx) { int rc = 0; - int32_t ctx_hdl = ctx->dev_hdl; - - mutex_lock(&ctx->ctx_mutex); - if (ctx->state_machine[ctx->state].ioctl_ops.stop_dev) { - rc = ctx->state_machine[ctx->state].ioctl_ops.stop_dev( - ctx, NULL); - if (rc < 0) - CAM_ERR(CAM_CORE, "Error while dev stop %d", rc); - } - if (ctx->state_machine[ctx->state].ioctl_ops.release_dev) { - rc = ctx->state_machine[ctx->state].ioctl_ops.release_dev( - ctx, NULL); - if (rc < 0) - CAM_ERR(CAM_CORE, "Error while dev release %d", rc); + struct cam_release_dev_cmd cmd; + + if (ctx->state > CAM_CTX_AVAILABLE && ctx->state < CAM_CTX_STATE_MAX) { + cmd.session_handle = ctx->session_hdl; + cmd.dev_handle = ctx->dev_hdl; + rc = cam_context_handle_release_dev(ctx, &cmd); + if (rc) + CAM_ERR(CAM_CORE, + "context release failed for dev_name %s", + ctx->dev_name); + else + cam_context_putref(ctx); + } else { + CAM_WARN(CAM_CORE, + "dev %s context id %u state %d invalid to release hdl", + ctx->dev_name, ctx->ctx_id, ctx->state); + rc = -EINVAL; } - mutex_unlock(&ctx->ctx_mutex); - if (!rc) - rc = cam_destroy_device_hdl(ctx_hdl); + rc = cam_destroy_device_hdl(ctx->dev_hdl); + if (rc) + CAM_ERR(CAM_CORE, "destroy device hdl failed for node %s", + ctx->dev_name); + else + ctx->dev_hdl = -1; + return rc; } @@ -484,6 +491,8 @@ int cam_context_handle_stop_dev(struct cam_context *ctx, /* stop device can be optional for some driver */ CAM_WARN(CAM_CORE, "No stop device in dev %d, name %s state %d", ctx->dev_hdl, ctx->dev_name, ctx->state); + + ctx->last_flush_req = 0; mutex_unlock(&ctx->ctx_mutex); return rc; @@ -518,6 +527,7 @@ int cam_context_init(struct cam_context *ctx, ctx->dev_name = dev_name; ctx->dev_id = dev_id; ctx->ctx_id = ctx_id; + ctx->last_flush_req = 0; ctx->ctx_crm_intf = NULL; ctx->crm_ctx_intf = crm_node_intf; ctx->hw_mgr_intf = hw_mgr_intf; diff --git a/drivers/media/platform/msm/ais/cam_core/cam_context.h b/drivers/media/platform/msm/ais/cam_core/cam_context.h index 003fea6a0df1..cf07d95eb7f6 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_context.h +++ b/drivers/media/platform/msm/ais/cam_core/cam_context.h @@ -180,6 +180,7 @@ struct cam_ctx_ops { * @refcount: Context object refcount * @node: The main node to which this context belongs * @sync_mutex: mutex to sync with sync cb thread + * @last_flush_req: Last request to flush * */ struct cam_context { @@ -215,6 +216,7 @@ struct cam_context { struct kref refcount; void *node; struct mutex sync_mutex; + uint32_t last_flush_req; }; /** diff --git a/drivers/media/platform/msm/ais/cam_core/cam_context_utils.c b/drivers/media/platform/msm/ais/cam_core/cam_context_utils.c index d78203a9609d..1c17fc7720ca 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_context_utils.c +++ b/drivers/media/platform/msm/ais/cam_core/cam_context_utils.c @@ -266,28 +266,84 @@ int32_t cam_context_release_dev_to_hw(struct cam_context *ctx, return 0; } +int32_t cam_context_config_dev_to_hw( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + size_t len; + struct cam_hw_stream_setttings cfg; + uintptr_t packet_addr; + struct cam_packet *packet; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + return -EINVAL; + } + + if (!ctx->hw_mgr_intf->hw_config_stream_settings) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + return rc; + } + + rc = cam_context_validate_thread(); + if (rc) { + CAM_ERR(CAM_CTXT, + "Not executing in the right context"); + return rc; + } + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_CTXT, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + memset(&cfg, 0, sizeof(cfg)); + cfg.packet = packet; + cfg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cfg.priv = NULL; + + CAM_DBG(CAM_CTXT, "Processing config settings"); + rc = ctx->hw_mgr_intf->hw_config_stream_settings( + ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc) { + CAM_ERR(CAM_CTXT, + "[%s][%d] Config failed stream settings", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + } + + return rc; +} + int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, struct cam_config_dev_cmd *cmd) { int rc = 0; struct cam_ctx_request *req = NULL; struct cam_hw_prepare_update_args cfg; - uint64_t packet_addr; + uintptr_t packet_addr; struct cam_packet *packet; size_t len = 0; int32_t i = 0, j = 0; if (!ctx || !cmd) { CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); - rc = -EINVAL; - goto end; + return -EINVAL; } if (!ctx->hw_mgr_intf) { CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", ctx->dev_name, ctx->ctx_id); - rc = -EFAULT; - goto end; + return -EFAULT; } rc = cam_context_validate_thread(); if (rc) @@ -304,8 +360,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, if (!req) { CAM_ERR(CAM_CTXT, "[%s][%d] No more request obj free", ctx->dev_name, ctx->ctx_id); - rc = -ENOMEM; - goto end; + return -ENOMEM; } memset(req, 0, sizeof(*req)); @@ -315,8 +370,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, /* for config dev, only memory handle is supported */ /* map packet from the memhandle */ rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, - (uint64_t *) &packet_addr, - &len); + &packet_addr, &len); if (rc != 0) { CAM_ERR(CAM_CTXT, "[%s][%d] Can not get packet address", ctx->dev_name, ctx->ctx_id); @@ -324,7 +378,19 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, goto free_req; } - packet = (struct cam_packet *) (packet_addr + cmd->offset); + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + if (packet->header.request_id <= ctx->last_flush_req) { + CAM_DBG(CAM_CORE, + "request %lld has been flushed, reject packet", + packet->header.request_id); + rc = -EINVAL; + goto free_cpu_buf; + } + + if (packet->header.request_id > ctx->last_flush_req) + ctx->last_flush_req = 0; /* preprocess the configuration */ memset(&cfg, 0, sizeof(cfg)); @@ -346,7 +412,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, "[%s][%d] Prepare config packet failed in HW layer", ctx->dev_name, ctx->ctx_id); rc = -EFAULT; - goto free_req; + goto free_cpu_buf; } req->num_hw_update_entries = cfg.num_hw_update_entries; req->num_out_map_entries = cfg.num_out_map_entries; @@ -397,30 +463,35 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->request_id); cam_context_putref(ctx); - goto put_ref; } CAM_DBG(CAM_CTXT, "register in fence cb: %d ret = %d", req->in_map_entries[j].sync_id, rc); } - goto end; } + if (cam_mem_put_cpu_buf((int32_t) cmd->packet_handle)) + CAM_WARN(CAM_CTXT, "[%s][%d] Can not put packet address", + ctx->dev_name, ctx->ctx_id); + return rc; put_ref: for (--i; i >= 0; i--) { - rc = cam_sync_put_obj_ref(req->out_map_entries[i].sync_id); - if (rc) + if (cam_sync_put_obj_ref(req->out_map_entries[i].sync_id)) CAM_ERR(CAM_CTXT, "Failed to put ref of fence %d", req->out_map_entries[i].sync_id); } +free_cpu_buf: + if (cam_mem_put_cpu_buf((int32_t) cmd->packet_handle)) + CAM_WARN(CAM_CTXT, "[%s][%d] Can not put packet address", + ctx->dev_name, ctx->ctx_id); free_req: spin_lock(&ctx->lock); list_add_tail(&req->list, &ctx->free_req_list); req->ctx = NULL; spin_unlock(&ctx->lock); -end: + return rc; } @@ -811,9 +882,10 @@ int32_t cam_context_flush_dev_to_hw(struct cam_context *ctx, goto end; } - if (cmd->flush_type == CAM_FLUSH_TYPE_ALL) + if (cmd->flush_type == CAM_FLUSH_TYPE_ALL) { + ctx->last_flush_req = cmd->req_id; rc = cam_context_flush_ctx_to_hw(ctx); - else if (cmd->flush_type == CAM_FLUSH_TYPE_REQ) + } else if (cmd->flush_type == CAM_FLUSH_TYPE_REQ) rc = cam_context_flush_req_to_hw(ctx, cmd); else { rc = -EINVAL; diff --git a/drivers/media/platform/msm/ais/cam_core/cam_context_utils.h b/drivers/media/platform/msm/ais/cam_core/cam_context_utils.h index 43e69405ee3b..e1809b2fa436 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_context_utils.h +++ b/drivers/media/platform/msm/ais/cam_core/cam_context_utils.h @@ -21,6 +21,8 @@ int32_t cam_context_release_dev_to_hw(struct cam_context *ctx, struct cam_release_dev_cmd *cmd); int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, struct cam_config_dev_cmd *cmd); +int32_t cam_context_config_dev_to_hw( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd); int32_t cam_context_acquire_dev_to_hw(struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd); int32_t cam_context_start_dev_to_hw(struct cam_context *ctx, diff --git a/drivers/media/platform/msm/ais/cam_core/cam_hw_mgr_intf.h b/drivers/media/platform/msm/ais/cam_core/cam_hw_mgr_intf.h index f427a4dac6d2..fd30f115cc0c 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_hw_mgr_intf.h +++ b/drivers/media/platform/msm/ais/cam_core/cam_hw_mgr_intf.h @@ -13,6 +13,9 @@ #ifndef _CAM_HW_MGR_INTF_H_ #define _CAM_HW_MGR_INTF_H_ +#include +#include + /* * This file declares Constants, Enums, Structures and APIs to be used as * Interface between HW Manager and Context. @@ -48,7 +51,7 @@ struct cam_hw_update_entry { uint32_t offset; uint32_t len; uint32_t flags; - uint64_t addr; + uintptr_t addr; }; /** @@ -94,7 +97,7 @@ struct cam_hw_acquire_args { cam_hw_event_cb_func event_cb; uint32_t num_acq; uint32_t acquire_info_size; - uint64_t acquire_info; + uintptr_t acquire_info; void *ctxt_to_hw_map; }; @@ -180,6 +183,20 @@ struct cam_hw_prepare_update_args { struct cam_hw_mgr_dump_pf_data *pf_data; }; +/** + * struct cam_hw_stream_setttings - Payload for config stream command + * + * @packet: CSL packet from user mode driver + * @ctxt_to_hw_map: HW context from the acquire + * @priv: Private pointer of hw update + * + */ +struct cam_hw_stream_setttings { + struct cam_packet *packet; + void *ctxt_to_hw_map; + void *priv; +}; + /** * struct cam_hw_config_args - Payload for config command * @@ -268,28 +285,30 @@ struct cam_hw_cmd_args { /** * cam_hw_mgr_intf - HW manager interface * - * @hw_mgr_priv: HW manager object - * @hw_get_caps: Function pointer for get hw caps + * @hw_mgr_priv: HW manager object + * @hw_get_caps: Function pointer for get hw caps * args = cam_query_cap_cmd - * @hw_acquire: Function poniter for acquire hw resources + * @hw_acquire: Function poniter for acquire hw resources * args = cam_hw_acquire_args - * @hw_release: Function pointer for release hw device resource + * @hw_release: Function pointer for release hw device resource * args = cam_hw_release_args - * @hw_start: Function pointer for start hw devices + * @hw_start: Function pointer for start hw devices * args = cam_hw_start_args - * @hw_stop: Function pointer for stop hw devices + * @hw_stop: Function pointer for stop hw devices * args = cam_hw_stop_args - * @hw_prepare_update: Function pointer for prepare hw update for hw devices - * args = cam_hw_prepare_update_args - * @hw_config: Function pointer for configure hw devices + * @hw_prepare_update: Function pointer for prepare hw update for hw + * devices args = cam_hw_prepare_update_args + * @hw_config_stream_settings: Function pointer for configure stream for hw + * devices args = cam_hw_stream_setttings + * @hw_config: Function pointer for configure hw devices * args = cam_hw_config_args - * @hw_read: Function pointer for read hardware registers - * @hw_write: Function pointer for Write hardware registers - * @hw_cmd: Function pointer for any customized commands for the - * hardware manager - * @hw_open: Function pointer for HW init - * @hw_close: Function pointer for HW deinit - * @hw_flush: Function pointer for HW flush + * @hw_read: Function pointer for read hardware registers + * @hw_write: Function pointer for Write hardware registers + * @hw_cmd: Function pointer for any customized commands for + * the hardware manager + * @hw_open: Function pointer for HW init + * @hw_close: Function pointer for HW deinit + * @hw_flush: Function pointer for HW flush * */ struct cam_hw_mgr_intf { @@ -301,6 +320,8 @@ struct cam_hw_mgr_intf { int (*hw_start)(void *hw_priv, void *hw_start_args); int (*hw_stop)(void *hw_priv, void *hw_stop_args); int (*hw_prepare_update)(void *hw_priv, void *hw_prepare_update_args); + int (*hw_config_stream_settings)(void *hw_priv, + void *hw_stream_settings); int (*hw_config)(void *hw_priv, void *hw_config_args); int (*hw_read)(void *hw_priv, void *read_args); int (*hw_write)(void *hw_priv, void *write_args); diff --git a/drivers/media/platform/msm/ais/cam_core/cam_node.c b/drivers/media/platform/msm/ais/cam_core/cam_node.c index 6584868e418f..397f19bf203e 100644 --- a/drivers/media/platform/msm/ais/cam_core/cam_node.c +++ b/drivers/media/platform/msm/ais/cam_core/cam_node.c @@ -31,7 +31,7 @@ static void cam_node_print_ctx_state( for (i = 0; i < node->ctx_size; i++) { ctx = &node->ctx_list[i]; - spin_lock(&ctx->lock); + spin_lock_bh(&ctx->lock); CAM_INFO(CAM_CORE, "[%s][%d] : state=%d, refcount=%d, active_req_list=%d, pending_req_list=%d, wait_req_list=%d, free_req_list=%d", ctx->dev_name ? ctx->dev_name : "null", @@ -41,7 +41,7 @@ static void cam_node_print_ctx_state( list_empty(&ctx->pending_req_list), list_empty(&ctx->wait_req_list), list_empty(&ctx->free_req_list)); - spin_unlock(&ctx->lock); + spin_unlock_bh(&ctx->lock); } mutex_unlock(&node->list_mutex); } @@ -344,6 +344,8 @@ static int __cam_node_handle_release_dev(struct cam_node *node, if (rc) CAM_ERR(CAM_CORE, "destroy device hdl failed for node %s", node->name); + else + ctx->dev_hdl = -1; CAM_DBG(CAM_CORE, "[%s] Release ctx_id=%d, refcount=%d", node->name, ctx->ctx_id, @@ -510,9 +512,6 @@ int cam_node_shutdown(struct cam_node *node) "Node [%s] invoking shutdown on context [%d]", node->name, i); rc = cam_context_shutdown(&(node->ctx_list[i])); - if (rc) - continue; - cam_context_putref(&(node->ctx_list[i])); } } @@ -580,7 +579,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_QUERY_CAP: { struct cam_query_cap_cmd query; - if (copy_from_user(&query, (void __user *)cmd->handle, + if (copy_from_user(&query, u64_to_user_ptr(cmd->handle), sizeof(query))) { rc = -EFAULT; break; @@ -593,7 +592,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) break; } - if (copy_to_user((void __user *)cmd->handle, &query, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &query, sizeof(query))) rc = -EFAULT; @@ -602,7 +601,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_ACQUIRE_DEV: { struct cam_acquire_dev_cmd acquire; - if (copy_from_user(&acquire, (void __user *)cmd->handle, + if (copy_from_user(&acquire, u64_to_user_ptr(cmd->handle), sizeof(acquire))) { rc = -EFAULT; break; @@ -613,7 +612,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) rc); break; } - if (copy_to_user((void __user *)cmd->handle, &acquire, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &acquire, sizeof(acquire))) rc = -EFAULT; break; @@ -658,6 +657,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) "acquire device failed(rc = %d)", rc); goto acquire_kfree; } + CAM_INFO(CAM_CORE, "Acquire HW successful"); } if (copy_to_user((void __user *)cmd->handle, acquire_ptr, @@ -671,7 +671,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_START_DEV: { struct cam_start_stop_dev_cmd start; - if (copy_from_user(&start, (void __user *)cmd->handle, + if (copy_from_user(&start, u64_to_user_ptr(cmd->handle), sizeof(start))) rc = -EFAULT; else { @@ -685,7 +685,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_STOP_DEV: { struct cam_start_stop_dev_cmd stop; - if (copy_from_user(&stop, (void __user *)cmd->handle, + if (copy_from_user(&stop, u64_to_user_ptr(cmd->handle), sizeof(stop))) rc = -EFAULT; else { @@ -699,7 +699,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_CONFIG_DEV: { struct cam_config_dev_cmd config; - if (copy_from_user(&config, (void __user *)cmd->handle, + if (copy_from_user(&config, u64_to_user_ptr(cmd->handle), sizeof(config))) rc = -EFAULT; else { @@ -713,7 +713,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_RELEASE_DEV: { struct cam_release_dev_cmd release; - if (copy_from_user(&release, (void __user *)cmd->handle, + if (copy_from_user(&release, u64_to_user_ptr(cmd->handle), sizeof(release))) rc = -EFAULT; else { @@ -764,6 +764,8 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) "release device failed(rc = %d)", rc); } + CAM_INFO(CAM_CORE, "Release HW done(rc = %d)", rc); + release_kfree: kfree(release_ptr); break; @@ -771,7 +773,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) case CAM_FLUSH_REQ: { struct cam_flush_dev_cmd flush; - if (copy_from_user(&flush, (void __user *)cmd->handle, + if (copy_from_user(&flush, u64_to_user_ptr(cmd->handle), sizeof(flush))) rc = -EFAULT; else { diff --git a/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_hw.h b/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_hw.h index 30d94269edc3..f93d036ecfcf 100644 --- a/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_hw.h +++ b/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_hw.h @@ -23,7 +23,7 @@ #define CAM_CPAS_AXI_MIN_MNOC_AB_BW (2048 * 1024) #define CAM_CPAS_AXI_MIN_MNOC_IB_BW (2048 * 1024) #define CAM_CPAS_AXI_MIN_CAMNOC_AB_BW (2048 * 1024) -#define CAM_CPAS_AXI_MIN_CAMNOC_IB_BW (3000000000L) +#define CAM_CPAS_AXI_MIN_CAMNOC_IB_BW (3000000000UL) #define CAM_CPAS_GET_CLIENT_IDX(handle) (handle) #define CAM_CPAS_GET_CLIENT_HANDLE(indx) (indx) diff --git a/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_intf.c b/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_intf.c index cdc8a3baef28..a9f1e4f8364e 100644 --- a/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_intf.c +++ b/drivers/media/platform/msm/ais/cam_cpas/cam_cpas_intf.c @@ -367,7 +367,7 @@ int cam_cpas_subdev_cmd(struct cam_cpas_intf *cpas_intf, case CAM_QUERY_CAP: { struct cam_cpas_query_cap query; - rc = copy_from_user(&query, (void __user *) cmd->handle, + rc = copy_from_user(&query, u64_to_user_ptr(cmd->handle), sizeof(query)); if (rc) { CAM_ERR(CAM_CPAS, "Failed in copy from user, rc=%d", @@ -381,7 +381,7 @@ int cam_cpas_subdev_cmd(struct cam_cpas_intf *cpas_intf, if (rc) break; - rc = copy_to_user((void __user *) cmd->handle, &query, + rc = copy_to_user(u64_to_user_ptr(cmd->handle), &query, sizeof(query)); if (rc) CAM_ERR(CAM_CPAS, "Failed in copy to user, rc=%d", rc); diff --git a/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.c index 7f531fdddd9e..ee72171f8ae1 100644 --- a/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -24,6 +24,7 @@ #include "cpastop_v170_110.h" #include "cpastop_v175_100.h" #include "cpastop_v175_101.h" +#include "cpastop_v175_120.h" struct cam_camnoc_info *camnoc_info; @@ -105,6 +106,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, (hw_caps->cpas_version.minor == 0) && (hw_caps->cpas_version.incr == 1)) soc_info->hw_version = CAM_CPAS_TITAN_175_V101; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 2) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_175_V120; } else if ((hw_caps->camera_version.major == 1) && (hw_caps->camera_version.minor == 5) && (hw_caps->camera_version.incr == 0)) { @@ -405,7 +410,8 @@ static void cam_cpastop_work(struct work_struct *work) if ((payload->irq_status & camnoc_info->irq_err[i].sbm_port) && (camnoc_info->irq_err[i].enable)) { irq_type = camnoc_info->irq_err[i].irq_type; - CAM_ERR(CAM_CPAS, "Error occurred, type=%d", irq_type); + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "Error occurred, type=%d", irq_type); memset(&irq_data, 0x0, sizeof(irq_data)); irq_data.irq_type = (enum cam_camnoc_irq_type)irq_type; @@ -586,6 +592,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_175_V101: camnoc_info = &cam175_cpas101_camnoc_info; break; + case CAM_CPAS_TITAN_175_V120: + camnoc_info = &cam175_cpas120_camnoc_info; + break; case CAM_CPAS_TITAN_150_V100: camnoc_info = &cam150_cpas100_camnoc_info; break; diff --git a/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.h index 465b4d5a9b89..fa98c474b189 100644 --- a/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -36,6 +36,10 @@ * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error * detected in the IPE/BPS UBWC * encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR: Triggered if any UBWC error + * is detected in IFE0 write path + * @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR: Triggered if any UBWC error + * is detected in IFE1 write path * @CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT : Triggered when the QHS_ICP * slave times out after 4000 * AHB cycles @@ -50,6 +54,10 @@ enum cam_camnoc_hw_irq_type { CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR = CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR = CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR = @@ -69,10 +77,16 @@ enum cam_camnoc_hw_irq_type { * @CAM_CAMNOC_CDM: Indicates CDM HW connection to camnoc * @CAM_CAMNOC_IFE02: Indicates IFE0, IFE2 HW connection to camnoc * @CAM_CAMNOC_IFE13: Indicates IFE1, IFE3 HW connection to camnoc + * @CAM_CAMNOC_IFE0123_RDI_WRITE: RDI write only for all IFEx + * @CAM_CAMNOC_IFE0_NRDI_WRITE: IFE0 non-RDI write + * @CAM_CAMNOC_IFE01_RDI_READ: IFE0/1 RDI READ + * @CAM_CAMNOC_IFE1_NRDI_WRITE: IFE1 non-RDI write * @CAM_CAMNOC_IPE_BPS_LRME_READ: Indicates IPE, BPS, LRME Read HW * connection to camnoc * @CAM_CAMNOC_IPE_BPS_LRME_WRITE: Indicates IPE, BPS, LRME Write HW * connection to camnoc + * @CAM_CAMNOC_IPE_VID_DISP_WRITE: Indicates IPE's VID/DISP Wrire HW + * connection to camnoc * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc @@ -81,8 +95,13 @@ enum cam_camnoc_port_type { CAM_CAMNOC_CDM, CAM_CAMNOC_IFE02, CAM_CAMNOC_IFE13, + CAM_CAMNOC_IFE0123_RDI_WRITE, + CAM_CAMNOC_IFE0_NRDI_WRITE, + CAM_CAMNOC_IFE01_RDI_READ, + CAM_CAMNOC_IFE1_NRDI_WRITE, CAM_CAMNOC_IPE_BPS_LRME_READ, CAM_CAMNOC_IPE_BPS_LRME_WRITE, + CAM_CAMNOC_IPE_VID_DISP_WRITE, CAM_CAMNOC_JPEG, CAM_CAMNOC_FD, CAM_CAMNOC_ICP, diff --git a/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cpastop_v175_120.h b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cpastop_v175_120.h new file mode 100644 index 000000000000..072361a98a92 --- /dev/null +++ b/drivers/media/platform/msm/ais/cam_cpas/cpas_top/cpastop_v175_120.h @@ -0,0 +1,730 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPASTOP_V175_120_H_ +#define _CPASTOP_V175_120_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v175_120_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2240, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v175_120_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3BA0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x3B90, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x3B98, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x55a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5590, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5598, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2Ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2B90, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v175_120_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* cdm_main_SpecificToNttpTr_Urgency_Low */ + .offset = 0x4238, + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0123_RDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_LOW */ + .offset = 0x3630, + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */ + .offset = 0x3634, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */ + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */ + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */ + .value = 1, + }, + }, + { + /* IFE0/1 RDI READ PATH */ + .port_type = CAM_CAMNOC_IFE01_RDI_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */ + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */ + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */ + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */ + .mask = 0x7, + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE1_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */ + .offset = 0x5434, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */ + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2E38, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */ + .offset = 0x5E30, + .value = 0x33330000, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */ + .offset = 0x5E34, + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */ + .offset = 0x5E38, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */ + .mask = 0x70, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */ + .offset = 0x5E40, + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */ + .offset = 0x5E48, + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + /*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/ + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2288, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam175_cpas120_err_logger_offsets = { + .mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam175_cpas120_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2300, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam175_cpas120_camnoc_info = { + .specific = &cam_cpas_v175_120_camnoc_specific[0], + .specific_size = sizeof(cam_cpas_v175_120_camnoc_specific) / + sizeof(cam_cpas_v175_120_camnoc_specific[0]), + .irq_sbm = &cam_cpas_v175_120_irq_sbm, + .irq_err = &cam_cpas_v175_120_irq_err[0], + .irq_err_size = sizeof(cam_cpas_v175_120_irq_err) / + sizeof(cam_cpas_v175_120_irq_err[0]), + .err_logger = &cam175_cpas120_err_logger_offsets, + .errata_wa_list = &cam175_cpas120_errata_wa_list, +}; + +#endif /* _CPASTOP_V175_120_H_ */ diff --git a/drivers/media/platform/msm/ais/cam_cpas/include/cam_cpas_api.h b/drivers/media/platform/msm/ais/cam_cpas/include/cam_cpas_api.h index 02c4d01ae7d6..2aabf47eadc2 100644 --- a/drivers/media/platform/msm/ais/cam_cpas/include/cam_cpas_api.h +++ b/drivers/media/platform/msm/ais/cam_cpas/include/cam_cpas_api.h @@ -47,6 +47,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_170_V120 = 0x170120, CAM_CPAS_TITAN_175_V100 = 0x175100, CAM_CPAS_TITAN_175_V101 = 0x175101, + CAM_CPAS_TITAN_175_V120 = 0x175120, CAM_CPAS_TITAN_MAX }; @@ -64,6 +65,11 @@ enum cam_cpas_hw_version { * @CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error detected * in the IFE1 or IFE3 UBWC encoder * instance + * @CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE0 UBWC encoder instance + * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE1 UBWC encoder + * instance * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error detected * in the IPE/BPS UBWC decoder * instance @@ -77,6 +83,8 @@ enum cam_camnoc_irq_type { CAM_CAMNOC_IRQ_SLAVE_ERROR, CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_AHB_TIMEOUT, diff --git a/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index d3c39f940f05..a28c99ae5147 100644 --- a/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -417,7 +417,7 @@ static int cam_fd_packet_generic_blob_handler(void *user_data, uint32_t *get_raw_results = (uint32_t *)blob_data; if (sizeof(uint32_t) != blob_size) { - CAM_ERR(CAM_FD, "Invalid blob size %lu %u", + CAM_ERR(CAM_FD, "Invalid blob size %zu %u", sizeof(uint32_t), blob_size); return -EINVAL; } @@ -430,7 +430,7 @@ static int cam_fd_packet_generic_blob_handler(void *user_data, (struct cam_fd_soc_clock_bw_request *)blob_data; if (sizeof(struct cam_fd_soc_clock_bw_request) != blob_size) { - CAM_ERR(CAM_FD, "Invalid blob size %lu %u", + CAM_ERR(CAM_FD, "Invalid blob size %zu %u", sizeof(struct cam_fd_soc_clock_bw_request), blob_size); return -EINVAL; @@ -534,10 +534,11 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, struct cam_fd_hw_io_buffer *output_buf, uint32_t io_buf_size) { int rc = -EINVAL; - uint32_t i, j, plane, num_out_buf, num_in_buf; + uint32_t plane, num_out_buf, num_in_buf; + int i, j; struct cam_buf_io_cfg *io_cfg; - uint64_t io_addr[CAM_PACKET_MAX_PLANES]; - uint64_t cpu_addr[CAM_PACKET_MAX_PLANES]; + dma_addr_t io_addr[CAM_PACKET_MAX_PLANES]; + uintptr_t cpu_addr[CAM_PACKET_MAX_PLANES]; size_t size; bool need_io_map, need_cpu_map; @@ -583,7 +584,7 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, rc = cam_mem_get_io_buf( io_cfg[i].mem_handle[plane], iommu_hdl, &io_addr[plane], &size); - if ((rc) || (io_addr[plane] >> 32)) { + if (rc) { CAM_ERR(CAM_FD, "Invalid io buf %d %d %d %d", io_cfg[i].direction, @@ -599,13 +600,14 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, rc = cam_mem_get_cpu_buf( io_cfg[i].mem_handle[plane], &cpu_addr[plane], &size); - if (rc) { + if (rc || ((io_addr[plane] & 0xFFFFFFFF) + != io_addr[plane])) { CAM_ERR(CAM_FD, "Invalid cpu buf %d %d %d %d", io_cfg[i].direction, io_cfg[i].resource_type, plane, rc); - return rc; + goto rel_cpu_buf; } cpu_addr[plane] += io_cfg[i].offsets[plane]; @@ -655,14 +657,34 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, default: CAM_ERR(CAM_FD, "Unsupported io direction %d", io_cfg[i].direction); - return -EINVAL; + rc = -EINVAL; + break; + } + + for (j = 0; j < plane; j++) { + if (need_cpu_map) { + if (cam_mem_put_cpu_buf( + io_cfg[i].mem_handle[j])) + CAM_WARN(CAM_FD, + "Invalid cpu buf %d %d %d %d", + io_cfg[i].direction, + io_cfg[i].resource_type, j); + } } } prepare->num_in_map_entries = num_in_buf; prepare->num_out_map_entries = num_out_buf; + return rc; - return 0; +rel_cpu_buf: + for (j = plane - 1; j >= 0; j--) { + if (cam_mem_put_cpu_buf(io_cfg[i].mem_handle[j])) + CAM_WARN(CAM_FD, "Fail to put cpu buf %d %d %d", + io_cfg[i].direction, + io_cfg[i].resource_type, j); + } + return rc; } static int cam_fd_mgr_util_prepare_hw_update_entries( @@ -1088,8 +1110,10 @@ static int cam_fd_mgr_hw_get_caps(void *hw_mgr_priv, void *hw_get_caps_args) struct cam_fd_hw_mgr *hw_mgr = hw_mgr_priv; struct cam_query_cap_cmd *query = hw_get_caps_args; struct cam_fd_query_cap_cmd query_fd; + void __user *caps_handle = + u64_to_user_ptr(query->caps_handle); - if (copy_from_user(&query_fd, (void __user *)query->caps_handle, + if (copy_from_user(&query_fd, caps_handle, sizeof(struct cam_fd_query_cap_cmd))) { CAM_ERR(CAM_FD, "Failed in copy from user, rc=%d", rc); return -EFAULT; @@ -1106,7 +1130,7 @@ static int cam_fd_mgr_hw_get_caps(void *hw_mgr_priv, void *hw_get_caps_args) query_fd.hw_caps.wrapper_version.major, query_fd.hw_caps.wrapper_version.minor); - if (copy_to_user((void __user *)query->caps_handle, &query_fd, + if (copy_to_user(caps_handle, &query_fd, sizeof(struct cam_fd_query_cap_cmd))) rc = -EFAULT; diff --git a/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c index 87dc6949de0c..8be20a772129 100644 --- a/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c +++ b/drivers/media/platform/msm/ais/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -427,6 +427,7 @@ static int cam_fd_hw_util_processcmd_frame_done(struct cam_hw_info *fd_hw, unsigned long flags; int i; + mutex_lock(&fd_hw->hw_mutex); spin_lock_irqsave(&fd_core->spin_lock, flags); if ((fd_core->core_state != CAM_FD_CORE_STATE_IDLE) || (fd_core->results_valid == false) || @@ -436,6 +437,7 @@ static int cam_fd_hw_util_processcmd_frame_done(struct cam_hw_info *fd_hw, fd_core->core_state, fd_core->results_valid, fd_core->hw_req_private); spin_unlock_irqrestore(&fd_core->spin_lock, flags); + mutex_unlock(&fd_hw->hw_mutex); return -EINVAL; } fd_core->core_state = CAM_FD_CORE_STATE_READING_RESULTS; @@ -516,6 +518,7 @@ static int cam_fd_hw_util_processcmd_frame_done(struct cam_hw_info *fd_hw, fd_core->hw_req_private = NULL; fd_core->core_state = CAM_FD_CORE_STATE_IDLE; spin_unlock_irqrestore(&fd_core->spin_lock, flags); + mutex_unlock(&fd_hw->hw_mutex); return 0; } @@ -544,6 +547,10 @@ irqreturn_t cam_fd_hw_irq(int irq_num, void *data) CAM_DBG(CAM_FD, "FD IRQ status 0x%x", reg_value); + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_clear, + reg_value); + if (reg_value & CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE)) { complete_all(&fd_core->halt_complete); irq_type = CAM_FD_IRQ_HALT_DONE; @@ -575,10 +582,6 @@ irqreturn_t cam_fd_hw_irq(int irq_num, void *data) trace_cam_irq_activated("FD", irq_type); - cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, - hw_static_info->wrapper_regs.irq_clear, - hw_static_info->irq_mask); - if (irq_type == CAM_FD_IRQ_HALT_DONE) { /* * Do not send HALT IRQ callback to Hw Mgr, @@ -651,7 +654,7 @@ int cam_fd_hw_init(void *hw_priv, void *init_hw_args, uint32_t arg_size) } if (arg_size != sizeof(struct cam_fd_hw_init_args)) { - CAM_ERR(CAM_FD, "Invalid arg size %u, %lu", arg_size, + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, sizeof(struct cam_fd_hw_init_args)); return -EINVAL; } @@ -735,7 +738,7 @@ int cam_fd_hw_deinit(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) } if (arg_size != sizeof(struct cam_fd_hw_deinit_args)) { - CAM_ERR(CAM_FD, "Invalid arg size %u, %lu", arg_size, + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, sizeof(struct cam_fd_hw_deinit_args)); return -EINVAL; } @@ -859,7 +862,7 @@ int cam_fd_hw_start(void *hw_priv, void *hw_start_args, uint32_t arg_size) } if (arg_size != sizeof(struct cam_fd_hw_cmd_start_args)) { - CAM_ERR(CAM_FD, "Invalid arg size %u, %lu", arg_size, + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, sizeof(struct cam_fd_hw_cmd_start_args)); return -EINVAL; } @@ -1010,7 +1013,7 @@ int cam_fd_hw_reserve(void *hw_priv, void *hw_reserve_args, uint32_t arg_size) } if (arg_size != sizeof(struct cam_fd_hw_reserve_args)) { - CAM_ERR(CAM_FD, "Invalid arg size %u, %lu", arg_size, + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, sizeof(struct cam_fd_hw_reserve_args)); return -EINVAL; } @@ -1079,7 +1082,7 @@ int cam_fd_hw_release(void *hw_priv, void *hw_release_args, uint32_t arg_size) } if (arg_size != sizeof(struct cam_fd_hw_release_args)) { - CAM_ERR(CAM_FD, "Invalid arg size %u, %lu", arg_size, + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, sizeof(struct cam_fd_hw_release_args)); return -EINVAL; } diff --git a/drivers/media/platform/msm/ais/cam_icp/cam_icp_context.c b/drivers/media/platform/msm/ais/cam_icp/cam_icp_context.c index 522a602883eb..b47ec34c0aeb 100644 --- a/drivers/media/platform/msm/ais/cam_icp/cam_icp_context.c +++ b/drivers/media/platform/msm/ais/cam_icp/cam_icp_context.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "cam_sync_api.h" #include "cam_node.h" #include "cam_context.h" @@ -123,8 +124,30 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, struct cam_config_dev_cmd *cmd) { int rc; + size_t len; + uintptr_t packet_addr; + struct cam_packet *packet; + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_ICP, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + if (((packet->header.op_code & 0xff) == + CAM_ICP_OPCODE_IPE_SETTINGS) || + ((packet->header.op_code & 0xff) == + CAM_ICP_OPCODE_BPS_SETTINGS)) + rc = cam_context_config_dev_to_hw(ctx, cmd); + else + rc = cam_context_prepare_dev_to_hw(ctx, cmd); - rc = cam_context_prepare_dev_to_hw(ctx, cmd); if (rc) CAM_ERR(CAM_ICP, "Failed to prepare device"); diff --git a/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_intf.h b/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_intf.h index 3e636c65138d..3d0ee725dcad 100644 --- a/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_intf.h +++ b/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_intf.h @@ -23,10 +23,10 @@ * @reserved: reserved field */ struct hfi_mem { - uint64_t len; - uint64_t kva; - uint32_t iova; - uint32_t reserved; + uint64_t len; + uintptr_t kva; + uint32_t iova; + uint32_t reserved; }; /** diff --git a/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_session_defs.h b/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_session_defs.h index 69e6ccfb1f37..38137b89295e 100644 --- a/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_session_defs.h +++ b/drivers/media/platform/msm/ais/cam_icp/fw_inc/hfi_session_defs.h @@ -30,10 +30,51 @@ #define HFI_IPEBPS_CMD_OPCODE_IPE_WAIT_FOR_BPS 0xb #define HFI_IPEBPS_CMD_OPCODE_IPE_WAIT_FOR_IPE 0xc +#define HFI_IPEBPS_CMD_OPCODE_MEM_MAP 0xe +#define HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP 0xf + #define HFI_IPEBPS_HANDLE_TYPE_BPS 0x1 #define HFI_IPEBPS_HANDLE_TYPE_IPE_RT 0x2 #define HFI_IPEBPS_HANDLE_TYPE_IPE_NON_RT 0x3 +/** + * struct mem_map_region_data + * @start_addr: cmd buffer region start addr + * @len : length of the region + * + * create mem_map_region_data + */ +struct mem_map_region_data { + uint32_t start_addr; + uint32_t len; +}; + +/** + * struct hfi_cmd_ipe_bps_map + * @user_data : user arg + * @mem_map_request_num: number of mappings + * @mem_map_region_sets: array of all map/unmap info + * + * create hfi_cmd_ipe_bps_map + */ +struct hfi_cmd_ipe_bps_map { + uint64_t user_data; + uint32_t mem_map_request_num; + struct mem_map_region_data mem_map_region_sets[1]; +} __packed; + +/** + * struct hfi_cmd_ipe_bps_map_ack + * @rc : Async return code + * @user_data: user_arg + * + * create hfi_cmd_ipe_bps_map_ack + */ +struct hfi_cmd_ipe_bps_map_ack { + uint32_t rc; + uint64_t user_data; +}; + /** * struct abort_data * @num_req_ids: Number of req ids diff --git a/drivers/media/platform/msm/ais/cam_icp/hfi.c b/drivers/media/platform/msm/ais/cam_icp/hfi.c index cd44d834dd06..c82a3b9bd5ef 100644 --- a/drivers/media/platform/msm/ais/cam_icp/hfi.c +++ b/drivers/media/platform/msm/ais/cam_icp/hfi.c @@ -42,6 +42,9 @@ #define HFI_MAX_POLL_TRY 5 +#define HFI_MAX_PC_POLL_TRY 150 +#define HFI_POLL_TRY_SLEEP 2 + static struct hfi_info *g_hfi; unsigned int g_icp_mmu_hdl; static DEFINE_MUTEX(hfi_cmd_q_mutex); @@ -513,8 +516,8 @@ void cam_hfi_disable_cpu(void __iomem *icp_base) uint32_t val; uint32_t try = 0; - while (try < HFI_MAX_POLL_TRY) { - data = cam_io_r(icp_base + HFI_REG_A5_CSR_A5_STATUS); + while (try < HFI_MAX_PC_POLL_TRY) { + data = cam_io_r_mb(icp_base + HFI_REG_A5_CSR_A5_STATUS); CAM_DBG(CAM_HFI, "wfi status = %x\n", (int)data); if (data & ICP_CSR_A5_STATUS_WFI) @@ -523,7 +526,7 @@ void cam_hfi_disable_cpu(void __iomem *icp_base) * and Host can the proceed. No interrupt is expected from FW * at this time. */ - msleep(100); + msleep_interruptible(HFI_POLL_TRY_SLEEP); try++; } @@ -537,7 +540,7 @@ void cam_hfi_disable_cpu(void __iomem *icp_base) cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_RESET, icp_base + HFI_REG_HOST_ICP_INIT_REQUEST); cam_io_w_mb((uint32_t)INTR_DISABLE, - g_hfi->csr_base + HFI_REG_A5_CSR_A2HOSTINTEN); + icp_base + HFI_REG_A5_CSR_A2HOSTINTEN); } void cam_hfi_enable_cpu(void __iomem *icp_base) diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.c b/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.c index 8f2c76943ebc..18bd6d8dd2c7 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.c +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.c @@ -167,7 +167,7 @@ static int32_t cam_icp_program_fw(const uint8_t *elf, if (prg_hdr->p_filesz != 0) { src = (u8 *)((u8 *)elf + prg_hdr->p_offset); dest = (u8 *)(((u8 *)core_info->fw_kva_addr) + - prg_hdr->p_vaddr); + prg_hdr->p_vaddr); memcpy_toio(dest, src, prg_hdr->p_filesz); } diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.h b/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.h index f4bc813353a8..9b02167b3c7f 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.h +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/a5_hw/a5_core.h @@ -69,7 +69,7 @@ struct cam_a5_device_core_info { const struct firmware *fw_elf; void *fw; uint32_t fw_buf; - uint64_t fw_kva_addr; + uintptr_t fw_kva_addr; uint64_t fw_buf_len; struct cam_icp_a5_query_cap query_cap; struct cam_icp_a5_acquire_dev a5_acquire[8]; diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/bps_hw/bps_core.c b/drivers/media/platform/msm/ais/cam_icp/icp_hw/bps_hw/bps_core.c index e73d53806383..b969c92ccbc8 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/bps_hw/bps_core.c +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/bps_hw/bps_core.c @@ -199,7 +199,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev) cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); if (pwr_ctrl & BPS_COLLAPSE_MASK) { - CAM_WARN(CAM_ICP, "BPS: pwr_ctrl set(%x)", pwr_ctrl); + CAM_DBG(CAM_ICP, "BPS: pwr_ctrl set(%x)", pwr_ctrl); cam_cpas_reg_write(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, 0); diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 0ea6b47c3484..901f54eeb1aa 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1088,6 +1088,7 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr, struct cam_hw_intf *ipe0_dev_intf = NULL; struct cam_hw_intf *ipe1_dev_intf = NULL; struct cam_hw_intf *bps_dev_intf = NULL; + uint32_t core_info_mask = 0; int rc = 0; ipe0_dev_intf = hw_mgr->ipe0_dev_intf; @@ -1111,8 +1112,8 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr, bps_dev_intf->hw_ops.process_cmd( bps_dev_intf->hw_priv, CAM_ICP_BPS_CMD_POWER_RESUME, NULL, 0); - hw_mgr->core_info = hw_mgr->core_info | ICP_PWR_CLP_BPS; } + core_info_mask = ICP_PWR_CLP_BPS; } else { if (hw_mgr->ipe_ctxt_cnt++) goto end; @@ -1139,19 +1140,20 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr, } } hw_mgr->ipe_clk_state = true; - if (icp_hw_mgr.ipe_bps_pc_flag) { - hw_mgr->core_info = hw_mgr->core_info | - (ICP_PWR_CLP_IPE0 | ICP_PWR_CLP_IPE1); - } + + if ((icp_hw_mgr.ipe1_enable) && + (ipe1_dev_intf)) + core_info_mask = (ICP_PWR_CLP_IPE0 | + ICP_PWR_CLP_IPE1); + else + core_info_mask = ICP_PWR_CLP_IPE0; } - CAM_DBG(CAM_ICP, "core_info %X", hw_mgr->core_info); + CAM_DBG(CAM_ICP, "core_info %X", core_info_mask); if (icp_hw_mgr.ipe_bps_pc_flag) - rc = hfi_enable_ipe_bps_pc(true, hw_mgr->core_info); - else if (icp_hw_mgr.icp_pc_flag) - rc = hfi_enable_ipe_bps_pc(false, hw_mgr->core_info); + rc = hfi_enable_ipe_bps_pc(true, core_info_mask); else - rc = hfi_enable_ipe_bps_pc(false, hw_mgr->core_info); + rc = hfi_enable_ipe_bps_pc(false, core_info_mask); end: return rc; } @@ -1186,13 +1188,12 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, if (hw_mgr->bps_ctxt_cnt) goto end; - if (icp_hw_mgr.ipe_bps_pc_flag && !hw_mgr->recovery) { + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { rc = bps_dev_intf->hw_ops.process_cmd( bps_dev_intf->hw_priv, CAM_ICP_BPS_CMD_POWER_COLLAPSE, NULL, 0); - hw_mgr->core_info = - hw_mgr->core_info & (~ICP_PWR_CLP_BPS); } if (hw_mgr->bps_clk_state) { @@ -1208,7 +1209,8 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, if (hw_mgr->ipe_ctxt_cnt) goto end; - if (icp_hw_mgr.ipe_bps_pc_flag && !hw_mgr->recovery) { + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { rc = ipe0_dev_intf->hw_ops.process_cmd( ipe0_dev_intf->hw_priv, CAM_ICP_IPE_CMD_POWER_COLLAPSE, NULL, 0); @@ -1219,7 +1221,8 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, ipe0_dev_intf->hw_priv, NULL, 0); if (ipe1_dev_intf) { - if (icp_hw_mgr.ipe_bps_pc_flag && !hw_mgr->recovery) { + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { rc = ipe1_dev_intf->hw_ops.process_cmd( ipe1_dev_intf->hw_priv, CAM_ICP_IPE_CMD_POWER_COLLAPSE, @@ -1232,13 +1235,8 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, } hw_mgr->ipe_clk_state = false; - if (icp_hw_mgr.ipe_bps_pc_flag && !hw_mgr->recovery) { - hw_mgr->core_info = hw_mgr->core_info & - (~(ICP_PWR_CLP_IPE0 | ICP_PWR_CLP_IPE1)); - } } - CAM_DBG(CAM_ICP, "Exit: core_info = %x", hw_mgr->core_info); end: return rc; } @@ -1455,15 +1453,12 @@ static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; request_id = ioconfig_ack->user_data2; - ctx_data = (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); if (!ctx_data) { - CAM_ERR(CAM_ICP, "Invalid Context"); + CAM_ERR(CAM_ICP, "Invalid Context req %llu", request_id); return -EINVAL; } - CAM_DBG(CAM_REQ, - "ctx_id : %u, request_id :%lld dev_type: %d", - ctx_data->ctx_id, request_id, - ctx_data->icp_dev_acquire_info->dev_type); mutex_lock(&ctx_data->ctx_mutex); cam_icp_ctx_timer_reset(ctx_data); @@ -1474,6 +1469,11 @@ static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) return 0; } + CAM_DBG(CAM_REQ, + "ctx_id : %u, request_id :%lld dev_type: %d", + ctx_data->ctx_id, request_id, + ctx_data->icp_dev_acquire_info->dev_type); + clk_type = ICP_DEV_TYPE_TO_CLK_TYPE( ctx_data->icp_dev_acquire_info->dev_type); cam_icp_device_timer_reset(&icp_hw_mgr, clk_type); @@ -1491,6 +1491,11 @@ static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) } idx = i; + if (flag == ICP_FRAME_PROCESS_FAILURE) + CAM_ERR(CAM_ICP, "Done with error: ctx_id %d req %llu dev %d", + ctx_data->ctx_id, request_id, + ctx_data->icp_dev_acquire_info->dev_type); + buf_data.request_id = hfi_frame_process->request_id[idx]; ctx_data->ctxt_event_cb(ctx_data->context_priv, flag, &buf_data); hfi_frame_process->request_id[idx] = 0; @@ -1520,7 +1525,9 @@ static int cam_icp_mgr_process_msg_frame_process(uint32_t *msg_ptr) ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; if (ioconfig_ack->err_type != HFI_ERR_SYS_NONE) { CAM_ERR(CAM_ICP, "failed with error : %u", - ioconfig_ack->err_type); + ioconfig_ack->err_type); + cam_icp_mgr_handle_frame_process(msg_ptr, + ICP_FRAME_PROCESS_FAILURE); return -EIO; } @@ -1562,8 +1569,8 @@ static int cam_icp_mgr_process_msg_config_io(uint32_t *msg_ptr) ipe_config_ack->rc, ioconfig_ack->err_type); return -EIO; } - ctx_data = - (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); if (!ctx_data) { CAM_ERR(CAM_ICP, "wrong ctx data from IPE response"); return -EINVAL; @@ -1577,8 +1584,8 @@ static int cam_icp_mgr_process_msg_config_io(uint32_t *msg_ptr) bps_config_ack->rc, ioconfig_ack->opcode); return -EIO; } - ctx_data = - (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); if (!ctx_data) { CAM_ERR(CAM_ICP, "wrong ctx data from BPS response"); return -EINVAL; @@ -1601,7 +1608,9 @@ static int cam_icp_mgr_process_msg_create_handle(uint32_t *msg_ptr) return -EINVAL; } - ctx_data = (struct cam_icp_hw_ctx_data *)create_handle_ack->user_data1; + ctx_data = + (struct cam_icp_hw_ctx_data *)(uintptr_t) + create_handle_ack->user_data1; if (!ctx_data) { CAM_ERR(CAM_ICP, "Invalid ctx_data"); return -EINVAL; @@ -1632,7 +1641,8 @@ static int cam_icp_mgr_process_msg_ping_ack(uint32_t *msg_ptr) return -EINVAL; } - ctx_data = (struct cam_icp_hw_ctx_data *)ping_ack->user_data; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ping_ack->user_data); if (!ctx_data) { CAM_ERR(CAM_ICP, "Invalid ctx_data"); return -EINVAL; @@ -1696,8 +1706,8 @@ static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) case HFI_IPEBPS_CMD_OPCODE_IPE_ABORT: case HFI_IPEBPS_CMD_OPCODE_BPS_ABORT: ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; - ctx_data = - (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) complete(&ctx_data->wait_complete); CAM_DBG(CAM_ICP, "received IPE/BPS/ ABORT: ctx_state =%d", @@ -1706,8 +1716,8 @@ static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) case HFI_IPEBPS_CMD_OPCODE_IPE_DESTROY: case HFI_IPEBPS_CMD_OPCODE_BPS_DESTROY: ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; - ctx_data = - (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); if ((ctx_data->state == CAM_ICP_CTX_STATE_RELEASE) || (ctx_data->state == CAM_ICP_CTX_STATE_IN_USE)) { complete(&ctx_data->wait_complete); @@ -1715,6 +1725,26 @@ static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) CAM_DBG(CAM_ICP, "received IPE/BPS/ DESTROY: ctx_state =%d", ctx_data->state); break; + case HFI_IPEBPS_CMD_OPCODE_MEM_MAP: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = + (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) + complete(&ctx_data->wait_complete); + CAM_DBG(CAM_ICP, + "received IPE/BPS MAP ACK:ctx_state =%d err_status =%u", + ctx_data->state, ioconfig_ack->err_type); + break; + case HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = + (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) + complete(&ctx_data->wait_complete); + CAM_DBG(CAM_ICP, + "received IPE/BPS UNMAP ACK:ctx_state =%d err_status =%u", + ctx_data->state, ioconfig_ack->err_type); + break; default: CAM_ERR(CAM_ICP, "Invalid opcode : %u", msg_ptr[ICP_PACKET_OPCODE]); @@ -1764,15 +1794,12 @@ static int cam_icp_ipebps_reset(struct cam_icp_hw_mgr *hw_mgr) static int cam_icp_mgr_trigger_recovery(struct cam_icp_hw_mgr *hw_mgr) { int rc = 0; - int i = 0; struct sfr_buf *sfr_buffer = NULL; CAM_DBG(CAM_ICP, "Enter"); - mutex_lock(&hw_mgr->hw_mgr_mutex); - if (hw_mgr->recovery) { + if (atomic_read(&hw_mgr->recovery)) { CAM_ERR(CAM_ICP, "Recovery is set"); - mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; } @@ -1781,28 +1808,7 @@ static int cam_icp_mgr_trigger_recovery(struct cam_icp_hw_mgr *hw_mgr) cam_icp_ipebps_reset(hw_mgr); - hw_mgr->recovery = true; - - if (hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog) { - hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog_reset_counter = 0; - crm_timer_exit(&hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog); - hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog = NULL; - } - if (hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog) { - hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog_reset_counter = 0; - crm_timer_exit(&hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog); - hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog = NULL; - } - - for (i = 0; i < CAM_ICP_CTX_MAX; i++) { - mutex_lock(&hw_mgr->ctx_data[i].ctx_mutex); - if (hw_mgr->ctx_data[i].state != CAM_ICP_CTX_STATE_RELEASE) - cam_icp_ctx_timer_stop(&hw_mgr->ctx_data[i]); - mutex_unlock(&hw_mgr->ctx_data[i].ctx_mutex); - } - - mutex_unlock(&hw_mgr->hw_mgr_mutex); - + atomic_set(&hw_mgr->recovery, 1); CAM_DBG(CAM_ICP, "Done"); return rc; } @@ -2133,7 +2139,7 @@ static int cam_icp_alloc_shared_mem(struct cam_mem_mgr_memory_desc *qtbl) static int cam_icp_allocate_fw_mem(void) { int rc; - uint64_t kvaddr; + uintptr_t kvaddr; size_t len; dma_addr_t iova; @@ -2147,7 +2153,7 @@ static int cam_icp_allocate_fw_mem(void) icp_hw_mgr.hfi_mem.fw_buf.iova = iova; icp_hw_mgr.hfi_mem.fw_buf.smmu_hdl = icp_hw_mgr.iommu_hdl; - CAM_DBG(CAM_ICP, "kva: %llX, iova: %llx, len: %zu", + CAM_DBG(CAM_ICP, "kva: %zX, iova: %llx, len: %zu", kvaddr, iova, len); return rc; @@ -2383,7 +2389,7 @@ static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr) } a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; - if (!hw_mgr->icp_pc_flag || hw_mgr->recovery) { + if (!hw_mgr->icp_pc_flag || atomic_read(&hw_mgr->recovery)) { cam_hfi_disable_cpu( a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); rc = cam_icp_mgr_hw_close_k(hw_mgr, NULL); @@ -2487,7 +2493,7 @@ static int cam_icp_mgr_abort_handle( reinit_completion(&ctx_data->wait_complete); abort_cmd->num_fw_handles = 1; abort_cmd->fw_handles[0] = ctx_data->fw_handle; - abort_cmd->user_data1 = (uint64_t)ctx_data; + abort_cmd->user_data1 = PTR_TO_U64(ctx_data); abort_cmd->user_data2 = (uint64_t)0x0; rc = hfi_write_cmd(abort_cmd); @@ -2538,7 +2544,7 @@ static int cam_icp_mgr_destroy_handle( reinit_completion(&ctx_data->wait_complete); destroy_cmd->num_fw_handles = 1; destroy_cmd->fw_handles[0] = ctx_data->fw_handle; - destroy_cmd->user_data1 = (uint64_t)ctx_data; + destroy_cmd->user_data1 = PTR_TO_U64(ctx_data); destroy_cmd->user_data2 = (uint64_t)0x0; memcpy(destroy_cmd->payload.direct, &ctx_data->temp_payload, sizeof(uint64_t)); @@ -2587,7 +2593,7 @@ static int cam_icp_mgr_release_ctx(struct cam_icp_hw_mgr *hw_mgr, int ctx_id) &hw_mgr->ctx_data[ctx_id], 0); hw_mgr->ctx_data[ctx_id].state = CAM_ICP_CTX_STATE_RELEASE; CAM_DBG(CAM_ICP, "E: ctx_id = %d recovery = %d", - ctx_id, hw_mgr->recovery); + ctx_id, atomic_read(&hw_mgr->recovery)); cam_icp_mgr_abort_handle(&hw_mgr->ctx_data[ctx_id]); cam_icp_mgr_destroy_handle(&hw_mgr->ctx_data[ctx_id]); cam_icp_mgr_cleanup_ctx(&hw_mgr->ctx_data[ctx_id]); @@ -2983,7 +2989,7 @@ static int cam_icp_mgr_hw_open(void *hw_mgr_priv, void *download_fw_args) hw_mgr->ctxt_cnt = 0; hw_mgr->fw_download = true; - hw_mgr->recovery = false; + atomic_set(&hw_mgr->recovery, 0); CAM_INFO(CAM_ICP, "FW download done successfully"); @@ -3097,7 +3103,7 @@ static int cam_icp_mgr_send_config_io(struct cam_icp_hw_ctx_data *ctx_data, ioconfig_cmd.num_fw_handles = 1; ioconfig_cmd.fw_handles[0] = ctx_data->fw_handle; ioconfig_cmd.payload.indirect = io_buf_addr; - ioconfig_cmd.user_data1 = (uint64_t)ctx_data; + ioconfig_cmd.user_data1 = PTR_TO_U64(ctx_data); ioconfig_cmd.user_data2 = (uint64_t)0x0; task_data = (struct hfi_cmd_work_data *)task->payload; task_data->data = (void *)&ioconfig_cmd; @@ -3228,7 +3234,7 @@ static int cam_icp_mgr_prepare_frame_process_cmd( hfi_cmd->num_fw_handles = 1; hfi_cmd->fw_handles[0] = ctx_data->fw_handle; hfi_cmd->payload.indirect = fw_cmd_buf_iova_addr; - hfi_cmd->user_data1 = (uint64_t)ctx_data; + hfi_cmd->user_data1 = PTR_TO_U64(ctx_data); hfi_cmd->user_data2 = request_id; CAM_DBG(CAM_ICP, "ctx_data : %pK, request_id :%lld cmd_buf %x", @@ -3238,6 +3244,60 @@ static int cam_icp_mgr_prepare_frame_process_cmd( return 0; } +static bool cam_icp_mgr_is_valid_inconfig(struct cam_packet *packet) +{ + int i, num_in_map_entries = 0; + bool in_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) + num_in_map_entries++; + + if (num_in_map_entries <= CAM_MAX_IN_RES) { + in_config_valid = true; + } else { + CAM_ERR(CAM_ICP, "In config entries(%u) more than allowed(%u)", + num_in_map_entries, CAM_MAX_IN_RES); + } + + CAM_DBG(CAM_ICP, "number of in_config info: %u %u %u %u", + packet->num_io_configs, IPE_IO_IMAGES_MAX, + num_in_map_entries, CAM_MAX_IN_RES); + + return in_config_valid; +} + +static bool cam_icp_mgr_is_valid_outconfig(struct cam_packet *packet) +{ + int i, num_out_map_entries = 0; + bool out_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) + num_out_map_entries++; + + if (num_out_map_entries <= CAM_MAX_OUT_RES) { + out_config_valid = true; + } else { + CAM_ERR(CAM_ICP, "Out config entries(%u) more than allowed(%u)", + num_out_map_entries, CAM_MAX_OUT_RES); + } + + CAM_DBG(CAM_ICP, "number of out_config info: %u %u %u %u", + packet->num_io_configs, IPE_IO_IMAGES_MAX, + num_out_map_entries, CAM_MAX_OUT_RES); + + return out_config_valid; +} + static int cam_icp_mgr_pkt_validation(struct cam_packet *packet) { if (((packet->header.op_code & 0xff) != @@ -3261,6 +3321,11 @@ static int cam_icp_mgr_pkt_validation(struct cam_packet *packet) return -EINVAL; } + if (!cam_icp_mgr_is_valid_inconfig(packet) || + !cam_icp_mgr_is_valid_outconfig(packet)) { + return -EINVAL; + } + CAM_DBG(CAM_ICP, "number of cmd/patch info: %u %u %u %u", packet->num_cmd_buf, packet->num_io_configs, IPE_IO_IMAGES_MAX, @@ -3268,16 +3333,36 @@ static int cam_icp_mgr_pkt_validation(struct cam_packet *packet) return 0; } +static int cam_icp_mgr_put_cmd_buf(struct cam_packet *packet) +{ + int i = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (cmd_desc[i].type == CAM_CMD_BUF_FW) { + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_ICP, "put cmd buf failed: 0x%x", + cmd_desc[i].mem_handle); + } + } + + return 0; +} + static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, struct cam_packet *packet, struct cam_icp_hw_ctx_data *ctx_data, uint32_t *fw_cmd_buf_iova_addr) { int rc = 0; int i, j, k; + int num_cmd_buf = 0; uint64_t addr; size_t len; struct cam_cmd_buf_desc *cmd_desc = NULL; - uint64_t cpu_addr = 0; + uintptr_t cpu_addr = 0; struct ipe_frame_process_data *frame_process_data = NULL; struct bps_frame_process_data *bps_frame_process_data = NULL; struct frame_set *ipe_set = NULL; @@ -3287,38 +3372,37 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); *fw_cmd_buf_iova_addr = 0; - for (i = 0; i < packet->num_cmd_buf; i++) { + for (i = 0; i < packet->num_cmd_buf; i++, num_cmd_buf++) { if (cmd_desc[i].type == CAM_CMD_BUF_FW) { rc = cam_mem_get_io_buf(cmd_desc[i].mem_handle, hw_mgr->iommu_hdl, &addr, &len); if (rc) { CAM_ERR(CAM_ICP, "get cmd buf failed %x", hw_mgr->iommu_hdl); - return rc; + num_cmd_buf = (num_cmd_buf > 0) ? + num_cmd_buf-- : 0; + goto rel_cmd_buf; } *fw_cmd_buf_iova_addr = addr; *fw_cmd_buf_iova_addr = (*fw_cmd_buf_iova_addr + cmd_desc[i].offset); rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, &cpu_addr, &len); - if (rc) { + if (rc || !cpu_addr) { CAM_ERR(CAM_ICP, "get cmd buf failed %x", hw_mgr->iommu_hdl); *fw_cmd_buf_iova_addr = 0; - return rc; + num_cmd_buf = (num_cmd_buf > 0) ? + num_cmd_buf-- : 0; + goto rel_cmd_buf; } cpu_addr = cpu_addr + cmd_desc[i].offset; } } - if (!cpu_addr) { - CAM_ERR(CAM_ICP, "Invalid cpu addr"); - return -EINVAL; - } - if (ctx_data->icp_dev_acquire_info->dev_type != CAM_ICP_RES_TYPE_BPS) { - CAM_DBG(CAM_ICP, "cpu addr = %llx", cpu_addr); + CAM_DBG(CAM_ICP, "cpu addr = %zx", cpu_addr); frame_process_data = (struct ipe_frame_process_data *)cpu_addr; CAM_DBG(CAM_ICP, "%u %u %u", frame_process_data->max_num_cores, frame_process_data->target_time, @@ -3339,7 +3423,7 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, } } } else { - CAM_DBG(CAM_ICP, "cpu addr = %llx", cpu_addr); + CAM_DBG(CAM_ICP, "cpu addr = %zx", cpu_addr); bps_frame_process_data = (struct bps_frame_process_data *)cpu_addr; CAM_DBG(CAM_ICP, "%u %u", @@ -3359,6 +3443,18 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, } } + return rc; + +rel_cmd_buf: + for (i = num_cmd_buf; i >= 0; i--) { + if (cmd_desc[i].type == CAM_CMD_BUF_FW) { + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) { + CAM_WARN(CAM_ICP, "put cmd buf failed 0x%x", + cmd_desc[i].mem_handle); + } + } + } + return rc; } @@ -3430,17 +3526,114 @@ static int cam_icp_mgr_process_io_cfg(struct cam_icp_hw_mgr *hw_mgr, return rc; } +static int cam_icp_process_stream_settings( + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_cmd_mem_regions *cmd_mem_regions, + bool map_unmap) +{ + int rc = 0, i = 0; + size_t packet_size, map_cmd_size, len; + uint64_t iova; + unsigned long rem_jiffies; + int timeout = 5000; + struct hfi_cmd_ipe_bps_map *map_cmd; + struct hfi_cmd_ipebps_async *async_direct; + + map_cmd_size = + sizeof(struct hfi_cmd_ipe_bps_map) + + ((cmd_mem_regions->num_regions - 1) * + sizeof(struct mem_map_region_data)); + + map_cmd = kzalloc(map_cmd_size, GFP_KERNEL); + if (!map_cmd) + return -ENOMEM; + + for (i = 0; i < cmd_mem_regions->num_regions; i++) { + rc = cam_mem_get_io_buf( + cmd_mem_regions->map_info_array[i].mem_handle, + icp_hw_mgr.iommu_hdl, &iova, &len); + if (rc) { + CAM_ERR(CAM_ICP, + "Failed to get cmd region iova for handle %u", + cmd_mem_regions->map_info_array[i].mem_handle); + kfree(map_cmd); + return -EINVAL; + } + + map_cmd->mem_map_region_sets[i].start_addr = (uint32_t)iova + + (cmd_mem_regions->map_info_array[i].offset); + map_cmd->mem_map_region_sets[i].len = (uint32_t) len; + + CAM_DBG(CAM_ICP, "Region %u mem_handle %d iova %pK len %u", + (i+1), cmd_mem_regions->map_info_array[i].mem_handle, + (uint32_t)iova, (uint32_t)len); + } + + map_cmd->mem_map_request_num = cmd_mem_regions->num_regions; + map_cmd->user_data = 0; + + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + (sizeof(struct hfi_cmd_ipe_bps_map) + + ((cmd_mem_regions->num_regions - 1) * + sizeof(struct mem_map_region_data))) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + + async_direct = kzalloc(packet_size, GFP_KERNEL); + if (!async_direct) { + kfree(map_cmd); + return -ENOMEM; + } + + async_direct->size = packet_size; + async_direct->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (map_unmap) + async_direct->opcode = HFI_IPEBPS_CMD_OPCODE_MEM_MAP; + else + async_direct->opcode = HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP; + async_direct->num_fw_handles = 1; + async_direct->fw_handles[0] = ctx_data->fw_handle; + async_direct->user_data1 = (uint64_t)ctx_data; + async_direct->user_data2 = (uint64_t)0x0; + memcpy(async_direct->payload.direct, map_cmd, + map_cmd_size); + + reinit_completion(&ctx_data->wait_complete); + rc = hfi_write_cmd(async_direct); + if (rc) { + CAM_ERR(CAM_ICP, "hfi write failed rc %d", rc); + goto end; + } + + CAM_DBG(CAM_ICP, "Sent FW %s cmd", + (map_unmap == true) ? "Map" : "Unmap"); + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_hfi_queue_dump(); + } + +end: + kfree(map_cmd); + kfree(async_direct); + return rc; +} + static int cam_icp_packet_generic_blob_handler(void *user_data, uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) { struct cam_icp_clk_bw_request *soc_req; struct cam_icp_clk_bw_request *clk_info; + struct cam_cmd_mem_regions *cmd_mem_regions; struct icp_cmd_generic_blob *blob; struct cam_icp_hw_ctx_data *ctx_data; uint32_t index; size_t io_buf_size; int rc = 0; - uint64_t pResource; + uintptr_t pResource; if (!blob_data || (blob_size == 0)) { CAM_ERR(CAM_ICP, "Invalid blob info %pK %d", blob_data, @@ -3491,6 +3684,40 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, *blob->io_buf_addr); break; + case CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_MAP: + cmd_mem_regions = + (struct cam_cmd_mem_regions *)blob_data; + if (cmd_mem_regions->num_regions <= 0) { + rc = -EINVAL; + CAM_ERR(CAM_ICP, + "Invalid number of regions for FW map %u", + cmd_mem_regions->num_regions); + } else { + CAM_DBG(CAM_ICP, + "Processing blob for mapping %u regions", + cmd_mem_regions->num_regions); + rc = cam_icp_process_stream_settings(ctx_data, + cmd_mem_regions, true); + } + break; + + case CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_UNMAP: + cmd_mem_regions = + (struct cam_cmd_mem_regions *)blob_data; + if (cmd_mem_regions->num_regions <= 0) { + rc = -EINVAL; + CAM_ERR(CAM_ICP, + "Invalid number of regions for FW unmap %u", + cmd_mem_regions->num_regions); + } else { + CAM_DBG(CAM_ICP, + "Processing blob for unmapping %u regions", + cmd_mem_regions->num_regions); + rc = cam_icp_process_stream_settings(ctx_data, + cmd_mem_regions, false); + } + break; + default: CAM_WARN(CAM_ICP, "Invalid blob type %d", blob_type); break; @@ -3546,7 +3773,7 @@ static int cam_icp_mgr_process_cfg_io_cmd( ioconfig_cmd->num_fw_handles = 1; ioconfig_cmd->fw_handles[0] = ctx_data->fw_handle; ioconfig_cmd->payload.indirect = io_config; - ioconfig_cmd->user_data1 = (uint64_t)ctx_data; + ioconfig_cmd->user_data1 = PTR_TO_U64(ctx_data); ioconfig_cmd->user_data2 = request_id; return 0; @@ -3651,9 +3878,11 @@ static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet, } CAM_INFO(CAM_ICP, - "pln %d w %d h %d size %d addr 0x%x offset 0x%x memh %x", + "pln %d w %d h %d s %u sh %u size %d addr 0x%x offset 0x%x memh %x", j, io_cfg[i].planes[j].width, io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + io_cfg[i].planes[j].slice_height, (int32_t)src_buf_size, (unsigned int)iova_addr, io_cfg[i].offsets[j], @@ -3665,6 +3894,52 @@ static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet, } } +static int cam_icp_mgr_config_stream_settings( + void *hw_mgr_priv, void *hw_stream_settings) +{ + int rc = 0; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct cam_packet *packet = NULL; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct icp_cmd_generic_blob cmd_generic_blob; + struct cam_hw_stream_setttings *config_args = + hw_stream_settings; + + if ((!hw_stream_settings) || + (!hw_mgr) || (!config_args->packet)) { + CAM_ERR(CAM_ICP, "Invalid input arguments"); + return -EINVAL; + } + + ctx_data = config_args->ctxt_to_hw_map; + mutex_lock(&ctx_data->ctx_mutex); + packet = config_args->packet; + + cmd_generic_blob.ctx = ctx_data; + cmd_generic_blob.frame_info_idx = -1; + cmd_generic_blob.io_buf_addr = NULL; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + if (!cmd_desc[0].length || + cmd_desc[0].meta_data != CAM_ICP_CMD_META_GENERIC_BLOB) { + CAM_ERR(CAM_ICP, "Invalid cmd buffer length/metadata"); + rc = -EINVAL; + goto end; + } + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[0], + cam_icp_packet_generic_blob_handler, &cmd_generic_blob); + if (rc) + CAM_ERR(CAM_ICP, "Failed in processing cmd mem blob %d", rc); + +end: + mutex_unlock(&ctx_data->ctx_mutex); + return rc; +} + static int cam_icp_mgr_prepare_hw_update(void *hw_mgr_priv, void *prepare_hw_update_args) { @@ -3745,11 +4020,12 @@ static int cam_icp_mgr_prepare_hw_update(void *hw_mgr_priv, fw_cmd_buf_iova_addr); prepare_args->num_hw_update_entries = 1; - prepare_args->hw_update_entries[0].addr = (uint64_t)hfi_cmd; + prepare_args->hw_update_entries[0].addr = (uintptr_t)hfi_cmd; prepare_args->priv = &ctx_data->hfi_frame_process.frame_info[idx]; CAM_DBG(CAM_ICP, "X: req id = %lld ctx_id = %u", packet->header.request_id, ctx_data->ctx_id); + cam_icp_mgr_put_cmd_buf(packet); mutex_unlock(&ctx_data->ctx_mutex); return rc; } @@ -3932,7 +4208,8 @@ static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) switch (flush_args->flush_type) { case CAM_FLUSH_TYPE_ALL: mutex_lock(&hw_mgr->hw_mgr_mutex); - if (!hw_mgr->recovery && flush_args->num_req_active) { + if (!atomic_read(&hw_mgr->recovery) + && flush_args->num_req_active) { mutex_unlock(&hw_mgr->hw_mgr_mutex); cam_icp_mgr_abort_handle(ctx_data); } else { @@ -3975,7 +4252,8 @@ static int cam_icp_mgr_release_hw(void *hw_mgr_priv, void *release_hw_args) return -EINVAL; } - CAM_DBG(CAM_ICP, "Enter recovery set %d", hw_mgr->recovery); + CAM_DBG(CAM_ICP, "Enter recovery set %d", + atomic_read(&hw_mgr->recovery)); ctx_data = release_hw->ctxt_to_hw_map; if (!ctx_data) { CAM_ERR(CAM_ICP, "NULL ctx data"); @@ -3997,12 +4275,10 @@ static int cam_icp_mgr_release_hw(void *hw_mgr_priv, void *release_hw_args) mutex_unlock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); mutex_lock(&hw_mgr->hw_mgr_mutex); - if (!hw_mgr->recovery) { + if (!atomic_read(&hw_mgr->recovery) && release_hw->active_req) { mutex_unlock(&hw_mgr->hw_mgr_mutex); - if (release_hw->active_req) { - cam_icp_mgr_abort_handle(ctx_data); - cam_icp_mgr_send_abort_status(ctx_data); - } + cam_icp_mgr_abort_handle(ctx_data); + cam_icp_mgr_send_abort_status(ctx_data); } else { mutex_unlock(&hw_mgr->hw_mgr_mutex); } @@ -4041,7 +4317,7 @@ static int cam_icp_mgr_create_handle(uint32_t dev_type, create_handle.size = sizeof(struct hfi_cmd_create_handle); create_handle.pkt_type = HFI_CMD_IPEBPS_CREATE_HANDLE; create_handle.handle_type = dev_type; - create_handle.user_data1 = (uint64_t)ctx_data; + create_handle.user_data1 = PTR_TO_U64(ctx_data); reinit_completion(&ctx_data->wait_complete); task_data = (struct hfi_cmd_work_data *)task->payload; task_data->data = (void *)&create_handle; @@ -4086,7 +4362,7 @@ static int cam_icp_mgr_send_ping(struct cam_icp_hw_ctx_data *ctx_data) ping_pkt.size = sizeof(struct hfi_cmd_ping_pkt); ping_pkt.pkt_type = HFI_CMD_SYS_PING; - ping_pkt.user_data = (uint64_t)ctx_data; + ping_pkt.user_data = PTR_TO_U64(ctx_data); init_completion(&ctx_data->wait_complete); task_data = (struct hfi_cmd_work_data *)task->payload; task_data->data = (void *)&ping_pkt; @@ -4204,6 +4480,7 @@ static int cam_icp_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) struct cam_icp_hw_ctx_data *ctx_data = NULL; struct cam_hw_acquire_args *args = acquire_hw_args; struct cam_icp_acquire_dev_info *icp_dev_acquire_info; + struct cam_cmd_mem_regions cmd_mem_region; if ((!hw_mgr_priv) || (!acquire_hw_args)) { CAM_ERR(CAM_ICP, "Invalid params: %pK %pK", hw_mgr_priv, @@ -4289,12 +4566,36 @@ static int cam_icp_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) goto create_handle_failed; } + cmd_mem_region.num_regions = 1; + cmd_mem_region.map_info_array[0].mem_handle = + icp_dev_acquire_info->io_config_cmd_handle; + cmd_mem_region.map_info_array[0].offset = 0; + cmd_mem_region.map_info_array[0].size = + icp_dev_acquire_info->io_config_cmd_size; + cmd_mem_region.map_info_array[0].flags = 0; + + rc = cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, true); + if (rc) { + CAM_ERR(CAM_ICP, + "sending config io mapping failed rc %d", rc); + goto send_map_info_failed; + } + rc = cam_icp_mgr_send_config_io(ctx_data, io_buf_addr); if (rc) { - CAM_ERR(CAM_ICP, "IO Config command failed"); + CAM_ERR(CAM_ICP, "IO Config command failed %d", rc); goto ioconfig_failed; } + rc = cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, false); + if (rc) { + CAM_ERR(CAM_ICP, + "sending config io unmapping failed %d", rc); + goto send_map_info_failed; + } + ctx_data->context_priv = args->context_data; args->ctxt_to_hw_map = ctx_data; @@ -4336,6 +4637,9 @@ static int cam_icp_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) kfree(ctx_data->hfi_frame_process.bitmap); ctx_data->hfi_frame_process.bitmap = NULL; ioconfig_failed: + cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, false); +send_map_info_failed: cam_icp_mgr_destroy_handle(ctx_data); create_handle_failed: send_ping_failed: @@ -4368,7 +4672,7 @@ static int cam_icp_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) mutex_lock(&hw_mgr->hw_mgr_mutex); if (copy_from_user(&icp_hw_mgr.icp_caps, - (void __user *)query_cap->caps_handle, + u64_to_user_ptr(query_cap->caps_handle), sizeof(struct cam_icp_query_cap_cmd))) { CAM_ERR(CAM_ICP, "copy_from_user failed"); rc = -EFAULT; @@ -4382,7 +4686,7 @@ static int cam_icp_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) icp_hw_mgr.icp_caps.dev_iommu_handle.non_secure = hw_mgr->iommu_hdl; icp_hw_mgr.icp_caps.dev_iommu_handle.secure = hw_mgr->iommu_sec_hdl; - if (copy_to_user((void __user *)query_cap->caps_handle, + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), &icp_hw_mgr.icp_caps, sizeof(struct cam_icp_query_cap_cmd))) { CAM_ERR(CAM_ICP, "copy_to_user failed"); rc = -EFAULT; @@ -4438,6 +4742,12 @@ static int cam_icp_mgr_alloc_devs(struct device_node *of_node) goto num_bps_failed; } + icp_hw_mgr.ipe_bps_pc_flag = of_property_read_bool(of_node, + "ipe_bps_pc_en"); + + icp_hw_mgr.icp_pc_flag = of_property_read_bool(of_node, + "icp_pc_en"); + return 0; num_bps_failed: kfree(icp_hw_mgr.devices[CAM_ICP_DEV_IPE]); @@ -4574,9 +4884,6 @@ static int cam_icp_mgr_create_wq(void) if (rc) goto debugfs_create_failed; - icp_hw_mgr.icp_pc_flag = true; - icp_hw_mgr.ipe_bps_pc_flag = true; - for (i = 0; i < ICP_WORKQ_NUM_TASK; i++) icp_hw_mgr.msg_work->task.pool[i].payload = &icp_hw_mgr.msg_work_data[i]; @@ -4653,6 +4960,8 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, hw_mgr_intf->hw_acquire = cam_icp_mgr_acquire_hw; hw_mgr_intf->hw_release = cam_icp_mgr_release_hw; hw_mgr_intf->hw_prepare_update = cam_icp_mgr_prepare_hw_update; + hw_mgr_intf->hw_config_stream_settings = + cam_icp_mgr_config_stream_settings; hw_mgr_intf->hw_config = cam_icp_mgr_config_hw; hw_mgr_intf->hw_open = cam_icp_mgr_hw_open_u; hw_mgr_intf->hw_close = cam_icp_mgr_hw_close_u; diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h b/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h index 8a1dc0485276..15fc7a61fde7 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h @@ -53,7 +53,7 @@ #define ICP_CLK_HW_BPS 0x1 #define ICP_CLK_HW_MAX 0x2 -#define ICP_OVER_CLK_THRESHOLD 15 +#define ICP_OVER_CLK_THRESHOLD 5 #define CPAS_IPE0_BIT 0x1000 #define CPAS_IPE1_BIT 0x2000 @@ -128,11 +128,11 @@ struct clk_work_data { }; /** - * struct icp_frame_info - * @request_id: request id - * @io_config: the address of io config - * @hfi_cfg_io_cmd: command struct to be sent to hfi - */ + * struct icp_frame_info + * @request_id: request id + * @io_config: the address of io config + * @hfi_cfg_io_cmd: command struct to be sent to hfi + */ struct icp_frame_info { uint64_t request_id; uint64_t io_config; @@ -304,7 +304,6 @@ struct cam_icp_clk_info { * @ipe0_enable: Flag for IPE0 * @ipe1_enable: Flag for IPE1 * @bps_enable: Flag for BPS - * @core_info: 32 bit value , tells IPE0/1 and BPS * @a5_dev_intf : Device interface for A5 * @ipe0_dev_intf: Device interface for IPE0 * @ipe1_dev_intf: Device interface for IPE1 @@ -354,14 +353,13 @@ struct cam_icp_hw_mgr { bool ipe0_enable; bool ipe1_enable; bool bps_enable; - uint32_t core_info; struct cam_hw_intf *a5_dev_intf; struct cam_hw_intf *ipe0_dev_intf; struct cam_hw_intf *ipe1_dev_intf; struct cam_hw_intf *bps_dev_intf; bool ipe_clk_state; bool bps_clk_state; - bool recovery; + atomic_t recovery; }; static int cam_icp_mgr_hw_close(void *hw_priv, void *hw_close_args); diff --git a/drivers/media/platform/msm/ais/cam_icp/icp_hw/ipe_hw/ipe_core.c b/drivers/media/platform/msm/ais/cam_icp/icp_hw/ipe_hw/ipe_core.c index 21035c74acc7..142fcdc6017d 100644 --- a/drivers/media/platform/msm/ais/cam_icp/icp_hw/ipe_hw/ipe_core.c +++ b/drivers/media/platform/msm/ais/cam_icp/icp_hw/ipe_hw/ipe_core.c @@ -195,7 +195,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev) CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); if (pwr_ctrl & IPE_COLLAPSE_MASK) { - CAM_WARN(CAM_ICP, "IPE pwr_ctrl set(%x)", pwr_ctrl); + CAM_DBG(CAM_ICP, "IPE pwr_ctrl set(%x)", pwr_ctrl); cam_cpas_reg_write(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, 0); diff --git a/drivers/media/platform/msm/ais/cam_isp/Makefile b/drivers/media/platform/msm/ais/cam_isp/Makefile index b309f9397528..75aa37ec2fa6 100644 --- a/drivers/media/platform/msm/ais/cam_isp/Makefile +++ b/drivers/media/platform/msm/ais/cam_isp/Makefile @@ -4,6 +4,7 @@ ccflags-y += -Idrivers/media/platform/msm/ais/cam_req_mgr ccflags-y += -Idrivers/media/platform/msm/ais/cam_smmu/ ccflags-y += -Idrivers/media/platform/msm/ais/cam_sync ccflags-y += -Idrivers/media/platform/msm/ais/cam_utils +ccflags-y += -Idrivers/media/platform/msm/ais/cam_cdm/ obj-$(CONFIG_MSM_AIS) += isp_hw_mgr/ obj-$(CONFIG_MSM_AIS) += cam_isp_dev.o cam_isp_context.o diff --git a/drivers/media/platform/msm/ais/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/ais/cam_isp/cam_isp_context.c index 99ff87890b36..bb32107831a5 100644 --- a/drivers/media/platform/msm/ais/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/ais/cam_isp/cam_isp_context.c @@ -16,7 +16,6 @@ #include #include -#include "cam_isp_context.h" #include "cam_mem_mgr.h" #include "cam_sync_api.h" #include "cam_req_mgr_dev.h" @@ -24,6 +23,9 @@ #include "cam_debug_util.h" #include "cam_packet_util.h" #include "cam_context_utils.h" +#include "cam_cdm_util.h" +#include "cam_isp_context.h" +#include "cam_common_util.h" static const char isp_dev_name[] = "isp"; @@ -121,6 +123,43 @@ static void __cam_isp_ctx_dump_state_monitor_array( } } +static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) +{ + int i = 0, rc = 0; + size_t len = 0; + uint32_t *buf_addr; + uint32_t *buf_start, *buf_end; + + for (i = 0; i < req_isp->num_cfg; i++) { + rc = cam_packet_util_get_cmd_mem_addr( + req_isp->cfg[i].handle, &buf_addr, &len); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Failed to get_cmd_mem_addr, rc=%d", + rc); + } else { + buf_start = (uint32_t *)((uint8_t *) buf_addr + + req_isp->cfg[i].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + req_isp->cfg[i].len - 1); + if (len < (buf_end - buf_start + 1)) { + CAM_ERR(CAM_ISP, + "Invalid len %lld buf_start-end=%d", + len, (buf_end - buf_start + 1)); + if (cam_mem_put_cpu_buf(req_isp->cfg[i].handle)) + CAM_WARN(CAM_ISP, + "Failed to put cpu buf: 0x%x", + req_isp->cfg[i].handle); + continue; + } + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + if (cam_mem_put_cpu_buf(req_isp->cfg[i].handle)) + CAM_WARN(CAM_ISP, "Failed to put cpu buf: 0x%x", + req_isp->cfg[i].handle); + } + } +} + static int __cam_isp_ctx_enqueue_request_in_order( struct cam_context *ctx, struct cam_ctx_request *req) { @@ -216,6 +255,8 @@ static int __cam_isp_ctx_enqueue_init_request( req_isp_new->num_cfg); req_isp_old->num_cfg += req_isp_new->num_cfg; + req_old->request_id = req->request_id; + list_add_tail(&req->list, &ctx->free_req_list); } } else { @@ -974,8 +1015,11 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, uint32_t i = 0; bool found = 0; struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_to_report = NULL; + struct cam_ctx_request *req_to_dump = NULL; struct cam_ctx_request *req_temp; struct cam_isp_ctx_req *req_isp = NULL; + struct cam_isp_ctx_req *req_isp_to_report = NULL; struct cam_req_mgr_error_notify notify; uint64_t error_request_id; struct cam_hw_fence_map_entry *fence_map_out = NULL; @@ -992,45 +1036,98 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, notify.error = CRM_KMD_ERR_OVERFLOW; /* - * Need to check the active req - * move all of them to the pending request list - * Note this funciton need revisit! + * The error is likely caused by first request on the active list. + * If active list is empty check wait list (maybe error hit as soon + * as RUP and we handle error before RUP. */ - if (list_empty(&ctx->active_req_list)) { - CAM_ERR_RATE_LIMIT(CAM_ISP, + CAM_DBG(CAM_ISP, "handling error with no active request"); + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Error with no active/wait request"); + goto end; + } else { + req_to_dump = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + } } else { - list_for_each_entry_safe(req, req_temp, - &ctx->active_req_list, list) { - req_isp = (struct cam_isp_ctx_req *) req->req_priv; - if (!req_isp->bubble_report) { - for (i = 0; i < req_isp->num_fence_map_out; - i++) { - fence_map_out = - &req_isp->fence_map_out[i]; - CAM_ERR(CAM_ISP, "req %llu, Sync fd %x", + req_to_dump = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + } + + req_isp = (struct cam_isp_ctx_req *) req_to_dump->req_priv; + cam_isp_ctx_dump_req(req_isp); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_ERROR, req_to_dump->request_id); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (!req_isp->bubble_report) { + for (i = 0; i < req_isp->num_fence_map_out; i++) { + fence_map_out = + &req_isp->fence_map_out[i]; + CAM_ERR(CAM_ISP, "req %llu, Sync fd %x", req->request_id, req_isp->fence_map_out[i].sync_id); - if (req_isp->fence_map_out[i].sync_id - != -1) { - rc = cam_sync_signal( + if (req_isp->fence_map_out[i].sync_id != -1) { + rc = cam_sync_signal( fence_map_out->sync_id, CAM_SYNC_STATE_SIGNALED_ERROR); - fence_map_out->sync_id = - -1; - } + fence_map_out->sync_id = -1; } - list_del_init(&req->list); - list_add_tail(&req->list, &ctx->free_req_list); - ctx_isp->active_req_cnt--; - } else { - found = 1; - break; } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + ctx_isp->active_req_cnt--; + } else { + found = 1; + break; } } + if (found) + goto move_to_pending; + + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (!req_isp->bubble_report) { + for (i = 0; i < req_isp->num_fence_map_out; i++) { + fence_map_out = + &req_isp->fence_map_out[i]; + CAM_ERR(CAM_ISP, "req %llu, Sync fd %x", + req->request_id, + req_isp->fence_map_out[i].sync_id); + if (req_isp->fence_map_out[i].sync_id != -1) { + rc = cam_sync_signal( + fence_map_out->sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + fence_map_out->sync_id = -1; + } + } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + ctx_isp->active_req_cnt--; + } else { + found = 1; + break; + } + } + +move_to_pending: + /* + * If bubble recovery is enabled on any request we need to move that + * request and all the subsequent requests to the pending list. + * Note: + * We need to traverse the active list in reverse order and add + * to head of pending list. + * e.g. pending current state: 10, 11 | active current state: 8, 9 + * intermittent for loop iteration- pending: 9, 10, 11 | active: 8 + * final state - pending: 8, 9, 10, 11 | active: NULL + */ if (found) { list_for_each_entry_safe_reverse(req, req_temp, &ctx->active_req_list, list) { @@ -1039,8 +1136,16 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, list_add(&req->list, &ctx->pending_req_list); ctx_isp->active_req_cnt--; } + list_for_each_entry_safe_reverse(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + ctx_isp->active_req_cnt--; + } } +end: do { if (list_empty(&ctx->pending_req_list)) { error_request_id = ctx_isp->last_applied_req_id + 1; @@ -1052,8 +1157,11 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, req_isp = (struct cam_isp_ctx_req *) req->req_priv; error_request_id = ctx_isp->last_applied_req_id; - if (req_isp->bubble_report) + if (req_isp->bubble_report) { + req_to_report = req; + req_isp_to_report = req_to_report->req_priv; break; + } for (i = 0; i < req_isp->num_fence_map_out; i++) { if (req_isp->fence_map_out[i].sync_id != -1) @@ -1067,14 +1175,17 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, } while (req->request_id < ctx_isp->last_applied_req_id); - if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_err) { notify.link_hdl = ctx->link_hdl; notify.dev_hdl = ctx->dev_hdl; notify.req_id = error_request_id; - if (req_isp && req_isp->bubble_report) - notify.error = CRM_KMD_ERR_BUBBLE; + if (req_isp_to_report && req_isp_to_report->bubble_report) { + if (error_event_data->recovery_enabled) + notify.error = CRM_KMD_ERR_BUBBLE; + } else { + notify.error = CRM_KMD_ERR_FATAL; + } CAM_WARN(CAM_ISP, "Notify CRM: req %lld, frame %lld\n", error_request_id, ctx_isp->frame_id); @@ -1086,15 +1197,8 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, rc = -EFAULT; } - - list_del_init(&req->list); - list_add(&req->list, &ctx->pending_req_list); - /* might need to check if active list is empty */ - if (req != NULL) { - __cam_isp_ctx_update_state_monitor_array(ctx_isp, - CAM_ISP_STATE_CHANGE_TRIGGER_ERROR, req->request_id); - } CAM_DBG(CAM_ISP, "Exit"); + return rc; } @@ -1197,13 +1301,14 @@ static int __cam_isp_ctx_apply_req_in_activated_state( * */ ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + spin_lock_bh(&ctx->lock); req = list_first_entry(&ctx->pending_req_list, struct cam_ctx_request, list); spin_unlock_bh(&ctx->lock); /* - * Check whehter the request id is matching the tip, if not, this means + * Check whether the request id is matching the tip, if not, this means * we are in the middle of the error handling. Need to reject this apply */ if (req->request_id != apply->request_id) { @@ -1391,59 +1496,19 @@ static int __cam_isp_ctx_flush_req_in_top_state( struct cam_context *ctx, struct cam_req_mgr_flush_request *flush_req) { - struct cam_isp_context *ctx_isp = - (struct cam_isp_context *) ctx->ctx_priv; - struct cam_isp_stop_args stop_isp; - struct cam_hw_stop_args stop_args; - struct cam_isp_start_args start_isp; int rc = 0; + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + CAM_INFO(CAM_ISP, "Last request id to flush is %lld", + flush_req->req_id); + ctx->last_flush_req = flush_req->req_id; + } + CAM_DBG(CAM_ISP, "try to flush pending list"); spin_lock_bh(&ctx->lock); rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); spin_unlock_bh(&ctx->lock); - if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { - /* if active and wait list are empty, return */ - spin_lock_bh(&ctx->lock); - if ((list_empty(&ctx->wait_req_list)) && - (list_empty(&ctx->active_req_list))) { - spin_unlock_bh(&ctx->lock); - CAM_DBG(CAM_ISP, "active and wait list are empty"); - goto end; - } - spin_unlock_bh(&ctx->lock); - - /* Stop hw first before active list flush */ - stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx; - stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY; - stop_isp.stop_only = true; - stop_args.args = (void *)&stop_isp; - ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, - &stop_args); - - spin_lock_bh(&ctx->lock); - CAM_DBG(CAM_ISP, "try to flush wait list"); - rc = __cam_isp_ctx_flush_req(ctx, &ctx->wait_req_list, - flush_req); - CAM_DBG(CAM_ISP, "try to flush active list"); - rc = __cam_isp_ctx_flush_req(ctx, &ctx->active_req_list, - flush_req); - ctx_isp->active_req_cnt = 0; - spin_unlock_bh(&ctx->lock); - - /* Start hw */ - start_isp.hw_config.ctxt_to_hw_map = ctx_isp->hw_ctx; - start_isp.start_only = true; - start_isp.hw_config.priv = NULL; - - rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, - &start_isp); - } - -end: - CAM_DBG(CAM_ISP, "Flush request in top state %d", - ctx->state); return rc; } @@ -1974,9 +2039,8 @@ static struct cam_ctx_ops }, }; -/* top level state machine */ -static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, - struct cam_release_dev_cmd *cmd) +static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, + void *cmd) { int rc = 0; struct cam_hw_release_args rel_arg; @@ -1984,22 +2048,16 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, (struct cam_isp_context *) ctx->ctx_priv; struct cam_req_mgr_flush_request flush_req; - if (cmd && ctx_isp->hw_ctx && ctx_isp->split_acquire) { - CAM_ERR(CAM_ISP, "ctx expects release HW before release dev"); - return rc; - } - if (ctx_isp->hw_ctx) { rel_arg.ctxt_to_hw_map = ctx_isp->hw_ctx; ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &rel_arg); ctx_isp->hw_ctx = NULL; + } else { + CAM_ERR(CAM_ISP, "No hw resources acquired for this ctx"); } - ctx->session_hdl = -1; - ctx->dev_hdl = -1; - ctx->link_hdl = -1; - ctx->ctx_crm_intf = NULL; + ctx->last_flush_req = 0; ctx_isp->frame_id = 0; ctx_isp->active_req_cnt = 0; ctx_isp->reported_req_id = 0; @@ -2011,7 +2069,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, * But we still add some sanity check code here to help the debug */ if (!list_empty(&ctx->active_req_list)) - CAM_ERR(CAM_ISP, "Active list is not empty"); + CAM_WARN(CAM_ISP, "Active list is not empty"); /* Flush all the pending request list */ flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; @@ -2022,7 +2080,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, spin_lock_bh(&ctx->lock); rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, &flush_req); spin_unlock_bh(&ctx->lock); - ctx->state = CAM_CTX_AVAILABLE; + ctx->state = CAM_CTX_ACQUIRED; trace_cam_context_state("ISP", ctx); CAM_DBG(CAM_ISP, "Release device success[%u] next state %d", @@ -2030,8 +2088,9 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, return rc; } -static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, - void *cmd) +/* top level state machine */ +static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) { int rc = 0; struct cam_hw_release_args rel_arg; @@ -2039,15 +2098,23 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, (struct cam_isp_context *) ctx->ctx_priv; struct cam_req_mgr_flush_request flush_req; + if (cmd && ctx_isp->hw_ctx) { + CAM_ERR(CAM_ISP, "releasing hw"); + __cam_isp_ctx_release_hw_in_top_state(ctx, NULL); + } + if (ctx_isp->hw_ctx) { rel_arg.ctxt_to_hw_map = ctx_isp->hw_ctx; ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &rel_arg); ctx_isp->hw_ctx = NULL; - } else { - CAM_ERR(CAM_ISP, "No hw resources acquired for this ctx"); } + ctx->session_hdl = -1; + ctx->dev_hdl = -1; + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + ctx->last_flush_req = 0; ctx_isp->frame_id = 0; ctx_isp->active_req_cnt = 0; ctx_isp->reported_req_id = 0; @@ -2059,7 +2126,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, * But we still add some sanity check code here to help the debug */ if (!list_empty(&ctx->active_req_list)) - CAM_WARN(CAM_ISP, "Active list is not empty"); + CAM_ERR(CAM_ISP, "Active list is not empty"); /* Flush all the pending request list */ flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; @@ -2070,7 +2137,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, spin_lock_bh(&ctx->lock); rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, &flush_req); spin_unlock_bh(&ctx->lock); - ctx->state = CAM_CTX_ACQUIRED; + ctx->state = CAM_CTX_AVAILABLE; trace_cam_context_state("ISP", ctx); CAM_DBG(CAM_ISP, "Release device success[%u] next state %d", @@ -2084,7 +2151,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( int rc = 0, i; struct cam_ctx_request *req = NULL; struct cam_isp_ctx_req *req_isp; - uint64_t packet_addr; + uintptr_t packet_addr; struct cam_packet *packet; size_t len = 0; struct cam_hw_prepare_update_args cfg; @@ -2105,8 +2172,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( if (!req) { CAM_ERR(CAM_ISP, "No more request obj free"); - rc = -ENOMEM; - goto end; + return -ENOMEM; } req_isp = (struct cam_isp_ctx_req *) req->req_priv; @@ -2114,16 +2180,16 @@ static int __cam_isp_ctx_config_dev_in_top_state( /* for config dev, only memory handle is supported */ /* map packet from the memhandle */ rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, - (uint64_t *) &packet_addr, &len); + &packet_addr, &len); if (rc != 0) { CAM_ERR(CAM_ISP, "Can not get packet address"); rc = -EINVAL; goto free_req; } - packet = (struct cam_packet *) (packet_addr + cmd->offset); + packet = (struct cam_packet *)(packet_addr + (uint32_t)cmd->offset); CAM_DBG(CAM_ISP, "pack_handle %llx", cmd->packet_handle); - CAM_DBG(CAM_ISP, "packet address is 0x%llx", packet_addr); + CAM_DBG(CAM_ISP, "packet address is 0x%zx", packet_addr); CAM_DBG(CAM_ISP, "packet with length %zu, offset 0x%llx", len, cmd->offset); CAM_DBG(CAM_ISP, "Packet request id %lld", @@ -2131,6 +2197,15 @@ static int __cam_isp_ctx_config_dev_in_top_state( CAM_DBG(CAM_ISP, "Packet size 0x%x", packet->header.size); CAM_DBG(CAM_ISP, "packet op %d", packet->header.op_code); + if ((((packet->header.op_code + 1) & 0xF) == CAM_ISP_PACKET_UPDATE_DEV) + && (packet->header.request_id <= ctx->last_flush_req)) { + CAM_INFO(CAM_ISP, + "request %lld has been flushed, reject packet", + packet->header.request_id); + rc = -EINVAL; + goto free_cpu_buf; + } + /* preprocess the configuration */ memset(&cfg, 0, sizeof(cfg)); cfg.packet = packet; @@ -2151,7 +2226,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( if (rc != 0) { CAM_ERR(CAM_ISP, "Prepare config packet failed in HW layer"); rc = -EFAULT; - goto free_req; + goto free_cpu_buf; } req_isp->num_cfg = cfg.num_hw_update_entries; req_isp->num_fence_map_out = cfg.num_out_map_entries; @@ -2212,6 +2287,10 @@ static int __cam_isp_ctx_config_dev_in_top_state( if (rc) goto put_ref; + if (cam_mem_put_cpu_buf((int32_t) cmd->packet_handle)) + CAM_WARN(CAM_ISP, "Can not put packet address : 0x%x", + cmd->packet_handle); + CAM_DBG(CAM_REQ, "Preprocessing Config req_id %lld successful on ctx %u", req->request_id, ctx->ctx_id); @@ -2220,16 +2299,19 @@ static int __cam_isp_ctx_config_dev_in_top_state( put_ref: for (--i; i >= 0; i--) { - rc = cam_sync_put_obj_ref(req_isp->fence_map_out[i].sync_id); - if (rc) + if (cam_sync_put_obj_ref(req_isp->fence_map_out[i].sync_id)) CAM_ERR(CAM_CTXT, "Failed to put ref of fence %d", req_isp->fence_map_out[i].sync_id); } +free_cpu_buf: + if (cam_mem_put_cpu_buf((int32_t) cmd->packet_handle)) + CAM_WARN(CAM_ISP, "Can not put packet address: 0x%x", + cmd->packet_handle); free_req: spin_lock_bh(&ctx->lock); list_add_tail(&req->list, &ctx->free_req_list); spin_unlock_bh(&ctx->lock); -end: + return rc; } @@ -2286,7 +2368,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, CAM_DBG(CAM_ISP, "start copy %d resources from user", cmd->num_resources); - if (copy_from_user(isp_res, (void __user *)cmd->resource_hdl, + if (copy_from_user(isp_res, u64_to_user_ptr(cmd->resource_hdl), sizeof(*isp_res)*cmd->num_resources)) { rc = -EFAULT; goto free_res; @@ -2295,7 +2377,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, param.context_data = ctx; param.event_cb = ctx->irq_cb_intf; param.num_acq = cmd->num_resources; - param.acquire_info = (uint64_t) isp_res; + param.acquire_info = (uintptr_t) isp_res; /* call HW manager to reserve the resource */ rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, @@ -2777,6 +2859,12 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( CAM_DBG(CAM_ISP, "Stop device success next state %d on ctx %u", ctx->state, ctx->ctx_id); + + if (!stop_cmd) { + rc = __cam_isp_ctx_unlink_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_ISP, "Unlink failed rc=%d", rc); + } return rc; } @@ -2966,7 +3054,7 @@ static int __cam_isp_ctx_handle_irq_in_activated(void *context, struct cam_isp_context *ctx_isp = (struct cam_isp_context *)ctx->ctx_priv; - spin_lock_bh(&ctx->lock); + spin_lock(&ctx->lock); trace_cam_isp_activated_irq(ctx, ctx_isp->substate_activated, evt_id, __cam_isp_ctx_get_event_ts(evt_id, evt_data)); @@ -2981,9 +3069,10 @@ static int __cam_isp_ctx_handle_irq_in_activated(void *context, ctx_isp->substate_activated); __cam_isp_ctx_dump_state_monitor_array(ctx_isp); } + CAM_DBG(CAM_ISP, "Exit: State %d Substate %d", ctx->state, ctx_isp->substate_activated); - spin_unlock_bh(&ctx->lock); + spin_unlock(&ctx->lock); return rc; } @@ -3097,6 +3186,26 @@ static int cam_isp_context_dump_active_request(void *data, unsigned long iova, req->request_id, rc); } + CAM_INFO(CAM_ISP, "Iterating over wait_list of isp ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + hw_update_data = &req_isp->hw_update_data; + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_ISP, "req_id : %lld ", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &mem_found); + if (rc) + CAM_ERR(CAM_ISP, "Failed to dump pf info"); + + if (mem_found) + CAM_ERR(CAM_ISP, "Found page fault in req %lld %d", + req->request_id, rc); + } + return rc; } diff --git a/drivers/media/platform/msm/ais/cam_isp/cam_isp_dev.c b/drivers/media/platform/msm/ais/cam_isp/cam_isp_dev.c index fc960bfba0f2..d8b7a7b5e73e 100644 --- a/drivers/media/platform/msm/ais/cam_isp/cam_isp_dev.c +++ b/drivers/media/platform/msm/ais/cam_isp/cam_isp_dev.c @@ -166,6 +166,8 @@ static int cam_isp_dev_probe(struct platform_device *pdev) cam_smmu_set_client_page_fault_handler(iommu_hdl, cam_isp_dev_iommu_fault_handler, node); + mutex_init(&g_isp_dev.isp_mutex); + CAM_INFO(CAM_ISP, "Camera ISP probe complete"); return 0; diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 6e9627c7fc8c..2cd34b656f6d 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -29,6 +29,7 @@ #include "cam_debug_util.h" #include "cam_cpas_api.h" #include "cam_mem_mgr_api.h" +#include "cam_common_util.h" #define CAM_IFE_HW_ENTRIES_MAX 20 @@ -42,13 +43,14 @@ (CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON + 1) #define CAM_ISP_GENERIC_BLOB_TYPE_MAX \ - (CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG + 1) + (CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG + 1) static uint32_t blob_type_hw_cmd_map[CAM_ISP_GENERIC_BLOB_TYPE_MAX] = { CAM_ISP_HW_CMD_GET_HFR_UPDATE, CAM_ISP_HW_CMD_CLOCK_UPDATE, CAM_ISP_HW_CMD_BW_UPDATE, CAM_ISP_HW_CMD_UBWC_UPDATE, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, }; static struct cam_ife_hw_mgr g_ife_hw_mgr; @@ -96,7 +98,8 @@ static int cam_ife_mgr_get_hw_caps(void *hw_mgr_priv, CAM_DBG(CAM_ISP, "enter"); - if (copy_from_user(&query_isp, (void __user *)query->caps_handle, + if (copy_from_user(&query_isp, + u64_to_user_ptr(query->caps_handle), sizeof(struct cam_isp_query_cap_cmd))) { rc = -EFAULT; return rc; @@ -115,8 +118,8 @@ static int cam_ife_mgr_get_hw_caps(void *hw_mgr_priv, query_isp.dev_caps[i].hw_version.reserved = 0; } - if (copy_to_user((void __user *)query->caps_handle, &query_isp, - sizeof(struct cam_isp_query_cap_cmd))) + if (copy_to_user(u64_to_user_ptr(query->caps_handle), + &query_isp, sizeof(struct cam_isp_query_cap_cmd))) rc = -EFAULT; CAM_DBG(CAM_ISP, "exit rc :%d", rc); @@ -430,7 +433,7 @@ static int cam_ife_hw_mgr_free_hw_res( sizeof(struct cam_isp_resource_node)); if (rc) CAM_ERR(CAM_ISP, - "Release hw resrouce id %d failed", + "Release hw resource id %d failed", isp_hw_res->res_id); isp_hw_res->hw_res[i] = NULL; } else @@ -1751,9 +1754,18 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) goto free_res; } - in_port = memdup_user((void __user *)isp_resource[i].res_hdl, + in_port = memdup_user( + u64_to_user_ptr(isp_resource[i].res_hdl), isp_resource[i].length); if (!IS_ERR(in_port)) { + if (in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + in_port_length = sizeof(struct cam_isp_in_port_info) + (in_port->num_out_res - 1) * sizeof(struct cam_isp_out_port_info); @@ -2220,17 +2232,6 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) CAM_DBG(CAM_ISP, "Halting CSIDs"); - if (cam_cdm_stream_off(ctx->cdm_handle)) - CAM_ERR(CAM_ISP, "CDM stream off failed %d", - ctx->cdm_handle); - - CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); - - /* IFE mux in resources */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { - cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); - } - CAM_DBG(CAM_ISP, "Going to stop IFE Out"); /* IFE out resources */ @@ -2244,6 +2245,13 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) } } + CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); + + /* IFE mux in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + cam_tasklet_stop(ctx->common.tasklet_info); /* @@ -2275,7 +2283,7 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_cid, master_base_idx, csid_halt_type); - /* stop rest of the CIDs */ + /* stop rest of the CIDs */ for (i = 0; i < ctx->num_base; i++) { if (ctx->base[i].idx == master_base_idx) continue; @@ -2285,15 +2293,18 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) ctx->base[i].idx, csid_halt_type); } + cam_ife_mgr_pause_hw(ctx); + if (stop_isp->stop_only) goto end; + if (cam_cdm_stream_off(ctx->cdm_handle)) + CAM_ERR(CAM_ISP, "CDM stream off failed %d", ctx->cdm_handle); + cam_ife_hw_mgr_deinit_hw(ctx); CAM_DBG(CAM_ISP, "Stop success for ctx id:%d rc :%d", ctx->ctx_index, rc); -end: - mutex_lock(&g_ife_hw_mgr.ctx_mutex); if (!atomic_dec_return(&g_ife_hw_mgr.active_ctx_cnt)) { rc = cam_ife_notify_safe_lut_scm(CAM_IFE_SAFE_DISABLE); @@ -2305,6 +2316,7 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) } mutex_unlock(&g_ife_hw_mgr.ctx_mutex); +end: return rc; } @@ -2425,6 +2437,12 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) return -EPERM; } + if ((!ctx->init_done) && start_isp->start_only) { + CAM_ERR(CAM_ISP, "Invalid args init_done %d start_only %d", + ctx->init_done, start_isp->start_only); + return -EINVAL; + } + CAM_DBG(CAM_ISP, "Enter... ctx id:%d", ctx->ctx_index); @@ -2466,10 +2484,10 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) rc = cam_ife_hw_mgr_init_hw(ctx); if (rc) { CAM_ERR(CAM_ISP, "Init failed"); - goto err; + goto tasklet_stop; } -start_only: + ctx->init_done = true; mutex_lock(&g_ife_hw_mgr.ctx_mutex); if (!atomic_fetch_inc(&g_ife_hw_mgr.active_ctx_cnt)) { @@ -2477,7 +2495,8 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) if (rc) { CAM_ERR(CAM_ISP, "SAFE SCM call failed:Check TZ/HYP dependency"); - rc = -1; + rc = -EFAULT; + goto deinit_hw; } } mutex_unlock(&g_ife_hw_mgr.ctx_mutex); @@ -2487,20 +2506,19 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) if (rc) { CAM_ERR(CAM_ISP, "Can not start cdm (%d)", ctx->cdm_handle); - goto err; + goto safe_disable; } - if (!start_isp->start_only) { - /* Apply initial configuration */ - CAM_DBG(CAM_ISP, "Config HW"); - rc = cam_ife_mgr_config_hw(hw_mgr_priv, - &start_isp->hw_config); - if (rc) { - CAM_ERR(CAM_ISP, "Config HW failed"); - goto err; - } + /* Apply initial configuration */ + CAM_DBG(CAM_ISP, "Config HW"); + rc = cam_ife_mgr_config_hw(hw_mgr_priv, &start_isp->hw_config); + if (rc) { + CAM_ERR(CAM_ISP, "Config HW failed"); + goto cdm_streamoff; } +start_only: + CAM_DBG(CAM_ISP, "START IFE OUT ... in ctx id:%d", ctx->ctx_index); /* start the IFE out devices */ @@ -2550,7 +2568,6 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) } } - ctx->init_done = true; /* Start IFE root node: do nothing */ CAM_DBG(CAM_ISP, "Start success for ctx id:%d", ctx->ctx_index); @@ -2565,6 +2582,21 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) cam_ife_mgr_stop_hw(hw_mgr_priv, &stop_args); CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); return rc; + +cdm_streamoff: + cam_cdm_stream_off(ctx->cdm_handle); + +safe_disable: + cam_ife_notify_safe_lut_scm(CAM_IFE_SAFE_DISABLE); + +deinit_hw: + cam_ife_hw_mgr_deinit_hw(ctx); + ctx->init_done = false; + +tasklet_stop: + cam_tasklet_stop(ctx->common.tasklet_info); + + return rc; } static int cam_ife_mgr_read(void *hw_mgr_priv, void *read_args) @@ -2852,6 +2884,53 @@ static int cam_isp_blob_hfr_update( return rc; } +static int cam_isp_blob_csid_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_csid_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_csid_clock_update_args csid_clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_ISP, + "csid clk=%llu", clock_config->csid_clock); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + clk_rate = clock_config->csid_clock; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + csid_clock_upd_args.clk_rate = clk_rate; + CAM_DBG(CAM_ISP, "i= %d clk=%llu\n", + i, csid_clock_upd_args.clk_rate); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + blob_type_hw_cmd_map[blob_type], + &csid_clock_upd_args, + sizeof( + struct cam_ife_csid_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + static int cam_isp_blob_clock_update( uint32_t blob_type, struct cam_isp_generic_blob_info *blob_info, @@ -3038,6 +3117,16 @@ static int cam_isp_packet_generic_blob_handler(void *user_data, CAM_ERR(CAM_ISP, "UBWC Update Failed rc: %d", rc); } break; + case CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG: { + struct cam_isp_csid_clock_config *clock_config = + (struct cam_isp_csid_clock_config *)blob_data; + + rc = cam_isp_blob_csid_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; default: CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); break; @@ -3266,7 +3355,7 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == GET_FD_FROM_HANDLE(pf_buf_info)) { CAM_INFO(CAM_ISP, - "Found PF at port: %d mem %x fd: %x", + "Found PF at port: 0x%x mem 0x%x fd: 0x%x", io_cfg[i].resource_type, io_cfg[i].mem_handle[j], pf_buf_info); @@ -3274,7 +3363,7 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, *mem_found = true; } - CAM_INFO(CAM_ISP, "port: %d f: %u format: %d dir %d", + CAM_INFO(CAM_ISP, "port: 0x%x f: %u format: %d dir %d", io_cfg[i].resource_type, io_cfg[i].fence, io_cfg[i].format, @@ -3286,7 +3375,9 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], mmu_hdl, &iova_addr, &src_buf_size); if (rc < 0) { - CAM_ERR(CAM_ISP, "get src buf address fail"); + CAM_ERR(CAM_ISP, + "get src buf address fail mem_handle 0x%x", + io_cfg[i].mem_handle[j]); continue; } if (iova_addr >> 32) { @@ -3296,11 +3387,14 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, } CAM_INFO(CAM_ISP, - "pln %d w %d h %d size %d addr 0x%x offset 0x%x memh %x", + "pln %d w %d h %d s %u size 0x%x addr 0x%x end_addr 0x%x offset %x memh %x", j, io_cfg[i].planes[j].width, io_cfg[i].planes[j].height, - (int32_t)src_buf_size, + io_cfg[i].planes[j].plane_stride, + (unsigned int)src_buf_size, (unsigned int)iova_addr, + (unsigned int)iova_addr + + (unsigned int)src_buf_size, io_cfg[i].offsets[j], io_cfg[i].mem_handle[j]); } @@ -3388,17 +3482,25 @@ static int cam_ife_mgr_cmd_get_sof_timestamp( list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_csid, list) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (!hw_mgr_res->hw_res[i] || - (i == CAM_ISP_HW_SPLIT_RIGHT)) + if (!hw_mgr_res->hw_res[i]) continue; + /* * Get the SOF time stamp from left resource only. * Left resource is master for dual vfe case and * Rdi only context case left resource only hold * the RDI resource */ + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; if (hw_intf->hw_ops.process_cmd) { + /* + * Single VFE case, Get the time stamp from + * available one csid hw in the context + * Dual VFE case, get the time stamp from + * master(left) would be sufficient + */ + csid_get_time.node_res = hw_mgr_res->hw_res[i]; rc = hw_intf->hw_ops.process_cmd( @@ -3407,23 +3509,16 @@ static int cam_ife_mgr_cmd_get_sof_timestamp( &csid_get_time, sizeof( struct cam_csid_get_time_stamp_args)); - if (!rc) { + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { *time_stamp = csid_get_time.time_stamp_val; *boot_time_stamp = csid_get_time.boot_timestamp; } - /* - * Single VFE case, Get the time stamp from available - * one csid hw in the context - * Dual VFE case, get the time stamp from master(left) - * would be sufficient - */ - goto end; } } } -end: + if (rc) CAM_ERR(CAM_ISP, "Getting sof time stamp failed"); @@ -3562,19 +3657,18 @@ static int cam_ife_hw_mgr_do_error_recovery( * is associated with this context. if YES * a. It fills the other cores associated with this context.in * affected_core[] - * b. Return 0 i.e.SUCCESS + * b. Return 1 if ctx is affected, 0 otherwise */ static int cam_ife_hw_mgr_is_ctx_affected( struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx, uint32_t *affected_core, uint32_t size) { - - int32_t rc = -EPERM; + int32_t rc = 0; uint32_t i = 0, j = 0; uint32_t max_idx = ife_hwr_mgr_ctx->num_base; uint32_t ctx_affected_core_idx[CAM_IFE_HW_NUM_MAX] = {0}; - CAM_DBG(CAM_ISP, "Enter:max_idx = %d", max_idx); + CAM_DBG(CAM_ISP, "max_idx = %d", max_idx); if ((max_idx >= CAM_IFE_HW_NUM_MAX) || (size > CAM_IFE_HW_NUM_MAX)) { @@ -3584,78 +3678,71 @@ static int cam_ife_hw_mgr_is_ctx_affected( for (i = 0; i < max_idx; i++) { if (affected_core[ife_hwr_mgr_ctx->base[i].idx]) - rc = 0; + rc = 1; else { ctx_affected_core_idx[j] = ife_hwr_mgr_ctx->base[i].idx; + CAM_DBG(CAM_ISP, "Add affected IFE %d for recovery", + ctx_affected_core_idx[j]); j = j + 1; } } - if (rc == 0) { + if (rc == 1) { while (j) { if (affected_core[ctx_affected_core_idx[j-1]] != 1) affected_core[ctx_affected_core_idx[j-1]] = 1; j = j - 1; } } - CAM_DBG(CAM_ISP, "Exit"); + return rc; } /* - * Loop through each context - * a. match core_idx - * b. For each context from ctx_list Stop the acquired resources - * c. Notify CRM with fatal error for the affected isp context - * d. For any dual VFE context, if copanion VFE is also serving - * other context it should also notify the CRM with fatal error + * For any dual VFE context, if non-affected VFE is also serving + * another context, then that context should also be notified with fatal error + * So Loop through each context and - + * a. match core_idx + * b. Notify CTX with fatal error */ -static int cam_ife_hw_mgr_process_overflow( - struct cam_ife_hw_mgr_ctx *curr_ife_hwr_mgr_ctx, - struct cam_isp_hw_error_event_data *error_event_data, - uint32_t curr_core_idx, - struct cam_hw_event_recovery_data *recovery_data) +static int cam_ife_hw_mgr_find_affected_ctx( + struct cam_ife_hw_mgr_ctx *curr_ife_hwr_mgr_ctx, + struct cam_isp_hw_error_event_data *error_event_data, + uint32_t curr_core_idx, + struct cam_hw_event_recovery_data *recovery_data) { uint32_t affected_core[CAM_IFE_HW_NUM_MAX] = {0}; struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx = NULL; - cam_hw_event_cb_func ife_hwr_irq_err_cb; - struct cam_ife_hw_mgr *ife_hwr_mgr = NULL; - struct cam_hw_stop_args stop_args; + cam_hw_event_cb_func notify_err_cb; + struct cam_ife_hw_mgr *ife_hwr_mgr = NULL; + enum cam_isp_hw_event_type event_type = CAM_ISP_HW_EVENT_ERROR; uint32_t i = 0; - CAM_DBG(CAM_ISP, "Enter"); - if (!recovery_data) { CAM_ERR(CAM_ISP, "recovery_data parameter is NULL"); return -EINVAL; } + recovery_data->no_of_context = 0; - /* affected_core is indexed by core_idx*/ affected_core[curr_core_idx] = 1; - ife_hwr_mgr = curr_ife_hwr_mgr_ctx->hw_mgr; list_for_each_entry(ife_hwr_mgr_ctx, &ife_hwr_mgr->used_ctx_list, list) { - /* * Check if current core_idx matches the HW associated * with this context */ - CAM_DBG(CAM_ISP, "Calling match Hw idx"); - if (cam_ife_hw_mgr_is_ctx_affected(ife_hwr_mgr_ctx, + if (!cam_ife_hw_mgr_is_ctx_affected(ife_hwr_mgr_ctx, affected_core, CAM_IFE_HW_NUM_MAX)) continue; atomic_set(&ife_hwr_mgr_ctx->overflow_pending, 1); + notify_err_cb = ife_hwr_mgr_ctx->common.event_cb[event_type]; - ife_hwr_irq_err_cb = - ife_hwr_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_ERROR]; - - stop_args.ctxt_to_hw_map = ife_hwr_mgr_ctx; - - /* Add affected_context in list of recovery data*/ - CAM_DBG(CAM_ISP, "Add new entry in affected_ctx_list"); + /* Add affected_context in list of recovery data */ + CAM_DBG(CAM_ISP, "Add affected ctx %d to list", + ife_hwr_mgr_ctx->ctx_index); if (recovery_data->no_of_context < CAM_CTX_MAX) recovery_data->affected_ctx[ recovery_data->no_of_context++] = @@ -3665,18 +3752,17 @@ static int cam_ife_hw_mgr_process_overflow( * In the call back function corresponding ISP context * will update CRM about fatal Error */ - - ife_hwr_irq_err_cb(ife_hwr_mgr_ctx->common.cb_priv, + notify_err_cb(ife_hwr_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_ERROR, error_event_data); - } + /* fill the affected_core in recovery data */ for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { recovery_data->affected_core[i] = affected_core[i]; CAM_DBG(CAM_ISP, "Vfe core %d is affected (%d)", i, recovery_data->affected_core[i]); } - CAM_DBG(CAM_ISP, "Exit"); + return 0; } @@ -3764,6 +3850,7 @@ static int cam_ife_hw_mgr_handle_camif_error( struct cam_vfe_top_irq_evt_payload *evt_payload; struct cam_isp_hw_error_event_data error_event_data = {0}; struct cam_hw_event_recovery_data recovery_data = {0}; + int rc = 0; ife_hwr_mgr_ctx = handler_priv; evt_payload = payload; @@ -3780,24 +3867,35 @@ static int cam_ife_hw_mgr_handle_camif_error( case CAM_ISP_HW_ERROR_P2I_ERROR: case CAM_ISP_HW_ERROR_VIOLATION: CAM_ERR(CAM_ISP, "Enter: error_type (%d)", error_status); + rc = -EFAULT; + + if (g_ife_hw_mgr.debug_cfg.enable_recovery) + error_event_data.recovery_enabled = true; error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; - cam_ife_hw_mgr_process_overflow(ife_hwr_mgr_ctx, + cam_ife_hw_mgr_find_affected_ctx(ife_hwr_mgr_ctx, &error_event_data, core_idx, &recovery_data); + if (!g_ife_hw_mgr.debug_cfg.enable_recovery) { + CAM_DBG(CAM_ISP, "recovery is not enabled"); + break; + } + + CAM_DBG(CAM_ISP, "IFE Mgr recovery is enabled"); /* Trigger for recovery */ recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; cam_ife_hw_mgr_do_error_recovery(&recovery_data); break; default: - CAM_DBG(CAM_ISP, "None error (%d)", error_status); + CAM_DBG(CAM_ISP, "No error (%d)", error_status); + break; } - return 0; + return rc; } /* @@ -4542,7 +4640,7 @@ static int cam_ife_hw_mgr_handle_buf_done_for_hw_res( * the affected context and any successful buf_done event is not * reported. */ - rc = cam_ife_hw_mgr_process_overflow(ife_hwr_mgr_ctx, + rc = cam_ife_hw_mgr_find_affected_ctx(ife_hwr_mgr_ctx, &error_event_data, evt_payload->core_index, &recovery_data); @@ -4569,8 +4667,8 @@ int cam_ife_mgr_do_tasklet_buf_done(void *handler_priv, evt_payload = evt_payload_priv; ife_hwr_mgr_ctx = (struct cam_ife_hw_mgr_ctx *)evt_payload->ctx; - CAM_DBG(CAM_ISP, "addr of evt_payload = %llx core index:0x%x", - (uint64_t)evt_payload, evt_payload->core_index); + CAM_DBG(CAM_ISP, "addr of evt_payload = %pK core index:0x%x", + evt_payload, evt_payload->core_index); CAM_DBG(CAM_ISP, "bus_irq_status_0: = %x", evt_payload->irq_reg_val[0]); CAM_DBG(CAM_ISP, "bus_irq_status_1: = %x", evt_payload->irq_reg_val[1]); CAM_DBG(CAM_ISP, "bus_irq_status_2: = %x", evt_payload->irq_reg_val[2]); @@ -4614,18 +4712,13 @@ int cam_ife_mgr_do_tasklet(void *handler_priv, void *evt_payload_priv) * for this context it needs to be handled remaining * interrupts are ignored. */ - if (g_ife_hw_mgr.debug_cfg.enable_recovery) { - CAM_DBG(CAM_ISP, "IFE Mgr recovery is enabled"); - rc = cam_ife_hw_mgr_handle_camif_error(ife_hwr_mgr_ctx, - evt_payload_priv); - } else { - CAM_DBG(CAM_ISP, "recovery is not enabled"); - rc = 0; - } + rc = cam_ife_hw_mgr_handle_camif_error(ife_hwr_mgr_ctx, + evt_payload_priv); if (rc) { - CAM_ERR(CAM_ISP, "Encountered Error (%d), ignoring other irqs", - rc); + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Encountered Error (%d), ignoring other irqs", + rc); goto put_payload; } diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index 807f9f602c22..f352144b809b 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -126,7 +126,8 @@ static int cam_isp_update_dual_config( CAM_ERR(CAM_UTIL, "failed update for i:%d > size_isp_out:%d", i, size_isp_out); - return -EINVAL; + rc = -EINVAL; + goto put_buf; } hw_mgr_res = &res_list_isp_out[i]; @@ -161,10 +162,15 @@ static int cam_isp_update_dual_config( &dual_isp_update_args, sizeof(struct cam_isp_hw_dual_isp_update_args)); if (rc) - return rc; + goto put_buf; } } +put_buf: + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_UTIL, "Failed to put buf: 0x%x", + cmd_desc->mem_handle); + return rc; } @@ -596,13 +602,6 @@ int cam_isp_add_io_buffers( return rc; } - if (io_addr[plane_id] >> 32) { - CAM_ERR(CAM_ISP, - "Invalid mapped address"); - rc = -EINVAL; - return rc; - } - /* need to update with offset */ io_addr[plane_id] += io_cfg[i].offsets[plane_id]; diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c index e418fa97081d..02344d790423 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c @@ -617,7 +617,7 @@ static void cam_irq_controller_th_processing( evt_handler->bottom_half, &bh_cmd); if (rc || !bh_cmd) { CAM_ERR_RATE_LIMIT(CAM_ISP, - "Can't get bh payload"); + "No payload, IRQ handling frozen"); continue; } } diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 1586216f2073..1a0f1ecab7b6 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -184,11 +184,13 @@ struct cam_isp_hw_eof_event_data { * * @error_type: Error type for the error event * @timestamp: Timestamp for the error event - * + * @recovery_enabled: Identifies if the context needs to recover & reapply + * this request */ struct cam_isp_hw_error_event_data { uint32_t error_type; uint64_t timestamp; + bool recovery_enabled; }; /* enum cam_isp_hw_mgr_command - Hardware manager command type */ diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 0cc456b74b78..3cca3c7bf1fe 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -45,6 +45,9 @@ /* Max number of sof irq's triggered in case of SOF freeze */ #define CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX 12 +/* Max CSI Rx irq error count threshold value */ +#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT 100 + static int cam_ife_csid_is_ipp_ppp_format_supported( uint32_t in_format) { @@ -435,6 +438,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) if (val != 0) CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", csid_hw->hw_intf->hw_idx, val); + csid_hw->error_irq_count = 0; return rc; } @@ -700,7 +704,7 @@ static int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, case CAM_IFE_PIX_PATH_RES_IPP: if (csid_hw->ipp_res.res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { - CAM_ERR(CAM_ISP, + CAM_DBG(CAM_ISP, "CSID:%d IPP resource not available", csid_hw->hw_intf->hw_idx); rc = -EINVAL; @@ -1004,8 +1008,8 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) { int rc = 0; const struct cam_ife_csid_reg_offset *csid_reg; - struct cam_hw_soc_info *soc_info; - uint32_t i, val; + struct cam_hw_soc_info *soc_info; + uint32_t i, val, clk_lvl; csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -1027,7 +1031,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", csid_hw->hw_intf->hw_idx); - rc = cam_ife_csid_enable_soc_resources(soc_info); + clk_lvl = cam_ife_csid_get_vote_level(soc_info, csid_hw->clk_rate); + CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl); + + rc = cam_ife_csid_enable_soc_resources(soc_info, clk_lvl); if (rc) { CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", csid_hw->hw_intf->hw_idx); @@ -1121,6 +1128,8 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) csid_hw->hw_intf->hw_idx); csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + csid_hw->error_irq_count = 0; + return rc; } @@ -2167,10 +2176,10 @@ static int cam_ife_csid_get_hbi_vbi( rdi_reg->csid_rdi_format_measure2_addr); } - CAM_INFO_RATE_LIMIT(CAM_ISP, "Resource %u HBI: 0x%x", res->res_id, - hbi); - CAM_INFO_RATE_LIMIT(CAM_ISP, "Resource %u VBI: 0x%x", res->res_id, - vbi); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "Device %s index %u Resource %u HBI: 0x%x VBI: 0x%x", + soc_info->dev_name, soc_info->index, + res->res_id, hbi, vbi); return 0; } @@ -2347,6 +2356,9 @@ static int cam_ife_csid_reserve(void *hw_priv, csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; reserv = (struct cam_csid_hw_reserve_resource_args *)reserve_args; + CAM_DBG(CAM_ISP, "res_type %d, CSID: %u", + reserv->res_type, csid_hw->hw_intf->hw_idx); + mutex_lock(&csid_hw->hw_info->hw_mutex); switch (reserv->res_type) { case CAM_ISP_RESOURCE_CID: @@ -2396,21 +2408,13 @@ static int cam_ife_csid_release(void *hw_priv, goto end; } - if (res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { - CAM_DBG(CAM_ISP, - "CSID:%d res type:%d Res %d in released state", + if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || + (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_WARN(CAM_ISP, + "CSID:%d res type:%d Res %d in state %d", csid_hw->hw_intf->hw_idx, - res->res_type, res->res_id); - goto end; - } - - if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && - res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { - CAM_DBG(CAM_ISP, - "CSID:%d res type:%d Res id:%d invalid state:%d", - csid_hw->hw_intf->hw_idx, - res->res_type, res->res_id, res->res_state); - rc = -EINVAL; + res->res_type, res->res_id, + res->res_state); goto end; } @@ -2790,18 +2794,28 @@ static int cam_ife_csid_sof_irq_debug( if (*((uint32_t *)cmd_args) == 1) sof_irq_enable = true; - val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + if (csid_hw->hw_info->hw_state == + CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_ISP, + "CSID powered down unable to %s sof irq", + (sof_irq_enable == true) ? "enable" : "disable"); + return 0; + } + + if (csid_reg->ipp_reg) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); - if (val) { - if (sof_irq_enable) - val |= CSID_PATH_INFO_INPUT_SOF; - else - val &= ~CSID_PATH_INFO_INPUT_SOF; + if (val) { + if (sof_irq_enable) + val |= CSID_PATH_INFO_INPUT_SOF; + else + val &= ~CSID_PATH_INFO_INPUT_SOF; - cam_io_w_mb(val, soc_info->reg_map[0].mem_base + - csid_reg->ipp_reg->csid_pxl_irq_mask_addr); - val = 0; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val = 0; + } } for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { @@ -2833,6 +2847,23 @@ static int cam_ife_csid_sof_irq_debug( return 0; } +static int cam_ife_csid_set_csid_clock( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_ife_csid_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_ife_csid_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_INFO(CAM_ISP, "CSID clock rate %llu", csid_hw->clk_rate); + + return 0; +} + static int cam_ife_csid_process_cmd(void *hw_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { @@ -2864,6 +2895,9 @@ static int cam_ife_csid_process_cmd(void *hw_priv, case CAM_IFE_CSID_SOF_IRQ_DEBUG: rc = cam_ife_csid_sof_irq_debug(csid_hw, cmd_args); break; + case CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE: + rc = cam_ife_csid_set_csid_clock(csid_hw, cmd_args); + break; default: CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", csid_hw->hw_intf->hw_idx, cmd_type); @@ -2979,10 +3013,12 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_EOT_RECEPTION", csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; } if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_SOT_RECEPTION", csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; } if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_PH_CRC) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC", @@ -3009,6 +3045,12 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->hw_intf->hw_idx); } + if (csid_hw->error_irq_count > + CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT) { + fatal_err_detected = true; + csid_hw->error_irq_count = 0; + } + if (fatal_err_detected) cam_ife_csid_halt_csi2(csid_hw); @@ -3342,6 +3384,8 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, } ife_csid_hw->csid_debug = 0; + ife_csid_hw->error_irq_count = 0; + return 0; err: if (rc) { diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h index d987f21965ae..43fd9b03132e 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h @@ -449,6 +449,8 @@ struct cam_ife_csid_path_cfg { * @sof_irq_triggered: Flag is set on receiving event to enable sof irq * incase of SOF freeze. * @irq_debug_cnt: Counter to track sof irq's when above flag is set. + * @error_irq_count Error IRQ count, if continuous error irq comes + * need to stop the CSID and mask interrupts. * */ struct cam_ife_csid_hw { @@ -474,6 +476,7 @@ struct cam_ife_csid_hw { uint64_t clk_rate; bool sof_irq_triggered; uint32_t irq_debug_cnt; + uint32_t error_irq_count; }; int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c index d3261f84e2f4..890dad3b66b2 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c @@ -116,7 +116,8 @@ int cam_ife_csid_deinit_soc_resources( return rc; } -int cam_ife_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info) +int cam_ife_csid_enable_soc_resources( + struct cam_hw_soc_info *soc_info, uint32_t clk_lvl) { int rc = 0; struct cam_csid_soc_private *soc_private; @@ -141,7 +142,7 @@ int cam_ife_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info) } rc = cam_soc_util_enable_platform_resource(soc_info, true, - CAM_SVS_VOTE, true); + clk_lvl, true); if (rc) { CAM_ERR(CAM_ISP, "enable platform failed"); goto stop_cpas; @@ -235,3 +236,23 @@ int cam_ife_csid_disable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, return rc; } +uint32_t cam_ife_csid_get_vote_level(struct cam_hw_soc_info *soc_info, + uint64_t clock_rate) +{ + int i = 0; + + if (!clock_rate) + return CAM_SVS_VOTE; + + for (i = 0; i < CAM_MAX_VOTE; i++) { + if (soc_info->clk_rate[i][soc_info->num_clk - 1] >= + clock_rate) { + CAM_DBG(CAM_ISP, + "Clock rate %lld, selected clock level %d", + clock_rate, i); + return i; + } + } + + return CAM_TURBO_VOTE; +} diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h index c83c191656a9..474f0852dbec 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h @@ -68,9 +68,11 @@ int cam_ife_csid_deinit_soc_resources(struct cam_hw_soc_info *soc_info); * @brief: csid soc resource enable function * * @soc_info: soc info structure pointer + * @clk_lvl: vote level to start with * */ -int cam_ife_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info); +int cam_ife_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); /** * cam_ife_csid_disable_soc_resources() @@ -109,6 +111,16 @@ int cam_ife_csid_enable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, int cam_ife_csid_disable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, uint32_t cpas_ife_base_offset); - +/** + * cam_ife_csid_get_vote_level() + * + * @brief: get the vote level from clock rate + * + * @soc_info: soc info structure pointer + * @clock_rate clock rate + * + */ +uint32_t cam_ife_csid_get_vote_level(struct cam_hw_soc_info *soc_info, + uint64_t clock_rate); #endif diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h index 5e35c47e85a7..58818fbecf67 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h @@ -171,4 +171,14 @@ enum cam_ife_csid_cmd_type { int cam_ife_csid_hw_init(struct cam_hw_intf **ife_csid_hw, uint32_t hw_idx); +/* + * struct cam_ife_csid_clock_update_args: + * + * @clk_rate: Clock rate requested + */ +struct cam_ife_csid_clock_update_args { + uint64_t clk_rate; +}; + + #endif /* _CAM_CSID_HW_INTF_H_ */ diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 6f5087d37825..b317f922cec5 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -98,6 +98,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_UBWC_UPDATE, CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, CAM_ISP_HW_CMD_MAX, }; diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index bab5f204b3ff..5e6bb2012fff 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -279,6 +279,13 @@ int cam_vfe_init_hw(void *hw_priv, void *init_hw_args, uint32_t arg_size) goto deinint_vfe_res; } + rc = core_info->vfe_top->hw_ops.init(core_info->vfe_top->top_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "Top HW init Failed rc=%d", rc); + goto deinint_vfe_res; + } + vfe_hw->hw_state = CAM_HW_STATE_POWER_UP; return rc; diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c index 12b7a03c6276..ba4849141ce8 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c @@ -26,6 +26,8 @@ static bool cam_vfe_cpas_cb(uint32_t client_handle, void *userdata, switch (irq_data->irq_type) { case CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR: case CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR: CAM_ERR_RATE_LIMIT(CAM_ISP, "IFE UBWC Encode error type=%d status=%x", irq_data->irq_type, diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c index 620349faef60..7ee9f000a8c0 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c @@ -1206,7 +1206,8 @@ static int cam_vfe_bus_start_wm(struct cam_isp_resource_node *wm_res) cam_io_w_mb(val, common_data->mem_base + ubwc_regs->mode_cfg_0); } else if ((camera_hw_version == CAM_CPAS_TITAN_175_V100) || - (camera_hw_version == CAM_CPAS_TITAN_175_V101)) { + (camera_hw_version == CAM_CPAS_TITAN_175_V101) || + (camera_hw_version == CAM_CPAS_TITAN_175_V120)) { struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *ubwc_regs; @@ -2543,7 +2544,7 @@ static void cam_vfe_bus_update_ubwc_meta_addr( CAM_ERR(CAM_ISP, "Failed to get HW version rc: %d", rc); goto end; } else if ((camera_hw_version < CAM_CPAS_TITAN_170_V100) || - (camera_hw_version > CAM_CPAS_TITAN_175_V101)) { + (camera_hw_version > CAM_CPAS_TITAN_175_V120)) { CAM_ERR(CAM_ISP, "Invalid HW version: %d", camera_hw_version); goto end; @@ -2561,6 +2562,7 @@ static void cam_vfe_bus_update_ubwc_meta_addr( break; case CAM_CPAS_TITAN_175_V100: case CAM_CPAS_TITAN_175_V101: + case CAM_CPAS_TITAN_175_V120: ubwc_3_regs = (struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *) regs; @@ -2644,10 +2646,10 @@ static int cam_vfe_bus_update_ubwc_3_regs( switch (wm_data->format) { case CAM_FORMAT_UBWC_TP10: - ubwc_bw_limit = 0x8 | BIT(0); + ubwc_bw_limit = (0x8 << 1) | BIT(0); break; case CAM_FORMAT_UBWC_NV12_4R: - ubwc_bw_limit = 0xB | BIT(0); + ubwc_bw_limit = (0xB << 1) | BIT(0); break; default: ubwc_bw_limit = 0; @@ -2786,6 +2788,7 @@ static int cam_vfe_bus_update_ubwc_regs( break; case CAM_CPAS_TITAN_175_V100: case CAM_CPAS_TITAN_175_V101: + case CAM_CPAS_TITAN_175_V120: rc = cam_vfe_bus_update_ubwc_3_regs( wm_data, reg_val_pair, i, j); break; @@ -2838,7 +2841,7 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { CAM_ERR(CAM_ISP, - "reg_val_pair %d exceeds the array limit %lu", + "reg_val_pair %d exceeds the array limit %zu", j, MAX_REG_VAL_PAIR_SIZE); return -ENOMEM; } @@ -2995,7 +2998,7 @@ static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { CAM_ERR(CAM_ISP, - "reg_val_pair %d exceeds the array limit %lu", + "reg_val_pair %d exceeds the array limit %zu", j, MAX_REG_VAL_PAIR_SIZE); return -ENOMEM; } @@ -3311,7 +3314,7 @@ static int cam_vfe_bus_deinit_hw(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) { struct cam_vfe_bus_ver2_priv *bus_priv = hw_priv; - int rc = 0; + int rc = 0, i; if (!bus_priv) { CAM_ERR(CAM_ISP, "Error: Invalid args"); @@ -3340,6 +3343,13 @@ static int cam_vfe_bus_deinit_hw(void *hw_priv, bus_priv->irq_handle = 0; } + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + list_add_tail(&bus_priv->common_data.evt_payload[i].list, + &bus_priv->common_data.free_payload_list); + } + return rc; } diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c index 64b77eb7ccb8..604f07619482 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c @@ -166,10 +166,7 @@ static int cam_vfe_camif_lite_resource_start( static int cam_vfe_camif_lite_resource_stop( struct cam_isp_resource_node *camif_lite_res) { - struct cam_vfe_mux_camif_lite_data *camif_lite_priv; - struct cam_vfe_camif_lite_ver2_reg *camif_lite_reg; int rc = 0; - uint32_t val = 0; if (!camif_lite_res) { CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); @@ -180,16 +177,6 @@ static int cam_vfe_camif_lite_resource_stop( (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) return 0; - camif_lite_priv = (struct cam_vfe_mux_camif_lite_data *) - camif_lite_res->res_priv; - camif_lite_reg = camif_lite_priv->camif_lite_reg; - - val = cam_io_r_mb(camif_lite_priv->mem_base + - camif_lite_priv->common_reg->core_cfg); - val &= (~(1 << camif_lite_priv->reg_data->dual_pd_path_sel_shift)); - cam_io_w_mb(val, camif_lite_priv->mem_base + - camif_lite_priv->common_reg->core_cfg); - if (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) camif_lite_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c index fc257ecaa604..8933326b47a1 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c @@ -285,6 +285,7 @@ static int cam_vfe_camif_resource_start( case CAM_CPAS_TITAN_170_V100: case CAM_CPAS_TITAN_170_V110: case CAM_CPAS_TITAN_170_V120: + case CAM_CPAS_TITAN_150_V100: cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg, rsrc_data->mem_base + rsrc_data->camif_reg->epoch_irq); @@ -378,6 +379,42 @@ static int cam_vfe_camif_reg_dump( return rc; } +static int cam_vfe_camif_reg_dump_bh(struct cam_vfe_mux_camif_data *camif_priv) +{ + uint32_t offset, val, wm_idx; + + for (offset = 0x0; offset < 0x1000; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val); + } + + for (offset = 0x2000; offset <= 0x20B8; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val); + } + + for (wm_idx = 0; wm_idx <= 23; wm_idx++) { + for (offset = 0x2200 + 0x100 * wm_idx; + offset < 0x2278 + 0x100 * wm_idx; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, + "offset 0x%x value 0x%x", offset, val); + } + } + + offset = 0x420; + val = cam_soc_util_r(camif_priv->soc_info, 1, offset); + CAM_INFO(CAM_ISP, "CAMNOC IFE02 MaxWR_LOW offset 0x%x value 0x%x", + offset, val); + + offset = 0x820; + val = cam_soc_util_r(camif_priv->soc_info, 1, offset); + CAM_INFO(CAM_ISP, "CAMNOC IFE13 MaxWR_LOW offset 0x%x value 0x%x", + offset, val); + + return 0; +} + static int cam_vfe_camif_resource_stop( struct cam_isp_resource_node *camif_res) { @@ -548,7 +585,7 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, if (irq_status1 & camif_priv->reg_data->error_irq_mask1) { CAM_DBG(CAM_ISP, "Received ERROR\n"); ret = CAM_ISP_HW_ERROR_OVERFLOW; - cam_vfe_camif_reg_dump(camif_node); + cam_vfe_camif_reg_dump_bh(camif_node->res_priv); } else { ret = CAM_ISP_HW_ERROR_NONE; } diff --git a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c index 4cd2b98d81dc..c4351a6858ad 100644 --- a/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c +++ b/drivers/media/platform/msm/ais/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -388,7 +388,11 @@ int cam_vfe_top_get_hw_caps(void *device_priv, int cam_vfe_top_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { - return -EPERM; + struct cam_vfe_top_ver2_priv *top_priv = device_priv; + + top_priv->hw_clk_rate = 0; + + return 0; } int cam_vfe_top_reset(void *device_priv, @@ -598,27 +602,6 @@ int cam_vfe_top_stop(void *device_priv, break; } } - - if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) { - rc = cam_vfe_top_set_hw_clk_rate(top_priv); - if (rc) { - CAM_ERR(CAM_ISP, - "set_hw_clk_rate failed, rc=%d", rc); - return rc; - } - - top_priv->hw_clk_rate = 0; - - rc = cam_vfe_top_set_axi_bw_vote(top_priv, true); - if (rc) { - CAM_ERR(CAM_ISP, - "set_axi_bw_vote failed, rc=%d", rc); - return rc; - } - } else { - CAM_ERR(CAM_ISP, "VFE HW not powered up"); - rc = -EPERM; - } } return rc; diff --git a/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 4c47b38d9705..66dc18dab185 100644 --- a/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -34,6 +34,7 @@ #include "cam_mem_mgr.h" #include "cam_cdm_intf_api.h" #include "cam_debug_util.h" +#include "cam_common_util.h" #define CAM_JPEG_HW_ENTRIES_MAX 20 #define CAM_JPEG_CHBASE 0 @@ -49,14 +50,15 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data); static int cam_jpeg_mgr_process_irq(void *priv, void *data) { int rc = 0; + int mem_hdl = 0; struct cam_jpeg_process_irq_work_data_t *task_data; struct cam_jpeg_hw_mgr *hw_mgr; int32_t i; struct cam_jpeg_hw_ctx_data *ctx_data = NULL; struct cam_hw_done_event_data buf_data; struct cam_jpeg_set_irq_cb irq_cb; - uint32_t dev_type = 0; - uint64_t kaddr; + uintptr_t dev_type = 0; + uintptr_t kaddr; uint32_t *cmd_buf_kaddr; size_t cmd_buf_len; struct cam_jpeg_config_inout_param_info *p_params; @@ -113,7 +115,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) rc = hw_mgr->devices[dev_type][0]->hw_ops.deinit( hw_mgr->devices[dev_type][0]->hw_priv, NULL, 0); if (rc) - CAM_ERR(CAM_JPEG, "Failed to Deinit %d HW", dev_type); + CAM_ERR(CAM_JPEG, "Failed to Deinit %lu HW", dev_type); } hw_mgr->device_in_use[dev_type][0] = false; @@ -133,7 +135,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) CAM_ERR(CAM_JPEG, "task_data is NULL"); return -EINVAL; } - wq_task_data->data = (void *)(uint64_t)dev_type; + wq_task_data->data = (void *)dev_type; wq_task_data->request_id = 0; wq_task_data->type = CAM_JPEG_WORKQ_TASK_CMD_TYPE; task->process_cb = cam_jpeg_mgr_process_cmd; @@ -144,9 +146,9 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) return rc; } - rc = cam_mem_get_cpu_buf( - p_cfg_req->hw_cfg_args.hw_update_entries[CAM_JPEG_PARAM].handle, - (uint64_t *)&kaddr, &cmd_buf_len); + mem_hdl = + p_cfg_req->hw_cfg_args.hw_update_entries[CAM_JPEG_PARAM].handle; + rc = cam_mem_get_cpu_buf(mem_hdl, &kaddr, &cmd_buf_len); if (rc) { CAM_ERR(CAM_JPEG, "unable to get info for cmd buf: %x %d", hw_mgr->iommu_hdl, rc); @@ -172,11 +174,14 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) p_cfg_req->hw_cfg_args.out_map_entries[i].resource_handle; } buf_data.request_id = - (uint64_t)p_cfg_req->hw_cfg_args.priv; + PTR_TO_U64(p_cfg_req->hw_cfg_args.priv); ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data); list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); + if (cam_mem_put_cpu_buf(mem_hdl)) + CAM_WARN(CAM_JPEG, "unable to put info for cmd buf: 0x%x", + mem_hdl); return rc; } @@ -257,12 +262,12 @@ static int cam_jpeg_insert_cdm_change_base( struct cam_jpeg_hw_ctx_data *ctx_data, struct cam_jpeg_hw_mgr *hw_mgr) { - int rc; + int rc = 0; uint32_t dev_type; struct cam_cdm_bl_request *cdm_cmd; uint32_t size; uint32_t mem_cam_base; - uint64_t iova_addr; + uintptr_t iova_addr; uint32_t *ch_base_iova_addr; size_t ch_base_len; @@ -314,7 +319,7 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) struct cam_cdm_bl_request *cdm_cmd; struct cam_hw_config_args *config_args = NULL; struct cam_jpeg_hw_ctx_data *ctx_data = NULL; - uint64_t request_id = 0; + uintptr_t request_id = 0; struct cam_jpeg_process_frame_work_data_t *task_data = (struct cam_jpeg_process_frame_work_data_t *)data; uint32_t dev_type; @@ -357,9 +362,9 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) config_args = (struct cam_hw_config_args *)&p_cfg_req->hw_cfg_args; request_id = task_data->request_id; - if (request_id != (uint64_t)config_args->priv) { - CAM_DBG(CAM_JPEG, "not a recent req %lld %lld", - request_id, (uint64_t)config_args->priv); + if (request_id != (uintptr_t)config_args->priv) { + CAM_DBG(CAM_JPEG, "not a recent req %zd %zd", + request_id, (uintptr_t)config_args->priv); } if (!config_args->num_hw_update_entries) { @@ -459,13 +464,13 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) hw_mgr->cdm_info[dev_type][0].cdm_handle, cdm_cmd); if (rc) { CAM_ERR(CAM_JPEG, "Failed to apply the configs %d", rc); - goto end_callcb; + goto rel_cpu_buf; } if (!hw_mgr->devices[dev_type][0]->hw_ops.start) { CAM_ERR(CAM_JPEG, "op start null "); rc = -EINVAL; - goto end_callcb; + goto rel_cpu_buf; } rc = hw_mgr->devices[dev_type][0]->hw_ops.start( hw_mgr->devices[dev_type][0]->hw_priv, @@ -473,12 +478,22 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) if (rc) { CAM_ERR(CAM_JPEG, "Failed to start hw %d", rc); - goto end_callcb; + goto rel_cpu_buf; } + if (cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle)) + CAM_WARN(CAM_JPEG, "unable to put info for cmd buf: 0x%x", + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; +rel_cpu_buf: + if (cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle)) + CAM_WARN(CAM_JPEG, "unable to put info for cmd buf: 0x%x", + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); end_callcb: mutex_unlock(&hw_mgr->hw_mgr_mutex); if (p_cfg_req) { @@ -489,10 +504,10 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) buf_data.resource_handle[i] = hw_cfg_args->out_map_entries[i].resource_handle; } - buf_data.request_id = (uint64_t)p_cfg_req->hw_cfg_args.priv; + buf_data.request_id = + (uintptr_t)p_cfg_req->hw_cfg_args.priv; ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data); } - end_unusedev: mutex_lock(&hw_mgr->hw_mgr_mutex); hw_mgr->device_in_use[p_cfg_req->dev_type][0] = false; @@ -509,7 +524,7 @@ static int cam_jpeg_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; struct cam_hw_config_args *config_args = config_hw_args; struct cam_jpeg_hw_ctx_data *ctx_data = NULL; - uint64_t request_id = 0; + uintptr_t request_id = 0; struct cam_hw_update_entry *hw_update_entries; struct crm_workq_task *task; struct cam_jpeg_process_frame_work_data_t *task_data; @@ -549,11 +564,11 @@ static int cam_jpeg_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) p_cfg_req->hw_cfg_args = *config_args; p_cfg_req->dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; - request_id = (uint64_t)config_args->priv; + request_id = (uintptr_t)config_args->priv; p_cfg_req->req_id = request_id; hw_update_entries = config_args->hw_update_entries; - CAM_DBG(CAM_JPEG, "ctx_data = %pK req_id = %lld %lld", - ctx_data, request_id, (uint64_t)config_args->priv); + CAM_DBG(CAM_JPEG, "ctx_data = %pK req_id = %lld %zd", + ctx_data, request_id, (uintptr_t)config_args->priv); task = cam_req_mgr_workq_get_task(g_jpeg_hw_mgr.work_process_frame); if (!task) { CAM_ERR(CAM_JPEG, "no empty task"); @@ -578,7 +593,7 @@ static int cam_jpeg_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) list_add_tail(&p_cfg_req->list, &hw_mgr->hw_config_req_list); mutex_unlock(&hw_mgr->hw_mgr_mutex); - task_data->data = (void *)(int64_t)p_cfg_req->dev_type; + task_data->data = (void *)(uintptr_t)p_cfg_req->dev_type; task_data->request_id = request_id; task_data->type = CAM_JPEG_WORKQ_TASK_CMD_TYPE; task->process_cb = cam_jpeg_mgr_process_cmd; @@ -790,7 +805,7 @@ static int cam_jpeg_mgr_prepare_hw_update(void *hw_mgr_priv, (uint32_t)cmd_desc[i].offset; } prepare_args->num_hw_update_entries = j; - prepare_args->priv = (void *)packet->header.request_id; + prepare_args->priv = (void *)(uintptr_t)packet->header.request_id; CAM_DBG(CAM_JPEG, "will wait on input sync sync_id %d", prepare_args->in_map_entries[0].sync_id); @@ -896,7 +911,7 @@ static int cam_jpeg_mgr_flush_req(void *hw_mgr_priv, struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; struct cam_jpeg_hw_cfg_req *cfg_req = NULL; struct cam_jpeg_hw_cfg_req *req_temp = NULL; - int64_t request_id = 0; + long request_id = 0; uint32_t dev_type; struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; bool b_req_found = false; @@ -911,13 +926,13 @@ static int cam_jpeg_mgr_flush_req(void *hw_mgr_priv, if (flush_args->num_req_pending) return 0; - request_id = (int64_t)flush_args->flush_req_active[0]; + request_id = (uintptr_t)flush_args->flush_req_active[0]; if (!flush_args->num_req_active) return 0; if (request_id <= 0) { - CAM_ERR(CAM_JPEG, "Invalid red id %lld", request_id); + CAM_ERR(CAM_JPEG, "Invalid red id %ld", request_id); return -EINVAL; } @@ -954,7 +969,7 @@ static int cam_jpeg_mgr_flush_req(void *hw_mgr_priv, } if (!b_req_found) { - CAM_ERR(CAM_JPEG, "req not found %lld", request_id); + CAM_ERR(CAM_JPEG, "req not found %ld", request_id); return -EINVAL; } @@ -1258,7 +1273,7 @@ static int cam_jpeg_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) mutex_lock(&hw_mgr->hw_mgr_mutex); - if (copy_to_user((void __user *)query_cap->caps_handle, + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), &g_jpeg_hw_mgr.jpeg_caps, sizeof(struct cam_jpeg_query_cap_cmd))) { CAM_ERR(CAM_JPEG, "copy_to_user failed"); diff --git a/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h b/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h index 5e1016725095..82022ec24a77 100644 --- a/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h +++ b/drivers/media/platform/msm/ais/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h @@ -38,7 +38,7 @@ struct cam_jpeg_process_frame_work_data_t { uint32_t type; void *data; - uint64_t request_id; + uintptr_t request_id; }; /** @@ -81,7 +81,7 @@ struct cam_jpeg_hw_cfg_req { struct list_head list; struct cam_hw_config_args hw_cfg_args; uint32_t dev_type; - int64_t req_id; + uintptr_t req_id; }; /** diff --git a/drivers/media/platform/msm/ais/cam_lrme/cam_lrme_context.c b/drivers/media/platform/msm/ais/cam_lrme/cam_lrme_context.c index 5dc87633991f..99a8fe1f8eca 100644 --- a/drivers/media/platform/msm/ais/cam_lrme/cam_lrme_context.c +++ b/drivers/media/platform/msm/ais/cam_lrme/cam_lrme_context.c @@ -22,7 +22,7 @@ static int __cam_lrme_ctx_acquire_dev_in_available(struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd) { int rc = 0; - uint64_t ctxt_to_hw_map = (uint64_t)ctx->ctxt_to_hw_map; + uintptr_t ctxt_to_hw_map = (uintptr_t)ctx->ctxt_to_hw_map; struct cam_lrme_context *lrme_ctx = ctx->ctx_priv; CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); diff --git a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c index 49d04d11bb43..0c236462b7f5 100644 --- a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +++ b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -188,12 +188,6 @@ static int cam_lrme_mgr_util_prepare_io_buffer(int32_t iommu_hdl, io_addr[plane] += io_cfg[i].offsets[plane]; - if (io_addr[plane] >> 32) { - CAM_ERR(CAM_LRME, "Invalid io addr for %d %d", - plane, rc); - return -ENOMEM; - } - CAM_DBG(CAM_LRME, "IO Address[%d][%d] : %llu", io_cfg[i].direction, plane, io_addr[plane]); } @@ -571,12 +565,13 @@ static int cam_lrme_mgr_get_caps(void *hw_mgr_priv, void *hw_get_caps_args) if (sizeof(struct cam_lrme_query_cap_cmd) != args->size) { CAM_ERR(CAM_LRME, - "sizeof(struct cam_query_cap_cmd) = %lu, args->size = %d", + "sizeof(struct cam_query_cap_cmd) = %zu, args->size = %d", sizeof(struct cam_query_cap_cmd), args->size); return -EFAULT; } - if (copy_to_user((void __user *)args->caps_handle, &(hw_mgr->lrme_caps), + if (copy_to_user(u64_to_user_ptr(args->caps_handle), + &(hw_mgr->lrme_caps), sizeof(struct cam_lrme_query_cap_cmd))) { CAM_ERR(CAM_LRME, "copy to user failed"); return -EFAULT; @@ -591,7 +586,7 @@ static int cam_lrme_mgr_hw_acquire(void *hw_mgr_priv, void *hw_acquire_args) struct cam_hw_acquire_args *args = (struct cam_hw_acquire_args *)hw_acquire_args; struct cam_lrme_acquire_args lrme_acquire_args; - uint64_t device_index; + uintptr_t device_index; if (!hw_mgr_priv || !args) { CAM_ERR(CAM_LRME, @@ -612,7 +607,7 @@ static int cam_lrme_mgr_hw_acquire(void *hw_mgr_priv, void *hw_acquire_args) CAM_DBG(CAM_LRME, "Get device id %llu", device_index); if (device_index >= hw_mgr->device_count) { - CAM_ERR(CAM_LRME, "Get wrong device id %llu", device_index); + CAM_ERR(CAM_LRME, "Get wrong device id %lu", device_index); return -EINVAL; } @@ -667,7 +662,7 @@ static int cam_lrme_mgr_hw_flush(void *hw_mgr_priv, void *hw_flush_args) } args = (struct cam_hw_flush_args *)hw_flush_args; - device_index = ((uint64_t)args->ctxt_to_hw_map & 0xF); + device_index = ((uintptr_t)args->ctxt_to_hw_map & 0xF); if (device_index >= hw_mgr->device_count) { CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); return -EPERM; diff --git a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h index b0e0cd1eba94..87419cf59e00 100644 --- a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h +++ b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h @@ -30,13 +30,13 @@ #define CAM_LRME_WORKQ_NUM_TASK 10 #define CAM_LRME_DECODE_DEVICE_INDEX(ctxt_to_hw_map) \ - ((uint64_t)ctxt_to_hw_map & 0xF) + ((uintptr_t)ctxt_to_hw_map & 0xF) #define CAM_LRME_DECODE_PRIORITY(ctxt_to_hw_map) \ - (((uint64_t)ctxt_to_hw_map & 0xF0) >> 4) + (((uintptr_t)ctxt_to_hw_map & 0xF0) >> 4) #define CAM_LRME_DECODE_CTX_INDEX(ctxt_to_hw_map) \ - ((uint64_t)ctxt_to_hw_map >> CAM_LRME_CTX_INDEX_SHIFT) + ((uint64_t)(uintptr_t)ctxt_to_hw_map >> CAM_LRME_CTX_INDEX_SHIFT) /** * enum cam_lrme_hw_mgr_ctx_priority diff --git a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c index 022e1a7fcf1e..fe82ca9a1262 100644 --- a/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c +++ b/drivers/media/platform/msm/ais/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c @@ -79,7 +79,9 @@ static void cam_lrme_hw_util_fill_fe_reg(struct cam_lrme_hw_io_buffer *io_buf, hw_info->bus_rd_reg.bus_client_reg[index].unpack_cfg_0, 0x0); else if (io_buf->io_cfg->format == CAM_FORMAT_Y_ONLY || - io_buf->io_cfg->format == CAM_FORMAT_PLAIN8) + io_buf->io_cfg->format == CAM_FORMAT_PLAIN8 || + io_buf->io_cfg->format == CAM_FORMAT_NV12 || + io_buf->io_cfg->format == CAM_FORMAT_NV21) cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, hw_info->bus_rd_reg.bus_client_reg[index].unpack_cfg_0, 0x1); @@ -126,7 +128,7 @@ static void cam_lrme_hw_util_fill_we_reg(struct cam_lrme_hw_io_buffer *io_buf, /* client stride */ cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, hw_info->bus_wr_reg.bus_client_reg[index].wr_stride, - io_buf->io_cfg->planes[0].meta_stride); + io_buf->io_cfg->planes[0].plane_stride); CAM_DBG(CAM_LRME, "plane_stride %d", io_buf->io_cfg->planes[0].plane_stride); } @@ -855,7 +857,8 @@ int cam_lrme_hw_stop(void *hw_priv, void *hw_stop_args, uint32_t arg_size) mutex_lock(&lrme_hw->hw_mutex); - if (lrme_hw->open_count == 0) { + if (lrme_hw->open_count == 0 || + lrme_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { mutex_unlock(&lrme_hw->hw_mutex); CAM_ERR(CAM_LRME, "Error Unbalanced stop"); return -EINVAL; @@ -884,17 +887,15 @@ int cam_lrme_hw_stop(void *hw_priv, void *hw_stop_args, uint32_t arg_size) } rc = cam_lrme_soc_disable_resources(lrme_hw); - if (rc) { + if (rc) CAM_ERR(CAM_LRME, "Failed in Disable SOC, rc=%d", rc); - goto unlock; - } lrme_hw->hw_state = CAM_HW_STATE_POWER_DOWN; if (lrme_core->state == CAM_LRME_CORE_STATE_IDLE) { lrme_core->state = CAM_LRME_CORE_STATE_INIT; } else { CAM_ERR(CAM_LRME, "HW in wrong state %d", lrme_core->state); - return -EINVAL; + rc = -EINVAL; } unlock: @@ -920,7 +921,7 @@ int cam_lrme_hw_submit_req(void *hw_priv, void *hw_submit_args, if (sizeof(struct cam_lrme_hw_submit_args) != arg_size) { CAM_ERR(CAM_LRME, - "size of args %lu, arg_size %d", + "size of args %zu, arg_size %d", sizeof(struct cam_lrme_hw_submit_args), arg_size); return -EINVAL; } @@ -1049,9 +1050,9 @@ int cam_lrme_hw_flush(void *hw_priv, void *hw_flush_args, uint32_t arg_size) if (lrme_core->state != CAM_LRME_CORE_STATE_PROCESSING && lrme_core->state != CAM_LRME_CORE_STATE_REQ_PENDING && - lrme_core->state == CAM_LRME_CORE_STATE_REQ_PROC_PEND) { + lrme_core->state != CAM_LRME_CORE_STATE_REQ_PROC_PEND) { mutex_unlock(&lrme_hw->hw_mutex); - CAM_DBG(CAM_LRME, "Stop not needed in %d state", + CAM_DBG(CAM_LRME, "Flush is not needed in %d state", lrme_core->state); return 0; } diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.c b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.c index 33e4db2eca2b..78937a75cecd 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.c @@ -26,8 +26,24 @@ static struct cam_mem_table tbl; +static int cam_mem_util_get_dma_dir(uint32_t flags) +{ + int rc = -EINVAL; + + if (flags & CAM_MEM_FLAG_HW_READ_ONLY) + rc = DMA_TO_DEVICE; + else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY) + rc = DMA_FROM_DEVICE; + else if (flags & CAM_MEM_FLAG_HW_READ_WRITE) + rc = DMA_BIDIRECTIONAL; + else if (flags & CAM_MEM_FLAG_PROTECTED_MODE) + rc = DMA_BIDIRECTIONAL; + + return rc; +} + static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf, - uint64_t *vaddr, + uintptr_t *vaddr, size_t *len) { int i, j, rc; @@ -39,7 +55,7 @@ static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf, */ rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL); if (rc) { - CAM_ERR(CAM_SMMU, "dma begin access failed rc=%d", rc); + CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); return rc; } @@ -75,7 +91,6 @@ static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf, dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL); return rc; } - static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf, uint64_t vaddr) { @@ -108,22 +123,6 @@ static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf, return rc; } -static int cam_mem_util_get_dma_dir(uint32_t flags) -{ - int rc = -EINVAL; - - if (flags & CAM_MEM_FLAG_HW_READ_ONLY) - rc = DMA_TO_DEVICE; - else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY) - rc = DMA_FROM_DEVICE; - else if (flags & CAM_MEM_FLAG_HW_READ_WRITE) - rc = DMA_BIDIRECTIONAL; - else if (flags & CAM_MEM_FLAG_PROTECTED_MODE) - rc = DMA_BIDIRECTIONAL; - - return rc; -} - int cam_mem_mgr_init(void) { int i; @@ -226,13 +225,11 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, } EXPORT_SYMBOL(cam_mem_get_io_buf); -int cam_mem_get_cpu_buf(int32_t buf_handle, uint64_t *vaddr_ptr, size_t *len) +int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) { int rc = 0; int idx; struct dma_buf *dmabuf = NULL; - uint64_t kvaddr = 0; - size_t klen = 0; if (!buf_handle || !vaddr_ptr || !len) return -EINVAL; @@ -244,45 +241,74 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uint64_t *vaddr_ptr, size_t *len) if (!tbl.bufq[idx].active) return -EPERM; - if (buf_handle != tbl.bufq[idx].buf_handle) { - rc = -EINVAL; - goto exit_func; - } + if (buf_handle != tbl.bufq[idx].buf_handle) + return -EINVAL; - if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) { - rc = -EINVAL; - goto exit_func; - } + if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) + return -EINVAL; - if (!tbl.bufq[idx].kmdvaddr) { - mutex_lock(&tbl.bufq[idx].q_lock); + if (tbl.bufq[idx].kmdvaddr) { dmabuf = tbl.bufq[idx].dma_buf; if (!dmabuf) { CAM_ERR(CAM_MEM, "Invalid DMA buffer pointer"); - rc = -EINVAL; - goto release_mutex; + return -EINVAL; } - - rc = cam_mem_util_map_cpu_va(dmabuf, - &kvaddr, &klen); - if (rc) - goto release_mutex; - - tbl.bufq[idx].kmdvaddr = kvaddr; - mutex_unlock(&tbl.bufq[idx].q_lock); + rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL); + if (rc) { + CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); + return rc; + } + } else { + return -EINVAL; } *vaddr_ptr = tbl.bufq[idx].kmdvaddr; *len = tbl.bufq[idx].len; return rc; +} +EXPORT_SYMBOL(cam_mem_get_cpu_buf); + +int cam_mem_put_cpu_buf(int32_t buf_handle) +{ + int rc = 0; + int idx; + struct dma_buf *dmabuf = NULL; + + if (!buf_handle) + return -EINVAL; + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) + return -EINVAL; + + if (!tbl.bufq[idx].active) + return -EPERM; + + if (buf_handle != tbl.bufq[idx].buf_handle) + return -EINVAL; + + dmabuf = tbl.bufq[idx].dma_buf; + if (!dmabuf) { + CAM_ERR(CAM_CRM, "Invalid DMA buffer pointer"); + return -EINVAL; + } + + if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) && + (tbl.bufq[idx].kmdvaddr)) { + rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL); + if (rc) { + CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); + return rc; + } + } else { + CAM_ERR(CAM_MEM, "Invalid buf flag"); + rc = -EINVAL; + } -release_mutex: - mutex_unlock(&tbl.bufq[idx].q_lock); -exit_func: return rc; } -EXPORT_SYMBOL(cam_mem_get_cpu_buf); +EXPORT_SYMBOL(cam_mem_put_cpu_buf); int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) { @@ -318,10 +344,10 @@ int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) if (dmabuf_flag & ION_FLAG_CACHED) { switch (cmd->mem_cache_ops) { case CAM_MEM_CLEAN_CACHE: - cache_dir = DMA_FROM_DEVICE; + cache_dir = DMA_TO_DEVICE; break; case CAM_MEM_INV_CACHE: - cache_dir = DMA_TO_DEVICE; + cache_dir = DMA_FROM_DEVICE; break; case CAM_MEM_CLEAN_INV_CACHE: cache_dir = DMA_BIDIRECTIONAL; @@ -338,7 +364,8 @@ int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) } rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf, - cache_dir); + (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); if (rc) { CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); goto end; @@ -423,7 +450,12 @@ static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd, uint32_t ion_flag = 0; int rc; - if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) { + if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) && + (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) { + heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID); + ion_flag |= + ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP; + } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) { heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID); ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA; } else { @@ -570,6 +602,8 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) int fd = -1; dma_addr_t hw_vaddr = 0; size_t len; + uintptr_t kvaddr = 0; + size_t klen; if (!cmd) { CAM_ERR(CAM_MEM, " Invalid argument"); @@ -605,7 +639,7 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) || (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) { - enum cam_smmu_region_id region = CAM_SMMU_REGION_INVALID; + enum cam_smmu_region_id region; if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) region = CAM_SMMU_REGION_IO; @@ -614,6 +648,9 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) region = CAM_SMMU_REGION_SHARED; + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) + region = CAM_SMMU_REGION_SECHEAP; + rc = cam_mem_util_map_hw_va(cmd->flags, cmd->mmu_hdls, cmd->num_hdl, @@ -637,13 +674,18 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd); if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true); - tbl.bufq[idx].kmdvaddr = 0; - if (cmd->num_hdl > 0) - tbl.bufq[idx].vaddr = hw_vaddr; - else - tbl.bufq[idx].vaddr = 0; + if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) { + rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen); + if (rc) { + CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d", + dmabuf, rc); + goto map_kernel_fail; + } + } + tbl.bufq[idx].kmdvaddr = kvaddr; + tbl.bufq[idx].vaddr = hw_vaddr; tbl.bufq[idx].dma_buf = dmabuf; tbl.bufq[idx].len = cmd->len; tbl.bufq[idx].num_hdl = cmd->num_hdl; @@ -663,6 +705,8 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) return rc; +map_kernel_fail: + mutex_unlock(&tbl.bufq[idx].q_lock); map_hw_fail: cam_mem_put_slot(idx); slot_fail: @@ -771,11 +815,11 @@ static int cam_mem_util_unmap_hw_va(int32_t idx, int32_t *mmu_hdls; int num_hdls; int fd; - int rc = -EINVAL; + int rc = 0; if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { CAM_ERR(CAM_MEM, "Incorrect index"); - return rc; + return -EINVAL; } flags = tbl.bufq[idx].flags; @@ -920,13 +964,11 @@ static int cam_mem_util_unmap(int32_t idx, if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) { rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf, tbl.bufq[idx].kmdvaddr); - if (rc) { + if (rc) CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK, kmdvaddr=%pK", tbl.bufq[idx].dma_buf, tbl.bufq[idx].kmdvaddr); - return rc; - } } } @@ -940,9 +982,13 @@ static int cam_mem_util_unmap(int32_t idx, if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) || (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) || - (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) - rc = cam_mem_util_unmap_hw_va(idx, region, client); - + (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) { + if (cam_mem_util_unmap_hw_va(idx, region, client)) + CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK", + tbl.bufq[idx].dma_buf); + if (client == CAM_SMMU_MAPPING_KERNEL) + tbl.bufq[idx].dma_buf = NULL; + } mutex_lock(&tbl.bufq[idx].q_lock); tbl.bufq[idx].flags = 0; @@ -957,10 +1003,8 @@ static int cam_mem_util_unmap(int32_t idx, tbl.bufq[idx].is_imported, tbl.bufq[idx].dma_buf); - if (tbl.bufq[idx].dma_buf) { + if (tbl.bufq[idx].dma_buf) dma_buf_put(tbl.bufq[idx].dma_buf); - tbl.bufq[idx].dma_buf = NULL; - } tbl.bufq[idx].fd = -1; tbl.bufq[idx].dma_buf = NULL; @@ -1019,7 +1063,7 @@ int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, int rc = 0; uint32_t heap_id; int32_t ion_flag = 0; - uint64_t kvaddr; + uintptr_t kvaddr; dma_addr_t iova = 0; size_t request_len = 0; uint32_t mem_handle; diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.h b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.h index 4f3944579a69..4c75b0e043ec 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr.h @@ -54,7 +54,7 @@ struct cam_mem_buf_queue { size_t len; uint32_t flags; uint64_t vaddr; - uint64_t kmdvaddr; + uintptr_t kmdvaddr; bool active; bool is_imported; }; diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr_api.h b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr_api.h index 379ca9f2cd82..3587132abb19 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr_api.h +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_mem_mgr_api.h @@ -43,7 +43,7 @@ struct cam_mem_mgr_request_desc { * @region : Region to which allocated memory belongs */ struct cam_mem_mgr_memory_desc { - uint64_t kva; + uintptr_t kva; uint32_t iova; int32_t smmu_hdl; uint32_t mem_handle; @@ -83,8 +83,10 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp); */ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, uint64_t *iova_ptr, size_t *len_ptr); + /** - * @brief: Returns CPU address information about buffer + * @brief: This indicates begin of CPU access. + * Also returns CPU address information about DMA buffer * * @buf_handle: Handle for the buffer * @vaddr_ptr : pointer to kernel virtual address @@ -92,9 +94,18 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, * * @return Status of operation. Negative in case of error. Zero otherwise. */ -int cam_mem_get_cpu_buf(int32_t buf_handle, uint64_t *vaddr_ptr, +int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len); +/** + * @brief: This indicates end of CPU access + * + * @buf_handle: Handle for the buffer + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_put_cpu_buf(int32_t buf_handle); + static inline bool cam_mem_is_secure_buf(int32_t buf_handle) { return CAM_MEM_MGR_IS_SECURE_HDL(buf_handle); diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.c index a43865e64c3d..796cdbbd9371 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.c @@ -24,6 +24,32 @@ #include "cam_req_mgr_dev.h" static struct cam_req_mgr_core_device *g_crm_core_dev; +static struct cam_req_mgr_core_link g_links[MAXIMUM_LINKS_PER_SESSION]; + +void cam_req_mgr_core_link_reset(struct cam_req_mgr_core_link *link) +{ + link->link_hdl = 0; + link->num_devs = 0; + link->max_delay = CAM_PIPELINE_DELAY_0; + link->workq = NULL; + link->pd_mask = 0; + link->l_dev = NULL; + link->req.in_q = NULL; + link->req.l_tbl = NULL; + link->req.num_tbl = 0; + link->watchdog = NULL; + link->state = CAM_CRM_LINK_STATE_AVAILABLE; + link->parent = NULL; + link->subscribe_event = 0; + link->trigger_mask = 0; + link->sync_link = 0; + link->sof_counter = 0; + link->sync_self_ref = 0; + link->frame_skip_flag = false; + link->sync_link_sof_skip = false; + link->open_req_cnt = 0; + link->last_flush_id = 0; +} void cam_req_mgr_handle_core_shutdown(void) { @@ -403,10 +429,53 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, struct cam_req_mgr_connected_device *dev = NULL; struct cam_req_mgr_apply_request apply_req; struct cam_req_mgr_link_evt_data evt_data; + struct cam_req_mgr_tbl_slot *slot = NULL; apply_req.link_hdl = link->link_hdl; apply_req.report_if_bubble = 0; + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (!dev) + continue; + pd = dev->dev_info.p_delay; + if (pd >= CAM_PIPELINE_DELAY_MAX) { + CAM_WARN(CAM_CRM, "pd %d greater than max", + pd); + continue; + } + + idx = link->req.apply_data[pd].idx; + slot = &dev->pd_tbl->slot[idx]; + /* + * Just let flash go for this request and other + * device get restricted + */ + + if ((slot->skip_next_frame != true) || + (slot->dev_hdl != dev->dev_hdl)) + continue; + + if (!(dev->dev_info.trigger & trigger)) + continue; + + apply_req.dev_hdl = dev->dev_hdl; + apply_req.request_id = + link->req.apply_data[pd].req_id; + apply_req.trigger_point = trigger; + if (dev->ops && dev->ops->apply_req) { + rc = dev->ops->apply_req(&apply_req); + if (rc) + return rc; + CAM_DBG(CAM_REQ, + "SEND: link_hdl: %x pd: %d req_id %lld", + link->link_hdl, pd, apply_req.request_id); + slot->skip_next_frame = false; + slot->is_applied = true; + return -EAGAIN; + } + } + for (i = 0; i < link->num_devs; i++) { dev = &link->l_dev[i]; if (dev) { @@ -430,9 +499,16 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, apply_req.request_id = link->req.apply_data[pd].req_id; idx = link->req.apply_data[pd].idx; + slot = &dev->pd_tbl->slot[idx]; apply_req.report_if_bubble = in_q->slot[idx].recover; + if ((slot->dev_hdl == dev->dev_hdl) && + (slot->is_applied == true)) { + slot->is_applied = false; + continue; + } + trace_cam_req_mgr_apply_request(link, &apply_req, dev); apply_req.trigger_point = trigger; @@ -1289,18 +1365,22 @@ static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( return NULL; } - if (session->num_links >= MAX_LINKS_PER_SESSION) { + if (session->num_links >= MAXIMUM_LINKS_PER_SESSION) { CAM_ERR(CAM_CRM, "Reached max links %d per session limit %d", - session->num_links, MAX_LINKS_PER_SESSION); + session->num_links, MAXIMUM_LINKS_PER_SESSION); return NULL; } - - link = (struct cam_req_mgr_core_link *) - kzalloc(sizeof(struct cam_req_mgr_core_link), GFP_KERNEL); - if (!link) { - CAM_ERR(CAM_CRM, "failed to create link, no mem"); - return NULL; + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + if (!atomic_cmpxchg(&g_links[i].is_used, 0, 1)) { + link = &g_links[i]; + CAM_DBG(CAM_CRM, "alloc link index %d", i); + cam_req_mgr_core_link_reset(link); + break; + } } + if (i == MAXIMUM_LINKS_PER_SESSION) + return NULL; + in_q = (struct cam_req_mgr_req_queue *) kzalloc(sizeof(struct cam_req_mgr_req_queue), GFP_KERNEL); if (!in_q) { @@ -1308,8 +1388,6 @@ static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( kfree(link); return NULL; } - mutex_init(&link->lock); - spin_lock_init(&link->link_state_spin_lock); mutex_lock(&link->lock); link->state = CAM_CRM_LINK_STATE_AVAILABLE; @@ -1326,7 +1404,7 @@ static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( mutex_lock(&session->lock); /* Loop through and find a free index */ - for (i = 0; i < MAX_LINKS_PER_SESSION; i++) { + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { if (!session->links[i]) { CAM_DBG(CAM_CRM, "Free link index %d found, num_links=%d", @@ -1336,7 +1414,7 @@ static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( } } - if (i == MAX_LINKS_PER_SESSION) { + if (i == MAXIMUM_LINKS_PER_SESSION) { CAM_ERR(CAM_CRM, "Free link index not found"); goto error; } @@ -1364,9 +1442,12 @@ static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( */ static void __cam_req_mgr_free_link(struct cam_req_mgr_core_link *link) { + ptrdiff_t i; kfree(link->req.in_q); link->req.in_q = NULL; - kfree(link); + i = link - g_links; + CAM_DBG(CAM_CRM, "free link index %d", i); + atomic_set(&g_links[i].is_used, 0); } /** @@ -1397,7 +1478,7 @@ static void __cam_req_mgr_unreserve_link( return; } - for (i = 0; i < MAX_LINKS_PER_SESSION; i++) { + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { if (session->links[i] == link) session->links[i] = NULL; } @@ -1409,7 +1490,7 @@ static void __cam_req_mgr_unreserve_link( * of only having 2 links in a given session */ session->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; - for (i = 0; i < MAX_LINKS_PER_SESSION; i++) { + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { if (session->links[i]) session->links[i]->sync_link = NULL; } @@ -1494,6 +1575,9 @@ int cam_req_mgr_process_flush_req(void *priv, void *data) mutex_lock(&link->req.lock); if (flush_info->flush_type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + link->last_flush_id = flush_info->req_id; + CAM_INFO(CAM_CRM, "Last request id to flush is %lld", + flush_info->req_id); for (i = 0; i < in_q->num_slots; i++) { slot = &in_q->slot[i]; slot->req_id = -1; @@ -1658,10 +1742,15 @@ int cam_req_mgr_process_add_req(void *priv, void *data) } slot = &tbl->slot[idx]; - if (add_req->skip_before_applying > slot->inject_delay) { - slot->inject_delay = add_req->skip_before_applying; - CAM_DBG(CAM_CRM, "Req_id %llu injecting delay %u", - add_req->req_id, add_req->skip_before_applying); + slot->is_applied = false; + if ((add_req->skip_before_applying & 0xFF) > slot->inject_delay) { + slot->inject_delay = (add_req->skip_before_applying & 0xFF); + slot->dev_hdl = add_req->dev_hdl; + if (add_req->skip_before_applying & SKIP_NEXT_FRAME) + slot->skip_next_frame = true; + CAM_DBG(CAM_CRM, "Req_id %llu injecting delay %llu", + add_req->req_id, + (add_req->skip_before_applying & 0xFF)); } if (slot->state != CRM_REQ_STATE_PENDING && @@ -2312,7 +2401,8 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) if (rc < 0) { CAM_ERR(CAM_CRM, "error destroying link hdl %x rc %d", link->link_hdl, rc); - } + } else + link->link_hdl = -1; mutex_unlock(&link->lock); return rc; @@ -2345,7 +2435,7 @@ int cam_req_mgr_destroy_session( ses_info->session_hdl, cam_session->num_links); - for (i = 0; i < MAX_LINKS_PER_SESSION; i++) { + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { link = cam_session->links[i]; if (!link) @@ -2422,6 +2512,7 @@ int cam_req_mgr_link(struct cam_req_mgr_link_info *link_info) goto link_hdl_fail; } link_info->link_hdl = link->link_hdl; + link->last_flush_id = 0; /* Allocate memory to hold data of all linked devs */ rc = __cam_req_mgr_create_subdevs(&link->l_dev, @@ -2468,7 +2559,7 @@ int cam_req_mgr_link(struct cam_req_mgr_link_info *link_info) __cam_req_mgr_destroy_subdev(link->l_dev); create_subdev_failed: cam_destroy_device_hdl(link->link_hdl); - link_info->link_hdl = 0; + link_info->link_hdl = -1; link_hdl_fail: mutex_unlock(&link->lock); __cam_req_mgr_unreserve_link(cam_session, link); @@ -2547,6 +2638,17 @@ int cam_req_mgr_schedule_request( goto end; } + if (sched_req->req_id <= link->last_flush_id) { + CAM_INFO(CAM_CRM, + "request %d is flushed, last_flush_id to flush %lld", + sched_req->req_id, link->last_flush_id); + rc = -EINVAL; + goto end; + } + + if (sched_req->req_id > link->last_flush_id) + link->last_flush_id = 0; + CAM_DBG(CAM_CRM, "link 0x%x req %lld, sync_mode %d", sched_req->link_hdl, sched_req->req_id, sched_req->sync_mode); @@ -2585,7 +2687,8 @@ int cam_req_mgr_sync_config( } if ((sync_info->num_links < 0) || - (sync_info->num_links > MAX_LINKS_PER_SESSION)) { + (sync_info->num_links > + MAX_LINKS_PER_SESSION)) { CAM_ERR(CAM_CRM, "Invalid num links %d", sync_info->num_links); return -EINVAL; } @@ -2734,6 +2837,13 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) goto end; } + if (control->num_links > MAX_LINKS_PER_SESSION) { + CAM_ERR(CAM_CRM, "Invalid number of links %d", + control->num_links); + rc = -EINVAL; + goto end; + } + mutex_lock(&g_crm_core_dev->crm_lock); for (i = 0; i < control->num_links; i++) { link = (struct cam_req_mgr_core_link *) @@ -2796,6 +2906,7 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) int cam_req_mgr_core_device_init(void) { + int i; CAM_DBG(CAM_CRM, "Enter g_crm_core_dev %pK", g_crm_core_dev); if (g_crm_core_dev) { @@ -2812,6 +2923,12 @@ int cam_req_mgr_core_device_init(void) mutex_init(&g_crm_core_dev->crm_lock); cam_req_mgr_debug_register(g_crm_core_dev); + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + mutex_init(&g_links[i].lock); + spin_lock_init(&g_links[i].link_state_spin_lock); + atomic_set(&g_links[i].is_used, 0); + cam_req_mgr_core_link_reset(&g_links[i]); + } return 0; } diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.h b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.h index 68ec09b1e89e..3bb051274e76 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_core.h @@ -34,6 +34,8 @@ #define SYNC_LINK_SOF_CNT_MAX_LMT 1 +#define MAXIMUM_LINKS_PER_SESSION 4 + /** * enum crm_workq_task_type * @codes: to identify which type of task is present @@ -166,16 +168,23 @@ struct cam_req_mgr_apply { /** * struct cam_req_mgr_tbl_slot - * @idx : slot index - * @req_ready_map : mask tracking which all devices have request ready - * @state : state machine for life cycle of a slot - * @inject_delay : insert extra bubbling for flash type of use cases + * @idx : slot index + * @req_ready_map : mask tracking which all devices have request ready + * @state : state machine for life cycle of a slot + * @inject_delay : insert extra bubbling for flash type of use cases + * @dev_hdl : stores the dev_hdl, who is having higher inject delay + * @skip_next_frame : flag to drop the frame after skip_before_apply frame + * @is_applied : flag to identify if request is already applied to + * device. */ struct cam_req_mgr_tbl_slot { int32_t idx; uint32_t req_ready_map; enum crm_req_state state; uint32_t inject_delay; + int32_t dev_hdl; + bool skip_next_frame; + bool is_applied; }; /** @@ -308,6 +317,8 @@ struct cam_req_mgr_connected_device { * frame in sync link as well. * @open_req_cnt : Counter to keep track of open requests that are yet * to be serviced in the kernel. + * @last_flush_id : Last request to flush + * @is_used : 1 if link is in use else 0 * */ struct cam_req_mgr_core_link { @@ -332,6 +343,8 @@ struct cam_req_mgr_core_link { bool frame_skip_flag; bool sync_link_sof_skip; int32_t open_req_cnt; + uint32_t last_flush_id; + atomic_t is_used; }; /** @@ -353,7 +366,7 @@ struct cam_req_mgr_core_link { struct cam_req_mgr_core_session { int32_t session_hdl; uint32_t num_links; - struct cam_req_mgr_core_link *links[MAX_LINKS_PER_SESSION]; + struct cam_req_mgr_core_link *links[MAXIMUM_LINKS_PER_SESSION]; struct list_head entry; struct mutex lock; int32_t force_err_recovery; diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_dev.c b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_dev.c index 1e6de6a4672c..5cf1d844f5e2 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_dev.c @@ -25,6 +25,7 @@ #include "cam_subdev.h" #include "cam_mem_mgr.h" #include "cam_debug_util.h" +#include "cam_common_util.h" #include #define CAM_REQ_MGR_EVENT_MAX 30 @@ -235,14 +236,15 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&ses_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_session_info))) { return -EFAULT; } rc = cam_req_mgr_create_session(&ses_info); if (!rc) - if (copy_to_user((void *)k_ioctl->handle, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), &ses_info, sizeof(struct cam_req_mgr_session_info))) rc = -EFAULT; @@ -256,7 +258,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&ses_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_session_info))) { return -EFAULT; } @@ -272,14 +274,15 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&link_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_link_info))) { return -EFAULT; } rc = cam_req_mgr_link(&link_info); if (!rc) - if (copy_to_user((void *)k_ioctl->handle, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), &link_info, sizeof(struct cam_req_mgr_link_info))) rc = -EFAULT; @@ -293,7 +296,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&unlink_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_unlink_info))) { return -EFAULT; } @@ -309,7 +312,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&sched_req, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_sched_request))) { return -EFAULT; } @@ -325,7 +328,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&flush_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_flush_info))) { return -EFAULT; } @@ -341,7 +344,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&sync_info, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_sync_mode))) { return -EFAULT; } @@ -356,7 +359,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&cmd, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_mem_mgr_alloc_cmd))) { rc = -EFAULT; break; @@ -364,7 +367,8 @@ static long cam_private_ioctl(struct file *file, void *fh, rc = cam_mem_mgr_alloc_and_map(&cmd); if (!rc) - if (copy_to_user((void *)k_ioctl->handle, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), &cmd, sizeof(struct cam_mem_mgr_alloc_cmd))) { rc = -EFAULT; break; @@ -378,7 +382,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&cmd, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_mem_mgr_map_cmd))) { rc = -EFAULT; break; @@ -386,7 +390,8 @@ static long cam_private_ioctl(struct file *file, void *fh, rc = cam_mem_mgr_map(&cmd); if (!rc) - if (copy_to_user((void *)k_ioctl->handle, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), &cmd, sizeof(struct cam_mem_mgr_map_cmd))) { rc = -EFAULT; break; @@ -400,7 +405,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&cmd, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_mem_mgr_release_cmd))) { rc = -EFAULT; break; @@ -416,7 +421,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&cmd, - (void *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_mem_cache_ops_cmd))) { rc = -EFAULT; break; @@ -434,7 +439,7 @@ static long cam_private_ioctl(struct file *file, void *fh, return -EINVAL; if (copy_from_user(&cmd, - (void __user *)k_ioctl->handle, + u64_to_user_ptr(k_ioctl->handle), sizeof(struct cam_req_mgr_link_control))) { rc = -EFAULT; break; diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_interface.h b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_interface.h index c9e4ab2e8886..409e74961b45 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_interface.h +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_interface.h @@ -27,6 +27,8 @@ struct cam_req_mgr_apply_request; struct cam_req_mgr_flush_request; struct cam_req_mgr_link_evt_data; +#define SKIP_NEXT_FRAME 0x100 + /* Request Manager -- camera device driver interface */ /** * @brief: camera kernel drivers to cam req mgr communication diff --git a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_workq.c b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_workq.c index 746a6f178d56..aca3f2f48157 100644 --- a/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_workq.c +++ b/drivers/media/platform/msm/ais/cam_req_mgr/cam_req_mgr_workq.c @@ -228,7 +228,7 @@ int cam_req_mgr_workq_create(char *name, int32_t num_tasks, sizeof(struct crm_workq_task), GFP_KERNEL); if (!crm_workq->task.pool) { - CAM_WARN(CAM_CRM, "Insufficient memory %lu", + CAM_WARN(CAM_CRM, "Insufficient memory %zu", sizeof(struct crm_workq_task) * crm_workq->task.num_task); kfree(crm_workq); @@ -254,7 +254,6 @@ void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **crm_workq) { unsigned long flags = 0; struct workqueue_struct *job; - CAM_DBG(CAM_CRM, "destroy workque %pK", crm_workq); if (*crm_workq) { WORKQ_ACQUIRE_LOCK(*crm_workq, flags); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c index 31d9d35062bd..5a4af3e6ec3e 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -16,6 +16,7 @@ #include "cam_sensor_util.h" #include "cam_trace.h" #include "cam_res_mgr_api.h" +#include "cam_common_util.h" int32_t cam_actuator_construct_default_power_setting( struct cam_sensor_power_ctrl_t *power_info) @@ -414,7 +415,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, size_t len_of_buff = 0; uint32_t *offset = NULL; uint32_t *cmd_buf = NULL; - uint64_t generic_ptr; + uintptr_t generic_ptr; + uintptr_t generic_pkt_ptr; struct common_header *cmm_hdr = NULL; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; @@ -436,11 +438,12 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, power_info = &soc_private->power_info; ioctl_ctrl = (struct cam_control *)arg; - if (copy_from_user(&config, (void __user *) ioctl_ctrl->handle, + if (copy_from_user(&config, + u64_to_user_ptr(ioctl_ctrl->handle), sizeof(config))) return -EFAULT; rc = cam_mem_get_cpu_buf(config.packet_handle, - (uint64_t *)&generic_ptr, &len_of_buff); + &generic_pkt_ptr, &len_of_buff); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Error in converting command Handle %d", rc); @@ -451,11 +454,27 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "offset is out of bounds: offset: %lld len: %zu", config.offset, len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + + csl_packet = (struct cam_packet *) + (generic_pkt_ptr + (uint32_t)config.offset); + CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", + csl_packet->header.op_code); + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_ACTUATOR_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= a_ctrl->last_flush_req + && a_ctrl->last_flush_req != 0) { + CAM_DBG(CAM_ACTUATOR, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, a_ctrl->last_flush_req); return -EINVAL; } - csl_packet = (struct cam_packet *)(generic_ptr + config.offset); - CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", csl_packet->header.op_code); + if (csl_packet->header.request_id > a_ctrl->last_flush_req) + a_ctrl->last_flush_req = 0; switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_ACTUATOR_PACKET_OPCODE_INIT: @@ -469,15 +488,15 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (!total_cmd_buf_in_bytes) continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&generic_ptr, &len_of_buff); + &generic_ptr, &len_of_buff); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed to get cpu buf"); - return rc; + goto rel_pkt_buf; } cmd_buf = (uint32_t *)generic_ptr; if (!cmd_buf) { CAM_ERR(CAM_ACTUATOR, "invalid cmd buf"); - return -EINVAL; + goto rel_cmd_buf; } cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); cmm_hdr = (struct common_header *)cmd_buf; @@ -491,7 +510,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed to parse slave info: %d", rc); - return rc; + goto rel_cmd_buf; } break; case CAMERA_SENSOR_CMD_TYPE_PWR_UP: @@ -506,7 +525,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "Failed:parse power settings: %d", rc); - return rc; + goto rel_cmd_buf; } break; default: @@ -526,10 +545,14 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "Failed:parse init settings: %d", rc); - return rc; + goto rel_cmd_buf; } break; } + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_ACTUATOR, + "Failed to put cpu buf: 0x%x", + cmd_desc[i].mem_handle); } if (a_ctrl->cam_act_state == CAM_ACTUATOR_ACQUIRE) { @@ -537,7 +560,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (rc < 0) { CAM_ERR(CAM_ACTUATOR, " Actuator Power up failed"); - return rc; + goto rel_pkt_buf; } a_ctrl->cam_act_state = CAM_ACTUATOR_CONFIG; } @@ -546,7 +569,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, &a_ctrl->i2c_data.init_settings); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Cannot apply Init settings"); - return rc; + goto rel_pkt_buf; } /* Delete the request even if the apply is failed */ @@ -563,7 +586,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_WARN(CAM_ACTUATOR, "Not in right state to move lens: %d", a_ctrl->cam_act_state); - return rc; + goto rel_pkt_buf; } a_ctrl->setting_apply_state = ACT_APPLY_SETTINGS_NOW; @@ -583,7 +606,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Auto move lens parsing failed: %d", rc); - return rc; + goto rel_pkt_buf; } cam_actuator_update_req_mgr(a_ctrl, csl_packet); break; @@ -593,7 +616,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_WARN(CAM_ACTUATOR, "Not in right state to move lens: %d", a_ctrl->cam_act_state); - return rc; + goto rel_pkt_buf; } a_ctrl->setting_apply_state = ACT_APPLY_SETTINGS_LATER; @@ -614,7 +637,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Manual move lens parsing failed: %d", rc); - return rc; + goto rel_pkt_buf; } cam_actuator_update_req_mgr(a_ctrl, csl_packet); @@ -624,13 +647,32 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_WARN(CAM_ACTUATOR, "Received NOP packets in invalid state: %d", a_ctrl->cam_act_state); - return -EINVAL; + goto rel_pkt_buf; } - cam_actuator_update_req_mgr(a_ctrl, csl_packet); break; + default: + CAM_ERR(CAM_ACTUATOR, "Wrong Opcode: %d", + csl_packet->header.op_code & 0xFFFFFF); + rc = -EINVAL; + goto rel_pkt_buf; } + if (cam_mem_put_cpu_buf(config.packet_handle)) + CAM_WARN(CAM_ACTUATOR, "Fail to put cmd buffer: 0x%x", + config.packet_handle); + + return rc; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_ACTUATOR, "Fail to put cmd buffer: 0x%x", + cmd_desc[i].mem_handle); +rel_pkt_buf: + if (cam_mem_put_cpu_buf(config.packet_handle)) + CAM_WARN(CAM_ACTUATOR, "Fail to put cmd buffer: 0x%x", + config.packet_handle); + return rc; } @@ -709,7 +751,7 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, goto release_mutex; } rc = copy_from_user(&actuator_acq_dev, - (void __user *) cmd->handle, + u64_to_user_ptr(cmd->handle), sizeof(actuator_acq_dev)); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed Copying from user\n"); @@ -730,7 +772,8 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, CAM_DBG(CAM_ACTUATOR, "Device Handle: %d", actuator_acq_dev.device_handle); - if (copy_to_user((void __user *) cmd->handle, &actuator_acq_dev, + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &actuator_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { CAM_ERR(CAM_ACTUATOR, "Failed Copy to User"); rc = -EFAULT; @@ -764,6 +807,16 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, rc = -EINVAL; goto release_mutex; } + + if (a_ctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_ACTUATOR, + "Device [%d] still active on link 0x%x", + a_ctrl->cam_act_state, + a_ctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + rc = cam_destroy_device_hdl(a_ctrl->bridge_intf.device_hdl); if (rc < 0) CAM_ERR(CAM_ACTUATOR, "destroying the device hdl"); @@ -771,6 +824,7 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, a_ctrl->bridge_intf.link_hdl = -1; a_ctrl->bridge_intf.session_hdl = -1; a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; + a_ctrl->last_flush_req = 0; kfree(power_info->power_setting); kfree(power_info->power_down_setting); power_info->power_setting = NULL; @@ -783,7 +837,8 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, struct cam_actuator_query_cap actuator_cap = {0}; actuator_cap.slot_info = a_ctrl->soc_info.index; - if (copy_to_user((void __user *) cmd->handle, &actuator_cap, + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &actuator_cap, sizeof(struct cam_actuator_query_cap))) { CAM_ERR(CAM_ACTUATOR, "Failed Copy to User"); rc = -EFAULT; @@ -800,6 +855,7 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, goto release_mutex; } a_ctrl->cam_act_state = CAM_ACTUATOR_START; + a_ctrl->last_flush_req = 0; } break; case CAM_STOP_DEV: { @@ -825,6 +881,7 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, i2c_set->request_id, rc); } } + a_ctrl->last_flush_req = 0; a_ctrl->cam_act_state = CAM_ACTUATOR_CONFIG; } break; @@ -888,6 +945,13 @@ int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req) return -EINVAL; } + mutex_lock(&(a_ctrl->actuator_mutex)); + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + a_ctrl->last_flush_req = flush_req->req_id; + CAM_DBG(CAM_ACTUATOR, "last reqest to flush is %lld", + flush_req->req_id); + } + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { i2c_set = &(a_ctrl->i2c_data.per_frame[i]); @@ -896,9 +960,7 @@ int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req) continue; if (i2c_set->is_settings_valid == 1) { - mutex_lock(&(a_ctrl->actuator_mutex)); rc = delete_request(i2c_set); - mutex_unlock(&(a_ctrl->actuator_mutex)); if (rc < 0) CAM_ERR(CAM_ACTUATOR, "delete request: %lld rc: %d", @@ -917,5 +979,6 @@ int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req) CAM_DBG(CAM_ACTUATOR, "Flush request id:%lld not found in the pending list", flush_req->req_id); + mutex_unlock(&(a_ctrl->actuator_mutex)); return rc; } diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.c index 7d23f900199e..89e4df4234ce 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.c @@ -209,12 +209,14 @@ static int32_t cam_actuator_driver_i2c_probe(struct i2c_client *client, INIT_LIST_HEAD(&(a_ctrl->i2c_data.per_frame[i].list_head)); a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; a_ctrl->bridge_intf.ops.get_dev_info = cam_actuator_publish_dev_info; a_ctrl->bridge_intf.ops.link_setup = cam_actuator_establish_link; a_ctrl->bridge_intf.ops.apply_req = cam_actuator_apply_request; + a_ctrl->last_flush_req = 0; v4l2_set_subdevdata(&(a_ctrl->v4l2_dev_str.sd), a_ctrl); @@ -363,6 +365,7 @@ static int32_t cam_actuator_driver_platform_probe( goto free_mem; a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; a_ctrl->bridge_intf.ops.get_dev_info = cam_actuator_publish_dev_info; a_ctrl->bridge_intf.ops.link_setup = @@ -371,6 +374,7 @@ static int32_t cam_actuator_driver_platform_probe( cam_actuator_apply_request; a_ctrl->bridge_intf.ops.flush_req = cam_actuator_flush_request; + a_ctrl->last_flush_req = 0; platform_set_drvdata(pdev, a_ctrl); v4l2_set_subdevdata(&a_ctrl->v4l2_dev_str.sd, a_ctrl); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.h index 8847f77e393b..36b2994b9d71 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_dev.h @@ -108,6 +108,7 @@ struct intf_params { * @act_info: Sensor query cap structure * @of_node: Node ptr * @device_name: Device name + * @last_flush_req: Last request to flush */ struct cam_actuator_ctrl_t { struct i2c_driver *i2c_driver; @@ -125,6 +126,7 @@ struct cam_actuator_ctrl_t { struct cam_actuator_query_cap act_info; struct intf_params bridge_intf; char device_name[20]; + uint32_t last_flush_req; }; #endif /* _CAM_ACTUATOR_DEV_H_ */ diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_core.c index 80dc2711aa15..b0e810711c5d 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_core.c @@ -869,7 +869,7 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, struct cam_cci_ctrl *c_ctrl) { int32_t rc = 0; - uint32_t val = 0, i = 0, j = 0; + uint32_t val = 0, i = 0, j = 0, irq_mask_update = 0; unsigned long rem_jiffies, flags; int32_t read_words = 0, exp_words = 0; int32_t index = 0, first_byte = 0, total_read_words = 0; @@ -1048,13 +1048,20 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, j, total_read_words); spin_lock_irqsave(&cci_dev->lock_status, flags); - if (cci_dev->irq_status1) { - CAM_DBG(CAM_CCI, "clear irq_status1:%x", - cci_dev->irq_status1); - cam_io_w_mb(cci_dev->irq_status1, - base + CCI_IRQ_CLEAR_1_ADDR); - cam_io_w_mb(0x1, base + CCI_IRQ_GLOBAL_CLEAR_CMD_ADDR); - cci_dev->irq_status1 = 0; + if (cci_dev->irqs_disabled) { + irq_mask_update = + cam_io_r_mb(base + CCI_IRQ_MASK_1_ADDR) | + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + if (master == MASTER_0 && cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) + irq_mask_update |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + else if (master == MASTER_1 && cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) + irq_mask_update |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + cam_io_w_mb(irq_mask_update, + base + CCI_IRQ_MASK_1_ADDR); } spin_unlock_irqrestore(&cci_dev->lock_status, flags); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.c index 3e1c5e19ec24..6ac042c83604 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -60,8 +60,8 @@ static long cam_cci_subdev_compat_ioctl(struct v4l2_subdev *sd, irqreturn_t cam_cci_irq(int irq_num, void *data) { - uint32_t irq_status0 = 0; - uint32_t irq_status1 = 0; + uint32_t irq_status0, irq_status1, reg_bmsk; + uint32_t irq_update_rd_done = 0; struct cci_device *cci_dev = data; struct cam_hw_soc_info *soc_info = &cci_dev->soc_info; @@ -143,6 +143,7 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) &cci_dev->cci_master_info[MASTER_0].lock_q[QUEUE_1], flags); } + rd_done_th_assert = false; if ((irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) && (irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD)) { cci_dev->cci_master_info[MASTER_1].status = 0; @@ -225,19 +226,67 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) cam_io_w_mb(CCI_M1_HALT_REQ_RMSK, base + CCI_HALT_REQ_ADDR); CAM_DBG(CAM_CCI, "MASTER_1 error 0x%x", irq_status0); + } - if ((rd_done_th_assert) || (!cci_dev->is_burst_read)) { - cam_io_w_mb(irq_status1, base + CCI_IRQ_CLEAR_1_ADDR); - CAM_DBG(CAM_CCI, "clear irq_status0:%x irq_status1:%x", - irq_status0, irq_status1); - } else { + cam_io_w_mb(irq_status0, base + CCI_IRQ_CLEAR_0_ADDR); + + reg_bmsk = CCI_IRQ_MASK_1_RMSK; + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) && + !(irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK)) { + reg_bmsk &= ~CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; spin_lock_irqsave(&cci_dev->lock_status, flags); - cci_dev->irq_status1 |= irq_status1; + cci_dev->irqs_disabled |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; spin_unlock_irqrestore(&cci_dev->lock_status, flags); } - cam_io_w_mb(irq_status0, base + CCI_IRQ_CLEAR_0_ADDR); + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) && + !(irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK)) { + reg_bmsk &= ~CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + spin_lock_irqsave(&cci_dev->lock_status, flags); + cci_dev->irqs_disabled |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + + if (reg_bmsk != CCI_IRQ_MASK_1_RMSK) { + cam_io_w_mb(reg_bmsk, base + CCI_IRQ_MASK_1_ADDR); + CAM_DBG(CAM_CCI, "Updating the reg mask for irq1: 0x%x", + reg_bmsk); + } else if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK || + irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) { + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK) { + spin_lock_irqsave(&cci_dev->lock_status, flags); + if (cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) { + irq_update_rd_done |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + cci_dev->irqs_disabled &= + ~CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + } + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) { + spin_lock_irqsave(&cci_dev->lock_status, flags); + if (cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) { + irq_update_rd_done |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + cci_dev->irqs_disabled &= + ~CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + } + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + } + + if (irq_update_rd_done != 0) { + irq_update_rd_done |= cam_io_r_mb(base + CCI_IRQ_MASK_1_ADDR); + cam_io_w_mb(irq_update_rd_done, base + CCI_IRQ_MASK_1_ADDR); + } + + + cam_io_w_mb(irq_status1, base + CCI_IRQ_CLEAR_1_ADDR); cam_io_w_mb(0x1, base + CCI_IRQ_GLOBAL_CLEAR_CMD_ADDR); return IRQ_HANDLED; } diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.h index 937450daf134..7db8d5ebcd4f 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -200,6 +200,7 @@ enum cam_cci_state_t { * @lock_status: to protect changes to irq_status1 * @is_burst_read: Flag to determine if we are performing * a burst read operation or not + * @irqs_disabled: Mask for IRQs that are disabled */ struct cci_device { struct v4l2_subdev subdev; @@ -227,6 +228,7 @@ struct cci_device { uint32_t irq_status1; spinlock_t lock_status; bool is_burst_read; + uint32_t irqs_disabled; }; enum cam_cci_i2c_cmd_type { diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 005957338567..d015b6572b57 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -14,6 +14,7 @@ #include "cam_csiphy_core.h" #include "cam_csiphy_dev.h" #include "cam_csiphy_soc.h" +#include "cam_common_util.h" #include #include @@ -157,7 +158,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, struct cam_config_dev_cmd *cfg_dev) { int32_t rc = 0; - uint64_t generic_ptr; + uintptr_t generic_ptr; + uintptr_t generic_pkt_ptr; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; uint32_t *cmd_buf = NULL; @@ -170,7 +172,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, } rc = cam_mem_get_cpu_buf((int32_t) cfg_dev->packet_handle, - (uint64_t *)&generic_ptr, &len); + &generic_pkt_ptr, &len); if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed to get packet Mem address: %d", rc); return rc; @@ -180,21 +182,23 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "offset is out of bounds: offset: %lld len: %zu", cfg_dev->offset, len); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } - csl_packet = (struct cam_packet *)(generic_ptr + cfg_dev->offset); + csl_packet = (struct cam_packet *) + (generic_pkt_ptr + (uint32_t)cfg_dev->offset); cmd_desc = (struct cam_cmd_buf_desc *) ((uint32_t *)&csl_packet->payload + csl_packet->cmd_buf_offset / 4); rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, - (uint64_t *)&generic_ptr, &len); + &generic_ptr, &len); if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed to get cmd buf Mem address : %d", rc); - return rc; + goto rel_pkt_buf; } cmd_buf = (uint32_t *)generic_ptr; @@ -219,6 +223,15 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, cam_csiphy_update_secure_info(csiphy_dev, cam_cmd_csiphy_info, cfg_dev); + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_CSIPHY, "Failed to put cmd buffer: 0x%x", + cmd_desc->mem_handle); + +rel_pkt_buf: + if (cam_mem_put_cpu_buf((int32_t) cfg_dev->packet_handle)) + CAM_WARN(CAM_CSIPHY, "Failed to put packet Mem address: 0x%x", + cfg_dev->packet_handle); + return rc; } @@ -506,7 +519,7 @@ static int32_t cam_csiphy_external_cmd(struct csiphy_device *csiphy_dev, int32_t rc = 0; if (copy_from_user(&cam_cmd_csiphy_info, - (void __user *)p_submit_cmd->packet_handle, + u64_to_user_ptr(p_submit_cmd->packet_handle), sizeof(struct cam_csiphy_info))) { CAM_ERR(CAM_CSIPHY, "failed to copy cam_csiphy_info\n"); rc = -EFAULT; @@ -566,7 +579,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, struct cam_create_dev_hdl bridge_params; rc = copy_from_user(&csiphy_acq_dev, - (void __user *)cmd->handle, + u64_to_user_ptr(cmd->handle), sizeof(csiphy_acq_dev)); if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed copying from User"); @@ -576,7 +589,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, csiphy_acq_params.combo_mode = 0; if (copy_from_user(&csiphy_acq_params, - (void __user *)csiphy_acq_dev.info_handle, + u64_to_user_ptr(csiphy_acq_dev.info_handle), sizeof(csiphy_acq_params))) { CAM_ERR(CAM_CSIPHY, "Failed copying from User"); @@ -632,7 +645,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, bridge_intf->session_hdl[csiphy_acq_params.combo_mode] = csiphy_acq_dev.session_handle; - if (copy_to_user((void __user *)cmd->handle, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &csiphy_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { CAM_ERR(CAM_CSIPHY, "Failed copying from User"); @@ -650,7 +663,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, struct cam_csiphy_query_cap csiphy_cap = {0}; cam_csiphy_query_cap(csiphy_dev, &csiphy_cap); - if (copy_to_user((void __user *)cmd->handle, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &csiphy_cap, sizeof(struct cam_csiphy_query_cap))) { CAM_ERR(CAM_CSIPHY, "Failed copying from User"); rc = -EINVAL; @@ -728,7 +741,8 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, goto release_mutex; } - if (copy_from_user(&release, (void __user *) cmd->handle, + if (copy_from_user(&release, + u64_to_user_ptr(cmd->handle), sizeof(release))) { rc = -EFAULT; goto release_mutex; @@ -766,7 +780,8 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, case CAM_CONFIG_DEV: { struct cam_config_dev_cmd config; - if (copy_from_user(&config, (void __user *)cmd->handle, + if (copy_from_user(&config, + u64_to_user_ptr(cmd->handle), sizeof(config))) { rc = -EFAULT; } else { @@ -819,9 +834,11 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, rc = cam_csiphy_notify_secure_mode( csiphy_dev, CAM_SECURE_MODE_SECURE, offset); - if (rc < 0) + if (rc < 0) { csiphy_dev->csiphy_info.secure_mode[offset] = CAM_SECURE_MODE_NON_SECURE; + goto release_mutex; + } } rc = cam_csiphy_enable_hw(csiphy_dev); @@ -848,7 +865,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, struct cam_config_dev_cmd submit_cmd; if (copy_from_user(&submit_cmd, - (void __user *)cmd->handle, + u64_to_user_ptr(cmd->handle), sizeof(struct cam_config_dev_cmd))) { CAM_ERR(CAM_CSIPHY, "failed copy config ext\n"); rc = -EFAULT; diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 0b9f52f9d333..0902601cebd5 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -14,6 +14,7 @@ #include "cam_csiphy_core.h" #include "include/cam_csiphy_1_1_hwreg.h" #include "include/cam_csiphy_1_0_hwreg.h" +#include "include/cam_csiphy_1_2_hwreg.h" #include "include/cam_csiphy_2_0_hwreg.h" #define BYTES_PER_REGISTER 4 @@ -193,6 +194,22 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->hw_version = CSIPHY_VERSION_V11; csiphy_dev->clk_lane = 0; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->hw_version = CSIPHY_VERSION_V12; + csiphy_dev->clk_lane = 0; } else if (of_device_is_compatible(soc_info->dev->of_node, "qcom,csiphy-v2.0")) { csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg; diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h index 972fff99b8e8..68ca68ced31b 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h @@ -37,6 +37,7 @@ #define CSIPHY_VERSION_V35 0x35 #define CSIPHY_VERSION_V10 0x10 #define CSIPHY_VERSION_V11 0x11 +#define CSIPHY_VERSION_V12 0x12 #define CSIPHY_VERSION_V20 0x20 /** diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h new file mode 100644 index 000000000000..a16fb888edc6 --- /dev/null +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -0,0 +1,399 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CAM_CSIPHY_1_2_HWREG_H_ +#define _CAM_CSIPHY_1_2_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_2 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_common_array_size = 4, + .csiphy_reset_array_size = 4, + .csiphy_2ph_config_array_size = 21, + .csiphy_3ph_config_array_size = 31, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_2[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_2[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_2[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct +csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x07C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x07C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x02C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x06C4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct +csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +#endif /* _CAM_CSIPHY_1_2_HWREG_H_ */ diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h index 04b827f9cb79..8d7a5b58215a 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h @@ -23,6 +23,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = { .csiphy_reset_array_size = 3, .csiphy_2ph_config_array_size = 15, .csiphy_3ph_config_array_size = 17, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, }; struct csiphy_reg_t csiphy_common_reg_2_0[] = { diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index a57ecef07dc4..ab4ea76c23d7 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -17,6 +17,7 @@ #include "cam_eeprom_core.h" #include "cam_eeprom_soc.h" #include "cam_debug_util.h" +#include "cam_common_util.h" /** * cam_eeprom_read_memory() - read map data into buffer @@ -341,7 +342,8 @@ static int32_t cam_eeprom_get_dev_handle(struct cam_eeprom_ctrl_t *e_ctrl, CAM_ERR(CAM_EEPROM, "Device is already acquired"); return -EFAULT; } - if (copy_from_user(&eeprom_acq_dev, (void __user *) cmd->handle, + if (copy_from_user(&eeprom_acq_dev, + u64_to_user_ptr(cmd->handle), sizeof(eeprom_acq_dev))) { CAM_ERR(CAM_EEPROM, "EEPROM:ACQUIRE_DEV: copy from user failed"); @@ -360,8 +362,8 @@ static int32_t cam_eeprom_get_dev_handle(struct cam_eeprom_ctrl_t *e_ctrl, e_ctrl->bridge_intf.session_hdl = eeprom_acq_dev.session_handle; CAM_DBG(CAM_EEPROM, "Device Handle: %d", eeprom_acq_dev.device_handle); - if (copy_to_user((void __user *) cmd->handle, &eeprom_acq_dev, - sizeof(struct cam_sensor_acquire_dev))) { + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &eeprom_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { CAM_ERR(CAM_EEPROM, "EEPROM:ACQUIRE_DEV: copy to user failed"); return -EFAULT; } @@ -530,7 +532,7 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, struct cam_cmd_buf_desc *cmd_desc = NULL; uint32_t *offset = NULL; uint32_t *cmd_buf = NULL; - uint64_t generic_pkt_addr; + uintptr_t generic_pkt_addr; size_t pkt_len = 0; uint32_t total_cmd_buf_in_bytes = 0; uint32_t processed_cmd_buf_in_bytes = 0; @@ -564,7 +566,7 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, if (!total_cmd_buf_in_bytes) continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&generic_pkt_addr, &pkt_len); + &generic_pkt_addr, &pkt_len); if (rc) { CAM_ERR(CAM_EEPROM, "Failed to get cpu buf"); return rc; @@ -572,7 +574,8 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, cmd_buf = (uint32_t *)generic_pkt_addr; if (!cmd_buf) { CAM_ERR(CAM_EEPROM, "invalid cmd buf"); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); /* Loop through multiple cmd formats in one cmd buffer */ @@ -603,7 +606,7 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, sizeof(uint32_t); if (rc) { CAM_ERR(CAM_EEPROM, "Failed"); - return rc; + goto rel_cmd_buf; } break; case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: @@ -623,7 +626,18 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, } } e_ctrl->cal_data.num_map = num_map + 1; + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_EEPROM, "Failed to put cpu buf: 0x%x", + cmd_desc[i].mem_handle); } + + return rc; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_EEPROM, "Failed to put cpu buf: 0x%x", + cmd_desc[i].mem_handle); + return rc; } @@ -641,7 +655,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, struct cam_buf_io_cfg *io_cfg; uint32_t i = 0; int rc = 0; - uint64_t buf_addr; + uintptr_t buf_addr; size_t buf_size; uint8_t *read_buffer; @@ -656,7 +670,13 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, CAM_DBG(CAM_EEPROM, "Direction: %d:", io_cfg->direction); if (io_cfg->direction == CAM_BUF_OUTPUT) { rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], - (uint64_t *)&buf_addr, &buf_size); + &buf_addr, &buf_size); + if (rc) { + CAM_ERR(CAM_EEPROM, "Fail in get buffer: %d", + rc); + return rc; + } + CAM_DBG(CAM_EEPROM, "buf_addr : %pK, buf_size : %zu\n", (void *)buf_addr, buf_size); @@ -664,26 +684,38 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, if (!read_buffer) { CAM_ERR(CAM_EEPROM, "invalid buffer to copy data"); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } read_buffer += io_cfg->offsets[0]; if (buf_size < e_ctrl->cal_data.num_data) { CAM_ERR(CAM_EEPROM, "failed to copy, Invalid size"); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } CAM_DBG(CAM_EEPROM, "copy the data, len:%d", e_ctrl->cal_data.num_data); memcpy(read_buffer, e_ctrl->cal_data.mapdata, e_ctrl->cal_data.num_data); - + if (cam_mem_put_cpu_buf(io_cfg->mem_handle[0])) + CAM_WARN(CAM_EEPROM, "Fail in put buffer: 0x%x", + io_cfg->mem_handle[0]); } else { CAM_ERR(CAM_EEPROM, "Invalid direction"); rc = -EINVAL; } } + + return rc; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(io_cfg->mem_handle[0])) + CAM_WARN(CAM_EEPROM, "Fail in put buffer : 0x%x", + io_cfg->mem_handle[0]); + return rc; } @@ -699,7 +731,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) int32_t rc = 0; struct cam_control *ioctl_ctrl = NULL; struct cam_config_dev_cmd dev_config; - uint64_t generic_pkt_addr; + uintptr_t generic_pkt_addr; size_t pkt_len; struct cam_packet *csl_packet = NULL; struct cam_eeprom_soc_private *soc_private = @@ -708,11 +740,12 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) ioctl_ctrl = (struct cam_control *)arg; - if (copy_from_user(&dev_config, (void __user *) ioctl_ctrl->handle, + if (copy_from_user(&dev_config, + u64_to_user_ptr(ioctl_ctrl->handle), sizeof(dev_config))) return -EFAULT; rc = cam_mem_get_cpu_buf(dev_config.packet_handle, - (uint64_t *)&generic_pkt_addr, &pkt_len); + &generic_pkt_addr, &pkt_len); if (rc) { CAM_ERR(CAM_EEPROM, "error in converting command Handle Error: %d", rc); @@ -723,11 +756,12 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) CAM_ERR(CAM_EEPROM, "Offset is out of bound: off: %lld, %zu", dev_config.offset, pkt_len); - return -EINVAL; + rc = -EINVAL; + goto release_buf; } csl_packet = (struct cam_packet *) - (generic_pkt_addr + dev_config.offset); + (generic_pkt_addr + (uint32_t)dev_config.offset); switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_EEPROM_PACKET_OPCODE_INIT: if (e_ctrl->userspace_probe == false) { @@ -735,7 +769,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) e_ctrl->soc_info.dev->of_node, e_ctrl); if (rc < 0) { CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); - return rc; + goto release_buf; } rc = cam_eeprom_get_cal_data(e_ctrl, csl_packet); vfree(e_ctrl->cal_data.mapdata); @@ -750,7 +784,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) if (rc) { CAM_ERR(CAM_EEPROM, "Failed in parsing the pkt"); - return rc; + goto release_buf; } e_ctrl->cal_data.mapdata = @@ -793,7 +827,13 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) default: break; } + + if (cam_mem_put_cpu_buf(dev_config.packet_handle)) + CAM_WARN(CAM_EEPROM, "Put cpu buffer failed : 0x%x", + dev_config.packet_handle); + return rc; + power_down: cam_eeprom_power_down(e_ctrl); memdata_free: @@ -807,6 +847,11 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) e_ctrl->cal_data.num_data = 0; e_ctrl->cal_data.num_map = 0; e_ctrl->cam_eeprom_state = CAM_EEPROM_INIT; +release_buf: + if (cam_mem_put_cpu_buf(dev_config.packet_handle)) + CAM_WARN(CAM_EEPROM, "Put cpu buffer failed : 0x%x", + dev_config.packet_handle); + return rc; } @@ -880,7 +925,7 @@ int32_t cam_eeprom_driver_cmd(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) else eeprom_cap.eeprom_kernel_probe = false; - if (copy_to_user((void __user *) cmd->handle, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &eeprom_cap, sizeof(struct cam_eeprom_query_cap_t))) { CAM_ERR(CAM_EEPROM, "Failed Copy to User"); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_core.c index a7c74dc07484..76c037aee701 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_core.c @@ -15,6 +15,7 @@ #include "cam_sensor_cmn_header.h" #include "cam_flash_core.h" #include "cam_res_mgr_api.h" +#include "cam_common_util.h" static int cam_flash_prepare(struct cam_flash_ctrl *flash_ctrl, bool regulator_enable) @@ -204,6 +205,7 @@ int cam_flash_pmic_power_ops(struct cam_flash_ctrl *fctrl, "Enable Regulator Failed rc = %d", rc); return rc; } + fctrl->last_flush_req = 0; } if (!regulator_enable) { @@ -393,7 +395,13 @@ int cam_flash_flush_request(struct cam_req_mgr_flush_request *flush) } mutex_lock(&fctrl->flash_mutex); + if (fctrl->flash_state == CAM_FLASH_STATE_INIT) + goto end; + if (flush->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + fctrl->last_flush_req = flush->req_id; + CAM_DBG(CAM_FLASH, "last reqest to flush is %lld", + flush->req_id); rc = fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); if (rc) { CAM_ERR(CAM_FLASH, "FLUSH_TYPE_ALL failed rc: %d", rc); @@ -729,12 +737,7 @@ int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, fctrl->flash_state); return -EINVAL; } - rc = cam_flash_prepare(fctrl, true); - if (rc) { - CAM_ERR(CAM_FLASH, - "Enable Regulator Failed rc = %d", rc); - return rc; - } + rc = cam_flash_high(fctrl, flash_data); if (rc) CAM_ERR(CAM_FLASH, @@ -749,12 +752,7 @@ int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, fctrl->flash_state); return -EINVAL; } - rc = cam_flash_prepare(fctrl, true); - if (rc) { - CAM_ERR(CAM_FLASH, - "Enable Regulator Failed rc = %d", rc); - return rc; - } + rc = cam_flash_low(fctrl, flash_data); if (rc) CAM_ERR(CAM_FLASH, @@ -769,15 +767,6 @@ int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, rc); return rc; } - if ((fctrl->flash_state == - CAM_FLASH_STATE_START) && - (fctrl->is_regulator_enabled == true)) { - rc = cam_flash_prepare(fctrl, false); - if (rc) - CAM_ERR(CAM_FLASH, - "Disable Regulator failed: %d", - rc); - } } } else if (fctrl->nrt_info.cmn_attr.cmd_type == CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET) { @@ -908,7 +897,7 @@ int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) { int rc = 0, i = 0; - uint64_t generic_ptr; + uintptr_t generic_ptr; uint32_t total_cmd_buf_in_bytes = 0; uint32_t processed_cmd_buf_in_bytes = 0; uint16_t cmd_length_in_bytes = 0; @@ -941,7 +930,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) } rc = cam_mem_get_cpu_buf(config.packet_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); + &generic_ptr, &len_of_buffer); if (rc) { CAM_ERR(CAM_FLASH, "Failed in getting the buffer : %d", rc); return rc; @@ -956,6 +945,20 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) /* Add offset to the flash csl header */ csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_FLASH_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= fctrl->last_flush_req + && fctrl->last_flush_req != 0) { + CAM_DBG(CAM_FLASH, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, fctrl->last_flush_req); + return -EINVAL; + } + + if (csl_packet->header.request_id > fctrl->last_flush_req) + fctrl->last_flush_req = 0; + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { /* INIT packet*/ @@ -970,7 +973,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (!total_cmd_buf_in_bytes) continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); + &generic_ptr, &len_of_buffer); if (rc < 0) { CAM_ERR(CAM_FLASH, "Failed to get cpu buf"); return rc; @@ -1217,7 +1220,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) { int rc = 0, i = 0; - uint64_t generic_ptr; + uintptr_t generic_ptr, cmd_buf_ptr; uint32_t *cmd_buf = NULL; uint32_t *offset = NULL; uint32_t frm_offset = 0; @@ -1227,7 +1230,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) struct cam_cmd_buf_desc *cmd_desc = NULL; struct common_header *cmn_hdr; struct cam_config_dev_cmd config; - struct cam_req_mgr_add_request add_req; + struct cam_req_mgr_add_request add_req = {0}; struct cam_flash_init *cam_flash_info = NULL; struct cam_flash_set_rer *flash_rer_info = NULL; struct cam_flash_set_on_off *flash_operation_info = NULL; @@ -1246,7 +1249,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) /* getting CSL Packet */ ioctl_ctrl = (struct cam_control *)arg; - if (copy_from_user((&config), (void __user *) ioctl_ctrl->handle, + if (copy_from_user((&config), + u64_to_user_ptr(ioctl_ctrl->handle), sizeof(config))) { CAM_ERR(CAM_FLASH, "Copy cmd handle from user failed"); rc = -EFAULT; @@ -1254,7 +1258,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) } rc = cam_mem_get_cpu_buf(config.packet_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); + &generic_ptr, &len_of_buffer); if (rc) { CAM_ERR(CAM_FLASH, "Failed in getting the buffer : %d", rc); return rc; @@ -1264,11 +1268,27 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "offset is out of bounds: offset: %lld len: %zu", config.offset, len_of_buffer); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } /* Add offset to the flash csl header */ - csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + csl_packet = + (struct cam_packet *)(generic_ptr + (uint32_t)config.offset); + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_FLASH_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= fctrl->last_flush_req + && fctrl->last_flush_req != 0) { + CAM_WARN(CAM_FLASH, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, fctrl->last_flush_req); + rc = -EINVAL; + goto rel_pkt_buf; + } + + if (csl_packet->header.request_id > fctrl->last_flush_req) + fctrl->last_flush_req = 0; switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { @@ -1277,8 +1297,13 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) csl_packet->cmd_buf_offset); cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); - cmd_buf = (uint32_t *)((uint8_t *)generic_ptr + + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + goto rel_pkt_buf; + } + + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); cam_flash_info = (struct cam_flash_init *)cmd_buf; @@ -1297,7 +1322,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Enable Regulator Failed rc = %d", rc); - return rc; + goto rel_cmd_buf; } fctrl->flash_state = @@ -1333,8 +1358,13 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) default: CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", cam_flash_info->cmd_type); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } + + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_FLASH, "Fail in put buffer: %pK", + cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_SET_OPS: { @@ -1355,12 +1385,19 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) flash_data->cmn_attr.is_settings_valid = true; cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); - cmd_buf = (uint32_t *)((uint8_t *)generic_ptr + - cmd_desc->offset); + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: 0x%x", + cmd_desc->mem_handle); + goto rel_pkt_buf; + } - if (!cmd_buf) - return -EINVAL; + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + + cmd_desc->offset); + if (!cmd_buf) { + rc = -EINVAL; + goto rel_cmd_buf; + } cmn_hdr = (struct common_header *)cmd_buf; @@ -1374,7 +1411,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_WARN(CAM_FLASH, "Rxed Flash fire ops without linking"); flash_data->cmn_attr.is_settings_valid = false; - return 0; + goto rel_cmd_buf; } flash_operation_info = @@ -1382,7 +1419,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (!flash_operation_info) { CAM_ERR(CAM_FLASH, "flash_operation_info Null"); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } flash_data->opcode = flash_operation_info->opcode; @@ -1391,13 +1429,20 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) for (i = 0; i < flash_operation_info->count; i++) flash_data->led_current_ma[i] = flash_operation_info->led_current_ma[i]; + + if (flash_data->opcode == CAMERA_SENSOR_FLASH_OP_OFF) + add_req.skip_before_applying |= SKIP_NEXT_FRAME; } break; default: CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", cmn_hdr->cmd_type); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_FLASH, "Fail in put buffer: 0x%x", + cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { @@ -1406,8 +1451,12 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) fctrl->nrt_info.cmn_attr.is_settings_valid = true; cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, - (uint64_t *)&generic_ptr, &len_of_buffer); - cmd_buf = (uint32_t *)((uint8_t *)generic_ptr + + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + goto rel_pkt_buf; + } + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); cmn_hdr = (struct common_header *)cmd_buf; @@ -1432,7 +1481,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) CAM_ERR(CAM_FLASH, "Apply setting failed: %d", rc); - return rc; + goto rel_cmd_buf; } case CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR: { int query_curr_ma = 0; @@ -1456,7 +1505,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Query current failed with rc=%d", rc); - return rc; + goto rel_cmd_buf; } flash_query_info->query_current_ma = query_curr_ma; break; @@ -1480,18 +1529,21 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) fctrl->nrt_info.led_current_ma[i] = flash_rer_info->led_current_ma[i]; - rc = fctrl->func_tbl.apply_setting(fctrl, 0); if (rc) CAM_ERR(CAM_FLASH, "apply_setting failed: %d", rc); - return rc; + goto rel_cmd_buf; } default: CAM_ERR(CAM_FLASH, "Wrong cmd_type : %d", cmn_hdr->cmd_type); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_FLASH, "Fail in put buffer: 0x%x", + cmd_desc->mem_handle); break; } case CAM_PKT_NOP_OPCODE: { @@ -1503,7 +1555,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) "Rxed NOP packets without linking"); fctrl->per_frame[frm_offset].cmn_attr.is_settings_valid = false; - return 0; + goto rel_pkt_buf; } fctrl->per_frame[frm_offset].cmn_attr.is_settings_valid = false; @@ -1511,14 +1563,15 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) fctrl->per_frame[frm_offset].opcode = CAM_PKT_NOP_OPCODE; CAM_DBG(CAM_FLASH, "NOP Packet is Received: req_id: %llu", csl_packet->header.request_id); - goto update_req_mgr; + break; } default: CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", (csl_packet->header.op_code & 0xFFFFFF)); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } -update_req_mgr: + if (((csl_packet->header.op_code & 0xFFFFF) == CAM_PKT_NOP_OPCODE) || ((csl_packet->header.op_code & 0xFFFFF) == @@ -1529,7 +1582,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if ((csl_packet->header.op_code & 0xFFFFF) == CAM_FLASH_PACKET_OPCODE_SET_OPS) - add_req.skip_before_applying = 1; + add_req.skip_before_applying |= 1; else add_req.skip_before_applying = 0; @@ -1539,6 +1592,21 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); } + if (cam_mem_put_cpu_buf(config.packet_handle)) + CAM_WARN(CAM_FLASH, "Failed in put the buffer: 0x%x ", + config.packet_handle); + + return 0; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_FLASH, "Fail in put buffer: 0x%x", + cmd_desc->mem_handle); +rel_pkt_buf: + if (cam_mem_put_cpu_buf(config.packet_handle)) + CAM_WARN(CAM_FLASH, "Failed in put the buffer: 0x%x ", + config.packet_handle); + return rc; } @@ -1589,6 +1657,7 @@ int cam_flash_release_dev(struct cam_flash_ctrl *fctrl) fctrl->bridge_intf.device_hdl = -1; fctrl->bridge_intf.link_hdl = -1; fctrl->bridge_intf.session_hdl = -1; + fctrl->last_flush_req = 0; } return rc; @@ -1603,9 +1672,7 @@ void cam_flash_shutdown(struct cam_flash_ctrl *fctrl) if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || (fctrl->flash_state == CAM_FLASH_STATE_START)) { - mutex_lock(&(fctrl->flash_mutex)); fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); - mutex_unlock(&(fctrl->flash_mutex)); rc = fctrl->func_tbl.power_ops(fctrl, false); if (rc) CAM_ERR(CAM_FLASH, "Power Down Failed rc: %d", diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.c index 199b50502cad..10c10ee8b68c 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -15,6 +15,7 @@ #include "cam_flash_dev.h" #include "cam_flash_soc.h" #include "cam_flash_core.h" +#include "cam_common_util.h" static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, void *arg, struct cam_flash_private_soc *soc_private) @@ -57,7 +58,8 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, goto release_mutex; } - rc = copy_from_user(&flash_acq_dev, (void __user *)cmd->handle, + rc = copy_from_user(&flash_acq_dev, + u64_to_user_ptr(cmd->handle), sizeof(flash_acq_dev)); if (rc) { CAM_ERR(CAM_FLASH, "Failed Copying from User"); @@ -77,7 +79,8 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, fctrl->bridge_intf.session_hdl = flash_acq_dev.session_handle; - rc = copy_to_user((void __user *) cmd->handle, &flash_acq_dev, + rc = copy_to_user(u64_to_user_ptr(cmd->handle), + &flash_acq_dev, sizeof(struct cam_sensor_acquire_dev)); if (rc) { CAM_ERR(CAM_FLASH, "Failed Copy to User with rc = %d", @@ -107,6 +110,15 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, goto release_mutex; } + if (fctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_SENSOR, + "Device [%d] still active on link 0x%x", + fctrl->flash_state, + fctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || (fctrl->flash_state == CAM_FLASH_STATE_START)) fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); @@ -137,8 +149,8 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, flash_cap.max_current_torch[i] = soc_private->torch_max_current[i]; - if (copy_to_user((void __user *) cmd->handle, &flash_cap, - sizeof(struct cam_flash_query_cap_info))) { + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &flash_cap, sizeof(struct cam_flash_query_cap_info))) { CAM_ERR(CAM_FLASH, "Failed Copy to User"); rc = -EFAULT; goto release_mutex; @@ -170,6 +182,7 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, } fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + fctrl->last_flush_req = 0; fctrl->flash_state = CAM_FLASH_STATE_ACQUIRE; break; } @@ -466,10 +479,12 @@ static int32_t cam_flash_platform_probe(struct platform_device *pdev) } fctrl->bridge_intf.device_hdl = -1; + fctrl->bridge_intf.link_hdl = -1; fctrl->bridge_intf.ops.get_dev_info = cam_flash_publish_dev_info; fctrl->bridge_intf.ops.link_setup = cam_flash_establish_link; fctrl->bridge_intf.ops.apply_req = cam_flash_apply_request; fctrl->bridge_intf.ops.flush_req = cam_flash_flush_request; + fctrl->last_flush_req = 0; mutex_init(&(fctrl->flash_mutex)); @@ -551,10 +566,12 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client, fctrl->func_tbl.flush_req = cam_flash_i2c_flush_request; fctrl->bridge_intf.device_hdl = -1; + fctrl->bridge_intf.link_hdl = -1; fctrl->bridge_intf.ops.get_dev_info = cam_flash_publish_dev_info; fctrl->bridge_intf.ops.link_setup = cam_flash_establish_link; fctrl->bridge_intf.ops.apply_req = cam_flash_apply_request; fctrl->bridge_intf.ops.flush_req = cam_flash_flush_request; + fctrl->last_flush_req = 0; mutex_init(&(fctrl->flash_mutex)); fctrl->flash_state = CAM_FLASH_STATE_INIT; diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.h index b59d7c916b8a..c7de59c93079 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_flash/cam_flash_dev.h @@ -173,7 +173,7 @@ struct cam_flash_func_tbl { * @flash_num_sources : Number of flash sources * @torch_num_source : Number of torch sources * @flash_mutex : Mutex for flash operations - * @flash_state : Current flash state (LOW/OFF/ON/INIT) + * @flash_state : Current flash state (LOW/OFF/ON/INIT) * @flash_type : Flash types (PMIC/I2C/GPIO) * @is_regulator_enable : Regulator disable/enable notifier * @func_tbl : Function table for different HW @@ -183,6 +183,7 @@ struct cam_flash_func_tbl { * @cci_i2c_master : I2C structure * @io_master_info : Information about the communication master * @i2c_data : I2C register settings + * @last_flush_req : last request to flush */ struct cam_flash_ctrl { struct cam_hw_soc_info soc_info; @@ -208,6 +209,7 @@ struct cam_flash_ctrl { enum cci_i2c_master_t cci_i2c_master; struct camera_io_master io_master_info; struct i2c_data_settings i2c_data; + uint32_t last_flush_req; }; int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_ois/cam_ois_core.c index d543bf9c7705..eff5c15fe43a 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_ois/cam_ois_core.c @@ -18,6 +18,7 @@ #include "cam_sensor_util.h" #include "cam_debug_util.h" #include "cam_res_mgr_api.h" +#include "cam_common_util.h" int32_t cam_ois_construct_default_power_setting( struct cam_sensor_power_ctrl_t *power_info) @@ -79,7 +80,7 @@ static int cam_ois_get_dev_handle(struct cam_ois_ctrl_t *o_ctrl, CAM_ERR(CAM_OIS, "Device is already acquired"); return -EFAULT; } - if (copy_from_user(&ois_acq_dev, (void __user *) cmd->handle, + if (copy_from_user(&ois_acq_dev, u64_to_user_ptr(cmd->handle), sizeof(ois_acq_dev))) return -EFAULT; @@ -95,7 +96,7 @@ static int cam_ois_get_dev_handle(struct cam_ois_ctrl_t *o_ctrl, o_ctrl->bridge_intf.session_hdl = ois_acq_dev.session_handle; CAM_DBG(CAM_OIS, "Device Handle: %d", ois_acq_dev.device_handle); - if (copy_to_user((void __user *) cmd->handle, &ois_acq_dev, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &ois_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { CAM_ERR(CAM_OIS, "ACQUIRE_DEV: copy to user failed"); return -EFAULT; @@ -324,7 +325,6 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) rc = request_firmware(&fw, fw_name_prog, dev); if (rc) { CAM_ERR(CAM_OIS, "Failed to locate %s", fw_name_prog); - release_firmware(fw); return rc; } @@ -370,7 +370,6 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) rc = request_firmware(&fw, fw_name_coeff, dev); if (rc) { CAM_ERR(CAM_OIS, "Failed to locate %s", fw_name_coeff); - release_firmware(fw); return rc; } @@ -427,12 +426,12 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) int32_t i = 0; uint32_t total_cmd_buf_in_bytes = 0; struct common_header *cmm_hdr = NULL; - uint64_t generic_ptr; + uintptr_t generic_ptr; struct cam_control *ioctl_ctrl = NULL; struct cam_config_dev_cmd dev_config; struct i2c_settings_array *i2c_reg_settings = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; - uint64_t generic_pkt_addr; + uintptr_t generic_pkt_addr; size_t pkt_len; struct cam_packet *csl_packet = NULL; size_t len_of_buff = 0; @@ -442,11 +441,12 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; ioctl_ctrl = (struct cam_control *)arg; - if (copy_from_user(&dev_config, (void __user *) ioctl_ctrl->handle, + if (copy_from_user(&dev_config, + u64_to_user_ptr(ioctl_ctrl->handle), sizeof(dev_config))) return -EFAULT; rc = cam_mem_get_cpu_buf(dev_config.packet_handle, - (uint64_t *)&generic_pkt_addr, &pkt_len); + &generic_pkt_addr, &pkt_len); if (rc) { CAM_ERR(CAM_OIS, "error in converting command Handle Error: %d", rc); @@ -457,11 +457,12 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) CAM_ERR(CAM_OIS, "offset is out of bound: off: %lld len: %zu", dev_config.offset, pkt_len); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt; } csl_packet = (struct cam_packet *) - (generic_pkt_addr + dev_config.offset); + (generic_pkt_addr + (uint32_t)dev_config.offset); switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_OIS_PACKET_OPCODE_INIT: offset = (uint32_t *)&csl_packet->payload; @@ -475,15 +476,17 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&generic_ptr, &len_of_buff); + &generic_ptr, &len_of_buff); if (rc < 0) { - CAM_ERR(CAM_OIS, "Failed to get cpu buf"); - return rc; + CAM_ERR(CAM_OIS, "Failed to get cpu buf : 0x%x", + cmd_desc[i].mem_handle); + goto rel_pkt; } cmd_buf = (uint32_t *)generic_ptr; if (!cmd_buf) { CAM_ERR(CAM_OIS, "invalid cmd buf"); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); cmm_hdr = (struct common_header *)cmd_buf; @@ -495,7 +498,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Failed in parsing slave info"); - return rc; + goto rel_cmd_buf; } break; case CAMERA_SENSOR_CMD_TYPE_PWR_UP: @@ -509,7 +512,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc) { CAM_ERR(CAM_OIS, "Failed: parse power settings"); - return rc; + goto rel_cmd_buf; } break; default: @@ -527,7 +530,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "init parsing failed: %d", rc); - return rc; + goto rel_cmd_buf; } } else if ((o_ctrl->is_ois_calib != 0) && (o_ctrl->i2c_calib_data.is_settings_valid == @@ -544,18 +547,21 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Calib parsing failed: %d", rc); - return rc; + goto rel_cmd_buf; } } break; } + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_OIS, "Failed to put cpu buf: 0x%x", + cmd_desc[i].mem_handle); } if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) { rc = cam_ois_power_up(o_ctrl); if (rc) { CAM_ERR(CAM_OIS, " OIS Power up failed"); - return rc; + goto rel_pkt; } o_ctrl->cam_ois_state = CAM_OIS_CONFIG; } @@ -602,7 +608,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) CAM_WARN(CAM_OIS, "Not in right state to control OIS: %d", o_ctrl->cam_ois_state); - return rc; + goto rel_pkt; } offset = (uint32_t *)&csl_packet->payload; offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); @@ -615,26 +621,43 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) cmd_desc, 1); if (rc < 0) { CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc); - return rc; + goto rel_pkt; } rc = cam_ois_apply_settings(o_ctrl, i2c_reg_settings); if (rc < 0) { CAM_ERR(CAM_OIS, "Cannot apply mode settings"); - return rc; + goto rel_pkt; } rc = delete_request(i2c_reg_settings); - if (rc < 0) + if (rc < 0) { CAM_ERR(CAM_OIS, "Fail deleting Mode data: rc: %d", rc); + goto rel_pkt; + } break; default: - break; + CAM_ERR(CAM_OIS, "Invalid Opcode: %d", + (csl_packet->header.op_code & 0xFFFFFF)); + rc = -EINVAL; + goto rel_pkt; } - return rc; + + if (!rc) + goto rel_pkt; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_OIS, "Failed to put cpu buf: 0x%x", + cmd_desc[i].mem_handle); pwr_dwn: cam_ois_power_down(o_ctrl); +rel_pkt: + if (cam_mem_put_cpu_buf(dev_config.packet_handle)) + CAM_WARN(CAM_OIS, "Fail in put buffer: 0x%x", + dev_config.packet_handle); + return rc; } @@ -718,7 +741,7 @@ int cam_ois_driver_cmd(struct cam_ois_ctrl_t *o_ctrl, void *arg) case CAM_QUERY_CAP: ois_cap.slot_info = o_ctrl->soc_info.index; - if (copy_to_user((void __user *) cmd->handle, + if (copy_to_user(u64_to_user_ptr(cmd->handle), &ois_cap, sizeof(struct cam_ois_query_cap_t))) { CAM_ERR(CAM_OIS, "Failed Copy to User"); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_res_mgr/cam_res_mgr.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_res_mgr/cam_res_mgr.c index d03faef4d3a6..91b19c8f7ff0 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_res_mgr/cam_res_mgr.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_res_mgr/cam_res_mgr.c @@ -178,8 +178,10 @@ int cam_res_mgr_shared_pinctrl_init(void) return 0; } + mutex_lock(&cam_res->gpio_res_lock); if (cam_res->pstatus != PINCTRL_STATUS_PUT) { CAM_DBG(CAM_RES, "The shared pinctrl already been got."); + mutex_unlock(&cam_res->gpio_res_lock); return 0; } @@ -190,6 +192,7 @@ int cam_res_mgr_shared_pinctrl_init(void) if (IS_ERR_OR_NULL(pinctrl_info->pinctrl)) { CAM_ERR(CAM_RES, "Pinctrl not available"); cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); return -EINVAL; } @@ -200,6 +203,7 @@ int cam_res_mgr_shared_pinctrl_init(void) CAM_ERR(CAM_RES, "Failed to get the active state pinctrl handle"); cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); return -EINVAL; } @@ -210,10 +214,10 @@ int cam_res_mgr_shared_pinctrl_init(void) CAM_ERR(CAM_RES, "Failed to get the active state pinctrl handle"); cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); return -EINVAL; } - mutex_lock(&cam_res->gpio_res_lock); cam_res->pstatus = PINCTRL_STATUS_GOT; mutex_unlock(&cam_res->gpio_res_lock); @@ -313,6 +317,7 @@ int cam_res_mgr_shared_pinctrl_select_state(bool active) pinctrl_info->gpio_state_suspend); cam_res->pstatus = PINCTRL_STATUS_SUSPEND; } + mutex_unlock(&cam_res->gpio_res_lock); return rc; @@ -379,12 +384,14 @@ static bool cam_res_mgr_gpio_is_shared(uint gpio) bool found = false; struct cam_res_mgr_dt *dt = &cam_res->dt; + mutex_lock(&cam_res->gpio_res_lock); for (; index < dt->num_shared_gpio; index++) { if (gpio == dt->shared_gpio[index]) { found = true; break; } } + mutex_unlock(&cam_res->gpio_res_lock); return found; } @@ -441,13 +448,14 @@ int cam_res_mgr_gpio_request(struct device *dev, uint gpio, INIT_LIST_HEAD(&gpio_res->list); INIT_LIST_HEAD(&gpio_res->dev_list); + mutex_lock(&cam_res->gpio_res_lock); rc = cam_res_mgr_add_device(dev, gpio_res); if (rc) { kfree(gpio_res); + mutex_unlock(&cam_res->gpio_res_lock); return rc; } - mutex_lock(&cam_res->gpio_res_lock); list_add_tail(&gpio_res->list, &cam_res->gpio_res_list); mutex_unlock(&cam_res->gpio_res_lock); } diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c index f56b0e5bc830..c47e38e50893 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -16,6 +16,7 @@ #include "cam_sensor_util.h" #include "cam_soc_util.h" #include "cam_trace.h" +#include "cam_common_util.h" static int32_t cam_sensor_update_i2c_slave_info( struct camera_io_master *io_master, @@ -91,7 +92,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, void *arg) { int32_t rc = 0; - uint64_t generic_ptr; + uintptr_t generic_ptr; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; @@ -108,13 +109,14 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, return -EINVAL; } - if (copy_from_user(&config, (void __user *) ioctl_ctrl->handle, + if (copy_from_user(&config, + u64_to_user_ptr(ioctl_ctrl->handle), sizeof(config))) return -EFAULT; rc = cam_mem_get_cpu_buf( config.packet_handle, - (uint64_t *)&generic_ptr, + &generic_ptr, &len_of_buff); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed in getting the buffer: %d", rc); @@ -122,14 +124,29 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, } csl_packet = (struct cam_packet *)(generic_ptr + - config.offset); + (uint32_t)config.offset); if (config.offset > len_of_buff) { CAM_ERR(CAM_SENSOR, "offset is out of bounds: off: %lld len: %zu", config.offset, len_of_buff); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG && + csl_packet->header.request_id <= s_ctrl->last_flush_req + && s_ctrl->last_flush_req != 0) { + CAM_DBG(CAM_SENSOR, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, s_ctrl->last_flush_req); + rc = -EINVAL; + goto rel_pkt_buf; + } + + if (csl_packet->header.request_id > s_ctrl->last_flush_req) + s_ctrl->last_flush_req = 0; + i2c_data = &(s_ctrl->i2c_data); CAM_DBG(CAM_SENSOR, "Header OpCode: %d", csl_packet->header.op_code); switch (csl_packet->header.op_code & 0xFFFFFF) { @@ -147,7 +164,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, } case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: { if (s_ctrl->streamon_count > 0) - return 0; + goto rel_pkt_buf; s_ctrl->streamon_count = s_ctrl->streamon_count + 1; i2c_reg_settings = &i2c_data->streamon_settings; @@ -157,7 +174,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, } case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: { if (s_ctrl->streamoff_count > 0) - return 0; + goto rel_pkt_buf; s_ctrl->streamoff_count = s_ctrl->streamoff_count + 1; i2c_reg_settings = &i2c_data->streamoff_settings; @@ -171,7 +188,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, (s_ctrl->sensor_state == CAM_SENSOR_ACQUIRE)) { CAM_WARN(CAM_SENSOR, "Rxed Update packets without linking"); - return 0; + goto rel_pkt_buf; } i2c_reg_settings = @@ -191,7 +208,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, * fix it. */ cam_sensor_update_req_mgr(s_ctrl, csl_packet); - return 0; + goto rel_pkt_buf; } break; } @@ -200,15 +217,16 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, (s_ctrl->sensor_state == CAM_SENSOR_ACQUIRE)) { CAM_WARN(CAM_SENSOR, "Rxed NOP packets without linking"); - return 0; + goto rel_pkt_buf; } cam_sensor_update_req_mgr(s_ctrl, csl_packet); - return 0; + goto rel_pkt_buf; } default: CAM_ERR(CAM_SENSOR, "Invalid Packet Header"); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } offset = (uint32_t *)&csl_packet->payload; @@ -219,7 +237,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, i2c_reg_settings, cmd_desc, 1); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Fail parsing I2C Pkt: %d", rc); - return rc; + goto rel_pkt_buf; } if ((csl_packet->header.op_code & 0xFFFFFF) == @@ -229,6 +247,11 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, cam_sensor_update_req_mgr(s_ctrl, csl_packet); } +rel_pkt_buf: + if (cam_mem_put_cpu_buf(config.packet_handle)) + CAM_WARN(CAM_SENSOR, "Failed in put the buffer: 0x%x", + config.packet_handle); + return rc; } @@ -403,14 +426,18 @@ int32_t cam_sensor_update_slave_info(struct cam_cmd_probe *probe_info, probe_info->expected_data; s_ctrl->sensordata->slave_info.sensor_id_mask = probe_info->data_mask; + /* Userspace passes the pipeline delay in reserved field */ + s_ctrl->pipeline_delay = + probe_info->reserved; s_ctrl->sensor_probe_addr_type = probe_info->addr_type; s_ctrl->sensor_probe_data_type = probe_info->data_type; CAM_DBG(CAM_SENSOR, - "Sensor Addr: 0x%x sensor_id: 0x%x sensor_mask: 0x%x", + "Sensor Addr: 0x%x sensor_id: 0x%x sensor_mask: 0x%x sensor_pipeline_delay:0x%x", s_ctrl->sensordata->slave_info.sensor_id_reg_addr, s_ctrl->sensordata->slave_info.sensor_id, - s_ctrl->sensordata->slave_info.sensor_id_mask); + s_ctrl->sensordata->slave_info.sensor_id_mask, + s_ctrl->pipeline_delay); return rc; } @@ -461,15 +488,16 @@ int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) { int rc = 0, i; - void *packet = NULL, *cmd_buf1 = NULL; uint32_t *cmd_buf; void *ptr; size_t len; struct cam_packet *pkt; struct cam_cmd_buf_desc *cmd_desc; + uintptr_t cmd_buf1 = 0; + uintptr_t packet = 0; rc = cam_mem_get_cpu_buf(handle, - (uint64_t *)&packet, &len); + &packet, &len); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to get the command Buffer"); return -EINVAL; @@ -479,22 +507,25 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) ((uint32_t *)&pkt->payload + pkt->cmd_buf_offset/4); if (cmd_desc == NULL) { CAM_ERR(CAM_SENSOR, "command descriptor pos is invalid"); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } if (pkt->num_cmd_buf != 2) { CAM_ERR(CAM_SENSOR, "Expected More Command Buffers : %d", pkt->num_cmd_buf); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } + for (i = 0; i < pkt->num_cmd_buf; i++) { if (!(cmd_desc[i].length)) continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&cmd_buf1, &len); + &cmd_buf1, &len); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to parse the command Buffer Header"); - return -EINVAL; + goto rel_pkt_buf; } cmd_buf = (uint32_t *)cmd_buf1; cmd_buf += cmd_desc[i].offset/4; @@ -505,9 +536,30 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to parse the command Buffer Header"); - return -EINVAL; + goto rel_cmd_buf; } + + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_SENSOR, + "Failed to put command Buffer : 0x%x", + cmd_desc[i].mem_handle); } + + if (cam_mem_put_cpu_buf(handle)) + CAM_WARN(CAM_SENSOR, "Failed to put the command Buffer: 0x%x", + handle); + + return rc; + +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_SENSOR, "Failed to put command Buffer : 0x%x", + cmd_desc[i].mem_handle); +rel_pkt_buf: + if (cam_mem_put_cpu_buf(handle)) + CAM_WARN(CAM_SENSOR, "Failed to put the command Buffer: 0x%x", + handle); + return rc; } @@ -563,11 +615,13 @@ void cam_sensor_shutdown(struct cam_sensor_ctrl_t *s_ctrl) cam_sensor_release_stream_rsc(s_ctrl); cam_sensor_release_per_frame_resource(s_ctrl); - cam_sensor_power_down(s_ctrl); + + if (s_ctrl->sensor_state != CAM_SENSOR_INIT) + cam_sensor_power_down(s_ctrl); rc = cam_destroy_device_hdl(s_ctrl->bridge_intf.device_hdl); if (rc < 0) - CAM_ERR(CAM_SENSOR, " failed destroying dhdl"); + CAM_ERR(CAM_SENSOR, "dhdl already destroyed: rc = %d", rc); s_ctrl->bridge_intf.device_hdl = -1; s_ctrl->bridge_intf.link_hdl = -1; s_ctrl->bridge_intf.session_hdl = -1; @@ -580,6 +634,7 @@ void cam_sensor_shutdown(struct cam_sensor_ctrl_t *s_ctrl) s_ctrl->streamon_count = 0; s_ctrl->streamoff_count = 0; s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; s_ctrl->sensor_state = CAM_SENSOR_INIT; } @@ -701,7 +756,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, } CAM_INFO(CAM_SENSOR, - "Probe Succees,slot:%d,slave_addr:0x%x,sensor_id:0x%x", + "Probe success,slot:%d,slave_addr:0x%x,sensor_id:0x%x", s_ctrl->soc_info.index, s_ctrl->sensordata->slave_info.sensor_slave_addr, s_ctrl->sensordata->slave_info.sensor_id); @@ -1076,7 +1131,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, kfree(wr_array); kfree(reg_setting); } - break; + break; case CAM_ACQUIRE_DEV: { struct cam_sensor_acquire_dev sensor_acq_dev; struct cam_create_dev_hdl bridge_params; @@ -1096,7 +1151,8 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, goto release_mutex; } rc = copy_from_user(&sensor_acq_dev, - (void __user *) cmd->handle, sizeof(sensor_acq_dev)); + u64_to_user_ptr(cmd->handle), + sizeof(sensor_acq_dev)); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed Copying from user"); goto release_mutex; @@ -1115,7 +1171,8 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, CAM_DBG(CAM_SENSOR, "Device Handle: %d", sensor_acq_dev.device_handle); - if (copy_to_user((void __user *) cmd->handle, &sensor_acq_dev, + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &sensor_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { CAM_ERR(CAM_SENSOR, "Failed Copy to User"); rc = -EFAULT; @@ -1129,6 +1186,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, } s_ctrl->sensor_state = CAM_SENSOR_ACQUIRE; + s_ctrl->last_flush_req = 0; CAM_INFO(CAM_SENSOR, "CAM_ACQUIRE_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", s_ctrl->sensordata->slave_info.sensor_id, @@ -1145,6 +1203,15 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, goto release_mutex; } + if (s_ctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_SENSOR, + "Device [%d] still active on link 0x%x", + s_ctrl->sensor_state, + s_ctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + rc = cam_sensor_power_down(s_ctrl); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Sensor Power Down failed"); @@ -1176,14 +1243,15 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, s_ctrl->sensordata->slave_info.sensor_slave_addr); s_ctrl->streamon_count = 0; s_ctrl->streamoff_count = 0; + s_ctrl->last_flush_req = 0; } break; case CAM_QUERY_CAP: { struct cam_sensor_query_cap sensor_cap; cam_sensor_query_cap(s_ctrl, &sensor_cap); - if (copy_to_user((void __user *) cmd->handle, &sensor_cap, - sizeof(struct cam_sensor_query_cap))) { + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &sensor_cap, sizeof(struct cam_sensor_query_cap))) { CAM_ERR(CAM_SENSOR, "Failed Copy to User"); rc = -EFAULT; goto release_mutex; @@ -1237,6 +1305,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, } cam_sensor_release_per_frame_resource(s_ctrl); + s_ctrl->last_flush_req = 0; s_ctrl->sensor_state = CAM_SENSOR_ACQUIRE; CAM_INFO(CAM_SENSOR, "CAM_STOP_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", @@ -1319,13 +1388,25 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, int cam_sensor_publish_dev_info(struct cam_req_mgr_device_info *info) { int rc = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; if (!info) return -EINVAL; + s_ctrl = (struct cam_sensor_ctrl_t *) + cam_get_device_priv(info->dev_hdl); + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "Device data is NULL"); + return -EINVAL; + } + info->dev_id = CAM_REQ_MGR_DEVICE_SENSOR; strlcpy(info->name, CAM_SENSOR_NAME, sizeof(info->name)); - info->p_delay = 2; + if (s_ctrl->pipeline_delay >= 1 && s_ctrl->pipeline_delay <= 3) + info->p_delay = s_ctrl->pipeline_delay; + else + info->p_delay = 2; info->trigger = CAM_TRIGGER_POINT_SOF; return rc; @@ -1617,6 +1698,13 @@ int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) return -EINVAL; } + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + s_ctrl->last_flush_req = flush_req->req_id; + CAM_DBG(CAM_SENSOR, "last reqest to flush is %lld", + flush_req->req_id); + } + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { i2c_set = &(s_ctrl->i2c_data.per_frame[i]); @@ -1625,9 +1713,7 @@ int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) continue; if (i2c_set->is_settings_valid == 1) { - mutex_lock(&(s_ctrl->cam_sensor_mutex)); rc = delete_request(i2c_set); - mutex_unlock(&(s_ctrl->cam_sensor_mutex)); if (rc < 0) CAM_ERR(CAM_SENSOR, "delete request: %lld rc: %d", @@ -1646,5 +1732,6 @@ int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) CAM_DBG(CAM_SENSOR, "Flush request id:%lld not found in the pending list", flush_req->req_id); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); return rc; } diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.c index 6cf40f8b0f10..8dcb6c73312f 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.c @@ -162,6 +162,7 @@ static int32_t cam_sensor_driver_i2c_probe(struct i2c_client *client, s_ctrl->of_node = client->dev.of_node; s_ctrl->io_master_info.master_type = I2C_MASTER; s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; rc = cam_sensor_parse_dt(s_ctrl); if (rc < 0) { @@ -191,6 +192,7 @@ static int32_t cam_sensor_driver_i2c_probe(struct i2c_client *client, INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; s_ctrl->bridge_intf.ops.get_dev_info = cam_sensor_publish_dev_info; s_ctrl->bridge_intf.ops.link_setup = cam_sensor_establish_link; s_ctrl->bridge_intf.ops.apply_req = cam_sensor_apply_request; @@ -275,6 +277,7 @@ static int32_t cam_sensor_driver_platform_probe( /* Initialize sensor device type */ s_ctrl->of_node = pdev->dev.of_node; s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; /*fill in platform device*/ s_ctrl->pdev = pdev; @@ -312,6 +315,7 @@ static int32_t cam_sensor_driver_platform_probe( INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; s_ctrl->bridge_intf.ops.get_dev_info = cam_sensor_publish_dev_info; s_ctrl->bridge_intf.ops.link_setup = cam_sensor_establish_link; s_ctrl->bridge_intf.ops.apply_req = cam_sensor_apply_request; diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.h b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.h index 8339d9b12de3..e98a592dd5ea 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.h +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_dev.h @@ -94,6 +94,8 @@ struct intf_params { * @streamoff_count: Count to hold the number of times stream off called * @bob_reg_index: Hold to BoB regulator index * @bob_pwm_switch: Boolean flag to switch into PWM mode for BoB regulator + * @last_flush_req: Last request to flush + * @pipeline_delay: Sensor pipeline delay */ struct cam_sensor_ctrl_t { struct platform_device *pdev; @@ -118,6 +120,8 @@ struct cam_sensor_ctrl_t { uint32_t streamoff_count; int bob_reg_index; bool bob_pwm_switch; + uint32_t last_flush_req; + uint16_t pipeline_delay; }; #endif /* _CAM_SENSOR_DEV_H_ */ diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index cbb068acf143..9556814be9ae 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -284,7 +284,7 @@ int cam_sensor_i2c_command_parser( { int16_t rc = 0, i = 0; size_t len_of_buff = 0; - uint64_t generic_ptr; + uintptr_t generic_ptr; uint16_t cmd_length_in_bytes = 0; for (i = 0; i < num_cmd_buffers; i++) { @@ -306,14 +306,14 @@ int cam_sensor_i2c_command_parser( continue; rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, - (uint64_t *)&generic_ptr, &len_of_buff); - cmd_buf = (uint32_t *)generic_ptr; + &generic_ptr, &len_of_buff); if (rc < 0) { CAM_ERR(CAM_SENSOR, - "cmd hdl failed:%d, Err: %d, Buffer_len: %ld", + "cmd hdl failed:%d, Err: %d, Buffer_len: %zd", cmd_desc[i].mem_handle, rc, len_of_buff); return rc; } + cmd_buf = (uint32_t *)generic_ptr; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); while (byte_cnt < cmd_desc[i].length) { @@ -333,7 +333,7 @@ int cam_sensor_i2c_command_parser( if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed in random write %d", rc); - return rc; + goto rel_buf; } cmd_buf += cmd_length_in_bytes / @@ -355,7 +355,7 @@ int cam_sensor_i2c_command_parser( if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed in continuous write %d", rc); - return rc; + goto rel_buf; } cmd_buf += cmd_length_in_bytes / @@ -377,7 +377,7 @@ int cam_sensor_i2c_command_parser( CAM_ERR(CAM_SENSOR, "delay hdl failed: %d", rc); - return rc; + goto rel_buf; } } else if (generic_op_code == @@ -389,13 +389,14 @@ int cam_sensor_i2c_command_parser( CAM_ERR(CAM_SENSOR, "Random read fail: %d", rc); - return rc; + goto rel_buf; } } else { CAM_ERR(CAM_SENSOR, "Wrong Wait Command: %d", generic_op_code); - return -EINVAL; + rc = -EINVAL; + goto rel_buf; } break; } @@ -406,7 +407,7 @@ int cam_sensor_i2c_command_parser( CAM_ERR(CAM_SENSOR, "Handle slave info failed with rc: %d", rc); - return rc; + goto rel_buf; } cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_info); @@ -418,13 +419,23 @@ int cam_sensor_i2c_command_parser( default: CAM_ERR(CAM_SENSOR, "Invalid Command Type:%d", cmm_hdr->cmd_type); - return -EINVAL; + rc = -EINVAL; + goto rel_buf; } } i2c_reg_settings->is_settings_valid = 1; + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_SENSOR, "put failed for buffer :0x%x", + cmd_desc[i].mem_handle); } return rc; + +rel_buf: + if (cam_mem_put_cpu_buf(cmd_desc[i].mem_handle)) + CAM_WARN(CAM_SENSOR, "put failed for buffer :0x%x", + cmd_desc[i].mem_handle); + return rc; } int cam_sensor_util_i2c_apply_setting( @@ -1811,14 +1822,15 @@ int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl, ctrl->pinctrl_info.gpio_state_suspend); if (ret) CAM_ERR(CAM_SENSOR, "cannot set pin to suspend state"); - cam_res_mgr_shared_pinctrl_select_state(false); devm_pinctrl_put(ctrl->pinctrl_info.pinctrl); - cam_res_mgr_shared_pinctrl_put(); } if (soc_info->use_shared_clk) cam_res_mgr_shared_clk_config(false); + cam_res_mgr_shared_pinctrl_select_state(false); + cam_res_mgr_shared_pinctrl_put(); + ctrl->cam_pinctrl_status = 0; cam_sensor_util_request_gpio_table(soc_info, 0); @@ -1993,14 +2005,15 @@ int cam_sensor_util_power_down(struct cam_sensor_power_ctrl_t *ctrl, if (ret) CAM_ERR(CAM_SENSOR, "cannot set pin to suspend state"); - cam_res_mgr_shared_pinctrl_select_state(false); devm_pinctrl_put(ctrl->pinctrl_info.pinctrl); - cam_res_mgr_shared_pinctrl_put(); } if (soc_info->use_shared_clk) cam_res_mgr_shared_clk_config(false); + cam_res_mgr_shared_pinctrl_select_state(false); + cam_res_mgr_shared_pinctrl_put(); + ctrl->cam_pinctrl_status = 0; cam_sensor_util_request_gpio_table(soc_info, 0); diff --git a/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.c b/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.c index 8e835ec24054..ac81a2f3c47c 100644 --- a/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.c +++ b/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.c @@ -27,7 +27,7 @@ #include "cam_smmu_api.h" #include "cam_debug_util.h" -#define SHARED_MEM_POOL_GRANULARITY 12 +#define SHARED_MEM_POOL_GRANULARITY 16 #define IOMMU_INVALID_DIR -1 #define BYTE_SIZE 8 @@ -530,7 +530,7 @@ static int cam_smmu_iommu_fault_handler(struct iommu_domain *domain, } if (++iommu_cb_set.cb_info[idx].pf_count > g_num_pf_handled) { - CAM_INFO(CAM_SMMU, "PF already handled %d %d %d", + CAM_INFO_RATE_LIMIT(CAM_SMMU, "PF already handled %d %d %d", g_num_pf_handled, idx, iommu_cb_set.cb_info[idx].pf_count); return -EINVAL; @@ -1087,7 +1087,7 @@ static int cam_smmu_free_iova(uint32_t addr, size_t size, int cam_smmu_alloc_firmware(int32_t smmu_hdl, dma_addr_t *iova, - uint64_t *cpuva, + uintptr_t *cpuva, size_t *len) { int rc; @@ -1156,7 +1156,7 @@ int cam_smmu_alloc_firmware(int32_t smmu_hdl, iommu_cb_set.cb_info[idx].is_fw_allocated = true; *iova = iommu_cb_set.cb_info[idx].firmware_info.iova_start; - *cpuva = (uint64_t)icp_fw.fw_kva; + *cpuva = (uintptr_t)icp_fw.fw_kva; *len = firmware_len; mutex_unlock(&iommu_cb_set.cb_info[idx].lock); @@ -1926,6 +1926,25 @@ static enum cam_smmu_buf_state cam_smmu_check_secure_fd_in_list(int idx, { struct cam_sec_buff_info *mapping; + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->ion_fd == ion_fd) { + *paddr_ptr = mapping->paddr; + *len_ptr = mapping->len; + mapping->ref_count++; + return CAM_SMMU_BUFF_EXIST; + } + } + + return CAM_SMMU_BUFF_NOT_EXIST; +} + +static enum cam_smmu_buf_state cam_smmu_validate_secure_fd_in_list(int idx, + int ion_fd, dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + struct cam_sec_buff_info *mapping; + list_for_each_entry(mapping, &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { @@ -2540,6 +2559,16 @@ int cam_smmu_unmap_stage2_iova(int handle, int ion_fd) goto put_addr_end; } + mapping_info->ref_count--; + if (mapping_info->ref_count > 0) { + CAM_DBG(CAM_SMMU, + "idx: %d fd = %d ref_count: %d", + idx, ion_fd, mapping_info->ref_count); + rc = 0; + goto put_addr_end; + } + mapping_info->ref_count = 0; + /* unmapping one buffer from device */ rc = cam_smmu_secure_unmap_buf_and_remove_from_list(mapping_info, idx); if (rc) { @@ -2815,7 +2844,7 @@ int cam_smmu_get_stage2_iova(int handle, int ion_fd, goto get_addr_end; } - buf_state = cam_smmu_check_secure_fd_in_list(idx, + buf_state = cam_smmu_validate_secure_fd_in_list(idx, ion_fd, paddr_ptr, len_ptr); @@ -3111,7 +3140,7 @@ static int cam_smmu_setup_cb(struct cam_context_bank_info *cb, cb->is_fw_allocated = false; cb->is_secheap_allocated = false; - /* Create a pool with 4K granularity for supporting shared memory */ + /* Create a pool with 64K granularity for supporting shared memory */ if (cb->shared_support) { cb->shared_mem_pool = gen_pool_create( SHARED_MEM_POOL_GRANULARITY, -1); diff --git a/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.h b/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.h index 8a2ca5145b3a..8aa80ac8fb4f 100644 --- a/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.h +++ b/drivers/media/platform/msm/ais/cam_smmu/cam_smmu_api.h @@ -47,8 +47,7 @@ enum cam_smmu_region_id { CAM_SMMU_REGION_SCRATCH, CAM_SMMU_REGION_IO, CAM_SMMU_REGION_SECHEAP, - CAM_SMMU_REGION_QDSS, - CAM_SMMU_REGION_INVALID + CAM_SMMU_REGION_QDSS }; /** @@ -318,7 +317,7 @@ int cam_smmu_unmap_stage2_iova(int handle, int ion_fd); */ int cam_smmu_alloc_firmware(int32_t smmu_hdl, dma_addr_t *iova, - uint64_t *kvaddr, + uintptr_t *kvaddr, size_t *len); /** diff --git a/drivers/media/platform/msm/ais/cam_sync/cam_sync.c b/drivers/media/platform/msm/ais/cam_sync/cam_sync.c index 4525bb5bce25..7a772f1c4269 100644 --- a/drivers/media/platform/msm/ais/cam_sync/cam_sync.c +++ b/drivers/media/platform/msm/ais/cam_sync/cam_sync.c @@ -65,7 +65,6 @@ int cam_sync_register_callback(sync_callback cb_func, void *userdata, int32_t sync_obj) { struct sync_callback_info *sync_cb; - struct sync_callback_info *cb_info; struct sync_table_row *row = NULL; int status = 0; @@ -83,17 +82,6 @@ int cam_sync_register_callback(sync_callback cb_func, return -EINVAL; } - /* Don't register if callback was registered earlier */ - list_for_each_entry(cb_info, &row->callback_list, list) { - if (cb_info->callback_func == cb_func && - cb_info->cb_data == userdata) { - CAM_ERR(CAM_SYNC, "Duplicate register for sync_obj %d", - sync_obj); - spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); - return -EALREADY; - } - } - sync_cb = kzalloc(sizeof(*sync_cb), GFP_ATOMIC); if (!sync_cb) { spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); @@ -426,7 +414,7 @@ static int cam_sync_handle_create(struct cam_private_ioctl_arg *k_ioctl) return -EINVAL; if (copy_from_user(&sync_create, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -434,7 +422,8 @@ static int cam_sync_handle_create(struct cam_private_ioctl_arg *k_ioctl) sync_create.name); if (!result) - if (copy_to_user((void *)k_ioctl->ioctl_ptr, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->ioctl_ptr), &sync_create, k_ioctl->size)) return -EFAULT; @@ -453,7 +442,7 @@ static int cam_sync_handle_signal(struct cam_private_ioctl_arg *k_ioctl) return -EINVAL; if (copy_from_user(&sync_signal, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -478,7 +467,7 @@ static int cam_sync_handle_merge(struct cam_private_ioctl_arg *k_ioctl) return -EINVAL; if (copy_from_user(&sync_merge, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -492,8 +481,8 @@ static int cam_sync_handle_merge(struct cam_private_ioctl_arg *k_ioctl) return -ENOMEM; if (copy_from_user(sync_objs, - (void *)sync_merge.sync_objs, - sizeof(uint32_t) * sync_merge.num_objs)) { + u64_to_user_ptr(sync_merge.sync_objs), + sizeof(uint32_t) * sync_merge.num_objs)) { kfree(sync_objs); return -EFAULT; } @@ -505,7 +494,8 @@ static int cam_sync_handle_merge(struct cam_private_ioctl_arg *k_ioctl) &sync_merge.merged); if (!result) - if (copy_to_user((void *)k_ioctl->ioctl_ptr, + if (copy_to_user( + u64_to_user_ptr(k_ioctl->ioctl_ptr), &sync_merge, k_ioctl->size)) { kfree(sync_objs); @@ -528,7 +518,7 @@ static int cam_sync_handle_wait(struct cam_private_ioctl_arg *k_ioctl) return -EINVAL; if (copy_from_user(&sync_wait, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -549,7 +539,7 @@ static int cam_sync_handle_destroy(struct cam_private_ioctl_arg *k_ioctl) return -EINVAL; if (copy_from_user(&sync_create, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -573,7 +563,7 @@ static int cam_sync_handle_register_user_payload( return -EINVAL; if (copy_from_user(&userpayload_info, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; @@ -654,7 +644,7 @@ static int cam_sync_handle_deregister_user_payload( } if (copy_from_user(&userpayload_info, - (void *)k_ioctl->ioctl_ptr, + u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; diff --git a/drivers/media/platform/msm/ais/cam_sync/cam_sync_util.c b/drivers/media/platform/msm/ais/cam_sync/cam_sync_util.c index 0a059184311d..5666218af76e 100644 --- a/drivers/media/platform/msm/ais/cam_sync/cam_sync_util.c +++ b/drivers/media/platform/msm/ais/cam_sync/cam_sync_util.c @@ -178,7 +178,7 @@ int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx) } if (row->state == CAM_SYNC_STATE_ACTIVE) - CAM_WARN(CAM_SYNC, + CAM_DBG(CAM_SYNC, "Destroying an active sync object name:%s id:%i", row->name, row->sync_id); @@ -225,7 +225,7 @@ int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx) } if (child_row->state == CAM_SYNC_STATE_ACTIVE) - CAM_WARN(CAM_SYNC, + CAM_DBG(CAM_SYNC, "Warning: destroying active child sync obj = %d", child_info->sync_id); @@ -254,7 +254,7 @@ int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx) } if (parent_row->state == CAM_SYNC_STATE_ACTIVE) - CAM_WARN(CAM_SYNC, + CAM_DBG(CAM_SYNC, "Warning: destroying active parent sync obj = %d", parent_info->sync_id); diff --git a/drivers/media/platform/msm/ais/cam_utils/cam_common_util.h b/drivers/media/platform/msm/ais/cam_utils/cam_common_util.h index 3e1281b62567..47d441fe3aa1 100644 --- a/drivers/media/platform/msm/ais/cam_utils/cam_common_util.h +++ b/drivers/media/platform/msm/ais/cam_utils/cam_common_util.h @@ -13,8 +13,14 @@ #ifndef _CAM_COMMON_UTIL_H_ #define _CAM_COMMON_UTIL_H_ +#include +#include + #define CAM_BITS_MASK_SHIFT(x, mask, shift) (((x) & (mask)) >> shift) +#define PTR_TO_U64(ptr) ((uint64_t)(uintptr_t)ptr) +#define U64_TO_PTR(ptr) ((void *)(uintptr_t)ptr) + /** * cam_common_util_get_string_index() * diff --git a/drivers/media/platform/msm/ais/cam_utils/cam_packet_util.c b/drivers/media/platform/msm/ais/cam_utils/cam_packet_util.c index f4186d2f9862..66c5b0f5e70f 100644 --- a/drivers/media/platform/msm/ais/cam_utils/cam_packet_util.c +++ b/drivers/media/platform/msm/ais/cam_utils/cam_packet_util.c @@ -21,7 +21,7 @@ int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr, size_t *len) { int rc = 0; - uint64_t kmd_buf_addr = 0; + uintptr_t kmd_buf_addr = 0; rc = cam_mem_get_cpu_buf(handle, &kmd_buf_addr, len); if (rc) { @@ -30,7 +30,7 @@ int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr, if (kmd_buf_addr && *len) { *buf_addr = (uint32_t *)kmd_buf_addr; } else { - CAM_ERR(CAM_UTIL, "Invalid addr and length :%ld", *len); + CAM_ERR(CAM_UTIL, "Invalid addr and length :%zd", *len); rc = -ENOMEM; } } @@ -101,9 +101,10 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, return rc; if (len < cmd_desc->size) { - CAM_ERR(CAM_UTIL, "invalid memory len:%ld and cmd desc size:%d", + CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d", len, cmd_desc->size); - return -EINVAL; + rc = -EINVAL; + goto rel_kmd_buf; } cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4); @@ -120,6 +121,11 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, kmd_buf->size = cmd_desc->size - cmd_desc->length; kmd_buf->used_bytes = 0; +rel_kmd_buf: + if (cam_mem_put_cpu_buf(cmd_desc->mem_handle)) + CAM_WARN(CAM_UTIL, "Put KMD Buf failed for: 0x%x", + cmd_desc->mem_handle); + return rc; } @@ -127,8 +133,8 @@ int cam_packet_util_process_patches(struct cam_packet *packet, int32_t iommu_hdl, int32_t sec_mmu_hdl) { struct cam_patch_desc *patch_desc = NULL; - uint64_t iova_addr; - uint64_t cpu_addr; + dma_addr_t iova_addr; + uintptr_t cpu_addr; uint32_t temp; uint32_t *dst_cpu_addr; uint32_t *src_buf_iova_addr; @@ -147,7 +153,6 @@ int cam_packet_util_process_patches(struct cam_packet *packet, sizeof(struct cam_patch_desc)); for (i = 0; i < packet->num_patches; i++) { - hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ? sec_mmu_hdl : iommu_hdl; rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, @@ -181,6 +186,9 @@ int cam_packet_util_process_patches(struct cam_packet *packet, "patch is done for dst %pK with src %pK value %llx", dst_cpu_addr, src_buf_iova_addr, *((uint64_t *)dst_cpu_addr)); + if (cam_mem_put_cpu_buf(patch_desc[i].dst_buf_hdl)) + CAM_WARN(CAM_UTIL, "unable to put dst buf address:0x%x", + patch_desc[i].dst_buf_hdl); } return rc; @@ -191,7 +199,7 @@ int cam_packet_util_process_generic_cmd_buffer( cam_packet_generic_blob_handler blob_handler_cb, void *user_data) { int rc; - uint64_t cpu_addr; + uintptr_t cpu_addr; size_t buf_size; uint32_t *blob_ptr; uint32_t blob_type, blob_size, blob_block_size, len_read; @@ -215,7 +223,8 @@ int cam_packet_util_process_generic_cmd_buffer( return rc; } - blob_ptr = (uint32_t *)((uint8_t *)cpu_addr + cmd_buf->offset); + blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) + + cmd_buf->offset); CAM_DBG(CAM_UTIL, "GenericCmdBuffer cpuaddr=%pK, blobptr=%pK, len=%d", @@ -243,7 +252,8 @@ int cam_packet_util_process_generic_cmd_buffer( CAM_ERR(CAM_UTIL, "Invalid Blob %d %d %d %d", blob_type, blob_size, len_read, cmd_buf->length); - return -EINVAL; + rc = -EINVAL; + goto rel_cmd_buf; } len_read += blob_block_size; @@ -253,11 +263,16 @@ int cam_packet_util_process_generic_cmd_buffer( if (rc) { CAM_ERR(CAM_UTIL, "Error in handling blob type %d %d", blob_type, blob_size); - return rc; + goto rel_cmd_buf; } blob_ptr += (blob_block_size / sizeof(uint32_t)); } - return 0; +rel_cmd_buf: + if (cam_mem_put_cpu_buf(cmd_buf->mem_handle)) + CAM_WARN(CAM_UTIL, "unable to put dst buf address: 0x%x", + cmd_buf->mem_handle); + + return rc; } -- GitLab From 58142ad6fabf78311edf8be55a1d951d875067f6 Mon Sep 17 00:00:00 2001 From: Terence Ho Date: Wed, 19 Dec 2018 18:41:46 -0500 Subject: [PATCH 0547/1286] msm: ais: fix csiphy settlecount units Remove unnecessary unit conversion in csiphy settlecount. Change-Id: Ic7317539768e4436b9e3d93a42a3f0fe4ccd8823 Signed-off-by: Terence Ho --- .../msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index d015b6572b57..5fe7721aaebd 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -414,12 +414,11 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) continue; } - settle_cnt = (csiphy_dev->csiphy_info.settle_time / 200000000); + settle_cnt = csiphy_dev->csiphy_info.settle_time; if (csiphy_dev->csiphy_info.combo_mode == 1 && (lane_pos >= 3)) settle_cnt = - (csiphy_dev->csiphy_info.settle_time_combo_sensor / - 200000000); + csiphy_dev->csiphy_info.settle_time_combo_sensor; for (i = 0; i < cfg_size; i++) { switch (reg_array[lane_pos][i].csiphy_param_type) { case CSIPHY_LANE_ENABLE: -- GitLab From 63c6d6d9eaa1fed894e537ed31c1c2b1fc1cca3f Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 20 Dec 2018 12:54:52 -0800 Subject: [PATCH 0548/1286] power: qpnp-fg-gen4: add support to register with thermal core framework Add support to register FG driver to register with thermal core framework so that the battery temperature can be monitored by any thermal governor and userspace is one of them. Change-Id: Ib828474cf464d78be4bf843b6b59a6adabe005cf Signed-off-by: Subbaraman Narayanamurthy --- .../power/supply/qcom/qpnp-fg-gen4.txt | 32 +++++++++++++++++++ drivers/power/supply/qcom/fg-core.h | 1 + drivers/power/supply/qcom/qpnp-fg-gen4.c | 31 ++++++++++++++++++ 3 files changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt index d5611757809d..c9ccd156c8f2 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt @@ -29,6 +29,8 @@ First Level Node - FG Gen4 device Definition: Should specify the phandle of PMIC revid module. This is used to identify the PMIC subtype. +- #thermal-sensor-cells: Should be 0. See thermal.txt for the description. + - qcom,fg-cutoff-voltage Usage: optional Value type: @@ -423,6 +425,7 @@ pm8150b_fg: qpnp,fg { #address-cells = <1>; #size-cells = <1>; qcom,pmic-revid = <&pm8150b_revid>; + #thermal-cells = <0>; status = "okay"; qcom,fg-batt-soc@4000 { @@ -487,3 +490,32 @@ pm8150b_fg: qpnp,fg { }; }; + +====================================== +Example for thermal zone configuration +====================================== + +thermal_zones { + pm8150b_fg { + polling-delay-passive = <200>; + polling-delay = <200>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_fg>; + + pm8150b_fg_trip1: pm8150b-fg-trip1 { + temperature = <40000>; + hysteresis = <0>; + type = "passive"; + }; + pm8150b_fg_trip2: pm8150b-fg-trip2 { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + pm8150b_fg_trip3: pm8150b-fg-trip3 { + temperature = <55000>; + hysteresis = <0>; + type = "passive"; + }; + }; +}; diff --git a/drivers/power/supply/qcom/fg-core.h b/drivers/power/supply/qcom/fg-core.h index b6d7a56a9d8a..2bb6ee733fb6 100644 --- a/drivers/power/supply/qcom/fg-core.h +++ b/drivers/power/supply/qcom/fg-core.h @@ -402,6 +402,7 @@ struct fg_memif { }; struct fg_dev { + struct thermal_zone_device *tz_dev; struct device *dev; struct pmic_revid_data *pmic_rev_id; struct regmap *regmap; diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index ea257bd62a13..a1eaf895513c 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "fg-core.h" #include "fg-reg.h" #include "fg-alg.h" @@ -659,6 +660,27 @@ static int fg_gen4_get_battery_temp(struct fg_dev *fg, int *val) return 0; } +static int fg_gen4_tz_get_temp(void *data, int *temperature) +{ + struct fg_dev *fg = (struct fg_dev *)data; + int rc, temp; + + if (!temperature) + return -EINVAL; + + rc = fg_gen4_get_battery_temp(fg, &temp); + if (rc < 0) + return rc; + + /* Convert deciDegC to milliDegC */ + *temperature = temp * 100; + return rc; +} + +static struct thermal_zone_of_device_ops fg_gen4_tz_ops = { + .get_temp = fg_gen4_tz_get_temp, +}; + static int fg_gen4_get_debug_batt_id(struct fg_dev *fg, int *batt_id) { int rc; @@ -4898,6 +4920,15 @@ static int fg_gen4_probe(struct platform_device *pdev) msoc, volt_uv, batt_temp, fg->batt_id_ohms); } + fg->tz_dev = thermal_zone_of_sensor_register(fg->dev, 0, fg, + &fg_gen4_tz_ops); + if (IS_ERR_OR_NULL(fg->tz_dev)) { + rc = PTR_ERR(fg->tz_dev); + fg->tz_dev = NULL; + dev_dbg(fg->dev, "Couldn't register with thermal framework rc:%d\n", + rc); + } + device_init_wakeup(fg->dev, true); if (!fg->battery_missing) schedule_delayed_work(&fg->profile_load_work, 0); -- GitLab From 3cf0cc189093f1352c400031c5bc24ae870b7a7e Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 20 Dec 2018 16:16:03 -0800 Subject: [PATCH 0549/1286] defconfig: sdxprairie: Enable QPNP_REVID driver Enable QPNP_REVID driver to support other client drivers to read PMIC revision information for sdxprairie platforms. Change-Id: I496c9c6387e43a34324664803b5324b7c01ab43b Signed-off-by: Subbaraman Narayanamurthy --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 459b0ea9d637..d94d009a7700 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -286,6 +286,7 @@ CONFIG_DMADEVICES=y CONFIG_UIO=y CONFIG_STAGING=y CONFIG_ION=y +CONFIG_QPNP_REVID=y CONFIG_SPS=y CONFIG_SPS_SUPPORT_NDP_BAM=y CONFIG_USB_BAM=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index b71a40c5c37f..cff5e74130df 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -277,6 +277,7 @@ CONFIG_DMADEVICES=y CONFIG_UIO=y CONFIG_STAGING=y CONFIG_ION=y +CONFIG_QPNP_REVID=y CONFIG_SPS=y CONFIG_SPS_SUPPORT_NDP_BAM=y CONFIG_GSI_REGISTER_VERSION_2=y -- GitLab From 69e29d1ce931808e20dde3c60034c2d2385fd58e Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Wed, 19 Dec 2018 07:43:43 +0530 Subject: [PATCH 0550/1286] sdcardfs: Fix a case where sdcardfs may fail to create a file Test case:- 1. touch /file1 2. In parallel keep dropping the caches. In below sequence:- 1. __sdcardfs_lookup 2. vfs_path_lookup --> returns -ENOENT(since file is not yet present) 3. d_hash_lookup --> if returned NULL, then sdcardfs returns NULL In above sequence of events, sdcardfs has not taken any ref count on lower_dentry while doing vfs_path_lookup. If in case like during low memory situation, if shrink_dcache is invoked then it will remove the dentry from lookup cache. Now when sdcardfs searches for d_hash_lookup, it could not find the dentry and assumes that lower FS did not create it and hence returns and error. To fix this, it should again go via lookup_one_len_unlocked call to see if dentry is really present or not. Change-Id: I58e73e39605bfd5e81dffd878701d3f744514c05 Signed-off-by: Ritesh Harjani --- fs/sdcardfs/lookup.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/fs/sdcardfs/lookup.c b/fs/sdcardfs/lookup.c index 73179ce2591f..a9e28ae8091f 100644 --- a/fs/sdcardfs/lookup.c +++ b/fs/sdcardfs/lookup.c @@ -369,18 +369,13 @@ static struct dentry *__sdcardfs_lookup(struct dentry *dentry, /* See if the low-level filesystem might want * to use its own hash */ - lower_dentry = d_hash_and_lookup(lower_dir_dentry, &dname); + lower_dentry = lookup_one_len_unlocked(dname.name, lower_dir_dentry, + dname.len); if (IS_ERR(lower_dentry)) return lower_dentry; - if (!lower_dentry) { - /* We called vfs_path_lookup earlier, and did not get a negative - * dentry then. Don't confuse the lower filesystem by forcing - * one on it now... - */ + if (d_really_is_negative(lower_dentry)) err = -ENOENT; - goto out; - } lower_path.dentry = lower_dentry; lower_path.mnt = mntget(lower_dir_mnt); -- GitLab From f0ab82bddb6145f5b8858d9a9a9dc29b9c2dd892 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Tue, 27 Nov 2018 09:49:44 +0530 Subject: [PATCH 0551/1286] msm: cam: isp: Add state machine for FS2 State machine is added for FS2 Preview and Snapshot. Change-Id: I3c2f0bf903994ea890e6498983091e721a85f230 Signed-off-by: Suresh Vankadara --- .../msm/camera/cam_isp/cam_isp_context.c | 384 +++++++++++++++++- .../cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 26 +- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 14 +- .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 7 +- 4 files changed, 408 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c index 78e481fa4283..14af855b9327 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c @@ -1228,6 +1228,236 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, return rc; } +static int __cam_isp_ctx_fs2_sof_in_sof_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_req_mgr_trigger_notify notify; + uint64_t request_id = 0; + + + req = list_last_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_SOF, req->request_id); + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + if (!(list_empty(&ctx->wait_req_list))) + goto end; + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + } + + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + break; + } + } + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + rc = -EFAULT; + } + +end: + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + struct cam_context *ctx = ctx_isp->base; + int prev_active_req_cnt = 0; + int curr_req_id = 0; + struct cam_ctx_request *req; + + prev_active_req_cnt = ctx_isp->active_req_cnt; + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + if (req) + curr_req_id = req->request_id; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 0); + + if (prev_active_req_cnt == ctx_isp->active_req_cnt + 1) { + if (list_empty(&ctx->wait_req_list) && + list_empty(&ctx->active_req_list)) { + CAM_DBG(CAM_ISP, "No request, move to SOF"); + ctx_isp->substate_activated = + CAM_ISP_CTX_ACTIVATED_SOF; + if (ctx_isp->reported_req_id < curr_req_id) { + ctx_isp->reported_req_id = curr_req_id; + __cam_isp_ctx_send_sof_timestamp(ctx_isp, + curr_req_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } + } + } + + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done_in_epoch(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + + rc = __cam_isp_ctx_fs2_buf_done(ctx_isp, evt_data); + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done_in_applied( + struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + + rc = __cam_isp_ctx_fs2_buf_done(ctx_isp, evt_data); + return rc; +} + +static int __cam_isp_ctx_fs2_reg_upd_in_sof(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + + if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) { + CAM_DBG(CAM_ISP, "invalid RUP"); + goto end; + } + + /* + * This is for the first update. The initial setting will + * cause the reg_upd in the first frame. + */ + if (!list_empty(&ctx->wait_req_list)) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out == req_isp->num_acked) + list_add_tail(&req->list, &ctx->free_req_list); + else + CAM_ERR(CAM_ISP, + "receive rup in unexpected state"); + } + if (req != NULL) { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, + req->request_id); + } +end: + return rc; +} + +static int __cam_isp_ctx_fs2_reg_upd_in_applied_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_ctx_req *req_isp; + struct cam_req_mgr_trigger_notify notify; + uint64_t request_id = 0; + + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request"); + goto end; + } + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out != 0) { + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d)", + req->request_id, ctx_isp->active_req_cnt); + } else { + /* no io config, so the request is completed. */ + list_add_tail(&req->list, &ctx->free_req_list); + } + + /* + * This function only called directly from applied and bubble applied + * state so change substate here. + */ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; + if (req_isp->num_fence_map_out != 1) + goto end; + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + break; + } + } + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + } + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + rc = -EFAULT; + } + + CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); +end: + if (req != NULL && !rc) { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, + req->request_id); + } + return rc; +} + static struct cam_isp_ctx_irq_ops cam_isp_ctx_activated_state_machine_irq[CAM_ISP_CTX_ACTIVATED_MAX] = { /* SOF */ @@ -1301,6 +1531,79 @@ static struct cam_isp_ctx_irq_ops }, }; +static struct cam_isp_ctx_irq_ops + cam_isp_ctx_fs2_state_machine_irq[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_fs2_sof_in_sof_state, + __cam_isp_ctx_fs2_reg_upd_in_sof, + __cam_isp_ctx_fs2_sof_in_sof_state, + __cam_isp_ctx_notify_eof_in_activated_state, + NULL, + }, + }, + /* APPLIED */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_fs2_reg_upd_in_applied_state, + __cam_isp_ctx_epoch_in_applied, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_fs2_buf_done_in_applied, + }, + }, + /* EPOCH */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_epoch, + __cam_isp_ctx_reg_upd_in_epoch_state, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_fs2_buf_done_in_epoch, + }, + }, + /* BUBBLE */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + NULL, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_buf_done_in_bubble, + }, + }, + /* Bubble Applied */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_activated_state, + __cam_isp_ctx_epoch_in_bubble_applied, + NULL, + __cam_isp_ctx_buf_done_in_bubble_applied, + }, + }, + /* HW ERROR */ + { + .irq_ops = { + NULL, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_hw_error, + NULL, + NULL, + NULL, + }, + }, + /* HALT */ + { + }, +}; + static int __cam_isp_ctx_apply_req_in_activated_state( struct cam_context *ctx, struct cam_req_mgr_apply_request *apply, uint32_t next_state) @@ -1620,6 +1923,58 @@ static struct cam_ctx_ops }, }; +static struct cam_ctx_ops + cam_isp_ctx_fs2_state_machine[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_sof, + }, + .irq_ops = NULL, + }, + /* APPLIED */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* EPOCH */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_epoch, + }, + .irq_ops = NULL, + }, + /* BUBBLE */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_bubble, + }, + .irq_ops = NULL, + }, + /* Bubble Applied */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HW ERROR */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HALT */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, +}; + static int __cam_isp_ctx_rdi_only_sof_in_top_state( struct cam_isp_context *ctx_isp, void *evt_data) { @@ -2424,7 +2779,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, /* Query the context has rdi only resource */ hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; - isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_IS_RDI_ONLY_CONTEXT; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_CTX_TYPE; hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, &hw_cmd_args); @@ -2433,7 +2788,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, goto free_hw; } - if (isp_hw_cmd_args.u.is_rdi_only_context) { + if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_RDI) { /* * this context has rdi only resource assign rdi only * state machine @@ -2444,6 +2799,13 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, cam_isp_ctx_rdi_only_activated_state_machine_irq; ctx_isp->substate_machine = cam_isp_ctx_rdi_only_activated_state_machine; + ctx_isp->rdi_only_context = true; + } else if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_FS2) { + CAM_DBG(CAM_ISP, "FS2 Session has PIX ,RD and RDI"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_fs2_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_fs2_state_machine; } else { CAM_DBG(CAM_ISP, "Session has PIX or PIX and RDI resources"); ctx_isp->substate_machine_irq = @@ -2452,7 +2814,6 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, cam_isp_ctx_activated_state_machine; } - ctx_isp->rdi_only_context = isp_hw_cmd_args.u.is_rdi_only_context; ctx_isp->hw_ctx = param.ctxt_to_hw_map; ctx_isp->hw_acquired = true; ctx_isp->split_acquire = false; @@ -2570,7 +2931,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, /* Query the context has rdi only resource */ hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; - isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_IS_RDI_ONLY_CONTEXT; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_CTX_TYPE; hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, &hw_cmd_args); @@ -2579,7 +2940,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, goto free_hw; } - if (isp_hw_cmd_args.u.is_rdi_only_context) { + if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_RDI) { /* * this context has rdi only resource assign rdi only * state machine @@ -2590,6 +2951,13 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, cam_isp_ctx_rdi_only_activated_state_machine_irq; ctx_isp->substate_machine = cam_isp_ctx_rdi_only_activated_state_machine; + ctx_isp->rdi_only_context = true; + } else if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_FS2) { + CAM_DBG(CAM_ISP, "FS2 Session has PIX ,RD and RDI"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_fs2_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_fs2_state_machine; } else { CAM_DBG(CAM_ISP, "Session has PIX or PIX and RDI resources"); ctx_isp->substate_machine_irq = @@ -2598,16 +2966,14 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, cam_isp_ctx_activated_state_machine; } - ctx_isp->rdi_only_context = isp_hw_cmd_args.u.is_rdi_only_context; ctx_isp->hw_ctx = param.ctxt_to_hw_map; ctx_isp->hw_acquired = true; ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; trace_cam_context_state("ISP", ctx); CAM_DBG(CAM_ISP, - "Acquire success on session_hdl 0x%xs RDI only %d ctx %u", - ctx->session_hdl, - (isp_hw_cmd_args.u.is_rdi_only_context ? 1 : 0), ctx->ctx_id); + "Acquire success on session_hdl 0x%xs ctx_type %d ctx_id %u", + ctx->session_hdl, isp_hw_cmd_args.u.ctx_type, ctx->ctx_id); kfree(acquire_hw_info); return rc; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 7547a1613672..5e72e2d88a2f 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -2220,7 +2220,8 @@ static int cam_isp_blob_bw_update( if (!hw_mgr_res->hw_res[i]) continue; - if (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) + if ((hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) + || (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_RD)) if (i == CAM_ISP_HW_SPLIT_LEFT) { if (camif_l_bw_updated) continue; @@ -3591,6 +3592,7 @@ static int cam_isp_packet_generic_blob_handler(void *user_data, CAM_ERR(CAM_ISP, "FS Update Failed rc: %d", rc); } break; + default: CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); break; @@ -3896,12 +3898,6 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) hw_cmd_args->u.internal_args; switch (isp_hw_cmd_args->cmd_type) { - case CAM_ISP_HW_MGR_CMD_IS_RDI_ONLY_CONTEXT: - if (ctx->is_rdi_only_context) - isp_hw_cmd_args->u.is_rdi_only_context = 1; - else - isp_hw_cmd_args->u.is_rdi_only_context = 0; - break; case CAM_ISP_HW_MGR_CMD_PAUSE_HW: cam_ife_mgr_pause_hw(ctx); break; @@ -3912,6 +3908,14 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) cam_ife_mgr_sof_irq_debug(ctx, isp_hw_cmd_args->u.sof_irq_enable); break; + case CAM_ISP_HW_MGR_CMD_CTX_TYPE: + if (ctx->is_fe_enable) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_FS2; + else if (ctx->is_rdi_only_context) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_RDI; + else + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; + break; default: CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", hw_cmd_args->cmd_type); @@ -4464,7 +4468,8 @@ static int cam_ife_hw_mgr_handle_reg_update( rup_status = hw_res->bottom_half_handler( hw_res, evt_payload); - if (!ife_hwr_mgr_ctx->is_rdi_only_context) + if (ife_hwr_mgr_ctx->is_rdi_only_context == 0 && + ife_hwr_mgr_ctx->is_fe_enable == false) continue; if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) @@ -4807,7 +4812,8 @@ static int cam_ife_hw_mgr_handle_sof( hw_res, evt_payload); /* check if it is rdi only context */ - if (ife_hw_mgr_ctx->is_rdi_only_context) { + if (ife_hw_mgr_ctx->is_fe_enable || + ife_hw_mgr_ctx->is_rdi_only_context) { if (!sof_status && !sof_sent) { cam_ife_mgr_cmd_get_sof_timestamp( ife_hw_mgr_ctx, @@ -4818,7 +4824,7 @@ static int cam_ife_hw_mgr_handle_sof( ife_hw_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); - CAM_DBG(CAM_ISP, "sof_status = %d", + CAM_DBG(CAM_ISP, "RDI sof_status = %d", sof_status); sof_sent = true; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 1a0f1ecab7b6..25103022fdec 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -199,20 +199,28 @@ enum cam_isp_hw_mgr_command { CAM_ISP_HW_MGR_CMD_PAUSE_HW, CAM_ISP_HW_MGR_CMD_RESUME_HW, CAM_ISP_HW_MGR_CMD_SOF_DEBUG, + CAM_ISP_HW_MGR_CMD_CTX_TYPE, CAM_ISP_HW_MGR_CMD_MAX, }; +enum cam_isp_ctx_type { + CAM_ISP_CTX_FS2 = 1, + CAM_ISP_CTX_RDI, + CAM_ISP_CTX_PIX, + CAM_ISP_CTX_MAX, +}; /** * struct cam_isp_hw_cmd_args - Payload for hw manager command * * @cmd_type HW command type - * @get_context Get context type information + * @sof_irq_enable To debug if SOF irq is enabled + * @ctx_type RDI_ONLY, PIX and RDI, or FS2 */ struct cam_isp_hw_cmd_args { - uint32_t cmd_type; + uint32_t cmd_type; union { - uint32_t is_rdi_only_context; uint32_t sof_irq_enable; + uint32_t ctx_type; } u; }; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index dade98e3a6b0..6b123c8d91a5 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -36,6 +36,11 @@ static uint32_t camif_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX] = { 0x00000000, }; +static uint32_t camif_fe_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX] = { + 0x10000056, + 0x00000000, +}; + static uint32_t camif_irq_err_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX] = { 0x0003FC00, 0xEFFF7EBC, @@ -606,7 +611,7 @@ int cam_vfe_start(void *hw_priv, void *start_args, uint32_t arg_size) cam_irq_controller_subscribe_irq( core_info->vfe_irq_controller, CAM_IRQ_PRIORITY_1, - camif_irq_reg_mask, + camif_fe_irq_reg_mask, &core_info->irq_payload, cam_vfe_irq_top_half, cam_ife_mgr_do_tasklet, -- GitLab From 30c64b5a4f2b88de1c69fcc556eb4a1238ad5ac3 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Mon, 13 Nov 2017 07:15:41 +0100 Subject: [PATCH 0552/1286] timer/debug: Change /proc/timer_list from 0444 to 0400 [ Upstream commit 8e7df2b5b7f245c9bd11064712db5cb69044a362 ] While it uses %pK, there's still few reasons to read this file as non-root. Suggested-by: Linus Torvalds Acked-by: Thomas Gleixner Cc: Peter Zijlstra Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- kernel/time/timer_list.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/time/timer_list.c b/kernel/time/timer_list.c index 0e7f5428a148..0ed768b56c60 100644 --- a/kernel/time/timer_list.c +++ b/kernel/time/timer_list.c @@ -389,7 +389,7 @@ static int __init init_timer_list_procfs(void) { struct proc_dir_entry *pe; - pe = proc_create("timer_list", 0444, NULL, &timer_list_fops); + pe = proc_create("timer_list", 0400, NULL, &timer_list_fops); if (!pe) return -ENOMEM; return 0; -- GitLab From 7ff0bcb2cb31602dd347b216f5f70851102d5067 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 4 Dec 2018 17:04:57 +0800 Subject: [PATCH 0553/1286] pinctrl: sunxi: a83t: Fix IRQ offset typo for PH11 commit 478b6767ad26ab86d9ecc341027dd09a87b1f997 upstream. Pin PH11 is used on various A83T board to detect a change in the OTG port's ID pin, as in when an OTG host cable is plugged in. The incorrect offset meant the gpiochip/irqchip was activating the wrong pin for interrupts. Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") Cc: Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c index 6624499eae72..4ada80317a3b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c @@ -568,7 +568,7 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */ }; static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = { -- GitLab From 5f4610fe2ed4351b45c0d82b3246f18b886d26f9 Mon Sep 17 00:00:00 2001 From: Jeff Moyer Date: Tue, 11 Dec 2018 12:37:49 -0500 Subject: [PATCH 0554/1286] aio: fix spectre gadget in lookup_ioctx commit a538e3ff9dabcdf6c3f477a373c629213d1c3066 upstream. Matthew pointed out that the ioctx_table is susceptible to spectre v1, because the index can be controlled by an attacker. The below patch should mitigate the attack for all of the aio system calls. Cc: stable@vger.kernel.org Reported-by: Matthew Wilcox Reported-by: Dan Carpenter Signed-off-by: Jeff Moyer Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- fs/aio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/aio.c b/fs/aio.c index 3a749c3a92e3..a2de58f77338 100644 --- a/fs/aio.c +++ b/fs/aio.c @@ -43,6 +43,7 @@ #include #include +#include #include "internal.h" @@ -1084,6 +1085,7 @@ static struct kioctx *lookup_ioctx(unsigned long ctx_id) if (!table || id >= table->nr) goto out; + id = array_index_nospec(id, table->nr); ctx = rcu_dereference(table->table[id]); if (ctx && ctx->user_id == ctx_id) { if (percpu_ref_tryget_live(&ctx->users)) -- GitLab From b99eaefb6850b38abdd8a2029bbfde08170ec6c9 Mon Sep 17 00:00:00 2001 From: Andrea Arcangeli Date: Fri, 14 Dec 2018 14:17:17 -0800 Subject: [PATCH 0555/1286] userfaultfd: check VM_MAYWRITE was set after verifying the uffd is registered commit 01e881f5a1fca4677e82733061868c6d6ea05ca7 upstream. Calling UFFDIO_UNREGISTER on virtual ranges not yet registered in uffd could trigger an harmless false positive WARN_ON. Check the vma is already registered before checking VM_MAYWRITE to shut off the false positive warning. Link: http://lkml.kernel.org/r/20181206212028.18726-2-aarcange@redhat.com Cc: Fixes: 29ec90660d68 ("userfaultfd: shmem/hugetlbfs: only allow to register VM_MAYWRITE vmas") Signed-off-by: Andrea Arcangeli Reported-by: syzbot+06c7092e7d71218a2c16@syzkaller.appspotmail.com Acked-by: Mike Rapoport Acked-by: Hugh Dickins Acked-by: Peter Xu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- fs/userfaultfd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c index f92e1f2fc846..5f10052d2671 100644 --- a/fs/userfaultfd.c +++ b/fs/userfaultfd.c @@ -1567,7 +1567,6 @@ static int userfaultfd_unregister(struct userfaultfd_ctx *ctx, cond_resched(); BUG_ON(!vma_can_userfault(vma)); - WARN_ON(!(vma->vm_flags & VM_MAYWRITE)); /* * Nothing to do: this vma is already registered into this @@ -1576,6 +1575,8 @@ static int userfaultfd_unregister(struct userfaultfd_ctx *ctx, if (!vma->vm_userfaultfd_ctx.ctx) goto skip; + WARN_ON(!(vma->vm_flags & VM_MAYWRITE)); + if (vma->vm_start > start) start = vma->vm_start; vma_end = min(end, vma->vm_end); -- GitLab From 87d143de94e24bc209b10750b1937d7b5b9ee648 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 10 Dec 2018 19:33:31 +0000 Subject: [PATCH 0556/1286] arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing commit 3238c359acee4ab57f15abb5a82b8ab38a661ee7 upstream. We need to invalidate the caches *before* clearing the buffer via the non-cacheable alias, else in the worst case __dma_flush_area() may write back dirty lines over the top of our nice new zeros. Fixes: dd65a941f6ba ("arm64: dma-mapping: clear buffers allocated with FORCE_CONTIGUOUS flag") Cc: # 4.18.x- Acked-by: Will Deacon Signed-off-by: Robin Murphy Signed-off-by: Catalin Marinas Signed-off-by: Greg Kroah-Hartman --- arch/arm64/mm/dma-mapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 58470b151bc3..ba88b5b68db6 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -633,9 +633,9 @@ static void *__iommu_alloc_attrs(struct device *dev, size_t size, prot, __builtin_return_address(0)); if (addr) { - memset(addr, 0, size); if (!coherent) __dma_flush_area(page_to_virt(page), iosize); + memset(addr, 0, size); } else { iommu_dma_unmap_page(dev, *handle, iosize, 0, attrs); dma_release_from_contiguous(dev, page, -- GitLab From 30d358d804dacc04c095a95ba8584fabca155e83 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Tue, 20 Nov 2018 01:14:00 +0200 Subject: [PATCH 0557/1286] MMC: OMAP: fix broken MMC on OMAP15XX/OMAP5910/OMAP310 commit e8cde625bfe8a714a856e1366bcbb259d7346095 upstream. Since v2.6.22 or so there has been reports [1] about OMAP MMC being broken on OMAP15XX based hardware (OMAP5910 and OMAP310). The breakage seems to have been caused by commit 46a6730e3ff9 ("mmc-omap: Fix omap to use MMC_POWER_ON") that changed clock enabling to be done on MMC_POWER_ON. This can happen multiple times in a row, and on 15XX the hardware doesn't seem to like it and the MMC just stops responding. Fix by memorizing the power mode and do the init only when necessary. Before the patch (on Palm TE): mmc0: new SD card at address b368 mmcblk0: mmc0:b368 SDC 977 MiB mmci-omap mmci-omap.0: command timeout (CMD18) mmci-omap mmci-omap.0: command timeout (CMD13) mmci-omap mmci-omap.0: command timeout (CMD13) mmci-omap mmci-omap.0: command timeout (CMD12) [x 6] mmci-omap mmci-omap.0: command timeout (CMD13) [x 6] mmcblk0: error -110 requesting status mmci-omap mmci-omap.0: command timeout (CMD8) mmci-omap mmci-omap.0: command timeout (CMD18) mmci-omap mmci-omap.0: command timeout (CMD13) mmci-omap mmci-omap.0: command timeout (CMD13) mmci-omap mmci-omap.0: command timeout (CMD12) [x 6] mmci-omap mmci-omap.0: command timeout (CMD13) [x 6] mmcblk0: error -110 requesting status mmcblk0: recovery failed! print_req_error: I/O error, dev mmcblk0, sector 0 Buffer I/O error on dev mmcblk0, logical block 0, async page read mmcblk0: unable to read partition table After the patch: mmc0: new SD card at address b368 mmcblk0: mmc0:b368 SDC 977 MiB mmcblk0: p1 The patch is based on a fix and analysis done by Ladislav Michl. Tested on OMAP15XX/OMAP310 (Palm TE), OMAP1710 (Nokia 770) and OMAP2420 (Nokia N810). [1] https://marc.info/?t=123175197000003&r=1&w=2 Fixes: 46a6730e3ff9 ("mmc-omap: Fix omap to use MMC_POWER_ON") Reported-by: Ladislav Michl Reported-by: Andrzej Zaborowski Tested-by: Ladislav Michl Acked-by: Tony Lindgren Signed-off-by: Aaro Koskinen Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/omap.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index bd49f34d7654..c28c51ad650f 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -104,6 +104,7 @@ struct mmc_omap_slot { unsigned int vdd; u16 saved_con; u16 bus_mode; + u16 power_mode; unsigned int fclk_freq; struct tasklet_struct cover_tasklet; @@ -1157,7 +1158,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) struct mmc_omap_slot *slot = mmc_priv(mmc); struct mmc_omap_host *host = slot->host; int i, dsor; - int clk_enabled; + int clk_enabled, init_stream; mmc_omap_select_slot(slot, 0); @@ -1167,6 +1168,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) slot->vdd = ios->vdd; clk_enabled = 0; + init_stream = 0; switch (ios->power_mode) { case MMC_POWER_OFF: mmc_omap_set_power(slot, 0, ios->vdd); @@ -1174,13 +1176,17 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) case MMC_POWER_UP: /* Cannot touch dsor yet, just power up MMC */ mmc_omap_set_power(slot, 1, ios->vdd); + slot->power_mode = ios->power_mode; goto exit; case MMC_POWER_ON: mmc_omap_fclk_enable(host, 1); clk_enabled = 1; dsor |= 1 << 11; + if (slot->power_mode != MMC_POWER_ON) + init_stream = 1; break; } + slot->power_mode = ios->power_mode; if (slot->bus_mode != ios->bus_mode) { if (slot->pdata->set_bus_mode != NULL) @@ -1196,7 +1202,7 @@ static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) for (i = 0; i < 2; i++) OMAP_MMC_WRITE(host, CON, dsor); slot->saved_con = dsor; - if (ios->power_mode == MMC_POWER_ON) { + if (init_stream) { /* worst case at 400kHz, 80 cycles makes 200 microsecs */ int usecs = 250; @@ -1234,6 +1240,7 @@ static int mmc_omap_new_slot(struct mmc_omap_host *host, int id) slot->host = host; slot->mmc = mmc; slot->id = id; + slot->power_mode = MMC_POWER_UNDEFINED; slot->pdata = &host->pdata->slots[id]; host->slots[id] = slot; -- GitLab From 38ef9c5a931163eb8abf8f1c654d1b13de26f792 Mon Sep 17 00:00:00 2001 From: Alek Du Date: Thu, 6 Dec 2018 17:24:59 +0800 Subject: [PATCH 0558/1286] mmc: sdhci: fix the timeout check window for clock and reset commit b704441e38f645dcfba1348ca3cc1ba43d1a9f31 upstream. We observed some premature timeouts on a virtualization platform, the log is like this: case 1: [159525.255629] mmc1: Internal clock never stabilised. [159525.255818] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [159525.256049] mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00001002 ... [159525.257205] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000fa03 From the clock control register dump, we are pretty sure the clock was stablized. case 2: [ 914.550127] mmc1: Reset 0x2 never completed. [ 914.550321] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [ 914.550608] mmc1: sdhci: Sys addr: 0x00000010 | Version: 0x00001002 After checking the sdhci code, we found the timeout check actually has a little window that the CPU can be scheduled out and when it comes back, the original time set or check is not valid. Fixes: 5a436cc0af62 ("mmc: sdhci: Optimize delay loops") Cc: stable@vger.kernel.org # v4.12+ Signed-off-by: Alek Du Acked-by: Adrian Hunter Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/sdhci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f063fe569339..0edcc2763f3c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -193,8 +193,12 @@ void sdhci_reset(struct sdhci_host *host, u8 mask) timeout = ktime_add_ms(ktime_get(), 100); /* hw clears the bit when it's done */ - while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { - if (ktime_after(ktime_get(), timeout)) { + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) + break; + if (timedout) { pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); sdhci_dumpregs(host); @@ -1417,9 +1421,13 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) /* Wait max 20 ms */ timeout = ktime_add_ms(ktime_get(), 20); - while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) - & SDHCI_CLOCK_INT_STABLE)) { - if (ktime_after(ktime_get(), timeout)) { + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); -- GitLab From c1149b873482a1f2a85659692376103e7d052dde Mon Sep 17 00:00:00 2001 From: Chad Austin Date: Mon, 10 Dec 2018 10:54:52 -0800 Subject: [PATCH 0559/1286] fuse: continue to send FUSE_RELEASEDIR when FUSE_OPEN returns ENOSYS commit 2e64ff154ce6ce9a8dc0f9556463916efa6ff460 upstream. When FUSE_OPEN returns ENOSYS, the no_open bit is set on the connection. Because the FUSE_RELEASE and FUSE_RELEASEDIR paths share code, this incorrectly caused the FUSE_RELEASEDIR request to be dropped and never sent to userspace. Pass an isdir bool to distinguish between FUSE_RELEASE and FUSE_RELEASEDIR inside of fuse_file_put. Fixes: 7678ac50615d ("fuse: support clients that don't implement 'open'") Cc: # v3.14 Signed-off-by: Chad Austin Signed-off-by: Miklos Szeredi Signed-off-by: Greg Kroah-Hartman --- fs/fuse/dir.c | 2 +- fs/fuse/file.c | 21 +++++++++++---------- fs/fuse/fuse_i.h | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 29868c35c19a..d933ecb7a08c 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -1424,7 +1424,7 @@ static int fuse_dir_open(struct inode *inode, struct file *file) static int fuse_dir_release(struct inode *inode, struct file *file) { - fuse_release_common(file, FUSE_RELEASEDIR); + fuse_release_common(file, true); return 0; } diff --git a/fs/fuse/file.c b/fs/fuse/file.c index 47d7a510be5b..52514a64dcd6 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -86,12 +86,12 @@ static void fuse_release_end(struct fuse_conn *fc, struct fuse_req *req) iput(req->misc.release.inode); } -static void fuse_file_put(struct fuse_file *ff, bool sync) +static void fuse_file_put(struct fuse_file *ff, bool sync, bool isdir) { if (refcount_dec_and_test(&ff->count)) { struct fuse_req *req = ff->reserved_req; - if (ff->fc->no_open) { + if (ff->fc->no_open && !isdir) { /* * Drop the release request when client does not * implement 'open' @@ -244,10 +244,11 @@ static void fuse_prepare_release(struct fuse_file *ff, int flags, int opcode) req->in.args[0].value = inarg; } -void fuse_release_common(struct file *file, int opcode) +void fuse_release_common(struct file *file, bool isdir) { struct fuse_file *ff = file->private_data; struct fuse_req *req = ff->reserved_req; + int opcode = isdir ? FUSE_RELEASEDIR : FUSE_RELEASE; fuse_prepare_release(ff, file->f_flags, opcode); @@ -269,7 +270,7 @@ void fuse_release_common(struct file *file, int opcode) * synchronous RELEASE is allowed (and desirable) in this case * because the server can be trusted not to screw up. */ - fuse_file_put(ff, ff->fc->destroy_req != NULL); + fuse_file_put(ff, ff->fc->destroy_req != NULL, isdir); } static int fuse_open(struct inode *inode, struct file *file) @@ -285,7 +286,7 @@ static int fuse_release(struct inode *inode, struct file *file) if (fc->writeback_cache) write_inode_now(inode, 1); - fuse_release_common(file, FUSE_RELEASE); + fuse_release_common(file, false); /* return value is ignored by VFS */ return 0; @@ -299,7 +300,7 @@ void fuse_sync_release(struct fuse_file *ff, int flags) * iput(NULL) is a no-op and since the refcount is 1 and everything's * synchronous, we are fine with not doing igrab() here" */ - fuse_file_put(ff, true); + fuse_file_put(ff, true, false); } EXPORT_SYMBOL_GPL(fuse_sync_release); @@ -804,7 +805,7 @@ static void fuse_readpages_end(struct fuse_conn *fc, struct fuse_req *req) put_page(page); } if (req->ff) - fuse_file_put(req->ff, false); + fuse_file_put(req->ff, false, false); } static void fuse_send_readpages(struct fuse_req *req, struct file *file) @@ -1458,7 +1459,7 @@ static void fuse_writepage_free(struct fuse_conn *fc, struct fuse_req *req) __free_page(req->pages[i]); if (req->ff) - fuse_file_put(req->ff, false); + fuse_file_put(req->ff, false, false); } static void fuse_writepage_finish(struct fuse_conn *fc, struct fuse_req *req) @@ -1615,7 +1616,7 @@ int fuse_write_inode(struct inode *inode, struct writeback_control *wbc) ff = __fuse_write_file_get(fc, fi); err = fuse_flush_times(inode, ff); if (ff) - fuse_file_put(ff, 0); + fuse_file_put(ff, false, false); return err; } @@ -1929,7 +1930,7 @@ static int fuse_writepages(struct address_space *mapping, err = 0; } if (data.ff) - fuse_file_put(data.ff, false); + fuse_file_put(data.ff, false, false); kfree(data.orig_pages); out: diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index e105640153ce..e682f2eff6c0 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -739,7 +739,7 @@ void fuse_sync_release(struct fuse_file *ff, int flags); /** * Send RELEASE or RELEASEDIR request */ -void fuse_release_common(struct file *file, int opcode); +void fuse_release_common(struct file *file, bool isdir); /** * Send FSYNC or FSYNCDIR request -- GitLab From 529571392b7a3efb91d12d70551ece5c0e60ece6 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 2 Dec 2018 12:12:24 +0100 Subject: [PATCH 0560/1286] ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt commit 76f4e2c3b6a560cdd7a75b87df543e04d05a9e5f upstream. cpu_is_mmp2() was equivalent to cpu_is_pj4(), wouldn't be correct for multiplatform kernels. Fix it by also considering mmp_chip_id, as is done for cpu_is_pxa168() and cpu_is_pxa910() above. Moreover, it is only available with CONFIG_CPU_MMP2 and thus doesn't work on DT-based MMP2 machines. Enable it on CONFIG_MACH_MMP2_DT too. Note: CONFIG_CPU_MMP2 is only used for machines that use board files instead of DT. It should perhaps be renamed. I'm not doing it now, because I don't have a better idea. Signed-off-by: Lubomir Rintel Acked-by: Arnd Bergmann Cc: stable@vger.kernel.org Signed-off-by: Olof Johansson Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-mmp/cputype.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mmp/cputype.h b/arch/arm/mach-mmp/cputype.h index 446edaeb78a7..a96abcf521b4 100644 --- a/arch/arm/mach-mmp/cputype.h +++ b/arch/arm/mach-mmp/cputype.h @@ -44,10 +44,12 @@ static inline int cpu_is_pxa910(void) #define cpu_is_pxa910() (0) #endif -#ifdef CONFIG_CPU_MMP2 +#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT) static inline int cpu_is_mmp2(void) { - return (((read_cpuid_id() >> 8) & 0xff) == 0x58); + return (((read_cpuid_id() >> 8) & 0xff) == 0x58) && + (((mmp_chip_id & 0xfff) == 0x410) || + ((mmp_chip_id & 0xfff) == 0x610)); } #else #define cpu_is_mmp2() (0) -- GitLab From cd5d8a9203ed16bfb16a03c570fb4cf7e7899125 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Tue, 11 Dec 2018 13:31:40 -0500 Subject: [PATCH 0561/1286] dm thin: send event about thin-pool state change _after_ making it commit f6c367585d0d851349d3a9e607c43e5bea993fa1 upstream. Sending a DM event before a thin-pool state change is about to happen is a bug. It wasn't realized until it became clear that userspace response to the event raced with the actual state change that the event was meant to notify about. Fix this by first updating internal thin-pool state to reflect what the DM event is being issued about. This fixes a long-standing racey/buggy userspace device-mapper-test-suite 'resize_io' test that would get an event but not find the state it was looking for -- so it would just go on to hang because no other events caused the test to reevaluate the thin-pool's state. Cc: stable@vger.kernel.org Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-thin.c | 68 +++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 33 deletions(-) diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index 699c40c7fe60..da98fc7b995c 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -195,7 +195,7 @@ static void throttle_unlock(struct throttle *t) struct dm_thin_new_mapping; /* - * The pool runs in 4 modes. Ordered in degraded order for comparisons. + * The pool runs in various modes. Ordered in degraded order for comparisons. */ enum pool_mode { PM_WRITE, /* metadata may be changed */ @@ -281,9 +281,38 @@ struct pool { struct dm_bio_prison_cell **cell_sort_array; }; -static enum pool_mode get_pool_mode(struct pool *pool); static void metadata_operation_failed(struct pool *pool, const char *op, int r); +static enum pool_mode get_pool_mode(struct pool *pool) +{ + return pool->pf.mode; +} + +static void notify_of_pool_mode_change(struct pool *pool) +{ + const char *descs[] = { + "write", + "out-of-data-space", + "read-only", + "read-only", + "fail" + }; + const char *extra_desc = NULL; + enum pool_mode mode = get_pool_mode(pool); + + if (mode == PM_OUT_OF_DATA_SPACE) { + if (!pool->pf.error_if_no_space) + extra_desc = " (queue IO)"; + else + extra_desc = " (error IO)"; + } + + dm_table_event(pool->ti->table); + DMINFO("%s: switching pool to %s%s mode", + dm_device_name(pool->pool_md), + descs[(int)mode], extra_desc ? : ""); +} + /* * Target context for a pool. */ @@ -2362,8 +2391,6 @@ static void do_waker(struct work_struct *ws) queue_delayed_work(pool->wq, &pool->waker, COMMIT_PERIOD); } -static void notify_of_pool_mode_change_to_oods(struct pool *pool); - /* * We're holding onto IO to allow userland time to react. After the * timeout either the pool will have been resized (and thus back in @@ -2376,7 +2403,7 @@ static void do_no_space_timeout(struct work_struct *ws) if (get_pool_mode(pool) == PM_OUT_OF_DATA_SPACE && !pool->pf.error_if_no_space) { pool->pf.error_if_no_space = true; - notify_of_pool_mode_change_to_oods(pool); + notify_of_pool_mode_change(pool); error_retry_list_with_code(pool, BLK_STS_NOSPC); } } @@ -2444,26 +2471,6 @@ static void noflush_work(struct thin_c *tc, void (*fn)(struct work_struct *)) /*----------------------------------------------------------------*/ -static enum pool_mode get_pool_mode(struct pool *pool) -{ - return pool->pf.mode; -} - -static void notify_of_pool_mode_change(struct pool *pool, const char *new_mode) -{ - dm_table_event(pool->ti->table); - DMINFO("%s: switching pool to %s mode", - dm_device_name(pool->pool_md), new_mode); -} - -static void notify_of_pool_mode_change_to_oods(struct pool *pool) -{ - if (!pool->pf.error_if_no_space) - notify_of_pool_mode_change(pool, "out-of-data-space (queue IO)"); - else - notify_of_pool_mode_change(pool, "out-of-data-space (error IO)"); -} - static bool passdown_enabled(struct pool_c *pt) { return pt->adjusted_pf.discard_passdown; @@ -2512,8 +2519,6 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode) switch (new_mode) { case PM_FAIL: - if (old_mode != new_mode) - notify_of_pool_mode_change(pool, "failure"); dm_pool_metadata_read_only(pool->pmd); pool->process_bio = process_bio_fail; pool->process_discard = process_bio_fail; @@ -2527,8 +2532,6 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode) case PM_OUT_OF_METADATA_SPACE: case PM_READ_ONLY: - if (!is_read_only_pool_mode(old_mode)) - notify_of_pool_mode_change(pool, "read-only"); dm_pool_metadata_read_only(pool->pmd); pool->process_bio = process_bio_read_only; pool->process_discard = process_bio_success; @@ -2549,8 +2552,6 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode) * alarming rate. Adjust your low water mark if you're * frequently seeing this mode. */ - if (old_mode != new_mode) - notify_of_pool_mode_change_to_oods(pool); pool->out_of_data_space = true; pool->process_bio = process_bio_read_only; pool->process_discard = process_discard_bio; @@ -2563,8 +2564,6 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode) break; case PM_WRITE: - if (old_mode != new_mode) - notify_of_pool_mode_change(pool, "write"); if (old_mode == PM_OUT_OF_DATA_SPACE) cancel_delayed_work_sync(&pool->no_space_timeout); pool->out_of_data_space = false; @@ -2584,6 +2583,9 @@ static void set_pool_mode(struct pool *pool, enum pool_mode new_mode) * doesn't cause an unexpected mode transition on resume. */ pt->adjusted_pf.mode = new_mode; + + if (old_mode != new_mode) + notify_of_pool_mode_change(pool); } static void abort_transaction(struct pool *pool) -- GitLab From d17cc664f1ebc528b11a8db74c5b84910bf4ab14 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Fri, 9 Nov 2018 11:56:03 -0500 Subject: [PATCH 0562/1286] dm cache metadata: verify cache has blocks in blocks_are_clean_separate_dirty() commit 687cf4412a343a63928a5c9d91bdc0f522939d43 upstream. Otherwise dm_bitset_cursor_begin() return -ENODATA. Other calls to dm_bitset_cursor_begin() have similar negative checks. Fixes inability to create a cache in passthrough mode (even though doing so makes no sense). Fixes: 0d963b6e65 ("dm cache metadata: fix metadata2 format's blocks_are_clean_separate_dirty") Cc: stable@vger.kernel.org Reported-by: David Teigland Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-cache-metadata.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/md/dm-cache-metadata.c b/drivers/md/dm-cache-metadata.c index 7f1c64c4ad24..bc60db87e6f1 100644 --- a/drivers/md/dm-cache-metadata.c +++ b/drivers/md/dm-cache-metadata.c @@ -929,6 +929,10 @@ static int blocks_are_clean_separate_dirty(struct dm_cache_metadata *cmd, bool dirty_flag; *result = true; + if (from_cblock(cmd->cache_blocks) == 0) + /* Nothing to do */ + return 0; + r = dm_bitset_cursor_begin(&cmd->dirty_info, cmd->dirty_root, from_cblock(cmd->cache_blocks), &cmd->dirty_cursor); if (r) { -- GitLab From b2e08ad9d4cb0d2c6776ff0a73903084ddc7588b Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Sun, 9 Dec 2018 21:17:30 -0500 Subject: [PATCH 0563/1286] tracing: Fix memory leak in set_trigger_filter() commit 3cec638b3d793b7cacdec5b8072364b41caeb0e1 upstream. When create_event_filter() fails in set_trigger_filter(), the filter may still be allocated and needs to be freed. The caller expects the data->filter to be updated with the new filter, even if the new filter failed (we could add an error message by setting set_str parameter of create_event_filter(), but that's another update). But because the error would just exit, filter was left hanging and nothing could free it. Found by kmemleak detector. Cc: stable@vger.kernel.org Fixes: bac5fb97a173a ("tracing: Add and use generic set_trigger_filter() implementation") Reviewed-by: Tom Zanussi Signed-off-by: Steven Rostedt (VMware) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/trace_events_trigger.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/trace/trace_events_trigger.c b/kernel/trace/trace_events_trigger.c index 43254c5e7e16..e2da180ca172 100644 --- a/kernel/trace/trace_events_trigger.c +++ b/kernel/trace/trace_events_trigger.c @@ -744,8 +744,10 @@ int set_trigger_filter(char *filter_str, /* The filter is for the 'trigger' event, not the triggered event */ ret = create_event_filter(file->event_call, filter_str, false, &filter); - if (ret) - goto out; + /* + * If create_event_filter() fails, filter still needs to be freed. + * Which the calling code will do with data->filter. + */ assign: tmp = rcu_access_pointer(data->filter); -- GitLab From a28d5f3d9c08a160801754804490dbac4ef9e2e1 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Mon, 10 Dec 2018 23:58:01 -0500 Subject: [PATCH 0564/1286] tracing: Fix memory leak of instance function hash filters commit 2840f84f74035e5a535959d5f17269c69fa6edc5 upstream. The following commands will cause a memory leak: # cd /sys/kernel/tracing # mkdir instances/foo # echo schedule > instance/foo/set_ftrace_filter # rmdir instances/foo The reason is that the hashes that hold the filters to set_ftrace_filter and set_ftrace_notrace are not freed if they contain any data on the instance and the instance is removed. Found by kmemleak detector. Cc: stable@vger.kernel.org Fixes: 591dffdade9f ("ftrace: Allow for function tracing instance to filter functions") Signed-off-by: Steven Rostedt (VMware) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/ftrace.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 7379bcf3baa0..9937d7cf2a64 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -5534,6 +5534,7 @@ void ftrace_destroy_filter_files(struct ftrace_ops *ops) if (ops->flags & FTRACE_OPS_FL_ENABLED) ftrace_shutdown(ops, 0); ops->flags |= FTRACE_OPS_FL_DELETED; + ftrace_free_filter(ops); mutex_unlock(&ftrace_lock); } -- GitLab From e89aa818353bccf626c317f0dee0d1cd7cdc6772 Mon Sep 17 00:00:00 2001 From: Radu Rendec Date: Tue, 27 Nov 2018 22:20:48 -0500 Subject: [PATCH 0565/1286] powerpc/msi: Fix NULL pointer access in teardown code commit 78e7b15e17ac175e7eed9e21c6f92d03d3b0a6fa upstream. The arch_teardown_msi_irqs() function assumes that controller ops pointers were already checked in arch_setup_msi_irqs(), but this assumption is wrong: arch_teardown_msi_irqs() can be called even when arch_setup_msi_irqs() returns an error (-ENOSYS). This can happen in the following scenario: - msi_capability_init() calls pci_msi_setup_msi_irqs() - pci_msi_setup_msi_irqs() returns -ENOSYS - msi_capability_init() notices the error and calls free_msi_irqs() - free_msi_irqs() calls pci_msi_teardown_msi_irqs() This is easier to see when CONFIG_PCI_MSI_IRQ_DOMAIN is not set and pci_msi_setup_msi_irqs() and pci_msi_teardown_msi_irqs() are just aliases to arch_setup_msi_irqs() and arch_teardown_msi_irqs(). The call to free_msi_irqs() upon pci_msi_setup_msi_irqs() failure seems legit, as it does additional cleanup; e.g. list_del(&entry->list) and kfree(entry) inside free_msi_irqs() do happen (MSI descriptors are allocated before pci_msi_setup_msi_irqs() is called and need to be cleaned up if that fails). Fixes: 6b2fd7efeb88 ("PCI/MSI/PPC: Remove arch_msi_check_device()") Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: Radu Rendec Signed-off-by: Michael Ellerman Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/kernel/msi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/msi.c b/arch/powerpc/kernel/msi.c index dab616a33b8d..f2197654be07 100644 --- a/arch/powerpc/kernel/msi.c +++ b/arch/powerpc/kernel/msi.c @@ -34,5 +34,10 @@ void arch_teardown_msi_irqs(struct pci_dev *dev) { struct pci_controller *phb = pci_bus_to_host(dev->bus); - phb->controller_ops.teardown_msi_irqs(dev); + /* + * We can be called even when arch_setup_msi_irqs() returns -ENOSYS, + * so check the pointer again. + */ + if (phb->controller_ops.teardown_msi_irqs) + phb->controller_ops.teardown_msi_irqs(dev); } -- GitLab From d0a954cbfbd09c9106192f880dbe52bf448f11a8 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Tue, 11 Dec 2018 18:56:20 -0500 Subject: [PATCH 0566/1286] drm/nouveau/kms: Fix memory leak in nv50_mstm_del() commit 24199c5436f267399afed0c4f1f57663c0408f57 upstream. Noticed this while working on redoing the reference counting scheme in the DP MST helpers. Nouveau doesn't attempt to call drm_dp_mst_topology_mgr_destroy() at all, which leaves it leaking all of the resources for drm_dp_mst_topology_mgr and it's children mstbs+ports. Fixes: f479c0ba4a17 ("drm/nouveau/kms/nv50: initial support for DP 1.2 multi-stream") Signed-off-by: Lyude Paul Cc: # v4.10+ Signed-off-by: Ben Skeggs Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/nouveau/nv50_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 926ec51ba5be..25f6a1f6ce20 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -3378,6 +3378,7 @@ nv50_mstm_del(struct nv50_mstm **pmstm) { struct nv50_mstm *mstm = *pmstm; if (mstm) { + drm_dp_mst_topology_mgr_destroy(&mstm->mgr); kfree(*pmstm); *pmstm = NULL; } -- GitLab From 8b1bdb94166862ac57b5a1f39d8e293265326e58 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 5 Dec 2018 10:16:57 -0800 Subject: [PATCH 0567/1286] Revert "drm/rockchip: Allow driver to be shutdown on reboot/kexec" commit 63238173b2faf3d6b85a416f1c69af6c7be2413f upstream. This reverts commit 7f3ef5dedb146e3d5063b6845781ad1bb59b92b5. It causes new warnings [1] on shutdown when running the Google Kevin or Scarlet (RK3399) boards under Chrome OS. Presumably our usage of DRM is different than what Marc and Heiko test. We're looking at a different approach (e.g., [2]) to replace this, but IMO the revert should be taken first, as it already propagated to -stable. [1] Report here: http://lkml.kernel.org/lkml/20181205030127.GA200921@google.com WARNING: CPU: 4 PID: 2035 at drivers/gpu/drm/drm_mode_config.c:477 drm_mode_config_cleanup+0x1c4/0x294 ... Call trace: drm_mode_config_cleanup+0x1c4/0x294 rockchip_drm_unbind+0x4c/0x8c component_master_del+0x88/0xb8 rockchip_drm_platform_remove+0x2c/0x44 rockchip_drm_platform_shutdown+0x20/0x2c platform_drv_shutdown+0x2c/0x38 device_shutdown+0x164/0x1b8 kernel_restart_prepare+0x40/0x48 kernel_restart+0x20/0x68 ... Memory manager not clean during takedown. WARNING: CPU: 4 PID: 2035 at drivers/gpu/drm/drm_mm.c:950 drm_mm_takedown+0x34/0x44 ... drm_mm_takedown+0x34/0x44 rockchip_drm_unbind+0x64/0x8c component_master_del+0x88/0xb8 rockchip_drm_platform_remove+0x2c/0x44 rockchip_drm_platform_shutdown+0x20/0x2c platform_drv_shutdown+0x2c/0x38 device_shutdown+0x164/0x1b8 kernel_restart_prepare+0x40/0x48 kernel_restart+0x20/0x68 ... [2] https://patchwork.kernel.org/patch/10556151/ https://www.spinics.net/lists/linux-rockchip/msg21342.html [PATCH] drm/rockchip: shutdown drm subsystem on shutdown Fixes: 7f3ef5dedb14 ("drm/rockchip: Allow driver to be shutdown on reboot/kexec") Cc: Jeffy Chen Cc: Robin Murphy Cc: Vicente Bergas Cc: Marc Zyngier Cc: Heiko Stuebner Cc: stable@vger.kernel.org Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20181205181657.177703-1-briannorris@chromium.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 4cacb03f6733..ff3d0f5efbb1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -425,11 +425,6 @@ static int rockchip_drm_platform_remove(struct platform_device *pdev) return 0; } -static void rockchip_drm_platform_shutdown(struct platform_device *pdev) -{ - rockchip_drm_platform_remove(pdev); -} - static const struct of_device_id rockchip_drm_dt_ids[] = { { .compatible = "rockchip,display-subsystem", }, { /* sentinel */ }, @@ -439,7 +434,6 @@ MODULE_DEVICE_TABLE(of, rockchip_drm_dt_ids); static struct platform_driver rockchip_drm_platform_driver = { .probe = rockchip_drm_platform_probe, .remove = rockchip_drm_platform_remove, - .shutdown = rockchip_drm_platform_shutdown, .driver = { .name = "rockchip-drm", .of_match_table = rockchip_drm_dt_ids, -- GitLab From 8a20046277e31905a1be1dc159f81668bc871d8c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 6 Dec 2018 08:44:31 +0000 Subject: [PATCH 0568/1286] drm/i915/execlists: Apply a full mb before execution for Braswell commit cf66b8a0ba142fbd1bf10ac8f3ae92d1b0cb7b8f upstream. Braswell is really picky about having our writes posted to memory before we execute or else the GPU may see stale values. A wmb() is insufficient as it only ensures the writes are visible to other cores, we need a full mb() to ensure the writes are in memory and visible to the GPU. The most frequent failure in flushing before execution is that we see stale PTE values and execute the wrong pages. References: 987abd5c62f9 ("drm/i915/execlists: Force write serialisation into context image vs execution") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: stable@vger.kernel.org Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20181206084431.9805-3-chris@chris-wilson.co.uk (cherry picked from commit 490b8c65b9db45896769e1095e78725775f47b3e) Signed-off-by: Joonas Lahtinen Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/intel_lrc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0775e71ea95b..e0483c068d23 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -343,8 +343,13 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq) * may not be visible to the HW prior to the completion of the UC * register write and that we may begin execution from the context * before its image is complete leading to invalid PD chasing. + * + * Furthermore, Braswell, at least, wants a full mb to be sure that + * the writes are coherent in memory (visible to the GPU) prior to + * execution, and not just visible to other CPUs (as is the result of + * wmb). */ - wmb(); + mb(); return ce->lrc_desc; } -- GitLab From c8626858b2d873e2528d3099b896459947996247 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 7 Dec 2018 15:15:03 +0800 Subject: [PATCH 0569/1286] drm/amdgpu: update SMC firmware image for polaris10 variants commit d55d8be0747c96db28a1d08fc24d22ccd9b448ac upstream. Some new variants require different firmwares. Signed-off-by: Junwei Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index e8d9479615c9..bb4b804255a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -723,7 +723,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, (adev->pdev->revision == 0xe7) || (adev->pdev->revision == 0xef))) || ((adev->pdev->device == 0x6fdf) && - (adev->pdev->revision == 0xef))) { + ((adev->pdev->revision == 0xef) || + (adev->pdev->revision == 0xff)))) { info->is_kicker = true; strcpy(fw_name, "amdgpu/polaris10_k_smc.bin"); } else -- GitLab From f02ef68bdad39ebf881f64cab027e8696fe57ade Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Dec 2018 15:27:19 +0900 Subject: [PATCH 0570/1286] x86/build: Fix compiler support check for CONFIG_RETPOLINE commit 25896d073d8a0403b07e6dec56f58e6c33678207 upstream. It is troublesome to add a diagnostic like this to the Makefile parse stage because the top-level Makefile could be parsed with a stale include/config/auto.conf. Once you are hit by the error about non-retpoline compiler, the compilation still breaks even after disabling CONFIG_RETPOLINE. The easiest fix is to move this check to the "archprepare" like this commit did: 829fe4aa9ac1 ("x86: Allow generating user-space headers without a compiler") Reported-by: Meelis Roos Tested-by: Meelis Roos Signed-off-by: Masahiro Yamada Acked-by: Zhenzhong Duan Cc: Borislav Petkov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Zhenzhong Duan Fixes: 4cd24de3a098 ("x86/retpoline: Make CONFIG_RETPOLINE depend on compiler support") Link: http://lkml.kernel.org/r/1543991239-18476-1-git-send-email-yamada.masahiro@socionext.com Link: https://lkml.org/lkml/2018/12/4/206 Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin Cc: Gi-Oh Kim Signed-off-by: Greg Kroah-Hartman --- arch/x86/Makefile | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/Makefile b/arch/x86/Makefile index ce3658dd98e8..c5290aecdf06 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -241,9 +241,6 @@ KBUILD_CFLAGS += -fno-asynchronous-unwind-tables # Avoid indirect branches in kernel to deal with Spectre ifdef CONFIG_RETPOLINE -ifeq ($(RETPOLINE_CFLAGS),) - $(error You are building kernel with non-retpoline compiler, please update your compiler.) -endif KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) endif @@ -260,6 +257,13 @@ archprepare: ifeq ($(CONFIG_KEXEC_FILE),y) $(Q)$(MAKE) $(build)=arch/x86/purgatory arch/x86/purgatory/kexec-purgatory.c endif +ifdef CONFIG_RETPOLINE +ifeq ($(RETPOLINE_CFLAGS),) + @echo "You are building kernel with non-retpoline compiler." >&2 + @echo "Please update your compiler." >&2 + @false +endif +endif ### # Kernel objects -- GitLab From a9febd662cee68712aea69012944df00033d2dd8 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 18 Dec 2018 18:13:51 +0100 Subject: [PATCH 0571/1286] locking: Remove smp_read_barrier_depends() from queued_spin_lock_slowpath() commit 548095dea63ffc016d39c35b32c628d033638aca upstream. Queued spinlocks are not used by DEC Alpha, and furthermore operations such as READ_ONCE() and release/relaxed RMW atomics are being changed to imply smp_read_barrier_depends(). This commit therefore removes the now-redundant smp_read_barrier_depends() from queued_spin_lock_slowpath(), and adjusts the comments accordingly. Signed-off-by: Paul E. McKenney Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 50dc42aeaa56..5541acb79e15 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -170,7 +170,7 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) * @tail : The new queue tail code word * Return: The previous queue tail code word * - * xchg(lock, tail) + * xchg(lock, tail), which heads an address dependency * * p,*,* -> n,*,* ; prev = xchg(lock, node) */ @@ -417,13 +417,11 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) if (old & _Q_TAIL_MASK) { prev = decode_tail(old); /* - * The above xchg_tail() is also a load of @lock which generates, - * through decode_tail(), a pointer. - * - * The address dependency matches the RELEASE of xchg_tail() - * such that the access to @prev must happen after. + * The above xchg_tail() is also a load of @lock which + * generates, through decode_tail(), a pointer. The address + * dependency matches the RELEASE of xchg_tail() such that + * the subsequent access to @prev happens after. */ - smp_read_barrier_depends(); WRITE_ONCE(prev->next, node); -- GitLab From 13f14c36323d71e2178d7d97dc65808c0e5c872e Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:52 +0100 Subject: [PATCH 0572/1286] locking/qspinlock: Ensure node is initialised before updating prev->next commit 95bcade33a8af38755c9b0636e36a36ad3789fe6 upstream. When a locker ends up queuing on the qspinlock locking slowpath, we initialise the relevant mcs node and publish it indirectly by updating the tail portion of the lock word using xchg_tail. If we find that there was a pre-existing locker in the queue, we subsequently update their ->next field to point at our node so that we are notified when it's our turn to take the lock. This can be roughly illustrated as follows: /* Initialise the fields in node and encode a pointer to node in tail */ tail = initialise_node(node); /* * Exchange tail into the lockword using an atomic read-modify-write * operation with release semantics */ old = xchg_tail(lock, tail); /* If there was a pre-existing waiter ... */ if (old & _Q_TAIL_MASK) { prev = decode_tail(old); smp_read_barrier_depends(); /* ... then update their ->next field to point to node. WRITE_ONCE(prev->next, node); } The conditional update of prev->next therefore relies on the address dependency from the result of xchg_tail ensuring order against the prior initialisation of node. However, since the release semantics of the xchg_tail operation apply only to the write portion of the RmW, then this ordering is not guaranteed and it is possible for the CPU to return old before the writes to node have been published, consequently allowing us to point prev->next to an uninitialised node. This patch fixes the problem by making the update of prev->next a RELEASE operation, which also removes the reliance on dependency ordering. Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1518528177-19169-2-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 5541acb79e15..d880296245c5 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -416,14 +416,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) */ if (old & _Q_TAIL_MASK) { prev = decode_tail(old); + /* - * The above xchg_tail() is also a load of @lock which - * generates, through decode_tail(), a pointer. The address - * dependency matches the RELEASE of xchg_tail() such that - * the subsequent access to @prev happens after. + * We must ensure that the stores to @node are observed before + * the write to prev->next. The address dependency from + * xchg_tail is not sufficient to ensure this because the read + * component of xchg_tail is unordered with respect to the + * initialisation of @node. */ - - WRITE_ONCE(prev->next, node); + smp_store_release(&prev->next, node); pv_wait_node(node, prev); arch_mcs_spin_lock_contended(&node->locked); -- GitLab From 3dab30f33814dc0b97c001921d3d724004c09b5f Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:53 +0100 Subject: [PATCH 0573/1286] locking/qspinlock: Bound spinning on pending->locked transition in slowpath commit 6512276d97b160d90b53285bd06f7f201459a7e3 upstream. If a locker taking the qspinlock slowpath reads a lock value indicating that only the pending bit is set, then it will spin whilst the concurrent pending->locked transition takes effect. Unfortunately, there is no guarantee that such a transition will ever be observed since concurrent lockers could continuously set pending and hand over the lock amongst themselves, leading to starvation. Whilst this would probably resolve in practice, it means that it is not possible to prove liveness properties about the lock and means that lock acquisition time is unbounded. Rather than removing the pending->locked spinning from the slowpath altogether (which has been shown to heavily penalise a 2-threaded locking stress test on x86), this patch replaces the explicit spinning with a call to atomic_cond_read_relaxed and allows the architecture to provide a bound on the number of spins. For architectures that can respond to changes in cacheline state in their smp_cond_load implementation, it should be sufficient to use the default bound of 1. Suggested-by: Waiman Long Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Cc: Linus Torvalds Cc: Thomas Gleixner Cc: boqun.feng@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1524738868-31318-4-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index d880296245c5..18161264227a 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -76,6 +76,18 @@ #define MAX_NODES 4 #endif +/* + * The pending bit spinning loop count. + * This heuristic is used to limit the number of lockword accesses + * made by atomic_cond_read_relaxed when waiting for the lock to + * transition out of the "== _Q_PENDING_VAL" state. We don't spin + * indefinitely because there's no guarantee that we'll make forward + * progress. + */ +#ifndef _Q_PENDING_LOOPS +#define _Q_PENDING_LOOPS 1 +#endif + /* * Per-CPU queue node structures; we can never have more than 4 nested * contexts: task, softirq, hardirq, nmi. @@ -306,13 +318,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) return; /* - * wait for in-progress pending->locked hand-overs + * Wait for in-progress pending->locked hand-overs with a bounded + * number of spins so that we guarantee forward progress. * * 0,1,0 -> 0,0,1 */ if (val == _Q_PENDING_VAL) { - while ((val = atomic_read(&lock->val)) == _Q_PENDING_VAL) - cpu_relax(); + int cnt = _Q_PENDING_LOOPS; + val = smp_cond_load_acquire(&lock->val.counter, + (VAL != _Q_PENDING_VAL) || !cnt--); } /* -- GitLab From 5261ad70e2d673b9cfea7c81f309cabc847b7a27 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:54 +0100 Subject: [PATCH 0574/1286] locking/qspinlock: Merge 'struct __qspinlock' into 'struct qspinlock' commit 625e88be1f41b53cec55827c984e4a89ea8ee9f9 upstream. 'struct __qspinlock' provides a handy union of fields so that subcomponents of the lockword can be accessed by name, without having to manage shifts and masks explicitly and take endianness into account. This is useful in qspinlock.h and also potentially in arch headers, so move the 'struct __qspinlock' into 'struct qspinlock' and kill the extra definition. Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Acked-by: Boqun Feng Cc: Linus Torvalds Cc: Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1524738868-31318-3-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- arch/x86/include/asm/qspinlock.h | 2 +- arch/x86/include/asm/qspinlock_paravirt.h | 3 +- include/asm-generic/qspinlock_types.h | 32 +++++++++++++++- kernel/locking/qspinlock.c | 46 ++--------------------- kernel/locking/qspinlock_paravirt.h | 34 ++++++----------- 5 files changed, 46 insertions(+), 71 deletions(-) diff --git a/arch/x86/include/asm/qspinlock.h b/arch/x86/include/asm/qspinlock.h index 9982dd96f093..cf4cdf508ef4 100644 --- a/arch/x86/include/asm/qspinlock.h +++ b/arch/x86/include/asm/qspinlock.h @@ -15,7 +15,7 @@ */ static inline void native_queued_spin_unlock(struct qspinlock *lock) { - smp_store_release((u8 *)lock, 0); + smp_store_release(&lock->locked, 0); } #ifdef CONFIG_PARAVIRT_SPINLOCKS diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/asm/qspinlock_paravirt.h index 923307ea11c7..9ef5ee03d2d7 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -22,8 +22,7 @@ PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath); * * void __pv_queued_spin_unlock(struct qspinlock *lock) * { - * struct __qspinlock *l = (void *)lock; - * u8 lockval = cmpxchg(&l->locked, _Q_LOCKED_VAL, 0); + * u8 lockval = cmpxchg(&lock->locked, _Q_LOCKED_VAL, 0); * * if (likely(lockval == _Q_LOCKED_VAL)) * return; diff --git a/include/asm-generic/qspinlock_types.h b/include/asm-generic/qspinlock_types.h index 034acd0c4956..0763f065b975 100644 --- a/include/asm-generic/qspinlock_types.h +++ b/include/asm-generic/qspinlock_types.h @@ -29,13 +29,41 @@ #endif typedef struct qspinlock { - atomic_t val; + union { + atomic_t val; + + /* + * By using the whole 2nd least significant byte for the + * pending bit, we can allow better optimization of the lock + * acquisition for the pending bit holder. + */ +#ifdef __LITTLE_ENDIAN + struct { + u8 locked; + u8 pending; + }; + struct { + u16 locked_pending; + u16 tail; + }; +#else + struct { + u16 tail; + u16 locked_pending; + }; + struct { + u8 reserved[2]; + u8 pending; + u8 locked; + }; +#endif + }; } arch_spinlock_t; /* * Initializier */ -#define __ARCH_SPIN_LOCK_UNLOCKED { ATOMIC_INIT(0) } +#define __ARCH_SPIN_LOCK_UNLOCKED { .val = ATOMIC_INIT(0) } /* * Bitfields in the atomic value: diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 18161264227a..e60e618287b4 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -126,40 +126,6 @@ static inline __pure struct mcs_spinlock *decode_tail(u32 tail) #define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK) -/* - * By using the whole 2nd least significant byte for the pending bit, we - * can allow better optimization of the lock acquisition for the pending - * bit holder. - * - * This internal structure is also used by the set_locked function which - * is not restricted to _Q_PENDING_BITS == 8. - */ -struct __qspinlock { - union { - atomic_t val; -#ifdef __LITTLE_ENDIAN - struct { - u8 locked; - u8 pending; - }; - struct { - u16 locked_pending; - u16 tail; - }; -#else - struct { - u16 tail; - u16 locked_pending; - }; - struct { - u8 reserved[2]; - u8 pending; - u8 locked; - }; -#endif - }; -}; - #if _Q_PENDING_BITS == 8 /** * clear_pending_set_locked - take ownership and clear the pending bit. @@ -171,9 +137,7 @@ struct __qspinlock { */ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - - WRITE_ONCE(l->locked_pending, _Q_LOCKED_VAL); + WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL); } /* @@ -188,13 +152,11 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) */ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) { - struct __qspinlock *l = (void *)lock; - /* * Use release semantics to make sure that the MCS node is properly * initialized before changing the tail code. */ - return (u32)xchg_release(&l->tail, + return (u32)xchg_release(&lock->tail, tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; } @@ -249,9 +211,7 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) */ static __always_inline void set_locked(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - - WRITE_ONCE(l->locked, _Q_LOCKED_VAL); + WRITE_ONCE(lock->locked, _Q_LOCKED_VAL); } diff --git a/kernel/locking/qspinlock_paravirt.h b/kernel/locking/qspinlock_paravirt.h index 15b6a39366c6..1435ba7954c3 100644 --- a/kernel/locking/qspinlock_paravirt.h +++ b/kernel/locking/qspinlock_paravirt.h @@ -70,10 +70,8 @@ struct pv_node { #define queued_spin_trylock(l) pv_queued_spin_steal_lock(l) static inline bool pv_queued_spin_steal_lock(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - if (!(atomic_read(&lock->val) & _Q_LOCKED_PENDING_MASK) && - (cmpxchg_acquire(&l->locked, 0, _Q_LOCKED_VAL) == 0)) { + (cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) { qstat_inc(qstat_pv_lock_stealing, true); return true; } @@ -88,16 +86,12 @@ static inline bool pv_queued_spin_steal_lock(struct qspinlock *lock) #if _Q_PENDING_BITS == 8 static __always_inline void set_pending(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - - WRITE_ONCE(l->pending, 1); + WRITE_ONCE(lock->pending, 1); } static __always_inline void clear_pending(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - - WRITE_ONCE(l->pending, 0); + WRITE_ONCE(lock->pending, 0); } /* @@ -107,10 +101,8 @@ static __always_inline void clear_pending(struct qspinlock *lock) */ static __always_inline int trylock_clear_pending(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; - - return !READ_ONCE(l->locked) && - (cmpxchg_acquire(&l->locked_pending, _Q_PENDING_VAL, + return !READ_ONCE(lock->locked) && + (cmpxchg_acquire(&lock->locked_pending, _Q_PENDING_VAL, _Q_LOCKED_VAL) == _Q_PENDING_VAL); } #else /* _Q_PENDING_BITS == 8 */ @@ -355,7 +347,6 @@ static void pv_wait_node(struct mcs_spinlock *node, struct mcs_spinlock *prev) static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node) { struct pv_node *pn = (struct pv_node *)node; - struct __qspinlock *l = (void *)lock; /* * If the vCPU is indeed halted, advance its state to match that of @@ -384,7 +375,7 @@ static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node) * the hash table later on at unlock time, no atomic instruction is * needed. */ - WRITE_ONCE(l->locked, _Q_SLOW_VAL); + WRITE_ONCE(lock->locked, _Q_SLOW_VAL); (void)pv_hash(lock, pn); } @@ -399,7 +390,6 @@ static u32 pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) { struct pv_node *pn = (struct pv_node *)node; - struct __qspinlock *l = (void *)lock; struct qspinlock **lp = NULL; int waitcnt = 0; int loop; @@ -450,13 +440,13 @@ pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) * * Matches the smp_rmb() in __pv_queued_spin_unlock(). */ - if (xchg(&l->locked, _Q_SLOW_VAL) == 0) { + if (xchg(&lock->locked, _Q_SLOW_VAL) == 0) { /* * The lock was free and now we own the lock. * Change the lock value back to _Q_LOCKED_VAL * and unhash the table. */ - WRITE_ONCE(l->locked, _Q_LOCKED_VAL); + WRITE_ONCE(lock->locked, _Q_LOCKED_VAL); WRITE_ONCE(*lp, NULL); goto gotlock; } @@ -464,7 +454,7 @@ pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) WRITE_ONCE(pn->state, vcpu_hashed); qstat_inc(qstat_pv_wait_head, true); qstat_inc(qstat_pv_wait_again, waitcnt); - pv_wait(&l->locked, _Q_SLOW_VAL); + pv_wait(&lock->locked, _Q_SLOW_VAL); /* * Because of lock stealing, the queue head vCPU may not be @@ -489,7 +479,6 @@ pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node) __visible void __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) { - struct __qspinlock *l = (void *)lock; struct pv_node *node; if (unlikely(locked != _Q_SLOW_VAL)) { @@ -518,7 +507,7 @@ __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) * Now that we have a reference to the (likely) blocked pv_node, * release the lock. */ - smp_store_release(&l->locked, 0); + smp_store_release(&lock->locked, 0); /* * At this point the memory pointed at by lock can be freed/reused, @@ -544,7 +533,6 @@ __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked) #ifndef __pv_queued_spin_unlock __visible void __pv_queued_spin_unlock(struct qspinlock *lock) { - struct __qspinlock *l = (void *)lock; u8 locked; /* @@ -552,7 +540,7 @@ __visible void __pv_queued_spin_unlock(struct qspinlock *lock) * unhash. Otherwise it would be possible to have multiple @lock * entries, which would be BAD. */ - locked = cmpxchg_release(&l->locked, _Q_LOCKED_VAL, 0); + locked = cmpxchg_release(&lock->locked, _Q_LOCKED_VAL, 0); if (likely(locked == _Q_LOCKED_VAL)) return; -- GitLab From 7a617996cba577806960e87882e60d7444d01df4 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:55 +0100 Subject: [PATCH 0575/1286] locking/qspinlock: Remove unbounded cmpxchg() loop from locking slowpath commit 59fb586b4a07b4e1a0ee577140ab4842ba451acd upstream. The qspinlock locking slowpath utilises a "pending" bit as a simple form of an embedded test-and-set lock that can avoid the overhead of explicit queuing in cases where the lock is held but uncontended. This bit is managed using a cmpxchg() loop which tries to transition the uncontended lock word from (0,0,0) -> (0,0,1) or (0,0,1) -> (0,1,1). Unfortunately, the cmpxchg() loop is unbounded and lockers can be starved indefinitely if the lock word is seen to oscillate between unlocked (0,0,0) and locked (0,0,1). This could happen if concurrent lockers are able to take the lock in the cmpxchg() loop without queuing and pass it around amongst themselves. This patch fixes the problem by unconditionally setting _Q_PENDING_VAL using atomic_fetch_or, and then inspecting the old value to see whether we need to spin on the current lock owner, or whether we now effectively hold the lock. The tricky scenario is when concurrent lockers end up queuing on the lock and the lock becomes available, causing us to see a lockword of (n,0,0). With pending now set, simply queuing could lead to deadlock as the head of the queue may not have observed the pending flag being cleared. Conversely, if the head of the queue did observe pending being cleared, then it could transition the lock from (n,0,0) -> (0,0,1) meaning that any attempt to "undo" our setting of the pending bit could race with a concurrent locker trying to set it. We handle this race by preserving the pending bit when taking the lock after reaching the head of the queue and leaving the tail entry intact if we saw pending set, because we know that the tail is going to be updated shortly. Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Cc: Linus Torvalds Cc: Thomas Gleixner Cc: boqun.feng@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1524738868-31318-6-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 102 ++++++++++++++++------------ kernel/locking/qspinlock_paravirt.h | 5 -- 2 files changed, 58 insertions(+), 49 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index e60e618287b4..7bd053e528c2 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -127,6 +127,17 @@ static inline __pure struct mcs_spinlock *decode_tail(u32 tail) #define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK) #if _Q_PENDING_BITS == 8 +/** + * clear_pending - clear the pending bit. + * @lock: Pointer to queued spinlock structure + * + * *,1,* -> *,0,* + */ +static __always_inline void clear_pending(struct qspinlock *lock) +{ + WRITE_ONCE(lock->pending, 0); +} + /** * clear_pending_set_locked - take ownership and clear the pending bit. * @lock: Pointer to queued spinlock structure @@ -162,6 +173,17 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) #else /* _Q_PENDING_BITS == 8 */ +/** + * clear_pending - clear the pending bit. + * @lock: Pointer to queued spinlock structure + * + * *,1,* -> *,0,* + */ +static __always_inline void clear_pending(struct qspinlock *lock) +{ + atomic_andnot(_Q_PENDING_VAL, &lock->val); +} + /** * clear_pending_set_locked - take ownership and clear the pending bit. * @lock: Pointer to queued spinlock structure @@ -266,7 +288,7 @@ static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock, void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) { struct mcs_spinlock *prev, *next, *node; - u32 new, old, tail; + u32 old, tail; int idx; BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS)); @@ -289,59 +311,51 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) (VAL != _Q_PENDING_VAL) || !cnt--); } + /* + * If we observe any contention; queue. + */ + if (val & ~_Q_LOCKED_MASK) + goto queue; + /* * trylock || pending * * 0,0,0 -> 0,0,1 ; trylock * 0,0,1 -> 0,1,1 ; pending */ - for (;;) { + val = atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); + if (!(val & ~_Q_LOCKED_MASK)) { /* - * If we observe any contention; queue. + * We're pending, wait for the owner to go away. + * + * *,1,1 -> *,1,0 + * + * this wait loop must be a load-acquire such that we match the + * store-release that clears the locked bit and create lock + * sequentiality; this is because not all + * clear_pending_set_locked() implementations imply full + * barriers. */ - if (val & ~_Q_LOCKED_MASK) - goto queue; - - new = _Q_LOCKED_VAL; - if (val == new) - new |= _Q_PENDING_VAL; + if (val & _Q_LOCKED_MASK) { + smp_cond_load_acquire(&lock->val.counter, + !(VAL & _Q_LOCKED_MASK)); + } /* - * Acquire semantic is required here as the function may - * return immediately if the lock was free. + * take ownership and clear the pending bit. + * + * *,1,0 -> *,0,1 */ - old = atomic_cmpxchg_acquire(&lock->val, val, new); - if (old == val) - break; - - val = old; - } - - /* - * we won the trylock - */ - if (new == _Q_LOCKED_VAL) + clear_pending_set_locked(lock); return; + } /* - * we're pending, wait for the owner to go away. - * - * *,1,1 -> *,1,0 - * - * this wait loop must be a load-acquire such that we match the - * store-release that clears the locked bit and create lock - * sequentiality; this is because not all clear_pending_set_locked() - * implementations imply full barriers. - */ - smp_cond_load_acquire(&lock->val.counter, !(VAL & _Q_LOCKED_MASK)); - - /* - * take ownership and clear the pending bit. - * - * *,1,0 -> *,0,1 + * If pending was clear but there are waiters in the queue, then + * we need to undo our setting of pending before we queue ourselves. */ - clear_pending_set_locked(lock); - return; + if (!(val & _Q_PENDING_MASK)) + clear_pending(lock); /* * End of pending bit optimistic spinning and beginning of MCS @@ -445,15 +459,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * claim the lock: * * n,0,0 -> 0,0,1 : lock, uncontended - * *,0,0 -> *,0,1 : lock, contended + * *,*,0 -> *,*,1 : lock, contended * - * If the queue head is the only one in the queue (lock value == tail), - * clear the tail code and grab the lock. Otherwise, we only need - * to grab the lock. + * If the queue head is the only one in the queue (lock value == tail) + * and nobody is pending, clear the tail code and grab the lock. + * Otherwise, we only need to grab the lock. */ for (;;) { /* In the PV case we might already have _Q_LOCKED_VAL set */ - if ((val & _Q_TAIL_MASK) != tail) { + if ((val & _Q_TAIL_MASK) != tail || (val & _Q_PENDING_MASK)) { set_locked(lock); break; } diff --git a/kernel/locking/qspinlock_paravirt.h b/kernel/locking/qspinlock_paravirt.h index 1435ba7954c3..854443f7b60b 100644 --- a/kernel/locking/qspinlock_paravirt.h +++ b/kernel/locking/qspinlock_paravirt.h @@ -89,11 +89,6 @@ static __always_inline void set_pending(struct qspinlock *lock) WRITE_ONCE(lock->pending, 1); } -static __always_inline void clear_pending(struct qspinlock *lock) -{ - WRITE_ONCE(lock->pending, 0); -} - /* * The pending bit check in pv_queued_spin_steal_lock() isn't a memory * barrier. Therefore, an atomic cmpxchg_acquire() is used to acquire the -- GitLab From 075703d79c3a0a603a69e09167f96c1a2502eabe Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:56 +0100 Subject: [PATCH 0576/1286] locking/qspinlock: Remove duplicate clear_pending() function from PV code commit 3bea9adc96842b8a7345c7fb202c16ae9c8d5b25 upstream. The native clear_pending() function is identical to the PV version, so the latter can simply be removed. This fixes the build for systems with >= 16K CPUs using the PV lock implementation. Reported-by: Waiman Long Signed-off-by: Will Deacon Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: boqun.feng@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/20180427101619.GB21705@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock_paravirt.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/kernel/locking/qspinlock_paravirt.h b/kernel/locking/qspinlock_paravirt.h index 854443f7b60b..1e882dfc8b79 100644 --- a/kernel/locking/qspinlock_paravirt.h +++ b/kernel/locking/qspinlock_paravirt.h @@ -106,11 +106,6 @@ static __always_inline void set_pending(struct qspinlock *lock) atomic_or(_Q_PENDING_VAL, &lock->val); } -static __always_inline void clear_pending(struct qspinlock *lock) -{ - atomic_andnot(_Q_PENDING_VAL, &lock->val); -} - static __always_inline int trylock_clear_pending(struct qspinlock *lock) { int val = atomic_read(&lock->val); -- GitLab From f2f76a2c666e9b09fa1fb903bdb20c756dc90e21 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:57 +0100 Subject: [PATCH 0577/1286] locking/qspinlock: Kill cmpxchg() loop when claiming lock from head of queue commit c61da58d8a9ba9238250a548f00826eaf44af0f7 upstream. When a queued locker reaches the head of the queue, it claims the lock by setting _Q_LOCKED_VAL in the lockword. If there isn't contention, it must also clear the tail as part of this operation so that subsequent lockers can avoid taking the slowpath altogether. Currently this is expressed as a cmpxchg() loop that practically only runs up to two iterations. This is confusing to the reader and unhelpful to the compiler. Rewrite the cmpxchg() loop without the loop, so that a failed cmpxchg() implies that there is contention and we just need to write to _Q_LOCKED_VAL without considering the rest of the lockword. Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Cc: Linus Torvalds Cc: Thomas Gleixner Cc: boqun.feng@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1524738868-31318-7-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 7bd053e528c2..841550dfb7b8 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -465,24 +465,21 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * and nobody is pending, clear the tail code and grab the lock. * Otherwise, we only need to grab the lock. */ - for (;;) { - /* In the PV case we might already have _Q_LOCKED_VAL set */ - if ((val & _Q_TAIL_MASK) != tail || (val & _Q_PENDING_MASK)) { - set_locked(lock); - break; - } + + /* In the PV case we might already have _Q_LOCKED_VAL set */ + if ((val & _Q_TAIL_MASK) == tail) { /* * The smp_cond_load_acquire() call above has provided the - * necessary acquire semantics required for locking. At most - * two iterations of this loop may be ran. + * necessary acquire semantics required for locking. */ old = atomic_cmpxchg_relaxed(&lock->val, val, _Q_LOCKED_VAL); if (old == val) - goto release; /* No contention */ - - val = old; + goto release; /* No contention */ } + /* Either somebody is queued behind us or _Q_PENDING_VAL is set */ + set_locked(lock); + /* * contended path; wait for next if not observed yet, release. */ -- GitLab From 49849a651b8456263391ae767be6f7d02af8ef26 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 18 Dec 2018 18:13:58 +0100 Subject: [PATCH 0578/1286] locking/qspinlock: Re-order code commit 53bf57fab7321fb42b703056a4c80fc9d986d170 upstream. Flip the branch condition after atomic_fetch_or_acquire(_Q_PENDING_VAL) such that we loose the indent. This also result in a more natural code flow IMO. Signed-off-by: Peter Zijlstra (Intel) Acked-by: Will Deacon Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: andrea.parri@amarulasolutions.com Cc: longman@redhat.com Link: https://lkml.kernel.org/r/20181003130257.156322446@infradead.org Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- kernel/locking/qspinlock.c | 54 ++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 841550dfb7b8..9ffc2f9af8b8 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -324,38 +324,36 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * 0,0,1 -> 0,1,1 ; pending */ val = atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); - if (!(val & ~_Q_LOCKED_MASK)) { - /* - * We're pending, wait for the owner to go away. - * - * *,1,1 -> *,1,0 - * - * this wait loop must be a load-acquire such that we match the - * store-release that clears the locked bit and create lock - * sequentiality; this is because not all - * clear_pending_set_locked() implementations imply full - * barriers. - */ - if (val & _Q_LOCKED_MASK) { - smp_cond_load_acquire(&lock->val.counter, - !(VAL & _Q_LOCKED_MASK)); - } - - /* - * take ownership and clear the pending bit. - * - * *,1,0 -> *,0,1 - */ - clear_pending_set_locked(lock); - return; + /* + * If we observe any contention; undo and queue. + */ + if (unlikely(val & ~_Q_LOCKED_MASK)) { + if (!(val & _Q_PENDING_MASK)) + clear_pending(lock); + goto queue; } /* - * If pending was clear but there are waiters in the queue, then - * we need to undo our setting of pending before we queue ourselves. + * We're pending, wait for the owner to go away. + * + * 0,1,1 -> 0,1,0 + * + * this wait loop must be a load-acquire such that we match the + * store-release that clears the locked bit and create lock + * sequentiality; this is because not all + * clear_pending_set_locked() implementations imply full + * barriers. + */ + if (val & _Q_LOCKED_MASK) + smp_cond_load_acquire(&lock->val.counter, !(VAL & _Q_LOCKED_MASK)); + + /* + * take ownership and clear the pending bit. + * + * 0,1,0 -> 0,0,1 */ - if (!(val & _Q_PENDING_MASK)) - clear_pending(lock); + clear_pending_set_locked(lock); + return; /* * End of pending bit optimistic spinning and beginning of MCS -- GitLab From 4e21502d37a503d4311e2bdb46a66aef783a7cfe Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 18 Dec 2018 18:13:59 +0100 Subject: [PATCH 0579/1286] locking/qspinlock/x86: Increase _Q_PENDING_LOOPS upper bound commit b247be3fe89b6aba928bf80f4453d1c4ba8d2063 upstream. On x86, atomic_cond_read_relaxed will busy-wait with a cpu_relax() loop, so it is desirable to increase the number of times we spin on the qspinlock lockword when it is found to be transitioning from pending to locked. According to Waiman Long: | Ideally, the spinning times should be at least a few times the typical | cacheline load time from memory which I think can be down to 100ns or | so for each cacheline load with the newest systems or up to several | hundreds ns for older systems. which in his benchmarking corresponded to 512 iterations. Suggested-by: Waiman Long Signed-off-by: Will Deacon Acked-by: Peter Zijlstra (Intel) Acked-by: Waiman Long Cc: Linus Torvalds Cc: Thomas Gleixner Cc: boqun.feng@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1524738868-31318-5-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- arch/x86/include/asm/qspinlock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/qspinlock.h b/arch/x86/include/asm/qspinlock.h index cf4cdf508ef4..2cb6624acaec 100644 --- a/arch/x86/include/asm/qspinlock.h +++ b/arch/x86/include/asm/qspinlock.h @@ -6,6 +6,8 @@ #include #include +#define _Q_PENDING_LOOPS (1 << 9) + #define queued_spin_unlock queued_spin_unlock /** * queued_spin_unlock - release a queued spinlock -- GitLab From 5d01e063296a80e93abe93803602e5cf37309865 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 18 Dec 2018 18:14:00 +0100 Subject: [PATCH 0580/1286] locking/qspinlock, x86: Provide liveness guarantee commit 7aa54be2976550f17c11a1c3e3630002dea39303 upstream. On x86 we cannot do fetch_or() with a single instruction and thus end up using a cmpxchg loop, this reduces determinism. Replace the fetch_or() with a composite operation: tas-pending + load. Using two instructions of course opens a window we previously did not have. Consider the scenario: CPU0 CPU1 CPU2 1) lock trylock -> (0,0,1) 2) lock trylock /* fail */ 3) unlock -> (0,0,0) 4) lock trylock -> (0,0,1) 5) tas-pending -> (0,1,1) load-val <- (0,1,0) from 3 6) clear-pending-set-locked -> (0,0,1) FAIL: _2_ owners where 5) is our new composite operation. When we consider each part of the qspinlock state as a separate variable (as we can when _Q_PENDING_BITS == 8) then the above is entirely possible, because tas-pending will only RmW the pending byte, so the later load is able to observe prior tail and lock state (but not earlier than its own trylock, which operates on the whole word, due to coherence). To avoid this we need 2 things: - the load must come after the tas-pending (obviously, otherwise it can trivially observe prior state). - the tas-pending must be a full word RmW instruction, it cannot be an XCHGB for example, such that we cannot observe other state prior to setting pending. On x86 we can realize this by using "LOCK BTS m32, r32" for tas-pending followed by a regular load. Note that observing later state is not a problem: - if we fail to observe a later unlock, we'll simply spin-wait for that store to become visible. - if we observe a later xchg_tail(), there is no difference from that xchg_tail() having taken place before the tas-pending. Suggested-by: Will Deacon Reported-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Will Deacon Cc: Linus Torvalds Cc: Peter Zijlstra Cc: andrea.parri@amarulasolutions.com Cc: longman@redhat.com Fixes: 59fb586b4a07 ("locking/qspinlock: Remove unbounded cmpxchg() loop from locking slowpath") Link: https://lkml.kernel.org/r/20181003130957.183726335@infradead.org Signed-off-by: Ingo Molnar [bigeasy: GEN_BINARY_RMWcc macro redo] Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Sasha Levin --- arch/x86/include/asm/qspinlock.h | 21 +++++++++++++++++++++ kernel/locking/qspinlock.c | 17 ++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/qspinlock.h b/arch/x86/include/asm/qspinlock.h index 2cb6624acaec..f784b95e44df 100644 --- a/arch/x86/include/asm/qspinlock.h +++ b/arch/x86/include/asm/qspinlock.h @@ -5,9 +5,30 @@ #include #include #include +#include #define _Q_PENDING_LOOPS (1 << 9) +#define queued_fetch_set_pending_acquire queued_fetch_set_pending_acquire + +static __always_inline bool __queued_RMW_btsl(struct qspinlock *lock) +{ + GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter, + "I", _Q_PENDING_OFFSET, "%0", c); +} + +static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock) +{ + u32 val = 0; + + if (__queued_RMW_btsl(lock)) + val |= _Q_PENDING_VAL; + + val |= atomic_read(&lock->val) & ~_Q_PENDING_MASK; + + return val; +} + #define queued_spin_unlock queued_spin_unlock /** * queued_spin_unlock - release a queued spinlock diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index 9ffc2f9af8b8..1011a1b292ac 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -225,6 +225,20 @@ static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) } #endif /* _Q_PENDING_BITS == 8 */ +/** + * queued_fetch_set_pending_acquire - fetch the whole lock value and set pending + * @lock : Pointer to queued spinlock structure + * Return: The previous lock value + * + * *,*,* -> *,1,* + */ +#ifndef queued_fetch_set_pending_acquire +static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock) +{ + return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); +} +#endif + /** * set_locked - Set the lock bit and own the lock * @lock: Pointer to queued spinlock structure @@ -323,7 +337,8 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * 0,0,0 -> 0,0,1 ; trylock * 0,0,1 -> 0,1,1 ; pending */ - val = atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val); + val = queued_fetch_set_pending_acquire(lock); + /* * If we observe any contention; undo and queue. */ -- GitLab From 2a35d21a4d12fe774c46d17831e2938781179c83 Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Wed, 25 Oct 2017 12:33:42 -0600 Subject: [PATCH 0581/1286] elevator: lookup mq vs non-mq elevators [ Upstream commit 2527d99789e248576ac8081530cd4fd88730f8c7 ] If an IO scheduler is selected via elevator= and it doesn't match the driver in question wrt blk-mq support, then we fail to boot. The elevator= parameter is deprecated and only supported for non-mq devices. Augment the elevator lookup API so that we pass in if we're looking for an mq capable scheduler or not, so that we only ever return a valid type for the queue in question. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=196695 Reviewed-by: Omar Sandoval Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- block/elevator.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/block/elevator.c b/block/elevator.c index 153926a90901..8320d97240be 100644 --- a/block/elevator.c +++ b/block/elevator.c @@ -83,12 +83,15 @@ bool elv_bio_merge_ok(struct request *rq, struct bio *bio) } EXPORT_SYMBOL(elv_bio_merge_ok); -static struct elevator_type *elevator_find(const char *name) +/* + * Return scheduler with name 'name' and with matching 'mq capability + */ +static struct elevator_type *elevator_find(const char *name, bool mq) { struct elevator_type *e; list_for_each_entry(e, &elv_list, list) { - if (!strcmp(e->elevator_name, name)) + if (!strcmp(e->elevator_name, name) && (mq == e->uses_mq)) return e; } @@ -100,25 +103,25 @@ static void elevator_put(struct elevator_type *e) module_put(e->elevator_owner); } -static struct elevator_type *elevator_get(const char *name, bool try_loading) +static struct elevator_type *elevator_get(struct request_queue *q, + const char *name, bool try_loading) { struct elevator_type *e; spin_lock(&elv_list_lock); - e = elevator_find(name); + e = elevator_find(name, q->mq_ops != NULL); if (!e && try_loading) { spin_unlock(&elv_list_lock); request_module("%s-iosched", name); spin_lock(&elv_list_lock); - e = elevator_find(name); + e = elevator_find(name, q->mq_ops != NULL); } if (e && !try_module_get(e->elevator_owner)) e = NULL; spin_unlock(&elv_list_lock); - return e; } @@ -144,8 +147,12 @@ void __init load_default_elevator_module(void) if (!chosen_elevator[0]) return; + /* + * Boot parameter is deprecated, we haven't supported that for MQ. + * Only look for non-mq schedulers from here. + */ spin_lock(&elv_list_lock); - e = elevator_find(chosen_elevator); + e = elevator_find(chosen_elevator, false); spin_unlock(&elv_list_lock); if (!e) @@ -202,7 +209,7 @@ int elevator_init(struct request_queue *q, char *name) q->boundary_rq = NULL; if (name) { - e = elevator_get(name, true); + e = elevator_get(q, name, true); if (!e) return -EINVAL; } @@ -214,7 +221,7 @@ int elevator_init(struct request_queue *q, char *name) * allowed from async. */ if (!e && !q->mq_ops && *chosen_elevator) { - e = elevator_get(chosen_elevator, false); + e = elevator_get(q, chosen_elevator, false); if (!e) printk(KERN_ERR "I/O scheduler %s not found\n", chosen_elevator); @@ -229,17 +236,17 @@ int elevator_init(struct request_queue *q, char *name) */ if (q->mq_ops) { if (q->nr_hw_queues == 1) - e = elevator_get("mq-deadline", false); + e = elevator_get(q, "mq-deadline", false); if (!e) return 0; } else - e = elevator_get(CONFIG_DEFAULT_IOSCHED, false); + e = elevator_get(q, CONFIG_DEFAULT_IOSCHED, false); if (!e) { printk(KERN_ERR "Default I/O scheduler not found. " \ "Using noop.\n"); - e = elevator_get("noop", false); + e = elevator_get(q, "noop", false); } } @@ -905,7 +912,7 @@ int elv_register(struct elevator_type *e) /* register, don't allow duplicate names */ spin_lock(&elv_list_lock); - if (elevator_find(e->elevator_name)) { + if (elevator_find(e->elevator_name, e->uses_mq)) { spin_unlock(&elv_list_lock); if (e->icq_cache) kmem_cache_destroy(e->icq_cache); @@ -1066,7 +1073,7 @@ static int __elevator_change(struct request_queue *q, const char *name) return elevator_switch(q, NULL); strlcpy(elevator_name, name, sizeof(elevator_name)); - e = elevator_get(strstrip(elevator_name), true); + e = elevator_get(q, strstrip(elevator_name), true); if (!e) return -EINVAL; @@ -1076,15 +1083,6 @@ static int __elevator_change(struct request_queue *q, const char *name) return 0; } - if (!e->uses_mq && q->mq_ops) { - elevator_put(e); - return -EINVAL; - } - if (e->uses_mq && !q->mq_ops) { - elevator_put(e); - return -EINVAL; - } - return elevator_switch(q, e); } -- GitLab From 5515c5bd3f560e89222cce52ea2f71c71687a2e8 Mon Sep 17 00:00:00 2001 From: Jozsef Kadlecsik Date: Fri, 12 Jan 2018 11:16:50 +0100 Subject: [PATCH 0582/1286] netfilter: ipset: Fix wraparound in hash:*net* types [ Upstream commit 0b8d9073539e217f79ec1bff65eb205ac796723d ] Fix wraparound bug which could lead to memory exhaustion when adding an x.x.x.x-255.255.255.255 range to any hash:*net* types. Fixes Netfilter's bugzilla id #1212, reported by Thomas Schwark. Fixes: 48596a8ddc46 ("netfilter: ipset: Fix adding an IPv4 range containing more than 2^31 addresses") Signed-off-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/ipset/ip_set_hash_ipportnet.c | 26 +++++++-------- net/netfilter/ipset/ip_set_hash_net.c | 9 +++-- net/netfilter/ipset/ip_set_hash_netiface.c | 9 +++-- net/netfilter/ipset/ip_set_hash_netnet.c | 28 ++++++++-------- net/netfilter/ipset/ip_set_hash_netport.c | 19 ++++++----- net/netfilter/ipset/ip_set_hash_netportnet.c | 35 ++++++++++---------- 6 files changed, 63 insertions(+), 63 deletions(-) diff --git a/net/netfilter/ipset/ip_set_hash_ipportnet.c b/net/netfilter/ipset/ip_set_hash_ipportnet.c index a2f19b9906e9..543518384aa7 100644 --- a/net/netfilter/ipset/ip_set_hash_ipportnet.c +++ b/net/netfilter/ipset/ip_set_hash_ipportnet.c @@ -168,7 +168,7 @@ hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[], struct hash_ipportnet4_elem e = { .cidr = HOST_MASK - 1 }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); u32 ip = 0, ip_to = 0, p = 0, port, port_to; - u32 ip2_from = 0, ip2_to = 0, ip2_last, ip2; + u32 ip2_from = 0, ip2_to = 0, ip2; bool with_ports = false; u8 cidr; int ret; @@ -269,22 +269,21 @@ hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[], ip_set_mask_from_to(ip2_from, ip2_to, e.cidr + 1); } - if (retried) + if (retried) { ip = ntohl(h->next.ip); + p = ntohs(h->next.port); + ip2 = ntohl(h->next.ip2); + } else { + p = port; + ip2 = ip2_from; + } for (; ip <= ip_to; ip++) { e.ip = htonl(ip); - p = retried && ip == ntohl(h->next.ip) ? ntohs(h->next.port) - : port; for (; p <= port_to; p++) { e.port = htons(p); - ip2 = retried && - ip == ntohl(h->next.ip) && - p == ntohs(h->next.port) - ? ntohl(h->next.ip2) : ip2_from; - while (ip2 <= ip2_to) { + do { e.ip2 = htonl(ip2); - ip2_last = ip_set_range_to_cidr(ip2, ip2_to, - &cidr); + ip2 = ip_set_range_to_cidr(ip2, ip2_to, &cidr); e.cidr = cidr - 1; ret = adtfn(set, &e, &ext, &ext, flags); @@ -292,9 +291,10 @@ hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[], return ret; ret = 0; - ip2 = ip2_last + 1; - } + } while (ip2++ < ip2_to); + ip2 = ip2_from; } + p = port; } return ret; } diff --git a/net/netfilter/ipset/ip_set_hash_net.c b/net/netfilter/ipset/ip_set_hash_net.c index 1c67a1761e45..5449e23af13a 100644 --- a/net/netfilter/ipset/ip_set_hash_net.c +++ b/net/netfilter/ipset/ip_set_hash_net.c @@ -143,7 +143,7 @@ hash_net4_uadt(struct ip_set *set, struct nlattr *tb[], ipset_adtfn adtfn = set->variant->adt[adt]; struct hash_net4_elem e = { .cidr = HOST_MASK }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); - u32 ip = 0, ip_to = 0, last; + u32 ip = 0, ip_to = 0; int ret; if (tb[IPSET_ATTR_LINENO]) @@ -193,16 +193,15 @@ hash_net4_uadt(struct ip_set *set, struct nlattr *tb[], } if (retried) ip = ntohl(h->next.ip); - while (ip <= ip_to) { + do { e.ip = htonl(ip); - last = ip_set_range_to_cidr(ip, ip_to, &e.cidr); + ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr); ret = adtfn(set, &e, &ext, &ext, flags); if (ret && !ip_set_eexist(ret, flags)) return ret; ret = 0; - ip = last + 1; - } + } while (ip++ < ip_to); return ret; } diff --git a/net/netfilter/ipset/ip_set_hash_netiface.c b/net/netfilter/ipset/ip_set_hash_netiface.c index d417074f1c1a..f5164c1efce2 100644 --- a/net/netfilter/ipset/ip_set_hash_netiface.c +++ b/net/netfilter/ipset/ip_set_hash_netiface.c @@ -200,7 +200,7 @@ hash_netiface4_uadt(struct ip_set *set, struct nlattr *tb[], ipset_adtfn adtfn = set->variant->adt[adt]; struct hash_netiface4_elem e = { .cidr = HOST_MASK, .elem = 1 }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); - u32 ip = 0, ip_to = 0, last; + u32 ip = 0, ip_to = 0; int ret; if (tb[IPSET_ATTR_LINENO]) @@ -255,17 +255,16 @@ hash_netiface4_uadt(struct ip_set *set, struct nlattr *tb[], if (retried) ip = ntohl(h->next.ip); - while (ip <= ip_to) { + do { e.ip = htonl(ip); - last = ip_set_range_to_cidr(ip, ip_to, &e.cidr); + ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr); ret = adtfn(set, &e, &ext, &ext, flags); if (ret && !ip_set_eexist(ret, flags)) return ret; ret = 0; - ip = last + 1; - } + } while (ip++ < ip_to); return ret; } diff --git a/net/netfilter/ipset/ip_set_hash_netnet.c b/net/netfilter/ipset/ip_set_hash_netnet.c index 7f9ae2e9645b..5a2b923bd81f 100644 --- a/net/netfilter/ipset/ip_set_hash_netnet.c +++ b/net/netfilter/ipset/ip_set_hash_netnet.c @@ -169,8 +169,8 @@ hash_netnet4_uadt(struct ip_set *set, struct nlattr *tb[], ipset_adtfn adtfn = set->variant->adt[adt]; struct hash_netnet4_elem e = { }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); - u32 ip = 0, ip_to = 0, last; - u32 ip2 = 0, ip2_from = 0, ip2_to = 0, last2; + u32 ip = 0, ip_to = 0; + u32 ip2 = 0, ip2_from = 0, ip2_to = 0; int ret; if (tb[IPSET_ATTR_LINENO]) @@ -247,27 +247,27 @@ hash_netnet4_uadt(struct ip_set *set, struct nlattr *tb[], ip_set_mask_from_to(ip2_from, ip2_to, e.cidr[1]); } - if (retried) + if (retried) { ip = ntohl(h->next.ip[0]); + ip2 = ntohl(h->next.ip[1]); + } else { + ip2 = ip2_from; + } - while (ip <= ip_to) { + do { e.ip[0] = htonl(ip); - last = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]); - ip2 = (retried && - ip == ntohl(h->next.ip[0])) ? ntohl(h->next.ip[1]) - : ip2_from; - while (ip2 <= ip2_to) { + ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]); + do { e.ip[1] = htonl(ip2); - last2 = ip_set_range_to_cidr(ip2, ip2_to, &e.cidr[1]); + ip2 = ip_set_range_to_cidr(ip2, ip2_to, &e.cidr[1]); ret = adtfn(set, &e, &ext, &ext, flags); if (ret && !ip_set_eexist(ret, flags)) return ret; ret = 0; - ip2 = last2 + 1; - } - ip = last + 1; - } + } while (ip2++ < ip2_to); + ip2 = ip2_from; + } while (ip++ < ip_to); return ret; } diff --git a/net/netfilter/ipset/ip_set_hash_netport.c b/net/netfilter/ipset/ip_set_hash_netport.c index e6ef382febe4..1a187be9ebc8 100644 --- a/net/netfilter/ipset/ip_set_hash_netport.c +++ b/net/netfilter/ipset/ip_set_hash_netport.c @@ -161,7 +161,7 @@ hash_netport4_uadt(struct ip_set *set, struct nlattr *tb[], ipset_adtfn adtfn = set->variant->adt[adt]; struct hash_netport4_elem e = { .cidr = HOST_MASK - 1 }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); - u32 port, port_to, p = 0, ip = 0, ip_to = 0, last; + u32 port, port_to, p = 0, ip = 0, ip_to = 0; bool with_ports = false; u8 cidr; int ret; @@ -239,25 +239,26 @@ hash_netport4_uadt(struct ip_set *set, struct nlattr *tb[], ip_set_mask_from_to(ip, ip_to, e.cidr + 1); } - if (retried) + if (retried) { ip = ntohl(h->next.ip); - while (ip <= ip_to) { + p = ntohs(h->next.port); + } else { + p = port; + } + do { e.ip = htonl(ip); - last = ip_set_range_to_cidr(ip, ip_to, &cidr); + ip = ip_set_range_to_cidr(ip, ip_to, &cidr); e.cidr = cidr - 1; - p = retried && ip == ntohl(h->next.ip) ? ntohs(h->next.port) - : port; for (; p <= port_to; p++) { e.port = htons(p); ret = adtfn(set, &e, &ext, &ext, flags); - if (ret && !ip_set_eexist(ret, flags)) return ret; ret = 0; } - ip = last + 1; - } + p = port; + } while (ip++ < ip_to); return ret; } diff --git a/net/netfilter/ipset/ip_set_hash_netportnet.c b/net/netfilter/ipset/ip_set_hash_netportnet.c index 0e6e40c6f652..613e18e720a4 100644 --- a/net/netfilter/ipset/ip_set_hash_netportnet.c +++ b/net/netfilter/ipset/ip_set_hash_netportnet.c @@ -184,8 +184,8 @@ hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[], ipset_adtfn adtfn = set->variant->adt[adt]; struct hash_netportnet4_elem e = { }; struct ip_set_ext ext = IP_SET_INIT_UEXT(set); - u32 ip = 0, ip_to = 0, ip_last, p = 0, port, port_to; - u32 ip2_from = 0, ip2_to = 0, ip2_last, ip2; + u32 ip = 0, ip_to = 0, p = 0, port, port_to; + u32 ip2_from = 0, ip2_to = 0, ip2; bool with_ports = false; int ret; @@ -288,33 +288,34 @@ hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[], ip_set_mask_from_to(ip2_from, ip2_to, e.cidr[1]); } - if (retried) + if (retried) { ip = ntohl(h->next.ip[0]); + p = ntohs(h->next.port); + ip2 = ntohl(h->next.ip[1]); + } else { + p = port; + ip2 = ip2_from; + } - while (ip <= ip_to) { + do { e.ip[0] = htonl(ip); - ip_last = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]); - p = retried && ip == ntohl(h->next.ip[0]) ? ntohs(h->next.port) - : port; + ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]); for (; p <= port_to; p++) { e.port = htons(p); - ip2 = (retried && ip == ntohl(h->next.ip[0]) && - p == ntohs(h->next.port)) ? ntohl(h->next.ip[1]) - : ip2_from; - while (ip2 <= ip2_to) { + do { e.ip[1] = htonl(ip2); - ip2_last = ip_set_range_to_cidr(ip2, ip2_to, - &e.cidr[1]); + ip2 = ip_set_range_to_cidr(ip2, ip2_to, + &e.cidr[1]); ret = adtfn(set, &e, &ext, &ext, flags); if (ret && !ip_set_eexist(ret, flags)) return ret; ret = 0; - ip2 = ip2_last + 1; - } + } while (ip2++ < ip2_to); + ip2 = ip2_from; } - ip = ip_last + 1; - } + p = port; + } while (ip++ < ip_to); return ret; } -- GitLab From 603bd4dc73594c8ac39a578d9fae997ea04e3a17 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Mon, 26 Mar 2018 16:21:04 +0300 Subject: [PATCH 0583/1286] mac80211: don't WARN on bad WMM parameters from buggy APs [ Upstream commit c470bdc1aaf36669e04ba65faf1092b2d1c6cabe ] Apparently, some APs are buggy enough to send a zeroed WMM IE. Don't WARN on this since this is not caused by a bug on the client's system. This aligns the condition of the WARNING in drv_conf_tx with the validity check in ieee80211_sta_wmm_params. We will now pick the default values whenever we get a zeroed WMM IE. This has been reported here: https://bugzilla.kernel.org/show_bug.cgi?id=199161 Fixes: f409079bb678 ("mac80211: sanity check CW_min/CW_max towards driver") Signed-off-by: Emmanuel Grumbach Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/mlme.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 328ac10084e4..75909a744121 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -1861,7 +1861,8 @@ static bool ieee80211_sta_wmm_params(struct ieee80211_local *local, params[ac].acm = acm; params[ac].uapsd = uapsd; - if (params[ac].cw_min > params[ac].cw_max) { + if (params->cw_min == 0 || + params[ac].cw_min > params[ac].cw_max) { sdata_info(sdata, "AP has invalid WMM params (CWmin/max=%d/%d for ACI %d), using defaults\n", params[ac].cw_min, params[ac].cw_max, aci); -- GitLab From 8f8a5a9be2b422af6a7ea12a8fe2bdefdab754c5 Mon Sep 17 00:00:00 2001 From: Ilan Peer Date: Tue, 3 Apr 2018 11:35:22 +0300 Subject: [PATCH 0584/1286] mac80211: Fix condition validating WMM IE [ Upstream commit 911a26484c33e10de6237228ca1d7293548e9f49 ] Commit c470bdc1aaf3 ("mac80211: don't WARN on bad WMM parameters from buggy APs") handled cases where an AP reports a zeroed WMM IE. However, the condition that checks the validity accessed the wrong index in the ieee80211_tx_queue_params array, thus wrongly deducing that the parameters are invalid. Fix it. Fixes: c470bdc1aaf3 ("mac80211: don't WARN on bad WMM parameters from buggy APs") Signed-off-by: Ilan Peer Signed-off-by: Luca Coelho Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/mlme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 75909a744121..4c59b5507e7a 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -1861,7 +1861,7 @@ static bool ieee80211_sta_wmm_params(struct ieee80211_local *local, params[ac].acm = acm; params[ac].uapsd = uapsd; - if (params->cw_min == 0 || + if (params[ac].cw_min == 0 || params[ac].cw_min > params[ac].cw_max) { sdata_info(sdata, "AP has invalid WMM params (CWmin/max=%d/%d for ACI %d), using defaults\n", -- GitLab From 12f75e8ad273df5b4e0bdab97d55cc23be1a0d7f Mon Sep 17 00:00:00 2001 From: "Michael J. Ruhl" Date: Tue, 18 Dec 2018 16:04:18 -0500 Subject: [PATCH 0585/1286] IB/hfi1: Remove race conditions in user_sdma send path commit 28a9a9e83ceae2cee25b9af9ad20d53aaa9ab951 upstream Packet queue state is over used to determine SDMA descriptor availablitity and packet queue request state. cpu 0 ret = user_sdma_send_pkts(req, pcount); cpu 0 if (atomic_read(&pq->n_reqs)) cpu 1 IRQ user_sdma_txreq_cb calls pq_update() (state to _INACTIVE) cpu 0 xchg(&pq->state, SDMA_PKT_Q_ACTIVE); At this point pq->n_reqs == 0 and pq->state is incorrectly SDMA_PKT_Q_ACTIVE. The close path will hang waiting for the state to return to _INACTIVE. This can also change the state from _DEFERRED to _ACTIVE. However, this is a mostly benign race. Remove the racy code path. Use n_reqs to determine if a packet queue is active or not. Cc: # 4.14.0> Reviewed-by: Mitko Haralanov Reviewed-by: Mike Marciniszyn Signed-off-by: Michael J. Ruhl Signed-off-by: Sasha Levin --- drivers/infiniband/hw/hfi1/user_sdma.c | 24 ++++++++++-------------- drivers/infiniband/hw/hfi1/user_sdma.h | 9 +++++---- 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c index c14ec04f2a89..cbe5ab26d95b 100644 --- a/drivers/infiniband/hw/hfi1/user_sdma.c +++ b/drivers/infiniband/hw/hfi1/user_sdma.c @@ -187,7 +187,6 @@ int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt, pq->ctxt = uctxt->ctxt; pq->subctxt = fd->subctxt; pq->n_max_reqs = hfi1_sdma_comp_ring_size; - pq->state = SDMA_PKT_Q_INACTIVE; atomic_set(&pq->n_reqs, 0); init_waitqueue_head(&pq->wait); atomic_set(&pq->n_locked, 0); @@ -276,7 +275,7 @@ int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd, /* Wait until all requests have been freed. */ wait_event_interruptible( pq->wait, - (ACCESS_ONCE(pq->state) == SDMA_PKT_Q_INACTIVE)); + !atomic_read(&pq->n_reqs)); kfree(pq->reqs); kfree(pq->req_in_use); kmem_cache_destroy(pq->txreq_cache); @@ -312,6 +311,13 @@ static u8 dlid_to_selector(u16 dlid) return mapping[hash]; } +/** + * hfi1_user_sdma_process_request() - Process and start a user sdma request + * @fd: valid file descriptor + * @iovec: array of io vectors to process + * @dim: overall iovec array size + * @count: number of io vector array entries processed + */ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, struct iovec *iovec, unsigned long dim, unsigned long *count) @@ -560,20 +566,12 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd, req->ahg_idx = sdma_ahg_alloc(req->sde); set_comp_state(pq, cq, info.comp_idx, QUEUED, 0); + pq->state = SDMA_PKT_Q_ACTIVE; /* Send the first N packets in the request to buy us some time */ ret = user_sdma_send_pkts(req, pcount); if (unlikely(ret < 0 && ret != -EBUSY)) goto free_req; - /* - * It is possible that the SDMA engine would have processed all the - * submitted packets by the time we get here. Therefore, only set - * packet queue state to ACTIVE if there are still uncompleted - * requests. - */ - if (atomic_read(&pq->n_reqs)) - xchg(&pq->state, SDMA_PKT_Q_ACTIVE); - /* * This is a somewhat blocking send implementation. * The driver will block the caller until all packets of the @@ -1391,10 +1389,8 @@ static void user_sdma_txreq_cb(struct sdma_txreq *txreq, int status) static inline void pq_update(struct hfi1_user_sdma_pkt_q *pq) { - if (atomic_dec_and_test(&pq->n_reqs)) { - xchg(&pq->state, SDMA_PKT_Q_INACTIVE); + if (atomic_dec_and_test(&pq->n_reqs)) wake_up(&pq->wait); - } } static void user_sdma_free_request(struct user_sdma_request *req, bool unpin) diff --git a/drivers/infiniband/hw/hfi1/user_sdma.h b/drivers/infiniband/hw/hfi1/user_sdma.h index 5af52334b7dc..2b5326d6db53 100644 --- a/drivers/infiniband/hw/hfi1/user_sdma.h +++ b/drivers/infiniband/hw/hfi1/user_sdma.h @@ -94,9 +94,10 @@ #define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */ #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */ -#define SDMA_PKT_Q_INACTIVE BIT(0) -#define SDMA_PKT_Q_ACTIVE BIT(1) -#define SDMA_PKT_Q_DEFERRED BIT(2) +enum pkt_q_sdma_state { + SDMA_PKT_Q_ACTIVE, + SDMA_PKT_Q_DEFERRED, +}; /* * Maximum retry attempts to submit a TX request @@ -124,7 +125,7 @@ struct hfi1_user_sdma_pkt_q { struct user_sdma_request *reqs; unsigned long *req_in_use; struct iowait busy; - unsigned state; + enum pkt_q_sdma_state state; wait_queue_head_t wait; unsigned long unpinned; struct mmu_rb_handler *handler; -- GitLab From 1f972505011c27d09423a46707789192a039b66a Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Thu, 21 Jun 2018 20:35:26 -0400 Subject: [PATCH 0586/1286] locking/qspinlock: Fix build for anonymous union in older GCC compilers [ Upstream commit 6cc65be4f6f2a7186af8f3e09900787c7912dad2 ] One of my tests compiles the kernel with gcc 4.5.3, and I hit the following build error: include/linux/semaphore.h: In function 'sema_init': include/linux/semaphore.h:35:17: error: unknown field 'val' specified in initializer include/linux/semaphore.h:35:17: warning: missing braces around initializer include/linux/semaphore.h:35:17: warning: (near initialization for '(anonymous).raw_lock..val') I bisected it down to: 625e88be1f41 ("locking/qspinlock: Merge 'struct __qspinlock' into 'struct qspinlock'") ... which makes qspinlock have an anonymous union, which makes initializing it special for older compilers. By adding strategic brackets, it makes the build happy again. Signed-off-by: Steven Rostedt (VMware) Acked-by: Waiman Long Cc: Andrew Morton Cc: Boqun Feng Cc: Linus Torvalds Cc: Peter Zijlstra (Intel) Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Fixes: 625e88be1f41 ("locking/qspinlock: Merge 'struct __qspinlock' into 'struct qspinlock'") Link: http://lkml.kernel.org/r/20180621203526.172ab5c4@vmware.local.home Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- include/asm-generic/qspinlock_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-generic/qspinlock_types.h b/include/asm-generic/qspinlock_types.h index 0763f065b975..d10f1e7d6ba8 100644 --- a/include/asm-generic/qspinlock_types.h +++ b/include/asm-generic/qspinlock_types.h @@ -63,7 +63,7 @@ typedef struct qspinlock { /* * Initializier */ -#define __ARCH_SPIN_LOCK_UNLOCKED { .val = ATOMIC_INIT(0) } +#define __ARCH_SPIN_LOCK_UNLOCKED { { .val = ATOMIC_INIT(0) } } /* * Bitfields in the atomic value: -- GitLab From 0d2d1629780025966c3fc793c201e387da18f5be Mon Sep 17 00:00:00 2001 From: Alexey Khoroshilov Date: Fri, 5 Oct 2018 23:22:06 +0300 Subject: [PATCH 0587/1286] mac80211_hwsim: fix module init error paths for netlink [ Upstream commit 05cc09de4c017663a217630682041066f2f9a5cd ] There is no unregister netlink notifier and family on error paths in init_mac80211_hwsim(). Also there is an error path where hwsim_class is not destroyed. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov Fixes: 62759361eb49 ("mac80211-hwsim: Provide multicast event for HWSIM_CMD_NEW_RADIO") Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- drivers/net/wireless/mac80211_hwsim.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 670224be3c8b..8f57ca969c9f 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -3472,16 +3472,16 @@ static int __init init_mac80211_hwsim(void) if (err) goto out_unregister_pernet; + err = hwsim_init_netlink(); + if (err) + goto out_unregister_driver; + hwsim_class = class_create(THIS_MODULE, "mac80211_hwsim"); if (IS_ERR(hwsim_class)) { err = PTR_ERR(hwsim_class); - goto out_unregister_driver; + goto out_exit_netlink; } - err = hwsim_init_netlink(); - if (err < 0) - goto out_unregister_driver; - for (i = 0; i < radios; i++) { struct hwsim_new_radio_params param = { 0 }; @@ -3587,6 +3587,8 @@ static int __init init_mac80211_hwsim(void) free_netdev(hwsim_mon); out_free_radios: mac80211_hwsim_free(); +out_exit_netlink: + hwsim_exit_netlink(); out_unregister_driver: platform_driver_unregister(&mac80211_hwsim_driver); out_unregister_pernet: -- GitLab From ce28c745aafcd5ae6a5a85731c8585e1cf0e3e2e Mon Sep 17 00:00:00 2001 From: Vitaly Kuznetsov Date: Thu, 15 Nov 2018 11:05:10 -0800 Subject: [PATCH 0588/1286] Input: hyper-v - fix wakeup from suspend-to-idle [ Upstream commit 10f91c73cc41ceead210a905dbd196398e99c7d2 ] It makes little sense but still possible to put Hyper-V guests into suspend-to-idle state. To wake them up two wakeup sources were registered in the past: hyperv-keyboard and hid-hyperv. However, since commit eed4d47efe95 ("ACPI / sleep: Ignore spurious SCI wakeups from suspend-to-idle") pm_wakeup_event() from these devices is ignored. Switch to pm_wakeup_hard_event() API as these devices are actually the only possible way to wakeup Hyper-V guests. Fixes: eed4d47efe95 (ACPI / sleep: Ignore spurious SCI wakeups from suspend-to-idle) Reviewed-by: Rafael J. Wysocki Acked-by: K. Y. Srinivasan Acked-by: Jiri Kosina Signed-off-by: Vitaly Kuznetsov Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/hid/hid-hyperv.c | 2 +- drivers/input/serio/hyperv-keyboard.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c index 6039f071fab1..5f1de24206ab 100644 --- a/drivers/hid/hid-hyperv.c +++ b/drivers/hid/hid-hyperv.c @@ -309,7 +309,7 @@ static void mousevsc_on_receive(struct hv_device *device, hid_input_report(input_dev->hid_device, HID_INPUT_REPORT, input_dev->input_buf, len, 1); - pm_wakeup_event(&input_dev->device->device, 0); + pm_wakeup_hard_event(&input_dev->device->device); break; default: diff --git a/drivers/input/serio/hyperv-keyboard.c b/drivers/input/serio/hyperv-keyboard.c index 25151d9214e0..55288a026e4e 100644 --- a/drivers/input/serio/hyperv-keyboard.c +++ b/drivers/input/serio/hyperv-keyboard.c @@ -177,7 +177,7 @@ static void hv_kbd_on_receive(struct hv_device *hv_dev, * state because the Enter-UP can trigger a wakeup at once. */ if (!(info & IS_BREAK)) - pm_wakeup_event(&hv_dev->device, 0); + pm_wakeup_hard_event(&hv_dev->device); break; -- GitLab From 1e30cdb191150be718bb01d0eb21c790ac24a1c3 Mon Sep 17 00:00:00 2001 From: Fred Herard Date: Tue, 20 Nov 2018 20:22:45 -0500 Subject: [PATCH 0589/1286] scsi: libiscsi: Fix NULL pointer dereference in iscsi_eh_session_reset [ Upstream commit 5db6dd14b31397e8cccaaddab2ff44ebec1acf25 ] This commit addresses NULL pointer dereference in iscsi_eh_session_reset. Reference should not be made to session->leadconn when session->state is set to ISCSI_STATE_TERMINATE. Signed-off-by: Fred Herard Reviewed-by: Konrad Rzeszutek Wilk Reviewed-by: Lee Duncan Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/libiscsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index cf8a15e54d83..3ff536b350a1 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -2416,8 +2416,8 @@ int iscsi_eh_session_reset(struct scsi_cmnd *sc) failed: ISCSI_DBG_EH(session, "failing session reset: Could not log back into " - "%s, %s [age %d]\n", session->targetname, - conn->persistent_address, session->age); + "%s [age %d]\n", session->targetname, + session->age); spin_unlock_bh(&session->frwd_lock); mutex_unlock(&session->eh_mutex); return FAILED; -- GitLab From 3a2c2aae1bca2e176bcc93f02ce4cc8fe8bda326 Mon Sep 17 00:00:00 2001 From: Cathy Avery Date: Tue, 27 Nov 2018 14:28:53 -0500 Subject: [PATCH 0590/1286] scsi: vmw_pscsi: Rearrange code to avoid multiple calls to free_irq during unload [ Upstream commit 02f425f811cefcc4d325d7a72272651e622dc97e ] Currently pvscsi_remove calls free_irq more than once as pvscsi_release_resources and __pvscsi_shutdown both call pvscsi_shutdown_intr. This results in a 'Trying to free already-free IRQ' warning and stack trace. To solve the problem pvscsi_shutdown_intr has been moved out of pvscsi_release_resources. Signed-off-by: Cathy Avery Reviewed-by: Ewan D. Milne Reviewed-by: Dan Carpenter Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/vmw_pvscsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/vmw_pvscsi.c b/drivers/scsi/vmw_pvscsi.c index 0cd947f78b5b..890b8aaf95e1 100644 --- a/drivers/scsi/vmw_pvscsi.c +++ b/drivers/scsi/vmw_pvscsi.c @@ -1202,8 +1202,6 @@ static void pvscsi_shutdown_intr(struct pvscsi_adapter *adapter) static void pvscsi_release_resources(struct pvscsi_adapter *adapter) { - pvscsi_shutdown_intr(adapter); - if (adapter->workqueue) destroy_workqueue(adapter->workqueue); @@ -1535,6 +1533,7 @@ static int pvscsi_probe(struct pci_dev *pdev, const struct pci_device_id *id) out_reset_adapter: ll_adapter_reset(adapter); out_release_resources: + pvscsi_shutdown_intr(adapter); pvscsi_release_resources(adapter); scsi_host_put(host); out_disable_device: @@ -1543,6 +1542,7 @@ static int pvscsi_probe(struct pci_dev *pdev, const struct pci_device_id *id) return error; out_release_resources_and_disable: + pvscsi_shutdown_intr(adapter); pvscsi_release_resources(adapter); goto out_disable_device; } -- GitLab From 81710cedad2fa7ea3221cdf77bcb1d39683f07ac Mon Sep 17 00:00:00 2001 From: YiFei Zhu Date: Thu, 29 Nov 2018 18:12:30 +0100 Subject: [PATCH 0591/1286] x86/earlyprintk/efi: Fix infinite loop on some screen widths [ Upstream commit 79c2206d369b87b19ac29cb47601059b6bf5c291 ] An affected screen resolution is 1366 x 768, which width is not divisible by 8, the default font width. On such screens, when longer lines are earlyprintk'ed, overflow-to-next-line can never trigger, due to the left-most x-coordinate of the next character always less than the screen width. Earlyprintk will infinite loop in trying to print the rest of the string but unable to, due to the line being full. This patch makes the trigger consider the right-most x-coordinate, instead of left-most, as the value to compare against the screen width threshold. Signed-off-by: YiFei Zhu Signed-off-by: Ard Biesheuvel Cc: Andy Lutomirski Cc: Arend van Spriel Cc: Bhupesh Sharma Cc: Borislav Petkov Cc: Dave Hansen Cc: Eric Snowberg Cc: Hans de Goede Cc: Joe Perches Cc: Jon Hunter Cc: Julien Thierry Cc: Linus Torvalds Cc: Marc Zyngier Cc: Matt Fleming Cc: Nathan Chancellor Cc: Peter Zijlstra Cc: Sai Praneeth Prakhya Cc: Sedat Dilek Cc: Thomas Gleixner Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20181129171230.18699-12-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- arch/x86/platform/efi/early_printk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/platform/efi/early_printk.c b/arch/x86/platform/efi/early_printk.c index 5fdacb322ceb..c3e6be110b7d 100644 --- a/arch/x86/platform/efi/early_printk.c +++ b/arch/x86/platform/efi/early_printk.c @@ -179,7 +179,7 @@ early_efi_write(struct console *con, const char *str, unsigned int num) num--; } - if (efi_x >= si->lfb_width) { + if (efi_x + font->width > si->lfb_width) { efi_x = 0; efi_y += font->height; } -- GitLab From 5094dea5acab748453e75fcb53db6fe9ce629ab7 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Wed, 3 Oct 2018 16:22:31 -0400 Subject: [PATCH 0592/1286] drm/msm: Grab a vblank reference when waiting for commit_done [ Upstream commit 3b712e43e3876b42b38321ecf790a1f5fe59c834 ] Similar to the atomic helpers, we should enable vblank while we're waiting for the commit to finish. DPU needs this, MDP5 seems to work fine without it. Reviewed-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/msm_atomic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 025d454163b0..8f77047a226d 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -93,7 +93,12 @@ static void msm_atomic_wait_for_commit_done(struct drm_device *dev, if (!new_crtc_state->active) continue; + if (drm_crtc_vblank_get(crtc)) + continue; + kms->funcs->wait_for_crtc_commit_done(kms, crtc); + + drm_crtc_vblank_put(crtc); } } -- GitLab From 32f91e02d0e93535b914bb8ed7111e5004dfdecd Mon Sep 17 00:00:00 2001 From: Jose Abreu Date: Fri, 30 Nov 2018 09:47:31 +0000 Subject: [PATCH 0593/1286] ARC: io.h: Implement reads{x}()/writes{x}() [ Upstream commit 10d443431dc2bb733cf7add99b453e3fb9047a2e ] Some ARC CPU's do not support unaligned loads/stores. Currently, generic implementation of reads{b/w/l}()/writes{b/w/l}() is being used with ARC. This can lead to misfunction of some drivers as generic functions do a plain dereference of a pointer that can be unaligned. Let's use {get/put}_unaligned() helpers instead of plain dereference of pointer in order to fix. The helpers allow to get and store data from an unaligned address whilst preserving the CPU internal alignment. According to [1], the use of these helpers are costly in terms of performance so we added an initial check for a buffer already aligned so that the usage of the helpers can be avoided, when possible. [1] Documentation/unaligned-memory-access.txt Cc: Alexey Brodkin Cc: Joao Pinto Cc: David Laight Tested-by: Vitor Soares Signed-off-by: Jose Abreu Signed-off-by: Vineet Gupta Signed-off-by: Sasha Levin --- arch/arc/include/asm/io.h | 72 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index c22b181e8206..2f39d9b3886e 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_ISA_ARCV2 #include @@ -94,6 +95,42 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return w; } +/* + * {read,write}s{b,w,l}() repeatedly access the same IO address in + * native endianness in 8-, 16-, 32-bit chunks {into,from} memory, + * @count times + */ +#define __raw_readsx(t,f) \ +static inline void __raw_reads##f(const volatile void __iomem *addr, \ + void *ptr, unsigned int count) \ +{ \ + bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ + u##t *buf = ptr; \ + \ + if (!count) \ + return; \ + \ + /* Some ARC CPU's don't support unaligned accesses */ \ + if (is_aligned) { \ + do { \ + u##t x = __raw_read##f(addr); \ + *buf++ = x; \ + } while (--count); \ + } else { \ + do { \ + u##t x = __raw_read##f(addr); \ + put_unaligned(x, buf++); \ + } while (--count); \ + } \ +} + +#define __raw_readsb __raw_readsb +__raw_readsx(8, b) +#define __raw_readsw __raw_readsw +__raw_readsx(16, w) +#define __raw_readsl __raw_readsl +__raw_readsx(32, l) + #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem *addr) { @@ -126,6 +163,35 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) } +#define __raw_writesx(t,f) \ +static inline void __raw_writes##f(volatile void __iomem *addr, \ + const void *ptr, unsigned int count) \ +{ \ + bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0; \ + const u##t *buf = ptr; \ + \ + if (!count) \ + return; \ + \ + /* Some ARC CPU's don't support unaligned accesses */ \ + if (is_aligned) { \ + do { \ + __raw_write##f(*buf++, addr); \ + } while (--count); \ + } else { \ + do { \ + __raw_write##f(get_unaligned(buf++), addr); \ + } while (--count); \ + } \ +} + +#define __raw_writesb __raw_writesb +__raw_writesx(8, b) +#define __raw_writesw __raw_writesw +__raw_writesx(16, w) +#define __raw_writesl __raw_writesl +__raw_writesx(32, l) + /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed * Based on ARM model for the typical use case @@ -141,10 +207,16 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readsb(p,d,l) ({ __raw_readsb(p,d,l); __iormb(); }) +#define readsw(p,d,l) ({ __raw_readsw(p,d,l); __iormb(); }) +#define readsl(p,d,l) ({ __raw_readsl(p,d,l); __iormb(); }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) +#define writesb(p,d,l) ({ __iowmb(); __raw_writesb(p,d,l); }) +#define writesw(p,d,l) ({ __iowmb(); __raw_writesw(p,d,l); }) +#define writesl(p,d,l) ({ __iowmb(); __raw_writesl(p,d,l); }) /* * Relaxed API for drivers which can handle barrier ordering themselves -- GitLab From 87c1a07b0e7f7127aa4be68864ef9cf6112e0535 Mon Sep 17 00:00:00 2001 From: Toni Peltonen Date: Tue, 27 Nov 2018 16:56:57 +0200 Subject: [PATCH 0594/1286] bonding: fix 802.3ad state sent to partner when unbinding slave [ Upstream commit 3b5b3a3331d141e8f2a7aaae3a94dfa1e61ecbe4 ] Previously when unbinding a slave the 802.3ad implementation only told partner that the port is not suitable for aggregation by setting the port aggregation state from aggregatable to individual. This is not enough. If the physical layer still stays up and we only unbinded this port from the bond there is nothing in the aggregation status alone to prevent the partner from sending traffic towards us. To ensure that the partner doesn't consider this port at all anymore we should also disable collecting and distributing to signal that this actor is going away. Also clear AD_STATE_SYNCHRONIZATION to ensure partner exits collecting + distributing state. I have tested this behaviour againts Arista EOS switches with mlx5 cards (physical link stays up even when interface is down) and simulated the same situation virtually Linux <-> Linux with two network namespaces running two veth device pairs. In both cases setting aggregation to individual doesn't alone prevent traffic from being to sent towards this port given that the link stays up in partners end. Partner still keeps it's end in collecting + distributing state and continues until timeout is reached. In most cases this means we are losing the traffic partner sends towards our port while we wait for timeout. This is most visible with slow periodic time (LACP rate slow). Other open source implementations like Open VSwitch and libreswitch, and vendor implementations like Arista EOS, seem to disable collecting + distributing to when doing similar port disabling/detaching/removing change. With this patch kernel implementation would behave the same way and ensure partner doesn't consider our actor viable anymore. Signed-off-by: Toni Peltonen Signed-off-by: Jay Vosburgh Acked-by: Jonathan Toppins Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/bonding/bond_3ad.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index f43fb2f958a5..93dfcef8afc4 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c @@ -2086,6 +2086,9 @@ void bond_3ad_unbind_slave(struct slave *slave) aggregator->aggregator_identifier); /* Tell the partner that this port is not suitable for aggregation */ + port->actor_oper_port_state &= ~AD_STATE_SYNCHRONIZATION; + port->actor_oper_port_state &= ~AD_STATE_COLLECTING; + port->actor_oper_port_state &= ~AD_STATE_DISTRIBUTING; port->actor_oper_port_state &= ~AD_STATE_AGGREGATION; __update_lacpdu_from_port(port); ad_lacpdu_send(port); -- GitLab From 27be23532ed8cdc4dbe872b9b3b16887d3252e17 Mon Sep 17 00:00:00 2001 From: David Miller Date: Wed, 28 Nov 2018 22:33:53 -0800 Subject: [PATCH 0595/1286] bpf: Fix verifier log string check for bad alignment. [ Upstream commit c01ac66b38660f2b507ccd0b75d28e3002d56fbb ] The message got changed a lot time ago. This was responsible for 36 test case failures on sparc64. Fixes: f1174f77b50c ("bpf/verifier: rework value tracking") Signed-off-by: David S. Miller Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- tools/testing/selftests/bpf/test_verifier.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c index 041dbbb30ff0..a0591d06c61b 100644 --- a/tools/testing/selftests/bpf/test_verifier.c +++ b/tools/testing/selftests/bpf/test_verifier.c @@ -8070,7 +8070,7 @@ static void do_test_single(struct bpf_test *test, bool unpriv, reject_from_alignment = fd_prog < 0 && (test->flags & F_NEEDS_EFFICIENT_UNALIGNED_ACCESS) && - strstr(bpf_vlog, "Unknown alignment."); + strstr(bpf_vlog, "misaligned"); #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS if (reject_from_alignment) { printf("FAIL\nFailed due to alignment despite having efficient unaligned access: '%s'!\n", -- GitLab From 76413fbfc7c1193b9b5b2a0fde8a90003adb32d3 Mon Sep 17 00:00:00 2001 From: Dave Kleikamp Date: Tue, 27 Nov 2018 19:31:30 +0000 Subject: [PATCH 0596/1286] nfs: don't dirty kernel pages read by direct-io [ Upstream commit ad3cba223ac02dc769c3bbe88efe277bbb457566 ] When we use direct_IO with an NFS backing store, we can trigger a WARNING in __set_page_dirty(), as below, since we're dirtying the page unnecessarily in nfs_direct_read_completion(). To fix, replicate the logic in commit 53cbf3b157a0 ("fs: direct-io: don't dirtying pages for ITER_BVEC/ITER_KVEC direct read"). Other filesystems that implement direct_IO handle this; most use blockdev_direct_IO(). ceph and cifs have similar logic. mount 127.0.0.1:/export /nfs dd if=/dev/zero of=/nfs/image bs=1M count=200 losetup --direct-io=on -f /nfs/image mkfs.btrfs /dev/loop0 mount -t btrfs /dev/loop0 /mnt/ kernel: WARNING: CPU: 0 PID: 8067 at fs/buffer.c:580 __set_page_dirty+0xaf/0xd0 kernel: Modules linked in: loop(E) nfsv3(E) rpcsec_gss_krb5(E) nfsv4(E) dns_resolver(E) nfs(E) fscache(E) nfsd(E) auth_rpcgss(E) nfs_acl(E) lockd(E) grace(E) fuse(E) tun(E) ip6t_rpfilter(E) ipt_REJECT(E) nf_ kernel: snd_seq(E) snd_seq_device(E) snd_pcm(E) video(E) snd_timer(E) snd(E) soundcore(E) ip_tables(E) xfs(E) libcrc32c(E) sd_mod(E) sr_mod(E) cdrom(E) ata_generic(E) pata_acpi(E) crc32c_intel(E) ahci(E) li kernel: CPU: 0 PID: 8067 Comm: kworker/0:2 Tainted: G E 4.20.0-rc1.master.20181111.ol7.x86_64 #1 kernel: Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS VirtualBox 12/01/2006 kernel: Workqueue: nfsiod rpc_async_release [sunrpc] kernel: RIP: 0010:__set_page_dirty+0xaf/0xd0 kernel: Code: c3 48 8b 02 f6 c4 04 74 d4 48 89 df e8 ba 05 f7 ff 48 89 c6 eb cb 48 8b 43 08 a8 01 75 1f 48 89 d8 48 8b 00 a8 04 74 02 eb 87 <0f> 0b eb 83 48 83 e8 01 eb 9f 48 83 ea 01 0f 1f 00 eb 8b 48 83 e8 kernel: RSP: 0000:ffffc1c8825b7d78 EFLAGS: 00013046 kernel: RAX: 000fffffc0020089 RBX: fffff2b603308b80 RCX: 0000000000000001 kernel: RDX: 0000000000000001 RSI: ffff9d11478115c8 RDI: ffff9d11478115d0 kernel: RBP: ffffc1c8825b7da0 R08: 0000646f6973666e R09: 8080808080808080 kernel: R10: 0000000000000001 R11: 0000000000000000 R12: ffff9d11478115d0 kernel: R13: ffff9d11478115c8 R14: 0000000000003246 R15: 0000000000000001 kernel: FS: 0000000000000000(0000) GS:ffff9d115ba00000(0000) knlGS:0000000000000000 kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 kernel: CR2: 00007f408686f640 CR3: 0000000104d8e004 CR4: 00000000000606f0 kernel: DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 kernel: DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 kernel: Call Trace: kernel: __set_page_dirty_buffers+0xb6/0x110 kernel: set_page_dirty+0x52/0xb0 kernel: nfs_direct_read_completion+0xc4/0x120 [nfs] kernel: nfs_pgio_release+0x10/0x20 [nfs] kernel: rpc_free_task+0x30/0x70 [sunrpc] kernel: rpc_async_release+0x12/0x20 [sunrpc] kernel: process_one_work+0x174/0x390 kernel: worker_thread+0x4f/0x3e0 kernel: kthread+0x102/0x140 kernel: ? drain_workqueue+0x130/0x130 kernel: ? kthread_stop+0x110/0x110 kernel: ret_from_fork+0x35/0x40 kernel: ---[ end trace 01341980905412c9 ]--- Signed-off-by: Dave Kleikamp Signed-off-by: Santosh Shilimkar [forward-ported to v4.20] Signed-off-by: Calum Mackay Reviewed-by: Dave Kleikamp Reviewed-by: Chuck Lever Signed-off-by: Trond Myklebust Signed-off-by: Sasha Levin --- fs/nfs/direct.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fs/nfs/direct.c b/fs/nfs/direct.c index 621c517b325c..89c03a507dd9 100644 --- a/fs/nfs/direct.c +++ b/fs/nfs/direct.c @@ -98,8 +98,11 @@ struct nfs_direct_req { struct pnfs_ds_commit_info ds_cinfo; /* Storage for cinfo */ struct work_struct work; int flags; + /* for write */ #define NFS_ODIRECT_DO_COMMIT (1) /* an unstable reply was received */ #define NFS_ODIRECT_RESCHED_WRITES (2) /* write verification failed */ + /* for read */ +#define NFS_ODIRECT_SHOULD_DIRTY (3) /* dirty user-space page after read */ struct nfs_writeverf verf; /* unstable write verifier */ }; @@ -412,7 +415,8 @@ static void nfs_direct_read_completion(struct nfs_pgio_header *hdr) struct nfs_page *req = nfs_list_entry(hdr->pages.next); struct page *page = req->wb_page; - if (!PageCompound(page) && bytes < hdr->good_bytes) + if (!PageCompound(page) && bytes < hdr->good_bytes && + (dreq->flags == NFS_ODIRECT_SHOULD_DIRTY)) set_page_dirty(page); bytes += req->wb_bytes; nfs_list_remove_request(req); @@ -587,6 +591,9 @@ ssize_t nfs_file_direct_read(struct kiocb *iocb, struct iov_iter *iter) if (!is_sync_kiocb(iocb)) dreq->iocb = iocb; + if (iter_is_iovec(iter)) + dreq->flags = NFS_ODIRECT_SHOULD_DIRTY; + nfs_start_io_direct(inode); NFS_I(inode)->read_io += count; -- GitLab From c3f68415c9871e4828255ffb52b01ed4fe28dca1 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Sat, 1 Dec 2018 23:18:00 -0500 Subject: [PATCH 0597/1286] SUNRPC: Fix a potential race in xprt_connect() [ Upstream commit 0a9a4304f3614e25d9de9b63502ca633c01c0d70 ] If an asynchronous connection attempt completes while another task is in xprt_connect(), then the call to rpc_sleep_on() could end up racing with the call to xprt_wake_pending_tasks(). So add a second test of the connection state after we've put the task to sleep and set the XPRT_CONNECTING flag, when we know that there can be no asynchronous connection attempts still in progress. Fixes: 0b9e79431377d ("SUNRPC: Move the test for XPRT_CONNECTING into...") Signed-off-by: Trond Myklebust Signed-off-by: Sasha Levin --- net/sunrpc/xprt.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c index 8eb0c4f3b3e9..d0282cc88b14 100644 --- a/net/sunrpc/xprt.c +++ b/net/sunrpc/xprt.c @@ -780,8 +780,15 @@ void xprt_connect(struct rpc_task *task) return; if (xprt_test_and_set_connecting(xprt)) return; - xprt->stat.connect_start = jiffies; - xprt->ops->connect(xprt, task); + /* Race breaker */ + if (!xprt_connected(xprt)) { + xprt->stat.connect_start = jiffies; + xprt->ops->connect(xprt, task); + } else { + xprt_clear_connecting(xprt); + task->tk_status = 0; + rpc_wake_up_queued_task(&xprt->pending, task); + } } xprt_release_write(xprt, task); } -- GitLab From 923e09c74a9ca2761d3fa5f2c31b497360138244 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 20 Nov 2018 08:30:40 -0500 Subject: [PATCH 0598/1286] sbus: char: add of_node_put() [ Upstream commit 87d81a23e24f24ebe014891e8bdf3ff8785031e8 ] use of_node_put() to release the refcount. Signed-off-by: Yangtao Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/sbus/char/display7seg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/sbus/char/display7seg.c b/drivers/sbus/char/display7seg.c index f32765d3cbd8..db761aca8667 100644 --- a/drivers/sbus/char/display7seg.c +++ b/drivers/sbus/char/display7seg.c @@ -221,6 +221,7 @@ static int d7s_probe(struct platform_device *op) dev_set_drvdata(&op->dev, p); d7s_device = p; err = 0; + of_node_put(opts); out: return err; -- GitLab From 6b37106bc20ab5265b113a67563d4fb0b5191153 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 20 Nov 2018 08:38:26 -0500 Subject: [PATCH 0599/1286] drivers/sbus/char: add of_node_put() [ Upstream commit 6bd520ab7cf69486ea81fd3cdfd2d5a390ad1100 ] use of_node_put() to release the refcount. Signed-off-by: Yangtao Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/sbus/char/envctrl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/sbus/char/envctrl.c b/drivers/sbus/char/envctrl.c index 56e962a01493..b8481927bfe4 100644 --- a/drivers/sbus/char/envctrl.c +++ b/drivers/sbus/char/envctrl.c @@ -910,8 +910,10 @@ static void envctrl_init_i2c_child(struct device_node *dp, for (len = 0; len < PCF8584_MAX_CHANNELS; ++len) { pchild->mon_type[len] = ENVCTRL_NOMON; } + of_node_put(root_node); return; } + of_node_put(root_node); } /* Get the monitor channels. */ -- GitLab From a19e57563ce7416727c7b318162972d780334020 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Wed, 21 Nov 2018 10:22:54 -0500 Subject: [PATCH 0600/1286] drivers/tty: add missing of_node_put() [ Upstream commit dac097c4546e4c5b16dd303a1e97c1d319c8ab3e ] of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. This place is not doing this, so fix it. Signed-off-by: Yangtao Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/tty/serial/suncore.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/suncore.c b/drivers/tty/serial/suncore.c index 127472bd6a7c..209f314745ab 100644 --- a/drivers/tty/serial/suncore.c +++ b/drivers/tty/serial/suncore.c @@ -111,6 +111,7 @@ void sunserial_console_termios(struct console *con, struct device_node *uart_dp) mode = of_get_property(dp, mode_prop, NULL); if (!mode) mode = "9600,8,n,1,-"; + of_node_put(dp); } cflag = CREAD | HUPCL | CLOCAL; -- GitLab From 8b9860ad1efa031be8b37bbd60cdb699d0fdb64c Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Tue, 20 Nov 2018 08:02:49 -0500 Subject: [PATCH 0601/1286] ide: pmac: add of_node_put() [ Upstream commit a51921c0db3fd26c4ed83dc0ec5d32988fa02aa5 ] use of_node_put() to release the refcount. Signed-off-by: Yangtao Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/ide/pmac.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index c5b902b86b44..203ed4adc04a 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -920,6 +920,7 @@ static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) struct device_node *root = of_find_node_by_path("/"); const char *model = of_get_property(root, "model", NULL); + of_node_put(root); /* Get cable type from device-tree. */ if (cable && !strncmp(cable, "80-", 3)) { /* Some drives fail to detect 80c cable in PowerBook */ -- GitLab From 308d65a18461c90b2e4e14dac55478376382a5d3 Mon Sep 17 00:00:00 2001 From: Wen Yang Date: Thu, 29 Nov 2018 14:01:50 +0800 Subject: [PATCH 0602/1286] drm/msm: Fix error return checking [ Upstream commit 098336deb946f37a70afc0979af388b615c378bf ] The error checks on ret for a negative error return always fails because the return value of iommu_map_sg() is unsigned and can never be negative. Detected with Coccinelle: drivers/gpu/drm/msm/msm_iommu.c:69:9-12: WARNING: Unsigned expression compared with zero: ret < 0 Signed-off-by: Wen Yang CC: Rob Clark CC: David Airlie CC: Julia Lawall CC: linux-arm-msm@vger.kernel.org CC: dri-devel@lists.freedesktop.org CC: freedreno@lists.freedesktop.org CC: linux-kernel@vger.kernel.org Signed-off-by: Sean Paul Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/msm_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index b23d33622f37..2a90aa4caec0 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -66,7 +66,7 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, // pm_runtime_get_sync(mmu->dev); ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot); // pm_runtime_put_sync(mmu->dev); - WARN_ON(ret < 0); + WARN_ON(!ret); return (ret == len) ? 0 : -EINVAL; } -- GitLab From d5f2432339ba2827d75f682887eac604afb06535 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 3 Dec 2018 17:50:55 +0300 Subject: [PATCH 0603/1286] clk: mvebu: Off by one bugs in cp110_of_clk_get() [ Upstream commit d9f5b7f5dd0fa74a89de5a7ac1e26366f211ccee ] These > comparisons should be >= to prevent reading beyond the end of of the clk_data->hws[] buffer. The clk_data->hws[] array is allocated in cp110_syscon_common_probe() when we do: cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) + sizeof(struct clk_hw *) * CP110_CLK_NUM, GFP_KERNEL); As you can see, it has CP110_CLK_NUM elements which is equivalent to CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system controller") Signed-off-by: Dan Carpenter Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/mvebu/cp110-system-controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c index ca9a0a536174..05c127cafa46 100644 --- a/drivers/clk/mvebu/cp110-system-controller.c +++ b/drivers/clk/mvebu/cp110-system-controller.c @@ -203,11 +203,11 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec, unsigned int idx = clkspec->args[1]; if (type == CP110_CLK_TYPE_CORE) { - if (idx > CP110_MAX_CORE_CLOCKS) + if (idx >= CP110_MAX_CORE_CLOCKS) return ERR_PTR(-EINVAL); return clk_data->hws[idx]; } else if (type == CP110_CLK_TYPE_GATABLE) { - if (idx > CP110_MAX_GATABLE_CLOCKS) + if (idx >= CP110_MAX_GATABLE_CLOCKS) return ERR_PTR(-EINVAL); return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx]; } -- GitLab From 2f74717d0237cde6fa63a70be9de7b275e2e8cd0 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 3 Dec 2018 17:51:43 +0300 Subject: [PATCH 0604/1286] clk: mmp: Off by one in mmp_clk_add() [ Upstream commit 2e85c57493e391b93445c1e0d530b36b95becc64 ] The > comparison should be >= or we write one element beyond the end of the unit->clk_table[] array. (The unit->clk_table[] array is allocated in the mmp_clk_init() function and it has unit->nr_clks elements). Fixes: 4661fda10f8b ("clk: mmp: add basic support functions for DT support") Signed-off-by: Dan Carpenter Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/mmp/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c index ad8d483a35cd..ca7d37e2c7be 100644 --- a/drivers/clk/mmp/clk.c +++ b/drivers/clk/mmp/clk.c @@ -183,7 +183,7 @@ void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, pr_err("CLK %d has invalid pointer %p\n", id, clk); return; } - if (id > unit->nr_clks) { + if (id >= unit->nr_clks) { pr_err("CLK %d is invalid\n", id); return; } -- GitLab From 2dc84c590cea6b1852e866132edb0079d477dbf6 Mon Sep 17 00:00:00 2001 From: Teika Kazura Date: Mon, 3 Dec 2018 11:26:03 -0800 Subject: [PATCH 0605/1286] Input: synaptics - enable SMBus for HP 15-ay000 [ Upstream commit 5a6dab15f7a79817cab4af612ddd99eda793fce6 ] SMBus works fine for the touchpad with id SYN3221, used in the HP 15-ay000 series, This device has been reported in these messages in the "linux-input" mailing list: * https://marc.info/?l=linux-input&m=152016683003369&w=2 * https://www.spinics.net/lists/linux-input/msg52525.html Reported-by: Nitesh Debnath Reported-by: Teika Kazura Signed-off-by: Teika Kazura Reviewed-by: Benjamin Tissoires Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/mouse/synaptics.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index 65c9095eb517..54f0d037b5b6 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -178,6 +178,7 @@ static const char * const smbus_pnp_ids[] = { "LEN0096", /* X280 */ "LEN0097", /* X280 -> ALPS trackpoint */ "LEN200f", /* T450s */ + "SYN3221", /* HP 15-ay000 */ NULL }; -- GitLab From 647492ad7341cc76a9ebafeb67cea1664f674cca Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 3 Dec 2018 11:24:30 -0800 Subject: [PATCH 0606/1286] Input: omap-keypad - fix keyboard debounce configuration [ Upstream commit 6c3516fed7b61a3527459ccfa67fab130d910610 ] I noticed that the Android v3.0.8 kernel on droid4 is using different keypad values from the mainline kernel and does not have issues with keys occasionally being stuck until pressed again. Turns out there was an earlier patch posted to fix this as "Input: omap-keypad: errata i689: Correct debounce time", but it was never reposted to fix use macros for timing calculations. This updated version is using macros, and also fixes the use of the input clock rate to use 32768KiHz instead of 32000KiHz. And we want to use the known good Android kernel values of 3 and 6 instead of 2 and 6 in the earlier patch. Reported-by: Pavel Machek Signed-off-by: Tony Lindgren Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/keyboard/omap4-keypad.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c index 940d38b08e6b..ce8e2baf31bb 100644 --- a/drivers/input/keyboard/omap4-keypad.c +++ b/drivers/input/keyboard/omap4-keypad.c @@ -60,8 +60,18 @@ /* OMAP4 values */ #define OMAP4_VAL_IRQDISABLE 0x0 -#define OMAP4_VAL_DEBOUNCINGTIME 0x7 -#define OMAP4_VAL_PVT 0x7 + +/* + * Errata i689: If a key is released for a time shorter than debounce time, + * the keyboard will idle and never detect the key release. The workaround + * is to use at least a 12ms debounce time. See omap5432 TRM chapter + * "26.4.6.2 Keyboard Controller Timer" for more information. + */ +#define OMAP4_KEYPAD_PTV_DIV_128 0x6 +#define OMAP4_KEYPAD_DEBOUNCINGTIME_MS(dbms, ptv) \ + ((((dbms) * 1000) / ((1 << ((ptv) + 1)) * (1000000 / 32768))) - 1) +#define OMAP4_VAL_DEBOUNCINGTIME_16MS \ + OMAP4_KEYPAD_DEBOUNCINGTIME_MS(16, OMAP4_KEYPAD_PTV_DIV_128) enum { KBD_REVISION_OMAP4 = 0, @@ -181,9 +191,9 @@ static int omap4_keypad_open(struct input_dev *input) kbd_writel(keypad_data, OMAP4_KBD_CTRL, OMAP4_DEF_CTRL_NOSOFTMODE | - (OMAP4_VAL_PVT << OMAP4_DEF_CTRL_PTV_SHIFT)); + (OMAP4_KEYPAD_PTV_DIV_128 << OMAP4_DEF_CTRL_PTV_SHIFT)); kbd_writel(keypad_data, OMAP4_KBD_DEBOUNCINGTIME, - OMAP4_VAL_DEBOUNCINGTIME); + OMAP4_VAL_DEBOUNCINGTIME_16MS); /* clear pending interrupts */ kbd_write_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS, kbd_read_irqreg(keypad_data, OMAP4_KBD_IRQSTATUS)); -- GitLab From 4b427e57f4f6eb3ad1c02d3faa3d551336f2fd59 Mon Sep 17 00:00:00 2001 From: Juha-Matti Tilli Date: Sun, 2 Dec 2018 12:47:08 +0200 Subject: [PATCH 0607/1286] libata: whitelist all SAMSUNG MZ7KM* solid-state disks [ Upstream commit fd6f32f78645db32b6b95a42e45da2ddd6de0e67 ] These devices support read zero after trim (RZAT), as they advertise to the OS. However, the OS doesn't believe the SSDs unless they are explicitly whitelisted. Acked-by: Martin K. Petersen Signed-off-by: Juha-Matti Tilli Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/ata/libata-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 6938bd86ff1c..04f406d7e973 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -4593,6 +4593,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { { "SSD*INTEL*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, { "Samsung*SSD*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, { "SAMSUNG*SSD*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "SAMSUNG*MZ7KM*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, { "ST[1248][0248]0[FH]*", NULL, ATA_HORKAGE_ZERO_AFTER_TRIM, }, /* -- GitLab From 1a130bc711d3931567575c0449cdd255859c1e58 Mon Sep 17 00:00:00 2001 From: Anderson Luiz Alves Date: Fri, 30 Nov 2018 21:58:36 -0200 Subject: [PATCH 0608/1286] mv88e6060: disable hardware level MAC learning [ Upstream commit a74515604a7b171f2702bdcbd1e231225fb456d0 ] Disable hardware level MAC learning because it breaks station roaming. When enabled it drops all frames that arrive from a MAC address that is on a different port at learning table. Signed-off-by: Anderson Luiz Alves Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6060.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c index f123ed57630d..86b41840f41a 100644 --- a/drivers/net/dsa/mv88e6060.c +++ b/drivers/net/dsa/mv88e6060.c @@ -114,8 +114,7 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds) /* Reset the switch. */ REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, GLOBAL_ATU_CONTROL_SWRESET | - GLOBAL_ATU_CONTROL_ATUSIZE_1024 | - GLOBAL_ATU_CONTROL_ATE_AGE_5MIN); + GLOBAL_ATU_CONTROL_LEARNDIS); /* Wait up to one second for reset to complete. */ timeout = jiffies + 1 * HZ; @@ -140,13 +139,10 @@ static int mv88e6060_setup_global(struct dsa_switch *ds) */ REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536); - /* Enable automatic address learning, set the address - * database size to 1024 entries, and set the default aging - * time to 5 minutes. + /* Disable automatic address learning. */ REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, - GLOBAL_ATU_CONTROL_ATUSIZE_1024 | - GLOBAL_ATU_CONTROL_ATE_AGE_5MIN); + GLOBAL_ATU_CONTROL_LEARNDIS); return 0; } -- GitLab From e7c36edac701bad12b54f182de7b63b137307e62 Mon Sep 17 00:00:00 2001 From: Saeed Mahameed Date: Sun, 2 Dec 2018 14:34:37 +0200 Subject: [PATCH 0609/1286] net/mlx4_en: Fix build break when CONFIG_INET is off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 1b603f9e4313348608f256b564ed6e3d9e67f377 ] MLX4_EN depends on NETDEVICES, ETHERNET and INET Kconfigs. Make sure they are listed in MLX4_EN Kconfig dependencies. This fixes the following build break: drivers/net/ethernet/mellanox/mlx4/en_rx.c:582:18: warning: ‘struct iphdr’ declared inside parameter list [enabled by default] struct iphdr *iph) ^ drivers/net/ethernet/mellanox/mlx4/en_rx.c:582:18: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] drivers/net/ethernet/mellanox/mlx4/en_rx.c: In function ‘get_fixed_ipv4_csum’: drivers/net/ethernet/mellanox/mlx4/en_rx.c:586:20: error: dereferencing pointer to incomplete type _u8 ipproto = iph->protocol; Signed-off-by: Saeed Mahameed Signed-off-by: Tariq Toukan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx4/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx4/Kconfig b/drivers/net/ethernet/mellanox/mlx4/Kconfig index 22b1cc012bc9..c1a39be0dbe7 100644 --- a/drivers/net/ethernet/mellanox/mlx4/Kconfig +++ b/drivers/net/ethernet/mellanox/mlx4/Kconfig @@ -5,7 +5,7 @@ config MLX4_EN tristate "Mellanox Technologies 1/10/40Gbit Ethernet support" depends on MAY_USE_DEVLINK - depends on PCI + depends on PCI && NETDEVICES && ETHERNET && INET select MLX4_CORE imply PTP_1588_CLOCK ---help--- -- GitLab From 394f9a113b4c42672c24ce03697712643dc87dee Mon Sep 17 00:00:00 2001 From: Chris Cole Date: Fri, 23 Nov 2018 12:20:45 +0100 Subject: [PATCH 0610/1286] ARM: 8814/1: mm: improve/fix ARM v7_dma_inv_range() unaligned address handling [ Upstream commit a1208f6a822ac29933e772ef1f637c5d67838da9 ] This patch addresses possible memory corruption when v7_dma_inv_range(start_address, end_address) address parameters are not aligned to whole cache lines. This function issues "invalidate" cache management operations to all cache lines from start_address (inclusive) to end_address (exclusive). When start_address and/or end_address are not aligned, the start and/or end cache lines are first issued "clean & invalidate" operation. The assumption is this is done to ensure that any dirty data addresses outside the address range (but part of the first or last cache lines) are cleaned/flushed so that data is not lost, which could happen if just an invalidate is issued. The problem is that these first/last partial cache lines are issued "clean & invalidate" and then "invalidate". This second "invalidate" is not required and worse can cause "lost" writes to addresses outside the address range but part of the cache line. If another component writes to its part of the cache line between the "clean & invalidate" and "invalidate" operations, the write can get lost. This fix is to remove the extra "invalidate" operation when unaligned addressed are used. A kernel module is available that has a stress test to reproduce the issue and a unit test of the updated v7_dma_inv_range(). It can be downloaded from http://ftp.sageembedded.com/outgoing/linux/cache-test-20181107.tgz. v7_dma_inv_range() is call by dmac_[un]map_area(addr, len, direction) when the direction is DMA_FROM_DEVICE. One can (I believe) successfully argue that DMA from a device to main memory should use buffers aligned to cache line size, because the "clean & invalidate" might overwrite data that the device just wrote using DMA. But if a driver does use unaligned buffers, at least this fix will prevent memory corruption outside the buffer. Signed-off-by: Chris Cole Signed-off-by: Russell King Signed-off-by: Sasha Levin --- arch/arm/mm/cache-v7.S | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index de78109d002d..50a70edbc863 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -359,14 +359,16 @@ v7_dma_inv_range: ALT_UP(W(nop)) #endif mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line + addne r0, r0, r2 tst r1, r3 bic r1, r1, r3 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line -1: - mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line - add r0, r0, r2 cmp r0, r1 +1: + mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line + addlo r0, r0, r2 + cmplo r0, r1 blo 1b dsb st ret lr -- GitLab From a2cc1b2d1954ec291ef61aa6976ae10467895f8d Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Fri, 23 Nov 2018 12:25:21 +0100 Subject: [PATCH 0611/1286] ARM: 8815/1: V7M: align v7m_dma_inv_range() with v7 counterpart [ Upstream commit 3d0358d0ba048c5afb1385787aaec8fa5ad78fcc ] Chris has discovered and reported that v7_dma_inv_range() may corrupt memory if address range is not aligned to cache line size. Since the whole cache-v7m.S was lifted form cache-v7.S the same observation applies to v7m_dma_inv_range(). So the fix just mirrors what has been done for v7 with a little specific of M-class. Cc: Chris Cole Signed-off-by: Vladimir Murzin Signed-off-by: Russell King Signed-off-by: Sasha Levin --- arch/arm/mm/cache-v7m.S | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index 788486e830d3..32aa2a2aa260 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -73,9 +73,11 @@ /* * dcimvac: Invalidate data cache line by MVA to PoC */ -.macro dcimvac, rt, tmp - v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC +.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo +.macro dcimvac\c, rt, tmp + v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c .endm +.endr /* * dccmvau: Clean data cache line by MVA to PoU @@ -369,14 +371,16 @@ v7m_dma_inv_range: tst r0, r3 bic r0, r0, r3 dccimvacne r0, r3 + addne r0, r0, r2 subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac tst r1, r3 bic r1, r1, r3 dccimvacne r1, r3 -1: - dcimvac r0, r3 - add r0, r0, r2 cmp r0, r1 +1: + dcimvaclo r0, r3 + addlo r0, r0, r2 + cmplo r0, r1 blo 1b dsb st ret lr -- GitLab From d126d4bf34807707445c8716d9d7c3584a478cfe Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Mon, 3 Dec 2018 13:21:01 +0100 Subject: [PATCH 0612/1286] ethernet: fman: fix wrong of_node_put() in probe function [ Upstream commit ecb239d96d369c23c33d41708646df646de669f4 ] After getting a reference to the platform device's of_node the probe function ends up calling of_find_matching_node() using the node as an argument. The function takes care of decreasing the refcount on it. We are then incorrectly decreasing the refcount on that node again. This patch removes the unwarranted call to of_node_put(). Fixes: 414fd46e7762 ("fsl/fman: Add FMan support") Signed-off-by: Nicolas Saenz Julienne Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/freescale/fman/fman.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/freescale/fman/fman.c b/drivers/net/ethernet/freescale/fman/fman.c index 9530405030a7..97425d94e280 100644 --- a/drivers/net/ethernet/freescale/fman/fman.c +++ b/drivers/net/ethernet/freescale/fman/fman.c @@ -2786,7 +2786,7 @@ static struct fman *read_dts_node(struct platform_device *of_dev) if (!muram_node) { dev_err(&of_dev->dev, "%s: could not find MURAM node\n", __func__); - goto fman_node_put; + goto fman_free; } err = of_address_to_resource(muram_node, 0, @@ -2795,11 +2795,10 @@ static struct fman *read_dts_node(struct platform_device *of_dev) of_node_put(muram_node); dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n", __func__, err); - goto fman_node_put; + goto fman_free; } of_node_put(muram_node); - of_node_put(fm_node); err = devm_request_irq(&of_dev->dev, irq, fman_irq, 0, "fman", fman); if (err < 0) { -- GitLab From 938199486ba9bc203fd312a6e02f7edb1640b2b4 Mon Sep 17 00:00:00 2001 From: Sam Bobroff Date: Mon, 3 Dec 2018 11:53:21 +1100 Subject: [PATCH 0613/1286] drm/ast: Fix connector leak during driver unload [ Upstream commit e594a5e349ddbfdaca1951bb3f8d72f3f1660d73 ] When unloading the ast driver, a warning message is printed by drm_mode_config_cleanup() because a reference is still held to one of the drm_connector structs. Correct this by calling drm_crtc_force_disable_all() in ast_fbdev_destroy(). Signed-off-by: Sam Bobroff Reviewed-by: Daniel Vetter Signed-off-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/1e613f3c630c7bbc72e04a44b178259b9164d2f6.1543798395.git.sbobroff@linux.ibm.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/ast/ast_fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c index 0cd827e11fa2..de26df0c6044 100644 --- a/drivers/gpu/drm/ast/ast_fb.c +++ b/drivers/gpu/drm/ast/ast_fb.c @@ -263,6 +263,7 @@ static void ast_fbdev_destroy(struct drm_device *dev, { struct ast_framebuffer *afb = &afbdev->afb; + drm_crtc_force_disable_all(dev); drm_fb_helper_unregister_fbi(&afbdev->helper); if (afb->obj) { -- GitLab From ab9697222a1da17b6a4e909fab554b6ae5691789 Mon Sep 17 00:00:00 2001 From: Steve French Date: Sat, 3 Nov 2018 15:02:44 -0500 Subject: [PATCH 0614/1286] cifs: In Kconfig CONFIG_CIFS_POSIX needs depends on legacy (insecure cifs) [ Upstream commit 6e785302dad32228819d8066e5376acd15d0e6ba ] Missing a dependency. Shouldn't show cifs posix extensions in Kconfig if CONFIG_CIFS_ALLOW_INSECURE_DIALECTS (ie SMB1 protocol) is disabled. Signed-off-by: Steve French Reviewed-by: Pavel Shilovsky Signed-off-by: Sasha Levin --- fs/cifs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/cifs/Kconfig b/fs/cifs/Kconfig index cb0f1fbe836d..7b95e7971d18 100644 --- a/fs/cifs/Kconfig +++ b/fs/cifs/Kconfig @@ -121,7 +121,7 @@ config CIFS_XATTR config CIFS_POSIX bool "CIFS POSIX Extensions" - depends on CIFS_XATTR + depends on CIFS && CIFS_ALLOW_INSECURE_LEGACY && CIFS_XATTR help Enabling this option will cause the cifs client to attempt to negotiate a newer dialect with servers, such as Samba 3.0.5 -- GitLab From 7e43eec4b4587716505fcf388879e4191331e6fa Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Thu, 6 Dec 2018 19:14:34 +0000 Subject: [PATCH 0615/1286] vhost/vsock: fix reset orphans race with close timeout [ Upstream commit c38f57da428b033f2721b611d84b1f40bde674a8 ] If a local process has closed a connected socket and hasn't received a RST packet yet, then the socket remains in the table until a timeout expires. When a vhost_vsock instance is released with the timeout still pending, the socket is never freed because vhost_vsock has already set the SOCK_DONE flag. Check if the close timer is pending and let it close the socket. This prevents the race which can leak sockets. Reported-by: Maximilian Riemensberger Cc: Graham Whaley Signed-off-by: Stefan Hajnoczi Signed-off-by: Michael S. Tsirkin Signed-off-by: Sasha Levin --- drivers/vhost/vsock.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c index b044a0800805..248533c0f9ac 100644 --- a/drivers/vhost/vsock.c +++ b/drivers/vhost/vsock.c @@ -561,13 +561,21 @@ static void vhost_vsock_reset_orphans(struct sock *sk) * executing. */ - if (!vhost_vsock_get(vsk->remote_addr.svm_cid)) { - sock_set_flag(sk, SOCK_DONE); - vsk->peer_shutdown = SHUTDOWN_MASK; - sk->sk_state = SS_UNCONNECTED; - sk->sk_err = ECONNRESET; - sk->sk_error_report(sk); - } + /* If the peer is still valid, no need to reset connection */ + if (vhost_vsock_get(vsk->remote_addr.svm_cid)) + return; + + /* If the close timeout is pending, let it expire. This avoids races + * with the timeout callback. + */ + if (vsk->close_work_scheduled) + return; + + sock_set_flag(sk, SOCK_DONE); + vsk->peer_shutdown = SHUTDOWN_MASK; + sk->sk_state = SS_UNCONNECTED; + sk->sk_err = ECONNRESET; + sk->sk_error_report(sk); } static int vhost_vsock_dev_release(struct inode *inode, struct file *file) -- GitLab From 73c821e378e86d9152bb53d9e261ac128b05e582 Mon Sep 17 00:00:00 2001 From: Ido Schimmel Date: Thu, 6 Dec 2018 17:44:53 +0000 Subject: [PATCH 0616/1286] mlxsw: spectrum_switchdev: Fix VLAN device deletion via ioctl [ Upstream commit 993107fea5eefdfdfde1ca38d3f01f0bebf76e77 ] When deleting a VLAN device using an ioctl the netdev is unregistered before the VLAN filter is updated via ndo_vlan_rx_kill_vid(). It can lead to a use-after-free in mlxsw in case the VLAN device is deleted while being enslaved to a bridge. The reason for the above is that when mlxsw receives the CHANGEUPPER event, it wrongly assumes that the VLAN device is no longer its upper and thus destroys the internal representation of the bridge port despite the reference count being non-zero. Fix this by checking if the VLAN device is our upper using its real device. In net-next I'm going to remove this trick and instead make mlxsw completely agnostic to the order of the events. Fixes: c57529e1d5d8 ("mlxsw: spectrum: Replace vPorts with Port-VLAN") Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- .../net/ethernet/mellanox/mlxsw/spectrum_switchdev.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c index 32c25772f755..21611613f44c 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c @@ -295,7 +295,13 @@ static bool mlxsw_sp_bridge_port_should_destroy(const struct mlxsw_sp_bridge_port * bridge_port) { - struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(bridge_port->dev); + struct net_device *dev = bridge_port->dev; + struct mlxsw_sp *mlxsw_sp; + + if (is_vlan_dev(dev)) + mlxsw_sp = mlxsw_sp_lower_get(vlan_dev_real_dev(dev)); + else + mlxsw_sp = mlxsw_sp_lower_get(dev); /* In case ports were pulled from out of a bridged LAG, then * it's possible the reference count isn't zero, yet the bridge @@ -1646,7 +1652,7 @@ mlxsw_sp_bridge_8021d_port_leave(struct mlxsw_sp_bridge_device *bridge_device, u16 vid = vlan_dev_vlan_id(bridge_port->dev); mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); - if (WARN_ON(!mlxsw_sp_port_vlan)) + if (!mlxsw_sp_port_vlan) return; mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); -- GitLab From 4bdfff5c4f913c50a419b1e28e5893ebc04a09ff Mon Sep 17 00:00:00 2001 From: "Adamski, Krzysztof (Nokia - PL/Wroclaw)" Date: Fri, 16 Nov 2018 13:24:41 +0000 Subject: [PATCH 0617/1286] i2c: axxia: properly handle master timeout [ Upstream commit 6c7f25cae54b840302e4f1b371dbf318fbf09ab2 ] According to Intel (R) Axxia TM Lionfish Communication Processor Peripheral Subsystem Hardware Reference Manual, the AXXIA I2C module have a programmable Master Wait Timer, which among others, checks the time between commands send in manual mode. When a timeout (25ms) passes, TSS bit is set in Master Interrupt Status register and a Stop command is issued by the hardware. The axxia_i2c_xfer(), does not properly handle this situation, however. For each message a separate axxia_i2c_xfer_msg() is called and this function incorrectly assumes that any interrupt might happen only when waiting for completion. This is mostly correct but there is one exception - a master timeout can trigger if enough time has passed between individual transfers. It will, by definition, happen between transfers when the interrupts are disabled by the code. If that happens, the hardware issues Stop command. The interrupt indicating timeout will not be triggered as soon as we enable them since the Master Interrupt Status is cleared when master mode is entered again (which happens before enabling irqs) meaning this error is lost and the transfer is continued even though the Stop was issued on the bus. The subsequent operations completes without error but a bogus value (0xFF in case of read) is read as the client device is confused because aborted transfer. No error is returned from master_xfer() making caller believe that a valid value was read. To fix the problem, the TSS bit (indicating timeout) in Master Interrupt Status register is checked before each transfer. If it is set, there was a timeout before this transfer and (as described above) the hardware already issued Stop command so the transaction should be aborted thus -ETIMEOUT is returned from the master_xfer() callback. In order to be sure no timeout was issued we can't just read the status just before starting new transaction as there will always be a small window of time (few CPU cycles at best) where this might still happen. For this reason we have to temporally disable the timer before checking for TSS bit. Disabling it will, however, clear the TSS bit so in order to preserve that information, we have to read it in ISR so we have to ensure that the TSS interrupt is not masked between transfers of one transaction. There is no need to call bus recovery or controller reinitialization if that happens so it's skipped. Signed-off-by: Krzysztof Adamski Reviewed-by: Alexander Sverdlin Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-axxia.c | 40 ++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-axxia.c b/drivers/i2c/busses/i2c-axxia.c index 13f07482ec68..deea13838648 100644 --- a/drivers/i2c/busses/i2c-axxia.c +++ b/drivers/i2c/busses/i2c-axxia.c @@ -74,8 +74,7 @@ MST_STATUS_ND) #define MST_STATUS_ERR (MST_STATUS_NAK | \ MST_STATUS_AL | \ - MST_STATUS_IP | \ - MST_STATUS_TSS) + MST_STATUS_IP) #define MST_TX_BYTES_XFRD 0x50 #define MST_RX_BYTES_XFRD 0x54 #define SCL_HIGH_PERIOD 0x80 @@ -241,7 +240,7 @@ static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) */ if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { idev->msg_err = -EPROTO; - i2c_int_disable(idev, ~0); + i2c_int_disable(idev, ~MST_STATUS_TSS); complete(&idev->msg_complete); break; } @@ -299,14 +298,19 @@ static irqreturn_t axxia_i2c_isr(int irq, void *_dev) if (status & MST_STATUS_SCC) { /* Stop completed */ - i2c_int_disable(idev, ~0); + i2c_int_disable(idev, ~MST_STATUS_TSS); complete(&idev->msg_complete); } else if (status & MST_STATUS_SNS) { /* Transfer done */ - i2c_int_disable(idev, ~0); + i2c_int_disable(idev, ~MST_STATUS_TSS); if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len) axxia_i2c_empty_rx_fifo(idev); complete(&idev->msg_complete); + } else if (status & MST_STATUS_TSS) { + /* Transfer timeout */ + idev->msg_err = -ETIMEDOUT; + i2c_int_disable(idev, ~MST_STATUS_TSS); + complete(&idev->msg_complete); } else if (unlikely(status & MST_STATUS_ERR)) { /* Transfer error */ i2c_int_disable(idev, ~0); @@ -339,10 +343,10 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) u32 rx_xfer, tx_xfer; u32 addr_1, addr_2; unsigned long time_left; + unsigned int wt_value; idev->msg = msg; idev->msg_xfrd = 0; - idev->msg_err = 0; reinit_completion(&idev->msg_complete); if (i2c_m_ten(msg)) { @@ -382,9 +386,18 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) else if (axxia_i2c_fill_tx_fifo(idev) != 0) int_mask |= MST_STATUS_TFL; + wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); + /* Disable wait timer temporarly */ + writel(wt_value, idev->base + WAIT_TIMER_CONTROL); + /* Check if timeout error happened */ + if (idev->msg_err) + goto out; + /* Start manual mode */ writel(CMD_MANUAL, idev->base + MST_COMMAND); + writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); + i2c_int_enable(idev, int_mask); time_left = wait_for_completion_timeout(&idev->msg_complete, @@ -395,13 +408,15 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) if (readl(idev->base + MST_COMMAND) & CMD_BUSY) dev_warn(idev->dev, "busy after xfer\n"); - if (time_left == 0) + if (time_left == 0) { idev->msg_err = -ETIMEDOUT; - - if (idev->msg_err == -ETIMEDOUT) i2c_recover_bus(&idev->adapter); + axxia_i2c_init(idev); + } - if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) +out: + if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && + idev->msg_err != -ETIMEDOUT) axxia_i2c_init(idev); return idev->msg_err; @@ -409,7 +424,7 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) static int axxia_i2c_stop(struct axxia_i2c_dev *idev) { - u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC; + u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC | MST_STATUS_TSS; unsigned long time_left; reinit_completion(&idev->msg_complete); @@ -436,6 +451,9 @@ axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) int i; int ret = 0; + idev->msg_err = 0; + i2c_int_enable(idev, MST_STATUS_TSS); + for (i = 0; ret == 0 && i < num; ++i) ret = axxia_i2c_xfer_msg(idev, &msgs[i]); -- GitLab From c39910b57c7f557d304f50775eab28b6c892a7fd Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 21 Nov 2018 10:19:55 +0100 Subject: [PATCH 0618/1286] i2c: scmi: Fix probe error on devices with an empty SMB0001 ACPI device node [ Upstream commit 0544ee4b1ad574aec3b6379af5f5cdee42840971 ] Some AMD based HP laptops have a SMB0001 ACPI device node which does not define any methods. This leads to the following error in dmesg: [ 5.222731] cmi: probe of SMB0001:00 failed with error -5 This commit makes acpi_smbus_cmi_add() return -ENODEV instead in this case silencing the error. In case of a failure of the i2c_add_adapter() call this commit now propagates the error from that call instead of -EIO. Signed-off-by: Hans de Goede Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-scmi.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-scmi.c b/drivers/i2c/busses/i2c-scmi.c index efefcfa24a4c..d2178f701b41 100644 --- a/drivers/i2c/busses/i2c-scmi.c +++ b/drivers/i2c/busses/i2c-scmi.c @@ -364,6 +364,7 @@ static int acpi_smbus_cmi_add(struct acpi_device *device) { struct acpi_smbus_cmi *smbus_cmi; const struct acpi_device_id *id; + int ret; smbus_cmi = kzalloc(sizeof(struct acpi_smbus_cmi), GFP_KERNEL); if (!smbus_cmi) @@ -385,8 +386,10 @@ static int acpi_smbus_cmi_add(struct acpi_device *device) acpi_walk_namespace(ACPI_TYPE_METHOD, smbus_cmi->handle, 1, acpi_smbus_cmi_query_methods, NULL, smbus_cmi, NULL); - if (smbus_cmi->cap_info == 0) + if (smbus_cmi->cap_info == 0) { + ret = -ENODEV; goto err; + } snprintf(smbus_cmi->adapter.name, sizeof(smbus_cmi->adapter.name), "SMBus CMI adapter %s", @@ -397,7 +400,8 @@ static int acpi_smbus_cmi_add(struct acpi_device *device) smbus_cmi->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; smbus_cmi->adapter.dev.parent = &device->dev; - if (i2c_add_adapter(&smbus_cmi->adapter)) { + ret = i2c_add_adapter(&smbus_cmi->adapter); + if (ret) { dev_err(&device->dev, "Couldn't register adapter!\n"); goto err; } @@ -407,7 +411,7 @@ static int acpi_smbus_cmi_add(struct acpi_device *device) err: kfree(smbus_cmi); device->driver_data = NULL; - return -EIO; + return ret; } static int acpi_smbus_cmi_remove(struct acpi_device *device) -- GitLab From 90265a60aff7ad21eed76a9e62159760d1d364b2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 6 Dec 2018 12:55:27 +0900 Subject: [PATCH 0619/1286] i2c: uniphier: fix violation of tLOW requirement for Fast-mode [ Upstream commit 8469636ab5d8c77645b953746c10fda6983a8830 ] Currently, the clock duty is set as tLOW/tHIGH = 1/1. For Fast-mode, tLOW is set to 1.25 us while the I2C spec requires tLOW >= 1.3 us. tLOW/tHIGH = 5/4 would meet both Standard-mode and Fast-mode: Standard-mode: tLOW = 5.56 us, tHIGH = 4.44 us Fast-mode: tLOW = 1.39 us, tHIGH = 1.11 us Signed-off-by: Masahiro Yamada Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-uniphier.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-uniphier.c b/drivers/i2c/busses/i2c-uniphier.c index 454f914ae66d..c488e558aef7 100644 --- a/drivers/i2c/busses/i2c-uniphier.c +++ b/drivers/i2c/busses/i2c-uniphier.c @@ -320,7 +320,13 @@ static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv) uniphier_i2c_reset(priv, true); - writel((cyc / 2 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK); + /* + * Bit30-16: clock cycles of tLOW. + * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us + * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us + * "tLow/tHIGH = 5/4" meets both. + */ + writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK); uniphier_i2c_reset(priv, false); } -- GitLab From 07d4f1c4cd57b6ba4b23d243bcb8d1a63316e784 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 6 Dec 2018 12:55:28 +0900 Subject: [PATCH 0620/1286] i2c: uniphier-f: fix violation of tLOW requirement for Fast-mode [ Upstream commit ece27a337d42a3197935711997f2880f0957ed7e ] Currently, the clock duty is set as tLOW/tHIGH = 1/1. For Fast-mode, tLOW is set to 1.25 us while the I2C spec requires tLOW >= 1.3 us. tLOW/tHIGH = 5/4 would meet both Standard-mode and Fast-mode: Standard-mode: tLOW = 5.56 us, tHIGH = 4.44 us Fast-mode: tLOW = 1.39 us, tHIGH = 1.11 us Signed-off-by: Masahiro Yamada Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-uniphier-f.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-uniphier-f.c b/drivers/i2c/busses/i2c-uniphier-f.c index a403e8579b65..bc26ec822e26 100644 --- a/drivers/i2c/busses/i2c-uniphier-f.c +++ b/drivers/i2c/busses/i2c-uniphier-f.c @@ -470,9 +470,26 @@ static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv) uniphier_fi2c_reset(priv); + /* + * Standard-mode: tLOW + tHIGH = 10 us + * Fast-mode: tLOW + tHIGH = 2.5 us + */ writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); - writel(cyc / 2, priv->membase + UNIPHIER_FI2C_LCTL); + /* + * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us + * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us + * "tLow/tHIGH = 5/4" meets both. + */ + writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL); + /* + * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us + * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us + */ writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); + /* + * Standard-mode: tSU;DAT = 250 ns + * Fast-mode: tSU;DAT = 100 ns + */ writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); uniphier_fi2c_prepare_operation(priv); -- GitLab From 60e3480e0bbf00ffcec4b1409131cf01b69c7cf1 Mon Sep 17 00:00:00 2001 From: Israel Rukshin Date: Wed, 5 Dec 2018 16:54:57 +0000 Subject: [PATCH 0621/1286] nvmet-rdma: fix response use after free [ Upstream commit d7dcdf9d4e15189ecfda24cc87339a3425448d5c ] nvmet_rdma_release_rsp() may free the response before using it at error flow. Fixes: 8407879 ("nvmet-rdma: fix possible bogus dereference under heavy load") Signed-off-by: Israel Rukshin Reviewed-by: Sagi Grimberg Reviewed-by: Max Gurtovoy Signed-off-by: Christoph Hellwig Signed-off-by: Sasha Levin --- drivers/nvme/target/rdma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/target/rdma.c b/drivers/nvme/target/rdma.c index a70b3d24936d..5d8140e58f6f 100644 --- a/drivers/nvme/target/rdma.c +++ b/drivers/nvme/target/rdma.c @@ -524,6 +524,7 @@ static void nvmet_rdma_send_done(struct ib_cq *cq, struct ib_wc *wc) { struct nvmet_rdma_rsp *rsp = container_of(wc->wr_cqe, struct nvmet_rdma_rsp, send_cqe); + struct nvmet_rdma_queue *queue = cq->cq_context; nvmet_rdma_release_rsp(rsp); @@ -531,7 +532,7 @@ static void nvmet_rdma_send_done(struct ib_cq *cq, struct ib_wc *wc) wc->status != IB_WC_WR_FLUSH_ERR)) { pr_err("SEND for CQE 0x%p failed with status %s (%d).\n", wc->wr_cqe, ib_wc_status_msg(wc->status), wc->status); - nvmet_rdma_error_comp(rsp->queue); + nvmet_rdma_error_comp(queue); } } -- GitLab From f1e1eb5c90b6b6a359e584e01468ce0c05801f4d Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 16 May 2018 16:45:51 -0700 Subject: [PATCH 0622/1286] rtc: snvs: Add timeouts to avoid kernel lockups [ Upstream commit cd7f3a249dbed2858e6c2f30e5be7f1f7a709ee2 ] In order to read correctly from asynchronously updated RTC registers, it's necessary to read repeatedly until their values do not change from read to read. It's also necessary to wait for three RTC clock ticks for certain operations. There are no timeouts in this code and these operations could possibly loop forever. To avoid kernel hangs, put in timeouts. The iMX7d can be configured to stop the SRTC on a tamper event, which will lockup the kernel inside this driver as described above. These hangs can happen when running under qemu, which doesn't emulate the SNVS RTC, though currently the driver will refuse to load on qemu due to a timeout in the driver probe method. It could also happen if the SRTC block where somehow placed into reset or the slow speed clock that drives the SRTC counter (but not the CPU) were to stop. The symptoms on a two core iMX7d are a work queue hang on rtc_timer_do_work(), which eventually blocks a systemd fsnotify operation that triggers a work queue flush, causing systemd to hang and thus causing all services that should be started by systemd, like a console getty, to fail to start or stop. Also optimize the wait code to wait less. It only needs to wait for the clock to advance three ticks, not to see it change three times. Cc: Alexandre Belloni Cc: Alessandro Zummo Cc: Fabio Estevam Cc: Shawn Guo Cc: Bryan O'Donoghue Signed-off-by: Trent Piepho Signed-off-by: Alexandre Belloni Signed-off-by: Sasha Levin --- drivers/rtc/rtc-snvs.c | 105 +++++++++++++++++++++++++++-------------- 1 file changed, 70 insertions(+), 35 deletions(-) diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c index 9af591d5223c..71eee39520f0 100644 --- a/drivers/rtc/rtc-snvs.c +++ b/drivers/rtc/rtc-snvs.c @@ -47,49 +47,83 @@ struct snvs_rtc_data { struct clk *clk; }; +/* Read 64 bit timer register, which could be in inconsistent state */ +static u64 rtc_read_lpsrt(struct snvs_rtc_data *data) +{ + u32 msb, lsb; + + regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb); + regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb); + return (u64)msb << 32 | lsb; +} + +/* Read the secure real time counter, taking care to deal with the cases of the + * counter updating while being read. + */ static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) { u64 read1, read2; - u32 val; + unsigned int timeout = 100; + /* As expected, the registers might update between the read of the LSB + * reg and the MSB reg. It's also possible that one register might be + * in partially modified state as well. + */ + read1 = rtc_read_lpsrt(data); do { - regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); - read1 = val; - read1 <<= 32; - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); - read1 |= val; - - regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); - read2 = val; - read2 <<= 32; - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); - read2 |= val; - } while (read1 != read2); + read2 = read1; + read1 = rtc_read_lpsrt(data); + } while (read1 != read2 && --timeout); + if (!timeout) + dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); /* Convert 47-bit counter to 32-bit raw second count */ return (u32) (read1 >> CNTR_TO_SECS_SH); } -static void rtc_write_sync_lp(struct snvs_rtc_data *data) +/* Just read the lsb from the counter, dealing with inconsistent state */ +static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb) { - u32 count1, count2, count3; - int i; - - /* Wait for 3 CKIL cycles */ - for (i = 0; i < 3; i++) { - do { - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); - } while (count1 != count2); - - /* Now wait until counter value changes */ - do { - do { - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); - regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3); - } while (count2 != count3); - } while (count3 == count1); + u32 count1, count2; + unsigned int timeout = 100; + + regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); + do { + count2 = count1; + regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); + } while (count1 != count2 && --timeout); + if (!timeout) { + dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); + return -ETIMEDOUT; } + + *lsb = count1; + return 0; +} + +static int rtc_write_sync_lp(struct snvs_rtc_data *data) +{ + u32 count1, count2; + u32 elapsed; + unsigned int timeout = 1000; + int ret; + + ret = rtc_read_lp_counter_lsb(data, &count1); + if (ret) + return ret; + + /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */ + do { + ret = rtc_read_lp_counter_lsb(data, &count2); + if (ret) + return ret; + elapsed = count2 - count1; /* wrap around _is_ handled! */ + } while (elapsed < 3 && --timeout); + if (!timeout) { + dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n"); + return -ETIMEDOUT; + } + return 0; } static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) @@ -173,9 +207,7 @@ static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); - rtc_write_sync_lp(data); - - return 0; + return rtc_write_sync_lp(data); } static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) @@ -183,11 +215,14 @@ static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) struct snvs_rtc_data *data = dev_get_drvdata(dev); struct rtc_time *alrm_tm = &alrm->time; unsigned long time; + int ret; rtc_tm_to_time(alrm_tm, &time); regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); - rtc_write_sync_lp(data); + ret = rtc_write_sync_lp(data); + if (ret) + return ret; regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); /* Clear alarm interrupt status bit */ -- GitLab From ad962d20d4eb1e690ace8ca9e390e2b05a786999 Mon Sep 17 00:00:00 2001 From: Nicolas Schichan Date: Wed, 19 Dec 2018 22:40:42 +0100 Subject: [PATCH 0623/1286] bpf, arm: fix emit_ldx_r and emit_mov_i using TMP_REG_1 emit_ldx_r() and emit_a32_mov_i() were both using TMP_REG_1 and clashing with each other. Using TMP_REG_2 in emit_ldx_r() fixes the issue. Fixes: ec19e02b343 ("ARM: net: bpf: fix LDX instructions") Cc: Russell King Signed-off-by: Nicolas Schichan Signed-off-by: Daniel Borkmann Signed-off-by: Sasha Levin --- arch/arm/net/bpf_jit_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index ece2d1d43724..dafeb5f81353 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -915,7 +915,7 @@ static inline void emit_str_r(const u8 dst, const u8 src, bool dstk, /* dst = *(size*)(src + off) */ static inline void emit_ldx_r(const u8 dst[], const u8 src, bool dstk, s32 off, struct jit_ctx *ctx, const u8 sz){ - const u8 *tmp = bpf2a32[TMP_REG_1]; + const u8 *tmp = bpf2a32[TMP_REG_2]; const u8 *rd = dstk ? tmp : dst; u8 rm = src; s32 off_max; -- GitLab From 592f5569e18471c07208f74540f4e0f646b226f7 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 21 Dec 2018 14:13:19 +0100 Subject: [PATCH 0624/1286] Linux 4.14.90 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b83477be8d0c..280c7193e246 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 -SUBLEVEL = 89 +SUBLEVEL = 90 EXTRAVERSION = NAME = Petit Gorille -- GitLab From 9792231a642b593aab6eab0c091059a5af79086e Mon Sep 17 00:00:00 2001 From: Dinesh K Garg Date: Fri, 21 Dec 2018 11:39:56 -0800 Subject: [PATCH 0625/1286] msm: mink: release cbobj refs While processing cbobjs, SMCinvoke increases cbobj's refcount when call goes to user space but when call returns from user space, it doesn't decreases refcount. Updating refcount logic for cbobjs. Change-Id: I4324c3f983cee46db2fe9d2081a1be2437de7e8c Signed-off-by: Dinesh K Garg --- drivers/soc/qcom/smcinvoke.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/qcom/smcinvoke.c b/drivers/soc/qcom/smcinvoke.c index c15c2420d227..46304b245d3f 100644 --- a/drivers/soc/qcom/smcinvoke.c +++ b/drivers/soc/qcom/smcinvoke.c @@ -1238,6 +1238,9 @@ static int marshal_out_tzcb_req(const struct smcinvoke_accept *user_req, int32_t tzhandles_to_release[OBJECT_COUNTS_MAX_OO] = {0}; struct smcinvoke_tzcb_req *tzcb_req = cb_txn->cb_req; union smcinvoke_tz_args *tz_args = tzcb_req->args; + put_pending_cbobj_locked( + TZHANDLE_GET_SERVER(cb_txn->cb_req->hdr.tzhandle), + TZHANDLE_GET_OBJID(cb_txn->cb_req->hdr.tzhandle)); tzcb_req->result = user_req->result; FOR_ARGS(i, tzcb_req->hdr.counts, BO) { @@ -1274,6 +1277,13 @@ static int marshal_out_tzcb_req(const struct smcinvoke_accept *user_req, goto out; tzhandles_to_release[i] = tz_args[i].handle; } + FOR_ARGS(i, tzcb_req->hdr.counts, OI) { + if (TZHANDLE_IS_CB_OBJ(tz_args[i].handle)) { + put_pending_cbobj_locked( + TZHANDLE_GET_SERVER(tz_args[i].handle), + TZHANDLE_GET_OBJID(tz_args[i].handle)); + } + } ret = 0; out: if (ret) @@ -1700,6 +1710,8 @@ static int smcinvoke_release(struct inode *nodp, struct file *filp) ret = prepare_send_scm_msg(in_buf, SMCINVOKE_TZ_MIN_BUF_SIZE, out_buf, SMCINVOKE_TZ_MIN_BUF_SIZE, &req, NULL, &release_handles); + + process_piggyback_data(out_buf, SMCINVOKE_TZ_MIN_BUF_SIZE); out: kfree(filp->private_data); free_page((long)in_buf); -- GitLab From cd6a404cc66844a9b369bdecd511dc9963e64ade Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Wed, 19 Dec 2018 14:26:16 +0530 Subject: [PATCH 0626/1286] msm: camera: sensor: Fix uninitialized vars Initialize uninitialized local variables with appropriate values and potential null pointer de-reference Change-Id: I826549869417b40abf22b7af456017ad28242745 Signed-off-by: Tony Lijo Jose --- .../cam_actuator/cam_actuator_core.c | 2 +- .../cam_csiphy/cam_csiphy_core.c | 4 ++-- .../cam_sensor/cam_sensor_core.c | 18 +++++++++++------- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c index 31d9d35062bd..23fd234d8787 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -414,7 +414,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, size_t len_of_buff = 0; uint32_t *offset = NULL; uint32_t *cmd_buf = NULL; - uint64_t generic_ptr; + uint64_t generic_ptr = 0; struct common_header *cmm_hdr = NULL; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 005957338567..dd8b4eb7e601 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -157,12 +157,12 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, struct cam_config_dev_cmd *cfg_dev) { int32_t rc = 0; - uint64_t generic_ptr; + uint64_t generic_ptr = 0; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; uint32_t *cmd_buf = NULL; struct cam_csiphy_info *cam_cmd_csiphy_info = NULL; - size_t len; + size_t len = 0; if (!cfg_dev || !csiphy_dev) { CAM_ERR(CAM_CSIPHY, "Invalid Args"); diff --git a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c index cde59ac9cf19..0492e82bb75a 100644 --- a/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/ais/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -91,7 +91,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, void *arg) { int32_t rc = 0; - uint64_t generic_ptr; + uint64_t generic_ptr = 0; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; @@ -455,13 +455,13 @@ int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) { - int rc = 0, i; + int rc = 0, i = 0; void *packet = NULL, *cmd_buf1 = NULL; - uint32_t *cmd_buf; - void *ptr; - size_t len; - struct cam_packet *pkt; - struct cam_cmd_buf_desc *cmd_desc; + uint32_t *cmd_buf = NULL; + void *ptr = NULL; + size_t len = 0; + struct cam_packet *pkt = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; rc = cam_mem_get_cpu_buf(handle, (uint64_t *)&packet, &len); @@ -470,6 +470,10 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) return -EINVAL; } pkt = (struct cam_packet *)packet; + if (pkt == NULL) { + CAM_ERR(CAM_SENSOR, "Invalid packet address"); + return -EINVAL; + } cmd_desc = (struct cam_cmd_buf_desc *) ((uint32_t *)&pkt->payload + pkt->cmd_buf_offset/4); if (cmd_desc == NULL) { -- GitLab From 8e6a0d2ecc7ed82f2d6216e6fe7cf782f4938733 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 28 Nov 2018 15:51:55 +0530 Subject: [PATCH 0627/1286] power: smb5: Enable uUSB moisture detection support for PMI632 Enable micro USB moisture detection support for PMI632 subtype. Also, TYPEC_U_USB_WATER_PROTECTION_CFG register address differs on PMI632 in comparison to PM6150/PM8150b and TYPE_C_SKU_MICRO_USB_MODE register is defined for only PMI632. Add logic to support both PMI632 and PM6150 register address space. Change-Id: I038531ab5efa9baf55d3c14ca123d38b08f63937 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/qpnp-smb5.c | 12 ++++++++---- drivers/power/supply/qcom/smb5-lib.c | 24 +++++++++++++++--------- drivers/power/supply/qcom/smb5-reg.h | 11 ++++++----- 3 files changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index bd89143a3a99..64add8f6ffb0 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -303,6 +303,8 @@ static int smb5_chg_config_init(struct smb5 *chip) chg->name = "pmi632_charger"; /* PMI632 does not support PD */ chg->pd_not_supported = true; + if (pmic_rev_id->rev4 >= 2) + chg->uusb_moisture_protection_enabled = true; chg->hw_max_icl_ua = (chip->dt.usb_icl_ua > 0) ? chip->dt.usb_icl_ua : PMI632_MAX_ICL_UA; @@ -1885,7 +1887,9 @@ static int smb5_configure_micro_usb(struct smb_charger *chg) } /* Disable periodic monitoring of CC_ID pin */ - rc = smblib_write(chg, TYPEC_U_USB_WATER_PROTECTION_CFG_REG, 0); + rc = smblib_write(chg, ((chg->smb_version == PMI632_SUBTYPE) ? + PMI632_TYPEC_U_USB_WATER_PROTECTION_CFG_REG : + TYPEC_U_USB_WATER_PROTECTION_CFG_REG), 0); if (rc < 0) { dev_err(chg->dev, "Couldn't disable periodic monitoring of CC_ID rc=%d\n", rc); @@ -2131,10 +2135,10 @@ static int smb5_init_hw(struct smb5 *chip) /* * PMI632 can have the connector type defined by a dedicated register - * TYPEC_MICRO_USB_MODE_REG or by a common TYPEC_U_USB_CFG_REG. + * PMI632_TYPEC_MICRO_USB_MODE_REG or by a common TYPEC_U_USB_CFG_REG. */ if (chg->smb_version == PMI632_SUBTYPE) { - rc = smblib_read(chg, TYPEC_MICRO_USB_MODE_REG, &val); + rc = smblib_read(chg, PMI632_TYPEC_MICRO_USB_MODE_REG, &val); if (rc < 0) { dev_err(chg->dev, "Couldn't read USB mode rc=%d\n", rc); return rc; @@ -2143,7 +2147,7 @@ static int smb5_init_hw(struct smb5 *chip) } /* - * If TYPEC_MICRO_USB_MODE_REG is not set and for all non-PMI632 + * If PMI632_TYPEC_MICRO_USB_MODE_REG is not set and for all non-PMI632 * check the connector type using TYPEC_U_USB_CFG_REG. */ if (!type) { diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index d69e99aef372..86423f9a453a 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -1430,13 +1430,15 @@ static int smblib_set_moisture_protection(struct smb_charger *chg, /* Set 1% duty cycle on ID detection */ rc = smblib_masked_write(chg, - TYPEC_U_USB_WATER_PROTECTION_CFG_REG, - EN_MICRO_USB_WATER_PROTECTION_BIT | - MICRO_USB_DETECTION_ON_TIME_CFG_MASK | - MICRO_USB_DETECTION_PERIOD_CFG_MASK, - EN_MICRO_USB_WATER_PROTECTION_BIT | - MICRO_USB_DETECTION_ON_TIME_20_MS | - MICRO_USB_DETECTION_PERIOD_X_100); + ((chg->smb_version == PMI632_SUBTYPE) ? + PMI632_TYPEC_U_USB_WATER_PROTECTION_CFG_REG : + TYPEC_U_USB_WATER_PROTECTION_CFG_REG), + EN_MICRO_USB_WATER_PROTECTION_BIT | + MICRO_USB_DETECTION_ON_TIME_CFG_MASK | + MICRO_USB_DETECTION_PERIOD_CFG_MASK, + EN_MICRO_USB_WATER_PROTECTION_BIT | + MICRO_USB_DETECTION_ON_TIME_20_MS | + MICRO_USB_DETECTION_PERIOD_X_100); if (rc < 0) { smblib_err(chg, "Couldn't set 1 percent CC_ID duty cycle rc=%d\n", rc); @@ -1461,7 +1463,9 @@ static int smblib_set_moisture_protection(struct smb_charger *chg, } /* Disable periodic monitoring of CC_ID pin */ - rc = smblib_write(chg, TYPEC_U_USB_WATER_PROTECTION_CFG_REG, 0); + rc = smblib_write(chg, ((chg->smb_version == PMI632_SUBTYPE) ? + PMI632_TYPEC_U_USB_WATER_PROTECTION_CFG_REG : + TYPEC_U_USB_WATER_PROTECTION_CFG_REG), 0); if (rc < 0) { smblib_err(chg, "Couldn't disable 1 percent CC_ID duty cycle rc=%d\n", rc); @@ -5685,7 +5689,9 @@ static void smblib_moisture_protection_work(struct work_struct *work) * Disable 1% duty cycle on CC_ID pin and enable uUSB factory mode * detection to track any change on RID, as interrupts are disable. */ - rc = smblib_write(chg, TYPEC_U_USB_WATER_PROTECTION_CFG_REG, 0); + rc = smblib_write(chg, ((chg->smb_version == PMI632_SUBTYPE) ? + PMI632_TYPEC_U_USB_WATER_PROTECTION_CFG_REG : + TYPEC_U_USB_WATER_PROTECTION_CFG_REG), 0); if (rc < 0) { smblib_err(chg, "Couldn't disable periodic monitoring of CC_ID rc=%d\n", rc); diff --git a/drivers/power/supply/qcom/smb5-reg.h b/drivers/power/supply/qcom/smb5-reg.h index 2376aeb46be5..0069ea0cf42f 100644 --- a/drivers/power/supply/qcom/smb5-reg.h +++ b/drivers/power/supply/qcom/smb5-reg.h @@ -436,12 +436,13 @@ enum { #define EN_MICRO_USB_FACTORY_MODE_BIT BIT(1) #define EN_MICRO_USB_MODE_BIT BIT(0) -#define TYPEC_U_USB_WATER_PROTECTION_CFG_REG (TYPEC_BASE + 0x73) -#define EN_MICRO_USB_WATER_PROTECTION_BIT BIT(4) -#define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2) -#define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0) +#define PMI632_TYPEC_U_USB_WATER_PROTECTION_CFG_REG (TYPEC_BASE + 0x72) +#define TYPEC_U_USB_WATER_PROTECTION_CFG_REG (TYPEC_BASE + 0x73) +#define EN_MICRO_USB_WATER_PROTECTION_BIT BIT(4) +#define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2) +#define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0) -#define TYPEC_MICRO_USB_MODE_REG (TYPEC_BASE + 0x73) +#define PMI632_TYPEC_MICRO_USB_MODE_REG (TYPEC_BASE + 0x73) #define MICRO_USB_MODE_ONLY_BIT BIT(0) /******************************** * MISC Peripheral Registers * -- GitLab From c995e9a997e96bd2075908a16d0974d0d4081bde Mon Sep 17 00:00:00 2001 From: Srinivas Ramana Date: Tue, 18 Dec 2018 22:53:10 +0530 Subject: [PATCH 0628/1286] genirq: Make sure the affinity to be set is not empty If the default_affinity is managed/initialized by a system and all the cpus present in irq_default_affinity are hotplugged out we may end up passing a cpumask of 0 to irq_do_set_affinity(). Fix this by falling back to cpu_online_mask in case the calculated affinity becomes zero. Change-Id: I11f6e6dd7e44865330296f7c48aa2d0594d31610 Signed-off-by: Srinivas Ramana --- kernel/irq/manage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 1a411203b1f9..406aeb8c5f9a 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -363,6 +363,9 @@ int irq_setup_affinity(struct irq_desc *desc) } cpumask_and(&mask, cpu_online_mask, set); + if (cpumask_empty(&mask)) + cpumask_copy(&mask, cpu_online_mask); + if (node != NUMA_NO_NODE) { const struct cpumask *nodemask = cpumask_of_node(node); -- GitLab From 11d34a9f442594a2f4f0c7a735fabeda34d07d9a Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Fri, 21 Dec 2018 12:30:09 -0800 Subject: [PATCH 0629/1286] msm: camera: reqmgr: Fix frame skip condition During transiting from non-sync mode to sync mode with pending requests to be still serviced in non-sync mode the frame skip condition needs to be reset. Change-Id: I613ae5bb98e67a9f613e3ea02ce4a8c1a078814d Signed-off-by: Karthik Anantha Ram --- .../media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c index 393e34244f15..7568a7fb4660 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c @@ -890,7 +890,6 @@ static int __cam_req_mgr_check_sync_req_is_ready( CAM_DBG(CAM_CRM, "Req: %lld [other link] not next req to be applied on link: %x", req_id, sync_link->link_hdl); - link->sync_link_sof_skip = true; return -EAGAIN; } @@ -1036,6 +1035,9 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, } spin_unlock_bh(&link->link_state_spin_lock); + if (link->sync_link_sof_skip) + link->sync_link_sof_skip = false; + if (link->trigger_mask == link->subscribe_event) { slot->status = CRM_SLOT_STATUS_REQ_APPLIED; link->trigger_mask = 0; -- GitLab From ad59e6f0075d3eb848ad8cebad2a3724080225eb Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 4 Sep 2018 10:45:42 -0700 Subject: [PATCH 0630/1286] ARM: dts: msm: Add minidump id for MSS Subsystem on SM8150 To collect minidump, we need to get subsystem ToC, which is obtained by dereferencing global ToC. To do this, the minidump id for a subsystem is required, as it is the offset of the subsystem's entry in the global ToC. Add minidump id for MSS to collect minidumps. Change-Id: I0119fd7f948268f623ac1d638d0a8490dc742b50 Signed-off-by: Isaac J. Manjarres --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b7bdd1f560aa..a4b7db045bf8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1653,6 +1653,7 @@ memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; qcom,sysmon-id = <0>; + qcom,minidump-id = <3>; qcom,ssctl-instance-id = <0x12>; qcom,pas-id = <4>; qcom,smem-id = <421>; -- GitLab From 94da06804aca704ac6cf451337da3df5d30ee83b Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Tue, 18 Dec 2018 21:16:40 -0800 Subject: [PATCH 0631/1286] msm: camera: Correct packet length check Userspace is sending csl packets and correct length check is mandate before accessing the offset. This change corrects the length check condition. Change-Id: I79f48cb21b14f55be019e8f6fb09cef587248402 Signed-off-by: Jigarkumar Zala --- .../cam_actuator/cam_actuator_core.c | 36 +++++++++-- .../cam_csiphy/cam_csiphy_core.c | 28 ++++++++- .../cam_flash/cam_flash_core.c | 63 +++++++++++++++---- .../cam_sensor_module/cam_ois/cam_ois_core.c | 30 ++++++++- .../cam_sensor/cam_sensor_core.c | 32 ++++++++-- 5 files changed, 162 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c index 5a4af3e6ec3e..2e533981edf7 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -413,6 +413,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, int32_t i = 0; uint32_t total_cmd_buf_in_bytes = 0; size_t len_of_buff = 0; + size_t remaining_len_of_buff = 0; uint32_t *offset = NULL; uint32_t *cmd_buf = NULL; uintptr_t generic_ptr; @@ -450,18 +451,31 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, return rc; } - if (config.offset > len_of_buff) { + remaining_len_of_buff = len_of_buff; + if ((sizeof(struct cam_packet) > len_of_buff) || + ((size_t)config.offset >= len_of_buff - + sizeof(struct cam_packet))) { CAM_ERR(CAM_ACTUATOR, - "offset is out of bounds: offset: %lld len: %zu", - config.offset, len_of_buff); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buff); rc = -EINVAL; goto rel_pkt_buf; } + remaining_len_of_buff -= config.offset; csl_packet = (struct cam_packet *) (generic_pkt_ptr + (uint32_t)config.offset); - CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", - csl_packet->header.op_code); + + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { + CAM_ERR(CAM_ACTUATOR, + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + + remaining_len_of_buff -= sizeof(struct cam_packet); + CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", csl_packet->header.op_code); if ((csl_packet->header.op_code & 0xFFFFFF) != CAM_ACTUATOR_PACKET_OPCODE_INIT && @@ -470,12 +484,22 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_DBG(CAM_ACTUATOR, "reject request %lld, last request to flush %lld", csl_packet->header.request_id, a_ctrl->last_flush_req); - return -EINVAL; + rc = -EINVAL; + goto rel_pkt_buf; } if (csl_packet->header.request_id > a_ctrl->last_flush_req) a_ctrl->last_flush_req = 0; + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_ACTUATOR, + "InVal len: %zu", remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_ACTUATOR_PACKET_OPCODE_INIT: offset = (uint32_t *)&csl_packet->payload; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index a7e9bdeaecad..095665c03290 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -165,6 +165,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, uint32_t *cmd_buf = NULL; struct cam_csiphy_info *cam_cmd_csiphy_info = NULL; size_t len; + size_t remaining_len_of_buff; if (!cfg_dev || !csiphy_dev) { CAM_ERR(CAM_CSIPHY, "Invalid Args"); @@ -178,17 +179,38 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, return rc; } - if (cfg_dev->offset > len) { + remaining_len_of_buff = len; + if ((sizeof(struct cam_packet) > len) || + ((size_t)cfg_dev->offset >= len - sizeof(struct cam_packet))) { CAM_ERR(CAM_CSIPHY, - "offset is out of bounds: offset: %lld len: %zu", - cfg_dev->offset, len); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len); rc = -EINVAL; goto rel_pkt_buf; } + remaining_len_of_buff -= cfg_dev->offset; csl_packet = (struct cam_packet *) (generic_pkt_ptr + (uint32_t)cfg_dev->offset); + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { + CAM_ERR(CAM_CSIPHY, + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + + remaining_len_of_buff -= sizeof(struct cam_packet); + + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_CSIPHY, "InVal len: %zu", remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + cmd_desc = (struct cam_cmd_buf_desc *) ((uint32_t *)&csl_packet->payload + csl_packet->cmd_buf_offset / 4); diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c index 97ab07d48b98..bf0e7e9bb70f 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c @@ -904,6 +904,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) uint32_t *offset = NULL; uint32_t frm_offset = 0; size_t len_of_buffer; + size_t remaining_len_of_buff; struct cam_flash_init *flash_init = NULL; struct common_header *cmn_hdr = NULL; struct cam_control *ioctl_ctrl = NULL; @@ -931,20 +932,30 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = cam_mem_get_cpu_buf(config.packet_handle, &generic_ptr, &len_of_buffer); if (rc) { - CAM_ERR(CAM_FLASH, "Failed in getting the buffer : %d", rc); + CAM_ERR(CAM_FLASH, "Failed in getting the packet : %d", rc); return rc; } - - if (config.offset > len_of_buffer) { + remaining_len_of_buff = len_of_buffer; + if ((sizeof(struct cam_packet) > len_of_buffer) || + ((size_t)config.offset >= len_of_buffer - + sizeof(struct cam_packet))) { CAM_ERR(CAM_FLASH, - "offset is out of bounds: offset: %lld len: %zu", - config.offset, len_of_buffer); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buffer); return -EINVAL; } + remaining_len_of_buff -= config.offset; /* Add offset to the flash csl header */ csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { + CAM_ERR(CAM_FLASH, + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); + return -EINVAL; + } + if ((csl_packet->header.op_code & 0xFFFFFF) != CAM_FLASH_PACKET_OPCODE_INIT && csl_packet->header.request_id <= fctrl->last_flush_req @@ -958,6 +969,14 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (csl_packet->header.request_id > fctrl->last_flush_req) fctrl->last_flush_req = 0; + remaining_len_of_buff -= sizeof(struct cam_packet); + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_FLASH, "InVal len: %zu", remaining_len_of_buff); + return -EINVAL; + } + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { /* INIT packet*/ @@ -1224,6 +1243,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) uint32_t *offset = NULL; uint32_t frm_offset = 0; size_t len_of_buffer; + size_t remaining_len_of_buff; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; @@ -1259,21 +1279,32 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = cam_mem_get_cpu_buf(config.packet_handle, &generic_ptr, &len_of_buffer); if (rc) { - CAM_ERR(CAM_FLASH, "Failed in getting the buffer : %d", rc); + CAM_ERR(CAM_FLASH, "Failed in getting the packet: %d", rc); return rc; } - if (config.offset > len_of_buffer) { + remaining_len_of_buff = len_of_buffer; + if ((sizeof(struct cam_packet) > len_of_buffer) || + ((size_t)config.offset >= len_of_buffer - + sizeof(struct cam_packet))) { CAM_ERR(CAM_FLASH, - "offset is out of bounds: offset: %lld len: %zu", - config.offset, len_of_buffer); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buffer); rc = -EINVAL; goto rel_pkt_buf; } + remaining_len_of_buff -= config.offset; /* Add offset to the flash csl header */ - csl_packet = - (struct cam_packet *)(generic_ptr + (uint32_t)config.offset); + csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { + CAM_ERR(CAM_FLASH, + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } if ((csl_packet->header.op_code & 0xFFFFFF) != CAM_FLASH_PACKET_OPCODE_INIT && @@ -1289,6 +1320,16 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (csl_packet->header.request_id > fctrl->last_flush_req) fctrl->last_flush_req = 0; + remaining_len_of_buff -= sizeof(struct cam_packet); + + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_FLASH, "InVal len: %zu", remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { /* INIT packet*/ diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c index eff5c15fe43a..8e51cd95e448 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c @@ -433,6 +433,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) struct cam_cmd_buf_desc *cmd_desc = NULL; uintptr_t generic_pkt_addr; size_t pkt_len; + size_t remaining_len_of_buff = 0; struct cam_packet *csl_packet = NULL; size_t len_of_buff = 0; uint32_t *offset = NULL, *cmd_buf; @@ -453,16 +454,39 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) return rc; } - if (dev_config.offset > pkt_len) { + remaining_len_of_buff = pkt_len; + if ((sizeof(struct cam_packet) > pkt_len) || + ((size_t)dev_config.offset >= pkt_len - + sizeof(struct cam_packet))) { CAM_ERR(CAM_OIS, - "offset is out of bound: off: %lld len: %zu", - dev_config.offset, pkt_len); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), pkt_len); rc = -EINVAL; goto rel_pkt; } + remaining_len_of_buff -= dev_config.offset; csl_packet = (struct cam_packet *) (generic_pkt_addr + (uint32_t)dev_config.offset); + + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { + CAM_ERR(CAM_OIS, + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt; + } + + remaining_len_of_buff -= sizeof(struct cam_packet); + + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_OIS, "InVal len: %zu", remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt; + } + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_OIS_PACKET_OPCODE_INIT: offset = (uint32_t *)&csl_packet->payload; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c index 5bbe2865f827..edd0cd28bd00 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -94,6 +94,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, struct cam_cmd_buf_desc *cmd_desc = NULL; struct i2c_settings_array *i2c_reg_settings = NULL; size_t len_of_buff = 0; + size_t remaining_len_of_buff = 0; uint32_t *offset = NULL; struct cam_config_dev_cmd config; struct i2c_data_settings *i2c_data = NULL; @@ -115,20 +116,35 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, &generic_ptr, &len_of_buff); if (rc < 0) { - CAM_ERR(CAM_SENSOR, "Failed in getting the buffer: %d", rc); + CAM_ERR(CAM_SENSOR, "Failed in getting the packet: %d", rc); return rc; } + remaining_len_of_buff = len_of_buff; + if ((sizeof(struct cam_packet) > len_of_buff) || + ((size_t)config.offset >= len_of_buff - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_SENSOR, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + + remaining_len_of_buff -= config.offset; csl_packet = (struct cam_packet *)(generic_ptr + (uint32_t)config.offset); - if (config.offset > len_of_buff) { + + if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { CAM_ERR(CAM_SENSOR, - "offset is out of bounds: off: %lld len: %zu", - config.offset, len_of_buff); + "Inval pkt_header_size: %zu, len:of_buff: %zu", + csl_packet->header.size, remaining_len_of_buff); rc = -EINVAL; goto rel_pkt_buf; } + remaining_len_of_buff -= sizeof(struct cam_packet); + if ((csl_packet->header.op_code & 0xFFFFFF) != CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG && csl_packet->header.request_id <= s_ctrl->last_flush_req @@ -225,6 +241,14 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, goto rel_pkt_buf; } + if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || + (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > + remaining_len_of_buff)) { + CAM_ERR(CAM_SENSOR, "InVal len: %zu", remaining_len_of_buff); + rc = -EINVAL; + goto rel_pkt_buf; + } + offset = (uint32_t *)&csl_packet->payload; offset += csl_packet->cmd_buf_offset / 4; cmd_desc = (struct cam_cmd_buf_desc *)(offset); -- GitLab From b256b9c894cd2d092e4a3c017aa6596bbf2270d2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 28 Dec 2018 13:06:27 +0530 Subject: [PATCH 0632/1286] clk: qcom: rcg: Return failure for RCG update In case of update config failure, return -EBUSY. Change-Id: Id753728c5045130ae68908aece9ec500ce1bc72d Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rcg2.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 63bbb49afc17..1058f541dbfe 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -147,8 +147,7 @@ static int update_config(struct clk_rcg2 *rcg, u32 cfg) WARN_CLK(hw->core, name, count == 0, "rcg didn't update its configuration."); - - return 0; + return -EBUSY; } static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) -- GitLab From e25d12eb70da2bcc43f21dd1fc91e1c532936b44 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Fri, 28 Dec 2018 15:43:08 +0530 Subject: [PATCH 0633/1286] msm: camera: isp: Avoid cuncurrency between CRM operations Camera context layer works on state machine principle that allows events to drive state transition and operation based on current state. Taking mutex_lock while processing the events and operations will avoid any conflict because of scheduling and state transitions. Change-Id: I6042bb9bf6cb3b6eb1c2dcb6646cf0b353623971 Signed-off-by: Abhilash Kumar --- drivers/media/platform/msm/camera/cam_core/cam_context.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/msm/camera/cam_core/cam_context.c b/drivers/media/platform/msm/camera/cam_core/cam_context.c index 081a96d311e3..1a46f88dd335 100644 --- a/drivers/media/platform/msm/camera/cam_core/cam_context.c +++ b/drivers/media/platform/msm/camera/cam_core/cam_context.c @@ -172,6 +172,7 @@ int cam_context_handle_crm_apply_req(struct cam_context *ctx, return -EINVAL; } + mutex_lock(&ctx->ctx_mutex); if (ctx->state_machine[ctx->state].crm_ops.apply_req) { rc = ctx->state_machine[ctx->state].crm_ops.apply_req(ctx, apply); @@ -180,6 +181,7 @@ int cam_context_handle_crm_apply_req(struct cam_context *ctx, ctx->dev_hdl, ctx->state); rc = -EPROTO; } + mutex_unlock(&ctx->ctx_mutex); return rc; } -- GitLab From 199699336d671bc8a9f679601eab9ddd916b1595 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Mon, 24 Dec 2018 21:20:34 +0530 Subject: [PATCH 0634/1286] msm: kgsl: improve memory stats maintenance While freeing memory, page_alloc memstat wrongly shows that the memory is freed while the process is still ongoing. While allocating memory if something goes wrong during the process, the memory allocated till that point is not reflected in page_alloc. Change the point of updation of page_alloc. Also add two stats, one to track allocation in progress and the other to track free in progress. Change-Id: I494c873fd90b8e504d5eea6966855b50493d9c09 Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/kgsl.c | 2 ++ drivers/gpu/msm/kgsl.h | 2 ++ drivers/gpu/msm/kgsl_sharedmem.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index bb481e0affc0..26243c558b68 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -4684,6 +4684,8 @@ struct kgsl_driver kgsl_driver = { .stats.secure_max = ATOMIC_LONG_INIT(0), .stats.mapped = ATOMIC_LONG_INIT(0), .stats.mapped_max = ATOMIC_LONG_INIT(0), + .stats.page_free_pending = ATOMIC_LONG_INIT(0), + .stats.page_alloc_pending = ATOMIC_LONG_INIT(0), }; EXPORT_SYMBOL(kgsl_driver); diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h index f495515dad69..dfb5050c734b 100644 --- a/drivers/gpu/msm/kgsl.h +++ b/drivers/gpu/msm/kgsl.h @@ -158,6 +158,8 @@ struct kgsl_driver { atomic_long_t secure_max; atomic_long_t mapped; atomic_long_t mapped_max; + atomic_long_t page_free_pending; + atomic_long_t page_alloc_pending; } stats; unsigned int full_cache_threshold; struct workqueue_struct *workqueue; diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c index eb63e8d36147..ca49afd49dd9 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.c +++ b/drivers/gpu/msm/kgsl_sharedmem.c @@ -533,7 +533,8 @@ static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc) atomic_long_sub(memdesc->size, &kgsl_driver.stats.secure); } else { - atomic_long_sub(memdesc->size, &kgsl_driver.stats.page_alloc); + atomic_long_add(memdesc->size, + &kgsl_driver.stats.page_free_pending); } /* Free pages using the pages array for non secure paged memory */ @@ -542,6 +543,11 @@ static void kgsl_page_alloc_free(struct kgsl_memdesc *memdesc) else kgsl_pool_free_sgt(memdesc->sgt); + if (!(memdesc->priv & KGSL_MEMDESC_TZ_LOCKED)) { + atomic_long_sub(memdesc->size, &kgsl_driver.stats.page_alloc); + atomic_long_sub(memdesc->size, + &kgsl_driver.stats.page_free_pending); + } } /* @@ -886,6 +892,8 @@ kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc, * are allocated by kgsl. This helps with improving the vm fault * routine by finding the faulted page in constant time. */ + if (!(memdesc->flags & KGSL_MEMFLAGS_SECURE)) + atomic_long_add(size, &kgsl_driver.stats.page_alloc_pending); memdesc->pages = kgsl_malloc(len_alloc * sizeof(struct page *)); memdesc->page_count = 0; @@ -980,6 +988,9 @@ kgsl_sharedmem_page_alloc_user(struct kgsl_memdesc *memdesc, &kgsl_driver.stats.page_alloc_max); done: + if (!(memdesc->flags & KGSL_MEMFLAGS_SECURE)) + atomic_long_sub(size, &kgsl_driver.stats.page_alloc_pending); + if (ret) { if (memdesc->pages) { unsigned int count = 1; -- GitLab From d63f62669b74cf65b21a539bbbc5215a93c16f82 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 17 Dec 2018 16:10:53 +0530 Subject: [PATCH 0635/1286] ARM: dts: msm: Enable CX IPeak cdev and thermal zone for TRINKET Enable CX peak current throttling cooling device and thermal zone rule to enable this cooling device for TRINKET. It can vote for CXIP LM hardware based on preset threshold. Change-Id: I3fee3506f6069087e95a6fc1f68d4efc507954dd Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index a0c9be8df109..077ebf480755 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -77,6 +77,14 @@ }; }; }; + + cxip_cdev: cxip-cdev@3ed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x3ed000 0xa008>; + qcom,thermal-client-offset = <0x9000>; + qcom,bypass-client-list = <0xa004>; + #cooling-cells = <2>; + }; }; &thermal_zones { @@ -1549,4 +1557,24 @@ }; }; }; + + cdsp-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + thermal-governor = "step_wise"; + trips { + cdsp_config: cdsp-config { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + }; + cooling-maps { + cxip-cdev { + trip = <&cdsp_config>; + cooling-device = <&cxip_cdev 1 1>; + }; + }; + }; }; -- GitLab From f9b2f0067a178b2ef93c5191ae2bcbeffda9fbeb Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Thu, 29 Nov 2018 13:57:53 +0800 Subject: [PATCH 0636/1286] locking/rwsem: for rwsem prio aware enhancement When add into waiting list will be prio aware, lower prio value means higher priority task will get lock before lower priority task. Only try to preempt waiters with which task priority which is higher than DEFAULT_PRIO. To avoid starvation, add count to record how many waiters preempt to queue in wait list. If preempt count is exceed MAX_PREEMPT_ALLOWED, use simple FIFO to queue in the wait list until the wait list is empty. Change-Id: I4d5fe6a823a16c9762e2e2f416d34bdd701341c4 Signed-off-by: Maria Yu --- include/linux/rwsem.h | 13 ++++++- kernel/Kconfig.locks | 4 +++ kernel/locking/rwsem-xadd.c | 31 +++++++++-------- kernel/locking/rwsem.h | 68 +++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+), 16 deletions(-) diff --git a/include/linux/rwsem.h b/include/linux/rwsem.h index c427ffaa4904..fa3291f9b38a 100644 --- a/include/linux/rwsem.h +++ b/include/linux/rwsem.h @@ -42,6 +42,10 @@ struct rw_semaphore { #ifdef CONFIG_DEBUG_LOCK_ALLOC struct lockdep_map dep_map; #endif +#ifdef CONFIG_RWSEM_PRIO_AWARE + /* count for waiters preempt to queue in wait list */ + long m_count; +#endif }; /* @@ -83,12 +87,19 @@ static inline int rwsem_is_locked(struct rw_semaphore *sem) #define __RWSEM_OPT_INIT(lockname) #endif +#ifdef CONFIG_RWSEM_PRIO_AWARE +#define __RWSEM_PRIO_AWARE_INIT(lockname) .m_count = 0 +#else +#define __RWSEM_PRIO_AWARE_INIT(lockname) +#endif + #define __RWSEM_INITIALIZER(name) \ { __RWSEM_INIT_COUNT(name), \ .wait_list = LIST_HEAD_INIT((name).wait_list), \ .wait_lock = __RAW_SPIN_LOCK_UNLOCKED(name.wait_lock) \ __RWSEM_OPT_INIT(name) \ - __RWSEM_DEP_MAP_INIT(name) } + __RWSEM_DEP_MAP_INIT(name), \ + __RWSEM_PRIO_AWARE_INIT(name) } #define DECLARE_RWSEM(name) \ struct rw_semaphore name = __RWSEM_INITIALIZER(name) diff --git a/kernel/Kconfig.locks b/kernel/Kconfig.locks index 84d882f3e299..621c296fe8f8 100644 --- a/kernel/Kconfig.locks +++ b/kernel/Kconfig.locks @@ -248,3 +248,7 @@ config ARCH_USE_QUEUED_RWLOCKS config QUEUED_RWLOCKS def_bool y if ARCH_USE_QUEUED_RWLOCKS depends on SMP + +config RWSEM_PRIO_AWARE + def_bool y + depends on RWSEM_XCHGADD_ALGORITHM diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c index a90336779375..8b41d8883dce 100644 --- a/kernel/locking/rwsem-xadd.c +++ b/kernel/locking/rwsem-xadd.c @@ -90,21 +90,13 @@ void __init_rwsem(struct rw_semaphore *sem, const char *name, sem->owner = NULL; osq_lock_init(&sem->osq); #endif +#ifdef CONFIG_RWSEM_PRIO_AWARE + sem->m_count = 0; +#endif } EXPORT_SYMBOL(__init_rwsem); -enum rwsem_waiter_type { - RWSEM_WAITING_FOR_WRITE, - RWSEM_WAITING_FOR_READ -}; - -struct rwsem_waiter { - struct list_head list; - struct task_struct *task; - enum rwsem_waiter_type type; -}; - enum rwsem_wake_type { RWSEM_WAKE_ANY, /* Wake whatever's at head of wait list */ RWSEM_WAKE_READERS, /* Wake readers only */ @@ -228,6 +220,7 @@ __rwsem_down_read_failed_common(struct rw_semaphore *sem, int state) long count, adjustment = -RWSEM_ACTIVE_READ_BIAS; struct rwsem_waiter waiter; DEFINE_WAKE_Q(wake_q); + bool is_first_waiter = false; waiter.task = current; waiter.type = RWSEM_WAITING_FOR_READ; @@ -235,7 +228,9 @@ __rwsem_down_read_failed_common(struct rw_semaphore *sem, int state) raw_spin_lock_irq(&sem->wait_lock); if (list_empty(&sem->wait_list)) adjustment += RWSEM_WAITING_BIAS; - list_add_tail(&waiter.list, &sem->wait_list); + + /* is_first_waiter == true means we are first in the queue */ + is_first_waiter = rwsem_list_add_per_prio(&waiter, sem); /* we're now waiting on the lock, but no longer actively locking */ count = atomic_long_add_return(adjustment, &sem->count); @@ -248,7 +243,8 @@ __rwsem_down_read_failed_common(struct rw_semaphore *sem, int state) */ if (count == RWSEM_WAITING_BIAS || (count > RWSEM_WAITING_BIAS && - adjustment != -RWSEM_ACTIVE_READ_BIAS)) + (adjustment != -RWSEM_ACTIVE_READ_BIAS || + is_first_waiter))) __rwsem_mark_wake(sem, RWSEM_WAKE_ANY, &wake_q); raw_spin_unlock_irq(&sem->wait_lock); @@ -498,6 +494,7 @@ __rwsem_down_write_failed_common(struct rw_semaphore *sem, int state) struct rwsem_waiter waiter; struct rw_semaphore *ret = sem; DEFINE_WAKE_Q(wake_q); + bool is_first_waiter = false; /* undo write bias from down_write operation, stop active locking */ count = atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS, &sem->count); @@ -519,7 +516,11 @@ __rwsem_down_write_failed_common(struct rw_semaphore *sem, int state) if (list_empty(&sem->wait_list)) waiting = false; - list_add_tail(&waiter.list, &sem->wait_list); + /* + * is_first_waiter == true means we are first in the queue, + * so there is no read locks that were queued ahead of us. + */ + is_first_waiter = rwsem_list_add_per_prio(&waiter, sem); /* we're now waiting on the lock, but no longer actively locking */ if (waiting) { @@ -530,7 +531,7 @@ __rwsem_down_write_failed_common(struct rw_semaphore *sem, int state) * no active writers, the lock must be read owned; so we try to * wake any read locks that were queued ahead of us. */ - if (count > RWSEM_WAITING_BIAS) { + if (!is_first_waiter && count > RWSEM_WAITING_BIAS) { __rwsem_mark_wake(sem, RWSEM_WAKE_READERS, &wake_q); /* * The wakeup is normally called _after_ the wait_lock diff --git a/kernel/locking/rwsem.h b/kernel/locking/rwsem.h index 410ee7b9ac2c..df2d6ee84d26 100644 --- a/kernel/locking/rwsem.h +++ b/kernel/locking/rwsem.h @@ -20,6 +20,17 @@ #define RWSEM_ANONYMOUSLY_OWNED (1UL << 0) #define RWSEM_READER_OWNED ((struct task_struct *)RWSEM_ANONYMOUSLY_OWNED) +enum rwsem_waiter_type { + RWSEM_WAITING_FOR_WRITE, + RWSEM_WAITING_FOR_READ +}; + +struct rwsem_waiter { + struct list_head list; + struct task_struct *task; + enum rwsem_waiter_type type; +}; + #ifdef CONFIG_RWSEM_SPIN_ON_OWNER /* * All writes to owner are protected by WRITE_ONCE() to make sure that @@ -79,3 +90,60 @@ static inline void rwsem_set_reader_owned(struct rw_semaphore *sem) { } #endif + +#ifdef CONFIG_RWSEM_PRIO_AWARE + +#define RWSEM_MAX_PREEMPT_ALLOWED 3000 + +/* + * Return true if current waiter is added in the front of the rwsem wait list. + */ +static inline bool rwsem_list_add_per_prio(struct rwsem_waiter *waiter_in, + struct rw_semaphore *sem) +{ + struct list_head *pos; + struct list_head *head; + struct rwsem_waiter *waiter = NULL; + + pos = head = &sem->wait_list; + /* + * Rules for task prio aware rwsem wait list queueing: + * 1: Only try to preempt waiters with which task priority + * which is higher than DEFAULT_PRIO. + * 2: To avoid starvation, add count to record + * how many high priority waiters preempt to queue in wait + * list. + * If preempt count is exceed RWSEM_MAX_PREEMPT_ALLOWED, + * use simple fifo until wait list is empty. + */ + if (list_empty(head)) { + list_add_tail(&waiter_in->list, head); + sem->m_count = 0; + return true; + } + + if (waiter_in->task->prio < DEFAULT_PRIO + && sem->m_count < RWSEM_MAX_PREEMPT_ALLOWED) { + + list_for_each(pos, head) { + waiter = list_entry(pos, struct rwsem_waiter, list); + if (waiter->task->prio > waiter_in->task->prio) { + list_add(&waiter_in->list, pos->prev); + sem->m_count++; + return &waiter_in->list == head->next; + } + } + } + + list_add_tail(&waiter_in->list, head); + + return false; +} +#else +static inline bool rwsem_list_add_per_prio(struct rwsem_waiter *waiter_in, + struct rw_semaphore *sem) +{ + list_add_tail(&waiter_in->list, &sem->wait_list); + return false; +} +#endif -- GitLab From 4724b674d00aeb6523d85e0a668caa570aef0c96 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Wed, 2 Jan 2019 18:57:28 +0530 Subject: [PATCH 0637/1286] ARM: dts: msm: enable smmu on trinket Enable smmu on trinket. Also define test device nodes that is used for smmu testing purpose on trinket. Change-Id: If011b229fe2f701f52bb1f7c8a6695a7b491735f Signed-off-by: Charan Teja Reddy --- .../boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index 68fb28a18835..2437a16178ab 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,7 +14,7 @@ &soc { kgsl_smmu: kgsl-smmu@0x59a0000 { - status = "disabled"; + status = "okay"; compatible = "qcom,qsmmu-v500"; reg = <0x59a0000 0x10000>, <0x59c2000 0x20>; @@ -47,7 +47,7 @@ }; apps_smmu: apps-smmu@0xc600000 { - status = "disabled"; + status = "okay"; compatible = "qcom,qsmmu-v500"; reg = <0xc600000 0x80000>, <0xc782000 0x20>; @@ -157,4 +157,14 @@ qcom,stream-id-range = <0xc00 0x400>; }; }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; }; -- GitLab From fabae43480076dcc46ee4ef68d38c1a58ebffab2 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Tue, 10 Oct 2017 15:21:01 -0700 Subject: [PATCH 0638/1286] arch: arm: Enabled HAVE_FUTEX_CMPXCHG if FUTEX is enabled Enable HAVE_FUTEX_CMPXCHG config if FUTEX is enabled on ARM architectures. Change-Id: Ie6f19454cb868507931c4454708497e6e9c735ea Signed-off-by: Jeevan Shriram --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9737e54bb978..e02925c3cdbb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -66,6 +66,7 @@ config ARM select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) + select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_GCC_PLUGINS select HAVE_GENERIC_DMA_COHERENT select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) -- GitLab From fb8be8cc76c156f5d1862fade2b4d79ac7634004 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 11 Dec 2018 18:55:52 -0800 Subject: [PATCH 0639/1286] net: qrtr: Add support for DEL_PROC control message Add the DEL_PROC control message for forwarding usecases. If this proc acts as a gateway between two procs then they need a notification to clean up servers and client ports when either goes down. This message acts as notification to clean up all resources associated with the node in the message. Change-Id: I3514f54aa0221e104196e2120e929cc9f351847d Signed-off-by: Chris Lew --- include/uapi/linux/qrtr.h | 7 +++++ net/qrtr/qrtr.c | 60 +++++++++++++++++++++++++++++++++++++++ net/qrtr/qrtr.h | 2 ++ 3 files changed, 69 insertions(+) diff --git a/include/uapi/linux/qrtr.h b/include/uapi/linux/qrtr.h index f7e2fb3d752b..ad3b401f1e2e 100644 --- a/include/uapi/linux/qrtr.h +++ b/include/uapi/linux/qrtr.h @@ -27,6 +27,8 @@ enum qrtr_pkt_type { QRTR_TYPE_NEW_LOOKUP = 10, QRTR_TYPE_DEL_LOOKUP = 11, }; +#define QRTR_TYPE_DEL_PROC 13 + struct qrtr_ctrl_pkt { __le32 cmd; @@ -43,6 +45,11 @@ struct qrtr_ctrl_pkt { __le32 node; __le32 port; } client; + + struct { + __le32 rsvd; + __le32 node; + } proc; }; } __packed; diff --git a/net/qrtr/qrtr.c b/net/qrtr/qrtr.c index 221a0aad6787..6ec0c2d525d2 100644 --- a/net/qrtr/qrtr.c +++ b/net/qrtr/qrtr.c @@ -233,6 +233,10 @@ static void qrtr_log_tx_msg(struct qrtr_node *node, struct qrtr_hdr_v1 *hdr, QRTR_INFO(node->ilc, "TX CTRL: cmd:0x%x node[0x%x]\n", hdr->type, hdr->src_node_id); + else if (hdr->type == QRTR_TYPE_DEL_PROC) + QRTR_INFO(node->ilc, + "TX CTRL: cmd:0x%x node[0x%x]\n", + hdr->type, pkt->proc.node); } } @@ -949,6 +953,60 @@ int qrtr_endpoint_register(struct qrtr_endpoint *ep, unsigned int net_id) } EXPORT_SYMBOL_GPL(qrtr_endpoint_register); +static u32 qrtr_calc_checksum(struct qrtr_ctrl_pkt *pkt) +{ + u32 checksum = 0; + u32 mask = 0xffff; + u16 upper_nb; + u16 lower_nb; + u32 *msg; + int i; + + if (!pkt) + return checksum; + msg = (u32 *)pkt; + + for (i = 0; i < sizeof(*pkt) / sizeof(*msg); i++) { + lower_nb = *msg & mask; + upper_nb = (*msg >> 16) & mask; + checksum += (upper_nb + lower_nb); + msg++; + } + while (checksum > 0xffff) + checksum = (checksum & mask) + ((checksum >> 16) & mask); + + checksum = ~checksum & mask; + + return checksum; +} + +static void qrtr_fwd_del_proc(struct qrtr_node *src, unsigned int nid) +{ + struct sockaddr_qrtr from = {AF_QIPCRTR, 0, QRTR_PORT_CTRL}; + struct sockaddr_qrtr to = {AF_QIPCRTR, 0, QRTR_PORT_CTRL}; + struct qrtr_ctrl_pkt *pkt; + struct qrtr_node *dst; + struct sk_buff *skb; + + list_for_each_entry(dst, &qrtr_all_epts, item) { + if (!qrtr_must_forward(nid, dst->nid, QRTR_TYPE_DEL_PROC)) + continue; + + skb = qrtr_alloc_ctrl_packet(&pkt); + if (!skb) + return; + + pkt->cmd = cpu_to_le32(QRTR_TYPE_DEL_PROC); + pkt->proc.rsvd = QRTR_DEL_PROC_MAGIC; + pkt->proc.node = cpu_to_le32(nid); + pkt->proc.rsvd = cpu_to_le32(qrtr_calc_checksum(pkt)); + + from.sq_node = src->nid; + to.sq_node = dst->nid; + qrtr_node_enqueue(dst, skb, QRTR_TYPE_DEL_PROC, &from, &to, 0); + } +} + /** * qrtr_endpoint_unregister - unregister endpoint * @ep: endpoint to unregister @@ -980,6 +1038,8 @@ void qrtr_endpoint_unregister(struct qrtr_endpoint *ep) src.sq_node = iter.index; pkt->cmd = cpu_to_le32(QRTR_TYPE_BYE); qrtr_local_enqueue(NULL, skb, QRTR_TYPE_BYE, &src, &dst, 0); + + qrtr_fwd_del_proc(node, iter.index); } up_read(&qrtr_node_lock); diff --git a/net/qrtr/qrtr.h b/net/qrtr/qrtr.h index 5005b1c5b56d..f9aede45fdc5 100644 --- a/net/qrtr/qrtr.h +++ b/net/qrtr/qrtr.h @@ -10,6 +10,8 @@ struct sk_buff; #define QRTR_EP_NID_AUTO (-1) #define QRTR_EP_NET_ID_AUTO (1) +#define QRTR_DEL_PROC_MAGIC 0xe111 + /** * struct qrtr_endpoint - endpoint handle * @xmit: Callback for outgoing packets -- GitLab From 3610cc1f0a0a024694ed094b09e892dd112d609b Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Fri, 14 Dec 2018 17:58:38 -0800 Subject: [PATCH 0640/1286] ARM: msm: dts: Add qrtr net ids for sm8150-sdxprairie Add forwarding net-ids for qrtr to enable forwarding between subnets. Change-Id: Id1f4c07afc90133c9cc354701e2a002726110de5 Signed-off-by: Chris Lew --- .../boot/dts/qcom/sm8150-sdxprairie.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index e08bfbd1236f..9363e724be4b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -38,6 +38,31 @@ mhi_chan@105 { status = "disabled"; }; + + mhi_devices { + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <3>; + }; + }; +}; + +&glink_adsp { + qcom,adsp_qrtr { + qcom,net-id = <2>; + }; +}; + +&glink_slpi { + qcom,slpi_qrtr { + qcom,net-id = <1>; + }; +}; + +&glink_cdsp { + qcom,cdsp_qrtr { + qcom,net-id = <1>; + }; }; &soc { -- GitLab From a6ab7437df9a46bb90fc37075dd06dd0bee42a45 Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 11:26:47 +0530 Subject: [PATCH 0641/1286] ARM: dts: msm: enable avb system property on trinket Enable avb_version and add "android,vbmeta" for setting system properties for verified boot. Change-Id: I9650d42c7f77391a2abd361c3a0f5ef18def7982 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 9c990ed5f72c..213a985c3e52 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -357,6 +357,10 @@ firmware: firmware { android { compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; fstab { compatible = "android,fstab"; vendor { -- GitLab From 89bf8eea39cf050abfb0e37dc6a15ae31c4a68fb Mon Sep 17 00:00:00 2001 From: Trilok Soni Date: Wed, 27 Jan 2016 18:23:25 -0800 Subject: [PATCH 0642/1286] arm64: errata: Enable #845719 Errataum for Kryo2xx Silver Errata#845719 is also applicable for Kryo2xx Silver. Enable the appropriate entry for it with rAp4 revision. Please note that default midr_range logic depends on the less or greather than logic with "min" and "max" range, assuming that rX where X will be zero only. This is not true for all the processors and since it is 4-bit field it can be greater than the the "max" or pY bits. We are specifying the direct match values like 0xA00004 instead here to keep the logic consistent. Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774 Signed-off-by: Trilok Soni Signed-off-by: Gaurav Kohli --- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 0951e9b03d7c..ad2d0bee68f6 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -130,6 +130,8 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_KRYO2XX_GOLD \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) +#define MIDR_KRYO2XX_SILVER \ + MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e805b8eee266..a0c6e5b988a3 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -432,6 +432,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, + { + /* Kryo2xx Silver rAp4 */ + .desc = "Kryo2xx Silver erratum 845719", + .capability = ARM64_WORKAROUND_845719, + MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), + }, #endif #ifdef CONFIG_CAVIUM_ERRATUM_23154 { -- GitLab From 1514d718bac751476dd3129ec158206f1d73f68f Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Thu, 3 Jan 2019 11:52:39 +0530 Subject: [PATCH 0643/1286] mmc: host: cmdq_hci: Don't dump descriptor table for induced errors Skip dumping ADMA descriptor table memory for induced errors, Dump it only for real ADMA errors. Otherwise, while inducing the errors dumping memory is causing excessive logging and resulting in watchdog bite. Change-Id: I9a18a985986fe4832108cac7dcd15db162749295 Signed-off-by: Veerabhadrarao Badiganti --- drivers/mmc/host/cmdq_hci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/cmdq_hci.c b/drivers/mmc/host/cmdq_hci.c index a9fc2a4e3fb1..2445a3f86a67 100644 --- a/drivers/mmc/host/cmdq_hci.c +++ b/drivers/mmc/host/cmdq_hci.c @@ -1020,10 +1020,10 @@ irqreturn_t cmdq_irq(struct mmc_host *mmc, int err) else mrq->cmd->error = err; /* - * Get ADMA descriptor memory in case of ADMA + * Get ADMA descriptor memory in case of real ADMA * error for debug. */ - if (err == -EIO) + if (err == -EIO && !err_inject) cmdq_dump_adma_mem(cq_host); goto skip_cqterri; } -- GitLab From f53a9171ededa0eb1fc8fe46ecf4adaabee6abbf Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 3 Jan 2019 13:02:48 +0530 Subject: [PATCH 0644/1286] ARM: dts: Add emmc and sdcard node in qrd device for trinket Add emmc and sdcard node in qrd device for trinket. Change-Id: I1c8eee71c48ba7466eede4d2a59fab904fa3950e Signed-off-by: Ram Prakash Gupta --- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 41 ++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 62b87f06b7bd..5d31125390b6 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,7 +10,46 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include &soc { }; + +&sdhc_1 { + vdd-supply = <&pm6125_l24>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6125_l11>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6125_l22>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6125_l5>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + status = "ok"; +}; -- GitLab From a599d2b5213c9d90506d6c52d67062667e5f62b2 Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Wed, 2 Jan 2019 20:55:34 +0530 Subject: [PATCH 0645/1286] msm: ice: check for crypto engine availability There can be many ice instances present in dtsi file but not all of them will be initialized by storage driver. Check if crypto instance is initialized before setting it up for data encryption/decryption usage. Change-Id: I7c9227007474052513b277dec5963a973781c524 Signed-off-by: Neeraj Soni --- drivers/crypto/msm/ice.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/msm/ice.c b/drivers/crypto/msm/ice.c index 4b37f69ef56f..08218503b2fe 100644 --- a/drivers/crypto/msm/ice.c +++ b/drivers/crypto/msm/ice.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1759,7 +1759,7 @@ int qcom_ice_setup_ice_hw(const char *storage_type, int enable) if (ice_dev == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; - if (!ice_dev) + if (!ice_dev || (ice_dev->is_ice_enabled == false)) return ret; if (enable) -- GitLab From 02ce7293f4f6182e806ab37a8f72efe1278f330a Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Thu, 3 Jan 2019 20:58:05 +0530 Subject: [PATCH 0646/1286] defconfig: sm6150: enable default key driver Enables default key driver which is needed for metadata encryption which encrypts the file system metadata. Change-Id: I2bdce274d6130eb299481cb9b37b891ef6987f8c Signed-off-by: Neeraj Soni --- arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index af8f6d7505be..c4ccc398ee27 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -271,6 +271,7 @@ CONFIG_SCSI_UFS_QCOM_ICE=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y +CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 9d8936e4421a..11638e3e3e13 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -282,6 +282,7 @@ CONFIG_SCSI_UFSHCD_CMD_LOGGING=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y +CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y -- GitLab From 549017d90f2c1d2453106a6988de0f6d0c63c0d1 Mon Sep 17 00:00:00 2001 From: Sreelakshmi Gownipalli Date: Wed, 19 Dec 2018 11:07:38 -0800 Subject: [PATCH 0647/1286] diag: Do not close mhi channels on usb disconnect Do not close mhi channels on usb disconnect. Close the channels only when a ssr notification from MHI occurs. This will reduce the over head of closing and opening mhi channels during usb disconnect/connect. Also this will resolve a deadlock issue while switching the logging from memory device mode to usb. Change-Id: If57bc0d4355da1f8e400bab8a312988721157eab Signed-off-by: Sreelakshmi Gownipalli --- drivers/char/diag/diagfwd_bridge.c | 15 +-------------- drivers/char/diag/diagfwd_mhi.c | 4 +++- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/char/diag/diagfwd_bridge.c b/drivers/char/diag/diagfwd_bridge.c index cd7c084e5117..fe418454465c 100644 --- a/drivers/char/diag/diagfwd_bridge.c +++ b/drivers/char/diag/diagfwd_bridge.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -92,19 +92,6 @@ static int diagfwd_bridge_mux_disconnect(int id, int mode) if (id < 0 || id >= NUM_REMOTE_DEV) return -EINVAL; - if ((mode == DIAG_USB_MODE && - driver->logging_mode == DIAG_MEMORY_DEVICE_MODE) || - (mode == DIAG_MEMORY_DEVICE_MODE && - driver->logging_mode == DIAG_USB_MODE)) { - /* - * Don't close the MHI channels when usb is disconnected - * and a process is running in memory device mode. - */ - return 0; - } - - if (bridge_info[id].dev_ops && bridge_info[id].dev_ops->close) - bridge_info[id].dev_ops->close(bridge_info[id].ctxt); return 0; } diff --git a/drivers/char/diag/diagfwd_mhi.c b/drivers/char/diag/diagfwd_mhi.c index 1ce9d81a3339..2da564ba846c 100644 --- a/drivers/char/diag/diagfwd_mhi.c +++ b/drivers/char/diag/diagfwd_mhi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -223,6 +223,8 @@ static int __mhi_close(struct diag_mhi_info *mhi_info, int close_flag) atomic_set(&(mhi_info->read_ch.opened), 0); atomic_set(&(mhi_info->write_ch.opened), 0); + cancel_work(&mhi_info->read_work); + cancel_work(&mhi_info->read_done_work); flush_workqueue(mhi_info->mhi_wq); if (close_flag == CLOSE_CHANNELS) { -- GitLab From 4f33b131634c8fa3d465fcd61e4ebaafcc09a111 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Wed, 2 Jan 2019 11:23:18 -0800 Subject: [PATCH 0648/1286] ARM: dts: msm: Add watchdog devicetree entries for SDXPRAIRIE target Add required watchdog device tree node for enabling watchdog timer to reset the device in case of fault. Change-Id: I5501ab04ddd1e9b0933ca46f11e54ce06cb84069 Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 7f86abc666fd..cf4fd4d34333 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -226,6 +226,16 @@ qcom,force-warm-reboot; }; + qcom,wdt@17817000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <1 3 0>, <1 2 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,wakeup-enable; + }; + keepalive_opp_table: keepalive-opp-table { compatible = "operating-points-v2"; opp-1 { -- GitLab From 3ed44035e4179521228154f0dd7ebb7635ad3bee Mon Sep 17 00:00:00 2001 From: Junzhe Zou Date: Thu, 13 Dec 2018 17:39:49 -0800 Subject: [PATCH 0649/1286] msm: camera: fd: put back the frame resource properly Put the frame request back properly during flush to avoid resource leak. Change-Id: I3f7bcc17d866f5d9416549eed12e8dbadce3b403 Signed-off-by: Junzhe Zou --- .../msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index a28c99ae5147..645249cb58a9 100644 --- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -162,8 +162,10 @@ static int cam_fd_mgr_util_put_frame_req( mutex_lock(&g_fd_hw_mgr.frame_req_mutex); req_ptr = *frame_req; - if (req_ptr) + if (req_ptr) { + list_del_init(&req_ptr->list); list_add_tail(&req_ptr->list, src_list); + } *frame_req = NULL; mutex_unlock(&g_fd_hw_mgr.frame_req_mutex); @@ -1465,6 +1467,16 @@ static int cam_fd_mgr_hw_flush_ctx(void *hw_mgr_priv, for (i = 0; i < flush_args->num_req_pending; i++) { flush_req = (struct cam_fd_mgr_frame_request *) flush_args->flush_req_pending[i]; + CAM_DBG(CAM_FD, "flush pending req %llu", + flush_req->request_id); + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &flush_req); + } + + for (i = 0; i < flush_args->num_req_active; i++) { + flush_req = (struct cam_fd_mgr_frame_request *) + flush_args->flush_req_active[i]; + CAM_DBG(CAM_FD, "flush active req %llu", flush_req->request_id); cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, &flush_req); } -- GitLab From 904f25efa14f5540d505e0098788117752e5c921 Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Thu, 3 Jan 2019 14:41:28 -0700 Subject: [PATCH 0650/1286] soc: qmi: dfc: reduce response waiting timeout The 10s response waiting timeout is too long and sometimes blocks the notification in the case of dropped or ignored request. Reducing to 1000ms which is more inline with transaction latency. Timeout value is converted to jiffies per API usage. Change-Id: I74e63b02b7418c271740854a9e158f6562280ee4 Acked-by: Ning Cai Signed-off-by: Sean Tranchetti --- drivers/soc/qcom/dfc_qmi.c | 10 +++++----- drivers/soc/qcom/wda_qmi.c | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/dfc_qmi.c b/drivers/soc/qcom/dfc_qmi.c index 7cfd0cee57f5..acb5ac44e6ef 100644 --- a/drivers/soc/qcom/dfc_qmi.c +++ b/drivers/soc/qcom/dfc_qmi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -70,7 +70,7 @@ static void dfc_svc_init(struct work_struct *work); /* **************************************************** */ #define DFC_SERVICE_ID_V01 0x4E #define DFC_SERVICE_VERS_V01 0x01 -#define DFC_TIMEOUT_MS 10000 +#define DFC_TIMEOUT_JF msecs_to_jiffies(1000) #define QMI_DFC_BIND_CLIENT_REQ_V01 0x0020 #define QMI_DFC_BIND_CLIENT_RESP_V01 0x0020 @@ -659,7 +659,7 @@ dfc_bind_client_req(struct qmi_handle *dfc_handle, goto out; } - ret = qmi_txn_wait(&txn, DFC_TIMEOUT_MS); + ret = qmi_txn_wait(&txn, DFC_TIMEOUT_JF); if (ret < 0) { pr_err("%s() Response waiting failed, err: %d\n", __func__, ret); @@ -715,7 +715,7 @@ dfc_indication_register_req(struct qmi_handle *dfc_handle, goto out; } - ret = qmi_txn_wait(&txn, DFC_TIMEOUT_MS); + ret = qmi_txn_wait(&txn, DFC_TIMEOUT_JF); if (ret < 0) { pr_err("%s() Response waiting failed, err: %d\n", __func__, ret); @@ -769,7 +769,7 @@ dfc_get_flow_status_req(struct qmi_handle *dfc_handle, goto out; } - ret = qmi_txn_wait(txn, DFC_TIMEOUT_MS); + ret = qmi_txn_wait(txn, DFC_TIMEOUT_JF); if (ret < 0) { pr_err("%s() Response waiting failed, err: %d\n", __func__, ret); diff --git a/drivers/soc/qcom/wda_qmi.c b/drivers/soc/qcom/wda_qmi.c index 1386757d4bfd..7d240f85b712 100644 --- a/drivers/soc/qcom/wda_qmi.c +++ b/drivers/soc/qcom/wda_qmi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,7 +31,7 @@ static void wda_svc_config(struct work_struct *work); /* **************************************************** */ #define WDA_SERVICE_ID_V01 0x1A #define WDA_SERVICE_VERS_V01 0x01 -#define WDA_TIMEOUT_MS 20 +#define WDA_TIMEOUT_JF msecs_to_jiffies(1000) #define QMI_WDA_SET_POWERSAVE_CONFIG_REQ_V01 0x002D #define QMI_WDA_SET_POWERSAVE_CONFIG_RESP_V01 0x002D @@ -241,7 +241,7 @@ static int wda_set_powersave_mode_req(void *wda_data, uint8_t enable) goto out; } - ret = qmi_txn_wait(&txn, WDA_TIMEOUT_MS); + ret = qmi_txn_wait(&txn, WDA_TIMEOUT_JF); if (ret < 0) { pr_err("%s() Response waiting failed, err: %d\n", __func__, ret); @@ -298,7 +298,7 @@ static int wda_set_powersave_config_req(struct qmi_handle *wda_handle) goto out; } - ret = qmi_txn_wait(&txn, WDA_TIMEOUT_MS); + ret = qmi_txn_wait(&txn, WDA_TIMEOUT_JF); if (ret < 0) { pr_err("%s() Response waiting failed, err: %d\n", __func__, ret); -- GitLab From e2a5ff731542b57993e107af71b167c807d20f97 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Thu, 3 Jan 2019 19:18:22 +0800 Subject: [PATCH 0651/1286] defconfig: msm: Disable ETM4x on perf build for SDMSTEPPE ETM should not be enabled on secondary boot due to power/performance impact. Change-Id: I0f31ad5644ccf7964a168293bb2c9807e3bb6b79 Signed-off-by: Mao Jinlong --- arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index af8f6d7505be..9febc95b4135 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -657,7 +657,6 @@ CONFIG_IPC_LOGGING=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y CONFIG_CORESIGHT_STM=y CONFIG_CORESIGHT_CTI=y -- GitLab From efc94e7d406b593160925412b929cefa891c3060 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 2 Jan 2019 11:34:00 +0530 Subject: [PATCH 0652/1286] configfs: Fix use-after-free when accessing sd->s_dentry In the vfs_statx() context, during path lookup, the dentry gets added to sd->s_dentry via configfs_attach_attr(). In the end, vfs_statx() kills the dentry by calling path_put(), which invokes configfs_d_iput(). Ideally, this dentry must be removed from sd->s_dentry but it doesn't if the sd->s_count >= 3. As a result, sd->s_dentry is holding reference to a stale dentry pointer whose memory is already freed up. This results in use-after-free issue, when this stale sd->s_dentry is accessed later in configfs_readdir() path. This issue can be easily reproduced, by running the LTP test case - sh fs_racer_file_list.sh /config Change-Id: I5ac8556837bbdf2e5d0540516efb106ec53d7536 Fixes: 76ae281f6307 ('configfs: fix race between dentry put and lookup') Signed-off-by: Sahitya Tummala --- fs/configfs/dir.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/fs/configfs/dir.c b/fs/configfs/dir.c index d2a1a79fa324..b6dbf115f914 100644 --- a/fs/configfs/dir.c +++ b/fs/configfs/dir.c @@ -58,15 +58,14 @@ static void configfs_d_iput(struct dentry * dentry, if (sd) { /* Coordinate with configfs_readdir */ spin_lock(&configfs_dirent_lock); - /* Coordinate with configfs_attach_attr where will increase - * sd->s_count and update sd->s_dentry to new allocated one. - * Only set sd->dentry to null when this dentry is the only - * sd owner. + /* + * Set sd->s_dentry to null only when this dentry is the + * one that is going to be killed. * If not do so, configfs_d_iput may run just after * configfs_attach_attr and set sd->s_dentry to null * even it's still in use. */ - if (atomic_read(&sd->s_count) <= 2) + if (sd->s_dentry == dentry) sd->s_dentry = NULL; spin_unlock(&configfs_dirent_lock); -- GitLab From 22f98c63a29f0477a2a787eff253697a62c8f6b8 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Thu, 3 Jan 2019 15:11:54 +0530 Subject: [PATCH 0653/1286] ARM: dts: msm: Remove extcon property for Trinket Remove extcon property from Trinket base dtsi file and update in the corresponding IDP file. Change-Id: I85e4935c99021316f1f0c46631ac331dc366fea6 Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/trinket-rumi.dtsi | 3 +-- arch/arm64/boot/dts/qcom/trinket.dtsi | 4 ---- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index c6d805dbea05..19b87993a108 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -71,3 +71,7 @@ qcom,sec-charger-config = <2>; dpdm-supply = <&qusb_phy0>; }; + +&usb0 { + extcon = <&pmi632_charger>; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi index 49be16db5cb9..52faa1915dab 100644 --- a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -50,7 +50,6 @@ }; &usb0 { - extcon = <0>; dwc3@4e00000 { usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; maximum-speed = "high-speed"; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..0e5e4477df1a 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1888,8 +1888,4 @@ &venus_gdsc { status = "ok"; }; - -&usb0 { - extcon = <&pmi632_charger>; -}; #include "trinket-thermal.dtsi" -- GitLab From 0f8d18c1481f81c09a0781fa39e5e5f858ead362 Mon Sep 17 00:00:00 2001 From: Manikanta Kanamarlapudi Date: Mon, 24 Dec 2018 20:34:56 +0530 Subject: [PATCH 0654/1286] msm: vidc: Add support for dynamic UBWC configuration Each video device will have a different UBWC capabilities, Hence read the supported capability from device platform data and set it to firmware using hfi. CRs-Fixed: 2360061 Change-Id: Ia2ba5ba1b2e686d5a2a5fe01c5d678a47545535d Signed-off-by: Manikanta Kanamarlapudi --- .../platform/msm/vidc/hfi_packetization.c | 29 +++++++++++++++- .../platform/msm/vidc/hfi_packetization.h | 4 ++- .../platform/msm/vidc/msm_vidc_internal.h | 4 ++- .../platform/msm/vidc/msm_vidc_platform.c | 31 +++++++++++++++++ .../platform/msm/vidc/msm_vidc_res_parse.c | 6 +++- .../platform/msm/vidc/msm_vidc_resources.h | 28 +++++++++++++++- drivers/media/platform/msm/vidc/venus_hfi.c | 33 +++++++++++++++++-- .../media/platform/msm/vidc/vidc_hfi_helper.h | 4 ++- 8 files changed, 131 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.c b/drivers/media/platform/msm/vidc/hfi_packetization.c index a5bbcd0102d9..f5db6dcecb81 100644 --- a/drivers/media/platform/msm/vidc/hfi_packetization.c +++ b/drivers/media/platform/msm/vidc/hfi_packetization.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2102,6 +2102,32 @@ int create_pkt_cmd_sys_image_version( return 0; } +int create_pkt_cmd_sys_ubwc_config(struct hfi_cmd_sys_set_property_packet *pkt, + struct msm_vidc_ubwc_config *config) +{ + struct msm_vidc_ubwc_config *hfi; + + if (!pkt) { + dprintk(VIDC_ERR, "%s invalid param :%pK\n", __func__, pkt); + return -EINVAL; + } + + pkt->size = sizeof(struct hfi_cmd_sys_set_property_packet) + + sizeof(struct msm_vidc_ubwc_config) + sizeof(u32); + pkt->packet_type = HFI_CMD_SYS_SET_PROPERTY; + pkt->num_properties = 1; + pkt->rg_property_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG; + hfi = (struct msm_vidc_ubwc_config *) &pkt->rg_property_data[1]; + hfi->sOverrideBitInfo.bMalLengthOverride = + config->sOverrideBitInfo.bMalLengthOverride; + hfi->nMalLength = config->nMalLength; + dprintk(VIDC_DBG, + "UBWC settings Mal Length Override : %u MalLength: %u", + hfi->sOverrideBitInfo.bMalLengthOverride, + hfi->nMalLength); + return 0; +} + int create_pkt_cmd_session_sync_process( struct hfi_cmd_session_sync_process_packet *pkt, struct hal_session *session) @@ -2129,6 +2155,7 @@ static struct hfi_packetization_ops hfi_default = { .sys_ping = create_pkt_cmd_sys_ping, .sys_image_version = create_pkt_cmd_sys_image_version, .ssr_cmd = create_pkt_ssr_cmd, + .sys_ubwc_config = create_pkt_cmd_sys_ubwc_config, .session_init = create_pkt_cmd_sys_session_init, .session_cmd = create_pkt_cmd_session_cmd, .session_set_buffers = create_pkt_cmd_session_set_buffers, diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.h b/drivers/media/platform/msm/vidc/hfi_packetization.h index 9bc3b27e5133..5479a7f1da43 100644 --- a/drivers/media/platform/msm/vidc/hfi_packetization.h +++ b/drivers/media/platform/msm/vidc/hfi_packetization.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -46,6 +46,8 @@ struct hfi_packetization_ops { int (*sys_image_version)(struct hfi_cmd_sys_get_property_packet *pkt); int (*ssr_cmd)(enum hal_ssr_trigger_type type, struct hfi_cmd_sys_test_ssr_packet *pkt); + int (*sys_ubwc_config)(struct hfi_cmd_sys_set_property_packet *pkt, + struct msm_vidc_ubwc_config *config); int (*session_init)( struct hfi_cmd_sys_session_init_packet *pkt, struct hal_session *session, diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h index 4705a2701723..c2fd6ae0176b 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h +++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -241,6 +241,8 @@ struct msm_vidc_platform_data { struct msm_vidc_csc_coeff csc_data; struct msm_vidc_efuse_data *efuse_data; unsigned int efuse_data_length; + struct msm_vidc_ubwc_config *ubwc_config; + unsigned int ubwc_config_length; unsigned int sku_version; phys_addr_t gcc_register_base; uint32_t gcc_register_size; diff --git a/drivers/media/platform/msm/vidc/msm_vidc_platform.c b/drivers/media/platform/msm/vidc/msm_vidc_platform.c index 9db4a4547603..3fa98f33e702 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_platform.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_platform.c @@ -36,6 +36,19 @@ .low_power_cycles = lp \ } +#define UBWC_CONFIG(mco, mlo, hbbo, rs1, mc, ml, hbb, rs2) \ +{ \ + .sOverrideBitInfo.bMaxChannelsOverride = mc, \ + .sOverrideBitInfo.bMalLengthOverride = mlo, \ + .sOverrideBitInfo.bHBBOverride = hbbo, \ + .sOverrideBitInfo.reserved1 = rs1, \ + .nMaxChannels = mc, \ + .nMalLength = ml, \ + .nHighestBankBit = hbb, \ + .reserved2 = {rs2} \ +} + + #define EFUSE_ENTRY(sa, s, m, sh, p) \ { \ .start_address = sa, \ @@ -688,11 +701,17 @@ static struct msm_vidc_efuse_data sdmmagpie_efuse_data[] = { EFUSE_ENTRY(0x00786018, 4, 0x00000400, 0x0a, SKU_VERSION), }; +static struct msm_vidc_ubwc_config trinket_ubwc_data[] = { + UBWC_CONFIG(0, 1, 0, 0, 0, 64, 0, 0), +}; + static struct msm_vidc_platform_data default_data = { .codec_data = default_codec_data, .codec_data_length = ARRAY_SIZE(default_codec_data), .common_data = default_common_data, .common_data_length = ARRAY_SIZE(default_common_data), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -709,6 +728,8 @@ static struct msm_vidc_platform_data sm6150_data = { .codec_data_length = ARRAY_SIZE(sm6150_codec_data), .common_data = sm6150_common_data, .common_data_length = ARRAY_SIZE(sm6150_common_data), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -725,6 +746,8 @@ static struct msm_vidc_platform_data trinket_data = { .codec_data_length = ARRAY_SIZE(trinket_codec_data), .common_data = trinket_common_data, .common_data_length = ARRAY_SIZE(trinket_common_data), + .ubwc_config = trinket_ubwc_data, + .ubwc_config_length = ARRAY_SIZE(trinket_ubwc_data), .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -741,6 +764,8 @@ static struct msm_vidc_platform_data sm8150_data = { .codec_data_length = ARRAY_SIZE(sm8150_codec_data), .common_data = sm8150_common_data, .common_data_length = ARRAY_SIZE(sm8150_common_data), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -757,6 +782,8 @@ static struct msm_vidc_platform_data sdmmagpie_data = { .codec_data_length = ARRAY_SIZE(sdmmagpie_codec_data), .common_data = sdmmagpie_common_data_v0, .common_data_length = ARRAY_SIZE(sdmmagpie_common_data_v0), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -773,6 +800,8 @@ static struct msm_vidc_platform_data sdm845_data = { .codec_data_length = ARRAY_SIZE(sdm845_codec_data), .common_data = sdm845_common_data, .common_data_length = ARRAY_SIZE(sdm845_common_data), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, @@ -789,6 +818,8 @@ static struct msm_vidc_platform_data sdm670_data = { .codec_data_length = ARRAY_SIZE(sdm670_codec_data), .common_data = sdm670_common_data_v0, .common_data_length = ARRAY_SIZE(sdm670_common_data_v0), + .ubwc_config = 0, + .ubwc_config_length = 0, .csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff, .csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff, .csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff, diff --git a/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c b/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c index d16239d5dad0..4e00cfc535f9 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -810,6 +810,10 @@ int read_platform_resources_from_drv_data( res->gcc_register_size = platform_data->gcc_register_size; res->vpu_ver = platform_data->vpu_ver; + + res->ubwc_config = platform_data->ubwc_config; + res->ubwc_config_length = platform_data->ubwc_config_length; + return rc; } diff --git a/drivers/media/platform/msm/vidc/msm_vidc_resources.h b/drivers/media/platform/msm/vidc/msm_vidc_resources.h index e2e2b000a102..f2049d5a2b6b 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_resources.h +++ b/drivers/media/platform/msm/vidc/msm_vidc_resources.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -204,6 +204,32 @@ struct msm_vidc_platform_resources { uint32_t fw_vpp_cycles; uint32_t clk_freq_threshold; struct cx_ipeak_client *cx_ipeak_context; + struct msm_vidc_ubwc_config *ubwc_config; + uint32_t ubwc_config_length; +}; + +/** + * @bMaxChannelsOverride : enable - 1 /disable - 0 max channel override + * @bMalLengthOverride : enable - 1 /disable - 0 HBB override + * @bHBBOverride : enable - 1 /disable – 0 mal length override + * @nMaxChannels: Num DDR channels 4/8 channel, + * This is to control mircotilling mode. + * @nMalLength : UBWC compression ratio granularity 32B/64B MAL + * @nHighestBankBit : Valid range 13-19 + */ + +struct msm_vidc_ubwc_config { + struct { + u32 bMaxChannelsOverride : 1; + u32 bMalLengthOverride : 1; + u32 bHBBOverride : 1; + u32 reserved1 : 29; + } sOverrideBitInfo; + + u32 nMaxChannels; + u32 nMalLength; + u32 nHighestBankBit; + u32 reserved2[2]; }; static inline bool is_iommu_present(struct msm_vidc_platform_resources *res) diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c index 314e684d3ed2..852b63645c36 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.c +++ b/drivers/media/platform/msm/vidc/venus_hfi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2094,6 +2094,30 @@ static int __sys_set_debug(struct venus_hfi_device *device, u32 debug) return 0; } +static int __sys_set_ubwc_config(void *device) +{ + int rc = 0; + struct venus_hfi_device *dev = device; + u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE] = {0}; + struct hfi_cmd_sys_set_property_packet *pkt = + (struct hfi_cmd_sys_set_property_packet *) &packet; + + if (!dev->res->ubwc_config) + return rc; + + rc = call_hfi_pkt_op(dev, sys_ubwc_config, pkt, dev->res->ubwc_config); + if (rc) { + dprintk(VIDC_WARN, + "UBWC Config setting to FW failed\n"); + return -ENOTEMPTY; + } + + if (__iface_cmdq_write(dev, pkt)) + return -ENOTEMPTY; + + return 0; +} + static int __sys_set_coverage(struct venus_hfi_device *device, u32 mode) { u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE]; @@ -2215,6 +2239,12 @@ static int venus_hfi_core_init(void *device) __sys_set_debug(device, msm_vidc_fw_debug); + rc = __sys_set_ubwc_config(device); + if (rc) { + dprintk(VIDC_ERR, "Failed to set ubwc config\n"); + goto err_core_init; + } + __enable_subcaches(device); __set_subcaches(device); __dsp_send_hfi_queue(device); @@ -3694,7 +3724,6 @@ static void venus_hfi_core_work_handler(struct work_struct *work) mutex_lock(&device->lock); - if (!__core_in_valid_state(device)) { dprintk(VIDC_DBG, "%s - Core not in init state\n", __func__); goto err_no_work; diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h index 3e8d8b4e1d99..798ea7ad58e1 100644 --- a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h +++ b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -204,6 +204,8 @@ struct hfi_buffer_info { (HFI_PROPERTY_SYS_COMMON_START + 0x006) #define HFI_PROPERTY_SYS_CONFIG_COVERAGE \ (HFI_PROPERTY_SYS_COMMON_START + 0x007) +#define HFI_PROPERTY_SYS_UBWC_CONFIG \ + (HFI_PROPERTY_SYS_COMMON_START + 0x008) #define HFI_PROPERTY_PARAM_COMMON_START \ (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000) -- GitLab From 6c706eeac7bc75b28d4c0346888b71f4dee61707 Mon Sep 17 00:00:00 2001 From: E V Ravi Date: Fri, 21 Dec 2018 19:53:10 +0530 Subject: [PATCH 0655/1286] defconfig: msm: sa6155: Adding AIS Kernel driver Adding Automotive Imaging driver for sa6155. Change-Id: Ifff252f5ccd9de43f22f7c9a2d9c97a08c2493f2 Signed-off-by: E V Ravi --- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 2 +- arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index 36ec1d58e372..c6ab2f95c01c 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -393,7 +393,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SPECTRA_CAMERA=y +CONFIG_MSM_AIS=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index 1be3971a1cd5..c420758e5ae7 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -407,7 +407,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SPECTRA_CAMERA=y +CONFIG_MSM_AIS=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y -- GitLab From 4a2ccaa7fc4dd89cf2ebef89ce956e57f63660dc Mon Sep 17 00:00:00 2001 From: Sreelakshmi Gownipalli Date: Fri, 4 Jan 2019 11:14:16 +0530 Subject: [PATCH 0656/1286] diag: Increase the MHI buffer size to 4k Increase the buffer size to 4k for the buffers submitted to MHI layer. Change-Id: Iec8f582a986f69ef078174a57ed4d062ac6ccfbb Signed-off-by: Sreelakshmi Gownipalli Signed-off-by: Manoj Prabhu B --- drivers/char/diag/diagchar.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h index f1e59bfd4875..d48d34632558 100644 --- a/drivers/char/diag/diagchar.h +++ b/drivers/char/diag/diagchar.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -261,9 +261,19 @@ do { \ #define DIAG_TS_SIZE 50 +#ifdef CONFIG_MHI_BUS +#define DIAG_MDM_BUF_SIZE 4096 +#else #define DIAG_MDM_BUF_SIZE 2048 +#endif + +/* The Maximum request size is 4k + DCI header + footer (6 bytes) */ +#ifdef CONFIG_MHI_BUS +#define DIAG_MDM_DCI_BUF_SIZE (4096 + 6) +#else /* The Maximum request size is 2k + DCI header + footer (6 bytes) */ #define DIAG_MDM_DCI_BUF_SIZE (2048 + 6) +#endif #define DIAG_LOCAL_PROC 0 -- GitLab From eef4b381bab28dfe911c6dbc467ae7f656482077 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 3 Jan 2019 15:09:43 +0800 Subject: [PATCH 0657/1286] ARM: dts: msm: Correct GPIO address size for PM6125 PM6125 has 9 GPIO modules so correct the address size to 0x900. Change-Id: I033fa195b8e3e52b336a189f835e30924d1654c4 Signed-off-by: Fenglin Wu --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index ecabcb3a15d9..c329012df1f3 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -141,7 +141,7 @@ pm6125_gpios: pinctrl@c000 { compatible = "qcom,spmi-gpio"; - reg = <0xc000 0xa00>; + reg = <0xc000 0x900>; interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, <0x0 0xc1 0 IRQ_TYPE_NONE>, <0x0 0xc2 0 IRQ_TYPE_NONE>, -- GitLab From b474470c1069a774395af634e7d06739fd52908a Mon Sep 17 00:00:00 2001 From: Aggarwal Shubham Date: Mon, 24 Dec 2018 13:00:36 +0530 Subject: [PATCH 0658/1286] defconfig: qcs405: Cleanup for memory improvement This is for optimizing ram usage for qcs403. Removing unused configs based on discussion with various tech teams. Change-Id: I030d1d923d6ba0fe3c3ba54188dabcd18b65fac6 Signed-off-by: Aggarwal Shubham --- arch/arm/configs/vendor/qcs405-perf_defconfig | 139 +++--------------- 1 file changed, 23 insertions(+), 116 deletions(-) diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 3fac1d1d4389..efc1584abe05 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -15,17 +15,16 @@ CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_CPUACCT=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_DEFAULT_USE_ENERGY_AWARE=y CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_STRONG=y CONFIG_MODULES=y @@ -42,7 +41,6 @@ CONFIG_ARCH_QCS405=y CONFIG_SMP=y CONFIG_ARM_PSCI=y CONFIG_PREEMPT=y -CONFIG_HIGHMEM=y CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_SECCOMP=y @@ -64,7 +62,6 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=y CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y @@ -72,18 +69,9 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y # CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_NETFILTER=y @@ -96,51 +84,33 @@ CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y CONFIG_NETFILTER_XT_MATCH_U32=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y @@ -155,25 +125,19 @@ CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_NF_DUP_IPV6=y CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_L2TP=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_PRIO=y CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y @@ -194,7 +158,6 @@ CONFIG_RFKILL=y CONFIG_NTAG_NQ=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y @@ -204,65 +167,37 @@ CONFIG_MTD_NAND=y CONFIG_MTD_UBI=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_QSEECOM=y CONFIG_UID_SYS_STATS=y CONFIG_QPNP_MISC=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y -CONFIG_TUN=y +CONFIG_PHYLIB=y CONFIG_AT803X_PHY=y CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC75XX=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y +CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_HS=y CONFIG_HW_RANDOM=y CONFIG_DIAG_CHAR=y CONFIG_MSM_ADSPRPC=y +CONFIG_I2C=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y CONFIG_I2C_MSM_V2=y CONFIG_SPI=y CONFIG_SPI_QUP=y @@ -285,12 +220,10 @@ CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y -CONFIG_QCOM_SPMI_TEMP_ALARM=y CONFIG_THERMAL_TSENS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_QMI_COOLING_DEVICE=y CONFIG_REGULATOR_COOLING_DEVICE=y -CONFIG_QTI_ADC_TM=y CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y @@ -302,52 +235,22 @@ CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_STUB=y CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y -CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=y CONFIG_HIDRAW=y -CONFIG_UHID=y -CONFIG_USB_HIDDEV=y +# CONFIG_USB_HID is not set +CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_KARMA=y -CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y -CONFIG_USB_QCOM_EMU_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VBUS_DRAW=900 CONFIG_USB_CONFIGFS=y @@ -373,6 +276,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y CONFIG_QCOM_SPS_DMA=y +CONFIG_SYNC_FILE=y CONFIG_UIO=y CONFIG_STAGING=y CONFIG_ASHMEM=y @@ -380,7 +284,6 @@ CONFIG_ION=y CONFIG_QPNP_REVID=y CONFIG_SPS=y CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y @@ -392,7 +295,6 @@ CONFIG_MAILBOX=y CONFIG_QCOM_APCS_IPC=y CONFIG_ARM_SMMU=y CONFIG_QCOM_LAZY_MAPPING=y -CONFIG_QCOM_IOMMU=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y @@ -425,24 +327,21 @@ CONFIG_QCOM_GLINK_PKT=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_QCOM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y CONFIG_EXTCON_USB_GPIO=y -CONFIG_IIO=y -CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y CONFIG_PWM_QTI_LPG=y CONFIG_QTI_MPM=y +CONFIG_PHY_QCOM_UFS=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y +CONFIG_DAX=y CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set @@ -453,26 +352,34 @@ CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y +# CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y CONFIG_PANIC_ON_RECURSIVE_FAULT=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=5 CONFIG_IPC_LOGGING=y CONFIG_QCOM_RTB=y CONFIG_QCOM_RTB_SEPARATE_CPUS=y +# CONFIG_FTRACE is not set CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y CONFIG_LSM_MMAP_MIN_ADDR=4096 CONFIG_HARDENED_USERCOPY=y CONFIG_SECURITY_SELINUX=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_XCBC=y CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_TWOFISH=y -CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_XZ_DEC=y -- GitLab From 811f8d6fa04e452deed4418dcf792cf24e222b02 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Mon, 24 Dec 2018 16:56:17 +0530 Subject: [PATCH 0659/1286] ARM: dts: msm: Add LPM node for trinket Add LPM node and SPM node for trinket. Change-Id: I748fc958756268de0cd40bf63fa8dbbfe572ca88 Signed-off-by: Raghavendra Kakarla --- arch/arm64/boot/dts/qcom/trinket-pm.dtsi | 224 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 2 files changed, 225 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-pm.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-pm.dtsi b/arch/arm64/boot/dts/qcom/trinket-pm.dtsi new file mode 100644 index 000000000000..773216ac082c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-pm.dtsi @@ -0,0 +1,224 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,spm@f1d2000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf1d2000 0x1000>; + reg-names = "saw-base"; + qcom,name = "system-cci"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0xe>; + qcom,saw2-avs-ctl = <0x10>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3 + &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <1654>; + qcom,min-residency-us = <2294>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,entry-latency-us = <10831>; + qcom,exit-latency-us = <4506>; + qcom,min-residency-us = <15338>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,is-reset; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <51>; + qcom,min-residency-us = <89>; + }; + + qcom,pm-cluster-level@1{ /* D3G */ + reg = <1>; + label = "pwr-l2-gdhs"; + qcom,psci-mode = <0x2>; + qcom,entry-latency-us = <360>; + qcom,exit-latency-us = <421>; + qcom,min-residency-us = <782>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D3 */ + reg = <2>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <800>; + qcom,exit-latency-us = <2118>; + qcom,min-residency-us = <7376>; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <49>; + qcom,exit-latency-us = <42>; + qcom,min-residency-us = <91>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <290>; + qcom,exit-latency-us = <376>; + qcom,min-residency-us = <1182>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <51>; + qcom,min-residency-us = <89>; + }; + + qcom,pm-cluster-level@1{ /* D3G*/ + reg = <1>; + label = "perf-l2-gdhs"; + qcom,psci-mode = <2>; + qcom,entry-latency-us = <314>; + qcom,exit-latency-us = <345>; + qcom,min-residency-us = <660>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D3 */ + reg = <2>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <1654>; + qcom,min-residency-us = <8094>; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <29>; + qcom,exit-latency-us = <39>; + qcom,min-residency-us = <68>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <297>; + qcom,exit-latency-us = <324>; + qcom,min-residency-us = <1110>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-master-stats@45f0150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x45f0150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..2bb941134b0f 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1697,6 +1697,7 @@ #include "trinket-qupv3.dtsi" #include "trinket-coresight.dtsi" #include "trinket-vidc.dtsi" +#include "trinket-pm.dtsi" &pm6125_vadc { rf_pa0_therm { -- GitLab From 7e2a13add84c29f4aa2b6b7b175658919ff1c3ed Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Fri, 26 Oct 2018 17:22:04 +0530 Subject: [PATCH 0660/1286] drivers: irqchip: qcom: Add mpm pin data for trinket Add mpm pin data for gic and gpio interrupts for trinket. Change-Id: I09cf150ace488a669ee25f67a1faf1be0102749f Signed-off-by: Raghavendra Kakarla --- .../bindings/interrupt-controller/qti,mpm.txt | 2 + drivers/irqchip/qcom/Makefile | 3 +- drivers/irqchip/qcom/mpm-trinket.c | 90 +++++++++++++++++++ drivers/irqchip/qcom/mpm.c | 10 ++- drivers/irqchip/qcom/mpm.h | 4 +- 5 files changed, 105 insertions(+), 4 deletions(-) create mode 100644 drivers/irqchip/qcom/mpm-trinket.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/qti,mpm.txt b/Documentation/devicetree/bindings/interrupt-controller/qti,mpm.txt index 969bf6531e31..551c8b8b7aa4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qti,mpm.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qti,mpm.txt @@ -22,6 +22,7 @@ Properties: "qcom,mpm-gic-msm8953", "qcom,mpm-gic-msm8937", "qcom,mpm-gic-qcs405" + "qcom,mpm-gic-trinket" - interrupts: Usage: required @@ -79,6 +80,7 @@ properties: "qcom,mpm-gpio-msm8953", "qcom,mpm-gpio-msm8937", "qcom,mpm-gpio-qcs405" + "qcom,mpm-gpio-trinket", - interrupt-parent: Usage: required diff --git a/drivers/irqchip/qcom/Makefile b/drivers/irqchip/qcom/Makefile index 13455731eae6..9b3056769633 100644 --- a/drivers/irqchip/qcom/Makefile +++ b/drivers/irqchip/qcom/Makefile @@ -3,5 +3,4 @@ obj-$(CONFIG_QTI_PDC_SM8150) += pdc-sm8150.o obj-$(CONFIG_QTI_PDC_SM6150) += pdc-sm6150.o obj-$(CONFIG_QTI_PDC_SDMMAGPIE) += pdc-sdmmagpie.o obj-$(CONFIG_QTI_PDC_SDXPRAIRIE) += pdc-sdxprairie.o -obj-$(CONFIG_QTI_MPM) += mpm.o -obj-$(CONFIG_QTI_MPM) += mpm.o mpm-8937.o mpm-qcs405.o +obj-$(CONFIG_QTI_MPM) += mpm.o mpm-8937.o mpm-qcs405.o mpm-trinket.o diff --git a/drivers/irqchip/qcom/mpm-trinket.c b/drivers/irqchip/qcom/mpm-trinket.c new file mode 100644 index 000000000000..0789d9b7eb34 --- /dev/null +++ b/drivers/irqchip/qcom/mpm-trinket.c @@ -0,0 +1,90 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "mpm.h" + +const struct mpm_pin mpm_trinket_gic_chip_data[] = { + {2, 222}, + {12, 454}, /* b3_lfps_rxterm_irq */ + {86, 215}, /* mpm_wake,spmi_m */ + {90, 286}, /* eud_p0_dpse_int_mx */ + {91, 286}, /* eud_p0_dmse_int_mx */ + {-1}, +}; + +const struct mpm_pin mpm_trinket_gpio_chip_data[] = { + {5, 43}, + {6, 45}, + {7, 59}, + {8, 72}, + {9, 83}, + {13, 124}, + {14, 1}, + {15, 3}, + {16, 4}, + {17, 9}, + {18, 13}, + {19, 15}, + {20, 17}, + {21, 19}, + {22, 21}, + {23, 14}, + {24, 25}, + {25, 26}, + {26, 27}, + {27, 29}, + {28, 33}, + {29, 36}, + {30, 42}, + {31, 44}, + {32, 47}, + {33, 50}, + {34, 70}, + {35, 75}, + {36, 79}, + {37, 80}, + {38, 81}, + {39, 82}, + {40, 85}, + {41, 86}, + {42, 88}, + {43, 89}, + {44, 91}, + {45, 92}, + {46, 93}, + {47, 94}, + {48, 95}, + {49, 96}, + {50, 98}, + {51, 99}, + {52, 101}, + {53, 102}, + {54, 105}, + {55, 107}, + {56, 110}, + {57, 111}, + {58, 112}, + {59, 118}, + {60, 122}, + {61, 123}, + {62, 126}, + {63, 128}, + {64, 100}, + {65, 130}, + {66, 131}, + {67, 132}, + {70, 97}, + {71, 120}, + {84, 22}, + {-1}, +}; diff --git a/drivers/irqchip/qcom/mpm.c b/drivers/irqchip/qcom/mpm.c index 143a5057a20f..0a31aee8da6f 100644 --- a/drivers/irqchip/qcom/mpm.c +++ b/drivers/irqchip/qcom/mpm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -609,6 +609,10 @@ static const struct of_device_id mpm_gic_chip_data_table[] = { .compatible = "qcom,mpm-gic-qcs405", .data = mpm_qcs405_gic_chip_data, }, + { + .compatible = "qcom,mpm-gic-trinket", + .data = mpm_trinket_gic_chip_data, + }, {} }; MODULE_DEVICE_TABLE(of, mpm_gic_chip_data_table); @@ -622,6 +626,10 @@ static const struct of_device_id mpm_gpio_chip_data_table[] = { .compatible = "qcom,mpm-gpio-qcs405", .data = mpm_qcs405_gpio_chip_data, }, + { + .compatible = "qcom,mpm-gpio-trinket", + .data = mpm_trinket_gpio_chip_data, + }, {} }; diff --git a/drivers/irqchip/qcom/mpm.h b/drivers/irqchip/qcom/mpm.h index 7b5c3d8f4048..209994e2b980 100644 --- a/drivers/irqchip/qcom/mpm.h +++ b/drivers/irqchip/qcom/mpm.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -26,4 +26,6 @@ extern const struct mpm_pin mpm_msm8937_gpio_chip_data[]; extern const struct mpm_pin mpm_qcs405_gic_chip_data[]; extern const struct mpm_pin mpm_qcs405_gpio_chip_data[]; +extern const struct mpm_pin mpm_trinket_gic_chip_data[]; +extern const struct mpm_pin mpm_trinket_gpio_chip_data[]; #endif /* __QCOM_MPM_H__ */ -- GitLab From f6dfa50978c9c8f25f9087bb720fd7d508df12cd Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Tue, 16 Oct 2018 18:26:17 +0530 Subject: [PATCH 0661/1286] ARM: dts: msm: Add MPM interrupt controller for trinket Add mpm interrupt controller as SOC interrupt parent and as a child domain under intc for trinket. Change-Id: I72e133e58b0faec6edc71efa4d5a2ce355b5a7aa Signed-off-by: Raghavendra Kakarla --- arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 3 ++- arch/arm64/boot/dts/qcom/trinket.dtsi | 23 ++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 4af810b8b3ca..2258e40186c7 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -17,10 +17,11 @@ compatible = "qcom,trinket-pinctrl"; reg = <0x400000 0xc00000>; reg-names = "pinctrl"; - interrupts = <0 227 0>; + interrupts-extended = <&wakegic GIC_SPI 227 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; interrupt-controller; + interrupt-parent = <&wakegpio>; #interrupt-cells = <2>; /* QUPv3_0 SE mappings */ diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2bb941134b0f..217624e8fedf 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -27,7 +27,7 @@ model = "Qualcomm Technologies, Inc. TRINKET"; compatible = "qcom,trinket"; qcom,msm-id = <394 0x10000>; - interrupt-parent = <&intc>; + interrupt-parent = <&wakegic>; aliases { serial0 = &qupv3_se4_2uart; @@ -520,6 +520,7 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; reg = <0xf200000 0x10000>, /* GICD */ @@ -615,6 +616,26 @@ qcom,coresight-jtagmm-cpu = <&CPU7>; }; + wakegic: wake-gic { + compatible = "qcom,mpm-gic-trinket", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 171 + IRQ_TYPE_EDGE_RISING>; + reg = <0x45f01b8 0x1000>, + <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio-trinket", "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, -- GitLab From b447790bb02e858a7a8d863d20961a70590ab126 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Mon, 31 Dec 2018 12:01:45 +0530 Subject: [PATCH 0662/1286] defconfig: Enable MSM_SPM support Enable MSM_SPM support in trinket. Change-Id: I2ab465c835df276e51d88e57caf79b4c928183cc Signed-off-by: Raghavendra Kakarla --- arch/arm64/configs/vendor/trinket-perf_defconfig | 2 ++ arch/arm64/configs/vendor/trinket_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a35f1169b3bf..a4577bb05fd2 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -497,6 +497,8 @@ CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y +CONFIG_MSM_SPM=y +CONFIG_MSM_L2_SPM=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 603c50f073bd..acad3e249723 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -519,6 +519,8 @@ CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y +CONFIG_MSM_SPM=y +CONFIG_MSM_L2_SPM=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -- GitLab From 27bcbdf442a1aa8fba01150f6ff8d391af5fb9ac Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Wed, 26 Dec 2018 14:26:16 +0530 Subject: [PATCH 0663/1286] msm: camera: isp: Improve logging by adding context info Add context id in the logs during various events ISP works upon. This will ease during debug process by reducing providing enough info from the logs. Change-Id: Iebcf02f66597faf64a464dd527dadc7b7201c5b8 Signed-off-by: Abhilash Kumar --- .../msm/camera/cam_isp/cam_isp_context.c | 104 ++++++++++-------- 1 file changed, 59 insertions(+), 45 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c index 14af855b9327..320beb7bd946 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c @@ -424,10 +424,11 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( if (!req_isp->bubble_detected) { CAM_DBG(CAM_ISP, - "Sync with success: req %lld res 0x%x fd 0x%x", + "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u", req->request_id, req_isp->fence_map_out[j].resource_handle, - req_isp->fence_map_out[j].sync_id); + req_isp->fence_map_out[j].sync_id, + ctx->ctx_id); rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, CAM_SYNC_STATE_SIGNALED_SUCCESS); @@ -435,11 +436,12 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( CAM_DBG(CAM_ISP, "Sync failed with rc = %d", rc); } else if (!req_isp->bubble_report) { - CAM_DBG(CAM_ISP, - "Sync with failure: req %lld res 0x%x fd 0x%x", + CAM_ERR(CAM_ISP, + "Sync with failure: req %lld res 0x%x fd 0x%x, ctx %u", req->request_id, req_isp->fence_map_out[j].resource_handle, - req_isp->fence_map_out[j].sync_id); + req_isp->fence_map_out[j].sync_id, + ctx->ctx_id); rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, CAM_SYNC_STATE_SIGNALED_ERROR); @@ -460,9 +462,9 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( continue; } - CAM_DBG(CAM_ISP, "req %lld, reset sync id 0x%x", + CAM_DBG(CAM_ISP, "req %lld, reset sync id 0x%x ctx %u", req->request_id, - req_isp->fence_map_out[j].sync_id); + req_isp->fence_map_out[j].sync_id, ctx->ctx_id); if (!rc) { req_isp->num_acked++; req_isp->fence_map_out[j].sync_id = -1; @@ -472,9 +474,9 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( if (req_isp->num_acked > req_isp->num_fence_map_out) { /* Should not happen */ CAM_ERR(CAM_ISP, - "WARNING: req_id %lld num_acked %d > map_out %d", + "WARNING: req_id %lld num_acked %d > map_out %d, ctx %u", req->request_id, req_isp->num_acked, - req_isp->num_fence_map_out); + req_isp->num_fence_map_out, ctx->ctx_id); WARN_ON(req_isp->num_acked > req_isp->num_fence_map_out); } @@ -491,15 +493,15 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( atomic_set(&ctx_isp->process_bubble, 0); CAM_DBG(CAM_REQ, - "Move active request %lld to pending list(cnt = %d) [bubble recovery]", - req->request_id, ctx_isp->active_req_cnt); + "Move active request %lld to pending list(cnt = %d) [bubble recovery], ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); } else { list_del_init(&req->list); list_add_tail(&req->list, &ctx->free_req_list); CAM_DBG(CAM_REQ, - "Move active request %lld to free list(cnt = %d) [all fences done]", - req->request_id, ctx_isp->active_req_cnt); + "Move active request %lld to free list(cnt = %d) [all fences done], ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); } end: @@ -598,14 +600,15 @@ static int __cam_isp_ctx_reg_upd_in_activated_state( if (req_isp->num_fence_map_out != 0) { list_add_tail(&req->list, &ctx->active_req_list); ctx_isp->active_req_cnt++; - CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d)", - req->request_id, ctx_isp->active_req_cnt); + CAM_DBG(CAM_REQ, + "move request %lld to active list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); } else { /* no io config, so the request is completed. */ list_add_tail(&req->list, &ctx->free_req_list); CAM_DBG(CAM_ISP, - "move active request %lld to free list(cnt = %d)", - req->request_id, ctx_isp->active_req_cnt); + "move active request %lld to free list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); } /* @@ -644,8 +647,8 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( notify.trigger = CAM_TRIGGER_POINT_SOF; ctx->ctx_crm_intf->notify_trigger(¬ify); - CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", - ctx_isp->frame_id); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld ctx %u", + ctx_isp->frame_id, ctx->ctx_id); } list_for_each_entry(req, &ctx->active_req_list, list) { @@ -662,7 +665,9 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); } else { - CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Can not notify SOF to CRM for ctx %u", + ctx->ctx_id); rc = -EFAULT; } @@ -687,10 +692,11 @@ static int __cam_isp_ctx_notify_eof_in_activated_state( notify.trigger = CAM_TRIGGER_POINT_EOF; ctx->ctx_crm_intf->notify_trigger(¬ify); - CAM_DBG(CAM_ISP, "Notify CRM EOF frame %lld\n", - ctx_isp->frame_id); + CAM_DBG(CAM_ISP, "Notify CRM EOF frame %lld ctx %u", + ctx_isp->frame_id, ctx->ctx_id); } else { - CAM_ERR(CAM_ISP, "Can not notify EOF to CRM"); + CAM_ERR(CAM_ISP, "Can not notify EOF to CRM for ctx %u", + ctx->ctx_id); rc = -EFAULT; } @@ -725,8 +731,8 @@ static int __cam_isp_ctx_sof_in_activated_state( ctx_isp->boot_timestamp = sof_event_data->boot_time; __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_SOF, req->request_id); - CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", - ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx, ctx %u", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val, ctx->ctx_id); return rc; } @@ -807,8 +813,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, notify.error = CRM_KMD_ERR_BUBBLE; ctx->ctx_crm_intf->notify_err(¬ify); atomic_set(&ctx_isp->process_bubble, 1); - CAM_DBG(CAM_ISP, "Notify CRM about Bubble frame %lld", - ctx_isp->frame_id); + CAM_DBG(CAM_ISP, "Notify CRM about Bubble frame %lld, ctx %u", + ctx_isp->frame_id, ctx->ctx_id); } else { req_isp->bubble_report = 0; } @@ -817,8 +823,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, * Always move the request to active list. Let buf done * function handles the rest. */ - CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d)", - req->request_id, ctx_isp->active_req_cnt); + CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); ctx_isp->active_req_cnt++; list_del_init(&req->list); list_add_tail(&req->list, &ctx->active_req_list); @@ -956,8 +962,8 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( notify.error = CRM_KMD_ERR_BUBBLE; ctx->ctx_crm_intf->notify_err(¬ify); CAM_DBG(CAM_REQ, - "Notify CRM about Bubble req_id %llu frame %lld", - req->request_id, ctx_isp->frame_id); + "Notify CRM about Bubble req_id %llu frame %lld, ctx %u", + req->request_id, ctx_isp->frame_id, ctx->ctx_id); } else { req_isp->bubble_report = 0; } @@ -966,7 +972,7 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( * Always move the request to active list. Let buf done * function handles the rest. */ - CAM_DBG(CAM_ISP, "move request %lld to active list(cnt = %d)", + CAM_DBG(CAM_ISP, "move request %lld to active list(cnt = %d) ctx %u", req->request_id, ctx_isp->active_req_cnt); ctx_isp->active_req_cnt++; list_del_init(&req->list); @@ -1072,9 +1078,11 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, for (i = 0; i < req_isp->num_fence_map_out; i++) { fence_map_out = &req_isp->fence_map_out[i]; - CAM_ERR(CAM_ISP, "req %llu, Sync fd %x", + CAM_ERR(CAM_ISP, + "req %llu, Sync fd 0x%x ctx %u", req->request_id, - req_isp->fence_map_out[i].sync_id); + req_isp->fence_map_out[i].sync_id, + ctx->ctx_id); if (req_isp->fence_map_out[i].sync_id != -1) { rc = cam_sync_signal( fence_map_out->sync_id, @@ -1101,9 +1109,11 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, for (i = 0; i < req_isp->num_fence_map_out; i++) { fence_map_out = &req_isp->fence_map_out[i]; - CAM_ERR(CAM_ISP, "req %llu, Sync fd %x", + CAM_ERR(CAM_ISP, + "req %llu, Sync fd 0x%x ctx %u", req->request_id, - req_isp->fence_map_out[i].sync_id); + req_isp->fence_map_out[i].sync_id, + ctx->ctx_id); if (req_isp->fence_map_out[i].sync_id != -1) { rc = cam_sync_signal( fence_map_out->sync_id, @@ -1190,8 +1200,8 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, notify.error = CRM_KMD_ERR_FATAL; } - CAM_WARN(CAM_ISP, "Notify CRM: req %lld, frame %lld\n", - error_request_id, ctx_isp->frame_id); + CAM_WARN(CAM_ISP, "Notify CRM: req %lld, frame %lld ctx %u", + error_request_id, ctx_isp->frame_id, ctx->ctx_id); ctx->ctx_crm_intf->notify_err(¬ify); @@ -1214,12 +1224,15 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, V4L_EVENT_CAM_REQ_MGR_ERROR, V4L_EVENT_CAM_REQ_MGR_EVENT)) CAM_ERR(CAM_ISP, - "Error in notifying the error time for req id:%lld", - ctx_isp->last_applied_req_id); + "Error in notifying the error time for req id:%lld ctx %u", + ctx_isp->last_applied_req_id, + ctx->ctx_id); } ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HW_ERROR; } else { - CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify ERRROR to CRM"); + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Can not notify ERRROR to CRM for ctx %u", + ctx->ctx_id); rc = -EFAULT; } @@ -1656,15 +1669,16 @@ static int __cam_isp_ctx_apply_req_in_activated_state( goto end; } - CAM_DBG(CAM_REQ, "Apply request %lld in substate %d", req->request_id, - ctx_isp->substate_activated); + CAM_DBG(CAM_REQ, "Apply request %lld in substate %d ctx %u", + req->request_id, ctx_isp->substate_activated, ctx->ctx_id); req_isp = (struct cam_isp_ctx_req *) req->req_priv; if (ctx_isp->active_req_cnt >= 2) { CAM_ERR_RATE_LIMIT(CAM_ISP, - "Reject apply request (id %lld) due to congestion(cnt = %d)", + "Reject apply request (id %lld) due to congestion(cnt = %d) ctx %u", req->request_id, - ctx_isp->active_req_cnt); + ctx_isp->active_req_cnt, + ctx->ctx_id); spin_lock_bh(&ctx->lock); if (!list_empty(&ctx->active_req_list)) -- GitLab From ca05280f3178b35f67f8025f6696af76be3e776c Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Fri, 26 Oct 2018 17:43:36 +0530 Subject: [PATCH 0664/1286] defconfig: Enable MPM support for trinket Enable MPM interrupt controller compilation support. Change-Id: I0581e0621ed08955947d09a82f193564d48c1755 Signed-off-by: Raghavendra Kakarla --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a35f1169b3bf..bcf6b29bf5d4 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -551,6 +551,7 @@ CONFIG_PWM=y CONFIG_PWM_QTI_LPG=y CONFIG_QCOM_KGSL=y CONFIG_ARM_GIC_V3_ACL=y +CONFIG_QTI_MPM=y CONFIG_RAS=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 603c50f073bd..346e7b1210fd 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -579,6 +579,7 @@ CONFIG_PWM=y CONFIG_PWM_QTI_LPG=y CONFIG_QCOM_KGSL=y CONFIG_ARM_GIC_V3_ACL=y +CONFIG_QTI_MPM=y CONFIG_PHY_XGENE=y CONFIG_RAS=y CONFIG_ANDROID=y -- GitLab From f4b06042c0b132997607263b62f096248c775c41 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 4 Jan 2019 15:07:09 +0800 Subject: [PATCH 0665/1286] ARM: dts: msm: Add volume up key for QRD Trinket interposer The volume up key is connecting to PM6125 GPIO5 so add the device configuration for it. Change-Id: I0d0ce48da216daabdcc3e1b41668906467d44986 Signed-off-by: Fenglin Wu --- .../qcom/sm6150-interposer-trinket-qrd.dtsi | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi index fe61d42a11bd..8c290200e04c 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,7 +12,36 @@ */ #include "sm6150-qrd.dtsi" +#include +#include + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; &soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; }; -- GitLab From 80fa8589cf5f68d9d75ad2ce35d129cca201f4df Mon Sep 17 00:00:00 2001 From: Prakash Kamliya Date: Thu, 27 Dec 2018 18:36:08 +0530 Subject: [PATCH 0666/1286] msm: kgsl: Relax adreno spin idle tight loop Tight loop of adreno_spin_idle() causing RT throttling. Relax the tight loop by giving chance to other thread. Change-Id: Ic23d4551c0cc0b5f2fa7844ca73444d1412d480c Signed-off-by: Prakash Kamliya --- drivers/gpu/msm/adreno.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index f220d198c18f..789cc4059253 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -3098,6 +3098,9 @@ int adreno_spin_idle(struct adreno_device *adreno_dev, unsigned int timeout) if (adreno_isidle(KGSL_DEVICE(adreno_dev))) return 0; + /* relax tight loop */ + cond_resched(); + } while (time_before(jiffies, wait)); /* -- GitLab From 303674ea21f78be3c489fd5dd6197d4fcfc7bc04 Mon Sep 17 00:00:00 2001 From: mjavid Date: Mon, 10 Dec 2018 18:24:01 +0530 Subject: [PATCH 0667/1286] msm: ipa3: Fix memleak issue for IPv6 NAt and IPA CT device Currently tmp memory is deleted in device destroy method, but there is no check for NULL. So it can cause for double free issue. Change-Id: Ide8d8d24c0f9cea68597ecbf6b6b84269062384a Acked-by: Pooja Kumari Signed-off-by: Mohammed Javid --- drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 2 ++ drivers/platform/msm/ipa/ipa_v3/ipa_nat.c | 25 +++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index 7f152f2c099f..bb3272770f65 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1110,6 +1110,7 @@ struct ipa3_nat_ipv6ct_common_mem { * @index_table_expansion_addr: index expansion table address * @public_ip_addr: ip address of nat table * @pdn_mem: pdn config table SW cache memory structure + * @is_tmp_mem_allocated: indicate if tmp mem has been allocated */ struct ipa3_nat_mem { struct ipa3_nat_ipv6ct_common_mem dev; @@ -1117,6 +1118,7 @@ struct ipa3_nat_mem { char *index_table_expansion_addr; u32 public_ip_addr; struct ipa_mem_buffer pdn_mem; + bool is_tmp_mem_allocated; }; /** diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c index 9212b7225d20..c20d2c2a33fe 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_nat.c @@ -279,14 +279,21 @@ static void ipa3_nat_ipv6ct_destroy_device( mutex_lock(&dev->lock); - dma_free_coherent(ipa3_ctx->pdev, IPA_NAT_IPV6CT_TEMP_MEM_SIZE, - dev->tmp_mem->vaddr, dev->tmp_mem->dma_handle); - kfree(dev->tmp_mem); + if (dev->tmp_mem != NULL && + ipa3_ctx->nat_mem.is_tmp_mem_allocated == false) { + dev->tmp_mem = NULL; + } else if (dev->tmp_mem != NULL && + ipa3_ctx->nat_mem.is_tmp_mem_allocated) { + dma_free_coherent(ipa3_ctx->pdev, IPA_NAT_IPV6CT_TEMP_MEM_SIZE, + dev->tmp_mem->vaddr, dev->tmp_mem->dma_handle); + kfree(dev->tmp_mem); + dev->tmp_mem = NULL; + ipa3_ctx->nat_mem.is_tmp_mem_allocated = false; + } device_destroy(dev->class, dev->dev_num); unregister_chrdev_region(dev->dev_num, 1); class_destroy(dev->class); dev->is_dev_init = false; - mutex_unlock(&dev->lock); IPADBG("return\n"); @@ -309,10 +316,15 @@ int ipa3_nat_ipv6ct_init_devices(void) /* * Allocate NAT/IPv6CT temporary memory. The memory is never deleted, * because provided to HW once NAT or IPv6CT table is deleted. - * NULL is a legal value */ tmp_mem = ipa3_nat_ipv6ct_allocate_tmp_memory(); + if (tmp_mem == NULL) { + IPAERR("unable to allocate tmp_mem\n"); + return -ENOMEM; + } + ipa3_ctx->nat_mem.is_tmp_mem_allocated = true; + if (ipa3_nat_ipv6ct_init_device( &ipa3_ctx->nat_mem.dev, IPA_NAT_DEV_NAME, @@ -341,10 +353,11 @@ int ipa3_nat_ipv6ct_init_devices(void) fail_init_ipv6ct_dev: ipa3_nat_ipv6ct_destroy_device(&ipa3_ctx->nat_mem.dev); fail_init_nat_dev: - if (tmp_mem != NULL) { + if (tmp_mem != NULL && ipa3_ctx->nat_mem.is_tmp_mem_allocated) { dma_free_coherent(ipa3_ctx->pdev, IPA_NAT_IPV6CT_TEMP_MEM_SIZE, tmp_mem->vaddr, tmp_mem->dma_handle); kfree(tmp_mem); + ipa3_ctx->nat_mem.is_tmp_mem_allocated = false; } return result; } -- GitLab From 66b2a799a6b72988bcd7e33ea744ca92d3518066 Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Fri, 4 Jan 2019 13:27:44 +0530 Subject: [PATCH 0668/1286] input: touchscreen: st: turn off regulator during suspend Add change to turn off the regulator during suspend, and turn it on during resume. Change-Id: Id83fd831622aaeab4d2b237a3bf5f1f2fc8122f1 Signed-off-by: Vevek Venkatesan --- drivers/input/touchscreen/st/fts.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/input/touchscreen/st/fts.c b/drivers/input/touchscreen/st/fts.c index b50bd83e30dd..b53169c49d0c 100644 --- a/drivers/input/touchscreen/st/fts.c +++ b/drivers/input/touchscreen/st/fts.c @@ -134,6 +134,7 @@ static int fts_init_afterProbe(struct fts_ts_info *info); static int fts_mode_handler(struct fts_ts_info *info, int force); static int fts_command(struct fts_ts_info *info, unsigned char cmd); static int fts_chip_initialization(struct fts_ts_info *info); +static int fts_enable_reg(struct fts_ts_info *info, bool enable); active_tp_setup(st); @@ -4021,6 +4022,11 @@ static void fts_resume_work(struct work_struct *work) __pm_wakeup_event(&info->wakeup_source, HZ); + if (fts_enable_reg(info, true) < 0) { + logError(1, "%s %s: ERROR Failed to enable regulators\n", + tag, __func__); + } + if (info->ts_pinctrl) { /* * Pinctrl handle is optional. If pinctrl handle is found @@ -4083,6 +4089,8 @@ static void fts_suspend_work(struct work_struct *work) __func__, PINCTRL_STATE_SUSPEND); } } + + fts_enable_reg(info, false); } -- GitLab From 7d18454f7caa3059e431e3222abbe9b3ddab2b43 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 27 Dec 2018 10:18:42 +0800 Subject: [PATCH 0669/1286] input: misc: qti-haptics: check NULL pointer before using it There might be a rare case that previous play has been terminated and the next play is generating in VMAX mode so that the play effect pointer would be set to NULL before the play IRQ being served. So check the effect pointer before using it in the play IRQ handler. Change-Id: I2d9ace5d09ffde885b4267e1e78771a169c57bec Signed-off-by: Fenglin Wu --- drivers/input/misc/qti-haptics.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/input/misc/qti-haptics.c b/drivers/input/misc/qti-haptics.c index c9b4997dd80a..7bbfa3155b8e 100644 --- a/drivers/input/misc/qti-haptics.c +++ b/drivers/input/misc/qti-haptics.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -737,6 +737,10 @@ static irqreturn_t qti_haptics_play_irq_handler(int irq, void *data) int rc; dev_dbg(chip->dev, "play_irq triggered\n"); + + if (effect == NULL) + goto handled; + if (play->playing_pos == effect->pattern_length) { dev_dbg(chip->dev, "waveform playing done\n"); if (chip->play_irq_en) { -- GitLab From 1d3459e93322dc24588609ff14e82d436f90e514 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Wed, 26 Dec 2018 10:13:33 +0530 Subject: [PATCH 0670/1286] ARM: dts: msm: Enable console UART for trinket track3 bringup Enables console uart for track3 bringup purpose for IDP platform. Change-Id: I861f4b8a1c7ee7990cbf2cbba47d6b1c313dc4f0 Signed-off-by: Mukesh Kumar Savaliya --- arch/arm64/boot/dts/qcom/sm6150-interposer-trinket.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket.dtsi index 84d8801b3f6b..fa03d63835c9 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,3 +48,7 @@ &usb0 { extcon = <&pmi632_charger>; }; + +&qupv3_se0_2uart { + status = "ok"; +}; -- GitLab From 75c52596e09aee334feeabce9d3488bd456bfc4b Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 20 Dec 2018 18:54:15 +0530 Subject: [PATCH 0671/1286] msm: dts: rename audio machine driver rename the sound adp star compatibility string and model to reflect the new machine for sa6155 Signed-off-by: Rahul Sharma Change-Id: I1676a1beab6f479fa291d0d152a7eb2dfb584e4a --- .../bindings/sound/qcom-audio-dev.txt | 119 +++++++++++++++++- arch/arm64/boot/dts/qcom/sa6155-audio.dtsi | 4 +- 2 files changed, 120 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index b824ed2d8626..fa3a6bfcc770 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -1865,4 +1865,121 @@ Example: compatible = "qcom,voice-mhi-audio"; memory-region = <&mailbox_mem>; voice_mhi_voting; - }; \ No newline at end of file + }; + +* SA6155 ASoC Machine driver + +Required properties: +- compatible : "qcom,sa6155-asoc-snd-auto" for auto adp codec and + "qcom,sa6155-asoc-snd-auto-custom" for auto custom codec. +- qcom,model : The user-visible name of this sound card. +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order given + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". +Optional properties: +- qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target +- qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target +- qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces + +Example: + + sound-adp-star { + compatible = "qcom,sa6155-asoc-snd-adp-star"; + qcom,model = "sa6155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_tx_0>, <&dai_sec_tdm_tx_1>, + <&dai_sec_tdm_tx_2>, <&dai_sec_tdm_tx_3>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_rx_1>, + <&dai_tert_tdm_rx_2>, <&dai_tert_tdm_rx_3>, + <&dai_tert_tdm_rx_4>, <&dai_tert_tdm_tx_0>, + <&dai_tert_tdm_tx_1>, <&dai_tert_tdm_tx_2>, + <&dai_tert_tdm_tx_3>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_tx_1>, <&dai_quat_tdm_tx_2>, + <&dai_quat_tdm_tx_3>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36883", + "msm-dai-q6-tdm.36885", "msm-dai-q6-tdm.36887", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36898", + "msm-dai-q6-tdm.36900", "msm-dai-q6-tdm.36902", + "msm-dai-q6-tdm.36904", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36899", "msm-dai-q6-tdm.36901", + "msm-dai-q6-tdm.36903", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36915", "msm-dai-q6-tdm.36917", + "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + }; diff --git a/arch/arm64/boot/dts/qcom/sa6155-audio.dtsi b/arch/arm64/boot/dts/qcom/sa6155-audio.dtsi index 3314876c1885..98508e0d2502 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-audio.dtsi @@ -412,8 +412,8 @@ sound-adp-star { status = "ok"; - compatible = "qcom,sa8155-asoc-snd-adp-star"; - qcom,model = "sa8155-adp-star-snd-card"; + compatible = "qcom,sa6155-asoc-snd-adp-star"; + qcom,model = "sa6155-adp-star-snd-card"; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; -- GitLab From 392094484b5d1fbb3e7ccaeb79ea5916b1fe5ff7 Mon Sep 17 00:00:00 2001 From: Neeraj Soni Date: Thu, 3 Jan 2019 12:54:41 +0530 Subject: [PATCH 0672/1286] scsi: ufs: release spinlock and fix workqueue allocation This fixes synchronization bug introduced with commit b557a6117a2b ("scsi: ufs: ice: propagate memeory allocation failure error") Also in low end ufs targets crypto engine is initialized in every resume operation. This will endup allocating memory for crypto worker queue in every resume. Check for queue pointer before allocating the memory for work queue. Change-Id: I919a6cbfc418de335e797d4fd724cd3c63bace55 Signed-off-by: Neeraj Soni --- drivers/scsi/ufs/ufs-qcom-ice.c | 38 +++++++++++++++------------------ 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/scsi/ufs/ufs-qcom-ice.c b/drivers/scsi/ufs/ufs-qcom-ice.c index 718c6abff14f..c5fe4784fa21 100644 --- a/drivers/scsi/ufs/ufs-qcom-ice.c +++ b/drivers/scsi/ufs/ufs-qcom-ice.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -225,15 +225,17 @@ int ufs_qcom_ice_init(struct ufs_qcom_host *qcom_host) } qcom_host->dbg_print_en |= UFS_QCOM_ICE_DEFAULT_DBG_PRINT_EN; - ice_workqueue = alloc_workqueue("ice-set-key", - WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); if (!ice_workqueue) { - dev_err(ufs_dev, "%s: workqueue allocation failed.\n", + ice_workqueue = alloc_workqueue("ice-set-key", + WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); + if (!ice_workqueue) { + dev_err(ufs_dev, "%s: workqueue allocation failed.\n", __func__); - err = -ENOMEM; - goto out; + err = -ENOMEM; + goto out; + } + INIT_WORK(&qcom_host->ice_cfg_work, ufs_qcom_ice_cfg_work); } - INIT_WORK(&qcom_host->ice_cfg_work, ufs_qcom_ice_cfg_work); out: return err; @@ -287,16 +289,13 @@ int ufs_qcom_ice_req_setup(struct ufs_qcom_host *qcom_host, */ if (err == -EAGAIN) { if (!ice_workqueue) { + spin_unlock_irqrestore( + &qcom_host->ice_work_lock, + flags); + dev_err(qcom_host->hba->dev, "%s: error %d workqueue NULL\n", __func__, err); - /* - * over write the error code to halt - * the request from upper layer as - * system is possibly in low memory - * state. Give system a chance to - * recover and reinitialize ice driver. - */ return -EINVAL; } @@ -425,16 +424,13 @@ int ufs_qcom_ice_cfg_start(struct ufs_qcom_host *qcom_host, */ if (err == -EAGAIN) { if (!ice_workqueue) { + spin_unlock_irqrestore( + &qcom_host->ice_work_lock, + flags); + dev_err(qcom_host->hba->dev, "%s: error %d workqueue NULL\n", __func__, err); - /* - * over write the error code to halt - * the request from upper layer as - * system is possibly in low memory - * state. Give system a chance to - * recover and reinitialize ice driver. - */ return -EINVAL; } -- GitLab From 56cd55ece8b514abbb4b6b0e2e220c8055da9421 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Fri, 4 Jan 2019 15:01:26 +0530 Subject: [PATCH 0673/1286] ARM: dts: msm: Enable Qupv3 serial console UART for trinket Add device tree node for QUPV3 uart instance to support serial console on trinket. Change-Id: Ib11b3703f30421d7dd2b5c2679b39553fb8b11ed Signed-off-by: Prudhvi Yarlagadda --- arch/arm64/boot/dts/qcom/trinket-rumi.dtsi | 6 +----- arch/arm64/boot/dts/qcom/trinket.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi index 49be16db5cb9..0cd615240172 100644 --- a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,10 +45,6 @@ }; }; -&qupv3_se4_2uart { - status = "ok"; -}; - &usb0 { extcon = <0>; dwc3@4e00000 { diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..f653c117668b 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1892,4 +1892,9 @@ &usb0 { extcon = <&pmi632_charger>; }; + +&qupv3_se4_2uart { + status = "ok"; +}; + #include "trinket-thermal.dtsi" -- GitLab From 2da29f45fbdb2d16f4ccc22bcdbecd32876751cd Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 4 Jan 2019 15:03:54 +0530 Subject: [PATCH 0674/1286] ARM: dts: msm: enable CDSP cooling device mitigation for SM6150 Enable CDSP cooling device mitigation for all CX tsens and skin temperature sensor for SM6150. Change-Id: I89c612ae6b68b11700f9c8a40908d5f77458c612 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi | 49 ++++++++++++++++++-- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi b/arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi index 602aee1cb6d6..26794a3b4afc 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -546,6 +546,10 @@ trip = <&gpu_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + gpu-cx-cdev3 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1553,11 +1557,17 @@ thermal-sensors = <&tsens0 10>; thermal-governor = "step_wise"; trips { - q6_hvx_config: q6-hvx-config { + q6_hvx_cxip: q6-hvx-config { temperature = <95000>; hysteresis = <20000>; type = "passive"; }; + q6_hvx_therm: q6-hvx-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + q6_hvx_cx_mon: q6-hvx-cx-mon { temperature = <100000>; hysteresis = <5000>; @@ -1566,9 +1576,14 @@ }; cooling-maps { cxip-cdev { - trip = <&q6_hvx_config>; + trip = <&q6_hvx_cxip>; cooling-device = <&cxip_cdev 1 1>; }; + cdsp-cdev { + trip = <&q6_hvx_therm>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 5>; + }; hvx-cx-cdev0 { trip = <&q6_hvx_cx_mon>; cooling-device = <&msm_gpu THERMAL_MAX_LIMIT @@ -1582,6 +1597,10 @@ trip = <&q6_hvx_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + hvx-cx-cdev3 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1611,6 +1630,10 @@ trip = <&mdm_core_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + mdm-cx-cdev3 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1640,6 +1663,10 @@ trip = <&camera_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + camera-cx-cdev3 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1669,6 +1696,10 @@ trip = <&wlan_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + wlan-cx-cdev3 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1698,6 +1729,10 @@ trip = <&dispaly_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + display-cx-cdev3 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1727,6 +1762,10 @@ trip = <&video_cx_mon>; cooling-device = <&modem_pa 3 3>; }; + video-cx-cdev3 { + trip = <&video_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; @@ -1981,6 +2020,10 @@ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + cx-skin-cdsp { + trip = <&cx_emer_trip>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; }; }; }; -- GitLab From 45220fc40607e854a9c1e13b7486e0d5f80cf167 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 27 Dec 2018 15:14:54 +0530 Subject: [PATCH 0675/1286] mmc: sdhci: Fix the timeout check window for clock and reset We observed some premature timeouts on a virtualization platform, the log is like this: case 1: [159525.255629] mmc1: Internal clock never stabilised. [159525.255818] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [159525.256049] mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00001002 ... [159525.257205] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000fa03 From the clock control register dump, we are pretty sure the clock was stablized. case 2: [ 914.550127] mmc1: Reset 0x2 never completed. [ 914.550321] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [ 914.550608] mmc1: sdhci: Sys addr: 0x00000010 | Version: 0x00001002 After checking the sdhci code, we found the timeout check actually has a little window that the CPU can be scheduled out and when it comes back, the original time set or check is not valid. Change-Id: I291379e640d2896cfdebbe73133329a64c57d8c7 Fixes: 5a436cc0af62 ("mmc: sdhci: Optimize delay loops") Cc: stable@vger.kernel.org # v4.12+ Signed-off-by: Alek Du Acked-by: Adrian Hunter Signed-off-by: Ulf Hansson Git-commit: b704441e38f645dcfba1348ca3cc1ba43d1a9f31 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 54f4381a7b71..ae72b0de7044 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -248,8 +248,12 @@ void sdhci_reset(struct sdhci_host *host, u8 mask) SDHCI_INT_STATUS); /* hw clears the bit when it's done */ - while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { - if (ktime_after(ktime_get(), timeout)) { + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) + break; + if (timedout) { pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); MMC_TRACE(host->mmc, "%s: Reset 0x%x never completed\n", @@ -1576,9 +1580,13 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) /* Wait max 20 ms */ timeout = ktime_add_ms(ktime_get(), 20); - while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) - & SDHCI_CLOCK_INT_STABLE)) { - if (ktime_after(ktime_get(), timeout)) { + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); MMC_TRACE(host->mmc, -- GitLab From 4543a7e524c03137b5cb661766d0ceb97ad9bbac Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Wed, 12 Dec 2018 12:26:28 +0530 Subject: [PATCH 0676/1286] mm: cma: add new cma api wrapper for hyp_assign A new API for modules to hyp_assign entire dev cma area. Change-Id: I2206f4dd9a08aa719776b3f5a40d805ca48181c9 Signed-off-by: Vishwanath Raju K --- drivers/soc/qcom/secure_buffer.c | 28 ++++++++++++++++++++++++++++ include/soc/qcom/secure_buffer.h | 13 +++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/soc/qcom/secure_buffer.c b/drivers/soc/qcom/secure_buffer.c index 1ce422322f1a..507f9e53c33c 100644 --- a/drivers/soc/qcom/secure_buffer.c +++ b/drivers/soc/qcom/secure_buffer.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -413,6 +414,33 @@ int hyp_assign_phys(phys_addr_t addr, u64 size, u32 *source_vm_list, } EXPORT_SYMBOL(hyp_assign_phys); +int cma_hyp_assign_phys(struct device *dev, u32 *source_vm_list, + int source_nelems, int *dest_vmids, + int *dest_perms, int dest_nelems) +{ + phys_addr_t addr; + u64 size; + struct cma *cma = NULL; + int ret; + + if (dev && dev->cma_area) + cma = dev->cma_area; + + if (cma) { + addr = cma_get_base(cma); + size = (size_t)cma_get_size(cma); + } else { + return -ENOMEM; + } + + ret = hyp_assign_phys(addr, size, source_vm_list, + source_nelems, dest_vmids, + dest_perms, dest_nelems); + + return ret; +} +EXPORT_SYMBOL(cma_hyp_assign_phys); + const char *msm_secure_vmid_to_string(int secure_vmid) { switch (secure_vmid) { diff --git a/include/soc/qcom/secure_buffer.h b/include/soc/qcom/secure_buffer.h index 7b13c8edb100..01c8f5996f9d 100644 --- a/include/soc/qcom/secure_buffer.h +++ b/include/soc/qcom/secure_buffer.h @@ -66,6 +66,12 @@ int try_hyp_assign_table(struct sg_table *table, extern int hyp_assign_phys(phys_addr_t addr, u64 size, u32 *source_vmlist, int source_nelems, int *dest_vmids, int *dest_perms, int dest_nelems); + + +extern int cma_hyp_assign_phys(struct device *dev, u32 *source_vm_list, + int source_nelems, int *dest_vmids, + int *dest_perms, int dest_nelems); + bool msm_secure_v2_is_supported(void); const char *msm_secure_vmid_to_string(int secure_vmid); #else @@ -102,6 +108,13 @@ static inline int hyp_assign_phys(phys_addr_t addr, u64 size, return -EINVAL; } +static inline int cma_hyp_assign_phys(struct device *dev, u32 *source_vm_list, + int source_nelems, int *dest_vmids, + int *dest_perms, int dest_nelems) +{ + return -EINVAL; +} + static inline bool msm_secure_v2_is_supported(void) { return false; -- GitLab From f9263067c785645d1012a7415ec6bdcd3742f9be Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 11:15:04 +0530 Subject: [PATCH 0677/1286] ARM64: dts: msm: Add qseecom node for trinket Add qseecom driver node to enable the qseecom driver to communicate with TZ. Change-Id: I87e867fec5dd0f07c80eb95cd5002e62d4109070 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..329701bae64a 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1563,6 +1563,23 @@ }; }; + qcom_seecom: qseecom@46d00000 { + compatible = "qcom,qseecom"; + reg = <0x46d00000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, -- GitLab From 076e785e407198d4bed92817e454d83372af7dea Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Fri, 4 Jan 2019 15:39:02 +0530 Subject: [PATCH 0678/1286] ARM64: dts: msm: Add smcinvoke node for trinket Current SMCInvoke based framework supports communication between TZ and HLOS where objects are owned by TZ i.e. services are provided by TZ. However, if TZ needs a service from Linux, it has to invoke operation on an object owned by Linux. Such objects are called local objects which could be either callback objects or memory objects. Callback objects provide services such as operations on a file. Memory objects provide large memory sharing facility between TZ and Linux. Adding smcinvoke node to support local objects. Change-Id: Ie24c2389964115ca4569999a9e4d57f2f842e339 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 329701bae64a..4cfc940bd7f9 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1580,6 +1580,12 @@ qcom,qsee-reentrancy-support = <2>; }; + qcom_smcinvoke: smcinvoke@46d00000 { + compatible = "qcom,smcinvoke"; + reg = <0x46d00000 0x2200000>; + reg-names = "secapp-region"; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, -- GitLab From 5cecab4c465bf49807d0abdafc5a5075cac75b4e Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 13:06:05 +0530 Subject: [PATCH 0679/1286] ARM: dts: msm: Add crypto devices for trinket Add qcedev and qcrypto device node to enable HW crypto CE operations. Change-Id: Ic3bcc0bea0b2f74055ab18a153b74daa2fa26d89 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 53 +++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..f0a4695a3982 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1589,6 +1589,59 @@ qcom,client-id = <0x00000001>; }; + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 247 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x01A6 0x0011>, + <&apps_smmu 0x01B6 0x0011>; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 247 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x01A4 0x0011>, + <&apps_smmu 0x01B4 0x0011>; + }; + slim_aud: slim@a2c0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; -- GitLab From 7122c15f3b29da70c9f60df1e1690f4bc52babcf Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 18:52:04 +0530 Subject: [PATCH 0680/1286] ARM: dts: msm: Add qrng node for trinket Add QRNG device node to enable the QRNG driver to communicate with /dev/random. Change-Id: I62699c60f7bc84dbb15b56717bb5cc8315bd3ef4 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 4cfc940bd7f9..4763d3d81928 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1586,6 +1586,21 @@ reg-names = "secapp-region"; }; + qcom_rng: qrng@1b53000 { + compatible = "qcom,msm-rng"; + reg = <0x1b53000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, -- GitLab From f47ea1201cac5e9436199cf4bead67187093ea80 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Fri, 4 Jan 2019 12:45:55 +0530 Subject: [PATCH 0681/1286] ARM: dts: msm: Vote at SVS for master clock for USB on Trinket The SVS range of master clock of USB core for Trinket is enough for USB Superspeed functionality. So, vote the master clock at SVS for Trinket. Also, also vote for the SYS_NOC bus at SVS at normal opertaion. Change-Id: I9cd551870ff3f1723b203b839bd785c417670abc Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-usb.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index ce6da358228b..388041ddf413 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -42,7 +42,7 @@ resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = @@ -65,7 +65,7 @@ /* nominal vote */ , + MSM_BUS_SLAVE_EBI_CH0 240000 700000>, , , -- GitLab From ef5bd846b57376eaa75dca1a43b1ddfccb1671fc Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 16:27:01 +0530 Subject: [PATCH 0682/1286] ARM: dts: msm: Enable TZ-log driver for trinket Enable TZ-log device node on include file to enable the TZ-log driver on trinket to access TZ diag area. Change-Id: I67802996bd9d5a8c4187ca0d76f2d55e39405d5b Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 4763d3d81928..34c6e7dc2b37 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1601,6 +1601,14 @@ clock-names = "iface_clk"; }; + qcom_tzlog: tz-log@0c125720 { + compatible = "qcom,tz-log"; + reg = <0x0c125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, -- GitLab From 363247d4c3e2ac9cb12f59e5cae680f8ed1e114d Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Mon, 10 Dec 2018 17:05:26 -0700 Subject: [PATCH 0683/1286] net: qualcomm: rmnet: Don't reference skb->data directly In preparation for receiving non-linear SKBs from lower level drivers, don't access skb->data in functions that will be used on the RX path unless we know the SKB is linear. Change-Id: I99429550966d4384d0725b9c72662469a1036552 Signed-off-by: Sean Tranchetti --- .../ethernet/qualcomm/rmnet/rmnet_handlers.c | 18 ++++++++++------- .../net/ethernet/qualcomm/rmnet/rmnet_map.h | 14 +++++++++++++ .../qualcomm/rmnet/rmnet_map_command.c | 16 ++++++++------- .../ethernet/qualcomm/rmnet/rmnet_map_data.c | 20 ++++++++++--------- 4 files changed, 45 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c index e4ed5bd72a7c..4029528dacf1 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c @@ -53,13 +53,15 @@ EXPORT_TRACEPOINT_SYMBOL(rmnet_err); static int rmnet_check_skb_can_gro(struct sk_buff *skb) { + unsigned char *data = rmnet_map_data_ptr(skb); + switch(skb->protocol) { case htons(ETH_P_IP): - if (ip_hdr(skb)->protocol == IPPROTO_TCP) + if (((struct iphdr *)data)->protocol == IPPROTO_TCP) return 0; break; case htons(ETH_P_IPV6): - if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) + if (((struct ipv6hdr *)data)->nexthdr == IPPROTO_TCP) return 0; /* Fall through */ } @@ -69,7 +71,7 @@ static int rmnet_check_skb_can_gro(struct sk_buff *skb) void rmnet_set_skb_proto(struct sk_buff *skb) { - switch (skb->data[0] & 0xF0) { + switch (rmnet_map_data_ptr(skb)[0] & 0xF0) { case RMNET_IP_VERSION_4: skb->protocol = htons(ETH_P_IP); break; @@ -137,11 +139,13 @@ static void __rmnet_map_ingress_handler(struct sk_buff *skb, struct rmnet_port *port) { + struct rmnet_map_header *qmap; struct rmnet_endpoint *ep; u16 len, pad; u8 mux_id; - if (RMNET_MAP_GET_CD_BIT(skb)) { + qmap = (struct rmnet_map_header *)rmnet_map_data_ptr(skb); + if (qmap->cd_bit) { if (port->data_format & RMNET_INGRESS_FORMAT_DL_MARKER) { if (!rmnet_map_flow_command(skb, port, false)) return; @@ -153,9 +157,9 @@ __rmnet_map_ingress_handler(struct sk_buff *skb, goto free_skb; } - mux_id = RMNET_MAP_GET_MUX_ID(skb); - pad = RMNET_MAP_GET_PAD(skb); - len = RMNET_MAP_GET_LENGTH(skb) - pad; + mux_id = qmap->mux_id; + pad = qmap->pad_len; + len = ntohs(qmap->pkt_len) - pad; if (mux_id >= RMNET_MAX_LOGICAL_EP) goto free_skb; diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h index 4e1aa2d4df3b..a8ab489f8e1b 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h @@ -144,6 +144,20 @@ struct rmnet_map_dl_ind { #define RMNET_MAP_NO_PAD_BYTES 0 #define RMNET_MAP_ADD_PAD_BYTES 1 +static inline unsigned char *rmnet_map_data_ptr(struct sk_buff *skb) +{ + return skb->data; +} + +static inline struct rmnet_map_control_command * +rmnet_map_get_cmd_start(struct sk_buff *skb) +{ + unsigned char *data = rmnet_map_data_ptr(skb); + + data += sizeof(struct rmnet_map_header); + return (struct rmnet_map_control_command *)data; +} + struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, struct rmnet_port *port); struct rmnet_map_header *rmnet_map_add_map_header(struct sk_buff *skb, diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c index 0c8318d61d24..28a9ad8981bd 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c @@ -31,6 +31,7 @@ static u8 rmnet_map_do_flow_control(struct sk_buff *skb, struct rmnet_port *port, int enable) { + struct rmnet_map_header *qmap; struct rmnet_map_control_command *cmd; struct rmnet_endpoint *ep; struct net_device *vnd; @@ -40,8 +41,9 @@ static u8 rmnet_map_do_flow_control(struct sk_buff *skb, u8 mux_id; int r; - mux_id = RMNET_MAP_GET_MUX_ID(skb); - cmd = RMNET_MAP_GET_CMD_START(skb); + qmap = (struct rmnet_map_header *)rmnet_map_data_ptr(skb); + mux_id = qmap->mux_id; + cmd = rmnet_map_get_cmd_start(skb); if (mux_id >= RMNET_MAX_LOGICAL_EP) { kfree_skb(skb); @@ -86,7 +88,7 @@ static void rmnet_map_send_ack(struct sk_buff *skb, skb->protocol = htons(ETH_P_MAP); - cmd = RMNET_MAP_GET_CMD_START(skb); + cmd = rmnet_map_get_cmd_start(skb); cmd->cmd_type = type & 0x03; netif_tx_lock(dev); @@ -133,7 +135,7 @@ static void rmnet_map_process_flow_start(struct sk_buff *skb, skb_pull(skb, RMNET_MAP_CMD_SIZE); - dlhdr = (struct rmnet_map_dl_ind_hdr *)skb->data; + dlhdr = (struct rmnet_map_dl_ind_hdr *)rmnet_map_data_ptr(skb); port->stats.dl_hdr_last_seq = dlhdr->le.seq; port->stats.dl_hdr_last_bytes = dlhdr->le.bytes; @@ -166,7 +168,7 @@ static void rmnet_map_process_flow_end(struct sk_buff *skb, skb_pull(skb, RMNET_MAP_CMD_SIZE); - dltrl = (struct rmnet_map_dl_ind_trl *)skb->data; + dltrl = (struct rmnet_map_dl_ind_trl *)rmnet_map_data_ptr(skb); port->stats.dl_trl_last_seq = dltrl->seq_le; port->stats.dl_trl_count++; @@ -192,7 +194,7 @@ void rmnet_map_command(struct sk_buff *skb, struct rmnet_port *port) unsigned char command_name; unsigned char rc = 0; - cmd = RMNET_MAP_GET_CMD_START(skb); + cmd = rmnet_map_get_cmd_start(skb); command_name = cmd->command_name; switch (command_name) { @@ -219,7 +221,7 @@ int rmnet_map_flow_command(struct sk_buff *skb, struct rmnet_port *port, struct rmnet_map_control_command *cmd; unsigned char command_name; - cmd = RMNET_MAP_GET_CMD_START(skb); + cmd = rmnet_map_get_cmd_start(skb); command_name = cmd->command_name; switch (command_name) { diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c index 10dfc46d9285..e156cde4d643 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c @@ -59,14 +59,14 @@ rmnet_map_ipv4_dl_csum_trailer(struct sk_buff *skb, void *txporthdr; __be16 addend; - ip4h = (struct iphdr *)(skb->data); + ip4h = (struct iphdr *)rmnet_map_data_ptr(skb); if ((ntohs(ip4h->frag_off) & IP_MF) || ((ntohs(ip4h->frag_off) & IP_OFFSET) > 0)) { priv->stats.csum_fragmented_pkt++; return -EOPNOTSUPP; } - txporthdr = skb->data + ip4h->ihl * 4; + txporthdr = rmnet_map_data_ptr(skb) + ip4h->ihl * 4; csum_field = rmnet_map_get_csum_field(ip4h->protocol, txporthdr); @@ -130,12 +130,12 @@ rmnet_map_ipv6_dl_csum_trailer(struct sk_buff *skb, u16 csum_value, csum_value_final; __be16 ip6_hdr_csum, addend; struct ipv6hdr *ip6h; - void *txporthdr; + void *txporthdr, *data = rmnet_map_data_ptr(skb); u32 length; - ip6h = (struct ipv6hdr *)(skb->data); + ip6h = data; - txporthdr = skb->data + sizeof(struct ipv6hdr); + txporthdr = data + sizeof(struct ipv6hdr); csum_field = rmnet_map_get_csum_field(ip6h->nexthdr, txporthdr); if (!csum_field) { @@ -146,7 +146,7 @@ rmnet_map_ipv6_dl_csum_trailer(struct sk_buff *skb, csum_value = ~ntohs(csum_trailer->csum_value); ip6_hdr_csum = (__force __be16) ~ntohs((__force __be16)ip_compute_csum(ip6h, - (int)(txporthdr - (void *)(skb->data)))); + (int)(txporthdr - data))); ip6_payload_csum = csum16_sub((__force __sum16)csum_value, ip6_hdr_csum); @@ -319,12 +319,13 @@ struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, { struct rmnet_map_header *maph; struct sk_buff *skbn; + unsigned char *data = rmnet_map_data_ptr(skb); u32 packet_len; if (skb->len == 0) return NULL; - maph = (struct rmnet_map_header *)skb->data; + maph = (struct rmnet_map_header *)data; packet_len = ntohs(maph->pkt_len) + sizeof(struct rmnet_map_header); if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) @@ -343,7 +344,7 @@ struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, skb_reserve(skbn, RMNET_MAP_DEAGGR_HEADROOM); skb_put(skbn, packet_len); - memcpy(skbn->data, skb->data, packet_len); + memcpy(skbn->data, data, packet_len); skb_pull(skb, packet_len); return skbn; @@ -365,7 +366,8 @@ int rmnet_map_checksum_downlink_packet(struct sk_buff *skb, u16 len) return -EOPNOTSUPP; } - csum_trailer = (struct rmnet_map_dl_csum_trailer *)(skb->data + len); + csum_trailer = (struct rmnet_map_dl_csum_trailer *) + (rmnet_map_data_ptr(skb) + len); if (!csum_trailer->valid) { priv->stats.csum_valid_unset++; -- GitLab From 171fcb2fdd24ce453f7a126e979f9c41d8934f0a Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Tue, 11 Dec 2018 13:40:49 -0700 Subject: [PATCH 0684/1286] net: qualcomm: rmnet: Allow nonlinear SKBs on RX path Receive path though the rmnet driver can now handle nonlinear SKBs from the lower level drivers along with the linear SKBs it expected previously. Change-Id: Ibc5bd977e995c2e9a9b0676e41b6008531c379c4 Signed-off-by: Sean Tranchetti --- .../ethernet/qualcomm/rmnet/rmnet_handlers.c | 4 +-- .../net/ethernet/qualcomm/rmnet/rmnet_map.h | 4 +++ .../qualcomm/rmnet/rmnet_map_command.c | 12 ++++---- .../ethernet/qualcomm/rmnet/rmnet_map_data.c | 30 ++++++++++++++----- 4 files changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c index 4029528dacf1..a76423c8d654 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c @@ -171,7 +171,7 @@ __rmnet_map_ingress_handler(struct sk_buff *skb, skb->dev = ep->egress_dev; /* Subtract MAP header */ - skb_pull(skb, sizeof(struct rmnet_map_header)); + pskb_pull(skb, sizeof(struct rmnet_map_header)); rmnet_set_skb_proto(skb); if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) { @@ -182,7 +182,7 @@ __rmnet_map_ingress_handler(struct sk_buff *skb, if (port->data_format & RMNET_INGRESS_FORMAT_PS) qmi_rmnet_work_maybe_restart(port); - skb_trim(skb, len); + pskb_trim(skb, len); rmnet_deliver_skb(skb, port); return; diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h index a8ab489f8e1b..3e8ae2df216d 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h @@ -146,6 +146,10 @@ struct rmnet_map_dl_ind { static inline unsigned char *rmnet_map_data_ptr(struct sk_buff *skb) { + /* Nonlinear packets we receive are entirely within frag 0 */ + if (skb_is_nonlinear(skb) && skb->len == skb->data_len) + return skb_frag_address(skb_shinfo(skb)->frags); + return skb->data; } diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c index 28a9ad8981bd..67a4e1ca508c 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c @@ -83,8 +83,8 @@ static void rmnet_map_send_ack(struct sk_buff *skb, struct net_device *dev = skb->dev; if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) - skb_trim(skb, - skb->len - sizeof(struct rmnet_map_dl_csum_trailer)); + pskb_trim(skb, + skb->len - sizeof(struct rmnet_map_dl_csum_trailer)); skb->protocol = htons(ETH_P_MAP); @@ -133,7 +133,7 @@ static void rmnet_map_process_flow_start(struct sk_buff *skb, if (skb->len < RMNET_DL_IND_HDR_SIZE) return; - skb_pull(skb, RMNET_MAP_CMD_SIZE); + pskb_pull(skb, RMNET_MAP_CMD_SIZE); dlhdr = (struct rmnet_map_dl_ind_hdr *)rmnet_map_data_ptr(skb); @@ -152,7 +152,7 @@ static void rmnet_map_process_flow_start(struct sk_buff *skb, pull_size = sizeof(struct rmnet_map_dl_ind_hdr); if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) pull_size += sizeof(struct rmnet_map_dl_csum_trailer); - skb_pull(skb, pull_size); + pskb_pull(skb, pull_size); } } @@ -166,7 +166,7 @@ static void rmnet_map_process_flow_end(struct sk_buff *skb, if (skb->len < RMNET_DL_IND_TRL_SIZE) return; - skb_pull(skb, RMNET_MAP_CMD_SIZE); + pskb_pull(skb, RMNET_MAP_CMD_SIZE); dltrl = (struct rmnet_map_dl_ind_trl *)rmnet_map_data_ptr(skb); @@ -180,7 +180,7 @@ static void rmnet_map_process_flow_end(struct sk_buff *skb, pull_size = sizeof(struct rmnet_map_dl_ind_trl); if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) pull_size += sizeof(struct rmnet_map_dl_csum_trailer); - skb_pull(skb, pull_size); + pskb_pull(skb, pull_size); } } diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c index e156cde4d643..1229a542571f 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c @@ -338,14 +338,30 @@ struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, if (ntohs(maph->pkt_len) == 0) return NULL; - skbn = alloc_skb(packet_len + RMNET_MAP_DEAGGR_SPACING, GFP_ATOMIC); - if (!skbn) - return NULL; + if (skb_is_nonlinear(skb)) { + skb_frag_t *frag0 = skb_shinfo(skb)->frags; + struct page *page = skb_frag_page(frag0); + + skbn = alloc_skb(RMNET_MAP_DEAGGR_HEADROOM, GFP_ATOMIC); + if (!skbn) + return NULL; + + skb_append_pagefrags(skbn, page, frag0->page_offset, + packet_len); + skbn->data_len += packet_len; + skbn->len += packet_len; + } else { + skbn = alloc_skb(packet_len + RMNET_MAP_DEAGGR_SPACING, + GFP_ATOMIC); + if (!skbn) + return NULL; + + skb_reserve(skbn, RMNET_MAP_DEAGGR_HEADROOM); + skb_put(skbn, packet_len); + memcpy(skbn->data, data, packet_len); + } - skb_reserve(skbn, RMNET_MAP_DEAGGR_HEADROOM); - skb_put(skbn, packet_len); - memcpy(skbn->data, data, packet_len); - skb_pull(skb, packet_len); + pskb_pull(skb, packet_len); return skbn; } -- GitLab From 18179404425dcd1f66396de632800561a4c10353 Mon Sep 17 00:00:00 2001 From: Junzhe Zou Date: Wed, 19 Dec 2018 17:21:51 -0800 Subject: [PATCH 0685/1286] msm: camera: ife: Stop CSID path properly Stop CSID path according to the stop cmd, and poll the stop status together to save time. Change-Id: I254a82c601a6806aee101e77168bd46a4da84481 Signed-off-by: Junzhe Zou --- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 77 ++++++++++++++++++- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 3a3906814f5b..bad6ae25669a 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1809,6 +1809,7 @@ static int cam_ife_csid_disable_pxl_path( enum cam_ife_csid_halt_cmd stop_cmd) { int rc = 0; + uint32_t val = 0; const struct cam_ife_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; struct cam_ife_csid_path_cfg *path_data; @@ -1869,6 +1870,17 @@ static int cam_ife_csid_disable_pxl_path( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_irq_mask_addr); + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { + /* configure Halt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + return rc; } @@ -2120,7 +2132,7 @@ static int cam_ife_csid_disable_rdi_path( enum cam_ife_csid_halt_cmd stop_cmd) { int rc = 0; - uint32_t id; + uint32_t id, val = 0; const struct cam_ife_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; @@ -2165,6 +2177,62 @@ static int cam_ife_csid_disable_rdi_path( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + /* Halt the RDI path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + return rc; +} + +static int cam_ife_csid_poll_stop_status( + struct cam_ife_csid_hw *csid_hw, + uint32_t res_mask) +{ + int rc = 0; + uint32_t csid_status_addr = 0, val = 0, res_id = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + for (; res_id < CAM_IFE_PIX_PATH_RES_MAX; res_id++, res_mask >>= 1) { + if ((res_mask & 0x1) == 0) + continue; + val = 0; + + if (res_id == CAM_IFE_PIX_PATH_RES_IPP) { + csid_status_addr = + csid_reg->ipp_reg->csid_pxl_status_addr; + } else if (res_id == CAM_IFE_PIX_PATH_RES_PPP) { + csid_status_addr = + csid_reg->ppp_reg->csid_pxl_status_addr; + } else { + csid_status_addr = + csid_reg->rdi_reg[res_id]->csid_rdi_status_addr; + } + + CAM_DBG(CAM_ISP, "start polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_status_addr, val, (val & 0x1) == 0x1, + CAM_IFE_CSID_TIMEOUT_SLEEP_US, + CAM_IFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d", + csid_hw->hw_intf->hw_idx, res_id, rc); + rc = -ETIMEDOUT; + break; + } + CAM_DBG(CAM_ISP, "End polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + } + return rc; } @@ -2743,6 +2811,7 @@ static int cam_ife_csid_stop(void *hw_priv, struct cam_isp_resource_node *res; struct cam_csid_hw_stop_args *csid_stop; uint32_t i; + uint32_t res_mask = 0; if (!hw_priv || !stop_args || (arg_size != sizeof(struct cam_csid_hw_stop_args))) { @@ -2774,6 +2843,7 @@ static int cam_ife_csid_stop(void *hw_priv, rc = cam_ife_csid_tpg_stop(csid_hw, res); break; case CAM_ISP_RESOURCE_PIX_PATH: + res_mask |= (1 << res->res_id); if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP || res->res_id == CAM_IFE_PIX_PATH_RES_PPP) rc = cam_ife_csid_disable_pxl_path(csid_hw, @@ -2791,6 +2861,9 @@ static int cam_ife_csid_stop(void *hw_priv, } } + if (!res_mask) + rc = cam_ife_csid_poll_stop_status(csid_hw, res_mask); + for (i = 0; i < csid_stop->num_res; i++) { res = csid_stop->node_res[i]; res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; -- GitLab From 97f9e3139f5ac5e52192932bfc50392b120703cd Mon Sep 17 00:00:00 2001 From: Vikram Panduranga Date: Fri, 7 Dec 2018 12:48:57 -0800 Subject: [PATCH 0686/1286] ARM: dts: msm: add voice_mhi driver entry Add voice_mhi device entry for SM8150+sdxprairie and carveout for mailbox memory used for voice packet exchange. Change-Id: I81d78397ad3352ecc559c83b77ba43eb74b9310a Signed-off-by: Vikram Panduranga --- .../boot/dts/qcom/sm8150-sdxprairie.dtsi | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index e08bfbd1236f..a67a0d62df0d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,3 +45,21 @@ qcom,platform-type = <2>; /* APQ platform */ }; }; + +&reserved_memory { + mailbox_mem: mailbox_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0x20000>; + }; +}; + +&audio_apr { + voice_mhi_audio: qcom,voice-mhi-audio { + compatible = "qcom,voice-mhi-audio"; + memory-region = <&mailbox_mem>; + voice_mhi_voting; + }; +}; -- GitLab From 1951816b1fb3d063166e84ec884d0ccbcb8ef0b3 Mon Sep 17 00:00:00 2001 From: Siddartha Mohanadoss Date: Fri, 4 Jan 2019 13:24:36 -0800 Subject: [PATCH 0687/1286] iio: adc: Fix buffer overflow in adc_configure Update buffer size to avoid buffer overflow when issuing multi byte SPMI reads. Change-Id: I1a5a1b75b8ae9f4db9f79ff5a272f8acfbd099f2 Signed-off-by: Siddartha Mohanadoss --- drivers/iio/adc/qcom-spmi-adc5.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 37c0aef27a63..d8f2801cf9d2 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -457,11 +457,13 @@ static int adc_pre_configure_usb_in_read(struct adc_chip *adc) return adc_write(adc, ADC_USR_CONV_REQ, &data, 1); } +#define ADC5_MULTI_TRANSFER 5 + static int adc_configure(struct adc_chip *adc, struct adc_channel_prop *prop) { int ret; - u8 buf[5]; + u8 buf[ADC5_MULTI_TRANSFER]; u8 conv_req = 0; bool channel_check = false; @@ -470,7 +472,7 @@ static int adc_configure(struct adc_chip *adc, channel_check = true; /* Read registers 0x42 through 0x46 */ - ret = adc_read(adc, ADC_USR_DIG_PARAM, buf, 6); + ret = adc_read(adc, ADC_USR_DIG_PARAM, buf, ADC5_MULTI_TRANSFER); if (ret < 0) return ret; @@ -497,7 +499,7 @@ static int adc_configure(struct adc_chip *adc, if (!adc->poll_eoc) reinit_completion(&adc->complete); - ret = adc_write(adc, ADC_USR_DIG_PARAM, buf, 5); + ret = adc_write(adc, ADC_USR_DIG_PARAM, buf, ADC5_MULTI_TRANSFER); if (ret) return ret; -- GitLab From d8b5ed83ff2fc28037ee5d42becce24e2ad892bf Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Thu, 3 Jan 2019 13:37:08 -0800 Subject: [PATCH 0688/1286] ARM: dts: msm: Enable SMMU stage 1 for WLAN Enable SMMU stage 1 for WLAN on SM8150 as it is able to provide more protection for device illegally access DDR memory as well as more consistent DMA memory for device view. Change-Id: I44d55115a6096380bf4535d3c23b569ef5faf102 Signed-off-by: Yue Ma --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b7bdd1f560aa..1de16bf0edc4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3670,6 +3670,7 @@ pinctrl-1 = <&cnss_wlan_en_sleep>; qcom,wlan-rc-num = <0>; qcom,wlan-ramdump-dynamic = <0x400000>; + qcom,smmu-s1-enable; mhi,max-channels = <30>; mhi,timeout = <10000>; -- GitLab From 857564e46dde5795c896e2761586ff82b27e44e9 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Fri, 4 Jan 2019 16:00:06 -0800 Subject: [PATCH 0689/1286] ARM: msm: dts: Fix mproc interrupts for sdxprairie SMP2P should use SPI interrupt 113 to match the modem side interrupt configuration. AOP QMP should use SPI interrupt 221 for sdxprairie. Change-Id: I2b27a884133bd55ade647d24b3247b5f9f839cf5 Signed-off-by: Chris Lew --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index c0904862c715..9d945a5b8693 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -625,7 +625,7 @@ reg = <0xc310000 0x1000>, <0x17811008 0x4>; reg-names = "msgram", "irq-reg-base"; qcom,irq-mask = <0x1>; - interrupts = ; + interrupts = ; label = "aop"; qcom,early-boot; @@ -660,7 +660,7 @@ qcom,smp2p-modem@1799000c { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; - interrupts = ; + interrupts = ; mboxes = <&apcs_glb 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; -- GitLab From a965aac2808bf4fc4c1bc5261ee7c3a33e5dd935 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Tue, 18 Dec 2018 20:16:06 -0800 Subject: [PATCH 0690/1286] power_supply: add batt_age_level property Add batt_age_level property to support loading multiple profiles based on the battery age level specified by the user. Change-Id: I41e61c615f2d1df988a0de83e4e2dbddd7a36441 Signed-off-by: Subbaraman Narayanamurthy --- drivers/power/supply/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 788795491f8e..5a3e4dc9c66f 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -390,6 +390,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(fg_reset), POWER_SUPPLY_ATTR(qc_opti_disable), POWER_SUPPLY_ATTR(cc_soc), + POWER_SUPPLY_ATTR(batt_age_level), /* Charge pump properties */ POWER_SUPPLY_ATTR(cp_status1), POWER_SUPPLY_ATTR(cp_status2), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index a27310247326..b9da4620a61e 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -321,6 +321,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_FG_RESET, POWER_SUPPLY_PROP_QC_OPTI_DISABLE, POWER_SUPPLY_PROP_CC_SOC, + POWER_SUPPLY_PROP_BATT_AGE_LEVEL, /* Charge pump properties */ POWER_SUPPLY_PROP_CP_STATUS1, POWER_SUPPLY_PROP_CP_STATUS2, -- GitLab From 570376d8e77fdcff33a2f056d39ab3bce7d111a9 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Tue, 18 Dec 2018 19:50:35 -0800 Subject: [PATCH 0691/1286] of: batterydata: Add support to get best battery profile based on age level To support multiple battery profile with same battery id but with different age level, add a function to select best profile based on battery id and age level. Change-Id: I4193529744b1efa342939008de0a9a55b3ca389a Signed-off-by: Subbaraman Narayanamurthy --- .../bindings/batterydata/batterydata.txt | 2 + drivers/of/of_batterydata.c | 79 ++++++++++++++++++- include/linux/of_batterydata.h | 25 +++++- 3 files changed, 103 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/batterydata/batterydata.txt b/Documentation/devicetree/bindings/batterydata/batterydata.txt index 3a0cb0a6b6b4..0cef324b40ab 100644 --- a/Documentation/devicetree/bindings/batterydata/batterydata.txt +++ b/Documentation/devicetree/bindings/batterydata/batterydata.txt @@ -139,6 +139,8 @@ Profile data node optional properties: JEITA conditions (cool/warm). Element 0 - FV value for soft cool. Element 1 - FV value for soft warm. +- qcom,batt-age-level: Battery age level. This is used only when multiple + profile loading is supported. Profile data node required subnodes: - qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes temperature to fcc lookup. The units for this lookup diff --git a/drivers/of/of_batterydata.c b/drivers/of/of_batterydata.c index 43417b2a771d..aa03fdf82bc5 100644 --- a/drivers/of/of_batterydata.c +++ b/drivers/of/of_batterydata.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -398,6 +398,83 @@ struct device_node *of_batterydata_get_best_profile( return best_node; } +struct device_node *of_batterydata_get_best_aged_profile( + const struct device_node *batterydata_container_node, + int batt_id_kohm, int batt_age_level, int *avail_age_level) +{ + struct batt_ids batt_ids; + struct device_node *node, *best_node = NULL; + const char *battery_type = NULL; + int delta = 0, best_id_kohm = 0, id_range_pct, i = 0, rc = 0, limit = 0; + u32 val; + bool in_range = false; + + /* read battery id range percentage for best profile */ + rc = of_property_read_u32(batterydata_container_node, + "qcom,batt-id-range-pct", &id_range_pct); + + if (rc) { + if (rc == -EINVAL) { + id_range_pct = 0; + } else { + pr_err("failed to read battery id range\n"); + return ERR_PTR(-ENXIO); + } + } + + /* + * Find the battery data with a battery id resistor closest to this one + */ + for_each_available_child_of_node(batterydata_container_node, node) { + val = 0; + of_property_read_u32(node, "qcom,batt-age-level", &val); + rc = of_batterydata_read_batt_id_kohm(node, + "qcom,batt-id-kohm", &batt_ids); + if (rc) + continue; + for (i = 0; i < batt_ids.num; i++) { + delta = abs(batt_ids.kohm[i] - batt_id_kohm); + limit = (batt_ids.kohm[i] * id_range_pct) / 100; + in_range = (delta <= limit); + + /* + * Check if the battery aging level matches and the + * limits are in range before selecting the best node. + */ + if ((batt_age_level == val || !best_node) && in_range) { + best_node = node; + best_id_kohm = batt_ids.kohm[i]; + *avail_age_level = val; + break; + } + } + } + + if (best_node == NULL) { + pr_err("No battery data found\n"); + return best_node; + } + + /* check that profile id is in range of the measured batt_id */ + if (abs(best_id_kohm - batt_id_kohm) > + ((best_id_kohm * id_range_pct) / 100)) { + pr_err("out of range: profile id %d batt id %d pct %d", + best_id_kohm, batt_id_kohm, id_range_pct); + return NULL; + } + + rc = of_property_read_string(best_node, "qcom,battery-type", + &battery_type); + if (!rc) + pr_info("%s age level %d found\n", battery_type, + *avail_age_level); + else + pr_info("%s age level %d found\n", best_node->name, + *avail_age_level); + + return best_node; +} + int of_batterydata_read_data(struct device_node *batterydata_container_node, struct bms_battery_data *batt_data, int batt_id_uv) diff --git a/include/linux/of_batterydata.h b/include/linux/of_batterydata.h index 2e847473d368..ada5fd246260 100644 --- a/include/linux/of_batterydata.h +++ b/include/linux/of_batterydata.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2014, 2016-2017 The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2014, 2016-2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,6 +48,21 @@ int of_batterydata_read_data(struct device_node *container_node, struct device_node *of_batterydata_get_best_profile( struct device_node *batterydata_container_node, int batt_id_kohm, const char *batt_type); + +/** + * of_batterydata_get_best_aged_profile() - Find best aged battery profile + * @batterydata_container_node: pointer to the battery-data container device + * node containing the profile nodes. + * @batt_id_kohm: Battery ID in KOhms for which we want to find the profile. + * @batt_age_level: Battery age level. + * @avail_age_level: Available battery age level. + * + * This routine returns a device_node pointer to the closest match battery data + * from device tree based on the battery id reading and age level. + */ +struct device_node *of_batterydata_get_best_aged_profile( + const struct device_node *batterydata_container_node, + int batt_id_kohm, int batt_age_level, int *avail_age_level); #else static inline int of_batterydata_read_data(struct device_node *container_node, struct bms_battery_data *batt_data, @@ -59,6 +74,12 @@ static inline struct device_node *of_batterydata_get_best_profile( struct device_node *batterydata_container_node, int batt_id_kohm, const char *batt_type) { - return -ENXIO; + return NULL; +} +static inline struct device_node *of_batterydata_get_best_aged_profile( + const struct device_node *batterydata_container_node, + int batt_id_kohm, u32 batt_age_level) +{ + return NULL; } #endif /* CONFIG_OF_QPNP */ -- GitLab From 7da24677bc1af59fcd5d7ba61e1b594962f3b190 Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Sun, 30 Dec 2018 12:49:20 +0200 Subject: [PATCH 0692/1286] msm: ipa: Log when embedded TX data sent on APQ platform On APQ platforms, embedded data does not go through IPA. This change logs such TX packets for better debugging. Change-Id: If0d97df6c03a2aaf1b33544e5dc5f16fa1e7f1f2 Signed-off-by: Ghanim Fodi --- drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index 26237654dbe1..5eb90be72f99 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -1106,6 +1106,13 @@ static int ipa3_wwan_xmit(struct sk_buff *skb, struct net_device *dev) bool qmap_check; struct ipa3_wwan_private *wwan_ptr = netdev_priv(dev); + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { + IPAWANERR_RL("IPA embedded data on APQ platform\n"); + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + return NETDEV_TX_OK; + } + if (skb->protocol != htons(ETH_P_MAP)) { IPAWANDBG_LOW ("SW filtering out none QMAP packet received from %s", -- GitLab From e62f1798f624605da3416d3be13c55ca17d59de9 Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Sat, 5 Jan 2019 12:45:32 -0800 Subject: [PATCH 0693/1286] msm: ipa: configure IPA pipes and group resources for IPA4.1 APQ IPA4.1 APQ uses different set of IPA pipes mapping and group resources configuration. This change make these configurations. Change-Id: Ic4b7b3b13767e1e0930972a7a2ebb5446dc3a4ae Signed-off-by: Bojun Pan --- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 35 ++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index fb42c311d6f9..2296eb4a6f6a 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -360,6 +360,19 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, }, + [IPA_4_1_APQ] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { + {1, 63}, {1, 63}, {0, 0}, {1, 63}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = { + {10, 10}, {10, 10}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { + {12, 12}, {14, 14}, {0, 0}, {8, 8}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { + {14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} }, + }, [IPA_4_2] = { /* UL_DL other are invalid */ [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = { @@ -454,6 +467,13 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { {2, 63}, {1, 63}, {1, 2}, {0, 2}, {0, 0}, {0, 0} }, }, + [IPA_4_1_APQ] = { + /* LWA_DL UL/DL/DPL uC, other are invalid */ + [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { + {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} }, + [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { + {2, 63}, {1, 63}, {1, 2}, {0, 2}, {0, 0}, {0, 0} }, + }, [IPA_4_2] = { /* UL/DL/DPL, other are invalid */ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { @@ -514,6 +534,11 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, }, + [IPA_4_1_APQ] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { + {3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} }, + }, [IPA_4_2] = { /* UL_DL, other are invalid */ [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = { @@ -562,6 +587,10 @@ static const u32 ipa3_rsrc_rx_grp_hps_weight_config /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, }, + [IPA_4_1_APQ] = { + /* LWA_DL UL_DL unused UC_RX_Q, other are invalid */ + [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 }, + }, }; enum ipa_ees { @@ -600,6 +629,8 @@ static const struct ipa_qmb_outstanding ipa3_qmb_outstanding [IPA_4_0_MHI][IPA_QMB_INSTANCE_PCIE] = {12, 4}, [IPA_4_1][IPA_QMB_INSTANCE_DDR] = {12, 8}, [IPA_4_1][IPA_QMB_INSTANCE_PCIE] = {12, 4}, + [IPA_4_1_APQ][IPA_QMB_INSTANCE_DDR] = {12, 8}, + [IPA_4_1_APQ][IPA_QMB_INSTANCE_PCIE] = {12, 4}, [IPA_4_2][IPA_QMB_INSTANCE_DDR] = {12, 8}, [IPA_4_5][IPA_QMB_INSTANCE_DDR] = {16, 8}, [IPA_4_5][IPA_QMB_INSTANCE_PCIE] = {12, 8}, @@ -6464,6 +6495,7 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, case IPA_4_0: case IPA_4_0_MHI: case IPA_4_1: + case IPA_4_1_APQ: if (src) { switch (group_index) { case IPA_v4_0_GROUP_LWA_DL: @@ -6721,6 +6753,7 @@ void ipa3_set_resorce_groups_min_max_limits(void) case IPA_4_0: case IPA_4_0_MHI: case IPA_4_1: + case IPA_4_1_APQ: src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX; dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX; src_grp_idx_max = IPA_v4_0_SRC_GROUP_MAX; -- GitLab From 4767972a72ee88a14d355a750c08ff7f9fc07f50 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Thu, 20 Dec 2018 15:42:56 +0800 Subject: [PATCH 0694/1286] tty: serial: msm_geni_serial: Disable manual rts if CRTSCTS is set When CRTSCTS is set, the flow control should be automatic. Change-Id: Ie1f6c8d6fd5bdb2d75ecb24b66dd9334a437cc97 Signed-off-by: Zhiqiang Tu --- drivers/tty/serial/msm_geni_serial.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index a6c4aa183ff7..bf25260f2e72 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1929,6 +1929,13 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, geni_serial_write_term_regs(uport, port->loopback, tx_trans_cfg, tx_parity_cfg, rx_trans_cfg, rx_parity_cfg, bits_per_char, stop_bit_len, ser_clk_cfg); + + if (termios->c_cflag & CRTSCTS) { + geni_write_reg_nolog(0x0, uport->membase, SE_UART_MANUAL_RFR); + IPC_LOG_MSG(port->ipc_log_misc, "%s: Manual flow off\n", + __func__); + } + IPC_LOG_MSG(port->ipc_log_misc, "%s: baud %d\n", __func__, baud); IPC_LOG_MSG(port->ipc_log_misc, "Tx: trans_cfg%d parity %d\n", tx_trans_cfg, tx_parity_cfg); -- GitLab From 580f6802c769046d6a57c8280518b3e3795788e9 Mon Sep 17 00:00:00 2001 From: Hardik Arya Date: Fri, 4 Jan 2019 16:32:18 +0530 Subject: [PATCH 0695/1286] diag: Do not update attribute of sk while closing channel Currently while closing the socket channel we are updating attributes of info->hdl->sk, which is already being done by calling sock release. The patch removes the cleanup of the same from socket channel close. Change-Id: I05c8677c2f96c6437c4ce11153ff18577baed28e Signed-off-by: Hardik Arya --- drivers/char/diag/diagfwd_socket.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/char/diag/diagfwd_socket.c b/drivers/char/diag/diagfwd_socket.c index 5c169df23c66..6423eae07a05 100644 --- a/drivers/char/diag/diagfwd_socket.c +++ b/drivers/char/diag/diagfwd_socket.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -502,7 +502,7 @@ static void __socket_close_channel(struct diag_socket_info *info) { unsigned long flags; - if (!info || !info->hdl) + if (!info) return; memset(&info->remote_addr, 0, sizeof(info->remote_addr)); @@ -513,12 +513,11 @@ static void __socket_close_channel(struct diag_socket_info *info) if (info->port_type == PORT_TYPE_SERVER) return; - write_lock_bh(&info->hdl->sk->sk_callback_lock); - info->hdl->sk->sk_user_data = NULL; - info->hdl->sk->sk_data_ready = NULL; - info->hdl->sk->sk_error_report = NULL; - write_unlock_bh(&info->hdl->sk->sk_callback_lock); mutex_lock(&info->socket_info_mutex); + if (!info->hdl) { + mutex_unlock(&info->socket_info_mutex); + return; + } sock_release(info->hdl); info->hdl = NULL; mutex_unlock(&info->socket_info_mutex); -- GitLab From 3fa4e23c3a159c137aff8df911a17253da0380f9 Mon Sep 17 00:00:00 2001 From: Vishnuvardhan Prodduturi Date: Fri, 4 Jan 2019 14:41:01 +0530 Subject: [PATCH 0696/1286] ARM: dts: msm: Add display support for dual display platform on sdmmagpie Add changes required to enable dual display on sdmmagpie dual display platform. Change-Id: I2d32304f4fd9161cd3d031b3a2d25e7b7de99fc3 Signed-off-by: Vishnuvardhan Prodduturi --- .../qcom/sdmmagpie-dual-display-idp-overlay.dts | 13 +++++++++++-- .../boot/dts/qcom/sdmmagpie-dual-display-idp.dts | 14 +++++++++++++- arch/arm64/boot/dts/qcom/sdmmagpie-idp.dts | 6 +++++- arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi | 4 +++- 4 files changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts b/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts index b86babc11664..ac5362f001d0 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -26,6 +26,15 @@ qcom,board-id = <34 3>; }; -&dsi_sw43404_amoled_video_display { +&dsi_sw43404_amoled_fhd_plus_cmd_display { qcom,dsi-display-active; }; + +&dsi_nt35695b_truly_fhd_cmd_sec_display { + qcom,dsi-display-active; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp.dts b/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp.dts index c0d3869e221e..846be99eec0f 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-dual-display-idp.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,3 +21,15 @@ qcom,board-id = <34 3>; }; +&dsi_sw43404_amoled_fhd_plus_cmd_display { + qcom,dsi-display-active; +}; + +&dsi_nt35695b_truly_fhd_cmd_sec_display { + qcom,dsi-display-active; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dts b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dts index 03c4bc1d9c89..94fe65d40f09 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,3 +20,7 @@ compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; qcom,board-id = <34 0>; }; + +&dsi_sw43404_amoled_video_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi index 26e973dca204..b428a4ddcb38 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -226,6 +226,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; @@ -236,6 +237,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; -- GitLab From bcbb605bcce8ecdec939659fe9dd6575df9ea390 Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 3 Jan 2019 17:08:14 +0530 Subject: [PATCH 0697/1286] ARM64: dts: msm: Add qseecom_ta_mem node for trinket Add qseecom TA pool, which is used for intermittent buffers to load TA on to the TZ apps region. Change-Id: I811c9427f93878ee4c40f0d633b3799aac77f23d Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..7c63db4bfef3 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -484,6 +484,14 @@ reg = <0 0x5e400000 0 0x1400000>; }; + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; -- GitLab From 1d55f7dc6f8cef16787d72553436f5df7b4e6636 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 4 Jan 2019 15:41:40 +0530 Subject: [PATCH 0698/1286] ARM: dts: msm: Disable USB3 on SSRD variants for QCS403 Disable USB3 nodes on SSRD variants for QCS403 target as USB3 is not required to be enabled. Change-Id: Id591b9be2e9cdf82bd5efe9dfb3dee6ffc484e27 Signed-off-by: Vijayavardhan Vennapusa --- arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts | 14 +++++++++++++- arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts | 14 +++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts index 00106edc7655..b9634febf659 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -112,6 +112,18 @@ extcon = <&usb2_extcon>; }; +&usb3 { + status = "disabled"; +}; + +&usb_ss_phy { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + &tlmm { evb_tlmm_gpio_key{ tlmm_gpio_key_active: tlmm_gpio_key_active { diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts index 50c537628de1..77ac0f29bb32 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -89,6 +89,18 @@ status = "ok"; }; +&usb3 { + status = "disabled"; +}; + +&usb_ss_phy { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + &tlmm { evb_tlmm_gpio_key{ tlmm_gpio_key_active: tlmm_gpio_key_active { -- GitLab From ecf60632b7a64529480c18bb9a8f0ffec2f34119 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Mon, 7 Jan 2019 16:38:54 +0800 Subject: [PATCH 0699/1286] coresight: csr: Disable bind/unbind via sysfs Disable bind/unbind via sysfs for csr driver incase of the coresight issue when do driver bind/unbind test. Change-Id: I1de9abbe43b7f76a2290791a2660231666405637 Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-csr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-csr.c b/drivers/hwtracing/coresight/coresight-csr.c index 1637ad234110..51459334ff83 100644 --- a/drivers/hwtracing/coresight/coresight-csr.c +++ b/drivers/hwtracing/coresight/coresight-csr.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2013, 2015-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2013, 2015-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -430,6 +430,7 @@ static struct platform_driver csr_driver = { .name = "coresight-csr", .owner = THIS_MODULE, .of_match_table = csr_match, + .suppress_bind_attrs = true, }, }; -- GitLab From e0ecec31a086aac15fd574a4d7a7577d6a9f895f Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Mon, 7 Jan 2019 12:31:12 +0530 Subject: [PATCH 0700/1286] ARM: dts: msm: Add PWM "num-lpg-channels" property for trinket Add "qcom,num-lpg-channels" property to specify the number of LPG channels for the PWM device. Change-Id: Iccedd22908704baa3baefccb760f19e70688c180 Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index ecabcb3a15d9..963804515b97 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -189,6 +189,7 @@ compatible = "qcom,pwm-lpg"; reg = <0xb300 0x100>; reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; #pwm-cells = <2>; }; }; -- GitLab From 81a7e599e32106c23ce079309ba12ba71f1ea4e8 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Mon, 7 Jan 2019 13:11:51 +0530 Subject: [PATCH 0701/1286] ARM: dts: msm: Add SMPS6 node for trinket Add SMPS6 regulator node for trinket-regulators. So that consumers are able to modify the physical state of the regulator. Change-Id: Ib84663963ed0b30cf353e813981e296081f1ea99 Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/trinket-regulator.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi index 8a6a8f33d258..b9fe073336d2 100644 --- a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -117,6 +117,16 @@ }; + rpm-regulator-smpa6 { + status = "okay"; + S6A: pm6125_s6: regulator-s6 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1424000>; + qcom,init-voltage = <1064000>; + status = "okay"; + }; + }; + rpm-regulator-ldoa1 { status = "okay"; L1A: pm6125_l1: regulator-l1 { -- GitLab From 50c2f64e319683a7d3c6704b4f8b60d0031b85be Mon Sep 17 00:00:00 2001 From: Qiwei Liu Date: Wed, 26 Dec 2018 16:44:48 +0800 Subject: [PATCH 0702/1286] PM / devfreq: fix NULL pointer dereference for freq_table Some devices freq_table is NULL, when show available_frequencies, shouldn't access freq_table if max_state is 0. Change-Id: I58ffaa23c1d27c0fe147c6d4f755244c3f69fbc0 Signed-off-by: Qiwei Liu --- drivers/devfreq/devfreq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index af34cfcaf49e..586691521ec2 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -1200,7 +1200,7 @@ static ssize_t available_frequencies_show(struct device *d, unsigned long freq = 0; use_opp = dev_pm_opp_get_opp_count(dev) > 0; - do { + while (use_opp || (!use_opp && i < max_state)) { if (use_opp) { opp = dev_pm_opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) @@ -1213,7 +1213,7 @@ static ssize_t available_frequencies_show(struct device *d, count += scnprintf(&buf[count], (PAGE_SIZE - count - 2), "%lu ", freq); freq++; - } while (use_opp || (!use_opp && i < max_state)); + } /* Truncate the trailing space */ if (count) -- GitLab From f8cc14ff7c88d78748b2c5e93833d1076dbf0019 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 21 Dec 2018 15:38:02 +0530 Subject: [PATCH 0703/1286] power: smb1355: Fix SMB1355 disable logic For disabling SMB1355, we switch SMB1355 to command control mode. However, by default, command control bit is set to enable SMB1355, resulting in enablement of SMB1355. Fix this by initializing command control bit to disable SMB1355. Change-Id: I290cb980d58ddc0118c24c46433c20a13cad0dab Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/smb1355-charger.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/smb1355-charger.c b/drivers/power/supply/qcom/smb1355-charger.c index 6042249b4660..84a3cdc9d3bb 100644 --- a/drivers/power/supply/qcom/smb1355-charger.c +++ b/drivers/power/supply/qcom/smb1355-charger.c @@ -54,6 +54,9 @@ #define BATT_GT_PRE_TO_FAST_BIT BIT(4) #define ENABLE_CHARGING_BIT BIT(3) +#define CHGR_CHARGING_ENABLE_CMD_REG (CHGR_BASE + 0x42) +#define CHARGING_ENABLE_CMD_BIT BIT(0) + #define CHGR_CFG2_REG (CHGR_BASE + 0x51) #define CHG_EN_SRC_BIT BIT(7) #define CHG_EN_POLARITY_BIT BIT(6) @@ -1039,7 +1042,17 @@ static int smb1355_init_hw(struct smb1355 *chip) return rc; } - /* disable parallel charging path */ + /* + * Disable command based SMB1355 enablement and disable parallel + * charging path by switching to command based mode. + */ + rc = smb1355_masked_write(chip, CHGR_CHARGING_ENABLE_CMD_REG, + CHARGING_ENABLE_CMD_BIT, 0); + if (rc < 0) { + pr_err("Coudln't configure command bit, rc=%d\n", rc); + return rc; + } + rc = smb1355_set_parallel_charging(chip, true); if (rc < 0) { pr_err("Couldn't disable parallel path rc=%d\n", rc); -- GitLab From 73ce650e14a2018947d74c3f4a69315953c80293 Mon Sep 17 00:00:00 2001 From: Manikanta Kanamarlapudi Date: Mon, 7 Jan 2019 15:34:05 +0530 Subject: [PATCH 0704/1286] ARM: dts: msm: Add venus pil node for trinket Add pil node to facilitate VENUS subsystem loading for trinket CRs-Fixed: 2360061 Change-Id: I3a451299136893804378a0626be15ac23440b9f8 Signed-off-by: Manikanta Kanamarlapudi --- arch/arm64/boot/dts/qcom/trinket.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6dfc3968fc7a..70d164f8b0b9 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1707,6 +1707,31 @@ status = "disabled"; }; + + qcom,venus@5ae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; #include "pmi632.dtsi" -- GitLab From 712c0ba1614c02f93412f41a0d25ea9ce7277d64 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Mon, 7 Jan 2019 14:59:46 +0530 Subject: [PATCH 0705/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: I455558f3e3f1293d4e2e8fe89cd1dacca05fcbe9 Signed-off-by: Pavankumar Kondeti --- kernel/sched/boost.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index 8216954b57be..16ea4ef8ee6d 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,12 +45,14 @@ static void boost_kick_cpus(void) if (boost_policy != SCHED_BOOST_ON_BIG) return; + cpus_read_lock(); cpumask_andnot(&kick_mask, cpu_online_mask, cpu_isolated_mask); for_each_cpu(i, &kick_mask) { if (cpu_capacity(i) != max_capacity) boost_kick(i); } + cpus_read_unlock(); } int got_boost_kick(void) -- GitLab From 2a9b37c1b8b91bd1d338afa37a695d28309b726a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 28 Dec 2018 13:42:00 +0530 Subject: [PATCH 0706/1286] ARM: dts: msm: Enable eud clock voting for Trinket Enable eud clock voting for Trinket. This is required to avoid unclocked access to eud registers. Change-Id: I4c7c728e8e26f272133f04c794ca0f0c22aa32ac Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/trinket.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6dfc3968fc7a..d9484e64a873 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -859,6 +859,9 @@ <0x1612000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; status = "ok"; }; -- GitLab From 773a14aba3cda299360ff8c861d1dcc066f5d490 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 28 Dec 2018 13:53:27 +0530 Subject: [PATCH 0707/1286] defconfig: msm: Enable branch predictor hardening on Trinket Enable branch predictor hardening to protect from cache aliasing attacks on Trinket SoC. Change-Id: I1a29baf89a099b7563e32efe793d64066707b67f Signed-off-by: Mukesh Ojha --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 - arch/arm64/configs/vendor/trinket_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a4fde9b73c78..7627bcf916df 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -67,7 +67,6 @@ CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 3f79a597e539..04131a8f710b 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -72,7 +72,6 @@ CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set CONFIG_PRINT_VMEMLAYOUT=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y -- GitLab From f01351b24e5fd9021605ffb80b3e2a1373c341ba Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 4 Jan 2019 14:54:22 -0800 Subject: [PATCH 0708/1286] usb: dwc3: Do not initiate remote wakeup from core layer commit c36d8e947a56a ("usb: dwc3: gadget: put link to U0 before Start Transfer") forcing remote wakeup even if it is not supported by function. In case remote wakeup fails it goes ahead and issues start transfer cmd, which defeats the purpose of the change. Function driver needs to make the decision if device needs to perform remote wakeup or not by calling usb_gadget_wakeup (in HS mode) or usb_func_wakeup (in SS or higher mode). Change-Id: I7ec5a29ae5beb1ea501f4127f440074396db9bda Signed-off-by: Hemant Kumar --- drivers/usb/dwc3/gadget.c | 82 --------------------------------------- 1 file changed, 82 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 2a7a1df1fe1f..756e021d0b6e 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -365,8 +365,6 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) return ret; } -static int __dwc3_gadget_wakeup(struct dwc3 *dwc); - /** * dwc3_send_gadget_ep_cmd - issue an endpoint command * @dep: the endpoint to which the command is going to be issued @@ -405,20 +403,6 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, } } - if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { - int needs_wakeup; - - needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || - dwc->link_state == DWC3_LINK_STATE_U2 || - dwc->link_state == DWC3_LINK_STATE_U3); - - if (unlikely(needs_wakeup)) { - ret = __dwc3_gadget_wakeup(dwc); - dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", - ret); - } - } - dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); @@ -1841,72 +1825,6 @@ static int dwc3_gadget_get_frame(struct usb_gadget *g) return __dwc3_gadget_get_frame(dwc); } -static int __dwc3_gadget_wakeup(struct dwc3 *dwc) -{ - int retries; - - int ret; - u32 reg; - - u8 link_state; - u8 speed; - - /* - * According to the Databook Remote wakeup request should - * be issued only when the device is in early suspend state. - * - * We can check that via USB Link State bits in DSTS register. - */ - reg = dwc3_readl(dwc->regs, DWC3_DSTS); - - speed = reg & DWC3_DSTS_CONNECTSPD; - if ((speed == DWC3_DSTS_SUPERSPEED) || - (speed == DWC3_DSTS_SUPERSPEED_PLUS)) - return 0; - - link_state = DWC3_DSTS_USBLNKST(reg); - - switch (link_state) { - case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ - case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ - break; - default: - return -EINVAL; - } - - ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); - if (ret < 0) { - dev_err(dwc->dev, "failed to put link in Recovery\n"); - return ret; - } - - /* Recent versions do this automatically */ - if (dwc->revision < DWC3_REVISION_194A) { - /* write zeroes to Link Change Request */ - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); - } - - /* poll until Link State changes to ON */ - retries = 20000; - - while (retries--) { - reg = dwc3_readl(dwc->regs, DWC3_DSTS); - - /* in HS, means ON */ - if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) - break; - } - - if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { - dev_err(dwc->dev, "failed to send remote wakeup\n"); - return -EINVAL; - } - - return 0; -} - #define DWC3_PM_RESUME_RETRIES 20 /* Max Number of retries */ #define DWC3_PM_RESUME_DELAY 100 /* 100 msec */ -- GitLab From 69faddf72407e705cf98e7378c62cccee2646cc3 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Mon, 7 Jan 2019 08:25:15 -0800 Subject: [PATCH 0709/1286] defconfig: enabled CONFIG_WATCHDOG_V2 for sdxprairie target Enable defconfig to compile watchdog timer driver to reset the sdxprairie target in case of software fault. Change-Id: I28c36d639544c52948299fbc3020071e5fe61dd0 Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 816e4b5ebbce..2399756ed133 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -320,6 +320,8 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 482b68b65942..784a57a8956c 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -309,6 +309,8 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y @@ -358,6 +360,7 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LIST=y -- GitLab From 94d421ca57a80877ae50219198f3f780618d0633 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Wed, 2 Jan 2019 19:14:06 -0800 Subject: [PATCH 0710/1286] ARM: dts: msm: Add RTB logging dt entry on SDXPRAIRIE Add devicetree entry for initializing RTB logging driver and trace register access which helps during debugging on sdxprairie target. Change-Id: I0d00435817547dc3bc8fd6ffc42f843b1811922c Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 1950591cda86..90d8d3f5c4e8 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -239,6 +239,11 @@ qcom,wakeup-enable; }; + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + keepalive_opp_table: keepalive-opp-table { compatible = "operating-points-v2"; opp-1 { -- GitLab From f38c9278fe208a3b9979f1604ce0c4bba2ba8b0e Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Mon, 7 Jan 2019 08:27:53 -0800 Subject: [PATCH 0711/1286] defconfig: Enable QCOM_RTB config on SDXPRAIRIE target Enable RTB (Register traceback) logging for compiling RTB driver and helpful for debugging from crash logs on SDXPRAIRIE target. Change-Id: I7a90e5e6ff2cc1e891f0f62d60dbe413e5516185 Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 784a57a8956c..485c6bb27c7f 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -369,6 +369,7 @@ CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y # CONFIG_FTRACE is not set # CONFIG_STRICT_DEVMEM is not set CONFIG_DEBUG_USER=y -- GitLab From e93bae2e362b36edddde6106f1a05a166c16e3a4 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Wed, 2 Jan 2019 11:49:37 -0800 Subject: [PATCH 0712/1286] ARM: dts: msm: Add node for mpm sleep counter for sdxprairie Add device node for mpm2 sleep counter which is required for the boot stats KPI reporting on sdxprairie target. Change-Id: Ie89156eeec9539643faa1cc43d48d4fbe5393f94 Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 90d8d3f5c4e8..a9180061cecc 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -221,6 +221,12 @@ }; }; + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + restart@c264000 { compatible = "qcom,pshold"; reg = <0xc264000 0x4>, -- GitLab From 6f71b1bc9edc1e494f09b2097b4ccb79f3bc9629 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Fri, 4 Jan 2019 17:36:46 -0800 Subject: [PATCH 0713/1286] ARM: dts: msm: Do not force warm reboot on sdxprairie target With warm reboot, DDR is not fully initialized and hangs in the early bootloader stage. Remove force warm reboot flag for the device to fully reset in case of reboot. Change-Id: I9b0e4febb7ec31c2e360693cb615045c163206bf Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 1950591cda86..83eb91da81f9 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -226,7 +226,6 @@ reg = <0xc264000 0x4>, <0x1fd3000 0x4>; reg-names = "pshold-base", "tcsr-boot-misc-detect"; - qcom,force-warm-reboot; }; qcom,wdt@17817000 { -- GitLab From be710ede67ae46de5824a0cf66a0653d693f4c8b Mon Sep 17 00:00:00 2001 From: Ahmad Masri Date: Mon, 7 Jan 2019 20:31:41 +0200 Subject: [PATCH 0714/1286] wil6210: prevent device memory access while in reset or suspend Accessing some of the memory of the device while the device is resetting or suspending may cause unexpected error as the HW is still not in a stable state. Prevent this access to guarantee successful read/write memory operations. Change-Id: Ia412d6ae82adb32d957e1bb78d5fa9d644f08581 Signed-off-by: Ahmad Masri Signed-off-by: Maya Erez --- drivers/net/wireless/ath/wil6210/debugfs.c | 28 +++++++++--- drivers/net/wireless/ath/wil6210/main.c | 43 ++++++++++++++----- drivers/net/wireless/ath/wil6210/pm.c | 29 ++++++++----- drivers/net/wireless/ath/wil6210/wil6210.h | 7 ++- .../net/wireless/ath/wil6210/wil_crash_dump.c | 18 +++----- 5 files changed, 84 insertions(+), 41 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c index 250d69228982..a52700a189d4 100644 --- a/drivers/net/wireless/ath/wil6210/debugfs.c +++ b/drivers/net/wireless/ath/wil6210/debugfs.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -280,6 +280,11 @@ static void wil_print_mbox_ring(struct seq_file *s, const char *prefix, wil_halp_vote(wil); + if (wil_mem_access_lock(wil)) { + wil_halp_unvote(wil); + return; + } + wil_memcpy_fromio_32(&r, off, sizeof(r)); wil_mbox_ring_le2cpus(&r); /* @@ -345,6 +350,7 @@ static void wil_print_mbox_ring(struct seq_file *s, const char *prefix, } out: seq_puts(s, "}\n"); + wil_mem_access_unlock(wil); wil_halp_unvote(wil); } @@ -633,6 +639,12 @@ static int wil_memread_debugfs_show(struct seq_file *s, void *data) if (ret < 0) return ret; + ret = wil_mem_access_lock(wil); + if (ret) { + wil_pm_runtime_put(wil); + return ret; + } + a = wmi_buffer(wil, cpu_to_le32(mem_addr)); if (a) @@ -640,6 +652,8 @@ static int wil_memread_debugfs_show(struct seq_file *s, void *data) else seq_printf(s, "[0x%08x] = INVALID\n", mem_addr); + wil_mem_access_unlock(wil); + wil_pm_runtime_put(wil); return 0; @@ -669,10 +683,6 @@ static ssize_t wil_read_file_ioblob(struct file *file, char __user *user_buf, size_t unaligned_bytes, aligned_count, ret; int rc; - if (test_bit(wil_status_suspending, wil_blob->wil->status) || - test_bit(wil_status_suspended, wil_blob->wil->status)) - return 0; - if (pos < 0) return -EINVAL; @@ -699,11 +709,19 @@ static ssize_t wil_read_file_ioblob(struct file *file, char __user *user_buf, return rc; } + rc = wil_mem_access_lock(wil); + if (rc) { + kfree(buf); + wil_pm_runtime_put(wil); + return rc; + } + wil_memcpy_fromio_32(buf, (const void __iomem *) wil_blob->blob.data + aligned_pos, aligned_count); ret = copy_to_user(user_buf, buf + unaligned_bytes, count); + wil_mem_access_unlock(wil); wil_pm_runtime_put(wil); kfree(buf); diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 7a9b6dbf7686..33e42598e15b 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -184,6 +184,28 @@ void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, } } +/* Device memory access is prohibited while reset or suspend. + * wil_mem_access_lock protects accessing device memory in these cases + */ +int wil_mem_access_lock(struct wil6210_priv *wil) +{ + if (!down_read_trylock(&wil->mem_lock)) + return -EBUSY; + + if (test_bit(wil_status_suspending, wil->status) || + test_bit(wil_status_suspended, wil->status)) { + up_read(&wil->mem_lock); + return -EBUSY; + } + + return 0; +} + +void wil_mem_access_unlock(struct wil6210_priv *wil) +{ + up_read(&wil->mem_lock); +} + static void wil_ring_fini_tx(struct wil6210_priv *wil, int id) { struct wil_ring *ring = &wil->ring_tx[id]; @@ -707,6 +729,7 @@ int wil_priv_init(struct wil6210_priv *wil) spin_lock_init(&wil->wmi_ev_lock); spin_lock_init(&wil->net_queue_lock); init_waitqueue_head(&wil->wq); + init_rwsem(&wil->mem_lock); wil->wmi_wq = create_singlethread_workqueue(WIL_NAME "_wmi"); if (!wil->wmi_wq) @@ -1639,15 +1662,6 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) } set_bit(wil_status_resetting, wil->status); - if (test_bit(wil_status_collecting_dumps, wil->status)) { - /* Device collects crash dump, cancel the reset. - * following crash dump collection, reset would take place. - */ - wil_dbg_misc(wil, "reject reset while collecting crash dump\n"); - rc = -EBUSY; - goto out; - } - mutex_lock(&wil->vif_mutex); wil_abort_scan_all_vifs(wil, false); mutex_unlock(&wil->vif_mutex); @@ -1831,7 +1845,9 @@ int __wil_up(struct wil6210_priv *wil) WARN_ON(!mutex_is_locked(&wil->mutex)); + down_write(&wil->mem_lock); rc = wil_reset(wil, true); + up_write(&wil->mem_lock); if (rc) return rc; @@ -1903,6 +1919,7 @@ int wil_up(struct wil6210_priv *wil) int __wil_down(struct wil6210_priv *wil) { + int rc; WARN_ON(!mutex_is_locked(&wil->mutex)); set_bit(wil_status_resetting, wil->status); @@ -1923,7 +1940,11 @@ int __wil_down(struct wil6210_priv *wil) wil_abort_scan_all_vifs(wil, false); mutex_unlock(&wil->vif_mutex); - return wil_reset(wil, false); + down_write(&wil->mem_lock); + rc = wil_reset(wil, false); + up_write(&wil->mem_lock); + + return rc; } int wil_down(struct wil6210_priv *wil) diff --git a/drivers/net/wireless/ath/wil6210/pm.c b/drivers/net/wireless/ath/wil6210/pm.c index 3a4194779ddf..8b33b1391da0 100644 --- a/drivers/net/wireless/ath/wil6210/pm.c +++ b/drivers/net/wireless/ath/wil6210/pm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2014,2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -195,14 +195,18 @@ static int wil_suspend_keep_radio_on(struct wil6210_priv *wil) wil_dbg_pm(wil, "suspend keep radio on\n"); /* Prevent handling of new tx and wmi commands */ - set_bit(wil_status_suspending, wil->status); - if (test_bit(wil_status_collecting_dumps, wil->status)) { - /* Device collects crash dump, cancel the suspend */ - wil_dbg_pm(wil, "reject suspend while collecting crash dump\n"); - clear_bit(wil_status_suspending, wil->status); + rc = down_write_trylock(&wil->mem_lock); + if (!rc) { + wil_err(wil, + "device is busy. down_write_trylock failed, returned (0x%x)\n", + rc); wil->suspend_stats.rejected_by_host++; return -EBUSY; } + + set_bit(wil_status_suspending, wil->status); + up_write(&wil->mem_lock); + wil_pm_stop_all_net_queues(wil); if (!wil_is_tx_idle(wil)) { @@ -311,15 +315,18 @@ static int wil_suspend_radio_off(struct wil6210_priv *wil) wil_dbg_pm(wil, "suspend radio off\n"); - set_bit(wil_status_suspending, wil->status); - if (test_bit(wil_status_collecting_dumps, wil->status)) { - /* Device collects crash dump, cancel the suspend */ - wil_dbg_pm(wil, "reject suspend while collecting crash dump\n"); - clear_bit(wil_status_suspending, wil->status); + rc = down_write_trylock(&wil->mem_lock); + if (!rc) { + wil_err(wil, + "device is busy. down_write_trylock failed, returned (0x%x)\n", + rc); wil->suspend_stats.rejected_by_host++; return -EBUSY; } + set_bit(wil_status_suspending, wil->status); + up_write(&wil->mem_lock); + /* if netif up, hardware is alive, shut it down */ mutex_lock(&wil->vif_mutex); active_ifaces = wil_has_active_ifaces(wil, true, false); diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index 7a254344b1bc..22cddb2f3df4 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -661,7 +661,6 @@ enum { /* for wil6210_priv.status */ wil_status_suspending, /* suspend in progress */ wil_status_suspended, /* suspend completed, device is suspended */ wil_status_resuming, /* resume in progress */ - wil_status_collecting_dumps, /* crashdump collection in progress */ wil_status_last /* keep last */ }; @@ -997,6 +996,8 @@ struct wil6210_priv { struct wil_txrx_ops txrx_ops; struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ + /* for synchronizing device memory access while reset or suspend */ + struct rw_semaphore mem_lock; /* statistics */ atomic_t isr_count_rx, isr_count_tx; /* debugfs */ @@ -1200,6 +1201,8 @@ void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, size_t count); void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, size_t count); +int wil_mem_access_lock(struct wil6210_priv *wil); +void wil_mem_access_unlock(struct wil6210_priv *wil); struct wil6210_vif * wil_vif_alloc(struct wil6210_priv *wil, const char *name, diff --git a/drivers/net/wireless/ath/wil6210/wil_crash_dump.c b/drivers/net/wireless/ath/wil6210/wil_crash_dump.c index dc33a0b4c3fa..772cb00c2002 100644 --- a/drivers/net/wireless/ath/wil6210/wil_crash_dump.c +++ b/drivers/net/wireless/ath/wil6210/wil_crash_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015,2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -57,7 +57,7 @@ static int wil_fw_get_crash_dump_bounds(struct wil6210_priv *wil, int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size) { - int i; + int i, rc; const struct fw_map *map; void *data; u32 host_min, dump_size, offset, len; @@ -73,14 +73,9 @@ int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size) return -EINVAL; } - set_bit(wil_status_collecting_dumps, wil->status); - if (test_bit(wil_status_suspending, wil->status) || - test_bit(wil_status_suspended, wil->status) || - test_bit(wil_status_resetting, wil->status)) { - wil_err(wil, "cannot collect fw dump during suspend/reset\n"); - clear_bit(wil_status_collecting_dumps, wil->status); - return -EINVAL; - } + rc = wil_mem_access_lock(wil); + if (rc) + return rc; /* copy to crash dump area */ for (i = 0; i < ARRAY_SIZE(fw_mapping); i++) { @@ -100,8 +95,7 @@ int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size) wil_memcpy_fromio_32((void * __force)(dest + offset), (const void __iomem * __force)data, len); } - - clear_bit(wil_status_collecting_dumps, wil->status); + wil_mem_access_unlock(wil); return 0; } -- GitLab From 8d076ce7ea7e26ff4e09c7831a6163fa3b84b4a3 Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Mon, 7 Jan 2019 20:32:25 +0200 Subject: [PATCH 0715/1286] msm_11ad: free old pci state before re-allocating pci_store_saved_state allocates pci state, hence the old state we saved needs to be released. Change-Id: I9c7cf43f375b4581bf9f3950d8a790b754589d81 Signed-off-by: Maya Erez --- drivers/platform/msm/msm_11ad/msm_11ad.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/msm_11ad/msm_11ad.c b/drivers/platform/msm/msm_11ad/msm_11ad.c index b8ddb58bceae..bd9d2e5cc052 100644 --- a/drivers/platform/msm/msm_11ad/msm_11ad.c +++ b/drivers/platform/msm/msm_11ad/msm_11ad.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -569,11 +569,13 @@ static int msm_11ad_suspend_power_off(void *handle) pcidev = ctx->pcidev; + /* free the old saved state and save the latest state */ rc = pci_save_state(pcidev); if (rc) { dev_err(ctx->dev, "pci_save_state failed :%d\n", rc); goto out; } + kfree(ctx->pristine_state); ctx->pristine_state = pci_store_saved_state(pcidev); rc = msm_pcie_pm_control(MSM_PCIE_SUSPEND, pcidev->bus->number, @@ -610,6 +612,7 @@ static int ops_suspend(void *handle, bool keep_device_power) dev_dbg(ctx->dev, "disable device and save config\n"); pci_disable_device(pcidev); pci_save_state(pcidev); + kfree(ctx->pristine_state); ctx->pristine_state = pci_store_saved_state(pcidev); dev_dbg(ctx->dev, "moving to D3\n"); pci_set_power_state(pcidev, PCI_D3hot); -- GitLab From 09d4e133ca190cc9535b5bb97347194fa589a7dc Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Fri, 4 Jan 2019 11:33:46 -0800 Subject: [PATCH 0716/1286] ARM: dts: msm: Add support for AQC platform on SDXPRAIRIE Add new device tree files for supporting AQC platform on SDXPRAIRIE target. Change-Id: I654a7219ca93dbfe28168830014e1533e25ede8b Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/Makefile | 3 ++- .../boot/dts/qcom/sdxprairie-mtp-aqc.dts | 27 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-mtp-aqc.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ce950caab349..60a7eb7be2a9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -206,7 +206,8 @@ dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ sdxprairie-cdp.dtb \ sdxprairie-mtp.dtb \ sdxprairie-cdp-256.dtb \ - sdxprairie-mtp-256.dtb + sdxprairie-mtp-256.dtb \ + sdxprairie-mtp-aqc.dtb ifeq ($(CONFIG_ARM64),y) always := $(dtb-y) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-mtp-aqc.dts b/arch/arm64/boot/dts/qcom/sdxprairie-mtp-aqc.dts new file mode 100644 index 000000000000..4f8f76fa5812 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-mtp-aqc.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP(AQC)"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x1010008 0x0>; +}; + +&qnand_1 { + status = "ok"; +}; -- GitLab From 86b89e3b7a1decb1769c0af555d12c6d494f01a4 Mon Sep 17 00:00:00 2001 From: Zhen Kong Date: Mon, 7 Jan 2019 11:22:56 -0800 Subject: [PATCH 0717/1286] firmware: qcom: change to use scnprintf in tz_log driver Change to use scnprintf as it returns the actual size written to the buffer. Change-Id: Idcd92a5dff75c3d42ba05377875c8272094e134e Signed-off-by: Zhen Kong --- drivers/firmware/qcom/tz_log.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/firmware/qcom/tz_log.c b/drivers/firmware/qcom/tz_log.c index fefa8ce3644e..55444788ba50 100644 --- a/drivers/firmware/qcom/tz_log.c +++ b/drivers/firmware/qcom/tz_log.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -336,7 +336,7 @@ static int _disp_tz_general_stats(void) { int len = 0; - len += snprintf(tzdbg.disp_buf + len, debug_rw_buf_size - 1, + len += scnprintf(tzdbg.disp_buf + len, debug_rw_buf_size - 1, " Version : 0x%x\n" " Magic Number : 0x%x\n" " Number of CPU : %d\n", @@ -361,7 +361,7 @@ static int _disp_tz_vmid_stats(void) for (i = 0; i < num_vmid; i++) { if (ptr->vmid < 0xFF) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " 0x%x %s\n", (uint32_t)ptr->vmid, (uint8_t *)ptr->desc); @@ -396,7 +396,7 @@ static int _disp_tz_boot_stats(void) for (i = 0; i < tzdbg.diag_buf->cpu_count; i++) { if (tzdbg.tz_version >= QSEE_VERSION_TZ_3_X) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " CPU #: %d\n" " Warmboot jump address : 0x%llx\n" @@ -423,7 +423,7 @@ static int _disp_tz_boot_stats(void) } ptr_64++; } else { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " CPU #: %d\n" " Warmboot jump address : 0x%x\n" @@ -459,7 +459,7 @@ static int _disp_tz_reset_stats(void) tzdbg.diag_buf->reset_info_off); for (i = 0; i < tzdbg.diag_buf->cpu_count; i++) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " CPU #: %d\n" " Reset Type (reason) : 0x%x\n" @@ -497,7 +497,7 @@ static int _disp_tz_interrupt_stats(void) if (tzdbg.tz_version < QSEE_VERSION_TZ_4_X) { tzdbg_ptr = ptr; for (i = 0; i < (*num_int); i++) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " Interrupt Number : 0x%x\n" " Type of Interrupt : 0x%x\n" @@ -506,13 +506,13 @@ static int _disp_tz_interrupt_stats(void) (uint32_t)tzdbg_ptr->int_info, (uint8_t *)tzdbg_ptr->int_desc); for (j = 0; j < tzdbg.diag_buf->cpu_count; j++) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " int_count on CPU # %d : %u\n", (uint32_t)j, (uint32_t)tzdbg_ptr->int_count[j]); } - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, debug_rw_buf_size - 1, "\n"); if (len > (debug_rw_buf_size - 1)) { @@ -525,7 +525,7 @@ static int _disp_tz_interrupt_stats(void) } else { tzdbg_ptr_tz40 = ptr; for (i = 0; i < (*num_int); i++) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " Interrupt Number : 0x%x\n" " Type of Interrupt : 0x%x\n" @@ -534,13 +534,13 @@ static int _disp_tz_interrupt_stats(void) (uint32_t)tzdbg_ptr_tz40->int_info, (uint8_t *)tzdbg_ptr_tz40->int_desc); for (j = 0; j < tzdbg.diag_buf->cpu_count; j++) { - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, (debug_rw_buf_size - 1) - len, " int_count on CPU # %d : %u\n", (uint32_t)j, (uint32_t)tzdbg_ptr_tz40->int_count[j]); } - len += snprintf(tzdbg.disp_buf + len, + len += scnprintf(tzdbg.disp_buf + len, debug_rw_buf_size - 1, "\n"); if (len > (debug_rw_buf_size - 1)) { @@ -563,7 +563,7 @@ static int _disp_tz_log_stats_legacy(void) ptr = (unsigned char *)tzdbg.diag_buf + tzdbg.diag_buf->ring_off; - len += snprintf(tzdbg.disp_buf, (debug_rw_buf_size - 1) - len, + len += scnprintf(tzdbg.disp_buf, (debug_rw_buf_size - 1) - len, "%s\n", ptr); tzdbg.stat[TZDBG_LOG].data = tzdbg.disp_buf; @@ -753,7 +753,7 @@ static int _disp_hyp_general_stats(size_t count) int i; struct hypdbg_boot_info_t *ptr = NULL; - len += snprintf((unsigned char *)tzdbg.disp_buf + len, + len += scnprintf((unsigned char *)tzdbg.disp_buf + len, tzdbg.hyp_debug_rw_buf_size - 1, " Magic Number : 0x%x\n" " CPU Count : 0x%x\n" @@ -764,7 +764,7 @@ static int _disp_hyp_general_stats(size_t count) ptr = tzdbg.hyp_diag_buf->boot_info; for (i = 0; i < tzdbg.hyp_diag_buf->cpu_count; i++) { - len += snprintf((unsigned char *)tzdbg.disp_buf + len, + len += scnprintf((unsigned char *)tzdbg.disp_buf + len, (tzdbg.hyp_debug_rw_buf_size - 1) - len, " CPU #: %d\n" " Warmboot entry CPU counter: 0x%x\n" -- GitLab From 9c3493278ddf6ee05484741978fcaadba213827c Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 3 Jan 2019 19:09:15 -0800 Subject: [PATCH 0718/1286] regulator: qpnp-amoled: Update AOD mode configuration As per the hardware recommendation, apply the AOD configuration only when the display driver requests for AOD exit and then apply the normal configuration 10 ms after SWIRE is high. Also, update the pulse skip threshold for AOD mode along with the maximum time to poll for VREG_OK to 100 ms. Change-Id: I3dd944b97da550c12f0e3a8731c7058182e8ae95 Signed-off-by: Subbaraman Narayanamurthy --- drivers/regulator/qpnp-amoled-regulator.c | 67 ++++++++++++++--------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/drivers/regulator/qpnp-amoled-regulator.c b/drivers/regulator/qpnp-amoled-regulator.c index 4b5edc780a24..69ffeffe30e9 100644 --- a/drivers/regulator/qpnp-amoled-regulator.c +++ b/drivers/regulator/qpnp-amoled-regulator.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -208,7 +208,7 @@ static int qpnp_ab_ibb_regulator_get_voltage(struct regulator_dev *rdev) return 0; } -#define AB_VREG_OK_POLL_TRIES 25 +#define AB_VREG_OK_POLL_TRIES 50 static int qpnp_ab_poll_vreg_ok(struct qpnp_amoled *chip, bool status) { u32 i = AB_VREG_OK_POLL_TRIES, poll_us = 2000; @@ -238,11 +238,39 @@ static int qpnp_ab_poll_vreg_ok(struct qpnp_amoled *chip, bool status) return -ETIMEDOUT; } +static int qpnp_ibb_aod_config(struct qpnp_amoled *chip, bool aod) +{ + int rc; + u8 ps_ctl, smart_ps_ctl, nlimit_dac; + + pr_debug("aod: %d\n", aod); + if (aod) { + ps_ctl = 0x82; + smart_ps_ctl = 0; + nlimit_dac = 0; + } else { + ps_ctl = 0x02; + smart_ps_ctl = 0x80; + nlimit_dac = 0x3; + } + + rc = qpnp_amoled_write(chip, IBB_SMART_PS_CTL(chip), &smart_ps_ctl, 1); + if (rc < 0) + return rc; + + rc = qpnp_amoled_write(chip, IBB_NLIMIT_DAC(chip), &nlimit_dac, 1); + if (rc < 0) + return rc; + + rc = qpnp_amoled_write(chip, IBB_PS_CTL(chip), &ps_ctl, 1); + return rc; +} + static void qpnp_amoled_aod_work(struct work_struct *work) { struct qpnp_amoled *chip = container_of(work, struct qpnp_amoled, aod_work); - u8 ps_ctl, smart_ps_ctl, nlimit_dac, val; + u8 val = 0; unsigned int mode; int rc; @@ -252,6 +280,10 @@ static void qpnp_amoled_aod_work(struct work_struct *work) pr_debug("mode: %d\n", mode); if (mode == REGULATOR_MODE_NORMAL) { + rc = qpnp_ibb_aod_config(chip, true); + if (rc < 0) + goto error; + /* poll for VREG_OK high */ rc = qpnp_ab_poll_vreg_ok(chip, true); if (rc < 0) @@ -265,40 +297,23 @@ static void qpnp_amoled_aod_work(struct work_struct *work) usleep_range(10000, 10001); - ps_ctl = 0x02; - smart_ps_ctl = 0x80; - nlimit_dac = 0x3; - val = 0; + rc = qpnp_ibb_aod_config(chip, false); + if (rc < 0) + goto error; } else if (mode == REGULATOR_MODE_IDLE) { /* poll for VREG_OK low */ rc = qpnp_ab_poll_vreg_ok(chip, false); if (rc < 0) goto error; - ps_ctl = 0x84; - smart_ps_ctl = 0; - nlimit_dac = 0; val = 0xF1; } else if (mode == REGULATOR_MODE_STANDBY) { /* Restore the normal configuration without any delay */ - ps_ctl = 0x02; - smart_ps_ctl = 0x80; - nlimit_dac = 0x3; - val = 0; + rc = qpnp_ibb_aod_config(chip, false); + if (rc < 0) + goto error; } - rc = qpnp_amoled_write(chip, IBB_SMART_PS_CTL(chip), &smart_ps_ctl, 1); - if (rc < 0) - goto error; - - rc = qpnp_amoled_write(chip, IBB_NLIMIT_DAC(chip), &nlimit_dac, 1); - if (rc < 0) - goto error; - - rc = qpnp_amoled_write(chip, IBB_PS_CTL(chip), &ps_ctl, 1); - if (rc < 0) - goto error; - rc = qpnp_amoled_write(chip, AB_LDO_SW_DBG_CTL(chip), &val, 1); error: if (rc < 0) -- GitLab From 5935e3aad7dc2808911e2c32c0410a59579fd880 Mon Sep 17 00:00:00 2001 From: Mukund Atre Date: Fri, 14 Dec 2018 18:01:26 -0800 Subject: [PATCH 0719/1286] msm: camera: flash: Validate led count in flash packet parser Add upper bound on count of leds in flash packet parser. Change-Id: I646bc92caa660e146feabdf161a178171f146115 Signed-off-by: Mukund Atre --- .../cam_flash/cam_flash_core.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c index bf0e7e9bb70f..842e7e841153 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1374,6 +1374,18 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) flash_operation_info = (struct cam_flash_set_on_off *) cmd_buf; + if (!flash_operation_info) { + CAM_ERR(CAM_FLASH, + "flash_operation_info Null"); + rc = -EINVAL; + goto rel_cmd_buf; + } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + goto rel_cmd_buf; + } fctrl->nrt_info.cmn_attr.count = flash_operation_info->count; fctrl->nrt_info.cmn_attr.request_id = 0; @@ -1462,6 +1474,12 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = -EINVAL; goto rel_cmd_buf; } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + goto rel_cmd_buf; + } flash_data->opcode = flash_operation_info->opcode; flash_data->cmn_attr.count = @@ -1505,6 +1523,19 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_DBG(CAM_FLASH, "Widget Flash Operation"); flash_operation_info = (struct cam_flash_set_on_off *) cmd_buf; + if (!flash_operation_info) { + CAM_ERR(CAM_FLASH, + "flash_operation_info Null"); + rc = -EINVAL; + goto rel_cmd_buf; + } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + goto rel_cmd_buf; + } + fctrl->nrt_info.cmn_attr.count = flash_operation_info->count; fctrl->nrt_info.cmn_attr.request_id = 0; @@ -1553,6 +1584,19 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) case CAMERA_SENSOR_FLASH_CMD_TYPE_RER: { rc = 0; flash_rer_info = (struct cam_flash_set_rer *)cmd_buf; + if (!flash_rer_info) { + CAM_ERR(CAM_FLASH, + "flash_rer_info Null"); + rc = -EINVAL; + goto rel_cmd_buf; + } + if (flash_rer_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + goto rel_cmd_buf; + } + fctrl->nrt_info.cmn_attr.cmd_type = CAMERA_SENSOR_FLASH_CMD_TYPE_RER; fctrl->nrt_info.opcode = flash_rer_info->opcode; -- GitLab From f5a9334117e76eb52eccee442afd0d4fe81e7004 Mon Sep 17 00:00:00 2001 From: Liam Mark Date: Mon, 7 Jan 2019 12:07:25 -0800 Subject: [PATCH 0720/1286] ion: ensure prefetch/drain requests are processed in order Currently when there is an ION prefetch or drain request we are adding them to the start of the prefetch_list list. This can cause the requests to be processed in the wrong order, for example if there is a prefetch request made followed by a drain request (before the prefetch request has been processed) the the drain request will be handled first. Ensure prefetch and drain requests are processed in order by appending requests to the end of the prefetch_list list Change-Id: I935a0d69a52267e888e9b19e1e8c0d9bd68e295b Signed-off-by: Liam Mark --- drivers/staging/android/ion/ion_system_secure_heap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/android/ion/ion_system_secure_heap.c b/drivers/staging/android/ion/ion_system_secure_heap.c index e000f8c665f6..2a6e2e143da6 100644 --- a/drivers/staging/android/ion/ion_system_secure_heap.c +++ b/drivers/staging/android/ion/ion_system_secure_heap.c @@ -1,6 +1,6 @@ /* * - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -285,7 +285,7 @@ static int __ion_system_secure_heap_resize(struct ion_heap *heap, void *ptr, spin_unlock_irqrestore(&secure_heap->work_lock, flags); goto out_free; } - list_splice_init(&items, &secure_heap->prefetch_list); + list_splice_tail_init(&items, &secure_heap->prefetch_list); queue_delayed_work(system_unbound_wq, &secure_heap->prefetch_work, shrink ? msecs_to_jiffies(SHRINK_DELAY) : 0); spin_unlock_irqrestore(&secure_heap->work_lock, flags); -- GitLab From c96348500ed0524dccb72497e856f2dd69eba263 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Tue, 30 Oct 2018 15:54:40 -0700 Subject: [PATCH 0721/1286] cnss2: Add support to handle new MHI status events Handle new MHI status events regarding device error properly. Change-Id: I13607414124593836b0bbb4e3428c78162136e1a Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/pci.c | 56 +++++++++++++++++++++++++++++--- drivers/net/wireless/cnss2/pci.h | 1 + 2 files changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index 057d16159498..9e433796de3e 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -50,6 +50,7 @@ #define WAKE_MSI_NAME "WAKE" #define FW_ASSERT_TIMEOUT 5000 +#define DEV_RDDM_TIMEOUT 5000 #ifdef CONFIG_CNSS_EMULATION #define EMULATION_HW 1 @@ -2027,6 +2028,34 @@ void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv) plat_priv->ramdump_info_v2.dump_data_valid = false; } +static char *cnss_mhi_notify_status_to_str(enum MHI_CB status) +{ + switch (status) { + case MHI_CB_IDLE: + return "IDLE"; + case MHI_CB_EE_RDDM: + return "RDDM"; + case MHI_CB_SYS_ERROR: + return "SYS_ERROR"; + case MHI_CB_FATAL_ERROR: + return "FATAL_ERROR"; + default: + return "UNKNOWN"; + } +}; + +static void cnss_dev_rddm_timeout_hdlr(unsigned long data) +{ + struct cnss_pci_data *pci_priv = (struct cnss_pci_data *)data; + + if (!pci_priv) + return; + + cnss_pr_err("Timeout waiting for RDDM notification\n"); + + cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT); +} + static int cnss_mhi_link_status(struct mhi_controller *mhi_ctrl, void *priv) { struct cnss_pci_data *pci_priv = priv; @@ -2061,7 +2090,8 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl, void *priv, plat_priv = pci_priv->plat_priv; - cnss_pr_dbg("MHI status cb is called with reason %d\n", reason); + cnss_pr_dbg("MHI status cb is called with reason %s(%d)\n", + cnss_mhi_notify_status_to_str(reason), reason); if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state)) { cnss_pr_dbg("Driver unload is in progress, ignore device error\n"); @@ -2069,7 +2099,23 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl, void *priv, } switch (reason) { + case MHI_CB_IDLE: + return; + case MHI_CB_FATAL_ERROR: + set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + del_timer(&plat_priv->fw_boot_timer); + cnss_pci_update_status(pci_priv, CNSS_FW_DOWN); + cnss_reason = CNSS_REASON_DEFAULT; + break; + case MHI_CB_SYS_ERROR: + set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + del_timer(&plat_priv->fw_boot_timer); + mod_timer(&pci_priv->dev_rddm_timer, + jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT)); + cnss_pci_update_status(pci_priv, CNSS_FW_DOWN); + return; case MHI_CB_EE_RDDM: + del_timer(&pci_priv->dev_rddm_timer); cnss_reason = CNSS_REASON_RDDM; break; default: @@ -2077,9 +2123,6 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl, void *priv, return; } - set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); - del_timer(&plat_priv->fw_boot_timer); - cnss_schedule_recovery(&pci_priv->pci_dev->dev, cnss_reason); } @@ -2492,6 +2535,10 @@ static int cnss_pci_probe(struct pci_dev *pci_dev, break; case QCA6290_DEVICE_ID: case QCA6390_DEVICE_ID: + setup_timer(&pci_priv->dev_rddm_timer, + cnss_dev_rddm_timeout_hdlr, + (unsigned long)pci_priv); + ret = cnss_pci_enable_msi(pci_priv); if (ret) goto disable_bus; @@ -2548,6 +2595,7 @@ static void cnss_pci_remove(struct pci_dev *pci_dev) case QCA6390_DEVICE_ID: cnss_pci_unregister_mhi(pci_priv); cnss_pci_disable_msi(pci_priv); + del_timer(&pci_priv->dev_rddm_timer); break; default: break; diff --git a/drivers/net/wireless/cnss2/pci.h b/drivers/net/wireless/cnss2/pci.h index bbd80dac1858..425f41a6ec87 100644 --- a/drivers/net/wireless/cnss2/pci.h +++ b/drivers/net/wireless/cnss2/pci.h @@ -71,6 +71,7 @@ struct cnss_pci_data { u32 msi_ep_base_data; struct mhi_controller *mhi_ctrl; unsigned long mhi_state; + struct timer_list dev_rddm_timer; bool disable_pc; }; -- GitLab From 2ef739037c73574b52bb05e26d2f07e89b7a030c Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Mon, 7 Jan 2019 08:32:20 -0800 Subject: [PATCH 0722/1286] defconfig: Enable more debug configs on SDXPRAIRIE target - FREELIST_RANDOM to control the state of the heap and reduce risk surface. - DEBUG_CREDENTIALS to debugging of credential management. - Enable config to trigger panic on data corruption. - Enable Panic on Recursive fault. - Enable GPIO debugfs. Change-Id: Ie5bcedbb875fda6396d133117bd12b5d0e4da4b5 Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 3 +++ arch/arm/configs/vendor/sdxprairie_defconfig | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 2399756ed133..06757e3b2072 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -21,6 +21,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y # CONFIG_SLUB_DEBUG is not set +CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_STRONG=y CONFIG_MODULES=y @@ -220,6 +221,7 @@ CONFIG_SPMI=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDXPRAIRIE=y CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y @@ -360,6 +362,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y CONFIG_PANIC_TIMEOUT=5 # CONFIG_SCHED_DEBUG is not set CONFIG_SCHEDSTATS=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 485c6bb27c7f..ea92f25481b0 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -21,6 +21,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y +CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_STRONG=y CONFIG_MODULES=y @@ -209,6 +210,7 @@ CONFIG_SLIMBUS=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDXPRAIRIE=y CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y @@ -357,6 +359,7 @@ CONFIG_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y CONFIG_DEBUG_SPINLOCK=y @@ -364,6 +367,7 @@ CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_CREDENTIALS=y CONFIG_FAULT_INJECTION=y CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAULT_INJECTION_DEBUG_FS=y @@ -371,12 +375,14 @@ CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_IPC_LOGGING=y CONFIG_QCOM_RTB=y # CONFIG_FTRACE is not set +CONFIG_PANIC_ON_DATA_CORRUPTION=y # CONFIG_STRICT_DEVMEM is not set CONFIG_DEBUG_USER=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_PAGESPAN=y CONFIG_SECURITY_SELINUX=y # CONFIG_SECURITY_SELINUX_AVC_STATS is not set CONFIG_CRYPTO_CMAC=y -- GitLab From cab95abc3eab957b92faf9cd260862b305dce329 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 7 Jan 2019 13:37:48 +0530 Subject: [PATCH 0723/1286] ARM: dts: msm: enable ulps feature for sm6150 platform Enable ulps feature for td4328 command mode panel on sm6150 platform. Change-Id: I58c956bbb45fc5f470f033e3e1aae4623e314258 Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm6150-sde.dtsi | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi index 1e34fbaf7549..83a9ead4c847 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -389,6 +389,7 @@ &dsi_td4328_truly_cmd { qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x32>; + qcom,ulps-enabled; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi index 73247d3f46a9..a0eee26dd2b0 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -421,8 +421,9 @@ compatible = "qcom,dsi-phy-v2.0"; label = "dsi-phy-0"; cell-index = <0>; - reg = <0xae94400 0x588>; - reg-names = "dsi_phy"; + reg = <0xae94400 0x588>, + <0xae01400 0x100>; + reg-names = "dsi_phy", "phy_clamp_base"; vdda-0p9-supply = <&pm6150_l4>; qcom,platform-strength-ctrl = [ff 06 ff 06 -- GitLab From eb74a947fc9a170d2f022faf86155b06340a4664 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Mon, 7 Jan 2019 20:10:23 -0800 Subject: [PATCH 0724/1286] power: qpnp-fg-gen4: schedule pl_current_en_work conditionally Currently, pl_current_en_work is scheduled whenever the status change work runs which is based on the notifications from other power supplies. Also, it is made to run 1 second after enabling mem_attn interrupt if it is disabled. This is to ensure that parallel current summing configuration is made at the right instant as per the hardware recommendation. If a work is pending already mostly scheduling after enabling mem_attn interrupt, do not schedule another work. This way, a possible race condition can be avoided when changing parallel current summing configuration. Also, schedule the work only if parallel charger is available as it is not required when charge pump is paired with the main charger. Change-Id: I66b767b26a2876884ba0d4b015311bd4dd090a3e Signed-off-by: Subbaraman Narayanamurthy --- drivers/power/supply/qcom/qpnp-fg-gen4.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index e0bc018a0e59..02d5a4d5e6bf 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -3220,7 +3220,9 @@ static void status_change_work(struct work_struct *work) if (rc < 0) pr_err("Error in adjusting FCC for ESR, rc=%d\n", rc); - schedule_delayed_work(&chip->pl_current_en_work, 0); + if (is_parallel_charger_available(fg) && + !delayed_work_pending(&chip->pl_current_en_work)) + schedule_delayed_work(&chip->pl_current_en_work, 0); ttf_update(chip->ttf, input_present); fg->prev_charge_status = fg->charge_status; -- GitLab From 139aa9844d4b702e7a3bfaf2d63c0d0cf2d1bc57 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 8 Feb 2018 09:54:14 +0530 Subject: [PATCH 0725/1286] irqchip: qcom: pdc: Correct irq_data argument for irq_set_irqchip_state GIC-v2 driver gets base address from irq_data in gic_poke_irq. Passing current irq_data to irq_set_irqchip_state can result in NULL pointer dereference. This issue is not seen on GIC-v3 driver since base address is calculated from global variable. Correctly pass parent_data as argument to irq_set_irqchip_state and irq_get_irqchip_state. Change-Id: Ie63561e002b0e0c1cb2404a20fa3d7151cf0b48a Signed-off-by: Maulik Shah --- drivers/irqchip/qcom/pdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom/pdc.c b/drivers/irqchip/qcom/pdc.c index f7284bdaf87a..f4e9799fa4f5 100644 --- a/drivers/irqchip/qcom/pdc.c +++ b/drivers/irqchip/qcom/pdc.c @@ -99,14 +99,14 @@ static inline int pdc_enable_intr(struct irq_data *d, bool on) static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool *state) { - return d->parent_data->chip->irq_get_irqchip_state(d, + return d->parent_data->chip->irq_get_irqchip_state(d->parent_data, which, state); } static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool value) { - return d->parent_data->chip->irq_set_irqchip_state(d, + return d->parent_data->chip->irq_set_irqchip_state(d->parent_data, which, value); } -- GitLab From b52d230bace2e848d103e46420d4d7a85d0fff90 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 7 Jan 2019 15:31:49 +0530 Subject: [PATCH 0726/1286] clk: qcom: gcc: Update the TCXO source map value sdmmagpie The enable_safe_config flag if used in the RCG assumes the TCXO source map to be '0', which otherwise would cause mapping it to incorrect source during clk_disable. Change-Id: I1926080a03bf051717853ceafecf3198b7c70a04 Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-sdmmagpie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdmmagpie.c b/drivers/clk/qcom/gcc-sdmmagpie.c index ae1936b00049..ac9a20b899a9 100644 --- a/drivers/clk/qcom/gcc-sdmmagpie.c +++ b/drivers/clk/qcom/gcc-sdmmagpie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -43,8 +43,8 @@ static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); enum { - P_AUD_REF_CLK, P_BI_TCXO, + P_AUD_REF_CLK, P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_EVEN, P_GPLL0_OUT_MAIN, -- GitLab From 304754a5a1ff368266d05624627a7abedaf8e3a8 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 7 Jan 2019 15:38:50 +0530 Subject: [PATCH 0727/1286] clk: qcom: rcg2: Remove support for update_src_map The commit 7533b7fb5495 ("clk: qcom: clk-rcg2: Read RCG source before calculating clk rate")' had introduced a function to update the src map, but there could be a race where a set_rate for a clock from a particular CC on a CPU could override the global cxo_f which was set by clock enable/disable for a clock from another CC. Change-Id: Id86818895e226a387e7fd1a09e2034eee18fd361 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rcg2.c | 30 +----------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 63bbb49afc17..60e042414135 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -73,16 +73,6 @@ static struct freq_tbl cxo_f = { .n = 0, }; -static void update_src_map(struct clk_hw *hw) -{ - struct clk_rcg2 *rcg = to_clk_rcg2(hw); - int i, num_parents = clk_hw_get_num_parents(hw); - - for (i = 0; i < num_parents; i++) - if (!rcg->parent_map[i].cfg) - cxo_f.src = rcg->parent_map[i].src; -} - static int clk_rcg2_is_enabled(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -524,12 +514,6 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, if (!f) return -EINVAL; - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - /* * Return if the RCG is currently disabled. This configuration update * will happen as part of the RCG enable sequence. @@ -631,12 +615,6 @@ static int clk_rcg2_enable(struct clk_hw *hw) unsigned long rate; const struct freq_tbl *f; - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - if (rcg->flags & FORCE_ENABLE_RCG) { clk_rcg2_set_force_enable(hw); return 0; @@ -678,12 +656,6 @@ static void clk_rcg2_disable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - /* - * Set the correct source value for CXO as per - * as per defined parent map. - */ - update_src_map(hw); - if (rcg->flags & FORCE_ENABLE_RCG) { clk_rcg2_clear_force_enable(hw); return; -- GitLab From dc6bb29b45d2dce46e14ba4ece7ff38e8285fa46 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 4 Jan 2019 11:15:30 +0530 Subject: [PATCH 0728/1286] ARM: dts: msm: Specify battery configuration for trinket Add battery-data specification to pmi632 charger and qgauge nodes for trinket idp and qrd target. While at it, specify secondary charger configuration for trinket target and also add the dpdm regulator handle and max temperature configuration. Also, shift the platform specific pmi632 charger and qgauge properties to trinket platform specific files. Change-Id: I5b21e71a62443e19d3fad6f7bad55cde962f2f9b Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/pmi632.dtsi | 17 +------------ arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 29 +++++++++++++++++++++++ 3 files changed, 44 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 9813e0ed3965..719dfe508fc7 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -194,8 +194,6 @@ #cooling-cells = <2>; qcom,pmic-revid = <&pmi632_revid>; - /* TODO Add dpdm supply once USB node is added */ - qcom,auto-recharge-soc = <98>; io-channels = <&pmi632_vadc ADC_USB_IN_V_16>, <&pmi632_vadc ADC_USB_IN_I>, <&pmi632_vadc ADC_CHG_TEMP>, @@ -204,16 +202,6 @@ "usb_in_current", "chg_temp", "die_temp"; - qcom,flash-disable-soc = <10>; - qcom,sw-jeita-enable; - qcom,step-charging-enable; - qcom,hw-die-temp-mitigation; - qcom,hw-connector-mitigation; - qcom,connector-internal-pull-kohm = <100>; - - qcom,thermal-mitigation - = <3000000 2500000 2000000 1500000 - 1000000 500000>; qcom,chgr@1000 { reg = <0x1000 0x100>; @@ -367,9 +355,6 @@ #address-cells = <1>; #size-cells = <1>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; qcom,pmic-revid = <&pmi632_revid>; io-channels = <&pmi632_vadc ADC_BAT_THERM_PU2>, <&pmi632_vadc ADC_BAT_ID_PU2>; diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 19b87993a108..0ecf8d826350 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -62,14 +62,28 @@ &pmi632_qg { qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; }; &pmi632_charger { qcom,battery-data = <&mtp_batterydata>; qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + qcom,step-charging-enable; /* SMB1355 only */ qcom,sec-charger-config = <2>; dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; }; &usb0 { diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 5d31125390b6..838457b3662b 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -13,7 +13,36 @@ #include &soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; +}; +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; }; &sdhc_1 { -- GitLab From fb9f3034d37b1a7899105541e9639d32352d80af Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Mon, 7 Jan 2019 15:54:02 +0530 Subject: [PATCH 0729/1286] Documentation: power: smb1355: Add pinctrl specification support Add support to define pinctrl property within smb1355-charger node. Change-Id: Ibde3aeee28462592e9735f779d567dfd1fc2a5c6 Signed-off-by: Umang Agrawal --- .../bindings/power/supply/qcom/smb1355-charger.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt b/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt index 528c285a9361..83a803465314 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt @@ -63,6 +63,18 @@ Charger specific properties: Value type: bool Definition: Boolean property to enable h/w controlled die temp mitigation. +- pinctrl-names + Usage: optional + Value type: + Definition: Should be "default". + Please refer to pinctrl-bindings.txt + +- pinctrl-0 + Usage: optional + Value type: + Definition: phandle of the pin configuration. + Please refer to pinctrl-bindings.txt + ================================================ Second Level Nodes - SMB1355 Charger Peripherals ================================================ -- GitLab From 25ec197b686fd37bba4bee1201a6ec3a8e700e64 Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Tue, 23 Oct 2018 15:33:45 +0530 Subject: [PATCH 0730/1286] usb: f_gsi: Increase max control transfer size to 8K Max packet size that GNSS can use is 8K. Increase the max buff size support in driver from 4K to 8K so that transfers larger than 4K are not failed. Change-Id: If74a7d9994101a55d27ff92258b8ab7ef2d54a50 Signed-off-by: Manu Gautam --- drivers/usb/gadget/function/f_gsi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index 1f378a81c7ab..be1260e81bc3 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -32,7 +32,7 @@ #define GSI_MBIM_CTRL_NAME "android_mbim" #define GSI_DPL_CTRL_NAME "dpl_ctrl" #define GSI_CTRL_NAME_LEN (sizeof(GSI_MBIM_CTRL_NAME)+2) -#define GSI_MAX_CTRL_PKT_SIZE 4096 +#define GSI_MAX_CTRL_PKT_SIZE 8192 #define GSI_CTRL_DTR (1 << 0) #define GSI_NUM_IN_RNDIS_BUFFERS 50 -- GitLab From 911f2a6ac5313dcdc16004312e5bd5c93c5d8438 Mon Sep 17 00:00:00 2001 From: Kim Zhang Date: Wed, 14 Nov 2018 16:43:14 +0800 Subject: [PATCH 0731/1286] ARM: dts: msm: Adding external VR viewer support Support external VR viewer and smp2p support in hid-qvr driver CRs-Fixed: 2366268 Change-Id: Ic036c5cdbfa7fc87b85b8f8b5a17ac85257d37a8 Signed-off-by: Kim Zhang --- arch/arm64/boot/dts/qcom/sdmmagpie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi index 0589f22f4733..b336932b3d8a 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi @@ -2096,6 +2096,11 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; }; sdcc1_ice: sdcc1ice@7C8000 { @@ -3154,6 +3159,7 @@ #include "sdmmagpie-sde.dtsi" #include "sdmmagpie-camera.dtsi" #include "msm-rdbg.dtsi" +#include "msm-qvr-external.dtsi" &pcie_0_gdsc { status = "ok"; -- GitLab From 548b285f7a018e65008fc3e5ecf26f7365c2015d Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Wed, 2 Jan 2019 21:52:16 +0530 Subject: [PATCH 0732/1286] Revert "CHROMIUM: dma-buf: dma-fence: fix warning when releasing active sync point" This reverts commit df9d8c41ac73d51e7a3be1aacd4283467388701e. The warning fixed by the above commit is no more present in kernel. Change-Id: I1fa1dd69a033b13b92c4f99d5afbc881d848d645 Signed-off-by: Vinayak Menon --- drivers/dma-buf/dma-fence.c | 6 +----- drivers/dma-buf/sw_sync.c | 8 -------- include/linux/dma-fence.h | 2 -- 3 files changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 33ea68b45654..9a302799040e 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -329,12 +329,8 @@ dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb) spin_lock_irqsave(fence->lock, flags); ret = !list_empty(&cb->node); - if (ret) { + if (ret) list_del_init(&cb->node); - if (list_empty(&fence->cb_list)) - if (fence->ops->disable_signaling) - fence->ops->disable_signaling(fence); - } spin_unlock_irqrestore(fence->lock, flags); diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index ebc11961d649..24f83f9eeaed 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -169,13 +169,6 @@ static bool timeline_fence_enable_signaling(struct dma_fence *fence) return true; } -static void timeline_fence_disable_signaling(struct dma_fence *fence) -{ - struct sync_pt *pt = dma_fence_to_sync_pt(fence); - - list_del_init(&pt->link); -} - static void timeline_fence_value_str(struct dma_fence *fence, char *str, int size) { @@ -194,7 +187,6 @@ static const struct dma_fence_ops timeline_fence_ops = { .get_driver_name = timeline_fence_get_driver_name, .get_timeline_name = timeline_fence_get_timeline_name, .enable_signaling = timeline_fence_enable_signaling, - .disable_signaling = timeline_fence_disable_signaling, .signaled = timeline_fence_signaled, .wait = dma_fence_default_wait, .release = timeline_fence_release, diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 6385ecd03155..171895072435 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -111,7 +111,6 @@ struct dma_fence_cb { * @get_driver_name: returns the driver name. * @get_timeline_name: return the name of the context this fence belongs to. * @enable_signaling: enable software signaling of fence. - * @disable_signaling: disable software signaling of fence (optional). * @signaled: [optional] peek whether the fence is signaled, can be null. * @wait: custom wait implementation, or dma_fence_default_wait. * @release: [optional] called on destruction of fence, can be null @@ -171,7 +170,6 @@ struct dma_fence_ops { const char * (*get_driver_name)(struct dma_fence *fence); const char * (*get_timeline_name)(struct dma_fence *fence); bool (*enable_signaling)(struct dma_fence *fence); - void (*disable_signaling)(struct dma_fence *fence); bool (*signaled)(struct dma_fence *fence); signed long (*wait)(struct dma_fence *fence, bool intr, signed long timeout); -- GitLab From 2ff61bd621bd14a75a96835f7ea0dba619f9ab90 Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Tue, 8 Jan 2019 11:56:53 +0530 Subject: [PATCH 0733/1286] ARM: dts: msm: add inline crypto engine node for trinket Add inline crypto engine device node to support hardware encryption. Change-Id: I4c3ccd95f60aa6284ad53e3051a0a24656afba48 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 3409196a5ab9..dbd8e0159333 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1763,6 +1763,28 @@ }; }; + sdcc1_ice: sdcc1ice@4748000{ + compatible = "qcom,ice"; + reg = <0x4748000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 757 0 0>, /* No vote */ + <1 757 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "sdcc"; + }; + sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x4744000 0x1000>, <0x4745000 0x1000>; @@ -1771,6 +1793,7 @@ interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; -- GitLab From a552942067e6bcd32f30ecec0d38bacf4bcedec9 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 4 Jan 2019 12:34:40 +0530 Subject: [PATCH 0734/1286] ARM: dts: msm: Add SMB1355 slave charger device to trinket Add support of parallel charger SMB1355 to trinket idp and qrd targets. Change-Id: I9c2ac8d12b42898c01d80ea1a38a8eff150937c6 Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 65 +++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 0ecf8d826350..5aa01d5760cd 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -14,6 +14,11 @@ #include "trinket-thermal-overlay.dtsi" +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + &soc { mtp_batterydata: qcom,battery-data { qcom,batt-id-range-pct = <15>; @@ -89,3 +94,63 @@ &usb0 { extcon = <&pmi632_charger>; }; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 838457b3662b..7c3cf74761fb 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -12,6 +12,11 @@ */ #include +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + &soc { mtp_batterydata: qcom,battery-data { qcom,batt-id-range-pct = <15>; @@ -82,3 +87,63 @@ status = "ok"; }; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; -- GitLab From d776d57cd44342ef26114ff4321082d2e3bc54ab Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 4 Jan 2019 11:27:10 +0530 Subject: [PATCH 0735/1286] power: smb5-lib: Fix DC peripheral access issues Certain PMICs like pmi632 does not have DC peripheral and hence DC peripheral access results in R/W error. Fix this by preventing DC peripheral register access for PMICs that doesn't support them. Change-Id: I9d8baf4c59cee01b11a6197eae55f101a7a7e5a8 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/smb5-lib.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index 0dff46ae2783..7f3717b3c499 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2728,6 +2728,11 @@ int smblib_get_prop_dc_present(struct smb_charger *chg, int rc; u8 stat; + if (chg->smb_version == PMI632_SUBTYPE) { + val->intval = 0; + return 0; + } + rc = smblib_read(chg, DCIN_BASE + INT_RT_STS_OFFSET, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read DCIN_RT_STS rc=%d\n", rc); @@ -2744,6 +2749,11 @@ int smblib_get_prop_dc_online(struct smb_charger *chg, int rc = 0; u8 stat; + if (chg->smb_version == PMI632_SUBTYPE) { + val->intval = 0; + return 0; + } + if (get_client_vote(chg->dc_suspend_votable, USER_VOTER)) { val->intval = false; return rc; -- GitLab From 28c2d618e93b506b5d8e56ba62f07878bcead8b0 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 4 Jan 2019 12:54:40 +0530 Subject: [PATCH 0736/1286] ARM: dts: msm: Modify JEITA specs of qg-ascent-3450mAh battery Change soft-jeita-fcc-ua value of qgauge ascent-3450mAh battery profile to reflect the fcc configuration defined in the soft jeita fcc table. Change-Id: Icf8f44f39847928f9cac0fd9cf95f0716975fc55 Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi b/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi index 8297c77a16f5..e8dff3cad2cd 100644 --- a/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi +++ b/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ qcom,ascent_3450mah { @@ -33,7 +33,7 @@ qcom,ascent_3450mah { /* COOL hys = 8 DegC, WARM hys = 37 DegC */ qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>; - qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fcc-ua = <1725000 2760000>; qcom,jeita-soft-fv-uv = <4250000 4250000>; qcom,fcc1-temp-lut { -- GitLab From 809094a39091e0df414c1badc8fa411e5edeeb22 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 24 Dec 2018 12:32:07 +0530 Subject: [PATCH 0737/1286] msm: kgsl: Add support for A610 GPU Add new GPU ID and required initial settings to support Graphics functionality on Trinket. Change-Id: I4fccaa0134eff39675c331bd903eb647694b9ee7 Signed-off-by: Deepak Kumar --- drivers/gpu/msm/adreno-gpulist.h | 17 +++++- drivers/gpu/msm/adreno.h | 4 +- drivers/gpu/msm/adreno_a6xx.c | 85 ++++++++++++++++++++------ drivers/gpu/msm/adreno_a6xx_snapshot.c | 14 ++++- 4 files changed, 99 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index 2b0a4d11940c..ec6d69904b4e 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -498,4 +498,19 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .gpmu_major = 0x1, .gpmu_minor = 0x003, }, + { + .gpurev = ADRENO_REV_A610, + .core = 6, + .major = 1, + .minor = 0, + .patchid = ANY_ID, + .features = ADRENO_64BIT | ADRENO_PREEMPTION | + ADRENO_CONTENT_PROTECTION, + .sqefw_name = "a630_sqe.fw", + .zap_name = "a610_zap", + .gpudev = &adreno_a6xx_gpudev, + .gmem_size = (SZ_128K + SZ_4K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, }; diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 5cf6ec541c1c..08224b48532c 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -219,6 +219,7 @@ enum adreno_gpurev { ADRENO_REV_A512 = 512, ADRENO_REV_A530 = 530, ADRENO_REV_A540 = 540, + ADRENO_REV_A610 = 610, ADRENO_REV_A612 = 612, ADRENO_REV_A615 = 615, ADRENO_REV_A616 = 616, @@ -1298,6 +1299,7 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) ADRENO_GPUREV(adreno_dev) < 700; } +ADRENO_TARGET(a610, ADRENO_REV_A610) ADRENO_TARGET(a612, ADRENO_REV_A612) ADRENO_TARGET(a618, ADRENO_REV_A618) ADRENO_TARGET(a630, ADRENO_REV_A630) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 2e89ebd180df..4b986d6f7373 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -1,4 +1,4 @@ -/* Copyright (c)2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c)2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,6 +14,7 @@ #include #include #include +#include #include "adreno.h" #include "a6xx_reg.h" @@ -58,6 +59,7 @@ static const struct adreno_vbif_platform a6xx_vbif_platforms[] = { { adreno_is_a640, a640_gbif }, { adreno_is_a680, a640_gbif }, { adreno_is_a612, a640_gbif }, + { adreno_is_a610, a640_gbif }, }; struct kgsl_hwcg_reg { @@ -352,6 +354,7 @@ static const struct { {adreno_is_a640, a640_hwcg_regs, ARRAY_SIZE(a640_hwcg_regs)}, {adreno_is_a680, a640_hwcg_regs, ARRAY_SIZE(a640_hwcg_regs)}, {adreno_is_a612, a612_hwcg_regs, ARRAY_SIZE(a612_hwcg_regs)}, + {adreno_is_a610, a612_hwcg_regs, ARRAY_SIZE(a612_hwcg_regs)}, }; static struct a6xx_protected_regs { @@ -591,7 +594,7 @@ __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) { if (adreno_is_a630(adreno_dev)) return 0x8AA8AA02; - else if (adreno_is_a612(adreno_dev)) + else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) return 0xAAA8AA82; else return 0x8AA8AA82; @@ -669,11 +672,12 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) /* * Disable SP clock before programming HWCG registers. - * A612 GPU is not having the GX power domain. Hence - * skip GMU_GX registers for A12. + * A612 and A610 GPU is not having the GX power domain. + * Hence skip GMU_GX registers for A612 and A610. */ - if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev)) + if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) && + !adreno_is_a610(adreno_dev)) gmu_core_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); @@ -682,10 +686,11 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) /* * Enable SP clock after programming HWCG registers. - * A612 GPU is not having the GX power domain. Hence - * skip GMU_GX registers for A612. + * A612 and A610 GPU is not having the GX power domain. + * Hence skip GMU_GX registers for A612 and A610. */ - if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev)) + if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) && + !adreno_is_a610(adreno_dev)) gmu_core_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); @@ -830,7 +835,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); - } else if (adreno_is_a612(adreno_dev)) { + } else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) { kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); } else { @@ -838,8 +843,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); } - if (adreno_is_a612(adreno_dev)) { - /* For A612 Mem pool size is reduced to 48 */ + if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) { + /* For A612 and A610 Mem pool size is reduced to 48 */ kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48); kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 47); } else { @@ -851,7 +856,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x400 << 11)); else if (adreno_is_a680(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x800 << 11)); - else if (adreno_is_a612(adreno_dev)) + else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x100 << 11)); else kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); @@ -1246,7 +1251,7 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, */ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) { - if (adreno_is_a612(adreno_dev)) + if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) return 0; return a6xx_gmu_sptprac_enable(adreno_dev); @@ -1258,7 +1263,7 @@ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) */ static void a6xx_sptprac_disable(struct adreno_device *adreno_dev) { - if (adreno_is_a612(adreno_dev)) + if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) return; a6xx_gmu_sptprac_disable(adreno_dev); @@ -1625,7 +1630,8 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS) | gpu_scid; - if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev)) { + if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev) || + adreno_is_a610(adreno_dev)) { kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1, A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val); } else { @@ -1647,7 +1653,8 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) * On A640, the GPUHTW SCID is configured via a NoC override in the * XBL image. */ - if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev)) + if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev) || + adreno_is_a610(adreno_dev)) return; gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice); @@ -1668,7 +1675,8 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) * Attributes override through GBIF is not supported with MMU-500. * Attributes are used as configured through SMMU pagetable entries. */ - if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev)) + if (adreno_is_a640(adreno_dev) || adreno_is_a612(adreno_dev) || + adreno_is_a610(adreno_dev)) return; /* @@ -2661,7 +2669,13 @@ static int a6xx_enable_pwr_counters(struct adreno_device *adreno_dev, return -ENODEV; kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xFF000000); - kgsl_regrmw(device, + + /* + * A610 GPU has only one power counter fixed to count GPU busy + * cycles with no select register. + */ + if (!adreno_is_a610(adreno_dev)) + kgsl_regrmw(device, A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xFF, 0x20); kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0x1); @@ -2903,6 +2917,17 @@ static void a6xx_perfcounter_init(struct adreno_device *adreno_dev) if (adreno_is_a612(adreno_dev)) { a6xx_pwrcounters_gpmu[4].countable = KGSL_PERFCOUNTER_BROKEN; a6xx_pwrcounters_gpmu[5].countable = KGSL_PERFCOUNTER_BROKEN; + } else if (adreno_is_a610(adreno_dev)) { + /* + * A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1 to 5 are not + * present on A610. Mark them as broken so that they + * can't be used. + */ + a6xx_pwrcounters_gpmu[1].countable = KGSL_PERFCOUNTER_BROKEN; + a6xx_pwrcounters_gpmu[2].countable = KGSL_PERFCOUNTER_BROKEN; + a6xx_pwrcounters_gpmu[3].countable = KGSL_PERFCOUNTER_BROKEN; + a6xx_pwrcounters_gpmu[4].countable = KGSL_PERFCOUNTER_BROKEN; + a6xx_pwrcounters_gpmu[5].countable = KGSL_PERFCOUNTER_BROKEN; } } @@ -2988,6 +3013,29 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, return ret; } +static void a6xx_clk_set_options(struct adreno_device *adreno_dev, + const char *name, struct clk *clk, bool on) +{ + if (!adreno_is_a610(adreno_dev)) + return; + + /* Handle clock settings for GFX PSCBCs */ + if (on) { + if (!strcmp(name, "mem_iface_clk")) { + clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH); + clk_set_flags(clk, CLKFLAG_NORETAIN_MEM); + } else if (!strcmp(name, "core_clk")) { + clk_set_flags(clk, CLKFLAG_RETAIN_PERIPH); + clk_set_flags(clk, CLKFLAG_RETAIN_MEM); + } + } else { + if (!strcmp(name, "core_clk")) { + clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH); + clk_set_flags(clk, CLKFLAG_NORETAIN_MEM); + } + } +} + struct adreno_gpudev adreno_a6xx_gpudev = { .reg_offsets = &a6xx_reg_offsets, .start = a6xx_start, @@ -3026,4 +3074,5 @@ struct adreno_gpudev adreno_a6xx_gpudev = { .perfcounter_init = a6xx_perfcounter_init, .perfcounter_update = a6xx_perfcounter_update, .coresight = {&a6xx_coresight, &a6xx_coresight_cx}, + .clk_set_options = a6xx_clk_set_options, }; diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c index 748e2e806ec1..85025a650ee6 100644 --- a/drivers/gpu/msm/adreno_a6xx_snapshot.c +++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -331,6 +331,13 @@ static const unsigned int a6xx_pre_crashdumper_registers[] = { 0x825, 0x825, }; +static const unsigned int a6xx_gmu_wrapper_registers[] = { + /* GMU CX */ + 0x1F840, 0x1F840, 0x1F844, 0x1F845, 0x1F887, 0x1F889, + /* GMU AO*/ + 0x23B0C, 0x23B0E, 0x23B15, 0x23B15, +}; + enum a6xx_debugbus_id { A6XX_DBGBUS_CP = 0x1, A6XX_DBGBUS_RBBM = 0x2, @@ -1536,6 +1543,11 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, if (!gx_on) return; + if (adreno_is_a610(adreno_dev)) + adreno_snapshot_registers(device, snapshot, + a6xx_gmu_wrapper_registers, + ARRAY_SIZE(a6xx_gmu_wrapper_registers) / 2); + /* Dump the registers which get affected by crash dumper trigger */ kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, a6xx_snapshot_pre_crashdump_regs, NULL); -- GitLab From dae3a5f0aa6d607ddeac745db6f81bd72c3e9d29 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Mon, 7 Jan 2019 21:25:27 +0530 Subject: [PATCH 0738/1286] ARM: dts: msm: add actlr settings for trinket Add actlr configuration settings for trinket that helps in performance improvements of usecases using that SMMU. Change-Id: I1e0b6fd1ef87eee42bce09059200bf91a171b94c Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index 2437a16178ab..656df0e15a73 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -168,3 +168,16 @@ iommus = <&apps_smmu 0x21 0>; }; }; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* MMRT and MMNRT TBUs: +3 deep PF */ + <0x400 0x3ff 0x103>, + <0x800 0x3ff 0x103>; +}; -- GitLab From 9e730178b2a87a10f34fdbcf6a2441cdff0cf2a5 Mon Sep 17 00:00:00 2001 From: mjavid Date: Tue, 27 Nov 2018 16:55:33 +0530 Subject: [PATCH 0739/1286] ARM: dts: msm: Add IPA device configuration for trinket The required configuration to support new IPA HW version 4.2 on trinket target. Change-Id: Ib43d7b52b3aed21ecf491fa814ce0a0919a1ce91 Acked-by: Praveen Kurapati Signed-off-by: Mohammed Javid --- arch/arm64/boot/dts/qcom/trinket.dtsi | 124 ++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 6b778ca090ae..3f201b6aa592 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -22,6 +22,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. TRINKET"; @@ -1510,6 +1511,18 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { @@ -1682,6 +1695,117 @@ status = "disabled"; }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x34000>, + <0x5804000 0x2c000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = <0 257 0>, <0 259 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,bandwidth-vote-for-ipa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + /* SVS2 */ + , + , + , + , + /* SVS */ + , + , + , + , + /* NOMINAL */ + , + , + , + , + /* TURBO */ + , + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x00E0 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x00E1 0x0>; + /* ipa-uc ram */ + qcom,additional-mapping = <0x5860000 0x5860000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x00E2 0x0>; + qcom,iova-mapping = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; }; #include "pmi632.dtsi" -- GitLab From d6aa9c1c79ad588d3f0d729d4ec249d86fbdf87c Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Tue, 8 Jan 2019 13:07:15 +0530 Subject: [PATCH 0740/1286] defconfig: trinket: enable configuration flag for Inline Crypto Engine Enable configuration flag for Inline Crypto Engine based Disk Encryption. Change-Id: I1e832ff5a1233035685d06c4073c5b226419c0e9 Signed-off-by: Ramandeep Trehan --- arch/arm64/configs/vendor/trinket-perf_defconfig | 3 +++ arch/arm64/configs/vendor/trinket_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 7627bcf916df..b80a7c986e05 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -563,6 +563,7 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_ENCRYPTION=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y @@ -599,6 +600,7 @@ CONFIG_CORESIGHT_DUMMY=y CONFIG_CORESIGHT_REMOTE_ETM=y CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 CONFIG_CORESIGHT_EVENT=y +CONFIG_PFK=y CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y CONFIG_HARDENED_USERCOPY=y @@ -612,6 +614,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 04131a8f710b..1d13cd92e4ed 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -592,6 +592,7 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_ENCRYPTION=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y @@ -682,6 +683,7 @@ CONFIG_CORESIGHT_REMOTE_ETM=y CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 CONFIG_CORESIGHT_TGU=y CONFIG_CORESIGHT_EVENT=y +CONFIG_PFK=y CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y CONFIG_HARDENED_USERCOPY=y @@ -696,6 +698,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y -- GitLab From 1955560bb7c0b6269bf5e96e08cfe0fef1cb1c3d Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Tue, 8 Jan 2019 13:14:56 +0530 Subject: [PATCH 0741/1286] ARM: dts: msm: add clock, gdsc changes for gfx smmu on trinket Add the required clock and regulator changes that need to be turned on before accessing graphics SMMU on trinket. Change-Id: I9cb126b1d2cc653ec432406efb6aa41037149708 Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index 656df0e15a73..d8f4149e6c81 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -24,6 +24,14 @@ qcom,skip-init; qcom,use-3-lvl-tables; #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; #size-cells = <1>; #address-cells = <1>; ranges; -- GitLab From dae9523ad2a50c2c687188e145dec68f8f64b516 Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Mon, 11 Feb 2013 15:53:34 +0530 Subject: [PATCH 0742/1286] usb: dwc3: gadget: Fail request submission if it was already queued Function driver should not try to queue a busy request again to DCD until DCD returns it by calling its completion handler or it is explicitly dequeued. Some buggy function driver may try to submit a request again which is with DCD resulting in corruption of request_list leading to crash later in giveback. Catch such conditions and fail the request submission to DCD. CRs-Fixed: 447192 Change-Id: Id2a4a1720f61dffc50cc22598734f229caf07ff3 Signed-off-by: Manu Gautam Signed-off-by: Mayank Rana --- drivers/usb/dwc3/gadget.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 2a7a1df1fe1f..844d5675a700 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1504,6 +1504,13 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) &req->request, req->dep->name)) return -EINVAL; + if (req->request.status == -EINPROGRESS) { + ret = -EBUSY; + dev_err(dwc->dev, "%s: %pK request already in queue", + dep->name, req); + return ret; + } + req->request.actual = 0; req->request.status = -EINPROGRESS; req->direction = dep->direction; -- GitLab From 9cb4dc8fdf2932ed400b6fccf1d8a8a75705d63e Mon Sep 17 00:00:00 2001 From: Vishwanath Raju K Date: Fri, 4 Jan 2019 16:15:33 +0530 Subject: [PATCH 0743/1286] ARM: dts: msm: optimize default,cma size for qcs403 Reduced default,cma size to 4MB from 16MB for qcs403. Change-Id: I54c14982cadaffd060bec12b47cf090307c7bfd5 Signed-off-by: Vishwanath Raju K --- arch/arm64/boot/dts/qcom/qcs403.dtsi | 8 +++++++- arch/arm64/boot/dts/qcom/qcs405.dtsi | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs403.dtsi b/arch/arm64/boot/dts/qcom/qcs403.dtsi index 11fa4f2d126b..87816c4ab749 100644 --- a/arch/arm64/boot/dts/qcom/qcs403.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs403.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,3 +45,9 @@ < 1401600 MHZ_TO_MBPS( 710, 8) >; }; }; + +&reserved_mem { + linux,cma { + size = <0 0x400000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi index 88206443866d..e5cf516bb369 100644 --- a/arch/arm64/boot/dts/qcom/qcs405.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -34,7 +34,7 @@ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; - reserved-memory { + reserved_mem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; -- GitLab From 84bac46307a099f1018e7800da5a2689a93e42c6 Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Thu, 27 Dec 2018 19:23:57 +0530 Subject: [PATCH 0744/1286] msm: ADSPRPC: Protect global remote heap maps Protect global remote heap map by using spin locks, so that no concurrent threads can corrupt the map list Change-Id: I688b532988bebc4ac6c4ed80b5bd857968671450 Acked-by: Himateja Reddy Signed-off-by: Tharun Kumar Merugu --- drivers/char/adsprpc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 00784651bd83..e470d9c21826 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -578,7 +578,9 @@ static void fastrpc_mmap_add(struct fastrpc_mmap *map) map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { struct fastrpc_apps *me = &gfa; + spin_lock(&me->hlock); hlist_add_head(&map->hn, &me->maps); + spin_unlock(&me->hlock); } else { struct fastrpc_file *fl = map->fl; @@ -598,6 +600,7 @@ static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, return -EOVERFLOW; if (mflags == ADSP_MMAP_HEAP_ADDR || mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + spin_lock(&me->hlock); hlist_for_each_entry_safe(map, n, &me->maps, hn) { if (va >= map->va && va + len <= map->va + map->len && @@ -608,6 +611,7 @@ static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, break; } } + spin_unlock(&me->hlock); } else { hlist_for_each_entry_safe(map, n, &fl->maps, hn) { if (va >= map->va && @@ -653,6 +657,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, struct hlist_node *n; struct fastrpc_apps *me = &gfa; + spin_lock(&me->hlock); hlist_for_each_entry_safe(map, n, &me->maps, hn) { if (map->raddr == va && map->raddr + map->len == va + len && @@ -662,6 +667,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, break; } } + spin_unlock(&me->hlock); if (match) { *ppmap = match; return 0; -- GitLab From e7358dd0404732256140ef708ddf934b64830e85 Mon Sep 17 00:00:00 2001 From: blong Date: Wed, 20 Jun 2018 17:33:16 +0800 Subject: [PATCH 0745/1286] Perf: Enable pmuv3 on 32 bit kernel Add mechanism to detect and enable pmuv3 on 32 bit kernel. Change-Id: I56e0c5a0bb2dbc2dc1445fb578782ec5e8c98def Signed-off-by: Sheetal Sahasrabudhe Signed-off-by: Biao long --- arch/arm/kernel/perf_event_v7.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 7cd83a230095..590853f0fe05 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1241,6 +1241,16 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) return armv7_probe_num_events(cpu_pmu); } +static int armv8_pmuv3_pmu_init(struct arm_pmu *cpu_pmu) +{ + armv7pmu_init(cpu_pmu); + cpu_pmu->name = "ARMv8 Cortex-A53"; + cpu_pmu->map_event = armv7_a7_map_event; + armv7_read_num_pmnc_events(&cpu_pmu->num_events); + cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + return 0; +} + static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) { armv7pmu_init(cpu_pmu); @@ -2011,6 +2021,7 @@ static const struct of_device_id armv7_pmu_of_device_ids[] = { {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, + {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, {}, }; -- GitLab From 272f00547a2e8a9992f43719c24fd0c4b3d0b929 Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Wed, 9 May 2018 19:49:48 -0700 Subject: [PATCH 0746/1286] perf: Add exclude_idle support for armv7 PMU By adding the exclude_idle support, the driver would update the PMU counter values into event->count right before it goes into an idle state. This way, even if the client, from another core, tries to read the value during this idle period, it would return the last updated value before moving into idle without waking the idle core up. Change-Id: Iccc9a9d73e7079b27d0e2978bd286c4c464ce28f Signed-off-by: Raghavendra Rao Ananta --- arch/arm/kernel/perf_event_v7.c | 81 +++++++++++++++++++++++++++------ 1 file changed, 68 insertions(+), 13 deletions(-) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 7cd83a230095..641235c50f10 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1067,8 +1067,6 @@ static int armv7pmu_set_event_filter(struct hw_perf_event *event, { unsigned long config_base = 0; - if (attr->exclude_idle) - return -EPERM; if (attr->exclude_user) config_base |= ARMV7_EXCLUDE_USER; if (attr->exclude_kernel) @@ -1185,11 +1183,68 @@ static void armv7_read_num_pmnc_events(void *info) *nb_cnt += 1; } -static int armv7_probe_num_events(struct arm_pmu *arm_pmu) +static void armv7_pmu_idle_update(struct arm_pmu *cpu_pmu) { - return smp_call_function_any(&arm_pmu->supported_cpus, + struct pmu_hw_events *hw_events; + struct perf_event *event; + int idx; + + if (!cpu_pmu) + return; + + hw_events = this_cpu_ptr(cpu_pmu->hw_events); + if (!hw_events) + return; + + for (idx = 0; idx < cpu_pmu->num_events; ++idx) { + event = hw_events->events[idx]; + + if (!event || !event->attr.exclude_idle || + event->state != PERF_EVENT_STATE_ACTIVE) + continue; + + cpu_pmu->pmu.read(event); + } +} + +struct armv7_pmu_idle_nb { + struct arm_pmu *cpu_pmu; + struct notifier_block perf_cpu_idle_nb; +}; + +static int armv7_pmu_idle_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct armv7_pmu_idle_nb *pmu_idle_nb = container_of(nb, + struct armv7_pmu_idle_nb, perf_cpu_idle_nb); + + if (action == IDLE_START) + armv7_pmu_idle_update(pmu_idle_nb->cpu_pmu); + + return NOTIFY_OK; +} + +static int armv7_probe_pmu(struct arm_pmu *arm_pmu) +{ + int ret; + struct armv7_pmu_idle_nb *pmu_idle_nb; + + pmu_idle_nb = devm_kzalloc(&arm_pmu->plat_device->dev, + sizeof(*pmu_idle_nb), GFP_KERNEL); + if (!pmu_idle_nb) + return -ENOMEM; + + ret = smp_call_function_any(&arm_pmu->supported_cpus, armv7_read_num_pmnc_events, &arm_pmu->num_events, 1); + if (ret) + return ret; + + pmu_idle_nb->cpu_pmu = arm_pmu; + pmu_idle_nb->perf_cpu_idle_nb.notifier_call = armv7_pmu_idle_notifier; + idle_notifier_register(&pmu_idle_nb->perf_cpu_idle_nb); + + return 0; } static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) @@ -1201,7 +1256,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv1_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) @@ -1213,7 +1268,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv1_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) @@ -1225,7 +1280,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv1_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) @@ -1238,7 +1293,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv2_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) @@ -1251,7 +1306,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv2_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) @@ -1264,7 +1319,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) &armv7_pmuv2_events_attr_group; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) @@ -1661,7 +1716,7 @@ static int krait_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->disable = krait_pmu_disable_event; cpu_pmu->get_event_idx = krait_pmu_get_event_idx; cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } /* @@ -1984,7 +2039,7 @@ static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->disable = scorpion_pmu_disable_event; cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) @@ -1997,7 +2052,7 @@ static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->disable = scorpion_pmu_disable_event; cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); + return armv7_probe_pmu(cpu_pmu); } static const struct of_device_id armv7_pmu_of_device_ids[] = { -- GitLab From 082be276354e5f432a7c6b71bd08e246ee7cd30a Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 10 Dec 2018 19:33:31 +0000 Subject: [PATCH 0747/1286] arm64: dma-mapping: Fix FORCE_CONTIGUOUS buffer clearing We need to invalidate the caches *before* clearing the buffer via the non-cacheable alias, else in the worst case __dma_flush_area() may write back dirty lines over the top of our nice new zeros. Change-Id: Ie1641f5e0ec4f725c15b282fcde2204c3c9fda42 Fixes: dd65a941f6ba ("arm64: dma-mapping: clear buffers allocated with FORCE_CONTIGUOUS flag") Cc: # 4.18.x- Acked-by: Will Deacon Signed-off-by: Robin Murphy Signed-off-by: Catalin Marinas Git-commit: 3238c359acee4ab57f15abb5a82b8ab38a661ee7 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Vinayak Menon --- arch/arm64/mm/dma-mapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 39d00f15bd46..7351c6f6cdce 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -774,9 +774,9 @@ static void *__iommu_alloc_attrs(struct device *dev, size_t size, prot, __builtin_return_address(0)); if (addr) { - memset(addr, 0, size); if (!coherent) __dma_flush_area(page_to_virt(page), iosize); + memset(addr, 0, size); } else { iommu_dma_unmap_page(dev, *handle, iosize, 0, attrs); dma_release_from_contiguous(dev, page, -- GitLab From 7200dee817d0c980df88a8e0f00a3055ff06b373 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 8 Jan 2019 17:24:28 +0530 Subject: [PATCH 0748/1286] ARM: configs: Enable ICE support for emmc on trinket Enable ICE support for emmc on trinket. Change-Id: I555d940664f8f3975fa2384a140c579b789b287c Signed-off-by: Ram Prakash Gupta --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..9781f2c014c1 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -445,6 +445,7 @@ CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..1042bd6dc66c 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -461,6 +461,7 @@ CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -- GitLab From 07a83ab2a704875c1cda8ac519ec12b772d4d6a5 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 8 Jan 2019 11:14:37 +0530 Subject: [PATCH 0749/1286] ARM: dts: msm: Update TSENS user thermal_zones for trinket Update user thermal_zone entries for trinket to reflect change in sensor assignment. Remove sensor 5 which is not used. Change-Id: I185b515d6f49741b027d76a5209b585d153aeb6f Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 42 ++++--------------- 1 file changed, 9 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 077ebf480755..44596816179f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -282,35 +282,11 @@ }; }; - cpu-1-3-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 4>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - reset-mon-1-cfg { - temperature = <110000>; - hysteresis = <5000>; - type = "passive"; - }; - reset-mon-2-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - video-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&tsens0 5>; + thermal-sensors = <&tsens0 4>; trips { active-config0 { temperature = <125000>; @@ -330,7 +306,7 @@ }; }; - cpu-1-0-usr { + cpuss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -354,7 +330,7 @@ }; }; - cpu-1-1-usr { + cpuss-1-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -378,7 +354,7 @@ }; }; - cpu-1-2-usr { + cpuss-2-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -402,7 +378,7 @@ }; }; - cpu-0-0-usr { + cpu-1-0-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -426,7 +402,7 @@ }; }; - cpu-0-1-usr { + cpu-1-1-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -450,7 +426,7 @@ }; }; - cpu-0-2-usr { + cpu-1-2-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -474,7 +450,7 @@ }; }; - cpu-0-3-usr { + cpu-1-3-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; -- GitLab From 19c3f605b9a477fdec23ed855a726dfa72e12484 Mon Sep 17 00:00:00 2001 From: Yuanyuan Liu Date: Fri, 4 Jan 2019 16:09:22 -0800 Subject: [PATCH 0750/1286] cnss2: Remove module_param* APIs module_param* APIs don't scale well for multiple device instances for one driver. Move module_param to debugfs. CRs-Fixed: 2377009 Change-Id: Ibe556be202b28462908d12bba4dcedd12929dc42 Signed-off-by: Yuanyuan Liu --- drivers/net/wireless/cnss2/debug.c | 140 ++++++++++++++++++++++++++++- drivers/net/wireless/cnss2/main.c | 77 ++++++++-------- drivers/net/wireless/cnss2/main.h | 23 ++++- drivers/net/wireless/cnss2/pci.c | 50 ++++------- drivers/net/wireless/cnss2/qmi.c | 45 +++------- drivers/net/wireless/cnss2/qmi.h | 7 +- 6 files changed, 230 insertions(+), 112 deletions(-) diff --git a/drivers/net/wireless/cnss2/debug.c b/drivers/net/wireless/cnss2/debug.c index 30e37a08d291..ea9c43e76edd 100644 --- a/drivers/net/wireless/cnss2/debug.c +++ b/drivers/net/wireless/cnss2/debug.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -504,6 +504,142 @@ static const struct file_operations cnss_runtime_pm_debug_fops = { .llseek = seq_lseek, }; +static ssize_t cnss_control_params_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + char buf[64]; + char *sptr, *token; + char *cmd; + u32 val; + unsigned int len = 0; + const char *delim = " "; + + if (!plat_priv) + return -ENODEV; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + sptr = buf; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + if (!sptr) + return -EINVAL; + cmd = token; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &val)) + return -EINVAL; + + if (strcmp(cmd, "quirks") == 0) + plat_priv->ctrl_params.quirks = val; + else if (strcmp(cmd, "mhi_timeout") == 0) + plat_priv->ctrl_params.mhi_timeout = val; + else if (strcmp(cmd, "qmi_timeout") == 0) + plat_priv->ctrl_params.qmi_timeout = val; + else if (strcmp(cmd, "bdf_type") == 0) + plat_priv->ctrl_params.bdf_type = val; + else + return -EINVAL; + + return count; +} + +static int cnss_show_quirks_state(struct seq_file *s, + struct cnss_plat_data *plat_priv) +{ + enum cnss_debug_quirks i; + int skip = 0; + unsigned long state; + + seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks); + for (i = 0, state = plat_priv->ctrl_params.quirks; + state != 0; state >>= 1, i++) { + if (!(state & 0x1)) + continue; + if (skip++) + seq_puts(s, " | "); + + switch (i) { + case LINK_DOWN_SELF_RECOVERY: + seq_puts(s, "LINK_DOWN_SELF_RECOVERY"); + continue; + case SKIP_DEVICE_BOOT: + seq_puts(s, "SKIP_DEVICE_BOOT"); + continue; + case USE_CORE_ONLY_FW: + seq_puts(s, "USE_CORE_ONLY_FW"); + continue; + case SKIP_RECOVERY: + seq_puts(s, "SKIP_RECOVERY"); + continue; + case QMI_BYPASS: + seq_puts(s, "QMI_BYPASS"); + continue; + case ENABLE_WALTEST: + seq_puts(s, "WALTEST"); + continue; + case ENABLE_PCI_LINK_DOWN_PANIC: + seq_puts(s, "PCI_LINK_DOWN_PANIC"); + continue; + case FBC_BYPASS: + seq_puts(s, "FBC_BYPASS"); + continue; + case ENABLE_DAEMON_SUPPORT: + seq_puts(s, "DAEMON_SUPPORT"); + continue; + } + + seq_printf(s, "UNKNOWN-%d", i); + } + seq_puts(s, ")\n"); + return 0; +} + +static int cnss_control_params_debug_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *cnss_priv = s->private; + + seq_puts(s, "\nUsage: echo > /cnss/control_params\n"); + seq_puts(s, " can be one of below:\n"); + seq_puts(s, "quirks: Debug quirks for driver\n"); + seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n"); + seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n"); + seq_puts(s, "bdf_type: Type of board data file to be downloaded\n"); + + seq_puts(s, "\nCurrent value:\n"); + cnss_show_quirks_state(s, cnss_priv); + seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout); + seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout); + seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type); + + return 0; +} + +static int cnss_control_params_debug_open(struct inode *inode, + struct file *file) +{ + return single_open(file, cnss_control_params_debug_show, + inode->i_private); +} + +static const struct file_operations cnss_control_params_debug_fops = { + .read = seq_read, + .write = cnss_control_params_debug_write, + .open = cnss_control_params_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + #ifdef CONFIG_CNSS2_DEBUG static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv) { @@ -517,6 +653,8 @@ static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv) &cnss_reg_write_debug_fops); debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv, &cnss_runtime_pm_debug_fops); + debugfs_create_file("control_params", 0600, root_dentry, plat_priv, + &cnss_control_params_debug_fops); return 0; } diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c index 8b9028e34a1b..6f0fa4c9d491 100644 --- a/drivers/net/wireless/cnss2/main.c +++ b/drivers/net/wireless/cnss2/main.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -38,27 +38,18 @@ #define FW_ASSERT_TIMEOUT 5000 #define CNSS_EVENT_PENDING 2989 -static struct cnss_plat_data *plat_env; - -static DECLARE_RWSEM(cnss_pm_sem); - -static bool qmi_bypass; -#ifdef CONFIG_CNSS2_DEBUG -module_param(qmi_bypass, bool, 0600); -MODULE_PARM_DESC(qmi_bypass, "Bypass QMI from platform driver"); +#define CNSS_QUIRKS_DEFAULT BIT(ENABLE_DAEMON_SUPPORT) +#ifdef CONFIG_CNSS_EMULATION +#define CNSS_MHI_TIMEOUT_DEFAULT 90000 +#else +#define CNSS_MHI_TIMEOUT_DEFAULT 0 #endif +#define CNSS_QMI_TIMEOUT_DEFAULT 10000 +#define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF -static bool enable_waltest; -#ifdef CONFIG_CNSS2_DEBUG -module_param(enable_waltest, bool, 0600); -MODULE_PARM_DESC(enable_waltest, "Enable to handle firmware waltest"); -#endif +static struct cnss_plat_data *plat_env; -unsigned long quirks; -#ifdef CONFIG_CNSS2_DEBUG -module_param(quirks, ulong, 0600); -MODULE_PARM_DESC(quirks, "Debug quirks for the driver"); -#endif +static DECLARE_RWSEM(cnss_pm_sem); static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = { "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin", @@ -253,7 +244,7 @@ int cnss_wlan_enable(struct device *dev, if (plat_priv->device_id == QCA6174_DEVICE_ID) return 0; - if (qmi_bypass) + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) return 0; if (!config || !host_version) { @@ -285,7 +276,7 @@ int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode) if (plat_priv->device_id == QCA6174_DEVICE_ID) return 0; - if (qmi_bypass) + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) return 0; return cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF); @@ -377,16 +368,6 @@ int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode) } EXPORT_SYMBOL(cnss_set_fw_log_mode); -bool *cnss_get_qmi_bypass(void) -{ - return &qmi_bypass; -} - -unsigned long *cnss_get_debug_quirks(void) -{ - return &quirks; -} - static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv) { int ret = 0; @@ -433,7 +414,7 @@ static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv) clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); } - if (enable_waltest) { + if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) { ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_WALTEST); } else if (test_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state)) { @@ -571,7 +552,14 @@ int cnss_driver_event_post(struct cnss_plat_data *plat_priv, unsigned int cnss_get_boot_timeout(struct device *dev) { - return cnss_get_qmi_timeout(); + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return 0; + } + + return cnss_get_qmi_timeout(plat_priv); } EXPORT_SYMBOL(cnss_get_boot_timeout); @@ -890,14 +878,15 @@ static int cnss_do_recovery(struct cnss_plat_data *plat_priv, if (plat_priv->device_id == QCA6174_DEVICE_ID) goto self_recovery; - if (test_bit(SKIP_RECOVERY, &quirks)) { + if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) { cnss_pr_dbg("Skip device recovery\n"); return 0; } switch (reason) { case CNSS_REASON_LINK_DOWN: - if (test_bit(LINK_DOWN_SELF_RECOVERY, &quirks)) + if (test_bit(LINK_DOWN_SELF_RECOVERY, + &plat_priv->ctrl_params.quirks)) goto self_recovery; break; case CNSS_REASON_RDDM: @@ -1513,7 +1502,7 @@ static ssize_t cnss_fs_ready_store(struct device *dev, cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n", fs_ready, count); - if (qmi_bypass) { + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) { cnss_pr_dbg("QMI is bypassed.\n"); return count; } @@ -1617,6 +1606,14 @@ static void cnss_misc_deinit(struct cnss_plat_data *plat_priv) del_timer(&plat_priv->fw_boot_timer); } +static void cnss_init_control_params(struct cnss_plat_data *plat_priv) +{ + plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT; + plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT; + plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT; + plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT; +} + static const struct platform_device_id cnss_platform_id_table[] = { { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, }, { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, }, @@ -1672,11 +1669,13 @@ static int cnss_probe(struct platform_device *plat_dev) cnss_set_plat_priv(plat_dev, plat_priv); platform_set_drvdata(plat_dev, plat_priv); + cnss_init_control_params(plat_priv); + ret = cnss_get_resources(plat_priv); if (ret) goto reset_ctx; - if (!test_bit(SKIP_DEVICE_BOOT, &quirks)) { + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) { ret = cnss_power_on_device(plat_priv); if (ret) goto free_res; @@ -1731,10 +1730,10 @@ static int cnss_probe(struct platform_device *plat_dev) unreg_esoc: cnss_unregister_esoc(plat_priv); deinit_bus: - if (!test_bit(SKIP_DEVICE_BOOT, &quirks)) + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) cnss_bus_deinit(plat_priv); power_off: - if (!test_bit(SKIP_DEVICE_BOOT, &quirks)) + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) cnss_power_off_device(plat_priv); free_res: cnss_put_resources(plat_priv); diff --git a/drivers/net/wireless/cnss2/main.h b/drivers/net/wireless/cnss2/main.h index d27fd50c20e9..b8598f2b2a36 100644 --- a/drivers/net/wireless/cnss2/main.h +++ b/drivers/net/wireless/cnss2/main.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -205,6 +205,24 @@ enum cnss_debug_quirks { SKIP_DEVICE_BOOT, USE_CORE_ONLY_FW, SKIP_RECOVERY, + QMI_BYPASS, + ENABLE_WALTEST, + ENABLE_PCI_LINK_DOWN_PANIC, + FBC_BYPASS, + ENABLE_DAEMON_SUPPORT, +}; + +enum cnss_bdf_type { + CNSS_BDF_BIN, + CNSS_BDF_ELF, + CNSS_BDF_DUMMY = 255, +}; + +struct cnss_control_params { + unsigned long quirks; + unsigned int mhi_timeout; + unsigned int qmi_timeout; + unsigned int bdf_type; }; struct cnss_plat_data { @@ -252,11 +270,10 @@ struct cnss_plat_data { bool powered_on; char firmware_name[13]; struct completion rddm_complete; + struct cnss_control_params ctrl_params; }; struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev); -bool *cnss_get_qmi_bypass(void); -unsigned long *cnss_get_debug_quirks(void); int cnss_driver_event_post(struct cnss_plat_data *plat_priv, enum cnss_driver_event_type type, u32 flags, void *data); diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index 057d16159498..807ad90e3cc8 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -59,32 +59,7 @@ static DEFINE_SPINLOCK(pci_link_down_lock); -static unsigned int pci_link_down_panic; -module_param(pci_link_down_panic, uint, 0600); -MODULE_PARM_DESC(pci_link_down_panic, - "Trigger kernel panic when PCI link down is detected"); - -static bool fbc_bypass; -#ifdef CONFIG_CNSS2_DEBUG -module_param(fbc_bypass, bool, 0600); -MODULE_PARM_DESC(fbc_bypass, - "Bypass firmware download when loading WLAN driver"); -#endif - -#ifdef CONFIG_CNSS2_DEBUG -#ifdef CONFIG_CNSS_EMULATION -static unsigned int mhi_timeout = 90000; -#else -static unsigned int mhi_timeout; -#endif -module_param(mhi_timeout, uint, 0600); -MODULE_PARM_DESC(mhi_timeout, - "Timeout for MHI operation in milliseconds"); - -#define MHI_TIMEOUT_OVERWRITE_MS mhi_timeout -#else -#define MHI_TIMEOUT_OVERWRITE_MS 0 -#endif +#define MHI_TIMEOUT_OVERWRITE_MS (plat_priv->ctrl_params.mhi_timeout) static int cnss_set_pci_config_space(struct cnss_pci_data *pci_priv, bool save) { @@ -227,13 +202,16 @@ int cnss_pci_link_down(struct device *dev) unsigned long flags; struct pci_dev *pci_dev = to_pci_dev(dev); struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; if (!pci_priv) { cnss_pr_err("pci_priv is NULL!\n"); return -EINVAL; } - if (pci_link_down_panic) + plat_priv = pci_priv->plat_priv; + if (test_bit(ENABLE_PCI_LINK_DOWN_PANIC, + &plat_priv->ctrl_params.quirks)) panic("cnss: PCI link is down!\n"); spin_lock_irqsave(&pci_link_down_lock, flags); @@ -510,7 +488,7 @@ static int cnss_qca6290_powerup(struct cnss_pci_data *pci_priv) return 0; } - if (test_bit(USE_CORE_ONLY_FW, cnss_get_debug_quirks())) { + if (test_bit(USE_CORE_ONLY_FW, &plat_priv->ctrl_params.quirks)) { clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state); clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); return 0; @@ -518,7 +496,7 @@ static int cnss_qca6290_powerup(struct cnss_pci_data *pci_priv) cnss_set_pin_connect_status(plat_priv); - if (*cnss_get_qmi_bypass()) { + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) { ret = cnss_pci_call_driver_probe(pci_priv); if (ret) goto stop_mhi; @@ -919,6 +897,7 @@ static void cnss_pci_event_cb(struct msm_pcie_notify *notify) unsigned long flags; struct pci_dev *pci_dev; struct cnss_pci_data *pci_priv; + struct cnss_plat_data *plat_priv; if (!notify) return; @@ -931,9 +910,11 @@ static void cnss_pci_event_cb(struct msm_pcie_notify *notify) if (!pci_priv) return; + plat_priv = pci_priv->plat_priv; switch (notify->event) { case MSM_PCIE_EVENT_LINKDOWN: - if (pci_link_down_panic) + if (test_bit(ENABLE_PCI_LINK_DOWN_PANIC, + &plat_priv->ctrl_params.quirks)) panic("cnss: PCI link is down!\n"); spin_lock_irqsave(&pci_link_down_lock, flags); @@ -2346,13 +2327,15 @@ int cnss_pci_set_mhi_state(struct cnss_pci_data *pci_priv, int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv) { int ret = 0; + struct cnss_plat_data *plat_priv; if (!pci_priv) { cnss_pr_err("pci_priv is NULL!\n"); return -ENODEV; } - if (fbc_bypass) + plat_priv = pci_priv->plat_priv; + if (test_bit(FBC_BYPASS, &plat_priv->ctrl_params.quirks)) return 0; if (MHI_TIMEOUT_OVERWRITE_MS) @@ -2381,10 +2364,9 @@ void cnss_pci_stop_mhi(struct cnss_pci_data *pci_priv) return; } - if (fbc_bypass) - return; - plat_priv = pci_priv->plat_priv; + if (test_bit(FBC_BYPASS, &plat_priv->ctrl_params.quirks)) + return; cnss_pci_set_mhi_state_bit(pci_priv, CNSS_MHI_RESUME); if (!pci_priv->pci_link_down_ind) diff --git a/drivers/net/wireless/cnss2/qmi.c b/drivers/net/wireless/cnss2/qmi.c index 5f948a4c0abe..fc4f613213d7 100644 --- a/drivers/net/wireless/cnss2/qmi.c +++ b/drivers/net/wireless/cnss2/qmi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,35 +28,11 @@ #define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b" #define DUMMY_BDF_FILE_NAME "bdwlan.dmy" -enum cnss_bdf_type { - CNSS_BDF_BIN, - CNSS_BDF_ELF, - CNSS_BDF_DUMMY = 255, -}; - -#ifdef CONFIG_CNSS2_DEBUG -static unsigned int qmi_timeout = 10000; -module_param(qmi_timeout, uint, 0600); -MODULE_PARM_DESC(qmi_timeout, "Timeout for QMI message in milliseconds"); - -#define QMI_WLFW_TIMEOUT_MS qmi_timeout -#else -#define QMI_WLFW_TIMEOUT_MS 10000 -#endif +#define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout) #define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS) #define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K -static bool daemon_support = true; -module_param(daemon_support, bool, 0600); -MODULE_PARM_DESC(daemon_support, "User space has cnss-daemon support or not"); - -static unsigned int bdf_type = CNSS_BDF_ELF; -#ifdef CONFIG_CNSS2_DEBUG -module_param(bdf_type, uint, 0600); -MODULE_PARM_DESC(bdf_type, "Type of board data file to be downloaded"); -#endif - static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode) { switch (mode) { @@ -181,7 +157,11 @@ static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv) } req->num_clients_valid = 1; - req->num_clients = daemon_support ? 2 : 1; + if (test_bit(ENABLE_DAEMON_SUPPORT, + &plat_priv->ctrl_params.quirks)) + req->num_clients = 2; + else + req->num_clients = 1; cnss_pr_dbg("Number of clients is %d\n", req->num_clients); req->wake_msi = cnss_bus_get_wake_irq(plat_priv); @@ -449,7 +429,7 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) return -ENOMEM; } - switch (bdf_type) { + switch (plat_priv->ctrl_params.bdf_type) { case CNSS_BDF_ELF: if (plat_priv->board_info.board_id == 0xFF) snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME); @@ -473,7 +453,8 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) remaining = MAX_BDF_FILE_NAME; goto bypass_bdf; default: - cnss_pr_err("Invalid BDF type: %d\n", bdf_type); + cnss_pr_err("Invalid BDF type: %d\n", + plat_priv->ctrl_params.bdf_type); ret = -EINVAL; goto err_req_fw; } @@ -500,7 +481,7 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) req->data_valid = 1; req->end_valid = 1; req->bdf_type_valid = 1; - req->bdf_type = bdf_type; + req->bdf_type = plat_priv->ctrl_params.bdf_type; if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) { req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01; @@ -555,7 +536,7 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) return 0; err_send: - if (bdf_type != CNSS_BDF_DUMMY) + if (plat_priv->ctrl_params.bdf_type != CNSS_BDF_DUMMY) release_firmware(fw_entry); err_req_fw: CNSS_ASSERT(0); @@ -1070,7 +1051,7 @@ int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv, return ret; } -unsigned int cnss_get_qmi_timeout(void) +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv) { cnss_pr_dbg("QMI timeout is %u ms\n", QMI_WLFW_TIMEOUT_MS); diff --git a/drivers/net/wireless/cnss2/qmi.h b/drivers/net/wireless/cnss2/qmi.h index f1b97b8c1841..50a7b1cf7ed0 100644 --- a/drivers/net/wireless/cnss2/qmi.h +++ b/drivers/net/wireless/cnss2/qmi.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,7 +27,7 @@ struct cnss_qmi_event_server_arrive_data { int cnss_qmi_init(struct cnss_plat_data *plat_priv); void cnss_qmi_deinit(struct cnss_plat_data *plat_priv); -unsigned int cnss_get_qmi_timeout(void); +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv); int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data); int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv); int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv); @@ -59,7 +59,8 @@ static inline void cnss_qmi_deinit(struct cnss_plat_data *plat_priv) { } -static inline unsigned int cnss_get_qmi_timeout(void) +static inline +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv) { return QMI_WLFW_TIMEOUT_MS; } -- GitLab From da72ac7af6891c670ba18fb450f6158cd42c7c9a Mon Sep 17 00:00:00 2001 From: Zhen Kong Date: Fri, 4 Jan 2019 12:34:50 -0800 Subject: [PATCH 0751/1286] qseecom: fix listener_access_lock and unregister issues When __qseecom_reentrancy_process_incomplete_cmd() calls __qseecom_process_reentrancy_blocked_on_listener(), it should first release listener_access_lock, as both of them will take this mutex inside. Besides, when qseecom processes a pending listener unregister, it should make sure qseecom_release() is already called on this listener to avoid free this listener's private data, which will be used by qseecom_release. Change-Id: I9dd1937e57f9eaf9d440c13244c66ef9f6771671 Signed-off-by: Zhen Kong --- drivers/misc/qseecom.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 1a1b52b2caa9..58058addcc97 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -1,7 +1,7 @@ /* * QTI Secure Execution Environment Communicator (QSEECOM) driver * - * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -339,6 +339,7 @@ struct qseecom_client_handle { struct qseecom_listener_handle { u32 id; bool unregister_pending; + bool release_called; }; static struct qseecom_control qseecom; @@ -1473,6 +1474,9 @@ static void __qseecom_processing_pending_lsnr_unregister(void) if (entry && entry->data) { pr_debug("process pending unregister %d\n", entry->data->listener.id); + /* don't process if qseecom_release is not called*/ + if (!entry->data->listener.release_called) + break; ptr_svc = __qseecom_find_svc( entry->data->listener.id); if (ptr_svc) { @@ -2330,8 +2334,10 @@ static int __qseecom_reentrancy_process_incomplete_cmd( ret = -EINVAL; goto exit; } + mutex_unlock(&listener_access_lock); ret = __qseecom_process_reentrancy_blocked_on_listener( resp, NULL, data); + mutex_lock(&listener_access_lock); if (ret) { pr_err("failed to process App(%d) %s blocked on listener %d\n", data->client.app_id, @@ -7846,6 +7852,7 @@ static int qseecom_release(struct inode *inode, struct file *file) free_private_data = false; mutex_lock(&listener_access_lock); ret = qseecom_unregister_listener(data); + data->listener.release_called = true; mutex_unlock(&listener_access_lock); break; case QSEECOM_CLIENT_APP: -- GitLab From 7092864785b40117340438ae0b7bbe6f9c01deeb Mon Sep 17 00:00:00 2001 From: Venkat Chinta Date: Fri, 4 Jan 2019 13:59:07 -0800 Subject: [PATCH 0752/1286] msm: camera: vfe: Add missing reg data for VFE 175 hw This change adds missing debug config and status register offsets that are read during bus errors to report the type of violation. Change-Id: If244185fd0a2fdb502116203aaae9379d19e76d7 Signed-off-by: Venkat Chinta --- .../cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h index a409b32eb033..d322b27e846e 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -296,6 +296,8 @@ static struct cam_vfe_bus_ver2_hw_info vfe175_bus_hw_info = { .addr_sync_cfg = 0x0000207C, .addr_sync_frame_hdr = 0x00002080, .addr_sync_no_sync = 0x00002084, + .debug_status_cfg = 0x0000226C, + .debug_status_0 = 0x00002270, }, .num_client = 24, .bus_client_reg = { -- GitLab From e968d29f5f3199d7ef111ba803897194d60bbd97 Mon Sep 17 00:00:00 2001 From: Puja Gupta Date: Tue, 8 Jan 2019 14:13:25 -0800 Subject: [PATCH 0753/1286] Revert "sched/fair: Add overutilization condition to sync wakeup case" This reverts commit 1212399d ("sched/fair: Add overutilization condition to sync wakeup case"). The change causes regression in some usecases which use sync wakeup, hence revert the change. Change-Id: I905a992a2c4d44dfa9b45ef06f0ed4b1b49b0eeb Signed-off-by: Puja Gupta --- kernel/sched/fair.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index b1d38be9bfdc..dc245251e2f7 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -5786,8 +5786,7 @@ static inline bool bias_to_waker_cpu(struct task_struct *p, int cpu, struct cpumask *rtg_target) { bool base_test = cpumask_test_cpu(cpu, &p->cpus_allowed) && - cpu_active(cpu) && task_fits_max(p, cpu) && - !__cpu_overutilized(cpu, task_util(p)); + cpu_active(cpu) && task_fits_max(p, cpu); bool rtg_test = rtg_target && cpumask_test_cpu(cpu, rtg_target); return base_test && (!rtg_target || rtg_test); -- GitLab From f94c8d83c26117eac3792527915fc11a77cee603 Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Tue, 8 Jan 2019 14:58:27 -0800 Subject: [PATCH 0754/1286] ARM: dts: msm: Remove dma-coherent for IPA for sdxprairie There is no support for IO Coherency on 32bit system. Remove the configuration for IPA AP context bank. Change-Id: I74f9782770b2d768ca12f8961b2fe421b19daaa7 Signed-off-by: Ghanim Fodi --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index ad18311148b4..2fa03630eddd 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -530,7 +530,6 @@ /* modem tables in IMEM */ <0x14688000 0x14688000 0x3000>; qcom,ipa-q6-smem-size = <16384>; - dma-coherent; }; ipa_smmu_wlan: ipa_smmu_wlan { -- GitLab From fbc681fcd5e489c5af6a763f328425a48d344ef0 Mon Sep 17 00:00:00 2001 From: Abhinay Reddy Vanipally Date: Tue, 18 Dec 2018 21:39:04 -0800 Subject: [PATCH 0755/1286] ARM: dts: msm: Disable wigig on sdxprairie Disable wil6210/wigig on SM8150 sdxprairie platforms as they are not supported Change-Id: I93b91cfa163758d82eb69c1f0be4d1a9eb4c52ce Signed-off-by: Abhinay Reddy Vanipally --- arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index 9a03f62d737f..530be575c643 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -88,3 +88,7 @@ voice_mhi_voting; }; }; + +&wil6210 { + status = "disabled"; +}; -- GitLab From 70e9e3116757b62484ff5a854534919402764314 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Mon, 7 Jan 2019 10:43:54 +0800 Subject: [PATCH 0756/1286] scsi: ufs: fix a quirk macro definition error This change fixes the macro definition error of quirk UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH as it is conflicting with previous quirk UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME. Change-Id: I5198c29ad7cfd2e841b122f9c4f3a4980dadfbda Signed-off-by: Can Guo --- drivers/scsi/ufs/ufs_quirks.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h index 2aca9a75b67b..db3bff0595a1 100644 --- a/drivers/scsi/ufs/ufs_quirks.h +++ b/drivers/scsi/ufs/ufs_quirks.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -138,6 +138,6 @@ struct ufs_dev_fix { * HS-G1 to HS-G2 followed by HS-G2 to HS-G3. Enabling this quirk for such * device would apply this 2 steps gear switch workaround. */ -#define UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH (1 << 8) +#define UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH (1 << 9) #endif /* UFS_QUIRKS_H_ */ -- GitLab From ddeae048af2f64721d8d6ec3a7d7a01149779c1d Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Tue, 8 Jan 2019 11:05:26 -0800 Subject: [PATCH 0757/1286] msm: ipa: Vote for IPA clocks before SMMU attach SMMU TBU2 clock requires IPA clocks to be voted before attach. Change-Id: I8e620217de2611e1a9ddbad6516f84bbb0fac8a9 Signed-off-by: Ghanim Fodi --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index ce1c8098edea..d272026b4efd 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -5025,14 +5025,15 @@ static void ipa3_load_ipa_fw(struct work_struct *work) IPADBG("Entry\n"); + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + result = ipa3_attach_to_smmu(); if (result) { IPAERR("IPA attach to smmu failed %d\n", result); + IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); return; } - IPA_ACTIVE_CLIENTS_INC_SIMPLE(); - if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION && ((ipa3_ctx->platform_type != IPA_PLAT_TYPE_MDM) || (ipa3_ctx->ipa_hw_type >= IPA_HW_v3_5))) -- GitLab From dc2a08bf3510879efcc625dd61a3a6c7e477d698 Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Mon, 7 Jan 2019 15:12:58 -0800 Subject: [PATCH 0758/1286] power: smb5-lib: Add DT option to disable LPD feature Currently, the Liquid Presence Detection feature is enabled by default on USB Type-C port. However, it is may not be desired on some platforms that share this driver. Provide a DT option to switch LPD feature off. Change-Id: I5c08e9fe8bd1bdc569de8dafdd5f3616edadb629 Signed-off-by: Harry Yang --- .../bindings/power/supply/qcom/qpnp-smb5.txt | 7 +++ drivers/power/supply/qcom/qpnp-smb5.c | 6 +- drivers/power/supply/qcom/smb5-lib.c | 62 ++++++++++++------- drivers/power/supply/qcom/smb5-lib.h | 1 + 4 files changed, 53 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt index 4953eb5b8803..634f1dbd72a1 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt @@ -281,6 +281,13 @@ Charger specific properties: Definition: Boolean flag which when present disables USB-PD operation. Not applicable for PMI632, where PD is not supported. +- qcom,lpd-disable + Usage: optional + Value type: bool + Definition: Boolean flag which when present disables liquid presence + detection. Not applicable for PMI632, which does not + support Type-C port. + - qcom,hw-die-temp-mitigation Usage: optional Value type: bool diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index 64add8f6ffb0..ead705647574 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -407,6 +407,8 @@ static int smb5_parse_dt(struct smb5 *chip) chg->pd_not_supported = of_property_read_bool(node, "qcom,usb-pd-disable"); + chg->lpd_disabled = of_property_read_bool(node, "qcom,lpd-disable"); + rc = of_property_read_u32(node, "qcom,wd-bark-time-secs", &chip->dt.wd_bark_time); if (rc < 0 || chip->dt.wd_bark_time < MIN_WD_BARK_TIME) @@ -1791,10 +1793,10 @@ static int smb5_configure_typec(struct smb_charger *chg) return rc; } + val = chg->lpd_disabled ? 0 : TYPEC_WATER_DETECTION_INT_EN_BIT; /* Use simple write to enable only required interrupts */ rc = smblib_write(chg, TYPE_C_INTERRUPT_EN_CFG_2_REG, - TYPEC_SRC_BATT_HPWR_INT_EN_BIT | - TYPEC_WATER_DETECTION_INT_EN_BIT); + TYPEC_SRC_BATT_HPWR_INT_EN_BIT | val); if (rc < 0) { dev_err(chg->dev, "Couldn't configure Type-C interrupts rc=%d\n", rc); diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index 7f3717b3c499..680d9fe0b0d8 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -4828,6 +4828,9 @@ static bool smblib_src_lpd(struct smb_charger *chg) u8 stat; int rc; + if (chg->lpd_disabled) + return false; + rc = smblib_read(chg, TYPE_C_SRC_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_SRC_STATUS_REG rc=%d\n", @@ -5070,12 +5073,35 @@ static void smblib_handle_rp_change(struct smb_charger *chg, int typec_mode) chg->typec_mode, typec_mode); } +static void smblib_lpd_launch_ra_open_work(struct smb_charger *chg) +{ + u8 stat; + int rc; + + if (chg->lpd_disabled) + return; + + rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); + if (rc < 0) { + smblib_err(chg, "Couldn't read TYPE_C_MISC_STATUS_REG rc=%d\n", + rc); + return; + } + + if (!(stat & TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT) + && chg->lpd_stage == LPD_STAGE_NONE) { + chg->lpd_stage = LPD_STAGE_FLOAT; + cancel_delayed_work_sync(&chg->lpd_ra_open_work); + vote(chg->awake_votable, LPD_VOTER, true, 0); + schedule_delayed_work(&chg->lpd_ra_open_work, + msecs_to_jiffies(300)); + } +} + irqreturn_t typec_or_rid_detection_change_irq_handler(int irq, void *data) { struct smb_irq_data *irq_data = data; struct smb_charger *chg = irq_data->parent_data; - u8 stat; - int rc; smblib_dbg(chg, PR_INTERRUPT, "IRQ: %s\n", irq_data->name); @@ -5107,21 +5133,7 @@ irqreturn_t typec_or_rid_detection_change_irq_handler(int irq, void *data) if (chg->pr_swap_in_progress || chg->pd_hard_reset) goto out; - rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); - if (rc < 0) { - smblib_err(chg, "Couldn't read TYPE_C_MISC_STATUS_REG rc=%d\n", - rc); - goto out; - } - - if (!(stat & TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT) - && chg->lpd_stage == LPD_STAGE_NONE) { - chg->lpd_stage = LPD_STAGE_FLOAT; - cancel_delayed_work_sync(&chg->lpd_ra_open_work); - vote(chg->awake_votable, LPD_VOTER, true, 0); - schedule_delayed_work(&chg->lpd_ra_open_work, - msecs_to_jiffies(300)); - } + smblib_lpd_launch_ra_open_work(chg); if (chg->usb_psy) power_supply_changed(chg->usb_psy); @@ -5156,6 +5168,16 @@ irqreturn_t typec_state_change_irq_handler(int irq, void *data) return IRQ_HANDLED; } +static void smblib_lpd_clear_ra_open_work(struct smb_charger *chg) +{ + if (chg->lpd_disabled) + return; + + cancel_delayed_work_sync(&chg->lpd_detach_work); + chg->lpd_stage = LPD_STAGE_FLOAT_CANCEL; + cancel_delayed_work_sync(&chg->lpd_ra_open_work); + vote(chg->awake_votable, LPD_VOTER, false, 0); +} irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) { @@ -5174,10 +5196,8 @@ irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) } if (stat & TYPEC_ATTACH_DETACH_STATE_BIT) { - cancel_delayed_work_sync(&chg->lpd_detach_work); - chg->lpd_stage = LPD_STAGE_FLOAT_CANCEL; - cancel_delayed_work_sync(&chg->lpd_ra_open_work); - vote(chg->awake_votable, LPD_VOTER, false, 0); + + smblib_lpd_clear_ra_open_work(chg); rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); if (rc < 0) { diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h index bee121f36c0d..a9a510ad9aeb 100644 --- a/drivers/power/supply/qcom/smb5-lib.h +++ b/drivers/power/supply/qcom/smb5-lib.h @@ -470,6 +470,7 @@ struct smb_charger { int smb_temp_max; u8 typec_try_mode; enum lpd_stage lpd_stage; + bool lpd_disabled; enum lpd_reason lpd_reason; bool fcc_stepper_enable; int die_temp; -- GitLab From 480dbddc9b5261d9b4dbff60a169793ca943ef3a Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Mon, 7 Jan 2019 15:31:09 -0800 Subject: [PATCH 0759/1286] power: smb5: Disable liquid present detection feature for PMI632 PMI632 does not support water detection over type-C port. Disable it. As a result, water detection interrupt is also disabled. Change-Id: I3cd20beefb89862630be7157f749b2c775e61d42 Signed-off-by: Umang Agrawal Signed-off-by: Harry Yang --- drivers/power/supply/qcom/qpnp-smb5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index ead705647574..c5012b6d3b7c 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -303,6 +303,7 @@ static int smb5_chg_config_init(struct smb5 *chip) chg->name = "pmi632_charger"; /* PMI632 does not support PD */ chg->pd_not_supported = true; + chg->lpd_disabled = true; if (pmic_rev_id->rev4 >= 2) chg->uusb_moisture_protection_enabled = true; chg->hw_max_icl_ua = -- GitLab From 0ee6ca5d3f7f018222b846f0f104215b5072fabb Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Fri, 4 Jan 2019 09:37:35 -0500 Subject: [PATCH 0760/1286] msm: npu: Fix race condition issue during npu power contrl This chaneg is to fix race condition issue when enable/disable npu power. Change-Id: Ic24d81e448beee236bcd3a1fc5c93705925a6731 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_dev.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_dev.c b/drivers/media/platform/msm/npu/npu_dev.c index a646c692a6ac..f1314d729aba 100644 --- a/drivers/media/platform/msm/npu/npu_dev.c +++ b/drivers/media/platform/msm/npu/npu_dev.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -478,6 +478,7 @@ int npu_enable_core_power(struct npu_device *npu_dev) struct npu_pwrctrl *pwr = &npu_dev->pwrctrl; int ret = 0; + mutex_lock(&npu_dev->dev_lock); if (!pwr->pwr_vote_num) { ret = npu_enable_regulators(npu_dev); if (ret) @@ -492,6 +493,7 @@ int npu_enable_core_power(struct npu_device *npu_dev) npu_resume_devbw(npu_dev); } pwr->pwr_vote_num++; + mutex_unlock(&npu_dev->dev_lock); return ret; } @@ -501,8 +503,12 @@ void npu_disable_core_power(struct npu_device *npu_dev) struct npu_pwrctrl *pwr = &npu_dev->pwrctrl; struct npu_thermalctrl *thermalctrl = &npu_dev->thermalctrl; - if (!pwr->pwr_vote_num) + mutex_lock(&npu_dev->dev_lock); + if (!pwr->pwr_vote_num) { + mutex_unlock(&npu_dev->dev_lock); return; + } + pwr->pwr_vote_num--; if (!pwr->pwr_vote_num) { npu_suspend_devbw(npu_dev); @@ -514,6 +520,7 @@ void npu_disable_core_power(struct npu_device *npu_dev) pr_debug("setting back to power level=%d\n", pwr->active_pwrlevel); } + mutex_unlock(&npu_dev->dev_lock); } static int npu_enable_core_clocks(struct npu_device *npu_dev) -- GitLab From a34f0122416b4bdbb339efd45ba1e3a2624126a9 Mon Sep 17 00:00:00 2001 From: Junzhe Zou Date: Mon, 7 Jan 2019 14:06:05 -0800 Subject: [PATCH 0761/1286] msm: camera: isp: fix the bug in CSID stop polling function Fix the bug by only calling the polling function when resource mask is not NULL. Change-Id: Ic6501fc23ea75e95cbc3c84e5c8e44a38c6da78c Signed-off-by: Junzhe Zou --- .../cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index bad6ae25669a..7de599569c1d 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -2861,7 +2861,7 @@ static int cam_ife_csid_stop(void *hw_priv, } } - if (!res_mask) + if (res_mask) rc = cam_ife_csid_poll_stop_status(csid_hw, res_mask); for (i = 0; i < csid_stop->num_res; i++) { -- GitLab From 78f2c15fa279891f00294bb092b962449302144e Mon Sep 17 00:00:00 2001 From: Sudarshan Rajagopalan Date: Fri, 21 Dec 2018 12:17:59 -0800 Subject: [PATCH 0762/1286] ion: msm: Add User Contiguous Heap ID This new heap shall be used for ION heap allocations for HLOS and user applications. Change-Id: I38944ea6fc620c73c796eff1acb2f23e2c044330 Signed-off-by: Sudarshan Rajagopalan Signed-off-by: Liam Mark --- drivers/staging/android/ion/ion.h | 3 ++- drivers/staging/android/ion/msm/msm_ion_of.c | 6 +++++- drivers/staging/android/uapi/msm_ion.h | 1 + 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/staging/android/ion/ion.h b/drivers/staging/android/ion/ion.h index e7eb5b2d62f8..9e98c9c2f452 100644 --- a/drivers/staging/android/ion/ion.h +++ b/drivers/staging/android/ion/ion.h @@ -2,7 +2,7 @@ * drivers/staging/android/ion/ion.h * * Copyright (C) 2011 Google, Inc. - * Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -38,6 +38,7 @@ #define ION_MM_HEAP_NAME "mm" #define ION_SPSS_HEAP_NAME "spss" #define ION_SECURE_CARVEOUT_HEAP_NAME "secure_carveout" +#define ION_USER_CONTIG_HEAP_NAME "user_contig" #define ION_QSECOM_HEAP_NAME "qsecom" #define ION_QSECOM_TA_HEAP_NAME "qsecom_ta" #define ION_SECURE_HEAP_NAME "secure_heap" diff --git a/drivers/staging/android/ion/msm/msm_ion_of.c b/drivers/staging/android/ion/msm/msm_ion_of.c index 8d5f39fef59f..4580bd47f57c 100644 --- a/drivers/staging/android/ion/msm/msm_ion_of.c +++ b/drivers/staging/android/ion/msm/msm_ion_of.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,6 +48,10 @@ static struct ion_heap_desc ion_heap_meta[] = { .id = ION_CP_MM_HEAP_ID, .name = ION_MM_HEAP_NAME, }, + { + .id = ION_USER_CONTIG_HEAP_ID, + .name = ION_USER_CONTIG_HEAP_NAME, + }, { .id = ION_QSECOM_HEAP_ID, .name = ION_QSECOM_HEAP_NAME, diff --git a/drivers/staging/android/uapi/msm_ion.h b/drivers/staging/android/uapi/msm_ion.h index d6fbd510495b..846b76983152 100644 --- a/drivers/staging/android/uapi/msm_ion.h +++ b/drivers/staging/android/uapi/msm_ion.h @@ -49,6 +49,7 @@ enum ion_heap_ids { #define ION_QSECOM_TA_HEAP_ID 19 #define ION_AUDIO_HEAP_ID 28 #define ION_CAMERA_HEAP_ID 20 +#define ION_USER_CONTIG_HEAP_ID 26 /** * Flags to be used when allocating from the secure heap for * content protection -- GitLab From 7e3fc4b2595ee324c32924da355515b5e8cfd474 Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Tue, 25 Dec 2018 11:04:18 +0800 Subject: [PATCH 0763/1286] msm: camera: reqmgr: Fix frame sync issue on SAT mode Sync link doesn't have the corresponding req in req table if the sync link is streamed on after corresponding req. Add a initial sync req variable to record the startup request number. Change-Id: I4b6c97f106a95b766ae94956e4a35357de752ca0 Signed-off-by: Depeng Shao Signed-off-by: Karthik Anantha Ram --- .../msm/camera/cam_req_mgr/cam_req_mgr_core.c | 137 +++++++++++------- .../msm/camera/cam_req_mgr/cam_req_mgr_core.h | 8 +- 2 files changed, 92 insertions(+), 53 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c index ccf593f772fc..bc0680e854b4 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -46,6 +46,8 @@ void cam_req_mgr_core_link_reset(struct cam_req_mgr_core_link *link) link->sync_link_sof_skip = false; link->open_req_cnt = 0; link->last_flush_id = 0; + link->initial_sync_req = -1; + link->in_msync_mode = false; } void cam_req_mgr_handle_core_shutdown(void) @@ -641,6 +643,7 @@ static int __cam_req_mgr_check_sync_for_mslave( struct cam_req_mgr_slot *slot) { struct cam_req_mgr_core_link *sync_link = NULL; + struct cam_req_mgr_slot *sync_slot = NULL; int sync_slot_idx = 0, prev_idx, next_idx, rd_idx, rc = 0; int64_t req_id = 0, sync_req_id = 0; @@ -653,8 +656,10 @@ static int __cam_req_mgr_check_sync_for_mslave( req_id = slot->req_id; CAM_DBG(CAM_CRM, - "link_hdl %x req %lld frame_skip_flag %d ", - link->link_hdl, req_id, link->sync_link_sof_skip); + "link_hdl %x req %lld frame_skip_flag %d open_req_cnt:%d initial_sync_req [%lld,%lld] is_master:%d", + link->link_hdl, req_id, link->sync_link_sof_skip, + link->open_req_cnt, link->initial_sync_req, + sync_link->initial_sync_req, link->is_master); if (sync_link->sync_link_sof_skip) { CAM_DBG(CAM_CRM, @@ -696,7 +701,8 @@ static int __cam_req_mgr_check_sync_for_mslave( rd_idx = sync_link->req.in_q->rd_idx; sync_req_id = link->req.in_q->slot[prev_idx].req_id; - if (sync_req_id != -1) { + if ((sync_link->initial_sync_req != -1) && + (sync_link->initial_sync_req <= sync_req_id)) { sync_slot_idx = __cam_req_mgr_find_slot_for_req( sync_link->req.in_q, sync_req_id); @@ -734,23 +740,6 @@ static int __cam_req_mgr_check_sync_for_mslave( if (link->initial_skip) link->initial_skip = false; - sync_slot_idx = __cam_req_mgr_find_slot_for_req( - sync_link->req.in_q, req_id); - if (sync_slot_idx == -1) { - CAM_DBG(CAM_CRM, - "Req: %lld not found on link: %x [master]", - req_id, sync_link->link_hdl); - return -EINVAL; - } - - if (sync_link->req.in_q->slot[sync_slot_idx].status != - CRM_SLOT_STATUS_REQ_APPLIED) { - CAM_DBG(CAM_CRM, - "Req: %lld [master] not applied yet: %x", - req_id, sync_link->link_hdl); - return -EAGAIN; - } - rc = __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); if (rc) { CAM_DBG(CAM_CRM, @@ -760,6 +749,14 @@ static int __cam_req_mgr_check_sync_for_mslave( return rc; } + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, true); + if (rc) { + CAM_DBG(CAM_CRM, + "Req: %lld [slave] not ready on link: %x, rc=%d", + req_id, link->link_hdl, rc); + return rc; + } + next_idx = link->req.in_q->rd_idx; rd_idx = sync_link->req.in_q->rd_idx; __cam_req_mgr_inc_idx(&next_idx, @@ -767,34 +764,39 @@ static int __cam_req_mgr_check_sync_for_mslave( link->req.in_q->num_slots); sync_req_id = link->req.in_q->slot[next_idx].req_id; - sync_slot_idx = __cam_req_mgr_find_slot_for_req( - sync_link->req.in_q, sync_req_id); - if (sync_slot_idx == -1) { - CAM_DBG(CAM_CRM, - "Next Req: %lld [slave] not found on link: %x [master]", - sync_req_id, sync_link->link_hdl); - return -EINVAL; - } - if ((sync_link->req.in_q->slot[sync_slot_idx].status != - CRM_SLOT_STATUS_REQ_APPLIED) && - ((sync_slot_idx - rd_idx) >= 1) && - (sync_link->req.in_q->slot[rd_idx].status != - CRM_SLOT_STATUS_REQ_APPLIED)) { - CAM_DBG(CAM_CRM, - "Next Req: %lld [slave] not next on link: %x [master]", - sync_req_id, sync_link->link_hdl); - return -EINVAL; - } + if ((sync_link->initial_sync_req != -1) && + (sync_link->initial_sync_req <= sync_req_id)) { + sync_slot_idx = __cam_req_mgr_find_slot_for_req( + sync_link->req.in_q, sync_req_id); + if (sync_slot_idx == -1) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not found on link: %x [master]", + sync_req_id, sync_link->link_hdl); + return -EINVAL; + } - rc = __cam_req_mgr_check_link_is_ready(sync_link, - sync_slot_idx, true); - if (rc && (sync_link->req.in_q->slot[sync_slot_idx].status != - CRM_SLOT_STATUS_REQ_APPLIED)) { - CAM_DBG(CAM_CRM, - "Next Req: %lld [slave] not ready on [master] link: %x, rc=%d", - sync_req_id, sync_link->link_hdl, rc); - return rc; + if ((sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) && + ((sync_slot_idx - rd_idx) >= 1) && + (sync_link->req.in_q->slot[rd_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not next on link: %x [master]", + sync_req_id, sync_link->link_hdl); + return -EINVAL; + } + + sync_slot = &sync_link->req.in_q->slot[sync_slot_idx]; + rc = __cam_req_mgr_check_link_is_ready(sync_link, + sync_slot_idx, true); + if (rc && (sync_slot->status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not ready on [master] link: %x, rc=%d", + sync_req_id, sync_link->link_hdl, rc); + return rc; + } } } @@ -979,13 +981,31 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, if ((slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) && (link->sync_link)) { - if (link->is_master || link->sync_link->is_master) + if (link->is_master || link->sync_link->is_master) { + if (!link->in_msync_mode) { + CAM_DBG(CAM_CRM, + "Settings master-slave sync mode for link 0x%x", + link->link_hdl); + link->in_msync_mode = true; + } + rc = __cam_req_mgr_check_sync_for_mslave( link, slot); - else + } else { rc = __cam_req_mgr_check_sync_req_is_ready( link, slot); + } } else { + if (link->in_msync_mode) { + CAM_DBG(CAM_CRM, + "Settings master-slave non sync mode for link 0x%x", + link->link_hdl); + link->in_msync_mode = false; + link->initial_sync_req = -1; + if (link->sync_link) + link->sync_link->initial_sync_req = -1; + } + rc = __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); if (!rc) @@ -1710,9 +1730,11 @@ int cam_req_mgr_process_sched_req(void *priv, void *data) sched_req = (struct cam_req_mgr_sched_request *)&task_data->u; in_q = link->req.in_q; - CAM_DBG(CAM_CRM, "link_hdl %x req_id %lld at slot %d sync_mode %d", + CAM_DBG(CAM_CRM, + "link_hdl %x req_id %lld at slot %d sync_mode %d is_master:%d", sched_req->link_hdl, sched_req->req_id, - in_q->wr_idx, sched_req->sync_mode); + in_q->wr_idx, sched_req->sync_mode, + link->is_master); mutex_lock(&link->req.lock); slot = &in_q->slot[in_q->wr_idx]; @@ -1728,6 +1750,14 @@ int cam_req_mgr_process_sched_req(void *priv, void *data) slot->recover = sched_req->bubble_enable; link->open_req_cnt++; __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots); + + if (slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) { + if (link->initial_sync_req == -1) + link->initial_sync_req = slot->req_id; + } else { + link->initial_sync_req = -1; + } + mutex_unlock(&link->req.lock); end: @@ -2830,6 +2860,11 @@ int cam_req_mgr_sync_config( link1->initial_skip = false; link2->initial_skip = false; + link1->in_msync_mode = false; + link2->in_msync_mode = false; + link1->initial_sync_req = -1; + link2->initial_sync_req = -1; + if (sync_info->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) { link1->sync_link = link2; link2->sync_link = link1; diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h index 4abf147764b3..26f5426b67b0 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -314,7 +314,9 @@ struct cam_req_mgr_connected_device { * is assigned as master * @initial_skip : Flag to determine if slave has started streaming in * master-slave sync - * + * @in_msync_mode : Flag to determine if a link is in master-slave mode + * @initial_sync_req : The initial req which is required to sync with the + * other link */ struct cam_req_mgr_core_link { int32_t link_hdl; @@ -339,6 +341,8 @@ struct cam_req_mgr_core_link { atomic_t is_used; bool is_master; bool initial_skip; + bool in_msync_mode; + int64_t initial_sync_req; }; /** -- GitLab From fd7676fd5b91517b9e699095301e271c2b4a03e4 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Fri, 28 Dec 2018 18:55:43 -0800 Subject: [PATCH 0764/1286] msm: camera: reqmgr: Deliver matching frames for master-slave sync If an SOF is skipped on one link due to request packet unavailability, skip the corresponding SOF on the sync link as well. Change-Id: Ife894d22393eb87ae60e3af3af23225ec81d43f0 Signed-off-by: Karthik Anantha Ram --- .../platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c index bc0680e854b4..bda29b6bca01 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c @@ -691,6 +691,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Req: %lld [master] not ready on link: %x, rc=%d", req_id, link->link_hdl, rc); + link->sync_link_sof_skip = true; return rc; } @@ -710,6 +711,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Prev Req: %lld [master] not found on link: %x [slave]", sync_req_id, sync_link->link_hdl); + link->sync_link_sof_skip = true; return -EINVAL; } @@ -733,6 +735,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Req: %lld not ready on [slave] link: %x, rc=%d", sync_req_id, sync_link->link_hdl, rc); + link->sync_link_sof_skip = true; return rc; } } @@ -754,6 +757,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Req: %lld [slave] not ready on link: %x, rc=%d", req_id, link->link_hdl, rc); + link->sync_link_sof_skip = true; return rc; } @@ -773,6 +777,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Next Req: %lld [slave] not found on link: %x [master]", sync_req_id, sync_link->link_hdl); + link->sync_link_sof_skip = true; return -EINVAL; } @@ -795,6 +800,7 @@ static int __cam_req_mgr_check_sync_for_mslave( CAM_DBG(CAM_CRM, "Next Req: %lld [slave] not ready on [master] link: %x, rc=%d", sync_req_id, sync_link->link_hdl, rc); + link->sync_link_sof_skip = true; return rc; } } -- GitLab From 0ed8c7f0971d6762f01d7e72e9584f5d8811e839 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Thu, 3 Jan 2019 17:47:14 +0530 Subject: [PATCH 0765/1286] msm: camera: Adds state variable in mem manager Add state variable for camera mem manager to show initialization status. Ensure that all operations are rejected before initialization. Change-Id: I1ddbaaf6fbed59e4804476562c97f6895d99e916 Signed-off-by: Trishansh Bhardwaj --- .../msm/camera/cam_req_mgr/cam_mem_mgr.c | 61 ++++++++++++++++++- .../msm/camera/cam_req_mgr/cam_mem_mgr.h | 8 ++- 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c index 78937a75cecd..7a2cee1d1782 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,6 +25,7 @@ #include "cam_debug_util.h" static struct cam_mem_table tbl; +static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED); static int cam_mem_util_get_dma_dir(uint32_t flags) { @@ -146,6 +147,8 @@ int cam_mem_mgr_init(void) } mutex_init(&tbl.m_lock); + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED); + return 0; } @@ -186,6 +189,11 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, *len_ptr = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) return -EINVAL; @@ -231,6 +239,11 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) int idx; struct dma_buf *dmabuf = NULL; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!buf_handle || !vaddr_ptr || !len) return -EINVAL; @@ -275,6 +288,11 @@ int cam_mem_put_cpu_buf(int32_t buf_handle) int idx; struct dma_buf *dmabuf = NULL; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!buf_handle) return -EINVAL; @@ -316,6 +334,11 @@ int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) uint32_t cache_dir; unsigned long dmabuf_flag = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) return -EINVAL; @@ -605,6 +628,11 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) uintptr_t kvaddr = 0; size_t klen; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) { CAM_ERR(CAM_MEM, " Invalid argument"); return -EINVAL; @@ -722,6 +750,11 @@ int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd) dma_addr_t hw_vaddr = 0; size_t len = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd || (cmd->fd < 0)) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -929,6 +962,7 @@ static int cam_mem_mgr_cleanup_table(void) void cam_mem_mgr_deinit(void) { + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED); cam_mem_mgr_cleanup_table(); mutex_lock(&tbl.m_lock); bitmap_zero(tbl.bitmap, tbl.bits); @@ -1025,6 +1059,11 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) int idx; int rc; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -1073,6 +1112,11 @@ int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp || !out) { CAM_ERR(CAM_MEM, "Invalid params"); return -EINVAL; @@ -1193,6 +1237,11 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) int32_t idx; int rc; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -1241,6 +1290,11 @@ int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, int32_t smmu_hdl = 0; int32_t num_hdl = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp || !out) { CAM_ERR(CAM_MEM, "Invalid param(s)"); return -EINVAL; @@ -1330,6 +1384,11 @@ int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) int rc; int32_t smmu_hdl; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h index 4c75b0e043ec..91d1c3917d6f 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,6 +20,12 @@ #define CAM_MEM_BUFQ_MAX 1024 +/* Enum for possible mem mgr states */ +enum cam_mem_mgr_state { + CAM_MEM_MGR_UNINITIALIZED, + CAM_MEM_MGR_INITIALIZED, +}; + /*Enum for possible SMMU operations */ enum cam_smmu_mapping_client { CAM_SMMU_MAPPING_USER, -- GitLab From ef39d57e43aee14d2e18d21568e80a3c3bb049cb Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Mon, 7 Jan 2019 18:11:38 +0530 Subject: [PATCH 0766/1286] ARM: dts: sa6155p: Add device tree for ADP air/star v2 Add initial device tree for platform V2.0 of SA6155p ADP Air and star. Change-Id: Ifbd9e0ec69394f3be0beffa856703b82e2be0747 Signed-off-by: Venkata Rao Kakani --- arch/arm64/boot/dts/qcom/Makefile | 10 +++++-- .../dts/qcom/sa6155p-v2-adp-air-overlay.dts | 26 +++++++++++++++++++ .../boot/dts/qcom/sa6155p-v2-adp-air.dts | 22 ++++++++++++++++ .../dts/qcom/sa6155p-v2-adp-star-overlay.dts | 26 +++++++++++++++++++ .../boot/dts/qcom/sa6155p-v2-adp-star.dts | 22 ++++++++++++++++ 5 files changed, 104 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air.dts create mode 100644 arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 60a7eb7be2a9..b4b15e938ad7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -122,7 +122,9 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) sa6155-adp-star-overlay.dtbo \ sa6155p-adp-star-overlay.dtbo \ sa6155-adp-air-overlay.dtbo \ - sa6155p-adp-air-overlay.dtbo + sa6155p-adp-air-overlay.dtbo \ + sa6155p-v2-adp-star-overlay.dtbo \ + sa6155p-v2-adp-air-overlay.dtbo sm6150-rumi-overlay.dtbo-base := sm6150.dtb sm6150-qrd-overlay.dtbo-base := sm6150.dtb @@ -135,8 +137,10 @@ sm6150-usbc-minidp-idp-overlay.dtbo-base := sm6150.dtb sm6150-cmd-mode-display-idp-overlay.dtbo-base := sm6150.dtb sa6155-adp-star-overlay.dtbo-base := sa6155.dtb sa6155p-adp-star-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-star-overlay.dtbo-base := sa6155p.dtb sa6155-adp-air-overlay.dtbo-base := sa6155.dtb sa6155p-adp-air-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-air-overlay.dtbo-base := sa6155p.dtb else dtb-$(CONFIG_ARCH_SM6150) += sm6150-rumi.dtb \ sm6150-qrd.dtb \ @@ -150,7 +154,9 @@ dtb-$(CONFIG_ARCH_SM6150) += sm6150-rumi.dtb \ sa6155-adp-star.dtb \ sa6155p-adp-star.dtb \ sa6155-adp-air.dtb \ - sa6155p-adp-air.dtb + sa6155p-adp-air.dtb \ + sa6155p-v2-adp-star.dtb \ + sa6155p-v2-adp-air.dtb endif diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..db177128ce81 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air.dts new file mode 100644 index 000000000000..28050b4f7723 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts new file mode 100644 index 000000000000..e57b835aba88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>; + qcom,board-id = <0x010019 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star.dts new file mode 100644 index 000000000000..45338ae8631b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x010019 0>; +}; -- GitLab From 59056eba2f511457fd6a44c38762c63b4af04385 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 8 Jan 2019 12:30:27 +0530 Subject: [PATCH 0767/1286] Revert "usb: pd: Don't retry sending Source Capabilities if PD capable" Commit 25bdeb88e6f8 ("usb: pd: Don't retry sending Source Capabilities if PD capable") added a Soft Reset signal to the sink device that we already know is PD capable if send Source Capabilities fail instead of retrying for nCapsCount times. This change was initially made to fix HARD RESET compliance failure but later it got fixed in the compliance SW. Revert this since it leads to re-enumeration failure of Multiport adapter when Hard Reset signal comes if adapter is already connected. Change-Id: I46a407ddc7ee3e8845e480940a8f966c9083f04d Signed-off-by: Pratham Pratap --- drivers/usb/pd/policy_engine.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c index 5db71cbaa3f7..6bf1e8295024 100644 --- a/drivers/usb/pd/policy_engine.c +++ b/drivers/usb/pd/policy_engine.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2625,16 +2625,6 @@ static void usbpd_sm(struct work_struct *w) ret = pd_send_msg(pd, MSG_SOURCE_CAPABILITIES, default_src_caps, ARRAY_SIZE(default_src_caps), SOP_MSG); if (ret) { - if (pd->pd_connected) { - usbpd_set_state(pd, PE_SEND_SOFT_RESET); - break; - } - - /* - * Technically this is PE_SRC_Discovery, but we can - * handle it by setting a timer to come back to the - * same state for the next retry. - */ pd->caps_count++; if (pd->caps_count >= PD_CAPS_COUNT) { usbpd_dbg(&pd->dev, "Src CapsCounter exceeded, disabling PD\n"); -- GitLab From b4d423a3c31942966ef6f69967595275016a90ed Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 9 Jan 2019 11:35:52 +0530 Subject: [PATCH 0768/1286] ARM: dts: msm: Add icnss node on trinket Add icnss node to enable wlan on trinket, add entry for membase, CE interrupt vectors. Change-Id: I6248a279d9f54bd1a891848d1569cb9a7745e3d3 Signed-off-by: Sandeep Singh --- arch/arm64/boot/dts/qcom/trinket.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..eb9be1529810 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -757,6 +757,28 @@ #clock-cells = <1>; }; + icnss: qcom,icnss@C800000 { + status = "disabled"; + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>; + reg-names = "membase"; + interrupts = <0 358 0 /* CE0 */ >, + <0 359 0 /* CE1 */ >, + <0 360 0 /* CE2 */ >, + <0 361 0 /* CE3 */ >, + <0 362 0 /* CE4 */ >, + <0 363 0 /* CE5 */ >, + <0 364 0 /* CE6 */ >, + <0 365 0 /* CE7 */ >, + <0 366 0 /* CE8 */ >, + <0 367 0 /* CE9 */ >, + <0 368 0 /* CE10 */ >, + <0 369 0 /* CE11 */ >; + qcom,smmu-s1-bypass; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + }; + arm64-cpu-erp { compatible = "arm,arm64-cpu-erp"; interrupts = <0 43 4>, -- GitLab From fbf8d2be13892e146153935b9d3cd298b9cb25a4 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 29 Oct 2018 15:35:55 +0530 Subject: [PATCH 0769/1286] clk: qcom: smd: Add support for rpm clocks for TRINKET Add rpm smd clocks, PMIC and bus clocks which are required on TRINKET for clients to vote on. Keep active only vote on XO and 19.2MHz vote on cnoc and snoc clocks. Change-Id: Ife815cd4f4a0a49cd0f60350fc42e7dfe86ff41b Signed-off-by: Odelu Kukatla --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 127 ++++++++++- include/dt-bindings/clock/qcom,rpmcc.h | 208 ++++++++++-------- include/linux/soc/qcom/smd-rpm.h | 3 + 4 files changed, 244 insertions(+), 95 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index bf124fed3711..da78c0c117cd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -14,6 +14,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-qcs405", "qcom,rpmcc" + "qcom,rpmcc-trinket", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 66ce2dd7f892..750a78b26e5a 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Linaro Limited - * Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016-2019, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -709,10 +709,112 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs405 = { .num_clks = ARRAY_SIZE(qcs405_clks), }; +/* Trinket */ +DEFINE_CLK_SMD_RPM_BRANCH(trinket, bi_tcxo, bi_tcxo_ao, + QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM(trinket, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(trinket, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM_QDSS(trinket, qdss_clk, qdss_a_clk, + QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM(trinket, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1); +DEFINE_CLK_SMD_RPM(trinket, snoc_periph_clk, snoc_periph_a_clk, + QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(trinket, snoc_lpass_clk, snoc_lpass_a_clk, + QCOM_SMD_RPM_BUS_CLK, 5); + +/* SMD_XO_BUFFER */ +DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk1, ln_bb_clk1_a, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk2, ln_bb_clk2_a, 2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, ln_bb_clk3, ln_bb_clk3_a, 3); +DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(trinket, rf_clk2, rf_clk2_a, 5); + +/* Voter clocks */ +static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); +static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(cnoc_keepalive_a_clk, cnoc_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(snoc_keepalive_a_clk, snoc_a_clk, LONG_MAX); + +/* Branch Voter clocks */ +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_otg_clk, bi_tcxo); +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_pronto_clk, bi_tcxo); +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_mss_clk, bi_tcxo); +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_wlan_clk, bi_tcxo); +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_lpass_clk, bi_tcxo); +static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_pil_cdsp_clk, bi_tcxo); + +static struct clk_hw *trinket_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &trinket_bi_tcxo.hw, + [RPM_SMD_XO_A_CLK_SRC] = &trinket_bi_tcxo_ao.hw, + [RPM_SMD_SNOC_CLK] = &trinket_snoc_clk.hw, + [RPM_SMD_SNOC_A_CLK] = &trinket_snoc_a_clk.hw, + [RPM_SMD_BIMC_CLK] = &trinket_bimc_clk.hw, + [RPM_SMD_BIMC_A_CLK] = &trinket_bimc_a_clk.hw, + [RPM_SMD_QDSS_CLK] = &trinket_qdss_clk.hw, + [RPM_SMD_QDSS_A_CLK] = &trinket_qdss_a_clk.hw, + [RPM_SMD_RF_CLK1] = &trinket_rf_clk1.hw, + [RPM_SMD_RF_CLK1_A] = &trinket_rf_clk1_a.hw, + [RPM_SMD_RF_CLK2] = &trinket_rf_clk2.hw, + [RPM_SMD_RF_CLK2_A] = &trinket_rf_clk2_a.hw, + [RPM_SMD_LN_BB_CLK1] = &trinket_ln_bb_clk1.hw, + [RPM_SMD_LN_BB_CLK1_A] = &trinket_ln_bb_clk1_a.hw, + [RPM_SMD_LN_BB_CLK2] = &trinket_ln_bb_clk2.hw, + [RPM_SMD_LN_BB_CLK2_A] = &trinket_ln_bb_clk2_a.hw, + [RPM_SMD_LN_BB_CLK3] = &trinket_ln_bb_clk3.hw, + [RPM_SMD_LN_BB_CLK3_A] = &trinket_ln_bb_clk3_a.hw, + [RPM_SMD_CNOC_CLK] = &trinket_cnoc_clk.hw, + [RPM_SMD_CNOC_A_CLK] = &trinket_cnoc_a_clk.hw, + [RPM_SMD_CE1_CLK] = &trinket_ce1_clk.hw, + [RPM_SMD_CE1_A_CLK] = &trinket_ce1_a_clk.hw, + [CNOC_MSMBUS_CLK] = &cnoc_msmbus_clk.hw, + [CNOC_MSMBUS_A_CLK] = &cnoc_msmbus_a_clk.hw, + [SNOC_KEEPALIVE_A_CLK] = &snoc_keepalive_a_clk.hw, + [CNOC_KEEPALIVE_A_CLK] = &cnoc_keepalive_a_clk.hw, + [SNOC_MSMBUS_CLK] = &snoc_msmbus_clk.hw, + [SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw, + [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, + [BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw, + [MCD_CE1_CLK] = &mcd_ce1_clk.hw, + [QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw, + [QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw, + [QSEECOM_CE1_CLK] = &qseecom_ce1_clk.hw, + [SCM_CE1_CLK] = &scm_ce1_clk.hw, + [CXO_SMD_OTG_CLK] = &bi_tcxo_otg_clk.hw, + [CXO_SMD_PIL_PRONTO_CLK] = &bi_tcxo_pil_pronto_clk.hw, + [CXO_SMD_PIL_MSS_CLK] = &bi_tcxo_pil_mss_clk.hw, + [CXO_SMD_WLAN_CLK] = &bi_tcxo_wlan_clk.hw, + [CXO_SMD_PIL_LPASS_CLK] = &bi_tcxo_pil_lpass_clk.hw, + [CXO_SMD_PIL_CDSP_CLK] = &bi_tcxo_pil_cdsp_clk.hw, + [RPM_SMD_IPA_CLK] = &trinket_ipa_clk.hw, + [RPM_SMD_IPA_A_CLK] = &trinket_ipa_a_clk.hw, + [RPM_SMD_QUP_CLK] = &trinket_qup_clk.hw, + [RPM_SMD_QUP_A_CLK] = &trinket_qup_a_clk.hw, + [RPM_SMD_MMRT_CLK] = &trinket_mmrt_clk.hw, + [RPM_SMD_MMRT_A_CLK] = &trinket_mmrt_a_clk.hw, + [RPM_SMD_MMNRT_CLK] = &trinket_mmnrt_clk.hw, + [RPM_SMD_MMNRT_A_CLK] = &trinket_mmnrt_a_clk.hw, + [RPM_SMD_SNOC_PERIPH_CLK] = &trinket_snoc_periph_clk.hw, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &trinket_snoc_periph_a_clk.hw, + [RPM_SMD_SNOC_LPASS_CLK] = &trinket_snoc_lpass_clk.hw, + [RPM_SMD_SNOC_LPASS_A_CLK] = &trinket_snoc_lpass_a_clk.hw, +}; + +static const struct rpm_smd_clk_desc rpm_clk_trinket = { + .clks = trinket_clks, + .num_rpm_clks = RPM_SMD_LN_BB_CLK3_A, + .num_clks = ARRAY_SIZE(trinket_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-qcs405", .data = &rpm_clk_qcs405 }, + { .compatible = "qcom,rpmcc-trinket", .data = &rpm_clk_trinket }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); @@ -723,17 +825,24 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) struct clk *clk; struct rpm_cc *rcc; struct clk_onecell_data *data; - int ret, is_qcs405; + int ret, is_qcs405, is_trinket; size_t num_clks, i; struct clk_hw **hw_clks; const struct rpm_smd_clk_desc *desc; is_qcs405 = of_device_is_compatible(pdev->dev.of_node, "qcom,rpmcc-qcs405"); + + is_trinket = of_device_is_compatible(pdev->dev.of_node, + "qcom,rpmcc-trinket"); if (is_qcs405) { ret = clk_vote_bimc(&qcs405_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; + } else if (is_trinket) { + ret = clk_vote_bimc(&trinket_bimc_clk.hw, INT_MAX); + if (ret < 0) + return ret; } desc = of_device_get_match_data(&pdev->dev); @@ -809,6 +918,20 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) /* Hold an active set vote for the pnoc_keepalive_a_clk */ clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000); clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); + } else if (is_trinket) { + /* + * Keep an active vote on CXO in case no other driver + * votes for it. + */ + clk_prepare_enable(trinket_bi_tcxo_ao.hw.clk); + + /* Hold an active set vote for the cnoc_keepalive_a_clk */ + clk_set_rate(cnoc_keepalive_a_clk.hw.clk, 19200000); + clk_prepare_enable(cnoc_keepalive_a_clk.hw.clk); + + /* Hold an active set vote for the snoc_keepalive_a_clk */ + clk_set_rate(snoc_keepalive_a_clk.hw.clk, 19200000); + clk_prepare_enable(snoc_keepalive_a_clk.hw.clk); } dev_info(&pdev->dev, "Registered RPM clocks\n"); diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index a0876ac455d8..a76ab72c4875 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -49,98 +49,120 @@ #define RPM_SMD_BIMC_A_CLK 7 #define RPM_SMD_QDSS_CLK 8 #define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_QPIC_CLK 64 -#define RPM_SMD_QPIC_A_CLK 65 -#define RPM_SMD_CE1_CLK 66 -#define RPM_SMD_CE1_A_CLK 67 -#define RPM_SMD_BIMC_GPU_CLK 68 -#define RPM_SMD_BIMC_GPU_A_CLK 69 -#define RPM_SMD_LN_BB_CLK 70 -#define RPM_SMD_LN_BB_CLK_A 71 -#define RPM_SMD_LN_BB_CLK_PIN 72 -#define RPM_SMD_LN_BB_CLK_A_PIN 73 -#define RPM_SMD_RF_CLK3 74 -#define RPM_SMD_RF_CLK3_A 75 -#define RPM_SMD_RF_CLK3_PIN 76 -#define RPM_SMD_RF_CLK3_A_PIN 77 -#define PNOC_MSMBUS_CLK 78 -#define PNOC_MSMBUS_A_CLK 79 -#define PNOC_KEEPALIVE_A_CLK 80 -#define SNOC_MSMBUS_CLK 81 -#define SNOC_MSMBUS_A_CLK 82 -#define BIMC_MSMBUS_CLK 83 -#define BIMC_MSMBUS_A_CLK 84 -#define PNOC_USB_CLK 85 -#define PNOC_USB_A_CLK 86 -#define SNOC_USB_CLK 87 -#define SNOC_USB_A_CLK 88 -#define BIMC_USB_CLK 89 -#define BIMC_USB_A_CLK 90 -#define SNOC_WCNSS_A_CLK 91 -#define BIMC_WCNSS_A_CLK 92 -#define MCD_CE1_CLK 93 -#define QCEDEV_CE1_CLK 94 -#define QCRYPTO_CE1_CLK 95 -#define QSEECOM_CE1_CLK 96 -#define SCM_CE1_CLK 97 -#define CXO_SMD_OTG_CLK 98 -#define CXO_SMD_LPM_CLK 99 -#define CXO_SMD_PIL_PRONTO_CLK 100 -#define CXO_SMD_PIL_MSS_CLK 101 -#define CXO_SMD_WLAN_CLK 102 -#define CXO_SMD_PIL_LPASS_CLK 103 -#define CXO_SMD_PIL_CDSP_CLK 104 +#define RPM_SMD_IPA_CLK 10 +#define RPM_SMD_IPA_A_CLK 11 +#define RPM_SMD_QUP_CLK 12 +#define RPM_SMD_QUP_A_CLK 13 +#define RPM_SMD_MMRT_CLK 14 +#define RPM_SMD_MMRT_A_CLK 15 +#define RPM_SMD_MMNRT_CLK 16 +#define RPM_SMD_MMNRT_A_CLK 17 +#define RPM_SMD_SNOC_PERIPH_CLK 18 +#define RPM_SMD_SNOC_PERIPH_A_CLK 19 +#define RPM_SMD_SNOC_LPASS_CLK 20 +#define RPM_SMD_SNOC_LPASS_A_CLK 21 +#define RPM_SMD_BB_CLK1 22 +#define RPM_SMD_BB_CLK1_A 23 +#define RPM_SMD_BB_CLK2 24 +#define RPM_SMD_BB_CLK2_A 25 +#define RPM_SMD_RF_CLK1 26 +#define RPM_SMD_RF_CLK1_A 27 +#define RPM_SMD_RF_CLK2 28 +#define RPM_SMD_RF_CLK2_A 29 +#define RPM_SMD_BB_CLK1_PIN 30 +#define RPM_SMD_BB_CLK1_A_PIN 31 +#define RPM_SMD_BB_CLK2_PIN 32 +#define RPM_SMD_BB_CLK2_A_PIN 33 +#define RPM_SMD_RF_CLK1_PIN 34 +#define RPM_SMD_RF_CLK1_A_PIN 35 +#define RPM_SMD_RF_CLK2_PIN 36 +#define RPM_SMD_RF_CLK2_A_PIN 37 +#define RPM_SMD_PNOC_CLK 38 +#define RPM_SMD_PNOC_A_CLK 39 +#define RPM_SMD_CNOC_CLK 40 +#define RPM_SMD_CNOC_A_CLK 41 +#define RPM_SMD_MMSSNOC_AHB_CLK 42 +#define RPM_SMD_MMSSNOC_AHB_A_CLK 43 +#define RPM_SMD_GFX3D_CLK_SRC 44 +#define RPM_SMD_GFX3D_A_CLK_SRC 45 +#define RPM_SMD_OCMEMGX_CLK 46 +#define RPM_SMD_OCMEMGX_A_CLK 47 +#define RPM_SMD_CXO_D0 48 +#define RPM_SMD_CXO_D0_A 49 +#define RPM_SMD_CXO_D1 50 +#define RPM_SMD_CXO_D1_A 51 +#define RPM_SMD_CXO_A0 52 +#define RPM_SMD_CXO_A0_A 53 +#define RPM_SMD_CXO_A1 54 +#define RPM_SMD_CXO_A1_A 55 +#define RPM_SMD_CXO_A2 56 +#define RPM_SMD_CXO_A2_A 57 +#define RPM_SMD_DIV_CLK1 58 +#define RPM_SMD_DIV_A_CLK1 59 +#define RPM_SMD_DIV_CLK2 60 +#define RPM_SMD_DIV_A_CLK2 61 +#define RPM_SMD_DIFF_CLK 62 +#define RPM_SMD_DIFF_A_CLK 63 +#define RPM_SMD_CXO_D0_PIN 64 +#define RPM_SMD_CXO_D0_A_PIN 65 +#define RPM_SMD_CXO_D1_PIN 66 +#define RPM_SMD_CXO_D1_A_PIN 67 +#define RPM_SMD_CXO_A0_PIN 68 +#define RPM_SMD_CXO_A0_A_PIN 69 +#define RPM_SMD_CXO_A1_PIN 70 +#define RPM_SMD_CXO_A1_A_PIN 71 +#define RPM_SMD_CXO_A2_PIN 72 +#define RPM_SMD_CXO_A2_A_PIN 73 +#define RPM_SMD_QPIC_CLK 74 +#define RPM_SMD_QPIC_A_CLK 75 +#define RPM_SMD_CE1_CLK 76 +#define RPM_SMD_CE1_A_CLK 77 +#define RPM_SMD_BIMC_GPU_CLK 78 +#define RPM_SMD_BIMC_GPU_A_CLK 79 +#define RPM_SMD_LN_BB_CLK 80 +#define RPM_SMD_LN_BB_CLK_A 81 +#define RPM_SMD_LN_BB_CLK_PIN 82 +#define RPM_SMD_LN_BB_CLK_A_PIN 83 +#define RPM_SMD_RF_CLK3 84 +#define RPM_SMD_RF_CLK3_A 85 +#define RPM_SMD_RF_CLK3_PIN 86 +#define RPM_SMD_RF_CLK3_A_PIN 87 +#define RPM_SMD_LN_BB_CLK1 88 +#define RPM_SMD_LN_BB_CLK1_A 89 +#define RPM_SMD_LN_BB_CLK2 90 +#define RPM_SMD_LN_BB_CLK2_A 91 +#define RPM_SMD_LN_BB_CLK3 92 +#define RPM_SMD_LN_BB_CLK3_A 93 +#define PNOC_MSMBUS_CLK 94 +#define PNOC_MSMBUS_A_CLK 95 +#define PNOC_KEEPALIVE_A_CLK 96 +#define SNOC_MSMBUS_CLK 97 +#define SNOC_MSMBUS_A_CLK 98 +#define BIMC_MSMBUS_CLK 99 +#define BIMC_MSMBUS_A_CLK 100 +#define PNOC_USB_CLK 101 +#define PNOC_USB_A_CLK 102 +#define SNOC_USB_CLK 103 +#define SNOC_USB_A_CLK 104 +#define BIMC_USB_CLK 105 +#define BIMC_USB_A_CLK 106 +#define SNOC_WCNSS_A_CLK 107 +#define BIMC_WCNSS_A_CLK 108 +#define MCD_CE1_CLK 109 +#define QCEDEV_CE1_CLK 110 +#define QCRYPTO_CE1_CLK 111 +#define QSEECOM_CE1_CLK 112 +#define SCM_CE1_CLK 113 +#define CXO_SMD_OTG_CLK 114 +#define CXO_SMD_LPM_CLK 115 +#define CXO_SMD_PIL_PRONTO_CLK 116 +#define CXO_SMD_PIL_MSS_CLK 117 +#define CXO_SMD_WLAN_CLK 118 +#define CXO_SMD_PIL_LPASS_CLK 119 +#define CXO_SMD_PIL_CDSP_CLK 120 +#define CNOC_MSMBUS_CLK 121 +#define CNOC_MSMBUS_A_CLK 122 +#define CNOC_KEEPALIVE_A_CLK 123 +#define SNOC_KEEPALIVE_A_CLK 124 #endif diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 5946731cd22e..8ca0e33b467f 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -28,6 +28,9 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_SPDM 0x63707362 #define QCOM_SMD_RPM_VSA 0x00617376 #define QCOM_SMD_RPM_CE_CLK 0x00006563 +#define QCOM_SMD_RPM_IPA_CLK 0x00617069 +#define QCOM_SMD_RPM_QUP_CLK 0x00707571 +#define QCOM_SMD_RPM_MMXI_CLK 0x69786D6D int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, -- GitLab From 32a46be46e8ba2a7d8505a62d5b1ef36ee85c0da Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 29 Oct 2018 12:23:36 +0530 Subject: [PATCH 0770/1286] clk: qcom: Add GCC clock driver for TRINKET Add support for peripheral and camera clocks controlled by global clock controller. Change-Id: Ie496cd111352ea287149b1b5498b30ef2754b285 Signed-off-by: Odelu Kukatla --- .../devicetree/bindings/clock/qcom,gcc.txt | 1 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-trinket.c | 4527 +++++++++++++++++ drivers/clk/qcom/vdd-level-trinket.h | 66 + include/dt-bindings/clock/qcom,gcc-trinket.h | 482 +- 6 files changed, 4827 insertions(+), 260 deletions(-) create mode 100644 drivers/clk/qcom/gcc-trinket.c create mode 100644 drivers/clk/qcom/vdd-level-trinket.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 3f5087692ccf..7f37d44a9167 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -26,6 +26,7 @@ Required properties : "qcom,gcc-sm6150" "qcom,gcc-sdmmagpie" "qcom,gcc-sdxprairie" + "qcom,gcc-trinket" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index fd8f4faaa963..75d2e599b04f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -502,3 +502,13 @@ config CLOCK_CPU_SDXPRAIRIE based devices. Say Y if you want to support CPU clock scaling using CPUfreq drivers for dynamic power management. + +config SM_GCC_TRINKET + tristate "TRINKET Global Clock Controller" + depends on COMMON_CLK_QCOM + select QCOM_GDSC + help + Support for the global clock controller on Qualcomm Technologies, Inc + TRINKET devices. + Say Y if you want to use peripheral devices such as UART, SPI, I2C, + USB, UFS, SD/eMMC, PCIe, etc. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ba1ab3e173db..c582b9a7a219 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-y += mdss/ diff --git a/drivers/clk/qcom/gcc-trinket.c b/drivers/clk/qcom/gcc-trinket.c new file mode 100644 index 000000000000..7537714650ae --- /dev/null +++ b/drivers/clk/qcom/gcc-trinket.c @@ -0,0 +1,4527 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "reset.h" +#include "vdd-level-trinket.h" + +#define GCC_VIDEO_MISC 0x80258 + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); + +enum { + P_BI_TCXO, + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_AUX2, + P_GPLL0_OUT_EARLY, + P_GPLL3_OUT_EARLY, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_EARLY, + P_GPLL6_OUT_MAIN, + P_GPLL7_OUT_MAIN, + P_GPLL8_OUT_EARLY, + P_GPLL8_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_0[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll0_out_aux2", + "core_bi_pll_test_se", +}; + +static const char * const gcc_parent_names_0_ao[] = { + "bi_tcxo_ao", + "gpll0_out_early", + "gpll0_out_aux2", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL6_OUT_MAIN, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_1[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll0_out_aux2", + "gpll6_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_2[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll0_out_aux2", + "sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL5_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_3[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll5_out_main", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_4[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll9_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_5[] = { + "bi_tcxo", + "gpll0_out_early", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_6[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_7[] = { + "bi_tcxo", + "gpll0_out_early", + "sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EARLY, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_8[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll9_out_main", + "gpll6_out_early", + "gpll8_out_main", + "gpll4_out_main", + "gpll3_out_early", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_9[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll8_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_10[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_MAIN, 4 }, + { P_GPLL3_OUT_EARLY, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_10[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll9_out_main", + "gpll6_out_early", + "gpll8_out_main", + "gpll3_out_early", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_11[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL8_OUT_EARLY, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_11[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll8_out_early", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_12[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL6_OUT_EARLY, 3 }, + { P_GPLL8_OUT_EARLY, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_12[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll6_out_early", + "gpll8_out_early", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_13[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_EARLY, 1 }, + { P_GPLL0_OUT_AUX2, 2 }, + { P_GPLL7_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_13[] = { + "bi_tcxo", + "gpll0_out_early", + "gpll0_out_aux2", + "gpll7_out_main", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_14[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_14[] = { + "bi_tcxo", + "sleep_clk", + "core_bi_pll_test_se", +}; + +static struct clk_alpha_pll gpll0_out_early = { + .offset = 0x0, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_early", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_aux2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_aux2", + .parent_names = (const char *[]){ "gpll0_out_early" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor gpll0_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]){ "gpll0_out_early" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll3_out_early = { + .offset = 0x3000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gpll3_out_early", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x4000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll5_out_main = { + .offset = 0x5000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll5_out_main", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll6_out_early = { + .offset = 0x6000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_early", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll6_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_main", + .parent_names = (const char *[]){ "gpll6_out_early" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll7_out_main = { + .offset = 0x7000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll7_out_main", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll8_out_early = { + .offset = 0x8000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gpll8_out_early", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll8_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll8_out_main", + .parent_names = (const char *[]){ "gpll8_out_early" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll9_out_early = { + .offset = 0x9000, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gpll9_out_early", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll9_out_main = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll9_out_main", + .parent_names = (const char *[]){ "gpll9_out_early" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0), + F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ahb_clk_src = { + .cmd_rcgr = 0x56088, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_9, + .freq_tbl = ftbl_gcc_camss_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ahb_clk_src", + .parent_names = gcc_parent_names_9, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 40000000, + [VDD_NOMINAL] = 80000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { + F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0), + F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cci_clk_src = { + .cmd_rcgr = 0x52004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 37500000, + [VDD_LOW] = 50000000, + [VDD_NOMINAL] = 100000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = { + F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0), + F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0), + F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0), + F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cpp_clk_src = { + .cmd_rcgr = 0x560c8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_10, + .freq_tbl = ftbl_gcc_camss_cpp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_clk_src", + .parent_names = gcc_parent_names_10, + .num_parents = 7, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 120000000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 384000000, + [VDD_NOMINAL] = 480000000, + [VDD_NOMINAL_L1] = 533000000, + [VDD_HIGH] = 576000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0), + F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0_clk_src = { + .cmd_rcgr = 0x55030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 311000000, + [VDD_NOMINAL] = 403200000, + [VDD_NOMINAL_L1] = 466500000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { + .cmd_rcgr = 0x53004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 268800000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1_clk_src = { + .cmd_rcgr = 0x5506c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 311000000, + [VDD_NOMINAL] = 403200000, + [VDD_NOMINAL_L1] = 466500000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { + .cmd_rcgr = 0x53024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 268800000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi2_clk_src = { + .cmd_rcgr = 0x550a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 311000000, + [VDD_NOMINAL] = 403200000, + [VDD_NOMINAL_L1] = 466500000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { + .cmd_rcgr = 0x53044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 268800000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi3_clk_src = { + .cmd_rcgr = 0x550e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 311000000, + [VDD_NOMINAL] = 403200000, + [VDD_NOMINAL_L1] = 466500000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = { + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0), + F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csiphy_clk_src = { + .cmd_rcgr = 0x55000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_11, + .freq_tbl = ftbl_gcc_camss_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy_clk_src", + .parent_names = gcc_parent_names_11, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 268800000, + [VDD_NOMINAL] = 320000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = { + F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_gp0_clk_src = { + .cmd_rcgr = 0x50000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp0_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_gp1_clk_src = { + .cmd_rcgr = 0x5001c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp1_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = { + F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0), + F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), + F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0), + F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0), + F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_jpeg_clk_src = { + .cmd_rcgr = 0x52028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_12, + .freq_tbl = ftbl_gcc_camss_jpeg_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_clk_src", + .parent_names = gcc_parent_names_12, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 66666667, + [VDD_LOW] = 133333333, + [VDD_LOW_L1] = 219428571, + [VDD_NOMINAL] = 320000000, + [VDD_NOMINAL_L1] = 480000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { + F(64000000, P_GPLL9_OUT_MAIN, 9, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_mclk0_clk_src = { + .cmd_rcgr = 0x51000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 64000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk1_clk_src = { + .cmd_rcgr = 0x5101c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 64000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk2_clk_src = { + .cmd_rcgr = 0x51038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 64000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk3_clk_src = { + .cmd_rcgr = 0x51054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 64000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = { + F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0), + F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0), + F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0), + F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_vfe0_clk_src = { + .cmd_rcgr = 0x54010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = 8, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 120000000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 403200000, + [VDD_NOMINAL] = 480000000, + [VDD_NOMINAL_L1] = 533000000, + [VDD_HIGH] = 576000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_vfe1_clk_src = { + .cmd_rcgr = 0x54048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_vfe0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = 8, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 120000000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 403200000, + [VDD_NOMINAL] = 480000000, + [VDD_NOMINAL_L1] = 533000000, + [VDD_HIGH] = 576000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { + .cmd_rcgr = 0x2b13c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk_src", + .parent_names = gcc_parent_names_0_ao, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx_ao, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 50000000, + [VDD_NOMINAL] = 100000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x4d004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x4e004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x4f004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x20010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 60000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75), + F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25), + F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75), + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15), + F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375), + F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75), + F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0), + F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x1f148, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x1f278, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x1f3a8, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x1f4d8, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x1f608, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x1f738, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { + .cmd_rcgr = 0x39148, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { + .cmd_rcgr = 0x39278, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { + .cmd_rcgr = 0x393a8, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { + .cmd_rcgr = 0x394d8, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { + .cmd_rcgr = 0x39608, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, + +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { + .cmd_rcgr = 0x39738, + .mnd_width = 16, + .hid_width = 5, + .enable_safe_config = true, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3), + F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x38028, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_NOMINAL] = 384000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x38010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 150000000, + [VDD_NOMINAL] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0), + F(202000000, P_GPLL7_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1e00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_13, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_names = gcc_parent_names_13, + .num_parents = 6, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 208000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), + F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x45020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .flags = FORCE_ENABLE_RCG, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000, + [VDD_HIGH] = 240000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), + F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x45048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .flags = FORCE_ENABLE_RCG, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 150000000, + [VDD_NOMINAL] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x4507c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .flags = FORCE_ENABLE_RCG, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0), + F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x45060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, + .flags = FORCE_ENABLE_RCG, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 37500000, + [VDD_LOW] = 75000000, + [VDD_NOMINAL] = 150000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0), + F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0x1a01c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 66666667, + [VDD_LOW] = 133333333, + [VDD_NOMINAL] = 200000000, + [VDD_HIGH] = 240000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0), + F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 20000000, + [VDD_LOW] = 60000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0x1a060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_14, + .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_names = gcc_parent_names_14, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static struct clk_rcg2 gcc_vs_ctrl_clk_src = { + .cmd_rcgr = 0x42030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0), + F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_vsensor_clk_src = { + .cmd_rcgr = 0x42018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_vsensor_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_vsensor_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 600000000}, + }, +}; + +static struct clk_branch gcc_ahb2phy_csi_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_csi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy_usb_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_usb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apc_vs_clk = { + .halt_reg = 0x4204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apc_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_axi_clk = { + .halt_reg = 0x71154, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x71154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x23004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_xo_clk = { + .halt_reg = 0x17028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_ahb_clk = { + .halt_reg = 0x52020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_clk = { + .halt_reg = 0x5201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_clk", + .parent_names = (const char *[]){ + "gcc_camss_cci_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid0_clk = { + .halt_reg = 0x5504c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5504c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid0_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid1_clk = { + .halt_reg = 0x55088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid1_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid2_clk = { + .halt_reg = 0x550c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550c0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid2_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_csid3_clk = { + .halt_reg = 0x550fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550fc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_csid3_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_ahb_clk = { + .halt_reg = 0x560e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_axi_clk = { + .halt_reg = 0x560f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560f4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_clk = { + .halt_reg = 0x560e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560e0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_clk", + .parent_names = (const char *[]){ + "gcc_camss_cpp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x560f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cpp_vbif_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_ahb_clk = { + .halt_reg = 0x55050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0_clk = { + .halt_reg = 0x55048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk = { + .halt_reg = 0x5301c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5301c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi0phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0pix_clk = { + .halt_reg = 0x55060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0pix_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0rdi_clk = { + .halt_reg = 0x55058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0rdi_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_ahb_clk = { + .halt_reg = 0x5508c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5508c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1_clk = { + .halt_reg = 0x55084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk = { + .halt_reg = 0x5303c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5303c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi1phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1pix_clk = { + .halt_reg = 0x5509c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5509c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1pix_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1rdi_clk = { + .halt_reg = 0x55094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1rdi_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_ahb_clk = { + .halt_reg = 0x550c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550c4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2_clk = { + .halt_reg = 0x550bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2phytimer_clk = { + .halt_reg = 0x5305c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5305c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi2phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2pix_clk = { + .halt_reg = 0x550d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2pix_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2rdi_clk = { + .halt_reg = 0x550cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2rdi_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3_ahb_clk = { + .halt_reg = 0x55100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3_clk = { + .halt_reg = 0x550f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x550f8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3pix_clk = { + .halt_reg = 0x55110, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3pix_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi3rdi_clk = { + .halt_reg = 0x55108, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi3rdi_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe0_clk = { + .halt_reg = 0x54074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi_vfe0_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi_vfe1_clk = { + .halt_reg = 0x54080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi_vfe1_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy0_clk = { + .halt_reg = 0x55018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy0_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy1_clk = { + .halt_reg = 0x5501c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy1_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy2_clk = { + .halt_reg = 0x55020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy2_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csiphy3_clk = { + .halt_reg = 0x55024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x55024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csiphy3_clk", + .parent_names = (const char *[]){ + "gcc_camss_csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp0_clk = { + .halt_reg = 0x50018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp0_clk", + .parent_names = (const char *[]){ + "gcc_camss_gp0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_gp1_clk = { + .halt_reg = 0x50034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_gp1_clk", + .parent_names = (const char *[]){ + "gcc_camss_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ispif_ahb_clk = { + .halt_reg = 0x540a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x540a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ispif_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_ahb_clk = { + .halt_reg = 0x52048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_axi_clk = { + .halt_reg = 0x5204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_jpeg_clk = { + .halt_reg = 0x52040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_jpeg_clk", + .parent_names = (const char *[]){ + "gcc_camss_jpeg_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk = { + .halt_reg = 0x51018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk = { + .halt_reg = 0x51034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk = { + .halt_reg = 0x51050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk3_clk = { + .halt_reg = 0x5106c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_micro_ahb_clk = { + .halt_reg = 0x560b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_micro_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_throttle_nrt_axi_clk = { + .halt_reg = 0x560a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_throttle_nrt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_throttle_rt_axi_clk = { + .halt_reg = 0x560a8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_throttle_rt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk = { + .halt_reg = 0x560a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x560a0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_top_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_ahb_clk = { + .halt_reg = 0x54034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_clk = { + .halt_reg = 0x54028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe0_stream_clk = { + .halt_reg = 0x54030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe0_stream_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_ahb_clk = { + .halt_reg = 0x5406c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5406c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_clk = { + .halt_reg = 0x54060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe1_stream_clk = { + .halt_reg = 0x54068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe1_stream_clk", + .parent_names = (const char *[]){ + "gcc_camss_vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_tsctr_clk = { + .halt_reg = 0x5409c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5409c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x5408c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5408c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_vbif_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_vfe_vbif_axi_clk = { + .halt_reg = 0x54090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_vfe_vbif_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_ahb_clk = { + .halt_reg = 0x2700c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_axi_clk = { + .halt_reg = 0x27008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_ahb_clk = { + .halt_reg = 0x2b000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk", + .parent_names = (const char *[]){ + "gcc_cpuss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk = { + .halt_reg = 0x2b004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_gnoc_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_throttle_core_clk = { + .halt_reg = 0x2b180, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b180, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(30), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_throttle_xo_clk = { + .halt_reg = 0x2b17c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2b17c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_throttle_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_ahb_clk = { + .halt_reg = 0x1700c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1700c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_gpll0_div_clk_src", + .parent_names = (const char *[]){ + "gpll0_out_early", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0x17020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_throttle_core_clk = { + .halt_reg = 0x17064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_xo_clk = { + .halt_reg = 0x1702c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1702c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x4d000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_names = (const char *[]){ + "gcc_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x4e000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4e000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_names = (const char *[]){ + "gcc_gp2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x4f000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_names = (const char *[]){ + "gcc_gp3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x36004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x36004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x36004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_names = (const char *[]){ + "gpll0_out_early", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_names = (const char *[]){ + "gpll0_out_aux2", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x3600c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x3600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x36018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_core_clk = { + .halt_reg = 0x36048, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(31), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_xo_clk = { + .halt_reg = 0x36044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_throttle_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_vs_clk = { + .halt_reg = 0x42048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x2000c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2000c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_names = (const char *[]){ + "gcc_pdm2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x20004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x20004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x20004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x20008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x21004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x21004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0x17014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0x17060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_cpuss_cfg_ahb_clk = { + .halt_reg = 0x2b178, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b178, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_cpuss_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0x17018, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { + .halt_reg = 0x36040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0x17010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x1f014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x1f00c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1f144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1f274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1f3a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1f4d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x1f604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s4_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x1f734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s5_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { + .halt_reg = 0x39014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk = { + .halt_reg = 0x3900c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk = { + .halt_reg = 0x39144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk = { + .halt_reg = 0x39274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(23), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk = { + .halt_reg = 0x393a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(24), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk = { + .halt_reg = 0x394d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk = { + .halt_reg = 0x39604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s4_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk = { + .halt_reg = 0x39734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap1_s5_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { + .halt_reg = 0x39004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { + .halt_reg = 0x39008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x39008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x38008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_names = (const char *[]){ + "gcc_sdcc1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x3800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_names = (const char *[]){ + "gcc_sdcc1_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x1e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x1e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_names = (const char *[]){ + "gcc_sdcc2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = { + .halt_reg = 0x1050c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1050c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_compute_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { + .halt_reg = 0x2b06c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_cpuss_ahb_clk", + .parent_names = (const char *[]){ + "gcc_cpuss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { + .halt_reg = 0x45098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x45098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_ufs_phy_axi_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_usb3_prim_axi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_mem_clkref_clk = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_mem_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x45014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk = { + .halt_reg = 0x45010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x45044, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x45078, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45078, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x4501c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x4501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x45018, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x45018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x45040, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_unipro_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0x1a010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0x1a018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0x1a014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk = { + .halt_reg = 0x80278, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80278, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0x1a054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_names = (const char *[]){ + "gcc_usb3_prim_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1a058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vdda_vs_clk = { + .halt_reg = 0x4200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vdda_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vddcx_vs_clk = { + .halt_reg = 0x42004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vddcx_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vddmx_vs_clk = { + .halt_reg = 0x42008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vddmx_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk = { + .halt_reg = 0x1701c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_throttle_core_clk = { + .halt_reg = 0x17068, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(28), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_xo_clk = { + .halt_reg = 0x17024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vs_ctrl_ahb_clk = { + .halt_reg = 0x42014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x42014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x42014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vs_ctrl_clk = { + .halt_reg = 0x42010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vs_ctrl_clk", + .parent_names = (const char *[]){ + "gcc_vs_ctrl_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_vs_clk = { + .halt_reg = 0x42050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x42050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_vs_clk", + .parent_names = (const char *[]){ + "gcc_vsensor_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +struct clk_hw *gcc_trinket_hws[] = { + [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw, + [GPLL0_OUT_MAIN] = &gpll0_out_main.hw, + [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, + [GPLL8_OUT_MAIN] = &gpll8_out_main.hw, + [GPLL9_OUT_MAIN] = &gpll9_out_main.hw, +}; + +static struct clk_regmap *gcc_trinket_clocks[] = { + [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, + [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, + [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, + [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, + [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, + [GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr, + [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, + [GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr, + [GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr, + [GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr, + [GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr, + [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr, + [GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, + [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, + [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, + [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr, + [GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr, + [GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr, + [GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr, + [GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr, + [GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr, + [GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr, + [GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr, + [GCC_CAMSS_CSIPHY3_CLK] = &gcc_camss_csiphy3_clk.clkr, + [GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr, + [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr, + [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr, + [GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr, + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, + [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr, + [GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, + [GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr, + [GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr, + [GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr, + [GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr, + [GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr, + [GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr, + [GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_THROTTLE_CORE_CLK] = &gcc_cpuss_throttle_core_clk.clkr, + [GCC_CPUSS_THROTTLE_XO_CLK] = &gcc_cpuss_throttle_xo_clk.clkr, + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, + [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, + [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, + [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr, + [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_CPUSS_CFG_AHB_CLK] = &gcc_qmip_cpuss_cfg_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr, + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, + [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, + [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, + [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, + [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, + [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, + [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, + [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, + [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, + [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, + [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, + [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, + [GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr, + [GPLL0_OUT_EARLY] = &gpll0_out_early.clkr, + [GPLL3_OUT_EARLY] = &gpll3_out_early.clkr, + [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, + [GPLL5_OUT_MAIN] = &gpll5_out_main.clkr, + [GPLL6_OUT_EARLY] = &gpll6_out_early.clkr, + [GPLL7_OUT_MAIN] = &gpll7_out_main.clkr, + [GPLL8_OUT_EARLY] = &gpll8_out_early.clkr, + [GPLL9_OUT_EARLY] = &gpll9_out_early.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, +}; + +static const struct qcom_reset_map gcc_trinket_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, +}; + +static struct clk_dfs gcc_dfs_clocks[] = { + { &gcc_qupv3_wrap0_s0_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap0_s1_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap0_s2_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap0_s3_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap0_s4_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap0_s5_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s0_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s1_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s2_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s3_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s4_clk_src, DFS_ENABLE_RCG }, + { &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG }, +}; + +static const struct qcom_cc_dfs_desc gcc_trinket_dfs_desc = { + .clks = gcc_dfs_clocks, + .num_clks = ARRAY_SIZE(gcc_dfs_clocks), +}; + +static const struct regmap_config gcc_trinket_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc7000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_trinket_desc = { + .config = &gcc_trinket_regmap_config, + .clks = gcc_trinket_clocks, + .num_clks = ARRAY_SIZE(gcc_trinket_clocks), + .hwclks = gcc_trinket_hws, + .num_hwclks = ARRAY_SIZE(gcc_trinket_hws), + .resets = gcc_trinket_resets, + .num_resets = ARRAY_SIZE(gcc_trinket_resets), +}; + +static const struct of_device_id gcc_trinket_match_table[] = { + { .compatible = "qcom,gcc-trinket" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_trinket_match_table); + +static int gcc_trinket_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao"); + if (IS_ERR(vdd_cx_ao.regulator[0])) { + if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_cx_ao regulator\n"); + return PTR_ERR(vdd_cx_ao.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &gcc_trinket_desc); + if (IS_ERR(regmap)) { + pr_err("Failed to map the gcc registers\n"); + return PTR_ERR(regmap); + } + + /* + * Disable the GPLL0 active input to video block via + * MISC registers. + */ + regmap_update_bits(regmap, GCC_VIDEO_MISC, 0x1, 0x1); + + ret = qcom_cc_really_probe(pdev, &gcc_trinket_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GCC clocks\n"); + return ret; + } + + /* DFS clock registration */ + ret = qcom_cc_register_rcg_dfs(pdev, &gcc_trinket_dfs_desc); + if (ret) + dev_err(&pdev->dev, "Failed to register with DFS!\n"); + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + + return 0; +} + +static struct platform_driver gcc_trinket_driver = { + .probe = gcc_trinket_probe, + .driver = { + .name = "gcc-trinket", + .of_match_table = gcc_trinket_match_table, + }, +}; + +static int __init gcc_trinket_init(void) +{ + return platform_driver_register(&gcc_trinket_driver); +} +subsys_initcall(gcc_trinket_init); + +static void __exit gcc_trinket_exit(void) +{ + platform_driver_unregister(&gcc_trinket_driver); +} +module_exit(gcc_trinket_exit); + +MODULE_DESCRIPTION("QTI GCC trinket Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:gcc-trinket"); diff --git a/drivers/clk/qcom/vdd-level-trinket.h b/drivers/clk/qcom/vdd-level-trinket.h new file mode 100644 index 000000000000..f4a28f64a3be --- /dev/null +++ b/drivers/clk/qcom/vdd-level-trinket.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_TRINKET_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_TRINKET_H + +#include +#include + +enum vdd_mx_levels { + VDD_MX_NONE, + VDD_MX_MIN, /* MIN SVS */ + VDD_MX_LOWER, /* SVS2 */ + VDD_MX_LOW, /* SVS */ + VDD_MX_LOW_L1, /* SVSL1 */ + VDD_MX_NOMINAL, /* NOM */ + VDD_MX_HIGH, /* TURBO */ + VDD_MX_NUM, +}; + +static int vdd_mx_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ + RPM_REGULATOR_LEVEL_MAX +}; + +enum vdd_dig_levels { + VDD_NONE, + VDD_MIN, /* MIN SVS */ + VDD_LOWER, /* SVS2 */ + VDD_LOW, /* SVS */ + VDD_LOW_L1, /* SVSL1 */ + VDD_NOMINAL, /* NOM */ + VDD_NOMINAL_L1, /* NOM */ + VDD_HIGH, /* TURBO */ + VDD_NUM, +}; + +static int vdd_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ + RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ + RPM_REGULATOR_LEVEL_MAX +}; + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-trinket.h b/include/dt-bindings/clock/qcom,gcc-trinket.h index d29bdb48e9e8..5ade908c851c 100644 --- a/include/dt-bindings/clock/qcom,gcc-trinket.h +++ b/include/dt-bindings/clock/qcom,gcc-trinket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,266 +14,228 @@ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H #define _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H -#define GCC_AHB2PHY_CSI_CLK 0 -#define GCC_AHB2PHY_USB_CLK 1 -#define GCC_APC_VS_CLK 2 -#define GCC_BOOT_ROM_AHB_CLK 3 -#define GCC_CAMERA_AHB_CLK 4 -#define GCC_CAMERA_XO_CLK 5 -#define GCC_CAMSS_AHB_CLK_SRC 6 -#define GCC_CAMSS_CCI_AHB_CLK 7 -#define GCC_CAMSS_CCI_CLK 8 -#define GCC_CAMSS_CCI_CLK_SRC 9 -#define GCC_CAMSS_CPHY_CSID0_CLK 10 -#define GCC_CAMSS_CPHY_CSID1_CLK 11 -#define GCC_CAMSS_CPHY_CSID2_CLK 12 -#define GCC_CAMSS_CPHY_CSID3_CLK 13 -#define GCC_CAMSS_CPP_AHB_CLK 14 -#define GCC_CAMSS_CPP_AXI_CLK 15 -#define GCC_CAMSS_CPP_CLK 16 -#define GCC_CAMSS_CPP_CLK_SRC 17 -#define GCC_CAMSS_CPP_TSCTR_CLK 18 -#define GCC_CAMSS_CPP_VBIF_AHB_CLK 19 -#define GCC_CAMSS_CSI0_AHB_CLK 20 -#define GCC_CAMSS_CSI0_CLK 21 -#define GCC_CAMSS_CSI0_CLK_SRC 22 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 23 -#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 24 -#define GCC_CAMSS_CSI0PIX_CLK 25 -#define GCC_CAMSS_CSI0RDI_CLK 26 -#define GCC_CAMSS_CSI1_AHB_CLK 27 -#define GCC_CAMSS_CSI1_CLK 28 -#define GCC_CAMSS_CSI1_CLK_SRC 29 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 30 -#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 31 -#define GCC_CAMSS_CSI1PIX_CLK 32 -#define GCC_CAMSS_CSI1RDI_CLK 33 -#define GCC_CAMSS_CSI2_AHB_CLK 34 -#define GCC_CAMSS_CSI2_CLK 35 -#define GCC_CAMSS_CSI2_CLK_SRC 36 -#define GCC_CAMSS_CSI2PHYTIMER_CLK 37 -#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 38 -#define GCC_CAMSS_CSI2PIX_CLK 39 -#define GCC_CAMSS_CSI2RDI_CLK 40 -#define GCC_CAMSS_CSI3_AHB_CLK 41 -#define GCC_CAMSS_CSI3_CLK 42 -#define GCC_CAMSS_CSI3_CLK_SRC 43 -#define GCC_CAMSS_CSI3PIX_CLK 44 -#define GCC_CAMSS_CSI3RDI_CLK 45 -#define GCC_CAMSS_CSI_VFE0_CLK 46 -#define GCC_CAMSS_CSI_VFE1_CLK 47 -#define GCC_CAMSS_CSIPHY0_CLK 48 -#define GCC_CAMSS_CSIPHY1_CLK 49 -#define GCC_CAMSS_CSIPHY2_CLK 50 -#define GCC_CAMSS_CSIPHY3_CLK 51 -#define GCC_CAMSS_CSIPHY_CLK_SRC 52 -#define GCC_CAMSS_GP0_CLK 53 -#define GCC_CAMSS_GP0_CLK_SRC 54 -#define GCC_CAMSS_GP1_CLK 55 -#define GCC_CAMSS_GP1_CLK_SRC 56 -#define GCC_CAMSS_ISPIF_AHB_CLK 57 -#define GCC_CAMSS_JPEG_AHB_CLK 58 -#define GCC_CAMSS_JPEG_AXI_CLK 59 -#define GCC_CAMSS_JPEG_CLK 60 -#define GCC_CAMSS_JPEG_CLK_SRC 61 -#define GCC_CAMSS_JPEG_TSCTR_CLK 62 -#define GCC_CAMSS_MCLK0_CLK 63 -#define GCC_CAMSS_MCLK0_CLK_SRC 64 -#define GCC_CAMSS_MCLK1_CLK 65 -#define GCC_CAMSS_MCLK1_CLK_SRC 66 -#define GCC_CAMSS_MCLK2_CLK 67 -#define GCC_CAMSS_MCLK2_CLK_SRC 68 -#define GCC_CAMSS_MCLK3_CLK 69 -#define GCC_CAMSS_MCLK3_CLK_SRC 70 -#define GCC_CAMSS_MICRO_AHB_CLK 71 -#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 72 -#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 73 -#define GCC_CAMSS_TOP_AHB_CLK 74 -#define GCC_CAMSS_VFE0_AHB_CLK 75 -#define GCC_CAMSS_VFE0_CLK 76 -#define GCC_CAMSS_VFE0_CLK_SRC 77 -#define GCC_CAMSS_VFE0_STREAM_CLK 78 -#define GCC_CAMSS_VFE1_AHB_CLK 79 -#define GCC_CAMSS_VFE1_CLK 80 -#define GCC_CAMSS_VFE1_CLK_SRC 81 -#define GCC_CAMSS_VFE1_STREAM_CLK 82 -#define GCC_CAMSS_VFE_TSCTR_CLK 83 -#define GCC_CAMSS_VFE_VBIF_AHB_CLK 84 -#define GCC_CAMSS_VFE_VBIF_AXI_CLK 85 -#define GCC_CE1_AHB_CLK 86 -#define GCC_CE1_AXI_CLK 87 -#define GCC_CE1_CLK 88 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 89 -#define GCC_CPUSS_AHB_CLK 90 -#define GCC_CPUSS_AHB_CLK_SRC 91 -#define GCC_CPUSS_GNOC_CLK 92 -#define GCC_CPUSS_THROTTLE_CORE_CLK 93 -#define GCC_CPUSS_THROTTLE_XO_CLK 94 -#define GCC_DISP_AHB_CLK 95 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 96 -#define GCC_DISP_HF_AXI_CLK 97 -#define GCC_DISP_THROTTLE_CORE_CLK 98 -#define GCC_DISP_XO_CLK 99 -#define GCC_GP1_CLK 100 -#define GCC_GP1_CLK_SRC 101 -#define GCC_GP2_CLK 102 -#define GCC_GP2_CLK_SRC 103 -#define GCC_GP3_CLK 104 -#define GCC_GP3_CLK_SRC 105 -#define GCC_GPU_CFG_AHB_CLK 106 -#define GCC_GPU_GPLL0_CLK_SRC 107 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 108 -#define GCC_GPU_MEMNOC_GFX_CLK 109 -#define GCC_GPU_SNOC_DVM_GFX_CLK 110 -#define GCC_GPU_THROTTLE_CORE_CLK 111 -#define GCC_GPU_THROTTLE_XO_CLK 112 -#define GCC_MSS_VS_CLK 113 -#define GCC_PDM2_CLK 114 -#define GCC_PDM2_CLK_SRC 115 -#define GCC_PDM_AHB_CLK 116 -#define GCC_PDM_XO4_CLK 117 -#define GCC_PRNG_AHB_CLK 118 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 119 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 120 -#define GCC_QMIP_CPUSS_CFG_AHB_CLK 121 -#define GCC_QMIP_DISP_AHB_CLK 122 -#define GCC_QMIP_GPU_CFG_AHB_CLK 123 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 124 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 125 -#define GCC_QUPV3_WRAP0_CORE_CLK 126 -#define GCC_QUPV3_WRAP0_S0_CLK 127 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 128 -#define GCC_QUPV3_WRAP0_S1_CLK 129 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 130 -#define GCC_QUPV3_WRAP0_S2_CLK 131 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 132 -#define GCC_QUPV3_WRAP0_S3_CLK 133 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 134 -#define GCC_QUPV3_WRAP0_S4_CLK 135 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 136 -#define GCC_QUPV3_WRAP0_S5_CLK 137 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 138 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 139 -#define GCC_QUPV3_WRAP1_CORE_CLK 140 -#define GCC_QUPV3_WRAP1_S0_CLK 141 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 142 -#define GCC_QUPV3_WRAP1_S1_CLK 143 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 144 -#define GCC_QUPV3_WRAP1_S2_CLK 145 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 146 -#define GCC_QUPV3_WRAP1_S3_CLK 147 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 148 -#define GCC_QUPV3_WRAP1_S4_CLK 149 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 150 -#define GCC_QUPV3_WRAP1_S5_CLK 151 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 152 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 153 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 154 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 155 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 156 -#define GCC_SDCC1_AHB_CLK 157 -#define GCC_SDCC1_APPS_CLK 158 -#define GCC_SDCC1_APPS_CLK_SRC 159 -#define GCC_SDCC1_ICE_CORE_CLK 160 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 161 -#define GCC_SDCC2_AHB_CLK 162 -#define GCC_SDCC2_APPS_CLK 163 -#define GCC_SDCC2_APPS_CLK_SRC 164 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 165 -#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 166 -#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 167 -#define GCC_UFS_PHY_AHB_CLK 168 -#define GCC_UFS_PHY_AXI_CLK 169 -#define GCC_UFS_PHY_AXI_CLK_SRC 170 -#define GCC_UFS_PHY_ICE_CORE_CLK 171 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 172 -#define GCC_UFS_PHY_PHY_AUX_CLK 173 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 174 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 175 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 176 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 177 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 178 -#define GCC_USB30_PRIM_MASTER_CLK 179 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 180 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 181 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 182 -#define GCC_USB30_PRIM_SLEEP_CLK 183 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 186 -#define GCC_VDDA_VS_CLK 187 -#define GCC_VDDCX_VS_CLK 188 -#define GCC_VDDMX_VS_CLK 189 -#define GCC_VIDEO_AHB_CLK 190 -#define GCC_VIDEO_AXI0_CLK 191 -#define GCC_VIDEO_THROTTLE_CORE_CLK 192 -#define GCC_VIDEO_XO_CLK 193 -#define GCC_VS_CTRL_AHB_CLK 194 -#define GCC_VS_CTRL_CLK 195 -#define GCC_VS_CTRL_CLK_SRC 196 -#define GCC_VSENSOR_CLK_SRC 197 -#define GCC_WCSS_VS_CLK 198 -#define GPLL0 199 -#define GPLL0_OUT_AUX2 200 -#define GPLL3 201 -#define GPLL4 202 -#define GPLL4_OUT_MAIN 203 -#define GPLL5 204 -#define GPLL5_OUT_MAIN 205 -#define GPLL6 206 -#define GPLL6_OUT_MAIN 207 -#define GPLL7 208 -#define GPLL7_OUT_MAIN 209 -#define GPLL8 210 -#define GPLL8_OUT_MAIN 211 -#define GPLL9 212 -#define GPLL9_OUT_MAIN 213 -#define GCC_USB3_PRIM_CLKREF_CLK 214 - -#define GCC_CAMSS_CCI_BCR 0 -#define GCC_CAMSS_CPP_BCR 1 -#define GCC_CAMSS_CPP_TOP_BCR 2 -#define GCC_CAMSS_CSI0_BCR 3 -#define GCC_CAMSS_CSI0PIX_BCR 4 -#define GCC_CAMSS_CSI0RDI_BCR 5 -#define GCC_CAMSS_CSI1_BCR 6 -#define GCC_CAMSS_CSI1PIX_BCR 7 -#define GCC_CAMSS_CSI1RDI_BCR 8 -#define GCC_CAMSS_CSI2_BCR 9 -#define GCC_CAMSS_CSI2PIX_BCR 10 -#define GCC_CAMSS_CSI2RDI_BCR 11 -#define GCC_CAMSS_CSI3_BCR 12 -#define GCC_CAMSS_CSI3PIX_BCR 13 -#define GCC_CAMSS_CSI3RDI_BCR 14 -#define GCC_CAMSS_CSI_VFE0_BCR 15 -#define GCC_CAMSS_CSI_VFE1_BCR 16 -#define GCC_CAMSS_ISPIF_BCR 17 -#define GCC_CAMSS_JPEG_BCR 18 -#define GCC_CAMSS_MICRO_BCR 19 -#define GCC_CAMSS_PHY0_BCR 20 -#define GCC_CAMSS_PHY1_BCR 21 -#define GCC_CAMSS_PHY2_BCR 22 -#define GCC_CAMSS_TOP_BCR 23 +#define GPLL0_OUT_EARLY 0 +#define GPLL0_OUT_AUX2 1 +#define GPLL0_OUT_MAIN 2 +#define GPLL3_OUT_EARLY 3 +#define GPLL4_OUT_MAIN 4 +#define GPLL5_OUT_MAIN 5 +#define GPLL6_OUT_EARLY 6 +#define GPLL6_OUT_MAIN 7 +#define GPLL7_OUT_MAIN 8 +#define GPLL8_OUT_EARLY 9 +#define GPLL8_OUT_MAIN 10 +#define GPLL9_OUT_EARLY 11 +#define GPLL9_OUT_MAIN 12 +#define GCC_AHB2PHY_CSI_CLK 13 +#define GCC_AHB2PHY_USB_CLK 14 +#define GCC_APC_VS_CLK 15 +#define GCC_BOOT_ROM_AHB_CLK 16 +#define GCC_CAMERA_AHB_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CAMSS_AHB_CLK_SRC 19 +#define GCC_CAMSS_CCI_AHB_CLK 20 +#define GCC_CAMSS_CCI_CLK 21 +#define GCC_CAMSS_CCI_CLK_SRC 22 +#define GCC_CAMSS_CPHY_CSID0_CLK 23 +#define GCC_CAMSS_CPHY_CSID1_CLK 24 +#define GCC_CAMSS_CPHY_CSID2_CLK 25 +#define GCC_CAMSS_CPHY_CSID3_CLK 26 +#define GCC_CAMSS_CPP_AHB_CLK 27 +#define GCC_CAMSS_CPP_AXI_CLK 28 +#define GCC_CAMSS_CPP_CLK 29 +#define GCC_CAMSS_CPP_CLK_SRC 30 +#define GCC_CAMSS_CPP_VBIF_AHB_CLK 31 +#define GCC_CAMSS_CSI0_AHB_CLK 32 +#define GCC_CAMSS_CSI0_CLK 33 +#define GCC_CAMSS_CSI0_CLK_SRC 34 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 35 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 36 +#define GCC_CAMSS_CSI0PIX_CLK 37 +#define GCC_CAMSS_CSI0RDI_CLK 38 +#define GCC_CAMSS_CSI1_AHB_CLK 39 +#define GCC_CAMSS_CSI1_CLK 40 +#define GCC_CAMSS_CSI1_CLK_SRC 41 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 42 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 43 +#define GCC_CAMSS_CSI1PIX_CLK 44 +#define GCC_CAMSS_CSI1RDI_CLK 45 +#define GCC_CAMSS_CSI2_AHB_CLK 46 +#define GCC_CAMSS_CSI2_CLK 47 +#define GCC_CAMSS_CSI2_CLK_SRC 48 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 49 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 50 +#define GCC_CAMSS_CSI2PIX_CLK 51 +#define GCC_CAMSS_CSI2RDI_CLK 52 +#define GCC_CAMSS_CSI3_AHB_CLK 53 +#define GCC_CAMSS_CSI3_CLK 54 +#define GCC_CAMSS_CSI3_CLK_SRC 55 +#define GCC_CAMSS_CSI3PIX_CLK 56 +#define GCC_CAMSS_CSI3RDI_CLK 57 +#define GCC_CAMSS_CSI_VFE0_CLK 58 +#define GCC_CAMSS_CSI_VFE1_CLK 59 +#define GCC_CAMSS_CSIPHY0_CLK 60 +#define GCC_CAMSS_CSIPHY1_CLK 61 +#define GCC_CAMSS_CSIPHY2_CLK 62 +#define GCC_CAMSS_CSIPHY3_CLK 63 +#define GCC_CAMSS_CSIPHY_CLK_SRC 64 +#define GCC_CAMSS_GP0_CLK 65 +#define GCC_CAMSS_GP0_CLK_SRC 66 +#define GCC_CAMSS_GP1_CLK 67 +#define GCC_CAMSS_GP1_CLK_SRC 68 +#define GCC_CAMSS_ISPIF_AHB_CLK 69 +#define GCC_CAMSS_JPEG_AHB_CLK 70 +#define GCC_CAMSS_JPEG_AXI_CLK 71 +#define GCC_CAMSS_JPEG_CLK 72 +#define GCC_CAMSS_JPEG_CLK_SRC 73 +#define GCC_CAMSS_MCLK0_CLK 74 +#define GCC_CAMSS_MCLK0_CLK_SRC 75 +#define GCC_CAMSS_MCLK1_CLK 76 +#define GCC_CAMSS_MCLK1_CLK_SRC 77 +#define GCC_CAMSS_MCLK2_CLK 78 +#define GCC_CAMSS_MCLK2_CLK_SRC 79 +#define GCC_CAMSS_MCLK3_CLK 80 +#define GCC_CAMSS_MCLK3_CLK_SRC 81 +#define GCC_CAMSS_MICRO_AHB_CLK 82 +#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83 +#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84 +#define GCC_CAMSS_TOP_AHB_CLK 85 +#define GCC_CAMSS_VFE0_AHB_CLK 86 +#define GCC_CAMSS_VFE0_CLK 87 +#define GCC_CAMSS_VFE0_CLK_SRC 88 +#define GCC_CAMSS_VFE0_STREAM_CLK 89 +#define GCC_CAMSS_VFE1_AHB_CLK 90 +#define GCC_CAMSS_VFE1_CLK 91 +#define GCC_CAMSS_VFE1_CLK_SRC 92 +#define GCC_CAMSS_VFE1_STREAM_CLK 93 +#define GCC_CAMSS_VFE_TSCTR_CLK 94 +#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95 +#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96 +#define GCC_CE1_AHB_CLK 97 +#define GCC_CE1_AXI_CLK 98 +#define GCC_CE1_CLK 99 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100 +#define GCC_CPUSS_AHB_CLK 101 +#define GCC_CPUSS_AHB_CLK_SRC 102 +#define GCC_CPUSS_GNOC_CLK 103 +#define GCC_CPUSS_THROTTLE_CORE_CLK 104 +#define GCC_CPUSS_THROTTLE_XO_CLK 105 +#define GCC_DISP_AHB_CLK 106 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 107 +#define GCC_DISP_HF_AXI_CLK 108 +#define GCC_DISP_THROTTLE_CORE_CLK 109 +#define GCC_DISP_XO_CLK 110 +#define GCC_GP1_CLK 111 +#define GCC_GP1_CLK_SRC 112 +#define GCC_GP2_CLK 113 +#define GCC_GP2_CLK_SRC 114 +#define GCC_GP3_CLK 115 +#define GCC_GP3_CLK_SRC 116 +#define GCC_GPU_CFG_AHB_CLK 117 +#define GCC_GPU_GPLL0_CLK_SRC 118 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 119 +#define GCC_GPU_MEMNOC_GFX_CLK 120 +#define GCC_GPU_SNOC_DVM_GFX_CLK 121 +#define GCC_GPU_THROTTLE_CORE_CLK 122 +#define GCC_GPU_THROTTLE_XO_CLK 123 +#define GCC_MSS_VS_CLK 124 +#define GCC_PDM2_CLK 125 +#define GCC_PDM2_CLK_SRC 126 +#define GCC_PDM_AHB_CLK 127 +#define GCC_PDM_XO4_CLK 128 +#define GCC_PRNG_AHB_CLK 129 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 130 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 131 +#define GCC_QMIP_CPUSS_CFG_AHB_CLK 132 +#define GCC_QMIP_DISP_AHB_CLK 133 +#define GCC_QMIP_GPU_CFG_AHB_CLK 134 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 135 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 136 +#define GCC_QUPV3_WRAP0_CORE_CLK 137 +#define GCC_QUPV3_WRAP0_S0_CLK 138 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 139 +#define GCC_QUPV3_WRAP0_S1_CLK 140 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 141 +#define GCC_QUPV3_WRAP0_S2_CLK 142 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 143 +#define GCC_QUPV3_WRAP0_S3_CLK 144 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 145 +#define GCC_QUPV3_WRAP0_S4_CLK 146 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 147 +#define GCC_QUPV3_WRAP0_S5_CLK 148 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 149 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 150 +#define GCC_QUPV3_WRAP1_CORE_CLK 151 +#define GCC_QUPV3_WRAP1_S0_CLK 152 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 153 +#define GCC_QUPV3_WRAP1_S1_CLK 154 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 155 +#define GCC_QUPV3_WRAP1_S2_CLK 156 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 157 +#define GCC_QUPV3_WRAP1_S3_CLK 158 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 159 +#define GCC_QUPV3_WRAP1_S4_CLK 160 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 161 +#define GCC_QUPV3_WRAP1_S5_CLK 162 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 163 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 164 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 165 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 166 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 167 +#define GCC_SDCC1_AHB_CLK 168 +#define GCC_SDCC1_APPS_CLK 169 +#define GCC_SDCC1_APPS_CLK_SRC 170 +#define GCC_SDCC1_ICE_CORE_CLK 171 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 172 +#define GCC_SDCC2_AHB_CLK 173 +#define GCC_SDCC2_APPS_CLK 174 +#define GCC_SDCC2_APPS_CLK_SRC 175 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 176 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 177 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 178 +#define GCC_UFS_PHY_AHB_CLK 179 +#define GCC_UFS_PHY_AXI_CLK 180 +#define GCC_UFS_PHY_AXI_CLK_SRC 181 +#define GCC_UFS_PHY_ICE_CORE_CLK 182 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 183 +#define GCC_UFS_PHY_PHY_AUX_CLK 184 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 185 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 186 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 187 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 188 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 189 +#define GCC_USB30_PRIM_MASTER_CLK 190 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 191 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 192 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 193 +#define GCC_USB30_PRIM_SLEEP_CLK 194 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 197 +#define GCC_VDDA_VS_CLK 198 +#define GCC_VDDCX_VS_CLK 199 +#define GCC_VDDMX_VS_CLK 200 +#define GCC_VIDEO_AHB_CLK 201 +#define GCC_VIDEO_AXI0_CLK 202 +#define GCC_VIDEO_THROTTLE_CORE_CLK 203 +#define GCC_VIDEO_XO_CLK 204 +#define GCC_VS_CTRL_AHB_CLK 205 +#define GCC_VS_CTRL_CLK 206 +#define GCC_VS_CTRL_CLK_SRC 207 +#define GCC_VSENSOR_CLK_SRC 208 +#define GCC_WCSS_VS_CLK 209 +#define GCC_USB3_PRIM_CLKREF_CLK 210 +#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 211 +#define GCC_BIMC_GPU_AXI_CLK 212 +#define GCC_UFS_MEM_CLKREF_CLK 213 /* GCC Resets */ -#define GCC_CAMSS_VFE0_BCR 24 -#define GCC_CAMSS_VFE1_BCR 25 -#define GCC_CAMSS_VFE_VBIF_BCR 26 -#define GCC_GPU_BCR 27 -#define GCC_MMSS_BCR 28 -#define GCC_PDM_BCR 29 -#define GCC_PRNG_BCR 30 -#define GCC_QUPV3_WRAPPER_0_BCR 31 -#define GCC_QUPV3_WRAPPER_1_BCR 32 -#define GCC_QUSB2PHY_PRIM_BCR 33 -#define GCC_QUSB2PHY_SEC_BCR 34 -#define GCC_SDCC1_BCR 35 -#define GCC_SDCC2_BCR 36 -#define GCC_UFS_PHY_BCR 37 -#define GCC_USB30_PRIM_BCR 38 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 39 -#define GCC_VS_BCR 40 -#define GCC_USB3_PHY_PRIM_SP0_BCR 41 -#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 42 +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 4 +#define GCC_USB3_PHY_PRIM_SP0_BCR 5 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6 #endif -- GitLab From a3e73829b02d92e5ab4f5d5c59246be35e8d9ccb Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 27 Dec 2018 15:15:13 +0530 Subject: [PATCH 0771/1286] ARM: dts: msm: Add GPIO configurations for ADC channels on trinket Add pinctrl configurations for ADC channels using GPIOs on trinket. In addition, remove xo_therm channel on PMI632 for trinket as it is not used. Change-Id: I39558e313fc0387c29d89e980279ac76d75fb53c Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/trinket.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..4c9ae7d58d49 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1982,6 +1982,9 @@ #include "trinket-pm.dtsi" &pm6125_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + rf_pa0_therm { reg = ; label = "rf_pa0_therm"; @@ -2024,6 +2027,23 @@ }; +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; + +}; + &spmi_bus { qcom,pm6125@0 { pm6125_adc_tm_iio: adc_tm@3400 { @@ -2081,6 +2101,13 @@ }; &pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + status = "disabled"; + }; + bat_therm { qcom,lut-index = <1>; }; @@ -2110,6 +2137,23 @@ }; }; +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + +}; + &pmi632_adc_tm { io-channels = <&pmi632_vadc ADC_GPIO1_PU2>, <&pmi632_vadc ADC_GPIO2_PU2>; -- GitLab From f87a78a5f3096e4e9c22c5fa082278aa6a135749 Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Wed, 12 Dec 2018 18:36:12 +0530 Subject: [PATCH 0772/1286] defconfig: enable synaptics_dsx driver for sdmsteppe and trinklet Enable synaptics_dsx driver in defconfig for sdmsteppe and trinklet targets and remove default yes in Kconfig. Change-Id: If2584a27ef5410009347896b9f88a5d6a3e1f108 Signed-off-by: Vevek Venkatesan --- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe_defconfig | 1 + arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + drivers/input/touchscreen/Kconfig | 2 +- drivers/input/touchscreen/synaptics_dsx/Kconfig | 1 - 8 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index c6ab2f95c01c..72f65cb93f69 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -315,6 +315,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index c420758e5ae7..f772e48c2da9 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -326,6 +326,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index 7463b2babe07..36c423078055 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -311,6 +311,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index bfd457725d9f..33e76a3f0e38 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -321,6 +321,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..46575cc4b202 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -299,6 +299,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..8174882e9239 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -311,6 +311,7 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index e9e59a3d6c59..e4ba3f6d84e5 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1269,7 +1269,7 @@ config TOUCHSCREEN_HIMAX_CHIPSET source "drivers/input/touchscreen/hxchipset/Kconfig" config TOUCHSCREEN_SYNAPTICS_DSX - bool "Synaptics Touchscreen Driver" + bool "Synaptics DSX Touchscreen Driver" depends on I2C help Say Y here if you have a Synaptics Touchscreen. diff --git a/drivers/input/touchscreen/synaptics_dsx/Kconfig b/drivers/input/touchscreen/synaptics_dsx/Kconfig index b54e792d53e3..3cedd236e04a 100644 --- a/drivers/input/touchscreen/synaptics_dsx/Kconfig +++ b/drivers/input/touchscreen/synaptics_dsx/Kconfig @@ -3,7 +3,6 @@ # menuconfig TOUCHSCREEN_SYNAPTICS_DSX bool "Synaptics DSX touchscreen" - default y help Say Y here if you have a Synaptics DSX touchscreen connected to your system. -- GitLab From 666664cf42a1c50e594b69cf1254045389e7d300 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Fri, 21 Dec 2018 15:40:13 +0530 Subject: [PATCH 0773/1286] qcom-geni-se: correct the bandwidth aggregation logic Current aggregation logic in geni driver doesn't take "agg ab" into consideration to put bandwidth request to bus driver. This is a issue if QUPv3 clock is not sufficient for multiple use cases. Correct the logic to include "agg ab" as well into consideration to decide next bandwidth request. Increase the bus bandwidth ranges. Change-Id: I9de47a727574cfb69db479ccacdf2bdd18f753f4 Signed-off-by: Prudhvi Yarlagadda --- drivers/platform/msm/qcom-geni-se.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/platform/msm/qcom-geni-se.c b/drivers/platform/msm/qcom-geni-se.c index 142ac3e5ef3b..18dc292738f7 100644 --- a/drivers/platform/msm/qcom-geni-se.c +++ b/drivers/platform/msm/qcom-geni-se.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -41,7 +41,8 @@ #define NUM_LOG_PAGES 2 #define MAX_CLK_PERF_LEVEL 32 -static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, 100000000}; +static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, + 100000000, 150000000, 200000000, 236000000}; /** * @struct geni_se_device - Data structure to represent the QUPv3 Core @@ -630,8 +631,11 @@ static bool geni_se_check_bus_bw(struct geni_se_device *geni_se_dev) int new_bus_bw_idx = geni_se_dev->bus_bw_set_size - 1; unsigned long new_bus_bw; bool bus_bw_update = false; + /* Convert agg ab into bytes per second */ + unsigned long new_ab_in_hz = DEFAULT_BUS_WIDTH * + ((2*geni_se_dev->cur_ab)*10000); - new_bus_bw = max(geni_se_dev->cur_ib, geni_se_dev->cur_ab) / + new_bus_bw = max(geni_se_dev->cur_ib, new_ab_in_hz) / DEFAULT_BUS_WIDTH; for (i = 0; i < geni_se_dev->bus_bw_set_size; i++) { if (geni_se_dev->bus_bw_set[i] >= new_bus_bw) { -- GitLab From 1b1cb5209b1dbe9b900f4b5561430a8cef682383 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 9 Jan 2019 12:16:17 +0530 Subject: [PATCH 0774/1286] ARM: dts: msm: Fix SMB1355 IRQ configuration Correct the IRQ port number for the gpio to which SMB1355 STAT pin is connected. While at it, correct the SMB1355 stat pin gpio configuration also. Change-Id: I55df4cd2fe245d25e475a1048e786ea7f0c74190 Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 3 +-- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 5aa01d5760cd..905e00a2a8b1 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -131,7 +131,6 @@ }; config { pins = "gpio130"; - drive-strength = <2>; bias-pull-up; input-enable; }; @@ -142,7 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&smb_int_default>; interrupt-parent = <&tlmm>; - interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + interrupts = <62 IRQ_TYPE_LEVEL_LOW>; status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 7c3cf74761fb..a509ab6a9b52 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -124,7 +124,6 @@ }; config { pins = "gpio130"; - drive-strength = <2>; bias-pull-up; input-enable; }; @@ -135,7 +134,7 @@ pinctrl-names = "default"; pinctrl-0 = <&smb_int_default>; interrupt-parent = <&tlmm>; - interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + interrupts = <62 IRQ_TYPE_LEVEL_LOW>; status = "ok"; }; -- GitLab From dd8180abaec4226f7f07770f42d55bd77dd47882 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 9 Jan 2019 12:36:56 +0530 Subject: [PATCH 0775/1286] power: smb5: Add extcon capability to report orientation and speed Currently, charger driver sets the CC orientation and USB speed property, but does not expose the capability to set these properties, which renders the former useless. Fix this by adding the capability to report CC orientation and USB speed while registering extcon. Change-Id: Ic029075c84171dfd8e21a63f1f97b2943ec61aa4 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/qpnp-smb5.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index 64add8f6ffb0..4951605aab9b 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -3087,6 +3087,21 @@ static int smb5_probe(struct platform_device *pdev) goto cleanup; } + /* Support reporting polarity and speed via properties */ + rc = extcon_set_property_capability(chg->extcon, + EXTCON_USB, EXTCON_PROP_USB_TYPEC_POLARITY); + rc |= extcon_set_property_capability(chg->extcon, + EXTCON_USB, EXTCON_PROP_USB_SS); + rc |= extcon_set_property_capability(chg->extcon, + EXTCON_USB_HOST, EXTCON_PROP_USB_TYPEC_POLARITY); + rc |= extcon_set_property_capability(chg->extcon, + EXTCON_USB_HOST, EXTCON_PROP_USB_SS); + if (rc < 0) { + dev_err(chg->dev, + "failed to configure extcon capabilities\n"); + goto cleanup; + } + rc = smb5_init_hw(chip); if (rc < 0) { pr_err("Couldn't initialize hardware rc=%d\n", rc); -- GitLab From 9bbb61ce7a58ba2649257dce1191d61164146a78 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Mon, 16 Apr 2018 11:17:22 +0530 Subject: [PATCH 0776/1286] mmc: host: sdhci-msm: Toggle FIFO write clk after MCLK ungated During GCC level clock gating of MCLK, the async FIFO gets into some hang condition, such that for the next transfer after MCLK ungating, first bit of CMD response doesn't get written in to the FIFO. This cause the CPSM to hang eventually leading to SW timeout. To fix the issue, toggle the FIFO write clock after MCLK ungated to get the FIFO pointers and flags to valid states. Change-Id: I29faefbcb814fcc36fb8afcf7ec2cb51c553b5e6 Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 9157e151ea12..5f2a243629bc 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -175,6 +175,8 @@ #define MAX_DRV_TYPES_SUPPORTED_HS200 4 #define MSM_AUTOSUSPEND_DELAY_MS 100 +#define RCLK_TOGGLE 0x2 + struct sdhci_msm_offset { u32 CORE_MCI_DATA_CNT; u32 CORE_MCI_STATUS; @@ -3478,6 +3480,33 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | CORE_HC_SELECT_IN_EN), host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC); } + /* + * After MCLK ugating, toggle the FIFO write clock to get + * the FIFO pointers and flags to valid state. + */ + if (msm_host->tuning_done || + (card && mmc_card_strobe(card) && + msm_host->enhanced_strobe)) { + /* + * set HC_REG_DLL_CONFIG_3[1] to select MCLK as + * DLL input clock + */ + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG)) + | RCLK_TOGGLE), host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG); + /* ensure above write as toggling same bit quickly */ + wmb(); + udelay(2); + /* + * clear HC_REG_DLL_CONFIG_3[1] to select RCLK as + * DLL input clock + */ + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG)) + & ~RCLK_TOGGLE), host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG); + } if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) { /* * Poll on DLL_LOCK and DDR_DLL_LOCK bits in -- GitLab From ddc0fd71094e4bada990875cfe59dfbab69f631c Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Tue, 8 Jan 2019 17:23:20 +0530 Subject: [PATCH 0777/1286] msm: mdss: dsi: correct the copyright header Modify the copyright year to omit 2017 as this file mdss_dsi_clk.c is not updated in 2017. Change-Id: Ia9e6f30c4ac37df3a0dfbb1d734230a63ee47f29 Signed-off-by: Narender Ankam --- drivers/video/fbdev/msm/mdss_dsi_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/msm/mdss_dsi_clk.c b/drivers/video/fbdev/msm/mdss_dsi_clk.c index 6423a5e2e9ab..41b94e3bc872 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_clk.c +++ b/drivers/video/fbdev/msm/mdss_dsi_clk.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and -- GitLab From 6783992d24949c6a2d3a0ba8edc8c5f484d53cb0 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Thu, 8 Nov 2018 11:21:21 +0530 Subject: [PATCH 0778/1286] ARM: dts: msm: Add UFS support for trinket This change enables UFS support on trinket platform. Change-Id: Ia9fe02c9b93ff888d1934fec58cd0ee2f928df58 Signed-off-by: Sayali Lokhande --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 26 +++++ arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 46 ++++++++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 26 +++++ arch/arm64/boot/dts/qcom/trinket-rumi.dtsi | 34 ++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 106 ++++++++++++++++++ 5 files changed, 238 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 5aa01d5760cd..be7497cedd08 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -154,3 +154,29 @@ qcom,hw-die-temp-mitigation; status = "ok"; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 2258e40186c7..1a25be5ab4a6 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -746,5 +746,51 @@ bias-disable; }; }; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 7c3cf74761fb..ee584086eb3e 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -147,3 +147,29 @@ qcom,hw-die-temp-mitigation; status = "ok"; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi index b3bb13495c68..7e86aa4b7e9f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi @@ -151,3 +151,37 @@ status = "ok"; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + scsi-cmd-timeout = <300000>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..c27c12336ede 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -34,6 +34,7 @@ serial0 = &qupv3_se4_2uart; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ }; cpus { @@ -772,6 +773,111 @@ poll-delay-ms = <5000>; }; + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xdb8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>; + interrupts = <0 356 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <26 26>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + qcom,msm-imem@c125000 { compatible = "qcom,msm-imem"; reg = <0xc125000 0x1000>; -- GitLab From 635c005836b1d9ffedb7c7d404d8f073fa1f61aa Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Tue, 7 Aug 2018 15:51:23 +0530 Subject: [PATCH 0779/1286] ARM: dts: msm: add rgb interface device node on qcs405 Add mdss_rgb device node to configure rgb interface and mdss_rgb_spi device node to configure spi controller to access rgb panel. Change-Id: I4f83aa6e18ddd9c6ad61f515b67d3b5d434f01c2 Signed-off-by: Narender Ankam --- arch/arm64/boot/dts/qcom/qcs405-iot-sku5.dts | 66 ++- .../boot/dts/qcom/qcs405-mdss-panels.dtsi | 3 +- arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi | 93 +++- arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi | 468 +++++++++++++++++- .../boot/dts/qcom/rgb-panel-st7789v.dtsi | 30 ++ 5 files changed, 656 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/rgb-panel-st7789v.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs405-iot-sku5.dts b/arch/arm64/boot/dts/qcom/qcs405-iot-sku5.dts index 433728cb4d54..235dc4039079 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-iot-sku5.dts +++ b/arch/arm64/boot/dts/qcom/qcs405-iot-sku5.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -17,9 +17,73 @@ #include "qcs405-audio-overlay.dtsi" #include "qcs405-geni-ir-overlay.dtsi" #include "qcs405-circular-pca9956.dtsi" +#include "qcs405-mdss-panels.dtsi" / { model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 RGB IOT"; compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x030020 0x1>; }; + +&mdss_dsi { + status = "disabled"; +}; + +&mdss_dsi0 { + status = "disabled"; +}; + +&mdss_hdmi_tx { + status = "disabled"; +}; + +&msm_ext_disp { + status = "disabled"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "rgb"; +}; + +&mdss_rgb { + qcom,rgb-panel = <&rgb_st7789v>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_rgb_active &mdss_rgb_data0_active + &mdss_rgb_data1_active &mdss_rgb_data2_active + &mdss_rgb_data3_active &mdss_rgb_data4_active + &mdss_rgb_data5_active &mdss_rgb_data_b0_active + &mdss_rgb_data_b1_active &mdss_rgb_data_b2_active + &mdss_rgb_data_b3_active &mdss_rgb_data_b4_active + &mdss_rgb_data_b5_active &mdss_rgb_hsync_active + &mdss_rgb_vsync_active &mdss_rgb_de_active + &mdss_rgb_clk_active>; + pinctrl-1 = <&mdss_rgb_suspend &mdss_rgb_data0_suspend + &mdss_rgb_data1_suspend &mdss_rgb_data2_suspend + &mdss_rgb_data3_suspend &mdss_rgb_data4_suspend + &mdss_rgb_data5_suspend &mdss_rgb_data_b0_suspend + &mdss_rgb_data_b1_suspend &mdss_rgb_data_b2_suspend + &mdss_rgb_data_b3_suspend &mdss_rgb_data_b4_suspend + &mdss_rgb_data_b5_suspend &mdss_rgb_hsync_suspend + &mdss_rgb_vsync_suspend &mdss_rgb_de_suspend + &mdss_rgb_clk_suspend>; + qcom,platform-reset-gpio = <&tlmm 58 0>; +}; + +&rgb_st7789v { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&spi_1 { + status = "ok"; + mdss_rgb_spi: qcom,mdss_rgb_spi@0 { + compatible = "qcom,mdss-rgb-spi"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; + +&soc { + gpio_keys { + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405-mdss-panels.dtsi b/arch/arm64/boot/dts/qcom/qcs405-mdss-panels.dtsi index 93aa6de6dc1a..71b90990eb4a 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-mdss-panels.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-mdss-panels.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,6 +11,7 @@ */ #include "dsi-panel-hx8394d-720p-video.dtsi" +#include "rgb-panel-st7789v.dtsi" &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { diff --git a/arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi b/arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi index d78813c1ef1c..ed939ade0dca 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -205,6 +205,96 @@ }; }; + mdss_rgb: qcom,mdss_rgb@0 { + compatible = "qcom,mdss-rgb"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x1a94400 0x1a94400 0x280 + 0x1a94b80 0x1a94b80 0x30 + 0x193e000 0x193e000 0x30>; + + reg = <0x1a94400 0x280>, + <0x1a94b80 0x30>, + <0x193e000 0x30>; + reg-names = "dsi_phy", + "dsi_phy_regulator", "mmss_misc_phys"; + + gdsc-supply = <&gdsc_mdss>; + vdda-1p2-supply = <&pms405_l4>; + vdda-1p8-supply = <&pms405_l5>; + vddio-supply = <&pms405_l6>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rgb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + + clocks = <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, + <&clock_gcc GCC_MDSS_AHB_CLK>, + <&clock_gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&clock_gcc_mdss GCC_MDSS_BYTE0_CLK>, + <&clock_gcc_mdss GCC_MDSS_PCLK0_CLK>, + <&clock_gcc GCC_MDSS_ESC0_CLK>, + <&clock_gcc_mdss BYTE0_CLK_SRC>, + <&clock_gcc_mdss PCLK0_CLK_SRC>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_pixel0_clk", + "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg"; + + qcom,mdss-fb-map = <&mdss_fb0>; + qcom,mdss-mdp = <&mdss_mdp>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p8"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + }; + mdss_dsi: qcom,mdss_dsi@0 { compatible = "qcom,mdss-dsi"; hw-config = "single_dsi"; @@ -366,6 +456,7 @@ }; qcom,mdss_wb_panel { + status = "disabled"; compatible = "qcom,mdss_wb"; qcom,mdss_pan_res = <640 640>; qcom,mdss_pan_bpp = <24>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi index 175c6c74673f..6a120e3ad285 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -791,6 +791,472 @@ }; }; + mdss_rgb_data0_active: mdss_rgb_data0_active { + mux { + pins = "gpio26", "gpio41"; + function = "rgb_data0"; + }; + + config { + pins = "gpio26", "gpio41"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data0_suspend: mdss_rgb_data0_suspend { + mux { + pins = "gpio26", "gpio41"; + function = "rgb_data0"; + }; + + config { + pins = "gpio26", "gpio41"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data1_active: mdss_rgb_data1_active { + mux { + pins = "gpio27", "gpio42"; + function = "rgb_data1"; + }; + + config { + pins = "gpio27", "gpio42"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data1_suspend: mdss_rgb_data1_suspend { + mux { + pins = "gpio27", "gpio42"; + function = "rgb_data1"; + }; + + config { + pins = "gpio27", "gpio42"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data2_active: mdss_rgb_data2_active { + mux { + pins = "gpio28", "gpio43"; + function = "rgb_data2"; + }; + + config { + pins = "gpio28", "gpio43"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data2_suspend: mdss_rgb_data2_suspend { + mux { + pins = "gpio28", "gpio43"; + function = "rgb_data2"; + }; + + config { + pins = "gpio28", "gpio43"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data3_active: mdss_rgb_data3_active { + mux { + pins = "gpio29", "gpio44"; + function = "rgb_data3"; + }; + + config { + pins = "gpio29", "gpio44"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data3_suspend: mdss_rgb_data3_suspend { + mux { + pins = "gpio29", "gpio44"; + function = "rgb_data3"; + }; + + config { + pins = "gpio29", "gpio44"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data4_active: mdss_rgb_data4_active { + mux { + pins = "gpio39", "gpio45"; + function = "rgb_data4"; + }; + + config { + pins = "gpio39", "gpio45"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data4_suspend: mdss_rgb_data4_suspend { + mux { + pins = "gpio39", "gpio45"; + function = "rgb_data4"; + }; + + config { + pins = "gpio39", "gpio45"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data5_active: mdss_rgb_data5_active { + mux { + pins = "gpio40", "gpio46"; + function = "rgb_data5"; + }; + + config { + pins = "gpio40", "gpio46"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data5_suspend: mdss_rgb_data5_suspend { + mux { + pins = "gpio40", "gpio46"; + function = "rgb_data5"; + }; + + config { + pins = "gpio40", "gpio46"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b0_active: mdss_rgb_data_b0_active { + mux { + pins = "gpio47"; + function = "rgb_data_b0"; + }; + + config { + pins = "gpio47"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b0_suspend: mdss_rgb_data_b0_suspend { + mux { + pins = "gpio47"; + function = "rgb_data_b0"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b1_active: mdss_rgb_data_b1_active { + mux { + pins = "gpio48"; + function = "rgb_data_b1"; + }; + + config { + pins = "gpio48"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b1_suspend: mdss_rgb_data_b1_suspend { + mux { + pins = "gpio48"; + function = "rgb_data_b1"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b2_active: mdss_rgb_data_b2_active { + mux { + pins = "gpio49"; + function = "rgb_data_b2"; + }; + + config { + pins = "gpio49"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b2_suspend: mdss_rgb_data_b2_suspend { + mux { + pins = "gpio49"; + function = "rgb_data_b2"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b3_active: mdss_rgb_data_b3_active { + mux { + pins = "gpio50"; + function = "rgb_data_b3"; + }; + + config { + pins = "gpio50"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b3_suspend: mdss_rgb_data_b3_suspend { + mux { + pins = "gpio50"; + function = "rgb_data_b3"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b4_active: mdss_rgb_data_b4_active { + mux { + pins = "gpio51"; + function = "rgb_data_b4"; + }; + + config { + pins = "gpio51"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b4_suspend: mdss_rgb_data_b4_suspend { + mux { + pins = "gpio51"; + function = "rgb_data_b4"; + }; + + config { + pins = "gpio51"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b5_active: mdss_rgb_data_b5_active { + mux { + pins = "gpio52"; + function = "rgb_data_b5"; + }; + + config { + pins = "gpio52"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b5_suspend: mdss_rgb_data_b5_suspend { + mux { + pins = "gpio52"; + function = "rgb_data_b5"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_hsync_active: mdss_rgb_hsync_active { + mux { + pins = "gpio53"; + function = "rgb_hsync"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_hsync_suspend: mdss_rgb_hsync_suspend { + mux { + pins = "gpio53"; + function = "rgb_hsync"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_vsync_active: mdss_rgb_vsync_active { + mux { + pins = "gpio54"; + function = "rgb_vsync"; + }; + + config { + pins = "gpio54"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_vsync_suspend: mdss_rgb_vsync_suspend { + mux { + pins = "gpio54"; + function = "rgb_vsync"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_de_active: mdss_rgb_de_active { + mux { + pins = "gpio55"; + function = "rgb_de"; + }; + + config { + pins = "gpio55"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_de_suspend: mdss_rgb_de_suspend { + mux { + pins = "gpio55"; + function = "rgb_de"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_clk_active: mdss_rgb_clk_active { + mux { + pins = "gpio56"; + function = "rgb_clk"; + }; + + config { + pins = "gpio56"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_clk_suspend: mdss_rgb_clk_suspend { + mux { + pins = "gpio56"; + function = "rgb_clk"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_active: mdss_rgb_active { + mux { + pins = "gpio58"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + + mdss_rgb_suspend: mdss_rgb_suspend { + mux { + pins = "gpio58"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + pmx_mdss: pmx_mdss { mdss_dsi_active: mdss_dsi_active { mux { diff --git a/arch/arm64/boot/dts/qcom/rgb-panel-st7789v.dtsi b/arch/arm64/boot/dts/qcom/rgb-panel-st7789v.dtsi new file mode 100644 index 000000000000..9f18064b5c7d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/rgb-panel-st7789v.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + rgb_st7789v: qcom,mdss_rgb_st7789v { + qcom,mdss-rgb-panel-name = "st7789v LCD rgb panel"; + qcom,mdss-rgb-panel-framerate = <60>; + qcom,mdss-rgb-panel-width = <240>; + qcom,mdss-rgb-panel-height = <320>; + qcom,mdss-rgb-h-front-porch = <38>; + qcom,mdss-rgb-h-back-porch = <10>; + qcom,mdss-rgb-h-pulse-width = <10>; + qcom,mdss-rgb-h-sync-skew = <0>; + qcom,mdss-rgb-v-back-porch = <4>; + qcom,mdss-rgb-v-front-porch = <8>; + qcom,mdss-rgb-v-pulse-width = <4>; + qcom,mdss-rgb-bpp = <18>; + qcom,mdss-rgb-panel-clockrate = <6000000>; + }; +}; -- GitLab From 121b1d7b826bd28f10193af90eb10f96c1dc277f Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Tue, 18 Sep 2018 13:26:53 +0530 Subject: [PATCH 0780/1286] defconfig: qcs405: enable RGB parallel interface driver Enable config to support RGB parallel interface feature to drive RGB parallel data to RGB panel. Change-Id: Ide9f0e138f38a7070fef476d0b71c4fe1e7db2ff Signed-off-by: Narender Ankam --- arch/arm64/configs/vendor/qcs405-perf_defconfig | 1 + arch/arm64/configs/vendor/qcs405_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index f2fa37e3d825..ccc2b0457402 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -330,6 +330,7 @@ CONFIG_FB_MSM_MDSS=y CONFIG_FB_MSM_MDSS_WRITEBACK=y CONFIG_FB_MSM_MDSS_HDMI_PANEL=y CONFIG_FB_MSM_MDSS_SPI_PANEL=y +CONFIG_FB_MSM_MDSS_RGB_PANEL=y CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_SOUND=y diff --git a/arch/arm64/configs/vendor/qcs405_defconfig b/arch/arm64/configs/vendor/qcs405_defconfig index f98496149b6f..319c36689008 100644 --- a/arch/arm64/configs/vendor/qcs405_defconfig +++ b/arch/arm64/configs/vendor/qcs405_defconfig @@ -338,6 +338,7 @@ CONFIG_FB_MSM_MDSS=y CONFIG_FB_MSM_MDSS_WRITEBACK=y CONFIG_FB_MSM_MDSS_HDMI_PANEL=y CONFIG_FB_MSM_MDSS_SPI_PANEL=y +CONFIG_FB_MSM_MDSS_RGB_PANEL=y CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y CONFIG_BACKLIGHT_LCD_SUPPORT=y -- GitLab From c5536bcf32708c7994fd20f35a12845e7c4c9c01 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sat, 8 Dec 2018 22:35:36 +0530 Subject: [PATCH 0781/1286] clk: qcom: Add graphics clock driver for TRINKET Add support for the graphics clock controller found on TRINKET based devices. This allows graphics device drivers to probe and control their clocks. Change-Id: I66bbf2377f3cdc85ac8748537553bc7fb21938b8 Signed-off-by: Odelu Kukatla --- .../devicetree/bindings/clock/qcom,gpucc.txt | 3 +- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-trinket.c | 502 ++++++++++++++++++ .../dt-bindings/clock/qcom,gpucc-trinket.h | 11 +- 5 files changed, 518 insertions(+), 7 deletions(-) create mode 100644 drivers/clk/qcom/gpucc-trinket.c diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index a500819ceb31..c2636c8a0988 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -6,7 +6,8 @@ Required properties : "qcom,gpucc-sm8150", "qcom,gpucc-sdmshrike", "qcom,gpucc-sm6150", - "qcom,gpucc-sdmmagpie". + "qcom,gpucc-sdmmagpie", + "qcom,gpucc-trinket". - reg : shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 75d2e599b04f..2fed0a10f92a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -512,3 +512,11 @@ config SM_GCC_TRINKET TRINKET devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SD/eMMC, PCIe, etc. + +config SM_GPUCC_TRINKET + tristate "TRINKET graphics Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the graphics clock controller on Qualcomm Technologies, Inc. + TRINKET devices. + Say Y if you want to support graphics clocks. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c582b9a7a219..29c36074210a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o +obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-y += mdss/ diff --git a/drivers/clk/qcom/gpucc-trinket.c b/drivers/clk/qcom/gpucc-trinket.c new file mode 100644 index 000000000000..ba20a7aab732 --- /dev/null +++ b/drivers/clk/qcom/gpucc-trinket.c @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "vdd-level-trinket.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xf +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xf +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_MX_NUM, 1, vdd_mx_corner); + +enum { + P_BI_TCXO, + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_CLK, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_AUX2, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpu_cc_parent_names_0[] = { + "bi_tcxo", + "gpu_cc_pll0_out_main", + "gpu_cc_pll1_out_main", + "gpll0_out_main", + "gpll0_out_main_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_CLK, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX, 3 }, + { P_GPU_CC_PLL1_OUT_AUX2, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpu_cc_parent_names_1[] = { + "bi_tcxo", + "gpu_cc_pll0_out_aux", + "gpu_cc_pll0_out_aux2", + "gpu_cc_pll1_out_aux", + "gpu_cc_pll1_out_aux2", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static struct pll_vco gpu_cc_pll_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, +}; + +/* 1020MHz configuration */ +static const struct alpha_pll_config gpu_pll0_config = { + .l = 0x35, + .config_ctl_val = 0x4001055b, + .test_ctl_hi_mask = 0x1, + .alpha_u = 0x20, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpu_pll1_config = { + .l = 0x30, + .config_ctl_val = 0x4001055b, + .test_ctl_hi_mask = 0x1, + .alpha_u = 0x70, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_MX_NUM, + .rate_max = (unsigned long[VDD_MX_NUM]) { + [VDD_MX_MIN] = 1000000000, + [VDD_MX_NOMINAL] = 2000000000}, + }, + }, +}; + +static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { + .offset = 0x100, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux2", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_MX_NUM, + .rate_max = (unsigned long[VDD_MX_NUM]) { + [VDD_MX_MIN] = 1000000000, + [VDD_MX_NOMINAL] = 2000000000}, + }, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_names = gpu_cc_parent_names_0, + .num_parents = 6, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000}, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .flags = FORCE_ENABLE_RCG, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_names = gpu_cc_parent_names_1, + .num_parents = 7, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 320000000, + [VDD_LOW] = 465000000, + [VDD_LOW_L1] = 600000000, + [VDD_NOMINAL] = 745000000, + [VDD_NOMINAL_L1] = 820000000, + [VDD_HIGH] = 900000000}, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_names = (const char *[]){ + "gpu_cc_gx_gfx3d_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_slv_clk", + .parent_names = (const char *[]){ + "gpu_cc_gx_gfx3d_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_names = (const char *[]){ + "gpu_cc_gmu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_names = (const char *[]){ + "gpu_cc_gx_gfx3d_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_trinket_clocks[] = { + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, +}; + +static const struct regmap_config gpu_cc_trinket_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7008, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_trinket_desc = { + .config = &gpu_cc_trinket_regmap_config, + .clks = gpu_cc_trinket_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_trinket_clocks), +}; + +static const struct of_device_id gpu_cc_trinket_match_table[] = { + { .compatible = "qcom,gpucc-trinket" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_trinket_match_table); + +static int gpu_cc_trinket_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + unsigned int value, mask; + + /* Get CX voltage regulator for CX and GMU clocks. */ + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + /* Get MX voltage regulator for GPU PLL graphic clock. */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &gpu_cc_trinket_desc); + if (IS_ERR(regmap)) { + pr_err("Failed to map the gpu_cc registers\n"); + return PTR_ERR(regmap); + } + + clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, + &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, + &gpu_pll1_config); + + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, + mask, value); + + ret = qcom_cc_really_probe(pdev, &gpu_cc_trinket_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPU CC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered GPU CC clocks\n"); + + return ret; +} + +static struct platform_driver gpu_cc_trinket_driver = { + .probe = gpu_cc_trinket_probe, + .driver = { + .name = "gpu_cc-trinket", + .of_match_table = gpu_cc_trinket_match_table, + }, +}; + +static int __init gpu_cc_trinket_init(void) +{ + return platform_driver_register(&gpu_cc_trinket_driver); +} +subsys_initcall(gpu_cc_trinket_init); + +static void __exit gpu_cc_trinket_exit(void) +{ + platform_driver_unregister(&gpu_cc_trinket_driver); +} +module_exit(gpu_cc_trinket_exit); + +MODULE_DESCRIPTION("QTI GPU_CC TRINKET Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:gpu_cc-trinket"); diff --git a/include/dt-bindings/clock/qcom,gpucc-trinket.h b/include/dt-bindings/clock/qcom,gpucc-trinket.h index b42cc5215fca..1e70d9b328d5 100644 --- a/include/dt-bindings/clock/qcom,gpucc-trinket.h +++ b/include/dt-bindings/clock/qcom,gpucc-trinket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -24,12 +24,11 @@ #define GPU_CC_CX_GMU_CLK 6 #define GPU_CC_CX_SNOC_DVM_CLK 7 #define GPU_CC_CXO_AON_CLK 8 -#define GPU_CC_CXO_CLK 9 +#define GPU_CC_CXO_CLK 9 #define GPU_CC_GMU_CLK_SRC 10 #define GPU_CC_SLEEP_CLK 11 -#define GPU_CC_GX_CXO_CLK 12 -#define GPU_CC_GX_GFX3D_CLK 13 -#define GPU_CC_GX_GFX3D_CLK_SRC 14 -#define GPU_CC_AHB_CLK 15 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_AHB_CLK 14 #endif -- GitLab From fdb4c0b5a36d98bcdbe0ec7de232d9e456854ae4 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 9 Jan 2019 14:37:18 +0530 Subject: [PATCH 0782/1286] defconfig: arm: Enable USB Link Layer test support on qcs405 Enable Link Layer Test driver to allow for SuperSpeed link layer testing for electrical compliance in host mode. Change-Id: I2305a208bbdec0e25198d2a45325566d0e0f9105 Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/configs/vendor/qcs405-perf_defconfig | 1 + arch/arm/configs/vendor/qcs405_defconfig | 1 + arch/arm64/configs/vendor/qcs405-perf_defconfig | 1 + arch/arm64/configs/vendor/qcs405_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 3fac1d1d4389..604187fe19f8 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -343,6 +343,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm/configs/vendor/qcs405_defconfig b/arch/arm/configs/vendor/qcs405_defconfig index 640035fca2b7..a949d9717895 100644 --- a/arch/arm/configs/vendor/qcs405_defconfig +++ b/arch/arm/configs/vendor/qcs405_defconfig @@ -372,6 +372,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index be4aab11a9aa..815c12e7fc48 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -366,6 +366,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y diff --git a/arch/arm64/configs/vendor/qcs405_defconfig b/arch/arm64/configs/vendor/qcs405_defconfig index f98496149b6f..679942017ce3 100644 --- a/arch/arm64/configs/vendor/qcs405_defconfig +++ b/arch/arm64/configs/vendor/qcs405_defconfig @@ -374,6 +374,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y -- GitLab From 163c89fd500059ffa396d97f5a800bbfc06032fc Mon Sep 17 00:00:00 2001 From: Ramakrishna Gottimukkula Date: Wed, 9 Jan 2019 14:44:57 +0530 Subject: [PATCH 0783/1286] defconfig: trinket: Enable PAN emulation on Trinket Privilege Access Never (PAN) enforces the usage of copy_to_user/copy_from_user and friends when kernel accesses data from user space. If user space memory is accessed outside of these functions a kernel panic occurs. Change-Id: Ifd6284de52e28a6950ad785d9e75f23acb039a50 Signed-off-by: Ramakrishna Gottimukkula --- arch/arm64/configs/vendor/trinket-perf_defconfig | 2 ++ arch/arm64/configs/vendor/trinket_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..3517c4a9ba87 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -71,6 +71,8 @@ CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_SW_TTBR0_PAN=y +# CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..9f25e11143a8 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -77,6 +77,8 @@ CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_SW_TTBR0_PAN=y +# CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -- GitLab From a2ff4acb0fbccdabd0a6d98d783bf18d0770b5af Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 8 Jan 2019 15:11:41 +0530 Subject: [PATCH 0784/1286] clk: qcom: smd: Add rpm voter clocks for TRINKET Add support for rpm voter clocks so that each master clock can be voted separately. Change-Id: If17e52ee4be7d27809b2edb0ae7b465e1e7d3bbd Signed-off-by: Odelu Kukatla --- drivers/clk/qcom/clk-smd-rpm.c | 77 ++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 30 ++++++++++ 2 files changed, 107 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 750a78b26e5a..3c8c3d26e53a 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -739,6 +739,50 @@ static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(cnoc_keepalive_a_clk, cnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(snoc_keepalive_a_clk, snoc_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(vfe_mmrt_msmbus_clk, mmrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(vfe_mmrt_msmbus_a_clk, mmrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(mdp_mmrt_msmbus_clk, mmrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(mdp_mmrt_msmbus_a_clk, mmrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(cpp_mmnrt_msmbus_clk, mmnrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(cpp_mmnrt_msmbus_a_clk, mmnrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(jpeg_mmnrt_msmbus_clk, mmnrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(jpeg_mmnrt_msmbus_a_clk, mmnrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(venus_mmnrt_msmbus_clk, mmnrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(venus_mmnrt_msmbus_a_clk, mmnrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(arm9_mmnrt_msmbus_clk, mmnrt_clk, LONG_MAX); +static DEFINE_CLK_VOTER(arm9_mmnrt_msmbus_a_clk, mmnrt_a_clk, LONG_MAX); +static DEFINE_CLK_VOTER(qup0_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(qup0_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(qup1_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(qup1_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(dap_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(dap_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc1_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc1_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc2_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc2_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(crypto_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(crypto_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc1_slv_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc1_slv_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc2_slv_msmbus_snoc_periph_clk, snoc_periph_clk, + LONG_MAX); +static DEFINE_CLK_VOTER(sdc2_slv_msmbus_snoc_periph_a_clk, snoc_periph_a_clk, + LONG_MAX); /* Branch Voter clocks */ static DEFINE_CLK_BRANCH_VOTER(bi_tcxo_otg_clk, bi_tcxo); @@ -779,6 +823,39 @@ static struct clk_hw *trinket_clks[] = { [SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw, [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, [BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw, + [CPP_MMNRT_MSMBUS_CLK] = &cpp_mmnrt_msmbus_clk.hw, + [CPP_MMNRT_MSMBUS_A_CLK] = &cpp_mmnrt_msmbus_a_clk.hw, + [JPEG_MMNRT_MSMBUS_CLK] = &jpeg_mmnrt_msmbus_clk.hw, + [JPEG_MMNRT_MSMBUS_A_CLK] = &jpeg_mmnrt_msmbus_a_clk.hw, + [VENUS_MMNRT_MSMBUS_CLK] = &venus_mmnrt_msmbus_clk.hw, + [VENUS_MMNRT_MSMBUS_A_CLK] = &venus_mmnrt_msmbus_a_clk.hw, + [ARM9_MMNRT_MSMBUS_CLK] = &arm9_mmnrt_msmbus_clk.hw, + [ARM9_MMNRT_MSMBUS_A_CLK] = &arm9_mmnrt_msmbus_a_clk.hw, + [VFE_MMRT_MSMBUS_CLK] = &vfe_mmrt_msmbus_clk.hw, + [VFE_MMRT_MSMBUS_A_CLK] = &vfe_mmrt_msmbus_a_clk.hw, + [MDP_MMRT_MSMBUS_CLK] = &mdp_mmrt_msmbus_clk.hw, + [MDP_MMRT_MSMBUS_A_CLK] = &mdp_mmrt_msmbus_a_clk.hw, + [QUP0_MSMBUS_SNOC_PERIPH_CLK] = &qup0_msmbus_snoc_periph_clk.hw, + [QUP0_MSMBUS_SNOC_PERIPH_A_CLK] = &qup0_msmbus_snoc_periph_a_clk.hw, + [QUP1_MSMBUS_SNOC_PERIPH_CLK] = &qup1_msmbus_snoc_periph_clk.hw, + [QUP1_MSMBUS_SNOC_PERIPH_A_CLK] = &qup1_msmbus_snoc_periph_a_clk.hw, + [DAP_MSMBUS_SNOC_PERIPH_CLK] = &dap_msmbus_snoc_periph_clk.hw, + [DAP_MSMBUS_SNOC_PERIPH_A_CLK] = &dap_msmbus_snoc_periph_a_clk.hw, + [SDC1_MSMBUS_SNOC_PERIPH_CLK] = &sdc1_msmbus_snoc_periph_clk.hw, + [SDC1_MSMBUS_SNOC_PERIPH_A_CLK] = &sdc1_msmbus_snoc_periph_a_clk.hw, + [SDC2_MSMBUS_SNOC_PERIPH_CLK] = &sdc2_msmbus_snoc_periph_clk.hw, + [SDC2_MSMBUS_SNOC_PERIPH_A_CLK] = &sdc2_msmbus_snoc_periph_a_clk.hw, + [CRYPTO_MSMBUS_SNOC_PERIPH_CLK] = &crypto_msmbus_snoc_periph_clk.hw, + [CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK] = + &crypto_msmbus_snoc_periph_a_clk.hw, + [SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK] = + &sdc1_slv_msmbus_snoc_periph_clk.hw, + [SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK] = + &sdc1_slv_msmbus_snoc_periph_a_clk.hw, + [SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK] = + &sdc2_slv_msmbus_snoc_periph_clk.hw, + [SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK] = + &sdc2_slv_msmbus_snoc_periph_a_clk.hw, [MCD_CE1_CLK] = &mcd_ce1_clk.hw, [QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw, [QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw, diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index a76ab72c4875..b28280e8f969 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -164,5 +164,35 @@ #define CNOC_MSMBUS_A_CLK 122 #define CNOC_KEEPALIVE_A_CLK 123 #define SNOC_KEEPALIVE_A_CLK 124 +#define CPP_MMNRT_MSMBUS_CLK 125 +#define CPP_MMNRT_MSMBUS_A_CLK 126 +#define JPEG_MMNRT_MSMBUS_CLK 127 +#define JPEG_MMNRT_MSMBUS_A_CLK 128 +#define VENUS_MMNRT_MSMBUS_CLK 129 +#define VENUS_MMNRT_MSMBUS_A_CLK 130 +#define ARM9_MMNRT_MSMBUS_CLK 131 +#define ARM9_MMNRT_MSMBUS_A_CLK 132 +#define MDP_MMRT_MSMBUS_CLK 133 +#define MDP_MMRT_MSMBUS_A_CLK 134 +#define VFE_MMRT_MSMBUS_CLK 135 +#define VFE_MMRT_MSMBUS_A_CLK 136 +#define QUP0_MSMBUS_SNOC_PERIPH_CLK 137 +#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK 138 +#define QUP1_MSMBUS_SNOC_PERIPH_CLK 139 +#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK 140 +#define QUP2_MSMBUS_SNOC_PERIPH_CLK 141 +#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK 142 +#define DAP_MSMBUS_SNOC_PERIPH_CLK 143 +#define DAP_MSMBUS_SNOC_PERIPH_A_CLK 144 +#define SDC1_MSMBUS_SNOC_PERIPH_CLK 145 +#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK 146 +#define SDC2_MSMBUS_SNOC_PERIPH_CLK 147 +#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK 148 +#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK 149 +#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK 150 +#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK 151 +#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK 152 +#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK 153 +#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK 154 #endif -- GitLab From 1a4a7c46e6fc47a9868cfa9d2e528260feacf798 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Mon, 7 Jan 2019 11:37:47 +0530 Subject: [PATCH 0785/1286] msm: vidc: add proper check for max secure instance allowed Current driver design allows one additional secure instance than max limit since the secure flags were updated later for the current instance. The change adds proper checks for the same. Change-Id: If08e04bee09d91bb33604fea7debeda3da14850f Signed-off-by: Dikshita Agarwal --- drivers/media/platform/msm/vidc/msm_vdec.c | 7 ++- drivers/media/platform/msm/vidc/msm_vidc.c | 29 +----------- .../media/platform/msm/vidc/msm_vidc_common.c | 25 ++++++++++- .../media/platform/msm/vidc/msm_vidc_common.h | 3 +- .../platform/msm/vidc/msm_vidc_platform.c | 44 ++++--------------- 5 files changed, 42 insertions(+), 66 deletions(-) diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c index 9b0224c1298e..6901d545f878 100644 --- a/drivers/media/platform/msm/vidc/msm_vdec.c +++ b/drivers/media/platform/msm/vidc/msm_vdec.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1024,6 +1024,11 @@ int msm_vdec_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) pdata = &property_val; dprintk(VIDC_DBG, "Setting secure mode to: %d\n", !!(inst->flags & VIDC_SECURE)); + if (msm_comm_check_for_inst_overload(inst->core)) { + dprintk(VIDC_ERR, + "Secure Instance reached Max limit, rejecting session\n"); + return -ENOTSUPP; + } break; case V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA: property_id = HAL_PARAM_INDEX_EXTRADATA; diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c index 438d1df63465..45fdd760e57c 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc.c +++ b/drivers/media/platform/msm/vidc/msm_vidc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1608,31 +1608,6 @@ int msm_vidc_private(void *vidc_inst, unsigned int cmd, return rc; } EXPORT_SYMBOL(msm_vidc_private); - -static bool msm_vidc_check_for_inst_overload(struct msm_vidc_core *core) -{ - u32 instance_count = 0; - u32 secure_instance_count = 0; - struct msm_vidc_inst *inst = NULL; - bool overload = false; - - mutex_lock(&core->lock); - list_for_each_entry(inst, &core->instances, list) { - instance_count++; - /* This flag is not updated yet for the current instance */ - if (inst->flags & VIDC_SECURE) - secure_instance_count++; - } - mutex_unlock(&core->lock); - - /* Instance count includes current instance as well. */ - - if ((instance_count > core->resources.max_inst_count) || - (secure_instance_count > core->resources.max_secure_inst_count)) - overload = true; - return overload; -} - static int msm_vidc_try_set_ctrl(void *instance, struct v4l2_ctrl *ctrl) { struct msm_vidc_inst *inst = instance; @@ -1933,7 +1908,7 @@ void *msm_vidc_open(int core_id, int session_type) } msm_dcvs_try_enable(inst); - if (msm_vidc_check_for_inst_overload(core)) { + if (msm_comm_check_for_inst_overload(core)) { dprintk(VIDC_ERR, "Instance count reached Max limit, rejecting session"); goto fail_init; diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c index a3f86a909244..1b316de5d6e0 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -6967,3 +6967,26 @@ int msm_comm_set_color_format_constraints(struct msm_vidc_inst *inst, kfree(pconstraint); return rc; } + +bool msm_comm_check_for_inst_overload(struct msm_vidc_core *core) +{ + u32 instance_count = 0; + u32 secure_instance_count = 0; + struct msm_vidc_inst *inst = NULL; + bool overload = false; + + mutex_lock(&core->lock); + list_for_each_entry(inst, &core->instances, list) { + instance_count++; + if (inst->flags & VIDC_SECURE) + secure_instance_count++; + } + mutex_unlock(&core->lock); + + /* Instance count includes current instance as well. */ + + if ((instance_count > core->resources.max_inst_count) || + (secure_instance_count > core->resources.max_secure_inst_count)) + overload = true; + return overload; +} diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.h b/drivers/media/platform/msm/vidc/msm_vidc_common.h index 954bb65d0668..497a1df01c9e 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_common.h +++ b/drivers/media/platform/msm/vidc/msm_vidc_common.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -252,4 +252,5 @@ int msm_comm_release_mark_data(struct msm_vidc_inst *inst); int msm_comm_qbuf_decode_batch(struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf); int msm_comm_num_queued_bufs(struct msm_vidc_inst *inst, u32 type); +bool msm_comm_check_for_inst_overload(struct msm_vidc_core *core); #endif diff --git a/drivers/media/platform/msm/vidc/msm_vidc_platform.c b/drivers/media/platform/msm/vidc/msm_vidc_platform.c index 9db4a4547603..3cd10402f0ff 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_platform.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_platform.c @@ -170,14 +170,7 @@ static struct msm_vidc_common_data sm6150_common_data[] = { }, { .key = "qcom,max-secure-instances", - .value = 2, /* - * As per design driver allows 3rd - * instance as well since the secure - * flags were updated later for the - * current instance. Hence total - * secure sessions would be - * max-secure-instances + 1. - */ + .value = 3, }, { .key = "qcom,max-hw-load", @@ -236,7 +229,7 @@ static struct msm_vidc_common_data trinket_common_data[] = { }, { .key = "qcom,max-secure-instances", - .value = 5, + .value = 6, }, { .key = "qcom,max-hw-load", @@ -295,14 +288,7 @@ static struct msm_vidc_common_data sm8150_common_data[] = { }, { .key = "qcom,max-secure-instances", - .value = 2, /* - * As per design driver allows 3rd - * instance as well since the secure - * flags were updated later for the - * current instance. Hence total - * secure sessions would be - * max-secure-instances + 1. - */ + .value = 3, }, { .key = "qcom,max-hw-load", @@ -378,14 +364,7 @@ static struct msm_vidc_common_data sdmmagpie_common_data_v0[] = { }, { .key = "qcom,max-secure-instances", - .value = 2, /* - * As per design driver allows 3rd - * instance as well since the secure - * flags were updated later for the - * current instance. Hence total - * secure sessions would be - * max-secure-instances + 1. - */ + .value = 3, }, { .key = "qcom,max-hw-load", @@ -456,14 +435,7 @@ static struct msm_vidc_common_data sdmmagpie_common_data_v1[] = { }, { .key = "qcom,max-secure-instances", - .value = 2, /* - * As per design driver allows 3rd - * instance as well since the secure - * flags were updated later for the - * current instance. Hence total - * secure sessions would be - * max-secure-instances + 1. - */ + .value = 3, }, { .key = "qcom,max-hw-load", @@ -538,7 +510,7 @@ static struct msm_vidc_common_data sdm845_common_data[] = { }, { .key = "qcom,max-secure-instances", - .value = 5, + .value = 3, }, { .key = "qcom,max-hw-load", @@ -593,7 +565,7 @@ static struct msm_vidc_common_data sdm670_common_data_v0[] = { }, { .key = "qcom,max-secure-instances", - .value = 5, + .value = 6, }, { .key = "qcom,max-hw-load", @@ -644,7 +616,7 @@ static struct msm_vidc_common_data sdm670_common_data_v1[] = { }, { .key = "qcom,max-secure-instances", - .value = 5, + .value = 6, }, { .key = "qcom,max-hw-load", -- GitLab From 53037026e78d123b385a63b8bd48f72e38622031 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Thu, 29 Nov 2018 12:46:50 +0530 Subject: [PATCH 0786/1286] ARM: dts: msm: Add support for S1 SMMU functionality on TRINKET Add iommu node for USB to enable support for S1 SMMU functionality on Trinket. Change-Id: Idfea0a02367d1fd2bced71c1c0f7c83c70e0446d Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index ce6da358228b..6f0247706c10 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -21,6 +21,7 @@ reg = <0x4e00000 0x100000>; reg-names = "core_base"; + iommus = <&apps_smmu 0x100 0x0>; #address-cells = <1>; #size-cells = <1>; ranges; -- GitLab From 4baa1ab856714e1a347818888cd96163a2a83305 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Tue, 8 Jan 2019 18:10:18 +0530 Subject: [PATCH 0787/1286] ARM: dts: msm: Update correct address for rpm ram for trinket Correct rpm ram address for rpm stats. Change-Id: Id4d8c724f9feab142853c5ef44e1d1b4035ef134 Signed-off-by: Raghavendra Kakarla --- arch/arm64/boot/dts/qcom/trinket-pm.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-pm.dtsi b/arch/arm64/boot/dts/qcom/trinket-pm.dtsi index 773216ac082c..7c19a94db509 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pm.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pm.dtsi @@ -204,11 +204,11 @@ }; }; - qcom,rpm-stats@200000 { + qcom,rpm-stats@4600000 { compatible = "qcom,rpm-stats"; - reg = <0x200000 0x1000>, - <0x290014 0x4>, - <0x29001c 0x4>; + reg = <0x04600000 0x1000>, + <0x04690014 0x4>, + <0x0469001c 0x4>; reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase"; qcom,sleep-stats-version = <2>; -- GitLab From 07a8874db1e8dac3edc764c10ea035d326f8761a Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Wed, 9 Jan 2019 15:38:29 +0530 Subject: [PATCH 0788/1286] ARM: dts: msm: Enable avb 2.0 verity for vendor partition for trinket Update fsmgr_flags for vendor partition to have verity enabled. Change-Id: I115a9f97c11946f62db8bcb570de0ac5fd610338 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..765e7517530c 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -387,7 +387,7 @@ dev = "/dev/block/platform/soc/4804000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro.barrier=1,discard"; - fsmgr_flags = "wait,slotselect"; + fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; -- GitLab From c11f2b1519bd20a9accdcd0aa92417fd849a71a4 Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Mon, 17 Dec 2018 21:54:59 +0530 Subject: [PATCH 0789/1286] ARM: dts: msm: Update the dummy GDSCs with actual GDSCs Update the Trinket GDSCs by replacing the dummy nodes with actual GDSC regulator driver. Also add support for turing_mmu and mm_snoc_mmu GDSCs. Change-Id: I76ac062c3f91ff7471f67cdf8836c07553c10ecf Signed-off-by: Diptanshu Jamgade --- arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi | 58 ++++++++++++++++++---- arch/arm64/boot/dts/qcom/trinket.dtsi | 16 ++++++ 2 files changed, 63 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi b/arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi index 8738bb5d9326..d8f935d90926 100644 --- a/arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi @@ -14,50 +14,86 @@ &soc { /* GDSCs in Global CC */ camss_cpp_gdsc: qcom,gdsc@14560bc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "cam_cpp_gdsc"; reg = <0x14560bc 0x4>; status = "disabled"; }; camss_top_gdsc: qcom,gdsc@145607c { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "camss_top_gdsc"; reg = <0x145607c 0x4>; status = "disabled"; }; camss_vfe0_gdsc: qcom,gdsc@1454004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "camss_vfe0_gdsc"; reg = <0x1454004 0x4>; status = "disabled"; }; camss_vfe1_gdsc: qcom,gdsc@145403c { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "camss_vfe1_gdsc"; reg = <0x145403c 0x4>; status = "disabled"; }; ufs_phy_gdsc: qcom,gdsc@1445004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "ufs_phy_gdsc"; reg = <0x1445004 0x4>; status = "disabled"; }; usb30_prim_gdsc: qcom,gdsc@141a004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "usb30_prim_gdsc"; reg = <0x141a004 0x4>; status = "disabled"; }; + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x147d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@1480094 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x1480094 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@1480074 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + reg = <0x1480074 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@1480084 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + reg = <0x1480084 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + /* GDSCs in Display CC */ mdss_core_gdsc: qcom,gdsc@5f03000 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "mdss_core_gdsc"; reg = <0x5f03000 0x4>; qcom,support-hw-trigger; @@ -73,7 +109,7 @@ }; gpu_cx_gdsc: qcom,gdsc@599106c { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "gpu_cx_gdsc"; reg = <0x599106c 0x4>; hw-ctrl-addr = <&gpu_cx_hw_ctrl>; @@ -84,7 +120,7 @@ }; gpu_gx_gdsc: qcom,gdsc@599100c { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "gpu_gx_gdsc"; reg = <0x599100c 0x4>; status = "disabled"; @@ -92,14 +128,14 @@ /* GDSCs in Video CC */ vcodec0_gdsc: qcom,gdsc@5b00874 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "vcodec0_gdsc"; reg = <0x5b00874 0x4>; status = "disabled"; }; venus_gdsc: qcom,gdsc@5b00814 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; regulator-name = "venus_gdsc"; reg = <0x5b00814 0x4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..42eac8f74d1e 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2152,6 +2152,22 @@ status = "ok"; }; +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + &mdss_core_gdsc { status = "ok"; }; -- GitLab From 62e31c6d74b678e3ec2c9f4f10b68ba3a51bf0fc Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sat, 15 Dec 2018 21:07:40 +0530 Subject: [PATCH 0790/1286] clk: qcom: Add video clock driver for TRINKET Add support for the video clock controller found on TRINKET based devices. This would allow video device drivers to probe and control their clocks. Change-Id: I9fa584fe704c4d632b888f5e8370b6fdbe492d4b Signed-off-by: Odelu Kukatla --- .../bindings/clock/qcom,videocc.txt | 3 +- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-trinket.c | 388 ++++++++++++++++++ .../dt-bindings/clock/qcom,videocc-trinket.h | 30 ++ 5 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/qcom/videocc-trinket.c create mode 100644 include/dt-bindings/clock/qcom,videocc-trinket.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt index 38dd889acdef..6a5232b5b6ec 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -2,7 +2,8 @@ Qualcomm Technologies, Inc. Video Clock & Reset Controller Bindings Required properties: - compatible: shall contain "qcom,videocc-sm8150" or "qcom,videocc-sm8150-v2" or - "qcom,videocc-sm6150", "qcom,videocc-sdmmagpie". + "qcom,videocc-sm6150", "qcom,videocc-sdmmagpie" or + "qcom,videocc-trinket". - reg: shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. - vdd_-supply: the logic rail supply which could be either MM or CX. diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 2fed0a10f92a..2b5d7e553f8b 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -520,3 +520,12 @@ config SM_GPUCC_TRINKET Support for the graphics clock controller on Qualcomm Technologies, Inc. TRINKET devices. Say Y if you want to support graphics clocks. + +config SM_VIDEOCC_TRINKET + tristate "TRINKET Video Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the video clock controller on Qualcomm Technologies, Inc. + TRINKET devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 29c36074210a..4a3c53d38da7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o +obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-y += mdss/ diff --git a/drivers/clk/qcom/videocc-trinket.c b/drivers/clk/qcom/videocc-trinket.c new file mode 100644 index 000000000000..a24081c5580f --- /dev/null +++ b/drivers/clk/qcom/videocc-trinket.c @@ -0,0 +1,388 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "vdd-level-trinket.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); + +enum { + P_BI_TCXO, + P_CHIP_SLEEP_CLK, + P_CORE_BI_PLL_TEST_SE, + P_VIDEO_PLL0_OUT_AUX, + P_VIDEO_PLL0_OUT_AUX2, + P_VIDEO_PLL0_OUT_MAIN, +}; + +static const struct parent_map video_cc_parent_map_0[] = { + { P_CHIP_SLEEP_CLK, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const video_cc_parent_names_0[] = { + "chip_sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, + { P_VIDEO_PLL0_OUT_AUX, 2 }, + { P_VIDEO_PLL0_OUT_AUX2, 3 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const video_cc_parent_names_1[] = { + "bi_tcxo", + "video_pll0_out_main", + "video_pll0_out_aux", + "video_pll0_out_aux2", + "core_bi_pll_test_se", +}; + +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const video_cc_parent_names_2[] = { + "bi_tcxo", + "core_bi_pll_test_se", +}; + +static struct pll_vco video_cc_pll_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +/* 600MHz configuration */ +static const struct alpha_pll_config video_pll0_config = { + .l = 0x1F, + .alpha_u = 0x40, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, + .test_ctl_hi_mask = 0x1, +}; + +static struct clk_alpha_pll video_pll0_out_main = { + .offset = 0x42c, + .vco_table = video_cc_pll_vco, + .num_vco = ARRAY_SIZE(video_cc_pll_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "video_pll0_out_main", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 1000000000, + [VDD_NOMINAL] = 2000000000}, + }, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { + F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src = { + .cmd_rcgr = 0xaf8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_0, + .freq_tbl = ftbl_video_cc_sleep_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_cc_sleep_clk_src", + .parent_names = video_cc_parent_names_0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 32000}, + }, +}; + +static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0), + F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_venus_clk_src = { + .cmd_rcgr = 0x7f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_venus_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_clk_src", + .parent_names = video_cc_parent_names_1, + .num_parents = 5, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 133333333, + [VDD_LOW] = 240000000, + [VDD_LOW_L1] = 300000000, + [VDD_NOMINAL] = 380000000, + [VDD_NOMINAL_L1] = 410000000, + [VDD_HIGH] = 460000000}, + }, +}; + +static struct clk_branch video_cc_apb_clk = { + .halt_reg = 0x990, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x990, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sleep_clk = { + .halt_reg = 0xb18, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb18, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_sleep_clk", + .parent_names = (const char *[]){ + "video_cc_sleep_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_axi_clk = { + .halt_reg = 0x8f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_vcodec0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_core_clk = { + .halt_reg = 0x890, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x890, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_vcodec0_core_clk", + .parent_names = (const char *[]){ + "video_cc_venus_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ahb_clk = { + .halt_reg = 0x9b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_axi_clk = { + .halt_reg = 0x8d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8d0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ctl_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_core_clk = { + .halt_reg = 0x850, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x850, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ctl_core_clk", + .parent_names = (const char *[]){ + "video_cc_venus_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_xo_clk = { + .halt_reg = 0xab8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xab8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *video_cc_trinket_clocks[] = { + [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr, + [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, + [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, + [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, + [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, + [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, + [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, + [VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr, + [VIDEO_PLL0_OUT_MAIN] = &video_pll0_out_main.clkr, +}; + +static const struct regmap_config video_cc_trinket_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xb94, + .fast_io = true, +}; + +static const struct qcom_cc_desc video_cc_trinket_desc = { + .config = &video_cc_trinket_regmap_config, + .clks = video_cc_trinket_clocks, + .num_clks = ARRAY_SIZE(video_cc_trinket_clocks), +}; + +static const struct of_device_id video_cc_trinket_match_table[] = { + { .compatible = "qcom,videocc-trinket" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_trinket_match_table); + +static int video_cc_trinket_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &video_cc_trinket_desc); + if (IS_ERR(regmap)) { + pr_err("Failed to map the video_cc registers\n"); + return PTR_ERR(regmap); + } + + clk_alpha_pll_configure(&video_pll0_out_main, regmap, + &video_pll0_config); + + ret = qcom_cc_really_probe(pdev, &video_cc_trinket_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register Video CC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered Video CC clocks\n"); + + return ret; +} + +static struct platform_driver video_cc_trinket_driver = { + .probe = video_cc_trinket_probe, + .driver = { + .name = "video_cc-trinket", + .of_match_table = video_cc_trinket_match_table, + }, +}; + +static int __init video_cc_trinket_init(void) +{ + return platform_driver_register(&video_cc_trinket_driver); +} +subsys_initcall(video_cc_trinket_init); + +static void __exit video_cc_trinket_exit(void) +{ + platform_driver_unregister(&video_cc_trinket_driver); +} +module_exit(video_cc_trinket_exit); + +MODULE_DESCRIPTION("QTI VIDEO_CC TRINKET Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:video_cc-trinket"); diff --git a/include/dt-bindings/clock/qcom,videocc-trinket.h b/include/dt-bindings/clock/qcom,videocc-trinket.h new file mode 100644 index 000000000000..a605b834a791 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-trinket.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_TRINKET_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_TRINKET_H + +/* VIDEOCC clock registers */ +#define VIDEO_PLL0_OUT_MAIN 0 +#define VIDEO_CC_APB_CLK 1 +#define VIDEO_CC_SLEEP_CLK 2 +#define VIDEO_CC_SLEEP_CLK_SRC 3 +#define VIDEO_CC_VCODEC0_AXI_CLK 4 +#define VIDEO_CC_VCODEC0_CORE_CLK 5 +#define VIDEO_CC_VENUS_AHB_CLK 6 +#define VIDEO_CC_VENUS_CLK_SRC 7 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 8 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 9 +#define VIDEO_CC_XO_CLK 10 + +#endif -- GitLab From c696b44563716fedab1eaad47424f811986d418d Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sat, 15 Dec 2018 21:11:09 +0530 Subject: [PATCH 0791/1286] clk: qcom: Add display clock driver for TRINKET Add support for the display clock controller found on TRINKET based devices. This would allow display device drivers to probe and control their clocks. Change-Id: I20c294ec2cfa7eced3c677bd84027af27d3a6cb9 Signed-off-by: Odelu Kukatla --- .../devicetree/bindings/clock/qcom,dispcc.txt | 3 +- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-trinket.c | 798 ++++++++++++++++++ .../dt-bindings/clock/qcom,dispcc-trinket.h | 51 +- 5 files changed, 841 insertions(+), 21 deletions(-) create mode 100644 drivers/clk/qcom/dispcc-trinket.c diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt index 0c2aefae8414..b1e3e93d93ed 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt @@ -6,7 +6,8 @@ Required properties : "qcom,dispcc-sm8150", "qcom,dispcc-sm8150-v2", "qcom,dispcc-sm6150", - "qcom,dispcc-sdmmagpie". + "qcom,dispcc-sdmmagpie", + "qcom,dispcc-trinket". - reg : Shall contain base register location and length. - reg-names: Address name. Must be "cc_base". - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 2b5d7e553f8b..043ce96117f4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -529,3 +529,12 @@ config SM_VIDEOCC_TRINKET TRINKET devices. Say Y if you want to support video devices and functionality such as video encode/decode. + +config SM_DISPCC_TRINKET + tristate "TRINKET Display Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the display clock controller on Qualcomm Technologies, Inc + TRINKET devices. + Say Y if you want to support display devices and functionality such as + splash screen. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4a3c53d38da7..19b20faf7f36 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o diff --git a/drivers/clk/qcom/dispcc-trinket.c b/drivers/clk/qcom/dispcc-trinket.c new file mode 100644 index 000000000000..e5ef9d9188a0 --- /dev/null +++ b/drivers/clk/qcom/dispcc-trinket.c @@ -0,0 +1,798 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "vdd-level-trinket.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); + +enum { + P_BI_TCXO, + P_CHIP_SLEEP_CLK, + P_CORE_BI_PLL_TEST_SE, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_0[] = { + "bi_tcxo", + "core_bi_pll_test_se", +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_1[] = { + "bi_tcxo", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_2[] = { + "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "core_bi_pll_test_se", +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_3[] = { + "bi_tcxo", + "disp_cc_pll0_out_main", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_4[] = { + "bi_tcxo", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_5[] = { + "bi_tcxo", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "core_bi_pll_test_se", +}; + +static struct pll_vco disp_cc_pll_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +/* 768MHz configuration */ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x28, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, + .test_ctl_hi_mask = 0x1, +}; + +static struct clk_alpha_pll disp_cc_pll0_out_main = { + .offset = 0x0, + .vco_table = disp_cc_pll_vco, + .num_vco = ARRAY_SIZE(disp_cc_pll_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0_out_main", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 1000000000, + [VDD_NOMINAL] = 2000000000}, + }, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_names = disp_cc_parent_names_4, + .num_parents = 3, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 37500000, + [VDD_NOMINAL] = 75000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x20bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_names = disp_cc_parent_names_2, + .num_parents = 3, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_byte2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 164000000, + [VDD_LOW] = 187500000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x213c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_names = disp_cc_parent_names_0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { + F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x210c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 180000, + [VDD_LOW_L1] = 360000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { + F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x20f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 270000, + [VDD_LOW_L1] = 540000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x2124, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_dp_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 337500}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x20d8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_names = disp_cc_parent_names_2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x2074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_names = disp_cc_parent_names_3, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 192000000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 307000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x205c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_names = disp_cc_parent_names_5, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_pixel_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 183310056, + [VDD_LOW] = 250000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x208c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_names = disp_cc_parent_names_3, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 192000000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 307000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x20a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_names = disp_cc_parent_names_0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_byte0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x2028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_byte0_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x2038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_crypto_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_pixel_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x202c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x202c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_esc0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_mdp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x2018, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x2018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_mdp_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_pclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x2010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_rot_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_vsync_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_xo_clk = { + .halt_reg = 0x604c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x604c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *disp_cc_trinket_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0_OUT_MAIN] = &disp_cc_pll0_out_main.clkr, + [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, +}; + +static const struct regmap_config disp_cc_trinket_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_trinket_desc = { + .config = &disp_cc_trinket_regmap_config, + .clks = disp_cc_trinket_clocks, + .num_clks = ARRAY_SIZE(disp_cc_trinket_clocks), +}; + +static const struct of_device_id disp_cc_trinket_match_table[] = { + { .compatible = "qcom,dispcc-trinket" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_trinket_match_table); + +static int disp_cc_trinket_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &disp_cc_trinket_desc); + if (IS_ERR(regmap)) { + pr_err("Failed to map the disp_cc registers\n"); + return PTR_ERR(regmap); + } + + clk_alpha_pll_configure(&disp_cc_pll0_out_main, regmap, + &disp_cc_pll0_config); + + ret = qcom_cc_really_probe(pdev, &disp_cc_trinket_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register Display CC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered Display CC clocks\n"); + + return ret; +} + +static struct platform_driver disp_cc_trinket_driver = { + .probe = disp_cc_trinket_probe, + .driver = { + .name = "disp_cc-trinket", + .of_match_table = disp_cc_trinket_match_table, + }, +}; + +static int __init disp_cc_trinket_init(void) +{ + return platform_driver_register(&disp_cc_trinket_driver); +} +subsys_initcall(disp_cc_trinket_init); + +static void __exit disp_cc_trinket_exit(void) +{ + platform_driver_unregister(&disp_cc_trinket_driver); +} +module_exit(disp_cc_trinket_exit); + +MODULE_DESCRIPTION("QTI DISP_CC trinket Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:disp_cc-trinket"); diff --git a/include/dt-bindings/clock/qcom,dispcc-trinket.h b/include/dt-bindings/clock/qcom,dispcc-trinket.h index b42cc5215fca..ce503928ba9b 100644 --- a/include/dt-bindings/clock/qcom,dispcc-trinket.h +++ b/include/dt-bindings/clock/qcom,dispcc-trinket.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,25 +11,36 @@ * GNU General Public License for more details. */ -#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_TRINKET_H -#define _DT_BINDINGS_CLK_QCOM_GPU_CC_TRINKET_H +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_TRINKET_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_TRINKET_H -/* GPUCC clock registers */ -#define GPU_CC_PLL0_OUT_AUX2 0 -#define GPU_CC_PLL1_OUT_AUX2 1 -#define GPU_CC_CRC_AHB_CLK 2 -#define GPU_CC_CX_APB_CLK 3 -#define GPU_CC_CX_GFX3D_CLK 4 -#define GPU_CC_CX_GFX3D_SLV_CLK 5 -#define GPU_CC_CX_GMU_CLK 6 -#define GPU_CC_CX_SNOC_DVM_CLK 7 -#define GPU_CC_CXO_AON_CLK 8 -#define GPU_CC_CXO_CLK 9 -#define GPU_CC_GMU_CLK_SRC 10 -#define GPU_CC_SLEEP_CLK 11 -#define GPU_CC_GX_CXO_CLK 12 -#define GPU_CC_GX_GFX3D_CLK 13 -#define GPU_CC_GX_GFX3D_CLK_SRC 14 -#define GPU_CC_AHB_CLK 15 +#define DISP_CC_PLL0_OUT_MAIN 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_DP_AUX_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9 +#define DISP_CC_MDSS_DP_LINK_CLK 10 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 12 +#define DISP_CC_MDSS_DP_PIXEL_CLK 13 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 14 +#define DISP_CC_MDSS_ESC0_CLK 15 +#define DISP_CC_MDSS_ESC0_CLK_SRC 16 +#define DISP_CC_MDSS_MDP_CLK 17 +#define DISP_CC_MDSS_MDP_CLK_SRC 18 +#define DISP_CC_MDSS_MDP_LUT_CLK 19 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 20 +#define DISP_CC_MDSS_PCLK0_CLK 21 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 22 +#define DISP_CC_MDSS_ROT_CLK 23 +#define DISP_CC_MDSS_ROT_CLK_SRC 24 +#define DISP_CC_MDSS_VSYNC_CLK 25 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 26 +#define DISP_CC_XO_CLK 27 #endif -- GitLab From 1bbadfe2bd6968051ef64594f3d49eccce2edb7a Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Wed, 9 Jan 2019 19:56:48 +0530 Subject: [PATCH 0792/1286] ARM: dts: msm: add carveout region for secure dsp on trinket Add carveout region for secure DSP that is used for the secure usecases by DSP clients. Change-Id: Ic70847910c011557cc273da7c93074f95ab1782d Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/trinket.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..a9cb7b355962 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -483,6 +483,12 @@ reg = <0 0x57115000 0 0x2000>; }; + cdsp_sec_mem: cdsp_sec_regions@5f800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x5f800000 0 0x800000>; + }; + qseecom_mem: qseecom_region@5e400000 { compatible = "shared-dma-pool"; no-map; -- GitLab From 458c6956c0b01d4ae2819a03d6486f9f0b0cece2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 4 Jan 2019 00:38:20 +0530 Subject: [PATCH 0793/1286] clk: qcom: gcc: Update the TCXO source map value sm8150 The enable_safe_config flag if used in the RCG assumes the TCXO source map to be '0', which otherwise would cause mapping it to incorrect source during clk_disable. Change-Id: I7007314f5772a028ab9d1acf755c35a3998dbc2e Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-sm8150.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 7e9ba8020fbb..8965589b76c9 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -46,8 +46,8 @@ static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner); enum { - P_AUD_REF_CLK, P_BI_TCXO, + P_AUD_REF_CLK, P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_EVEN, P_GPLL0_OUT_MAIN, -- GitLab From 07091bbfa82f8db070f67e09e1fa511e51f5b578 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Tue, 8 Jan 2019 18:59:02 -0800 Subject: [PATCH 0794/1286] cnss2: Add support for more board data file extensions Currently driver only supports two bytes of board IDs. Add the support to extend it to four bytes so that more board data file choices can be used. Change-Id: I95a26d427d4255820a15e54d8bfd73f1767ff7ef Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/qmi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/cnss2/qmi.c b/drivers/net/wireless/cnss2/qmi.c index fc4f613213d7..f93d59f71882 100644 --- a/drivers/net/wireless/cnss2/qmi.c +++ b/drivers/net/wireless/cnss2/qmi.c @@ -21,7 +21,7 @@ #define WLFW_SERVICE_INS_ID_V01 1 #define WLFW_CLIENT_ID 0x4b4e454c -#define MAX_BDF_FILE_NAME 11 +#define MAX_BDF_FILE_NAME 13 #define ELF_BDF_FILE_NAME "bdwlan.elf" #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e" #define BIN_BDF_FILE_NAME "bdwlan.bin" @@ -433,18 +433,26 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) case CNSS_BDF_ELF: if (plat_priv->board_info.board_id == 0xFF) snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME); - else + else if (plat_priv->board_info.board_id < 0xFF) snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME_PREFIX "%02x", plat_priv->board_info.board_id); + else + snprintf(filename, sizeof(filename), + ELF_BDF_FILE_NAME_PREFIX "%04x", + plat_priv->board_info.board_id); break; case CNSS_BDF_BIN: if (plat_priv->board_info.board_id == 0xFF) snprintf(filename, sizeof(filename), BIN_BDF_FILE_NAME); - else + else if (plat_priv->board_info.board_id < 0xFF) snprintf(filename, sizeof(filename), BIN_BDF_FILE_NAME_PREFIX "%02x", plat_priv->board_info.board_id); + else + snprintf(filename, sizeof(filename), + BIN_BDF_FILE_NAME_PREFIX "%04x", + plat_priv->board_info.board_id); break; case CNSS_BDF_DUMMY: cnss_pr_dbg("CNSS_BDF_DUMMY is set, sending dummy BDF\n"); -- GitLab From e6fdd5e99dd514741ef189b16d6abfb7d0545a71 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 8 Jan 2019 12:00:58 -0800 Subject: [PATCH 0795/1286] ARM: dts: msm: Fix GLINK interrupts for sdxprairie GLINK on mdm targets should use the fourth ipc interrupt instead of the first interrupt. Change glink device tree entry to use SPI interrupt 114 and mailbox bit 15. Change-Id: I986cd2c8f86eb06afd43ff28df634bdc6b5f9472 Signed-off-by: Chris Lew --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index ad18311148b4..beaa988a38c9 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -590,9 +590,9 @@ glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; - mboxes = <&apcs_glb 12>; + mboxes = <&apcs_glb 15>; mbox-names = "mpss_smem"; - interrupts = ; + interrupts = ; label = "modem"; qcom,glink-label = "mpss"; -- GitLab From 5a05d8733e8cc7515127cf84bf69340746256ad0 Mon Sep 17 00:00:00 2001 From: Sudarshan Rajagopalan Date: Fri, 21 Dec 2018 12:24:37 -0800 Subject: [PATCH 0796/1286] ARM: dts: msm: Add ion user contiguous heap for sm8150 Add the memory region reserved for the user contiguous heap allocator. Change-Id: I065d109d8b304562ed5782bc42588fc6ef3aa430 Signed-off-by: Sudarshan Rajagopalan Signed-off-by: Liam Mark --- arch/arm64/boot/dts/qcom/sm8150-ion.dtsi | 8 +++++++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-ion.dtsi b/arch/arm64/boot/dts/qcom/sm8150-ion.dtsi index 3ae20469f0e9..5fd5253e3907 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-ion.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-ion.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,6 +27,12 @@ qcom,ion-heap-type = "DMA"; }; + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = <26>; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + qcom,ion-heap@27 { /* QSEECOM HEAP */ reg = <27>; memory-region = <&qseecom_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b7bdd1f560aa..a6ef88ff11f4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -727,6 +727,14 @@ size = <0x0 0x400000>; }; + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; -- GitLab From d7f709e15f12ea5b34a7d55fa0dd9f8ad2c86ef0 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Thu, 6 Dec 2018 14:33:32 -0800 Subject: [PATCH 0797/1286] dt-bindings: mhi: update devicetree doc for new transfer type support MHI host now accept pre-mapped buffers from client for transfer, updating devicetree documentation to reflect new support. CRs-Fixed: 2361266 Change-Id: I4ea7cbda6ebcb6bf73d4f6f758267c5b62c6cfb4 Signed-off-by: Sujeev Dias --- Documentation/devicetree/bindings/bus/mhi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/mhi.txt b/Documentation/devicetree/bindings/bus/mhi.txt index e4a18d536f0f..dfbd8468cae4 100644 --- a/Documentation/devicetree/bindings/bus/mhi.txt +++ b/Documentation/devicetree/bindings/bus/mhi.txt @@ -97,6 +97,8 @@ mhi channel node properties: 1 = accept skb 2 = accept scatterlist 3 = offload channel, does not accept any transfer type + 4 = accept pre-mapped buffers + 5 = rsc channel type, accept pre-mapped buffers - mhi,doorbell-mode Usage: required -- GitLab From 43f1b0a243e566678f156e46227d32c929ce2ca2 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Sat, 8 Dec 2018 13:05:19 -0800 Subject: [PATCH 0798/1286] mhi: dev: netdev: add support for recycle buffers Memory allocation and memory mapping is relatively expensive operations to do during high throughput data transfer. To avoid mips consumption, add support for recycling buffers for IP traffic. CRs-Fixed: 2361266 Change-Id: If4068969e6b722d298364ac15b177012461e0e1b Signed-off-by: Sujeev Dias --- drivers/bus/mhi/devices/mhi_netdev.c | 400 ++++++++++++++++++++------- 1 file changed, 307 insertions(+), 93 deletions(-) diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 9fdef4263743..35d608f42d0d 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,6 +28,7 @@ #define MHI_NETDEV_DRIVER_NAME "mhi_netdev" #define WATCHDOG_TIMEOUT (30 * HZ) #define IPC_LOG_PAGES (100) +#define MAX_NETBUF_SIZE (128) #ifdef CONFIG_MHI_DEBUG @@ -86,10 +87,15 @@ struct mhi_netdev { int wake; u32 mru; + u32 order; const char *interface_name; struct napi_struct napi; struct net_device *ndev; + struct mhi_netbuf **netbuf_pool; + int pool_size; /* must be power of 2 */ + int current_index; + struct dentry *dentry; enum MHI_DEBUG_LEVEL msg_lvl; enum MHI_DEBUG_LEVEL ipc_log_lvl; @@ -100,15 +106,25 @@ struct mhi_netdev_priv { struct mhi_netdev *mhi_netdev; }; +/* Try not to make this structure bigger than 128 bytes, since this take space + * in payload packet. + * Example: If MRU = 16K, effective MRU = 16K - sizeof(mhi_netbuf) + */ +struct mhi_netbuf { + struct mhi_buf mhi_buf; /* this must be first element */ + void (*unmap)(struct device *dev, dma_addr_t addr, size_t size, + enum dma_data_direction dir); +}; + static struct mhi_driver mhi_netdev_driver; static void mhi_netdev_create_debugfs(struct mhi_netdev *mhi_netdev); -static __be16 mhi_netdev_ip_type_trans(struct sk_buff *skb) +static __be16 mhi_netdev_ip_type_trans(u8 data) { __be16 protocol = 0; /* determine L3 protocol */ - switch (skb->data[0] & 0xf0) { + switch (data & 0xf0) { case 0x40: protocol = htons(ETH_P_IP); break; @@ -123,39 +139,200 @@ static __be16 mhi_netdev_ip_type_trans(struct sk_buff *skb) return protocol; } -static int mhi_netdev_alloc_skb(struct mhi_netdev *mhi_netdev, gfp_t gfp_t) +static struct mhi_netbuf *mhi_netdev_alloc(struct device *dev, + gfp_t gfp, + unsigned int order) { - u32 cur_mru = mhi_netdev->mru; - struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; - int ret; - struct sk_buff *skb; - int no_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - int i; + struct page *page; + struct mhi_netbuf *netbuf; + struct mhi_buf *mhi_buf; + void *vaddr; + + page = __dev_alloc_pages(gfp, order); + if (!page) + return NULL; + + vaddr = page_address(page); + + /* we going to use the end of page to store cached data */ + netbuf = vaddr + (PAGE_SIZE << order) - sizeof(*netbuf); + + mhi_buf = (struct mhi_buf *)netbuf; + mhi_buf->page = page; + mhi_buf->buf = vaddr; + mhi_buf->len = (void *)netbuf - vaddr; + mhi_buf->dma_addr = dma_map_page(dev, page, 0, mhi_buf->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(dev, mhi_buf->dma_addr)) { + __free_pages(mhi_buf->page, order); + return NULL; + } + + return netbuf; +} - for (i = 0; i < no_tre; i++) { - skb = alloc_skb(cur_mru, gfp_t); - if (!skb) +static void mhi_netdev_unmap_page(struct device *dev, + dma_addr_t dma_addr, + size_t len, + enum dma_data_direction dir) +{ + dma_unmap_page(dev, dma_addr, len, dir); +} + +static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, int nr_tre) +{ + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; + struct device *dev = mhi_dev->dev.parent; + const u32 order = mhi_netdev->order; + int i, ret; + + for (i = 0; i < nr_tre; i++) { + struct mhi_buf *mhi_buf; + struct mhi_netbuf *netbuf = mhi_netdev_alloc(dev, GFP_ATOMIC, + order); + if (!netbuf) return -ENOMEM; - skb->dev = mhi_netdev->ndev; + mhi_buf = (struct mhi_buf *)netbuf; + netbuf->unmap = mhi_netdev_unmap_page; + + ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, + mhi_buf->len, MHI_EOT); + if (unlikely(ret)) { + MSG_ERR("Failed to queue transfer, ret:%d\n", ret); + mhi_netdev_unmap_page(dev, mhi_buf->dma_addr, + mhi_buf->len, DMA_FROM_DEVICE); + __free_pages(mhi_buf->page, order); + return ret; + } + } + + return 0; +} - ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, skb, cur_mru, - MHI_EOT); +static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev) +{ + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; + struct device *dev = mhi_dev->dev.parent; + struct mhi_netbuf *netbuf; + struct mhi_buf *mhi_buf; + struct mhi_netbuf **netbuf_pool = mhi_netdev->netbuf_pool; + int nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); + int i, peak, cur_index, ret; + const int pool_size = mhi_netdev->pool_size - 1, max_peak = 4; - if (ret) { - MSG_ERR("Failed to queue skb, ret:%d\n", ret); - ret = -EIO; - goto error_queue; + MSG_VERB("Enter free_desc:%d\n", nr_tre); + + if (!nr_tre) + return; + + /* try going thru reclaim pool first */ + for (i = 0; i < nr_tre; i++) { + /* peak for the next buffer, we going to peak several times, + * and we going to give up if buffers are not yet free + */ + cur_index = mhi_netdev->current_index; + netbuf = NULL; + for (peak = 0; peak < max_peak; peak++) { + struct mhi_netbuf *tmp = netbuf_pool[cur_index]; + + mhi_buf = &tmp->mhi_buf; + + cur_index = (cur_index + 1) & pool_size; + + /* page == 1 idle, buffer is free to reclaim */ + if (page_ref_count(mhi_buf->page) == 1) { + netbuf = tmp; + break; + } } + /* could not find a free buffer */ + if (!netbuf) + break; + + /* increment reference count so when network stack is done + * with buffer, the buffer won't be freed + */ + page_ref_inc(mhi_buf->page); + dma_sync_single_for_device(dev, mhi_buf->dma_addr, mhi_buf->len, + DMA_FROM_DEVICE); + ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, + mhi_buf->len, MHI_EOT); + if (unlikely(ret)) { + MSG_ERR("Failed to queue buffer, ret:%d\n", ret); + netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, + DMA_FROM_DEVICE); + page_ref_dec(mhi_buf->page); + return; + } + mhi_netdev->current_index = cur_index; } + /* recyling did not work, buffers are still busy allocate temp pkts */ + if (i < nr_tre) + mhi_netdev_tmp_alloc(mhi_netdev, nr_tre - i); +} + +/* allocating pool of memory */ +static int mhi_netdev_alloc_pool(struct mhi_netdev *mhi_netdev) +{ + int i; + struct mhi_netbuf *netbuf, **netbuf_pool; + struct mhi_buf *mhi_buf; + const u32 order = mhi_netdev->order; + struct device *dev = mhi_netdev->mhi_dev->dev.parent; + + netbuf_pool = kmalloc_array(mhi_netdev->pool_size, sizeof(*netbuf_pool), + GFP_KERNEL); + if (!netbuf_pool) + return -ENOMEM; + + for (i = 0; i < mhi_netdev->pool_size; i++) { + /* allocate paged data */ + netbuf = mhi_netdev_alloc(dev, GFP_KERNEL, order); + if (!netbuf) + goto error_alloc_page; + + netbuf->unmap = dma_sync_single_for_cpu; + netbuf_pool[i] = netbuf; + } + + mhi_netdev->netbuf_pool = netbuf_pool; + return 0; -error_queue: - dev_kfree_skb_any(skb); +error_alloc_page: + for (--i; i >= 0; i--) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; + dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, + DMA_FROM_DEVICE); + __free_pages(mhi_buf->page, order); + } - return ret; + kfree(netbuf_pool); + + return -ENOMEM; +} + +static void mhi_netdev_free_pool(struct mhi_netdev *mhi_netdev) +{ + int i; + struct mhi_netbuf *netbuf, **netbuf_pool = mhi_netdev->netbuf_pool; + struct device *dev = mhi_netdev->mhi_dev->dev.parent; + struct mhi_buf *mhi_buf; + + for (i = 0; i < mhi_netdev->pool_size; i++) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; + dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, + DMA_FROM_DEVICE); + __free_pages(mhi_buf->page, mhi_netdev->order); + } + + kfree(mhi_netdev->netbuf_pool); + mhi_netdev->netbuf_pool = NULL; } static int mhi_netdev_poll(struct napi_struct *napi, int budget) @@ -177,7 +354,7 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) } /* queue new buffers */ - mhi_netdev_alloc_skb(mhi_netdev, GFP_ATOMIC); + mhi_netdev_queue(mhi_netdev); /* complete work if # of packet processed less than allocated budget */ if (rx_work < budget) @@ -362,58 +539,47 @@ static int mhi_netdev_enable_iface(struct mhi_netdev *mhi_netdev) char ifalias[IFALIASZ]; char ifname[IFNAMSIZ]; struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; - int no_tre; - - MSG_LOG("Prepare the channels for transfer\n"); + struct device_node *of_node = mhi_dev->dev.of_node; + struct mhi_netdev_priv *mhi_netdev_priv; - ret = mhi_prepare_for_transfer(mhi_dev); - if (ret) { - MSG_ERR("Failed to start TX chan ret %d\n", ret); - goto mhi_failed_to_start; - } + mhi_netdev->alias = of_alias_get_id(of_node, "mhi_netdev"); + if (mhi_netdev->alias < 0) + return -ENODEV; - /* first time enabling the node */ - if (!mhi_netdev->ndev) { - struct mhi_netdev_priv *mhi_netdev_priv; + ret = of_property_read_string(of_node, "mhi,interface-name", + &mhi_netdev->interface_name); + if (ret) + mhi_netdev->interface_name = mhi_netdev_driver.driver.name; - snprintf(ifalias, sizeof(ifalias), "%s_%04x_%02u.%02u.%02u_%u", - mhi_netdev->interface_name, mhi_dev->dev_id, - mhi_dev->domain, mhi_dev->bus, mhi_dev->slot, - mhi_netdev->alias); + snprintf(ifalias, sizeof(ifalias), "%s_%04x_%02u.%02u.%02u_%u", + mhi_netdev->interface_name, mhi_dev->dev_id, mhi_dev->domain, + mhi_dev->bus, mhi_dev->slot, mhi_netdev->alias); - snprintf(ifname, sizeof(ifname), "%s%%d", - mhi_netdev->interface_name); + snprintf(ifname, sizeof(ifname), "%s%%d", mhi_netdev->interface_name); - rtnl_lock(); - mhi_netdev->ndev = alloc_netdev(sizeof(*mhi_netdev_priv), + rtnl_lock(); + mhi_netdev->ndev = alloc_netdev(sizeof(*mhi_netdev_priv), ifname, NET_NAME_PREDICTABLE, mhi_netdev_setup); - - if (!mhi_netdev->ndev) { - ret = -ENOMEM; - rtnl_unlock(); - goto net_dev_alloc_fail; - } - - mhi_netdev->ndev->mtu = mhi_dev->mtu; - SET_NETDEV_DEV(mhi_netdev->ndev, &mhi_dev->dev); - dev_set_alias(mhi_netdev->ndev, ifalias, strlen(ifalias)); - mhi_netdev_priv = netdev_priv(mhi_netdev->ndev); - mhi_netdev_priv->mhi_netdev = mhi_netdev; + if (!mhi_netdev->ndev) { rtnl_unlock(); - - netif_napi_add(mhi_netdev->ndev, &mhi_netdev->napi, - mhi_netdev_poll, NAPI_POLL_WEIGHT); - ret = register_netdev(mhi_netdev->ndev); - if (ret) { - MSG_ERR("Network device registration failed\n"); - goto net_dev_reg_fail; - } + return -ENOMEM; } - /* queue buffer for rx path */ - no_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - mhi_netdev_alloc_skb(mhi_netdev, GFP_KERNEL); + mhi_netdev->ndev->mtu = mhi_dev->mtu; + SET_NETDEV_DEV(mhi_netdev->ndev, &mhi_dev->dev); + dev_set_alias(mhi_netdev->ndev, ifalias, strlen(ifalias)); + mhi_netdev_priv = netdev_priv(mhi_netdev->ndev); + mhi_netdev_priv->mhi_netdev = mhi_netdev; + rtnl_unlock(); + + netif_napi_add(mhi_netdev->ndev, &mhi_netdev->napi, + mhi_netdev_poll, NAPI_POLL_WEIGHT); + ret = register_netdev(mhi_netdev->ndev); + if (ret) { + MSG_ERR("Network device registration failed\n"); + goto net_dev_reg_fail; + } napi_enable(&mhi_netdev->napi); @@ -426,12 +592,6 @@ static int mhi_netdev_enable_iface(struct mhi_netdev *mhi_netdev) free_netdev(mhi_netdev->ndev); mhi_netdev->ndev = NULL; -net_dev_alloc_fail: - mhi_unprepare_from_transfer(mhi_dev); - -mhi_failed_to_start: - MSG_ERR("Exited ret %d.\n", ret); - return ret; } @@ -450,23 +610,46 @@ static void mhi_netdev_xfer_ul_cb(struct mhi_device *mhi_dev, netif_wake_queue(ndev); } +static void mhi_netdev_push_skb(struct mhi_netdev *mhi_netdev, + struct mhi_buf *mhi_buf, + struct mhi_result *mhi_result) +{ + struct sk_buff *skb; + + skb = alloc_skb(0, GFP_ATOMIC); + if (!skb) { + __free_pages(mhi_buf->page, mhi_netdev->order); + return; + } + + skb_add_rx_frag(skb, 0, mhi_buf->page, 0, + mhi_result->bytes_xferd, mhi_netdev->mru); + skb->dev = mhi_netdev->ndev; + skb->protocol = mhi_netdev_ip_type_trans(*(u8 *)mhi_buf->buf); + netif_receive_skb(skb); +} + static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result) { struct mhi_netdev *mhi_netdev = mhi_device_get_devdata(mhi_dev); - struct sk_buff *skb = mhi_result->buf_addr; - struct net_device *dev = mhi_netdev->ndev; + struct mhi_netbuf *netbuf = mhi_result->buf_addr; + struct mhi_buf *mhi_buf = &netbuf->mhi_buf; + struct net_device *ndev = mhi_netdev->ndev; + struct device *dev = mhi_dev->dev.parent; + + netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); + /* modem is down, drop the buffer */ if (mhi_result->transaction_status == -ENOTCONN) { - dev_kfree_skb(skb); + __free_pages(mhi_buf->page, mhi_netdev->order); return; } - skb_put(skb, mhi_result->bytes_xferd); - dev->stats.rx_packets++; - dev->stats.rx_bytes += mhi_result->bytes_xferd; - skb->protocol = mhi_netdev_ip_type_trans(skb); - netif_receive_skb(skb); + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += mhi_result->bytes_xferd; + + mhi_netdev_push_skb(mhi_netdev, mhi_buf, mhi_result); } static void mhi_netdev_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) @@ -533,6 +716,7 @@ static void mhi_netdev_remove(struct mhi_device *mhi_dev) unregister_netdev(mhi_netdev->ndev); netif_napi_del(&mhi_netdev->napi); free_netdev(mhi_netdev->ndev); + mhi_netdev_free_pool(mhi_netdev); if (!IS_ERR_OR_NULL(mhi_netdev->dentry)) debugfs_remove_recursive(mhi_netdev->dentry); @@ -544,6 +728,7 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, int ret; struct mhi_netdev *mhi_netdev; struct device_node *of_node = mhi_dev->dev.of_node; + int nr_tre; char node_name[32]; if (!of_node) @@ -554,10 +739,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (!mhi_netdev) return -ENOMEM; - mhi_netdev->alias = of_alias_get_id(of_node, "mhi_netdev"); - if (mhi_netdev->alias < 0) - return -ENODEV; - mhi_netdev->mhi_dev = mhi_dev; mhi_device_set_devdata(mhi_dev, mhi_netdev); @@ -565,28 +746,60 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (ret) return -ENODEV; - ret = of_property_read_string(of_node, "mhi,interface-name", - &mhi_netdev->interface_name); + /* MRU must be multiplication of page size */ + mhi_netdev->order = __ilog2_u32(mhi_netdev->mru / PAGE_SIZE); + if ((PAGE_SIZE << mhi_netdev->order) < mhi_netdev->mru) + return -EINVAL; + + ret = mhi_netdev_enable_iface(mhi_netdev); if (ret) - mhi_netdev->interface_name = mhi_netdev_driver.driver.name; + return ret; /* create ipc log buffer */ snprintf(node_name, sizeof(node_name), "%s_%04x_%02u.%02u.%02u_%u", mhi_netdev->interface_name, mhi_dev->dev_id, mhi_dev->domain, mhi_dev->bus, mhi_dev->slot, mhi_netdev->alias); - mhi_netdev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, node_name, - 0); + mhi_netdev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, + node_name, 0); mhi_netdev->msg_lvl = MHI_MSG_LVL_ERROR; mhi_netdev->ipc_log_lvl = IPC_LOG_LVL; - /* setup network interface */ - ret = mhi_netdev_enable_iface(mhi_netdev); + mhi_netdev_create_debugfs(mhi_netdev); + + /* move mhi channels to start state */ + ret = mhi_prepare_for_transfer(mhi_dev); + if (ret) { + MSG_ERR("Failed to start channels ret %d\n", ret); + goto error_start; + } + + /* setup pool size ~2x ring length*/ + nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); + mhi_netdev->pool_size = 1 << __ilog2_u32(nr_tre); + if (nr_tre > mhi_netdev->pool_size) + mhi_netdev->pool_size <<= 1; + mhi_netdev->pool_size <<= 1; + + /* allocate memory pool */ + ret = mhi_netdev_alloc_pool(mhi_netdev); if (ret) - return ret; + goto error_start; - mhi_netdev_create_debugfs(mhi_netdev); + /* now we have a pool of buffers allocated, queue to hardware + * by triggering a napi_poll + */ + napi_schedule(&mhi_netdev->napi); return 0; + +error_start: + netif_stop_queue(mhi_netdev->ndev); + napi_disable(&mhi_netdev->napi); + unregister_netdev(mhi_netdev->ndev); + netif_napi_del(&mhi_netdev->napi); + free_netdev(mhi_netdev->ndev); + + return ret; } static const struct mhi_device_id mhi_netdev_match_table[] = { @@ -610,6 +823,7 @@ static struct mhi_driver mhi_netdev_driver = { static int __init mhi_netdev_init(void) { + BUILD_BUG_ON(sizeof(struct mhi_netbuf) > MAX_NETBUF_SIZE); mhi_netdev_create_debugfs_dir(); return mhi_driver_register(&mhi_netdev_driver); -- GitLab From fa5b5e56cb9675c6e79c032f3686ae8ca71eea91 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Sat, 8 Dec 2018 13:34:04 -0800 Subject: [PATCH 0799/1286] mhi: dev: netdev: add support for chain skb to reduce cpu mips consumption Instead of pushing individual IP packets into a network stack during napi poll, chain all the skbs into a single skb list and do a single push to network stack. CRs-Fixed: 2361266 Change-Id: I620408994295d66635038bd9390988a76783cfb8 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/devices/mhi_netdev.c | 51 +++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 35d608f42d0d..82d91be62518 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -81,6 +81,10 @@ __func__, ##__VA_ARGS__); \ } while (0) +struct mhi_net_chain { + struct sk_buff *head, *tail; /* chained skb */ +}; + struct mhi_netdev { int alias; struct mhi_device *mhi_dev; @@ -95,6 +99,8 @@ struct mhi_netdev { struct mhi_netbuf **netbuf_pool; int pool_size; /* must be power of 2 */ int current_index; + bool chain_skb; + struct mhi_net_chain *chain; struct dentry *dentry; enum MHI_DEBUG_LEVEL msg_lvl; @@ -341,11 +347,19 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) struct mhi_netdev_priv *mhi_netdev_priv = netdev_priv(dev); struct mhi_netdev *mhi_netdev = mhi_netdev_priv->mhi_netdev; struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; + struct mhi_net_chain *chain = mhi_netdev->chain; int rx_work = 0; MSG_VERB("Entered\n"); rx_work = mhi_poll(mhi_dev, budget); + + /* chained skb, push it to stack */ + if (chain && chain->head) { + netif_receive_skb(chain->head); + chain->head = NULL; + } + if (rx_work < 0) { MSG_ERR("Error polling ret:%d\n", rx_work); rx_work = 0; @@ -635,8 +649,10 @@ static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev, struct mhi_netdev *mhi_netdev = mhi_device_get_devdata(mhi_dev); struct mhi_netbuf *netbuf = mhi_result->buf_addr; struct mhi_buf *mhi_buf = &netbuf->mhi_buf; + struct sk_buff *skb; struct net_device *ndev = mhi_netdev->ndev; struct device *dev = mhi_dev->dev.parent; + struct mhi_net_chain *chain = mhi_netdev->chain; netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); @@ -649,7 +665,30 @@ static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev, ndev->stats.rx_packets++; ndev->stats.rx_bytes += mhi_result->bytes_xferd; - mhi_netdev_push_skb(mhi_netdev, mhi_buf, mhi_result); + if (unlikely(!chain)) { + mhi_netdev_push_skb(mhi_netdev, mhi_buf, mhi_result); + return; + } + + /* we support chaining */ + skb = alloc_skb(0, GFP_ATOMIC); + if (likely(skb)) { + skb_add_rx_frag(skb, 0, mhi_buf->page, 0, + mhi_result->bytes_xferd, mhi_netdev->mru); + /* this is first on list */ + if (!chain->head) { + skb->dev = ndev; + skb->protocol = + mhi_netdev_ip_type_trans(*(u8 *)mhi_buf->buf); + chain->head = skb; + } else { + skb_shinfo(chain->tail)->frag_list = skb; + } + + chain->tail = skb; + } else { + __free_pages(mhi_buf->page, mhi_netdev->order); + } } static void mhi_netdev_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) @@ -730,6 +769,7 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, struct device_node *of_node = mhi_dev->dev.of_node; int nr_tre; char node_name[32]; + bool no_chain; if (!of_node) return -ENODEV; @@ -751,6 +791,15 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if ((PAGE_SIZE << mhi_netdev->order) < mhi_netdev->mru) return -EINVAL; + no_chain = of_property_read_bool(of_node, "mhi,disable-chain-skb"); + if (!no_chain) { + mhi_netdev->chain = devm_kzalloc(&mhi_dev->dev, + sizeof(*mhi_netdev->chain), + GFP_KERNEL); + if (!mhi_netdev->chain) + return -ENOMEM; + } + ret = mhi_netdev_enable_iface(mhi_netdev); if (ret) return ret; -- GitLab From fa6a5e3e81d2207aa3225e7bee6a09e6b957d1bf Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Thu, 3 Jan 2019 20:36:35 -0800 Subject: [PATCH 0800/1286] mhi: dev: netdev: since there is no clean up, return immediately If mhi_poll fails, return immediately instead of branching to a goto statement since no clean up required. CRs-Fixed: 2361266 Change-Id: I7d3349a4678fd87c2b73dd83c7dfcba0b7d30e0f Signed-off-by: Sujeev Dias --- drivers/bus/mhi/devices/mhi_netdev.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 82d91be62518..95809ccef1d2 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -362,9 +362,8 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) if (rx_work < 0) { MSG_ERR("Error polling ret:%d\n", rx_work); - rx_work = 0; napi_complete(napi); - goto exit_poll; + return 0; } /* queue new buffers */ @@ -374,8 +373,6 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) if (rx_work < budget) napi_complete(napi); -exit_poll: - MSG_VERB("polled %d pkts\n", rx_work); return rx_work; -- GitLab From fecad3f4be35a58b01f22bff74afafa092c305fd Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Sat, 8 Dec 2018 14:06:20 -0800 Subject: [PATCH 0801/1286] mhi: dev: net_dev: add support for reserve side coalesced (rsc) channel RSC channel allows hardware to combine multiple small IP packets into a single jumbo IP packet before transferring to host. Also, RSC operate in parallel with legacy IP_HW0 channels. This change add support for RSC by linking rsc device into IP_HW0 device. CRs-Fixed: 2361266 Change-Id: I20c74acb203527a9e71a2654784ccd2803ebfb32 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/devices/mhi_netdev.c | 140 ++++++++++++++++++++------- 1 file changed, 104 insertions(+), 36 deletions(-) diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 95809ccef1d2..12932c0afed4 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -88,12 +88,14 @@ struct mhi_net_chain { struct mhi_netdev { int alias; struct mhi_device *mhi_dev; + struct mhi_netdev *rsc_dev; /* rsc linked node */ + bool is_rsc_dev; int wake; u32 mru; u32 order; const char *interface_name; - struct napi_struct napi; + struct napi_struct *napi; struct net_device *ndev; struct mhi_netbuf **netbuf_pool; @@ -347,6 +349,7 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) struct mhi_netdev_priv *mhi_netdev_priv = netdev_priv(dev); struct mhi_netdev *mhi_netdev = mhi_netdev_priv->mhi_netdev; struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; + struct mhi_netdev *rsc_dev = mhi_netdev->rsc_dev; struct mhi_net_chain *chain = mhi_netdev->chain; int rx_work = 0; @@ -369,6 +372,9 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) /* queue new buffers */ mhi_netdev_queue(mhi_netdev); + if (rsc_dev) + mhi_netdev_queue(rsc_dev); + /* complete work if # of packet processed less than allocated budget */ if (rx_work < budget) napi_complete(napi); @@ -584,7 +590,14 @@ static int mhi_netdev_enable_iface(struct mhi_netdev *mhi_netdev) mhi_netdev_priv->mhi_netdev = mhi_netdev; rtnl_unlock(); - netif_napi_add(mhi_netdev->ndev, &mhi_netdev->napi, + mhi_netdev->napi = devm_kzalloc(&mhi_dev->dev, + sizeof(*mhi_netdev->napi), GFP_KERNEL); + if (!mhi_netdev->napi) { + ret = -ENOMEM; + goto napi_alloc_fail; + } + + netif_napi_add(mhi_netdev->ndev, mhi_netdev->napi, mhi_netdev_poll, NAPI_POLL_WEIGHT); ret = register_netdev(mhi_netdev->ndev); if (ret) { @@ -592,14 +605,16 @@ static int mhi_netdev_enable_iface(struct mhi_netdev *mhi_netdev) goto net_dev_reg_fail; } - napi_enable(&mhi_netdev->napi); + napi_enable(mhi_netdev->napi); MSG_LOG("Exited.\n"); return 0; net_dev_reg_fail: - netif_napi_del(&mhi_netdev->napi); + netif_napi_del(mhi_netdev->napi); + +napi_alloc_fail: free_netdev(mhi_netdev->ndev); mhi_netdev->ndev = NULL; @@ -695,11 +710,7 @@ static void mhi_netdev_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) if (mhi_cb != MHI_CB_PENDING_DATA) return; - if (napi_schedule_prep(&mhi_netdev->napi)) { - __napi_schedule(&mhi_netdev->napi); - return; - } - + napi_schedule(mhi_netdev->napi); } #ifdef CONFIG_DEBUG_FS @@ -747,10 +758,16 @@ static void mhi_netdev_remove(struct mhi_device *mhi_dev) MSG_LOG("Remove notification received\n"); + /* rsc parent takes cares of the cleanup */ + if (mhi_netdev->is_rsc_dev) { + mhi_netdev_free_pool(mhi_netdev); + return; + } + netif_stop_queue(mhi_netdev->ndev); - napi_disable(&mhi_netdev->napi); + napi_disable(mhi_netdev->napi); unregister_netdev(mhi_netdev->ndev); - netif_napi_del(&mhi_netdev->napi); + netif_napi_del(mhi_netdev->napi); free_netdev(mhi_netdev->ndev); mhi_netdev_free_pool(mhi_netdev); @@ -758,14 +775,33 @@ static void mhi_netdev_remove(struct mhi_device *mhi_dev) debugfs_remove_recursive(mhi_netdev->dentry); } +static int mhi_netdev_match(struct device *dev, void *data) +{ + /* if phandle dt == device dt, we found a match */ + return (dev->of_node == data); +} + +static void mhi_netdev_clone_dev(struct mhi_netdev *mhi_netdev, + struct mhi_netdev *parent) +{ + mhi_netdev->ndev = parent->ndev; + mhi_netdev->napi = parent->napi; + mhi_netdev->ipc_log = parent->ipc_log; + mhi_netdev->msg_lvl = parent->msg_lvl; + mhi_netdev->ipc_log_lvl = parent->ipc_log_lvl; + mhi_netdev->is_rsc_dev = true; + mhi_netdev->chain = parent->chain; +} + static int mhi_netdev_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id) { int ret; - struct mhi_netdev *mhi_netdev; + struct mhi_netdev *mhi_netdev, *p_netdev = NULL; struct device_node *of_node = mhi_dev->dev.of_node; int nr_tre; char node_name[32]; + struct device_node *phandle; bool no_chain; if (!of_node) @@ -788,29 +824,53 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if ((PAGE_SIZE << mhi_netdev->order) < mhi_netdev->mru) return -EINVAL; - no_chain = of_property_read_bool(of_node, "mhi,disable-chain-skb"); - if (!no_chain) { - mhi_netdev->chain = devm_kzalloc(&mhi_dev->dev, - sizeof(*mhi_netdev->chain), - GFP_KERNEL); - if (!mhi_netdev->chain) - return -ENOMEM; - } - - ret = mhi_netdev_enable_iface(mhi_netdev); - if (ret) - return ret; + /* check if this device shared by a parent device */ + phandle = of_parse_phandle(of_node, "mhi,rsc-parent", 0); + if (phandle) { + struct device *dev; + struct mhi_device *pdev; + /* find the parent device */ + dev = driver_find_device(mhi_dev->dev.driver, NULL, phandle, + mhi_netdev_match); + if (!dev) + return -ENODEV; + + /* this device is shared with parent device. so we won't be + * creating a new network interface. Clone parent + * information to child node + */ + pdev = to_mhi_device(dev); + p_netdev = mhi_device_get_devdata(pdev); + mhi_netdev_clone_dev(mhi_netdev, p_netdev); + put_device(dev); + } else { + mhi_netdev->msg_lvl = MHI_MSG_LVL_ERROR; + no_chain = of_property_read_bool(of_node, + "mhi,disable-chain-skb"); + if (!no_chain) { + mhi_netdev->chain = devm_kzalloc(&mhi_dev->dev, + sizeof(*mhi_netdev->chain), + GFP_KERNEL); + if (!mhi_netdev->chain) + return -ENOMEM; + } - /* create ipc log buffer */ - snprintf(node_name, sizeof(node_name), "%s_%04x_%02u.%02u.%02u_%u", - mhi_netdev->interface_name, mhi_dev->dev_id, mhi_dev->domain, - mhi_dev->bus, mhi_dev->slot, mhi_netdev->alias); - mhi_netdev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, - node_name, 0); - mhi_netdev->msg_lvl = MHI_MSG_LVL_ERROR; - mhi_netdev->ipc_log_lvl = IPC_LOG_LVL; + ret = mhi_netdev_enable_iface(mhi_netdev); + if (ret) + return ret; - mhi_netdev_create_debugfs(mhi_netdev); + /* create ipc log buffer */ + snprintf(node_name, sizeof(node_name), + "%s_%04x_%02u.%02u.%02u_%u", + mhi_netdev->interface_name, mhi_dev->dev_id, + mhi_dev->domain, mhi_dev->bus, mhi_dev->slot, + mhi_netdev->alias); + mhi_netdev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, + node_name, 0); + mhi_netdev->ipc_log_lvl = IPC_LOG_LVL; + + mhi_netdev_create_debugfs(mhi_netdev); + } /* move mhi channels to start state */ ret = mhi_prepare_for_transfer(mhi_dev); @@ -831,18 +891,25 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (ret) goto error_start; + /* link child node with parent node if it's children dev */ + if (p_netdev) + p_netdev->rsc_dev = mhi_netdev; + /* now we have a pool of buffers allocated, queue to hardware * by triggering a napi_poll */ - napi_schedule(&mhi_netdev->napi); + napi_schedule(mhi_netdev->napi); return 0; error_start: + if (phandle) + return ret; + netif_stop_queue(mhi_netdev->ndev); - napi_disable(&mhi_netdev->napi); + napi_disable(mhi_netdev->napi); unregister_netdev(mhi_netdev->ndev); - netif_napi_del(&mhi_netdev->napi); + netif_napi_del(mhi_netdev->napi); free_netdev(mhi_netdev->ndev); return ret; @@ -851,6 +918,7 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, static const struct mhi_device_id mhi_netdev_match_table[] = { { .chan = "IP_HW0" }, { .chan = "IP_HW_ADPL" }, + { .chan = "IP_HW0_RSC" }, {}, }; -- GitLab From a601657697a160ddeea1e9d7f2441cb8fd09458b Mon Sep 17 00:00:00 2001 From: Can Guo Date: Mon, 7 Jan 2019 11:05:46 +0800 Subject: [PATCH 0802/1286] scsi: ufs: add delay after reference clock ungating This change adds a device quirk for some UFS devices which need long delay after device reference clock is turned on but before initiation of the state transition to STALL from a LS-MODE or from the HIBERN8 state. Change-Id: I587dba737633034cca93b8ba839ab367dbc326e1 Signed-off-by: Can Guo --- drivers/scsi/ufs/ufs-qcom.c | 13 +++++++++---- drivers/scsi/ufs/ufs_quirks.h | 8 ++++++++ drivers/scsi/ufs/ufshcd.c | 4 +++- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index cb8459a6e6cc..837046fb74a5 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1360,11 +1360,16 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) /* * If we call hibern8 exit after this, we need to make sure that - * device ref_clk is stable for at least 1us before the hibern8 + * device ref_clk is stable for a given time before the hibern8 * exit command. */ - if (enable) - udelay(1); + if (enable) { + if (host->hba->dev_info.quirks & + UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE) + usleep_range(50, 60); + else + udelay(1); + } host->is_dev_ref_clk_enabled = enable; } diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h index db3bff0595a1..acf36c443ea6 100644 --- a/drivers/scsi/ufs/ufs_quirks.h +++ b/drivers/scsi/ufs/ufs_quirks.h @@ -140,4 +140,12 @@ struct ufs_dev_fix { */ #define UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH (1 << 9) +/* + * Some UFS devices need more delay after device reference clk is turned on + * but before initiation of the state transition to STALL from a LS-MODE or + * from the HIBERN8 state. Enable this quirk to give UFS devices 50us delay + * instead of the default delay. + */ +#define UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE (1 << 10) + #endif /* UFS_QUIRKS_H_ */ diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 95ccadb78bd9..fa15ebd825c1 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -3,7 +3,7 @@ * * This code is based on drivers/scsi/ufs/ufshcd.c * Copyright (C) 2011-2013 Samsung India Software Operations - * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * Authors: * Santosh Yaraganavi @@ -419,6 +419,8 @@ static struct ufs_dev_fix ufs_fixups[] = { UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ), UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME), + UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, + UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE), UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1", UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH), UFS_FIX(UFS_VENDOR_SKHYNIX, "hC8aL1", -- GitLab From 38eef0503689d1e657a80a525c2cc80b6950ddda Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Wed, 9 Jan 2019 20:29:04 +0530 Subject: [PATCH 0803/1286] ARM: dts: msm: Add ion heap types of carveout and dma on trinket Add ion heap type support of carveout and DMA that will be used by secure carveout and qseecom_ta applications. Change-Id: I47e23dbed98c21485b931c22bda58b656cb49a12 Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/trinket-ion.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-ion.dtsi b/arch/arm64/boot/dts/qcom/trinket-ion.dtsi index 7c35e6991afe..4adf296afb30 100644 --- a/arch/arm64/boot/dts/qcom/trinket-ion.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-ion.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,9 +27,24 @@ qcom,ion-heap-type = "DMA"; }; + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + qcom,ion-heap@9 { reg = <9>; qcom,ion-heap-type = "SYSTEM_SECURE"; }; + + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = <14>; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_sec_mem>; + token = <0x20000000>; + }; + }; }; }; -- GitLab From 9b4c8567ab1e5be817a3e7011afa75dff6ded848 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Fri, 16 Nov 2018 20:05:29 +0530 Subject: [PATCH 0804/1286] power: smb5: Implement charge termination WA Currently post charge termination, if the charger switches to BSM mode, then there exist a possibility of battery being overcharged. This is due to finite delay in opening of BATFET post its requirement to stay in BSM mode, allowing charge current to leak into the battery, resulting in over charge. Add a SW WA to suspend input, once cc_soc increases beyond a certain threshold post termination. Change-Id: I6c1966bb69445c89bc29b099ab9adf2d5f3e2334 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/qpnp-smb5.c | 6 +- drivers/power/supply/qcom/smb5-lib.c | 165 ++++++++++++++++++++++++++ drivers/power/supply/qcom/smb5-lib.h | 6 + 3 files changed, 175 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index bd89143a3a99..5b70fac1690a 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -285,19 +285,21 @@ static int smb5_chg_config_init(struct smb5 *chip) chip->chg.smb_version = PM8150B_SUBTYPE; chg->param = smb5_pm8150b_params; chg->name = "pm8150b_charger"; + chg->wa_flags |= CHG_TERMINATION_WA; break; case PM6150_SUBTYPE: chip->chg.smb_version = PM6150_SUBTYPE; chg->param = smb5_pm8150b_params; chg->name = "pm6150_charger"; - chg->wa_flags |= SW_THERM_REGULATION_WA; + chg->wa_flags |= SW_THERM_REGULATION_WA | CHG_TERMINATION_WA; if (pmic_rev_id->rev4 >= 2) chg->uusb_moisture_protection_enabled = true; chg->main_fcc_max = PM6150_MAX_FCC_UA; break; case PMI632_SUBTYPE: chip->chg.smb_version = PMI632_SUBTYPE; - chg->wa_flags |= WEAK_ADAPTER_WA | USBIN_OV_WA; + chg->wa_flags |= WEAK_ADAPTER_WA | USBIN_OV_WA + | CHG_TERMINATION_WA; chg->param = smb5_pmi632_params; chg->use_extcon = true; chg->name = "pmi632_charger"; diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index e31f0ababd95..f405eb0a8075 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -1085,6 +1085,7 @@ static void smblib_uusb_removal(struct smb_charger *chg) false); cancel_delayed_work_sync(&chg->pl_enable_work); + alarm_cancel(&chg->chg_termination_alarm); if (chg->wa_flags & BOOST_BACK_WA) { data = chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data; @@ -1106,6 +1107,7 @@ static void smblib_uusb_removal(struct smb_charger *chg) is_flash_active(chg) ? SDP_CURRENT_UA : SDP_100_MA); vote(chg->usb_icl_votable, SW_QC3_VOTER, false, 0); vote(chg->usb_icl_votable, HVDCP2_ICL_VOTER, false, 0); + vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, false, 0); /* Remove SW thermal regulation WA votes */ vote(chg->usb_icl_votable, SW_THERM_REGULATION_VOTER, false, 0); @@ -1839,6 +1841,16 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, return 0; } + /* + * If charge termination WA is active and has suspended charging, then + * continue reporting charging status as FULL. + */ + if (is_client_vote_enabled(chg->usb_icl_votable, + CHG_TERMINATION_VOTER)) { + val->intval = POWER_SUPPLY_STATUS_FULL; + return 0; + } + if (val->intval != POWER_SUPPLY_STATUS_CHARGING) return 0; @@ -2745,6 +2757,12 @@ int smblib_get_prop_dc_online(struct smb_charger *chg, return rc; } + if (is_client_vote_enabled(chg->dc_suspend_votable, + CHG_TERMINATION_VOTER)) { + rc = smblib_get_prop_dc_present(chg, val); + return rc; + } + rc = smblib_read(chg, POWER_PATH_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read POWER_PATH_STATUS rc=%d\n", @@ -2857,6 +2875,12 @@ int smblib_get_prop_usb_online(struct smb_charger *chg, return rc; } + if (is_client_vote_enabled(chg->usb_icl_votable, + CHG_TERMINATION_VOTER)) { + rc = smblib_get_prop_usb_present(chg, val); + return rc; + } + rc = smblib_read(chg, POWER_PATH_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read POWER_PATH_STATUS rc=%d\n", @@ -4133,6 +4157,38 @@ irqreturn_t default_irq_handler(int irq, void *data) return IRQ_HANDLED; } +#define CHG_TERM_WA_ENTRY_DELAY_MS 300000 /* 5 min */ +#define CHG_TERM_WA_EXIT_DELAY_MS 60000 /* 1 min */ +static void smblib_eval_chg_termination(struct smb_charger *chg, u8 batt_status) +{ + union power_supply_propval pval = {0, }; + int rc = 0; + + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CAPACITY, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't read SOC value, rc=%d\n", rc); + return; + } + + /* + * Post charge termination, switch to BSM mode triggers the risk of + * over charging as BATFET opening may take some time post the necessity + * of staying in supplemental mode, leading to unintended charging of + * battery. Trigger the charge termination WA once charging is completed + * to prevent overcharing. + */ + if ((batt_status == TERMINATE_CHARGE) && (pval.intval == 100)) { + alarm_start_relative(&chg->chg_termination_alarm, + ms_to_ktime(CHG_TERM_WA_ENTRY_DELAY_MS)); + } else if (pval.intval < 100) { + /* + * Reset CC_SOC reference value for charge termination WA once + * we exit the TERMINATE_CHARGE state and soc drops below 100% + */ + chg->cc_soc_ref = 0; + } +} + irqreturn_t chg_state_change_irq_handler(int irq, void *data) { struct smb_irq_data *irq_data = data; @@ -4150,6 +4206,10 @@ irqreturn_t chg_state_change_irq_handler(int irq, void *data) } stat = stat & BATTERY_CHARGER_STATUS_MASK; + + if (chg->wa_flags & CHG_TERMINATION_WA) + smblib_eval_chg_termination(chg, stat); + power_supply_changed(chg->batt_psy); return IRQ_HANDLED; } @@ -4943,6 +5003,7 @@ static void typec_src_removal(struct smb_charger *chg) } cancel_delayed_work_sync(&chg->pl_enable_work); + alarm_cancel(&chg->chg_termination_alarm); /* reset input current limit voters */ vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, @@ -4954,6 +5015,7 @@ static void typec_src_removal(struct smb_charger *chg) vote(chg->usb_icl_votable, OTG_VOTER, false, 0); vote(chg->usb_icl_votable, CTM_VOTER, false, 0); vote(chg->usb_icl_votable, HVDCP2_ICL_VOTER, false, 0); + vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, false, 0); /* reset usb irq voters */ vote(chg->usb_irq_enable_votable, PD_VOTER, false, 0); @@ -5776,6 +5838,94 @@ static enum alarmtimer_restart moisture_protection_alarm_cb(struct alarm *alarm, return ALARMTIMER_NORESTART; } +static void smblib_chg_termination_work(struct work_struct *work) +{ + union power_supply_propval pval; + struct smb_charger *chg = container_of(work, struct smb_charger, + chg_termination_work); + int rc, input_present, delay = CHG_TERM_WA_ENTRY_DELAY_MS; + + /* + * Hold awake votable to prevent pm_relax being called prior to + * completion of this work. + */ + vote(chg->awake_votable, CHG_TERMINATION_VOTER, true, 0); + + rc = smblib_is_input_present(chg, &input_present); + if ((rc < 0) || !input_present) + goto out; + + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CAPACITY, &pval); + if ((rc < 0) || (pval.intval < 100)) { + vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, false, 0); + goto out; + } + + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CHARGE_FULL, + &pval); + if (rc < 0) + goto out; + + /* + * On change in the value of learned capacity, re-initialize the + * reference cc_soc value due to change in cc_soc characteristic value + * at full capacity. Also, in case cc_soc_ref value is reset, + * re-initialize it. + */ + if (pval.intval != chg->charge_full_cc || !chg->cc_soc_ref) { + chg->charge_full_cc = pval.intval; + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CC_SOC, + &pval); + if (rc < 0) + goto out; + + chg->cc_soc_ref = pval.intval; + } else { + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CC_SOC, + &pval); + if (rc < 0) + goto out; + } + + /* + * Suspend/Unsuspend USB input to keep cc_soc within the 0.5% to 0.75% + * overshoot range of the cc_soc value at termination, to prevent + * overcharging. + */ + if (pval.intval < DIV_ROUND_CLOSEST(chg->cc_soc_ref * 10050, 10000)) { + vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, false, 0); + vote(chg->dc_suspend_votable, CHG_TERMINATION_VOTER, false, 0); + delay = CHG_TERM_WA_ENTRY_DELAY_MS; + } else if (pval.intval > DIV_ROUND_CLOSEST(chg->cc_soc_ref * 10075, + 10000)) { + vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, true, 0); + vote(chg->dc_suspend_votable, CHG_TERMINATION_VOTER, true, 0); + delay = CHG_TERM_WA_EXIT_DELAY_MS; + } + + smblib_dbg(chg, PR_MISC, "Chg Term WA readings: cc_soc: %d, cc_soc_ref: %d, delay: %d\n", + pval.intval, chg->cc_soc_ref, delay); + alarm_start_relative(&chg->chg_termination_alarm, ms_to_ktime(delay)); +out: + vote(chg->awake_votable, CHG_TERMINATION_VOTER, false, 0); +} + +static enum alarmtimer_restart chg_termination_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct smb_charger *chg = container_of(alarm, struct smb_charger, + chg_termination_alarm); + + smblib_dbg(chg, PR_MISC, "Charge termination WA alarm triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + pm_stay_awake(chg->dev); + schedule_work(&chg->chg_termination_work); + + return ALARMTIMER_NORESTART; +} + static void jeita_update_work(struct work_struct *work) { struct smb_charger *chg = container_of(work, struct smb_charger, @@ -6147,6 +6297,19 @@ int smblib_init(struct smb_charger *chg) smblib_thermal_regulation_work); INIT_DELAYED_WORK(&chg->usbov_dbc_work, smblib_usbov_dbc_work); + if (chg->wa_flags & CHG_TERMINATION_WA) { + INIT_WORK(&chg->chg_termination_work, + smblib_chg_termination_work); + + if (alarmtimer_get_rtcdev()) { + alarm_init(&chg->chg_termination_alarm, ALARM_BOOTTIME, + chg_termination_alarm_cb); + } else { + smblib_err(chg, "Couldn't get rtc device\n"); + return -ENODEV; + } + } + if (chg->uusb_moisture_protection_enabled) { INIT_WORK(&chg->moisture_protection_work, smblib_moisture_protection_work); @@ -6256,9 +6419,11 @@ int smblib_deinit(struct smb_charger *chg) alarm_cancel(&chg->moisture_protection_alarm); cancel_work_sync(&chg->moisture_protection_work); } + alarm_cancel(&chg->chg_termination_alarm); cancel_work_sync(&chg->bms_update_work); cancel_work_sync(&chg->jeita_update_work); cancel_work_sync(&chg->pl_update_work); + cancel_work_sync(&chg->chg_termination_work); cancel_delayed_work_sync(&chg->clear_hdc_work); cancel_delayed_work_sync(&chg->icl_change_work); cancel_delayed_work_sync(&chg->pl_enable_work); diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h index bee121f36c0d..b31f9255568e 100644 --- a/drivers/power/supply/qcom/smb5-lib.h +++ b/drivers/power/supply/qcom/smb5-lib.h @@ -72,6 +72,7 @@ enum print_reason { #define HVDCP2_ICL_VOTER "HVDCP2_ICL_VOTER" #define AICL_THRESHOLD_VOTER "AICL_THRESHOLD_VOTER" #define USBOV_DBC_VOTER "USBOV_DBC_VOTER" +#define CHG_TERMINATION_VOTER "CHG_TERMINATION_VOTER" #define BOOST_BACK_STORM_COUNT 3 #define WEAK_CHG_STORM_COUNT 8 @@ -114,6 +115,7 @@ enum { SW_THERM_REGULATION_WA = BIT(1), WEAK_ADAPTER_WA = BIT(2), USBIN_OV_WA = BIT(3), + CHG_TERMINATION_WA = BIT(4), }; enum jeita_cfg_stat { @@ -402,6 +404,7 @@ struct smb_charger { struct work_struct pl_update_work; struct work_struct jeita_update_work; struct work_struct moisture_protection_work; + struct work_struct chg_termination_work; struct delayed_work ps_change_timeout_work; struct delayed_work clear_hdc_work; struct delayed_work icl_change_work; @@ -415,6 +418,7 @@ struct smb_charger { struct alarm lpd_recheck_timer; struct alarm moisture_protection_alarm; + struct alarm chg_termination_alarm; /* secondary charger config */ bool sec_pl_present; @@ -493,6 +497,8 @@ struct smb_charger { int aicl_cont_threshold_mv; int default_aicl_cont_threshold_mv; bool aicl_max_reached; + int charge_full_cc; + int cc_soc_ref; /* workaround flag */ u32 wa_flags; -- GitLab From 43e0fc7085ef9f717ec70bec36995e1eee3b5e40 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 10 Jan 2019 11:22:38 +0530 Subject: [PATCH 0805/1286] ARM: dts: msm: Configure the LDO10 as a parent to LDO15 for trinket Configure the LDO10 as a parent-supply to the LDO15 as per the client's requirement. Change-Id: Ibacaff43c3fbacb027181dfe0ac00063b885bca9 Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/trinket-regulator.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi index b9fe073336d2..c4562ae48bab 100644 --- a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi @@ -270,6 +270,7 @@ rpm-regulator-ldoa15 { status = "okay"; + pm6125_l15-parent-supply = <&pm6125_l10>; L15A: pm6125_l15: regulator-l15 { regulator-min-microvolt = <2928000>; regulator-max-microvolt = <3232000>; -- GitLab From cc9b6ab15b6d70ffa664cd1d49a5b9fd9da74190 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 10 Jan 2019 11:15:39 +0530 Subject: [PATCH 0806/1286] defconfig: sm6150: Enable AMOLED regulator driver for SDMMAGPIE Enable AMOLED regulator driver to control triple power supply provided by OLEDB, AB and IBB modules that is used for AMOLED panels on SM6150/SDMMAGPIE. Change-Id: I840c2efb53b8dc108d36f601a4aad7070a0b4672 Signed-off-by: Kiran Gunda --- arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index 282f3ac8b05d..3fab4b3bc3e2 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -378,6 +378,7 @@ CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_RPMH=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 11638e3e3e13..1b75a4ca0e97 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -391,6 +391,7 @@ CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_RPMH=y -- GitLab From 7c95dd43254590b61130028cc47d77e3e9d8e2e8 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Mon, 24 Dec 2018 12:28:28 +0530 Subject: [PATCH 0807/1286] ARM: dts: msm: Add GPU properties for Trinket Add GPU properties for Trinket. This is needed to support graphics driver functionality on Trinket. Change-Id: I50eebfb6dce5d79f3f11063d98398de4124ba950 Signed-off-by: Deepak Kumar --- arch/arm64/boot/dts/qcom/trinket-gpu.dtsi | 269 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 2 files changed, 270 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-gpu.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi b/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi new file mode 100644 index 000000000000..d01fd1fcc313 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi @@ -0,0 +1,269 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a610_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */ + opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */ + opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */ + opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */ + opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */ + opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */ + opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */ + opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */ + opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */ + opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */ + opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */ + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; + }; + + msm_gpu: qcom,kgsl-3d0@5900000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + + reg = <0x5900000 0x90000>, + <0x5961000 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; + + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + qcom,id = <0>; + qcom,chipid = <0x06010000>; + + qcom,initial-pwrlevel = <6>; + qcom,idle-timeout = <80>; + + qcom,ubwc-mode = <1>; + qcom,min-access-length = <64>; + qcom,highest-bank-bit = <14>; + + /* size in bytes */ + qcom,snapshot-size = <1048576>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "iface_clock", "mem_iface_clk", + "alt_mem_iface_clk", "gmu_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 800000>, /* 1 bus=100 (LOW SVS) */ + <26 512 0 1600000>, /* 2 bus=200 (LOW SVS) */ + <26 512 0 2400000>, /* 3 bus=300 (LOW SVS) */ + <26 512 0 3608000>, /* 4 bus=451 (LOW SVS) */ + <26 512 0 4376000>, /* 5 bus=547 (LOW SVS) */ + <26 512 0 5448000>, /* 6 bus=681 (SVS) */ + <26 512 0 6144000>, /* 7 bus=768 (SVS) */ + <26 512 0 8136000>, /* 8 bus=1017 (SVS_L1) */ + <26 512 0 10824000>, /* 9 bus=1353 (NOM) */ + <26 512 0 12440000>, /* 10 bus=1555 (NOM) */ + <26 512 0 14432000>; /* 11 bus=1804 (TURBO) */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <422>; + qcom,pm-qos-wakeup-latency = <422>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <5>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <980000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <820000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x59a0000 0x10000>; + qcom,protect = <0xa0000 0x10000>; + + clocks = <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>; + + clock-names = "mem_clk", "mem_iface_clk", + "alt_mem_iface_clk"; + + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0 1>; + qcom,gpu-offset = <0xa8000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 2 0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..e19ddd6e62aa 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1980,6 +1980,7 @@ #include "trinket-coresight.dtsi" #include "trinket-vidc.dtsi" #include "trinket-pm.dtsi" +#include "trinket-gpu.dtsi" &pm6125_vadc { rf_pa0_therm { -- GitLab From 49ea1c4693ba8e38e039b96e8538659dd638223b Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 10 Jan 2019 13:20:13 +0530 Subject: [PATCH 0808/1286] pinctrl: dt-bindings: Add dt-bindings for clk-names and external clk Add lpi clock-names and clocks properties to dt-bindings for pinctrl. Change-Id: I81b4891e85749111ce3e013aa7f83fba3a6c2157 Signed-off-by: Vatsal Bucha --- .../devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt index 2d09a6a01457..d1feda2e0f70 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpi-pinctrl.txt @@ -37,6 +37,16 @@ Following properties are for LPI GPIO controller device main node. The first cell will be used to define gpio number and the second denotes the flags for this gpio. +- clock-names: + Usage: optional + Value type: + Definition: Must be "lpass_core_hw_vote" + +- clocks: + Usage: optional + Value type: + Definition: Gives external clock source if present. + Please refer to ../gpio/gpio.txt for general description of GPIO bindings. Please refer to pinctrl-bindings.txt in this directory for details of the -- GitLab From a07d809a4b83d8f9f81641692d90ac3a7b34a881 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Wed, 2 Jan 2019 18:14:40 +0530 Subject: [PATCH 0809/1286] msm: camera: icp: Reset if clock is enabled Reset IPE/BPS only if clock is enabled. Change-Id: I6331b60b00af8eff02e1d072929df85e6502aa9d Signed-off-by: Trishansh Bhardwaj --- .../platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c | 9 ++++++++- .../platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c b/drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c index b969c92ccbc8..a330cff293d6 100644 --- a/drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c +++ b/drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -226,6 +226,13 @@ static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info, bool reset_bps_top_fail = false; CAM_DBG(CAM_ICP, "CAM_ICP_BPS_CMD_RESET"); + + if (!core_info->clk_enable || !core_info->cpas_start) { + CAM_ERR(CAM_ICP, "BPS reset failed. clk_en %d cpas_start %d", + core_info->clk_enable, core_info->cpas_start); + return -EINVAL; + } + /* Reset BPS CDM core*/ cam_io_w_mb((uint32_t)0xF, soc_info->reg_map[0].mem_base + BPS_CDM_RST_CMD); diff --git a/drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c b/drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c index 142fcdc6017d..1f71c7d4cd36 100644 --- a/drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c +++ b/drivers/media/platform/msm/camera/cam_icp/icp_hw/ipe_hw/ipe_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -222,6 +222,12 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info, bool reset_ipe_top_fail = false; CAM_DBG(CAM_ICP, "CAM_ICP_IPE_CMD_RESET"); + if (!core_info->clk_enable || !core_info->cpas_start) { + CAM_ERR(CAM_HFI, "IPE reset failed. clk_en %d cpas_start %d", + core_info->clk_enable, core_info->cpas_start); + return -EINVAL; + } + /* IPE CDM core reset*/ cam_io_w_mb((uint32_t)0xF, soc_info->reg_map[0].mem_base + IPE_CDM_RST_CMD); -- GitLab From 6545d0b891545977e10a1825df6a89f99174b516 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Thu, 10 Jan 2019 12:35:39 +0530 Subject: [PATCH 0810/1286] ARM: dts: msm: Add audio support for miniDP usbc sm6150 variant Add audio entry in miniDP usbc sm6150 variant related files. Change-Id: If5b4e29b9d19d9d41f56341e2a0822fe6532e588 Signed-off-by: Laxminath Kasam --- arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts | 3 ++- arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts b/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts index 998aeb40a64d..86f784bad3bb 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -17,6 +17,7 @@ #include #include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" / { model = "USBC mini DP Primary Panel IDP"; diff --git a/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp.dts b/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp.dts index af2fdaa3b901..416d1d3df8b4 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp.dts +++ b/arch/arm64/boot/dts/qcom/sm6150-usbc-minidp-idp.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,6 +14,7 @@ #include "sm6150.dtsi" #include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" / { model = "Qualcomm Technologies, Inc. SM6150 PM6150 USBC mini DP Primary Panel IDP"; -- GitLab From 1505afb5def2ac59a3605dca28bfd068d67dd5f1 Mon Sep 17 00:00:00 2001 From: xigualu Date: Wed, 12 Dec 2018 16:55:23 +0530 Subject: [PATCH 0811/1286] input: touchscreen: add synaptics_tcm v1.1 reference touch driver Add synaptics_tcm v1.1 reference touch driver code for third generation touch controller chipsets including TDDI support. Change-Id: I42bc348f5365a0542f5bdba30da2e4c63ab4a1cf Signed-off-by: xigualu Git-commit: c0ee4c3b5d7f274adc2cd0ede9c083f694329abe Git-repo: https://source.codeaurora.org/external/thundersoft/ihvjointlab/sensor-driver/commit/?h=Synaptics_tcm_v1.1 [feim1@codeaurora.org: add TDDI support with Display dependency] [vevekv@codeaurora.org: resolve merge conflicts and fix errors] Signed-off-by: Fei Mao Signed-off-by: Vevek Venkatesan --- .../input/touchscreen/synaptics_tcm_i2c.txt | 71 + .../input/touchscreen/synaptics_tcm_spi.txt | 86 + drivers/input/touchscreen/Kconfig | 10 + drivers/input/touchscreen/Makefile | 1 + .../input/touchscreen/synaptics_tcm/Kconfig | 128 + .../input/touchscreen/synaptics_tcm/Makefile | 16 + .../synaptics_tcm/synaptics_tcm_core.c | 3561 +++++++++++++++++ .../synaptics_tcm/synaptics_tcm_core.h | 666 +++ .../synaptics_tcm/synaptics_tcm_device.c | 704 ++++ .../synaptics_tcm/synaptics_tcm_diagnostics.c | 564 +++ .../synaptics_tcm/synaptics_tcm_i2c.c | 496 +++ .../synaptics_tcm/synaptics_tcm_recovery.c | 898 +++++ .../synaptics_tcm/synaptics_tcm_reflash.c | 2184 ++++++++++ .../synaptics_tcm/synaptics_tcm_spi.c | 670 ++++ .../synaptics_tcm/synaptics_tcm_testing.c | 1938 +++++++++ .../synaptics_tcm/synaptics_tcm_testing.h | 85 + .../synaptics_tcm/synaptics_tcm_touch.c | 1265 ++++++ .../synaptics_tcm/synaptics_tcm_zeroflash.c | 1012 +++++ include/linux/input/synaptics_tcm.h | 63 + 19 files changed, 14418 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_i2c.txt create mode 100644 Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_spi.txt create mode 100644 drivers/input/touchscreen/synaptics_tcm/Kconfig create mode 100644 drivers/input/touchscreen/synaptics_tcm/Makefile create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_device.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_diagnostics.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_i2c.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_recovery.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_spi.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.h create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_touch.c create mode 100644 drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_zeroflash.c create mode 100644 include/linux/input/synaptics_tcm.h diff --git a/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_i2c.txt b/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_i2c.txt new file mode 100644 index 000000000000..11ec15a5603b --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_i2c.txt @@ -0,0 +1,71 @@ +Synaptics TCM I2C touchscreen controller + +Required properties: + - compatible: + should be "synaptics,tcm-i2c" + - reg: + i2c slave address of device + - interrupt-parent: + hardware controller of interrupt signal + - interrupts: + gpio number and flags of interrupt signal + - vdd-supply: + digital power source + - avdd-supply: + analog power source + - pinctrl-names: + - pinctrl-0: + - pinctrl-1: + should be defined if using pinctrl framework + "pmx_ts_active": active configuration of pins + "pmx_ts_suspend": disabled configuration of pins + - synaptics,bus-reg-name: + name of digital power source regulator + - synaptics,pwr-reg-name: + name of analog power source regulator + - synaptics,irq-gpio: + interrupt hardware controller, gpio number, and flags + - synaptics,irq-on-state: + active state of interrupt signal + +Optional properties: + - synaptics,power-gpio: + hardware controller and gpio number of power control signal + - synaptics,power-delay-ms: + delay time in ms after powering on device + - synaptics,reset-gpio: + hardware controller and gpio number of reset signal + - synaptics,reset-delay-ms: + delay time in ms after issuing reset to device + - synaptics,reset-on-state: + active state of reset signal + - synaptics,reset-active-ms: + active duration in ms of reset signal + - synaptics,x-flip: + flip x axis + - synaptics,y-flip: + flip y axis + - synaptics,swap-axes: + swap x and y axes + - synaptics,ubl-i2c-addr: + i2c slave address of device in microbootloader mode + +Example: + synaptics_tcm@2c { + compatible = "synaptics,tcm-i2c"; + reg = <0x2c>; + interrupt-parent = <&msm_gpio>; + interrupts = <65 0x2008>; + vdd-supply = <&pm8994_lvs2>; + avdd-supply = <&pm8994_l22>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_suspend>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&msm_gpio 65 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x2c>; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_spi.txt b/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_spi.txt new file mode 100644 index 000000000000..b9d5c20d425a --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/synaptics_tcm_spi.txt @@ -0,0 +1,86 @@ +Synaptics TCM SPI touchscreen controller + +Required properties: + - compatible: + should be "synaptics,tcm-spi" + - reg: + should be 0 + - spi-max-frequency: + maximum spi clock frequency + - interrupt-parent: + hardware controller of interrupt signal + - interrupts: + gpio number and flags of interrupt signal + - vdd-supply: + digital power source + - avdd-supply: + analog power source + - pinctrl-names: + - pinctrl-0: + - pinctrl-1: + should be defined if using pinctrl framework + "pmx_ts_active": active configuration of pins + "pmx_ts_suspend": disabled configuration of pins + - synaptics,bus-reg-name: + name of digital power source regulator + - synaptics,pwr-reg-name: + name of analog power source regulator + - synaptics,irq-gpio: + interrupt hardware controller, gpio number, and flags + - synaptics,irq-on-state: + active state of interrupt signal + +Optional properties: + - synaptics,spi-mode: + spi mode + - synaptics,byte-delay-us: + inter-byte delay time in us + - synaptics,block-delay-us: + inter-block delay time in us + - synaptics,power-gpio: + hardware controller and gpio number of power control signal + - synaptics,power-delay-ms: + delay time in ms after powering on device + - synaptics,reset-gpio: + hardware controller and gpio number of reset signal + - synaptics,reset-delay-ms: + delay time in ms after issuing reset to device + - synaptics,reset-on-state: + active state of reset signal + - synaptics,reset-active-ms: + active duration in ms of reset signal + - synaptics,x-flip: + flip x axis + - synaptics,y-flip: + flip y axis + - synaptics,swap-axes: + swap x and y axes + - synaptics,ubl-max-freq: + maximum spi clock frequency for microbootloader mode + - synaptics,ubl-byte-delay-us: + inter-byte delay time in us for microbootloader mode + +Example: + synaptics_tcm@0 { + compatible = "synaptics,tcm-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&msm_gpio>; + interrupts = <65 0x2008>; + vdd-supply = <&pm8994_lvs2>; + avdd-supply = <&pm8994_l22>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_suspend>; + synaptics,bus-reg-name = "vdd"; + synaptics,pwr-reg-name = "avdd"; + synaptics,irq-gpio = <&msm_gpio 65 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,spi-mode = <3>; + synaptics,byte-delay-us = <0>; + synaptics,block-delay-us = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,ubl-max-freq = <5000000>; + synaptics,ubl-byte-delay-us = <20>; + }; diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index e9e59a3d6c59..4a48349be6a1 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1278,4 +1278,14 @@ config TOUCHSCREEN_SYNAPTICS_DSX source "drivers/input/touchscreen/synaptics_dsx/Kconfig" +config TOUCHSCREEN_SYNAPTICS_TCM + bool "Synaptics TCM Touchscreen Driver" + depends on I2C + help + Say Y here if you have a Synaptics Touchscreen. + + If unsure, say N. + +source "drivers/input/touchscreen/synaptics_tcm/Kconfig" + endif diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index fbc7fdbaf3f0..8c54ef46cf2c 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -107,3 +107,4 @@ obj-$(CONFIG_TOUCHSCREEN_COLIBRI_VF50) += colibri-vf50-ts.o obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o obj-$(CONFIG_TOUCHSCREEN_ST) += st/ obj-$(CONFIG_TOUCHSCREEN_HIMAX_CHIPSET) += hxchipset/ +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM) += synaptics_tcm/ diff --git a/drivers/input/touchscreen/synaptics_tcm/Kconfig b/drivers/input/touchscreen/synaptics_tcm/Kconfig new file mode 100644 index 000000000000..88bd4159967b --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/Kconfig @@ -0,0 +1,128 @@ +# +# Synaptics TCM touchscreen driver configuration +# +menuconfig TOUCHSCREEN_SYNAPTICS_TCM + bool "Synaptics TCM touchscreen" + help + Say Y here if you have a Synaptics TCM touchscreen connected + to your system. + + If unsure, say N. + +if TOUCHSCREEN_SYNAPTICS_TCM + +choice + default TOUCHSCREEN_SYNAPTICS_TCM_I2C + prompt "Synaptics TCM bus module" +config TOUCHSCREEN_SYNAPTICS_TCM_I2C + bool "I2C" + depends on I2C + help + Say Y here to use I2C bus for communication. + + Else, say N. + + This will configure I2C bus for communicating + with touch controller. + +config TOUCHSCREEN_SYNAPTICS_TCM_SPI + bool "SPI" + depends on SPI_MASTER + help + Say Y here to use SPI bus for communication. + + Else, say N. + + This will configure SPI bus for communicating + with touch controller. + +endchoice + +config TOUCHSCREEN_SYNAPTICS_TCM_CORE + tristate "Synaptics TCM core module" + depends on I2C || SPI_MASTER + help + Say Y here to enable core functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_core. + +config TOUCHSCREEN_SYNAPTICS_TCM_TOUCH + tristate "Synaptics TCM touch module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for touch reporting. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_touch. + +config TOUCHSCREEN_SYNAPTICS_TCM_DEVICE + tristate "Synaptics TCM device module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for TCM device functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_device. + +config TOUCHSCREEN_SYNAPTICS_TCM_TESTING + tristate "Synaptics TCM testing module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for testing functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_testing. + +config TOUCHSCREEN_SYNAPTICS_TCM_REFLASH + tristate "Synaptics TCM reflash module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for reflash functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_reflash. + +config TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY + tristate "Synaptics TCM recovery module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for recovery functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_recovery. + +config TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH + tristate "Synaptics TCM zeroflash module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for ZeroFlash functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_zeroflash. + +config TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS + tristate "Synaptics TCM diagnostics module" + depends on TOUCHSCREEN_SYNAPTICS_TCM_CORE + help + Say Y here to enable support for diagnostics functionality. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called synaptics_tcm_diagnostics. +endif diff --git a/drivers/input/touchscreen/synaptics_tcm/Makefile b/drivers/input/touchscreen/synaptics_tcm/Makefile new file mode 100644 index 000000000000..30db3b56516a --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/Makefile @@ -0,0 +1,16 @@ +# +# Makefile for the Synaptics TCM touchscreen driver. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_SPI) += synaptics_tcm_spi.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_I2C) += synaptics_tcm_i2c.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE) += synaptics_tcm_core.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH) += synaptics_tcm_touch.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE) += synaptics_tcm_device.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING) += synaptics_tcm_testing.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH) += synaptics_tcm_reflash.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY) += synaptics_tcm_recovery.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH) += synaptics_tcm_zeroflash.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS) += synaptics_tcm_diagnostics.o diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c new file mode 100644 index 000000000000..70ce96a250f0 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c @@ -0,0 +1,3561 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include +#include +#include "synaptics_tcm_core.h" + +#define RESET_ON_RESUME + +/* #define RESUME_EARLY_UNBLANK */ + +#define RESET_ON_RESUME_DELAY_MS 20 + +#define PREDICTIVE_READING + +#define MIN_READ_LENGTH 9 + +#define KEEP_DRIVER_ON_ERROR + +#define FORCE_RUN_APPLICATION_FIRMWARE + +#define NOTIFIER_PRIORITY 2 + +#define RESPONSE_TIMEOUT_MS 3000 + +#define APP_STATUS_POLL_TIMEOUT_MS 1000 + +#define APP_STATUS_POLL_MS 100 + +#define ENABLE_IRQ_DELAY_MS 20 + +#define FALL_BACK_ON_POLLING + +#define POLLING_DELAY_MS 5 + +#define RUN_WATCHDOG true + +#define WATCHDOG_TRIGGER_COUNT 2 + +#define WATCHDOG_DELAY_MS 1000 + +#define MODE_SWITCH_DELAY_MS 100 + +#define READ_RETRY_US_MIN 5000 + +#define READ_RETRY_US_MAX 10000 + +#define WRITE_DELAY_US_MIN 500 + +#define WRITE_DELAY_US_MAX 1000 + +#define HOST_DOWNLOAD_WAIT_MS 100 + +#define HOST_DOWNLOAD_TIMEOUT_MS 1000 + +#define DYNAMIC_CONFIG_SYSFS_DIR_NAME "dynamic_config" + +#define dynamic_config_sysfs(c_name, id) \ +static ssize_t syna_tcm_sysfs_##c_name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + int retval; \ + unsigned short value; \ + struct device *p_dev; \ + struct kobject *p_kobj; \ + struct syna_tcm_hcd *tcm_hcd; \ +\ + p_kobj = sysfs_dir->parent; \ + p_dev = container_of(p_kobj, struct device, kobj); \ + tcm_hcd = dev_get_drvdata(p_dev); \ +\ + mutex_lock(&tcm_hcd->extif_mutex); \ +\ + retval = tcm_hcd->get_dynamic_config(tcm_hcd, id, &value); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to get dynamic config\n"); \ + goto exit; \ + } \ +\ + retval = snprintf(buf, PAGE_SIZE, "%u\n", value); \ +\ +exit: \ + mutex_unlock(&tcm_hcd->extif_mutex); \ +\ + return retval; \ +} \ +\ +static ssize_t syna_tcm_sysfs_##c_name##_store(struct device *dev, \ + struct device_attribute *attr, const char *buf, size_t count) \ +{ \ + int retval; \ + unsigned int input; \ + struct device *p_dev; \ + struct kobject *p_kobj; \ + struct syna_tcm_hcd *tcm_hcd; \ +\ + p_kobj = sysfs_dir->parent; \ + p_dev = container_of(p_kobj, struct device, kobj); \ + tcm_hcd = dev_get_drvdata(p_dev); \ +\ + if (kstrtouint(buf, 10, &input)) \ + return -EINVAL; \ +\ + mutex_lock(&tcm_hcd->extif_mutex); \ +\ + retval = tcm_hcd->set_dynamic_config(tcm_hcd, id, input); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to set dynamic config\n"); \ + goto exit; \ + } \ +\ + retval = count; \ +\ +exit: \ + mutex_unlock(&tcm_hcd->extif_mutex); \ +\ + return retval; \ +} + +DECLARE_COMPLETION(response_complete); + +static struct kobject *sysfs_dir; + +static struct syna_tcm_module_pool mod_pool; + +SHOW_PROTOTYPE(syna_tcm, info); +STORE_PROTOTYPE(syna_tcm, irq_en); +STORE_PROTOTYPE(syna_tcm, reset); +STORE_PROTOTYPE(syna_tcm, watchdog); +SHOW_STORE_PROTOTYPE(syna_tcm, no_doze); +SHOW_STORE_PROTOTYPE(syna_tcm, disable_noise_mitigation); +SHOW_STORE_PROTOTYPE(syna_tcm, inhibit_frequency_shift); +SHOW_STORE_PROTOTYPE(syna_tcm, requested_frequency); +SHOW_STORE_PROTOTYPE(syna_tcm, disable_hsync); +SHOW_STORE_PROTOTYPE(syna_tcm, rezero_on_exit_deep_sleep); +SHOW_STORE_PROTOTYPE(syna_tcm, charger_connected); +SHOW_STORE_PROTOTYPE(syna_tcm, no_baseline_relaxation); +SHOW_STORE_PROTOTYPE(syna_tcm, in_wakeup_gesture_mode); +SHOW_STORE_PROTOTYPE(syna_tcm, stimulus_fingers); +SHOW_STORE_PROTOTYPE(syna_tcm, grip_suppression_enabled); +SHOW_STORE_PROTOTYPE(syna_tcm, enable_thick_glove); +SHOW_STORE_PROTOTYPE(syna_tcm, enable_glove); + +static struct device_attribute *attrs[] = { + ATTRIFY(info), + ATTRIFY(irq_en), + ATTRIFY(reset), + ATTRIFY(watchdog), +}; + +static struct device_attribute *dynamic_config_attrs[] = { + ATTRIFY(no_doze), + ATTRIFY(disable_noise_mitigation), + ATTRIFY(inhibit_frequency_shift), + ATTRIFY(requested_frequency), + ATTRIFY(disable_hsync), + ATTRIFY(rezero_on_exit_deep_sleep), + ATTRIFY(charger_connected), + ATTRIFY(no_baseline_relaxation), + ATTRIFY(in_wakeup_gesture_mode), + ATTRIFY(stimulus_fingers), + ATTRIFY(grip_suppression_enabled), + ATTRIFY(enable_thick_glove), + ATTRIFY(enable_glove), +}; + +static ssize_t syna_tcm_sysfs_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + unsigned int count; + struct device *p_dev; + struct kobject *p_kobj; + struct syna_tcm_hcd *tcm_hcd; + + p_kobj = sysfs_dir->parent; + p_dev = container_of(p_kobj, struct device, kobj); + tcm_hcd = dev_get_drvdata(p_dev); + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = tcm_hcd->identify(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto exit; + } + + count = 0; + + retval = snprintf(buf, PAGE_SIZE - count, + "TouchComm version: %d\n", + tcm_hcd->id_info.version); + if (retval < 0) + goto exit; + + buf += retval; + count += retval; + + if (SYNAPTICS_TCM_ID_SUBVERSION == 0) { + retval = snprintf(buf, PAGE_SIZE - count, + "Driver version: %d.%d\n", + (unsigned char)(SYNAPTICS_TCM_ID_VERSION >> 8), + (unsigned char)SYNAPTICS_TCM_ID_VERSION); + } else { + retval = snprintf(buf, PAGE_SIZE - count, + "Driver version: %d.%d.%d\n", + (unsigned char)(SYNAPTICS_TCM_ID_VERSION >> 8), + (unsigned char)SYNAPTICS_TCM_ID_VERSION, + SYNAPTICS_TCM_ID_SUBVERSION); + } + if (retval < 0) + goto exit; + + buf += retval; + count += retval; + + switch (tcm_hcd->id_info.mode) { + case MODE_APPLICATION: + retval = snprintf(buf, PAGE_SIZE - count, + "Firmware mode: Application\n"); + if (retval < 0) + goto exit; + break; + case MODE_HOST_DOWNLOAD: + retval = snprintf(buf, PAGE_SIZE - count, + "Firmware mode: Host Download\n"); + if (retval < 0) + goto exit; + break; + case MODE_BOOTLOADER: + retval = snprintf(buf, PAGE_SIZE - count, + "Firmware mode: Bootloader\n"); + if (retval < 0) + goto exit; + break; + case MODE_TDDI_BOOTLOADER: + retval = snprintf(buf, PAGE_SIZE - count, + "Firmware mode: TDDI Bootloader\n"); + if (retval < 0) + goto exit; + break; + default: + retval = snprintf(buf, PAGE_SIZE - count, + "Firmware mode: Unknown (%d)\n", + tcm_hcd->id_info.mode); + if (retval < 0) + goto exit; + break; + } + buf += retval; + count += retval; + + retval = snprintf(buf, PAGE_SIZE - count, + "Part number: "); + if (retval < 0) + goto exit; + + buf += retval; + count += retval; + + retval = secure_memcpy(buf, + PAGE_SIZE - count, + tcm_hcd->id_info.part_number, + sizeof(tcm_hcd->id_info.part_number), + sizeof(tcm_hcd->id_info.part_number)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy part number string\n"); + goto exit; + } + buf += sizeof(tcm_hcd->id_info.part_number); + count += sizeof(tcm_hcd->id_info.part_number); + + retval = snprintf(buf, PAGE_SIZE - count, + "\n"); + if (retval < 0) + goto exit; + + buf += retval; + count += retval; + + retval = snprintf(buf, PAGE_SIZE - count, + "Packrat number: %d\n", + tcm_hcd->packrat_number); + if (retval < 0) + goto exit; + + count += retval; + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t syna_tcm_sysfs_irq_en_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int retval; + unsigned int input; + struct device *p_dev; + struct kobject *p_kobj; + struct syna_tcm_hcd *tcm_hcd; + + p_kobj = sysfs_dir->parent; + p_dev = container_of(p_kobj, struct device, kobj); + tcm_hcd = dev_get_drvdata(p_dev); + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (input == 0) { + retval = tcm_hcd->enable_irq(tcm_hcd, false, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable interrupt\n"); + goto exit; + } + } else if (input == 1) { + retval = tcm_hcd->enable_irq(tcm_hcd, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable interrupt\n"); + goto exit; + } + } else { + retval = -EINVAL; + goto exit; + } + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t syna_tcm_sysfs_reset_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int retval; + bool hw_reset; + unsigned int input; + struct device *p_dev; + struct kobject *p_kobj; + struct syna_tcm_hcd *tcm_hcd; + + p_kobj = sysfs_dir->parent; + p_dev = container_of(p_kobj, struct device, kobj); + tcm_hcd = dev_get_drvdata(p_dev); + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + if (input == 1) + hw_reset = false; + else if (input == 2) + hw_reset = true; + else + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = tcm_hcd->reset(tcm_hcd, hw_reset, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + goto exit; + } + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t syna_tcm_sysfs_watchdog_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned int input; + struct device *p_dev; + struct kobject *p_kobj; + struct syna_tcm_hcd *tcm_hcd; + + p_kobj = sysfs_dir->parent; + p_dev = container_of(p_kobj, struct device, kobj); + tcm_hcd = dev_get_drvdata(p_dev); + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + if (input != 0 && input != 1) + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + tcm_hcd->watchdog.run = input; + tcm_hcd->update_watchdog(tcm_hcd, input); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return count; +} + +dynamic_config_sysfs(no_doze, DC_NO_DOZE) + +dynamic_config_sysfs(disable_noise_mitigation, DC_DISABLE_NOISE_MITIGATION) + +dynamic_config_sysfs(inhibit_frequency_shift, DC_INHIBIT_FREQUENCY_SHIFT) + +dynamic_config_sysfs(requested_frequency, DC_REQUESTED_FREQUENCY) + +dynamic_config_sysfs(disable_hsync, DC_DISABLE_HSYNC) + +dynamic_config_sysfs(rezero_on_exit_deep_sleep, DC_REZERO_ON_EXIT_DEEP_SLEEP) + +dynamic_config_sysfs(charger_connected, DC_CHARGER_CONNECTED) + +dynamic_config_sysfs(no_baseline_relaxation, DC_NO_BASELINE_RELAXATION) + +dynamic_config_sysfs(in_wakeup_gesture_mode, DC_IN_WAKEUP_GESTURE_MODE) + +dynamic_config_sysfs(stimulus_fingers, DC_STIMULUS_FINGERS) + +dynamic_config_sysfs(grip_suppression_enabled, DC_GRIP_SUPPRESSION_ENABLED) + +dynamic_config_sysfs(enable_thick_glove, DC_ENABLE_THICK_GLOVE) + +dynamic_config_sysfs(enable_glove, DC_ENABLE_GLOVE) + +int syna_tcm_add_module(struct syna_tcm_module_cb *mod_cb, bool insert) +{ + struct syna_tcm_module_handler *mod_handler; + + if (!mod_pool.initialized) { + mutex_init(&mod_pool.mutex); + INIT_LIST_HEAD(&mod_pool.list); + mod_pool.initialized = true; + } + + mutex_lock(&mod_pool.mutex); + + if (insert) { + mod_handler = kzalloc(sizeof(*mod_handler), GFP_KERNEL); + if (!mod_handler) { + mutex_unlock(&mod_pool.mutex); + return -ENOMEM; + } + mod_handler->mod_cb = mod_cb; + mod_handler->insert = true; + mod_handler->detach = false; + list_add_tail(&mod_handler->link, &mod_pool.list); + } else if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (mod_handler->mod_cb->type == mod_cb->type) { + mod_handler->insert = false; + mod_handler->detach = true; + goto exit; + } + } + } + +exit: + mutex_unlock(&mod_pool.mutex); + + if (mod_pool.queue_work) + queue_work(mod_pool.workqueue, &mod_pool.work); + + return 0; +} +EXPORT_SYMBOL(syna_tcm_add_module); + +static void syna_tcm_module_work(struct work_struct *work) +{ + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_module_handler *tmp_handler; + struct syna_tcm_hcd *tcm_hcd = mod_pool.tcm_hcd; + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry_safe(mod_handler, + tmp_handler, + &mod_pool.list, + link) { + if (mod_handler->insert) { + if (mod_handler->mod_cb->init) + mod_handler->mod_cb->init(tcm_hcd); + mod_handler->insert = false; + } + if (mod_handler->detach) { + if (mod_handler->mod_cb->remove) + mod_handler->mod_cb->remove(tcm_hcd); + list_del(&mod_handler->link); + kfree(mod_handler); + } + } + } + + mutex_unlock(&mod_pool.mutex); +} + +/** + * syna_tcm_report_notifier() - notify occurrence of report received from device + * + * @data: handle of core module + * + * The occurrence of the report generated by the device is forwarded to the + * asynchronous inbox of each registered application module. + */ +static int syna_tcm_report_notifier(void *data) +{ + struct sched_param param = { .sched_priority = NOTIFIER_PRIORITY }; + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = data; + + sched_setscheduler_nocheck(current, SCHED_RR, ¶m); + + set_current_state(TASK_INTERRUPTIBLE); + + while (!kthread_should_stop()) { + schedule(); + + if (kthread_should_stop()) + break; + + set_current_state(TASK_RUNNING); + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->asyncbox)) + mod_handler->mod_cb->asyncbox(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + + set_current_state(TASK_INTERRUPTIBLE); + }; + + return 0; +} + +/** + * syna_tcm_dispatch_report() - dispatch report received from device + * + * @tcm_hcd: handle of core module + * + * The report generated by the device is forwarded to the synchronous inbox of + * each registered application module for further processing. In addition, the + * report notifier thread is woken up for asynchronous notification of the + * report occurrence. + */ +static void syna_tcm_dispatch_report(struct syna_tcm_hcd *tcm_hcd) +{ + struct syna_tcm_module_handler *mod_handler; + + LOCK_BUFFER(tcm_hcd->in); + LOCK_BUFFER(tcm_hcd->report.buffer); + + tcm_hcd->report.buffer.buf = &tcm_hcd->in.buf[MESSAGE_HEADER_SIZE]; + + tcm_hcd->report.buffer.buf_size = tcm_hcd->in.buf_size; + tcm_hcd->report.buffer.buf_size -= MESSAGE_HEADER_SIZE; + + tcm_hcd->report.buffer.data_length = tcm_hcd->payload_length; + + tcm_hcd->report.id = tcm_hcd->status_report_code; + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->syncbox)) + mod_handler->mod_cb->syncbox(tcm_hcd); + } + } + + + tcm_hcd->async_report_id = tcm_hcd->status_report_code; + + mutex_unlock(&mod_pool.mutex); + + UNLOCK_BUFFER(tcm_hcd->report.buffer); + UNLOCK_BUFFER(tcm_hcd->in); + + wake_up_process(tcm_hcd->notifier_thread); +} + +/** + * syna_tcm_dispatch_response() - dispatch response received from device + * + * @tcm_hcd: handle of core module + * + * The response to a command is forwarded to the sender of the command. + */ +static void syna_tcm_dispatch_response(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (atomic_read(&tcm_hcd->command_status) != CMD_BUSY) + return; + + tcm_hcd->response_code = tcm_hcd->status_report_code; + + if (tcm_hcd->payload_length == 0) { + atomic_set(&tcm_hcd->command_status, CMD_IDLE); + goto exit; + } + + LOCK_BUFFER(tcm_hcd->resp); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->resp, + tcm_hcd->payload_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for tcm_hcd->resp.buf\n"); + UNLOCK_BUFFER(tcm_hcd->resp); + atomic_set(&tcm_hcd->command_status, CMD_ERROR); + goto exit; + } + + LOCK_BUFFER(tcm_hcd->in); + + retval = secure_memcpy(tcm_hcd->resp.buf, + tcm_hcd->resp.buf_size, + &tcm_hcd->in.buf[MESSAGE_HEADER_SIZE], + tcm_hcd->in.buf_size - MESSAGE_HEADER_SIZE, + tcm_hcd->payload_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy payload\n"); + UNLOCK_BUFFER(tcm_hcd->in); + UNLOCK_BUFFER(tcm_hcd->resp); + atomic_set(&tcm_hcd->command_status, CMD_ERROR); + goto exit; + } + + tcm_hcd->resp.data_length = tcm_hcd->payload_length; + + UNLOCK_BUFFER(tcm_hcd->in); + UNLOCK_BUFFER(tcm_hcd->resp); + + atomic_set(&tcm_hcd->command_status, CMD_IDLE); + +exit: + complete(&response_complete); +} + +/** + * syna_tcm_dispatch_message() - dispatch message received from device + * + * @tcm_hcd: handle of core module + * + * The information received in the message read in from the device is dispatched + * to the appropriate destination based on whether the information represents a + * report or a response to a command. + */ +static void syna_tcm_dispatch_message(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *build_id; + unsigned int payload_length; + unsigned int max_write_size; + + if (tcm_hcd->status_report_code == REPORT_IDENTIFY) { + payload_length = tcm_hcd->payload_length; + + LOCK_BUFFER(tcm_hcd->in); + + retval = secure_memcpy((unsigned char *)&tcm_hcd->id_info, + sizeof(tcm_hcd->id_info), + &tcm_hcd->in.buf[MESSAGE_HEADER_SIZE], + tcm_hcd->in.buf_size - MESSAGE_HEADER_SIZE, + MIN(sizeof(tcm_hcd->id_info), payload_length)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy identification info\n"); + UNLOCK_BUFFER(tcm_hcd->in); + return; + } + + UNLOCK_BUFFER(tcm_hcd->in); + + build_id = tcm_hcd->id_info.build_id; + tcm_hcd->packrat_number = le4_to_uint(build_id); + + max_write_size = le2_to_uint(tcm_hcd->id_info.max_write_size); + tcm_hcd->wr_chunk_size = MIN(max_write_size, WR_CHUNK_SIZE); + if (tcm_hcd->wr_chunk_size == 0) + tcm_hcd->wr_chunk_size = max_write_size; + + LOGN(tcm_hcd->pdev->dev.parent, + "Received identify report (firmware mode = 0x%02x)\n", + tcm_hcd->id_info.mode); + + if (atomic_read(&tcm_hcd->command_status) == CMD_BUSY) { + switch (tcm_hcd->command) { + case CMD_RESET: + case CMD_RUN_BOOTLOADER_FIRMWARE: + case CMD_RUN_APPLICATION_FIRMWARE: + case CMD_ENTER_PRODUCTION_TEST_MODE: + tcm_hcd->response_code = STATUS_OK; + atomic_set(&tcm_hcd->command_status, CMD_IDLE); + complete(&response_complete); + break; + default: + LOGN(tcm_hcd->pdev->dev.parent, + "Device has been reset\n"); + atomic_set(&tcm_hcd->command_status, CMD_ERROR); + complete(&response_complete); + break; + } + } + + if (tcm_hcd->id_info.mode == MODE_HOST_DOWNLOAD) { + tcm_hcd->host_download_mode = true; + return; + } + +#ifdef FORCE_RUN_APPLICATION_FIRMWARE + if (tcm_hcd->id_info.mode != MODE_APPLICATION && + !mutex_is_locked(&tcm_hcd->reset_mutex)) { + if (atomic_read(&tcm_hcd->helper.task) == HELP_NONE) { + atomic_set(&tcm_hcd->helper.task, + HELP_RUN_APPLICATION_FIRMWARE); + queue_work(tcm_hcd->helper.workqueue, + &tcm_hcd->helper.work); + return; + } + } +#endif + } + + if (tcm_hcd->status_report_code >= REPORT_IDENTIFY) + syna_tcm_dispatch_report(tcm_hcd); + else + syna_tcm_dispatch_response(tcm_hcd); +} + +/** + * syna_tcm_continued_read() - retrieve entire payload from device + * + * @tcm_hcd: handle of core module + * + * Read transactions are carried out until the entire payload is retrieved from + * the device and stored in the handle of the core module. + */ +static int syna_tcm_continued_read(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char marker; + unsigned char code; + unsigned int idx; + unsigned int offset; + unsigned int chunks; + unsigned int chunk_space; + unsigned int xfer_length; + unsigned int total_length; + unsigned int remaining_length; + + total_length = MESSAGE_HEADER_SIZE + tcm_hcd->payload_length + 1; + + remaining_length = total_length - tcm_hcd->read_length; + + LOCK_BUFFER(tcm_hcd->in); + + retval = syna_tcm_realloc_mem(tcm_hcd, + &tcm_hcd->in, + total_length + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reallocate memory for tcm_hcd->in.buf\n"); + UNLOCK_BUFFER(tcm_hcd->in); + return retval; + } + + /** + * available chunk space for payload = total chunk size minus header + * marker byte and header code byte + */ + if (tcm_hcd->rd_chunk_size == 0) + chunk_space = remaining_length; + else + chunk_space = tcm_hcd->rd_chunk_size - 2; + + chunks = ceil_div(remaining_length, chunk_space); + + chunks = chunks == 0 ? 1 : chunks; + + offset = tcm_hcd->read_length; + + LOCK_BUFFER(tcm_hcd->temp); + + for (idx = 0; idx < chunks; idx++) { + if (remaining_length > chunk_space) + xfer_length = chunk_space; + else + xfer_length = remaining_length; + + if (xfer_length == 1) { + tcm_hcd->in.buf[offset] = MESSAGE_PADDING; + offset += xfer_length; + remaining_length -= xfer_length; + continue; + } + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->temp, + xfer_length + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for temp.buf\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + return retval; + } + + retval = syna_tcm_read(tcm_hcd, + tcm_hcd->temp.buf, + xfer_length + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read from device\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + return retval; + } + + marker = tcm_hcd->temp.buf[0]; + code = tcm_hcd->temp.buf[1]; + + if (marker != MESSAGE_MARKER) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect header marker (0x%02x)\n", + marker); + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + return -EIO; + } + + if (code != STATUS_CONTINUED_READ) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect header code (0x%02x)\n", + code); + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + return -EIO; + } + + retval = secure_memcpy(&tcm_hcd->in.buf[offset], + tcm_hcd->in.buf_size - offset, + &tcm_hcd->temp.buf[2], + tcm_hcd->temp.buf_size - 2, + xfer_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy payload\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + return retval; + } + + offset += xfer_length; + + remaining_length -= xfer_length; + } + + UNLOCK_BUFFER(tcm_hcd->temp); + UNLOCK_BUFFER(tcm_hcd->in); + + return 0; +} + +/** + * syna_tcm_raw_read() - retrieve specific number of data bytes from device + * + * @tcm_hcd: handle of core module + * @in_buf: buffer for storing data retrieved from device + * @length: number of bytes to retrieve from device + * + * Read transactions are carried out until the specific number of data bytes + * are retrieved from the device and stored in in_buf. + */ +static int syna_tcm_raw_read(struct syna_tcm_hcd *tcm_hcd, + unsigned char *in_buf, unsigned int length) +{ + int retval; + unsigned char code; + unsigned int idx; + unsigned int offset; + unsigned int chunks; + unsigned int chunk_space; + unsigned int xfer_length; + unsigned int remaining_length; + + if (length < 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid length information\n"); + return -EINVAL; + } + + /* minus header marker byte and header code byte */ + remaining_length = length - 2; + + /** + * available chunk space for data = total chunk size minus header + * marker byte and header code byte + */ + if (tcm_hcd->rd_chunk_size == 0) + chunk_space = remaining_length; + else + chunk_space = tcm_hcd->rd_chunk_size - 2; + + chunks = ceil_div(remaining_length, chunk_space); + + chunks = chunks == 0 ? 1 : chunks; + + offset = 0; + + LOCK_BUFFER(tcm_hcd->temp); + + for (idx = 0; idx < chunks; idx++) { + if (remaining_length > chunk_space) + xfer_length = chunk_space; + else + xfer_length = remaining_length; + + if (xfer_length == 1) { + in_buf[offset] = MESSAGE_PADDING; + offset += xfer_length; + remaining_length -= xfer_length; + continue; + } + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->temp, + xfer_length + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for temp.buf\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + return retval; + } + + retval = syna_tcm_read(tcm_hcd, + tcm_hcd->temp.buf, + xfer_length + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read from device\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + return retval; + } + + code = tcm_hcd->temp.buf[1]; + + if (idx == 0) { + retval = secure_memcpy(&in_buf[0], + length, + &tcm_hcd->temp.buf[0], + tcm_hcd->temp.buf_size, + xfer_length + 2); + } else { + if (code != STATUS_CONTINUED_READ) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect header code (0x%02x)\n", + code); + UNLOCK_BUFFER(tcm_hcd->temp); + return -EIO; + } + + retval = secure_memcpy(&in_buf[offset], + length - offset, + &tcm_hcd->temp.buf[2], + tcm_hcd->temp.buf_size - 2, + xfer_length); + } + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy data\n"); + UNLOCK_BUFFER(tcm_hcd->temp); + return retval; + } + + if (idx == 0) + offset += (xfer_length + 2); + else + offset += xfer_length; + + remaining_length -= xfer_length; + } + + UNLOCK_BUFFER(tcm_hcd->temp); + + return 0; +} + +/** + * syna_tcm_raw_write() - write command/data to device without receiving + * response + * + * @tcm_hcd: handle of core module + * @command: command to send to device + * @data: data to send to device + * @length: length of data in bytes + * + * A command and its data, if any, are sent to the device. + */ +static int syna_tcm_raw_write(struct syna_tcm_hcd *tcm_hcd, + unsigned char command, unsigned char *data, unsigned int length) +{ + int retval; + unsigned int idx; + unsigned int chunks; + unsigned int chunk_space; + unsigned int xfer_length; + unsigned int remaining_length; + + remaining_length = length; + + /** + * available chunk space for data = total chunk size minus command + * byte + */ + if (tcm_hcd->wr_chunk_size == 0) + chunk_space = remaining_length; + else + chunk_space = tcm_hcd->wr_chunk_size - 1; + + chunks = ceil_div(remaining_length, chunk_space); + + chunks = chunks == 0 ? 1 : chunks; + + LOCK_BUFFER(tcm_hcd->out); + + for (idx = 0; idx < chunks; idx++) { + if (remaining_length > chunk_space) + xfer_length = chunk_space; + else + xfer_length = remaining_length; + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->out, + xfer_length + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + UNLOCK_BUFFER(tcm_hcd->out); + return retval; + } + + if (idx == 0) + tcm_hcd->out.buf[0] = command; + else + tcm_hcd->out.buf[0] = CMD_CONTINUE_WRITE; + + if (xfer_length) { + retval = secure_memcpy(&tcm_hcd->out.buf[1], + tcm_hcd->out.buf_size - 1, + &data[idx * chunk_space], + remaining_length, + xfer_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy data\n"); + UNLOCK_BUFFER(tcm_hcd->out); + return retval; + } + } + + retval = syna_tcm_write(tcm_hcd, + tcm_hcd->out.buf, + xfer_length + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to device\n"); + UNLOCK_BUFFER(tcm_hcd->out); + return retval; + } + + remaining_length -= xfer_length; + } + + UNLOCK_BUFFER(tcm_hcd->out); + + return 0; +} + +/** + * syna_tcm_read_message() - read message from device + * + * @tcm_hcd: handle of core module + * @in_buf: buffer for storing data in raw read mode + * @length: length of data in bytes in raw read mode + * + * If in_buf is not NULL, raw read mode is used and syna_tcm_raw_read() is + * called. Otherwise, a message including its entire payload is retrieved from + * the device and dispatched to the appropriate destination. + */ +static int syna_tcm_read_message(struct syna_tcm_hcd *tcm_hcd, + unsigned char *in_buf, unsigned int length) +{ + int retval; + bool retry; + unsigned int total_length; + struct syna_tcm_message_header *header; + + mutex_lock(&tcm_hcd->rw_ctrl_mutex); + + if (in_buf != NULL) { + retval = syna_tcm_raw_read(tcm_hcd, in_buf, length); + goto exit; + } + + retry = true; + +retry: + LOCK_BUFFER(tcm_hcd->in); + + retval = syna_tcm_read(tcm_hcd, + tcm_hcd->in.buf, + tcm_hcd->read_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read from device\n"); + UNLOCK_BUFFER(tcm_hcd->in); + if (retry) { + usleep_range(READ_RETRY_US_MIN, READ_RETRY_US_MAX); + retry = false; + goto retry; + } + goto exit; + } + + header = (struct syna_tcm_message_header *)tcm_hcd->in.buf; + + if (header->marker != MESSAGE_MARKER) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect header marker (0x%02x)\n", + header->marker); + UNLOCK_BUFFER(tcm_hcd->in); + retval = -ENXIO; + if (retry) { + usleep_range(READ_RETRY_US_MIN, READ_RETRY_US_MAX); + retry = false; + goto retry; + } + goto exit; + } + + tcm_hcd->status_report_code = header->code; + + tcm_hcd->payload_length = le2_to_uint(header->length); + + LOGD(tcm_hcd->pdev->dev.parent, + "Header code = 0x%02x\n", + tcm_hcd->status_report_code); + + LOGD(tcm_hcd->pdev->dev.parent, + "Payload length = %d\n", + tcm_hcd->payload_length); + + if (tcm_hcd->status_report_code <= STATUS_ERROR || + tcm_hcd->status_report_code == STATUS_INVALID) { + switch (tcm_hcd->status_report_code) { + case STATUS_OK: + break; + case STATUS_CONTINUED_READ: + LOGD(tcm_hcd->pdev->dev.parent, + "Out-of-sync continued read\n"); + case STATUS_IDLE: + case STATUS_BUSY: + tcm_hcd->payload_length = 0; + UNLOCK_BUFFER(tcm_hcd->in); + retval = 0; + goto exit; + default: + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect header code (0x%02x)\n", + tcm_hcd->status_report_code); + if (tcm_hcd->status_report_code == STATUS_INVALID) { + if (retry) { + usleep_range(READ_RETRY_US_MIN, + READ_RETRY_US_MAX); + retry = false; + goto retry; + } else { + tcm_hcd->payload_length = 0; + } + } + } + } + + total_length = MESSAGE_HEADER_SIZE + tcm_hcd->payload_length + 1; + +#ifdef PREDICTIVE_READING + if (total_length <= tcm_hcd->read_length) { + goto check_padding; + } else if (total_length - 1 == tcm_hcd->read_length) { + tcm_hcd->in.buf[total_length - 1] = MESSAGE_PADDING; + goto check_padding; + } +#else + if (tcm_hcd->payload_length == 0) { + tcm_hcd->in.buf[total_length - 1] = MESSAGE_PADDING; + goto check_padding; + } +#endif + + UNLOCK_BUFFER(tcm_hcd->in); + + retval = syna_tcm_continued_read(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do continued read\n"); + goto exit; + }; + + LOCK_BUFFER(tcm_hcd->in); + + tcm_hcd->in.buf[0] = MESSAGE_MARKER; + tcm_hcd->in.buf[1] = tcm_hcd->status_report_code; + tcm_hcd->in.buf[2] = (unsigned char)tcm_hcd->payload_length; + tcm_hcd->in.buf[3] = (unsigned char)(tcm_hcd->payload_length >> 8); + +check_padding: + if (tcm_hcd->in.buf[total_length - 1] != MESSAGE_PADDING) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incorrect message padding byte (0x%02x)\n", + tcm_hcd->in.buf[total_length - 1]); + UNLOCK_BUFFER(tcm_hcd->in); + retval = -EIO; + goto exit; + } + + UNLOCK_BUFFER(tcm_hcd->in); + +#ifdef PREDICTIVE_READING + total_length = MAX(total_length, MIN_READ_LENGTH); + tcm_hcd->read_length = MIN(total_length, tcm_hcd->rd_chunk_size); + if (tcm_hcd->rd_chunk_size == 0) + tcm_hcd->read_length = total_length; +#endif + + syna_tcm_dispatch_message(tcm_hcd); + + retval = 0; + +exit: + if (retval < 0) { + if (atomic_read(&tcm_hcd->command_status) == CMD_BUSY) { + atomic_set(&tcm_hcd->command_status, CMD_ERROR); + complete(&response_complete); + } + } + + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + + return retval; +} + +/** + * syna_tcm_write_message() - write message to device and receive response + * + * @tcm_hcd: handle of core module + * @command: command to send to device + * @payload: payload of command + * @length: length of payload in bytes + * @resp_buf: buffer for storing command response + * @resp_buf_size: size of response buffer in bytes + * @resp_length: length of command response in bytes + * @response_code: status code returned in command response + * @polling_delay_ms: delay time after sending command before resuming polling + * + * If resp_buf is NULL, raw write mode is used and syna_tcm_raw_write() is + * called. Otherwise, a command and its payload, if any, are sent to the device + * and the response to the command generated by the device is read in. + */ +static int syna_tcm_write_message(struct syna_tcm_hcd *tcm_hcd, + unsigned char command, unsigned char *payload, + unsigned int length, unsigned char **resp_buf, + unsigned int *resp_buf_size, unsigned int *resp_length, + unsigned char *response_code, unsigned int polling_delay_ms) +{ + int retval; + unsigned int idx; + unsigned int chunks; + unsigned int chunk_space; + unsigned int xfer_length; + unsigned int remaining_length; + unsigned int command_status; + + if (response_code != NULL) + *response_code = STATUS_INVALID; + + if (!tcm_hcd->do_polling && current->pid == tcm_hcd->isr_pid) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid execution context\n"); + return -EINVAL; + } + + mutex_lock(&tcm_hcd->command_mutex); + + mutex_lock(&tcm_hcd->rw_ctrl_mutex); + + if (resp_buf == NULL) { + retval = syna_tcm_raw_write(tcm_hcd, command, payload, length); + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + goto exit; + } + + if (tcm_hcd->do_polling && polling_delay_ms) { + cancel_delayed_work_sync(&tcm_hcd->polling_work); + flush_workqueue(tcm_hcd->polling_workqueue); + } + + atomic_set(&tcm_hcd->command_status, CMD_BUSY); + + reinit_completion(&response_complete); + + tcm_hcd->command = command; + + LOCK_BUFFER(tcm_hcd->resp); + + tcm_hcd->resp.buf = *resp_buf; + tcm_hcd->resp.buf_size = *resp_buf_size; + tcm_hcd->resp.data_length = 0; + + UNLOCK_BUFFER(tcm_hcd->resp); + + /* adding two length bytes as part of payload */ + remaining_length = length + 2; + + /** + * available chunk space for payload = total chunk size minus command + * byte + */ + if (tcm_hcd->wr_chunk_size == 0) + chunk_space = remaining_length; + else + chunk_space = tcm_hcd->wr_chunk_size - 1; + + chunks = ceil_div(remaining_length, chunk_space); + + chunks = chunks == 0 ? 1 : chunks; + + LOGD(tcm_hcd->pdev->dev.parent, + "Command = 0x%02x\n", + command); + + LOCK_BUFFER(tcm_hcd->out); + + for (idx = 0; idx < chunks; idx++) { + if (remaining_length > chunk_space) + xfer_length = chunk_space; + else + xfer_length = remaining_length; + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->out, + xfer_length + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + UNLOCK_BUFFER(tcm_hcd->out); + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + goto exit; + } + + if (idx == 0) { + tcm_hcd->out.buf[0] = command; + tcm_hcd->out.buf[1] = (unsigned char)length; + tcm_hcd->out.buf[2] = (unsigned char)(length >> 8); + + if (xfer_length > 2) { + retval = secure_memcpy(&tcm_hcd->out.buf[3], + tcm_hcd->out.buf_size - 3, + payload, + remaining_length - 2, + xfer_length - 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy payload\n"); + UNLOCK_BUFFER(tcm_hcd->out); + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + goto exit; + } + } + } else { + tcm_hcd->out.buf[0] = CMD_CONTINUE_WRITE; + + retval = secure_memcpy(&tcm_hcd->out.buf[1], + tcm_hcd->out.buf_size - 1, + &payload[idx * chunk_space - 2], + remaining_length, + xfer_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy payload\n"); + UNLOCK_BUFFER(tcm_hcd->out); + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + goto exit; + } + } + + retval = syna_tcm_write(tcm_hcd, + tcm_hcd->out.buf, + xfer_length + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to device\n"); + UNLOCK_BUFFER(tcm_hcd->out); + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + goto exit; + } + + remaining_length -= xfer_length; + + if (chunks > 1) + usleep_range(WRITE_DELAY_US_MIN, WRITE_DELAY_US_MAX); + } + + UNLOCK_BUFFER(tcm_hcd->out); + + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + + if (tcm_hcd->do_polling && polling_delay_ms) { + queue_delayed_work(tcm_hcd->polling_workqueue, + &tcm_hcd->polling_work, + msecs_to_jiffies(polling_delay_ms)); + } + + retval = wait_for_completion_timeout(&response_complete, + msecs_to_jiffies(RESPONSE_TIMEOUT_MS)); + if (retval == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Timed out waiting for response (command 0x%02x)\n", + tcm_hcd->command); + retval = -EIO; + goto exit; + } + + command_status = atomic_read(&tcm_hcd->command_status); + if (command_status != CMD_IDLE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get valid response (command 0x%02x)\n", + tcm_hcd->command); + retval = -EIO; + goto exit; + } + + LOCK_BUFFER(tcm_hcd->resp); + + if (tcm_hcd->response_code != STATUS_OK) { + if (tcm_hcd->resp.data_length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Error code = 0x%02x (command 0x%02x)\n", + tcm_hcd->resp.buf[0], tcm_hcd->command); + } + retval = -EIO; + } else { + retval = 0; + } + + *resp_buf = tcm_hcd->resp.buf; + *resp_buf_size = tcm_hcd->resp.buf_size; + *resp_length = tcm_hcd->resp.data_length; + + if (response_code != NULL) + *response_code = tcm_hcd->response_code; + + UNLOCK_BUFFER(tcm_hcd->resp); + +exit: + tcm_hcd->command = CMD_NONE; + + atomic_set(&tcm_hcd->command_status, CMD_IDLE); + + mutex_unlock(&tcm_hcd->command_mutex); + + return retval; +} + +static int syna_tcm_wait_hdl(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + msleep(HOST_DOWNLOAD_WAIT_MS); + + if (!atomic_read(&tcm_hcd->host_downloading)) + return 0; + + retval = wait_event_interruptible_timeout(tcm_hcd->hdl_wq, + !atomic_read(&tcm_hcd->host_downloading), + msecs_to_jiffies(HOST_DOWNLOAD_TIMEOUT_MS)); + if (retval == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Timed out waiting for completion of host download\n"); + atomic_set(&tcm_hcd->host_downloading, 0); + retval = -EIO; + } else { + retval = 0; + } + + return retval; +} + +static void syna_tcm_check_hdl(struct syna_tcm_hcd *tcm_hcd) +{ + struct syna_tcm_module_handler *mod_handler; + + LOCK_BUFFER(tcm_hcd->report.buffer); + + tcm_hcd->report.buffer.buf = NULL; + tcm_hcd->report.buffer.buf_size = 0; + tcm_hcd->report.buffer.data_length = 0; + tcm_hcd->report.id = REPORT_HDL; + + UNLOCK_BUFFER(tcm_hcd->report.buffer); + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->syncbox)) + mod_handler->mod_cb->syncbox(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); +} + +static void syna_tcm_update_watchdog(struct syna_tcm_hcd *tcm_hcd, bool en) +{ + cancel_delayed_work_sync(&tcm_hcd->watchdog.work); + flush_workqueue(tcm_hcd->watchdog.workqueue); + + if (!tcm_hcd->watchdog.run) { + tcm_hcd->watchdog.count = 0; + return; + } + + if (en) { + queue_delayed_work(tcm_hcd->watchdog.workqueue, + &tcm_hcd->watchdog.work, + msecs_to_jiffies(WATCHDOG_DELAY_MS)); + } else { + tcm_hcd->watchdog.count = 0; + } +} + +static void syna_tcm_watchdog_work(struct work_struct *work) +{ + int retval; + unsigned char marker; + struct delayed_work *delayed_work = + container_of(work, struct delayed_work, work); + struct syna_tcm_watchdog *watchdog = + container_of(delayed_work, struct syna_tcm_watchdog, + work); + struct syna_tcm_hcd *tcm_hcd = + container_of(watchdog, struct syna_tcm_hcd, watchdog); + + if (mutex_is_locked(&tcm_hcd->rw_ctrl_mutex)) + goto exit; + + mutex_lock(&tcm_hcd->rw_ctrl_mutex); + + retval = syna_tcm_read(tcm_hcd, + &marker, + 1); + + mutex_unlock(&tcm_hcd->rw_ctrl_mutex); + + if (retval < 0 || marker != MESSAGE_MARKER) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read from device\n"); + + tcm_hcd->watchdog.count++; + + if (tcm_hcd->watchdog.count >= WATCHDOG_TRIGGER_COUNT) { + retval = tcm_hcd->reset(tcm_hcd, true, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + tcm_hcd->watchdog.count = 0; + } + } + +exit: + queue_delayed_work(tcm_hcd->watchdog.workqueue, + &tcm_hcd->watchdog.work, + msecs_to_jiffies(WATCHDOG_DELAY_MS)); +} + +static void syna_tcm_polling_work(struct work_struct *work) +{ + int retval; + struct delayed_work *delayed_work = + container_of(work, struct delayed_work, work); + struct syna_tcm_hcd *tcm_hcd = + container_of(delayed_work, struct syna_tcm_hcd, + polling_work); + + if (!tcm_hcd->do_polling) + return; + + retval = tcm_hcd->read_message(tcm_hcd, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read message\n"); + if (retval == -ENXIO && tcm_hcd->hw_if->bus_io->type == BUS_SPI) + syna_tcm_check_hdl(tcm_hcd); + } + + if (!(tcm_hcd->in_suspend && retval < 0)) { + queue_delayed_work(tcm_hcd->polling_workqueue, + &tcm_hcd->polling_work, + msecs_to_jiffies(POLLING_DELAY_MS)); + } +} + +static irqreturn_t syna_tcm_isr(int irq, void *data) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = data; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (unlikely(gpio_get_value(bdata->irq_gpio) != bdata->irq_on_state)) + goto exit; + + tcm_hcd->isr_pid = current->pid; + + retval = tcm_hcd->read_message(tcm_hcd, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, "Failed to read message\n"); + if (retval == -ENXIO && + tcm_hcd->hw_if->bus_io->type == BUS_SPI) + syna_tcm_check_hdl(tcm_hcd); + } + +exit: + return IRQ_HANDLED; +} + +static int syna_tcm_enable_irq(struct syna_tcm_hcd *tcm_hcd, bool en, bool ns) +{ + int retval; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + static bool irq_freed = true; + + mutex_lock(&tcm_hcd->irq_en_mutex); + + if (en) { + if (tcm_hcd->irq_enabled) { + LOGD(tcm_hcd->pdev->dev.parent, + "Interrupt already enabled\n"); + retval = 0; + goto exit; + } + + if (bdata->irq_gpio < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid IRQ GPIO\n"); + retval = -EINVAL; + goto queue_polling_work; + } + + if (irq_freed) { + retval = request_threaded_irq(tcm_hcd->irq, NULL, + syna_tcm_isr, bdata->irq_flags, + PLATFORM_DRIVER_NAME, tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create interrupt thread\n"); + } + } else { + enable_irq(tcm_hcd->irq); + retval = 0; + } + +queue_polling_work: + if (retval < 0) { +#ifdef FALL_BACK_ON_POLLING + queue_delayed_work(tcm_hcd->polling_workqueue, + &tcm_hcd->polling_work, + msecs_to_jiffies(POLLING_DELAY_MS)); + tcm_hcd->do_polling = true; + retval = 0; +#endif + } + + if (retval < 0) + goto exit; + else + msleep(ENABLE_IRQ_DELAY_MS); + } else { + if (!tcm_hcd->irq_enabled) { + LOGD(tcm_hcd->pdev->dev.parent, + "Interrupt already disabled\n"); + retval = 0; + goto exit; + } + + if (bdata->irq_gpio >= 0) { + if (ns) { + disable_irq_nosync(tcm_hcd->irq); + } else { + disable_irq(tcm_hcd->irq); + free_irq(tcm_hcd->irq, tcm_hcd); + } + irq_freed = !ns; + } + + if (ns) { + cancel_delayed_work(&tcm_hcd->polling_work); + } else { + cancel_delayed_work_sync(&tcm_hcd->polling_work); + flush_workqueue(tcm_hcd->polling_workqueue); + } + + tcm_hcd->do_polling = false; + } + + retval = 0; + +exit: + if (retval == 0) + tcm_hcd->irq_enabled = en; + + mutex_unlock(&tcm_hcd->irq_en_mutex); + + return retval; +} + +static int syna_tcm_set_gpio(struct syna_tcm_hcd *tcm_hcd, int gpio, + bool config, int dir, int state) +{ + int retval; + char label[16]; + + if (config) { + retval = snprintf(label, 16, "tcm_gpio_%d\n", gpio); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set GPIO label\n"); + return retval; + } + + retval = gpio_request(gpio, label); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to request GPIO %d\n", + gpio); + return retval; + } + + if (dir == 0) + retval = gpio_direction_input(gpio); + else + retval = gpio_direction_output(gpio, state); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set GPIO %d direction\n", + gpio); + return retval; + } + } else { + gpio_free(gpio); + } + + return 0; +} + +static int syna_tcm_config_gpio(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (bdata->irq_gpio >= 0) { + retval = syna_tcm_set_gpio(tcm_hcd, bdata->irq_gpio, + true, 0, 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to configure interrupt GPIO\n"); + goto err_set_gpio_irq; + } + } + + if (bdata->power_gpio >= 0) { + retval = syna_tcm_set_gpio(tcm_hcd, bdata->power_gpio, + true, 1, !bdata->power_on_state); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to configure power GPIO\n"); + goto err_set_gpio_power; + } + } + + if (bdata->reset_gpio >= 0) { + retval = syna_tcm_set_gpio(tcm_hcd, bdata->reset_gpio, + true, 1, !bdata->reset_on_state); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to configure reset GPIO\n"); + goto err_set_gpio_reset; + } + } + + if (bdata->power_gpio >= 0) { + gpio_set_value(bdata->power_gpio, bdata->power_on_state); + msleep(bdata->power_delay_ms); + } + + if (bdata->reset_gpio >= 0) { + gpio_set_value(bdata->reset_gpio, bdata->reset_on_state); + msleep(bdata->reset_active_ms); + gpio_set_value(bdata->reset_gpio, !bdata->reset_on_state); + msleep(bdata->reset_delay_ms); + } + + return 0; + +err_set_gpio_reset: + if (bdata->power_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->power_gpio, false, 0, 0); + +err_set_gpio_power: + if (bdata->irq_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->irq_gpio, false, 0, 0); + +err_set_gpio_irq: + return retval; +} + +static int syna_tcm_enable_regulator(struct syna_tcm_hcd *tcm_hcd, bool en) +{ + int retval; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (!en) { + retval = 0; + goto disable_pwr_reg; + } + + if (tcm_hcd->bus_reg) { + retval = regulator_enable(tcm_hcd->bus_reg); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable bus regulator\n"); + goto exit; + } + } + + if (tcm_hcd->pwr_reg) { + retval = regulator_enable(tcm_hcd->pwr_reg); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable power regulator\n"); + goto disable_bus_reg; + } + msleep(bdata->power_delay_ms); + } + + return 0; + +disable_pwr_reg: + if (tcm_hcd->pwr_reg) + regulator_disable(tcm_hcd->pwr_reg); + +disable_bus_reg: + if (tcm_hcd->bus_reg) + regulator_disable(tcm_hcd->bus_reg); + +exit: + return retval; +} + +static int syna_tcm_get_regulator(struct syna_tcm_hcd *tcm_hcd, bool get) +{ + int retval; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (!get) { + retval = 0; + goto regulator_put; + } + + if (bdata->bus_reg_name != NULL && *bdata->bus_reg_name != 0) { + tcm_hcd->bus_reg = regulator_get(tcm_hcd->pdev->dev.parent, + bdata->bus_reg_name); + if (IS_ERR(tcm_hcd->bus_reg)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get bus regulator\n"); + retval = PTR_ERR(tcm_hcd->bus_reg); + goto regulator_put; + } + } + + if (bdata->pwr_reg_name != NULL && *bdata->pwr_reg_name != 0) { + tcm_hcd->pwr_reg = regulator_get(tcm_hcd->pdev->dev.parent, + bdata->pwr_reg_name); + if (IS_ERR(tcm_hcd->pwr_reg)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get power regulator\n"); + retval = PTR_ERR(tcm_hcd->pwr_reg); + goto regulator_put; + } + } + + return 0; + +regulator_put: + if (tcm_hcd->bus_reg) { + regulator_put(tcm_hcd->bus_reg); + tcm_hcd->bus_reg = NULL; + } + + if (tcm_hcd->pwr_reg) { + regulator_put(tcm_hcd->pwr_reg); + tcm_hcd->pwr_reg = NULL; + } + + return retval; +} + +static int syna_tcm_get_app_info(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + unsigned int timeout; + + timeout = APP_STATUS_POLL_TIMEOUT_MS; + + resp_buf = NULL; + resp_buf_size = 0; + +get_app_info: + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_APPLICATION_INFO, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_APPLICATION_INFO)); + goto exit; + } + + retval = secure_memcpy((unsigned char *)&tcm_hcd->app_info, + sizeof(tcm_hcd->app_info), + resp_buf, + resp_buf_size, + MIN(sizeof(tcm_hcd->app_info), resp_length)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy application info\n"); + goto exit; + } + + tcm_hcd->app_status = le2_to_uint(tcm_hcd->app_info.status); + + if (tcm_hcd->app_status == APP_STATUS_BOOTING || + tcm_hcd->app_status == APP_STATUS_UPDATING) { + if (timeout > 0) { + msleep(APP_STATUS_POLL_MS); + timeout -= APP_STATUS_POLL_MS; + goto get_app_info; + } + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_get_boot_info(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + resp_buf = NULL; + resp_buf_size = 0; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_BOOT_INFO, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_BOOT_INFO)); + goto exit; + } + + retval = secure_memcpy((unsigned char *)&tcm_hcd->boot_info, + sizeof(tcm_hcd->boot_info), + resp_buf, + resp_buf_size, + MIN(sizeof(tcm_hcd->boot_info), resp_length)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy boot info\n"); + goto exit; + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_identify(struct syna_tcm_hcd *tcm_hcd, bool id) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + unsigned int max_write_size; + + resp_buf = NULL; + resp_buf_size = 0; + + mutex_lock(&tcm_hcd->identify_mutex); + + if (!id) + goto get_info; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_IDENTIFY, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_IDENTIFY)); + goto exit; + } + + retval = secure_memcpy((unsigned char *)&tcm_hcd->id_info, + sizeof(tcm_hcd->id_info), + resp_buf, + resp_buf_size, + MIN(sizeof(tcm_hcd->id_info), resp_length)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy identification info\n"); + goto exit; + } + + tcm_hcd->packrat_number = le4_to_uint(tcm_hcd->id_info.build_id); + + max_write_size = le2_to_uint(tcm_hcd->id_info.max_write_size); + tcm_hcd->wr_chunk_size = MIN(max_write_size, WR_CHUNK_SIZE); + if (tcm_hcd->wr_chunk_size == 0) + tcm_hcd->wr_chunk_size = max_write_size; + +get_info: + switch (tcm_hcd->id_info.mode) { + case MODE_APPLICATION: + retval = syna_tcm_get_app_info(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get application info\n"); + goto exit; + } + break; + case MODE_BOOTLOADER: + case MODE_TDDI_BOOTLOADER: + retval = syna_tcm_get_boot_info(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get boot info\n"); + goto exit; + } + break; + default: + break; + } + + retval = 0; + +exit: + mutex_unlock(&tcm_hcd->identify_mutex); + + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_run_production_test_firmware(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + bool retry; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + retry = true; + + resp_buf = NULL; + resp_buf_size = 0; + +retry: + retval = tcm_hcd->write_message(tcm_hcd, + CMD_ENTER_PRODUCTION_TEST_MODE, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + MODE_SWITCH_DELAY_MS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_ENTER_PRODUCTION_TEST_MODE)); + goto exit; + } + + if (tcm_hcd->id_info.mode != MODE_PRODUCTION_TEST) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run production test firmware\n"); + if (retry) { + retry = false; + goto retry; + } + retval = -EINVAL; + goto exit; + } else if (tcm_hcd->app_status != APP_STATUS_OK) { + LOGE(tcm_hcd->pdev->dev.parent, + "Application status = 0x%02x\n", + tcm_hcd->app_status); + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_run_application_firmware(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + bool retry; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + retry = true; + + resp_buf = NULL; + resp_buf_size = 0; + +retry: + retval = tcm_hcd->write_message(tcm_hcd, + CMD_RUN_APPLICATION_FIRMWARE, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + MODE_SWITCH_DELAY_MS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_RUN_APPLICATION_FIRMWARE)); + goto exit; + } + + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto exit; + } + + if (tcm_hcd->id_info.mode != MODE_APPLICATION) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application (status = 0x%02x)\n", + tcm_hcd->boot_info.status); + if (retry) { + retry = false; + goto retry; + } + retval = -EINVAL; + goto exit; + } else if (tcm_hcd->app_status != APP_STATUS_OK) { + LOGE(tcm_hcd->pdev->dev.parent, + "Application status = 0x%02x\n", + tcm_hcd->app_status); + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_run_bootloader_firmware(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + resp_buf = NULL; + resp_buf_size = 0; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_RUN_BOOTLOADER_FIRMWARE, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + MODE_SWITCH_DELAY_MS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_RUN_BOOTLOADER_FIRMWARE)); + goto exit; + } + + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto exit; + } + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter bootloader mode\n"); + retval = -EINVAL; + goto exit; + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_switch_mode(struct syna_tcm_hcd *tcm_hcd, + enum firmware_mode mode) +{ + int retval; + + mutex_lock(&tcm_hcd->reset_mutex); + + tcm_hcd->update_watchdog(tcm_hcd, false); + + switch (mode) { + case FW_MODE_BOOTLOADER: + retval = syna_tcm_run_bootloader_firmware(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to switch to bootloader mode\n"); + goto exit; + } + break; + case FW_MODE_APPLICATION: + retval = syna_tcm_run_application_firmware(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to switch to application mode\n"); + goto exit; + } + break; + case FW_MODE_PRODUCTION_TEST: + retval = syna_tcm_run_production_test_firmware(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to switch to production test mode\n"); + goto exit; + } + break; + default: + LOGE(tcm_hcd->pdev->dev.parent, "Invalid firmware mode\n"); + retval = -EINVAL; + goto exit; + } + + retval = 0; + +exit: + tcm_hcd->update_watchdog(tcm_hcd, true); + + mutex_unlock(&tcm_hcd->reset_mutex); + + return retval; +} + +static int syna_tcm_get_dynamic_config(struct syna_tcm_hcd *tcm_hcd, + enum dynamic_config_id id, unsigned short *value) +{ + int retval; + unsigned char out_buf; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + resp_buf = NULL; + resp_buf_size = 0; + + out_buf = (unsigned char)id; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_DYNAMIC_CONFIG, + &out_buf, + sizeof(out_buf), + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_DYNAMIC_CONFIG)); + goto exit; + } + + if (resp_length < 2) { + LOGE(tcm_hcd->pdev->dev.parent, "Invalid data length\n"); + retval = -EINVAL; + goto exit; + } + + *value = (unsigned short)le2_to_uint(resp_buf); + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_set_dynamic_config(struct syna_tcm_hcd *tcm_hcd, + enum dynamic_config_id id, unsigned short value) +{ + int retval; + unsigned char out_buf[3]; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + resp_buf = NULL; + resp_buf_size = 0; + + out_buf[0] = (unsigned char)id; + out_buf[1] = (unsigned char)value; + out_buf[2] = (unsigned char)(value >> 8); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_SET_DYNAMIC_CONFIG, + out_buf, + sizeof(out_buf), + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_SET_DYNAMIC_CONFIG)); + goto exit; + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_get_data_location(struct syna_tcm_hcd *tcm_hcd, + enum flash_area area, unsigned int *addr, unsigned int *length) +{ + int retval; + unsigned char out_buf; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + switch (area) { + case CUSTOM_LCM: + out_buf = LCM_DATA; + break; + case CUSTOM_OEM: + out_buf = OEM_DATA; + break; + case PPDT: + out_buf = PPDT_DATA; + break; + default: + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid flash area\n"); + return -EINVAL; + } + + resp_buf = NULL; + resp_buf_size = 0; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_DATA_LOCATION, + &out_buf, + sizeof(out_buf), + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_DATA_LOCATION)); + goto exit; + } + + if (resp_length != 4) { + LOGE(tcm_hcd->pdev->dev.parent, "Invalid data length\n"); + retval = -EINVAL; + goto exit; + } + + *addr = le2_to_uint(&resp_buf[0]); + *length = le2_to_uint(&resp_buf[2]); + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_sleep(struct syna_tcm_hcd *tcm_hcd, bool en) +{ + int retval; + unsigned char command; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + command = en ? CMD_ENTER_DEEP_SLEEP : CMD_EXIT_DEEP_SLEEP; + + resp_buf = NULL; + resp_buf_size = 0; + + retval = tcm_hcd->write_message(tcm_hcd, + command, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + en ? + STR(CMD_ENTER_DEEP_SLEEP) : + STR(CMD_EXIT_DEEP_SLEEP)); + goto exit; + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_reset(struct syna_tcm_hcd *tcm_hcd, bool hw, bool update_wd) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + struct syna_tcm_module_handler *mod_handler; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + resp_buf = NULL; + resp_buf_size = 0; + + mutex_lock(&tcm_hcd->reset_mutex); + + if (update_wd) + tcm_hcd->update_watchdog(tcm_hcd, false); + + if (hw) { + if (bdata->reset_gpio < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Hardware reset unavailable\n"); + retval = -EINVAL; + goto exit; + } + gpio_set_value(bdata->reset_gpio, bdata->reset_on_state); + msleep(bdata->reset_active_ms); + gpio_set_value(bdata->reset_gpio, !bdata->reset_on_state); + } else { + retval = tcm_hcd->write_message(tcm_hcd, + CMD_RESET, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + bdata->reset_delay_ms); + if (retval < 0 && !tcm_hcd->host_download_mode) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_RESET)); + goto exit; + } + } + + if (tcm_hcd->host_download_mode) { + mutex_unlock(&tcm_hcd->reset_mutex); + kfree(resp_buf); + retval = syna_tcm_wait_hdl(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to wait for completion of download\n"); + return retval; + } + if (update_wd) + tcm_hcd->update_watchdog(tcm_hcd, true); + return 0; + } + + msleep(bdata->reset_delay_ms); + + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto exit; + } + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) + goto get_features; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_RUN_APPLICATION_FIRMWARE, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + MODE_SWITCH_DELAY_MS); + if (retval < 0) { + LOGN(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_RUN_APPLICATION_FIRMWARE)); + } + + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto exit; + } + +get_features: + LOGN(tcm_hcd->pdev->dev.parent, + "Firmware mode = 0x%02x\n", + tcm_hcd->id_info.mode); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION) { + LOGN(tcm_hcd->pdev->dev.parent, + "Boot status = 0x%02x\n", + tcm_hcd->boot_info.status); + } else if (tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application status = 0x%02x\n", + tcm_hcd->app_status); + } + + if (tcm_hcd->id_info.mode != MODE_APPLICATION) + goto dispatch_reset; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_FEATURES, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) + LOGN(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_FEATURES)); + else { + retval = secure_memcpy((unsigned char *)&tcm_hcd->features, + sizeof(tcm_hcd->features), + resp_buf, + resp_buf_size, + MIN(sizeof(tcm_hcd->features), resp_length)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy feature description\n"); + } + } + +dispatch_reset: + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->reset)) + mod_handler->mod_cb->reset(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + + retval = 0; + +exit: + if (update_wd) + tcm_hcd->update_watchdog(tcm_hcd, true); + + mutex_unlock(&tcm_hcd->reset_mutex); + + kfree(resp_buf); + + return retval; +} + +static int syna_tcm_rezero(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *resp_buf; + unsigned int resp_buf_size; + unsigned int resp_length; + + resp_buf = NULL; + resp_buf_size = 0; + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_REZERO, + NULL, + 0, + &resp_buf, + &resp_buf_size, + &resp_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_REZERO)); + goto exit; + } + + retval = 0; + +exit: + kfree(resp_buf); + + return retval; +} + +static void syna_tcm_helper_work(struct work_struct *work) +{ + int retval; + unsigned char task; + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_helper *helper = + container_of(work, struct syna_tcm_helper, work); + struct syna_tcm_hcd *tcm_hcd = + container_of(helper, struct syna_tcm_hcd, helper); + + task = atomic_read(&helper->task); + + switch (task) { + case HELP_RUN_APPLICATION_FIRMWARE: + mutex_lock(&tcm_hcd->reset_mutex); + tcm_hcd->update_watchdog(tcm_hcd, false); + retval = syna_tcm_run_application_firmware(tcm_hcd); + if (retval < 0) + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to switch to application mode\n"); + tcm_hcd->update_watchdog(tcm_hcd, true); + mutex_unlock(&tcm_hcd->reset_mutex); + break; + case HELP_SEND_RESET_NOTIFICATION: + mutex_lock(&tcm_hcd->reset_mutex); + retval = tcm_hcd->identify(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + mutex_unlock(&tcm_hcd->reset_mutex); + break; + } + mutex_lock(&mod_pool.mutex); + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->reset)) + mod_handler->mod_cb->reset(tcm_hcd); + } + } + mutex_unlock(&mod_pool.mutex); + mutex_unlock(&tcm_hcd->reset_mutex); + wake_up_interruptible(&tcm_hcd->hdl_wq); + break; + default: + break; + } + + atomic_set(&helper->task, HELP_NONE); +} + +#if defined(CONFIG_PM) || defined(CONFIG_DRM) || defined(CONFIG_FB) + +static int syna_tcm_deferred_probe(struct device *dev); + +static int syna_tcm_resume(struct device *dev) +{ + int retval; + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = dev_get_drvdata(dev); + + if (!tcm_hcd->init_okay) + syna_tcm_deferred_probe(dev); + + if (!tcm_hcd->in_suspend) + return 0; + + if (tcm_hcd->host_download_mode) { +#ifndef WAKEUP_GESTURE + syna_tcm_check_hdl(tcm_hcd); + retval = syna_tcm_wait_hdl(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to wait for completion of download\n"); + goto exit; + } +#endif + } else { + tcm_hcd->enable_irq(tcm_hcd, true, NULL); +#ifdef RESET_ON_RESUME + msleep(RESET_ON_RESUME_DELAY_MS); + goto do_reset; +#endif + } + + tcm_hcd->update_watchdog(tcm_hcd, true); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + goto do_reset; + } + + retval = tcm_hcd->sleep(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to exit deep sleep\n"); + goto exit; + } + + retval = syna_tcm_rezero(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to rezero\n"); + goto exit; + } + + goto mod_resume; + +do_reset: + retval = tcm_hcd->reset(tcm_hcd, false, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + goto exit; + } + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + retval = 0; + goto exit; + } + +mod_resume: + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->resume)) + mod_handler->mod_cb->resume(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + + retval = 0; + +exit: + tcm_hcd->in_suspend = false; + + return retval; +} + +static int syna_tcm_suspend(struct device *dev) +{ + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = dev_get_drvdata(dev); + + if (tcm_hcd->in_suspend || !tcm_hcd->init_okay) + return 0; + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->suspend)) + mod_handler->mod_cb->suspend(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + +#ifndef WAKEUP_GESTURE + tcm_hcd->enable_irq(tcm_hcd, false, true); +#endif + + tcm_hcd->in_suspend = true; + + return 0; +} +#endif + + + +#ifdef CONFIG_DRM + +static int syna_tcm_early_suspend(struct device *dev) +{ +#ifndef WAKEUP_GESTURE + int retval; +#endif + + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = dev_get_drvdata(dev); + + if (tcm_hcd->in_suspend || !tcm_hcd->init_okay) + return 0; + + tcm_hcd->update_watchdog(tcm_hcd, false); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + return 0; + } + +#ifndef WAKEUP_GESTURE + retval = tcm_hcd->sleep(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter deep sleep\n"); + return retval; + } +#endif + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->early_suspend)) + mod_handler->mod_cb->early_suspend(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + + return 0; +} + +static int syna_tcm_fb_notifier_cb(struct notifier_block *nb, + unsigned long action, void *data) +{ + int retval = 0; + int *transition; + struct msm_drm_notifier *evdata = data; + struct syna_tcm_hcd *tcm_hcd = + container_of(nb, struct syna_tcm_hcd, fb_notifier); + + if (!evdata || (evdata->id != 0)) + return 0; + + if (evdata && evdata->data && tcm_hcd) { + transition = (int *) evdata->data; + if (action == MSM_DRM_EARLY_EVENT_BLANK && + *transition == MSM_DRM_BLANK_POWERDOWN) + retval = syna_tcm_early_suspend(&tcm_hcd->pdev->dev); + else if (action == MSM_DRM_EVENT_BLANK) { + if (*transition == MSM_DRM_BLANK_POWERDOWN) { + retval = syna_tcm_suspend(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready = 0; + } else if (*transition == MSM_DRM_BLANK_UNBLANK) { +#ifndef RESUME_EARLY_UNBLANK + retval = syna_tcm_resume(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready++; +#endif + } + } else if (action == MSM_DRM_EARLY_EVENT_BLANK && + *transition == MSM_DRM_BLANK_UNBLANK) { +#ifdef RESUME_EARLY_UNBLANK + retval = syna_tcm_resume(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready++; +#endif + } + } + + return 0; +} + +#elif CONFIG_FB + +static int syna_tcm_early_suspend(struct device *dev) +{ +#ifndef WAKEUP_GESTURE + int retval; +#endif + + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = dev_get_drvdata(dev); + + if (tcm_hcd->in_suspend) + return 0; + + tcm_hcd->update_watchdog(tcm_hcd, false); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + return 0; + } + +#ifndef WAKEUP_GESTURE + retval = tcm_hcd->sleep(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter deep sleep\n"); + return retval; + } +#endif + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (!mod_handler->insert && + !mod_handler->detach && + (mod_handler->mod_cb->early_suspend)) + mod_handler->mod_cb->early_suspend(tcm_hcd); + } + } + + mutex_unlock(&mod_pool.mutex); + + return 0; +} + +static int syna_tcm_fb_notifier_cb(struct notifier_block *nb, + unsigned long action, void *data) +{ + int retval; + int *transition; + struct fb_event *evdata = data; + struct syna_tcm_hcd *tcm_hcd = + container_of(nb, struct syna_tcm_hcd, fb_notifier); + + retval = 0; + + if (evdata && evdata->data && tcm_hcd) { + transition = (int *)evdata->data; + if (action == FB_EARLY_EVENT_BLANK && + *transition == FB_BLANK_POWERDOWN) + retval = syna_tcm_early_suspend(&tcm_hcd->pdev->dev); + else if (action == FB_EVENT_BLANK) { + if (*transition == FB_BLANK_POWERDOWN) { + retval = syna_tcm_suspend(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready = 0; + } else if (*transition == FB_BLANK_UNBLANK) { +#ifndef RESUME_EARLY_UNBLANK + retval = syna_tcm_resume(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready++; +#endif + } + } else if (action == FB_EARLY_EVENT_BLANK && + *transition == FB_BLANK_UNBLANK) { +#ifdef RESUME_EARLY_UNBLANK + retval = syna_tcm_resume(&tcm_hcd->pdev->dev); + tcm_hcd->fb_ready++; +#endif + } + } + + return 0; +} +#endif + +static int syna_tcm_probe(struct platform_device *pdev) +{ + int retval; + int idx; + struct syna_tcm_hcd *tcm_hcd; + const struct syna_tcm_board_data *bdata; + const struct syna_tcm_hw_interface *hw_if; + + hw_if = pdev->dev.platform_data; + if (!hw_if) { + LOGE(&pdev->dev, + "Hardware interface not found\n"); + return -ENODEV; + } + + bdata = hw_if->bdata; + if (!bdata) { + LOGE(&pdev->dev, + "Board data not found\n"); + return -ENODEV; + } + + tcm_hcd = kzalloc(sizeof(*tcm_hcd), GFP_KERNEL); + if (!tcm_hcd) { + LOGE(&pdev->dev, + "Failed to allocate memory for tcm_hcd\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, tcm_hcd); + + tcm_hcd->pdev = pdev; + tcm_hcd->hw_if = hw_if; + tcm_hcd->reset = syna_tcm_reset; + tcm_hcd->sleep = syna_tcm_sleep; + tcm_hcd->identify = syna_tcm_identify; + tcm_hcd->enable_irq = syna_tcm_enable_irq; + tcm_hcd->switch_mode = syna_tcm_switch_mode; + tcm_hcd->read_message = syna_tcm_read_message; + tcm_hcd->write_message = syna_tcm_write_message; + tcm_hcd->get_dynamic_config = syna_tcm_get_dynamic_config; + tcm_hcd->set_dynamic_config = syna_tcm_set_dynamic_config; + tcm_hcd->get_data_location = syna_tcm_get_data_location; + + tcm_hcd->rd_chunk_size = RD_CHUNK_SIZE; + tcm_hcd->wr_chunk_size = WR_CHUNK_SIZE; + +#ifdef PREDICTIVE_READING + tcm_hcd->read_length = MIN_READ_LENGTH; +#else + tcm_hcd->read_length = MESSAGE_HEADER_SIZE; +#endif + + tcm_hcd->watchdog.run = RUN_WATCHDOG; + tcm_hcd->update_watchdog = syna_tcm_update_watchdog; + + if (bdata->irq_gpio >= 0) + tcm_hcd->irq = gpio_to_irq(bdata->irq_gpio); + else + tcm_hcd->irq = bdata->irq_gpio; + + mutex_init(&tcm_hcd->extif_mutex); + mutex_init(&tcm_hcd->reset_mutex); + mutex_init(&tcm_hcd->irq_en_mutex); + mutex_init(&tcm_hcd->io_ctrl_mutex); + mutex_init(&tcm_hcd->rw_ctrl_mutex); + mutex_init(&tcm_hcd->command_mutex); + mutex_init(&tcm_hcd->identify_mutex); + + INIT_BUFFER(tcm_hcd->in, false); + INIT_BUFFER(tcm_hcd->out, false); + INIT_BUFFER(tcm_hcd->resp, true); + INIT_BUFFER(tcm_hcd->temp, false); + INIT_BUFFER(tcm_hcd->config, false); + INIT_BUFFER(tcm_hcd->report.buffer, true); + + LOCK_BUFFER(tcm_hcd->in); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->in, + tcm_hcd->read_length + 1); + if (retval < 0) { + LOGE(&pdev->dev, + "Failed to allocate memory for tcm_hcd->in.buf\n"); + UNLOCK_BUFFER(tcm_hcd->in); + goto err_alloc_mem; + } + + UNLOCK_BUFFER(tcm_hcd->in); + + atomic_set(&tcm_hcd->command_status, CMD_IDLE); + + atomic_set(&tcm_hcd->helper.task, HELP_NONE); + + device_init_wakeup(&pdev->dev, 1); + + init_waitqueue_head(&tcm_hcd->hdl_wq); + + if (!mod_pool.initialized) { + mutex_init(&mod_pool.mutex); + INIT_LIST_HEAD(&mod_pool.list); + mod_pool.initialized = true; + } + + retval = syna_tcm_get_regulator(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get regulators\n"); + goto err_get_regulator; + } + + retval = syna_tcm_enable_regulator(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable regulators\n"); + goto err_enable_regulator; + } + + retval = syna_tcm_config_gpio(tcm_hcd); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to configure GPIO's\n"); + goto err_config_gpio; + } + + sysfs_dir = kobject_create_and_add(PLATFORM_DRIVER_NAME, + &pdev->dev.kobj); + if (!sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dir; + } + + tcm_hcd->sysfs_dir = sysfs_dir; + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + retval = sysfs_create_file(tcm_hcd->sysfs_dir, + &(*attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs file\n"); + goto err_sysfs_create_file; + } + } + + tcm_hcd->dynamnic_config_sysfs_dir = + kobject_create_and_add(DYNAMIC_CONFIG_SYSFS_DIR_NAME, + tcm_hcd->sysfs_dir); + if (!tcm_hcd->dynamnic_config_sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create dynamic config sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dynamic_config_dir; + } + + for (idx = 0; idx < ARRAY_SIZE(dynamic_config_attrs); idx++) { + retval = sysfs_create_file(tcm_hcd->dynamnic_config_sysfs_dir, + &(*dynamic_config_attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create dynamic config sysfs file\n"); + goto err_sysfs_create_dynamic_config_file; + } + } + +#ifdef CONFIG_DRM + tcm_hcd->fb_notifier.notifier_call = syna_tcm_fb_notifier_cb; + retval = msm_drm_register_client(&tcm_hcd->fb_notifier); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to register DRM notifier client\n"); + } +#elif CONFIG_FB + tcm_hcd->fb_notifier.notifier_call = syna_tcm_fb_notifier_cb; + retval = fb_register_client(&tcm_hcd->fb_notifier); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to register FB notifier client\n"); + } +#endif + + tcm_hcd->notifier_thread = kthread_run(syna_tcm_report_notifier, + tcm_hcd, "syna_tcm_report_notifier"); + if (IS_ERR(tcm_hcd->notifier_thread)) { + retval = PTR_ERR(tcm_hcd->notifier_thread); + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create and run tcm_hcd->notifier_thread\n"); + goto err_create_run_kthread; + } + + tcm_hcd->helper.workqueue = + create_singlethread_workqueue("syna_tcm_helper"); + INIT_WORK(&tcm_hcd->helper.work, syna_tcm_helper_work); + + tcm_hcd->watchdog.workqueue = + create_singlethread_workqueue("syna_tcm_watchdog"); + INIT_DELAYED_WORK(&tcm_hcd->watchdog.work, syna_tcm_watchdog_work); + + tcm_hcd->polling_workqueue = + create_singlethread_workqueue("syna_tcm_polling"); + INIT_DELAYED_WORK(&tcm_hcd->polling_work, syna_tcm_polling_work); + + mod_pool.workqueue = + create_singlethread_workqueue("syna_tcm_module"); + INIT_WORK(&mod_pool.work, syna_tcm_module_work); + mod_pool.tcm_hcd = tcm_hcd; + mod_pool.queue_work = true; + + return 0; + + +err_create_run_kthread: +#ifdef CONFIG_DRM + msm_drm_unregister_client(&tcm_hcd->fb_notifier); +#elif CONFIG_FB + fb_unregister_client(&tcm_hcd->fb_notifier); +#endif + +err_sysfs_create_dynamic_config_file: + for (idx--; idx >= 0; idx--) { + sysfs_remove_file(tcm_hcd->dynamnic_config_sysfs_dir, + &(*dynamic_config_attrs[idx]).attr); + } + + kobject_put(tcm_hcd->dynamnic_config_sysfs_dir); + + idx = ARRAY_SIZE(attrs); + +err_sysfs_create_dynamic_config_dir: +err_sysfs_create_file: + for (idx--; idx >= 0; idx--) + sysfs_remove_file(tcm_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(tcm_hcd->sysfs_dir); + +err_sysfs_create_dir: + if (bdata->irq_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->irq_gpio, false, 0, 0); + + if (bdata->power_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->power_gpio, false, 0, 0); + + if (bdata->reset_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->reset_gpio, false, 0, 0); + +err_config_gpio: + syna_tcm_enable_regulator(tcm_hcd, false); + +err_enable_regulator: + syna_tcm_get_regulator(tcm_hcd, false); + +err_get_regulator: + device_init_wakeup(&pdev->dev, 0); + +err_alloc_mem: + RELEASE_BUFFER(tcm_hcd->report.buffer); + RELEASE_BUFFER(tcm_hcd->config); + RELEASE_BUFFER(tcm_hcd->temp); + RELEASE_BUFFER(tcm_hcd->resp); + RELEASE_BUFFER(tcm_hcd->out); + RELEASE_BUFFER(tcm_hcd->in); + + kfree(tcm_hcd); + + return retval; +} + +static int syna_tcm_deferred_probe(struct device *dev) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = dev_get_drvdata(dev); + + retval = tcm_hcd->enable_irq(tcm_hcd, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable interrupt\n"); + goto err_enable_irq; + } + retval = tcm_hcd->reset(tcm_hcd, false, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + tcm_hcd->init_okay = false; + tcm_hcd->watchdog.run = false; + tcm_hcd->update_watchdog(tcm_hcd, false); + tcm_hcd->enable_irq(tcm_hcd, false, false); +#ifndef KEEP_DRIVER_ON_ERROR + goto err_reset; +#endif + } else { + tcm_hcd->init_okay = true; + tcm_hcd->update_watchdog(tcm_hcd, true); + } + + queue_work(mod_pool.workqueue, &mod_pool.work); + + return 0; +#ifndef KEEP_DRIVER_ON_ERROR +err_reset: +#endif +err_enable_irq: + return retval; +} + + +static int syna_tcm_remove(struct platform_device *pdev) +{ + int idx; + struct syna_tcm_module_handler *mod_handler; + struct syna_tcm_hcd *tcm_hcd = platform_get_drvdata(pdev); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&mod_pool.mutex); + + if (!list_empty(&mod_pool.list)) { + list_for_each_entry(mod_handler, &mod_pool.list, link) { + if (mod_handler->mod_cb->remove) + mod_handler->mod_cb->remove(tcm_hcd); + list_del(&mod_handler->link); + kfree(mod_handler); + } + } + + mod_pool.queue_work = false; + cancel_work_sync(&mod_pool.work); + flush_workqueue(mod_pool.workqueue); + destroy_workqueue(mod_pool.workqueue); + + mutex_unlock(&mod_pool.mutex); + + if (tcm_hcd->irq_enabled && bdata->irq_gpio >= 0) { + disable_irq(tcm_hcd->irq); + free_irq(tcm_hcd->irq, tcm_hcd); + } + + cancel_delayed_work_sync(&tcm_hcd->polling_work); + flush_workqueue(tcm_hcd->polling_workqueue); + destroy_workqueue(tcm_hcd->polling_workqueue); + + cancel_delayed_work_sync(&tcm_hcd->watchdog.work); + flush_workqueue(tcm_hcd->watchdog.workqueue); + destroy_workqueue(tcm_hcd->watchdog.workqueue); + + cancel_work_sync(&tcm_hcd->helper.work); + flush_workqueue(tcm_hcd->helper.workqueue); + destroy_workqueue(tcm_hcd->helper.workqueue); + + kthread_stop(tcm_hcd->notifier_thread); + +#ifdef CONFIG_DRM + msm_drm_unregister_client(&tcm_hcd->fb_notifier); +#elif CONFIG_FB + fb_unregister_client(&tcm_hcd->fb_notifier); +#endif + + for (idx = 0; idx < ARRAY_SIZE(dynamic_config_attrs); idx++) { + sysfs_remove_file(tcm_hcd->dynamnic_config_sysfs_dir, + &(*dynamic_config_attrs[idx]).attr); + } + + kobject_put(tcm_hcd->dynamnic_config_sysfs_dir); + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) + sysfs_remove_file(tcm_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(tcm_hcd->sysfs_dir); + + if (bdata->irq_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->irq_gpio, false, 0, 0); + + if (bdata->power_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->power_gpio, false, 0, 0); + + if (bdata->reset_gpio >= 0) + syna_tcm_set_gpio(tcm_hcd, bdata->reset_gpio, false, 0, 0); + + syna_tcm_enable_regulator(tcm_hcd, false); + + syna_tcm_get_regulator(tcm_hcd, false); + + device_init_wakeup(&pdev->dev, 0); + + RELEASE_BUFFER(tcm_hcd->report.buffer); + RELEASE_BUFFER(tcm_hcd->config); + RELEASE_BUFFER(tcm_hcd->temp); + RELEASE_BUFFER(tcm_hcd->resp); + RELEASE_BUFFER(tcm_hcd->out); + RELEASE_BUFFER(tcm_hcd->in); + + kfree(tcm_hcd); + + return 0; +} + +#ifdef CONFIG_PM +static const struct dev_pm_ops syna_tcm_dev_pm_ops = { +#if !defined(CONFIG_DRM) && !defined(CONFIG_FB) + .suspend = syna_tcm_suspend, + .resume = syna_tcm_resume, +#endif +}; +#endif + +static struct platform_driver syna_tcm_driver = { + .driver = { + .name = PLATFORM_DRIVER_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &syna_tcm_dev_pm_ops, +#endif + }, + .probe = syna_tcm_probe, + .remove = syna_tcm_remove, +}; + +static int __init syna_tcm_module_init(void) +{ + int retval; + + retval = syna_tcm_bus_init(); + if (retval < 0) + return retval; + + return platform_driver_register(&syna_tcm_driver); +} + +static void __exit syna_tcm_module_exit(void) +{ + platform_driver_unregister(&syna_tcm_driver); + + syna_tcm_bus_exit(); +} + +module_init(syna_tcm_module_init); +module_exit(syna_tcm_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Touch Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h new file mode 100644 index 000000000000..09d7078cbae4 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h @@ -0,0 +1,666 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#ifndef _SYNAPTICS_TCM_CORE_H_ +#define _SYNAPTICS_TCM_CORE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DRM +#include +#elif CONFIG_FB +#include +#include +#endif +#include + +#define SYNAPTICS_TCM_ID_PRODUCT (1 << 0) +#define SYNAPTICS_TCM_ID_VERSION 0x0101 +#define SYNAPTICS_TCM_ID_SUBVERSION 0 + +#define PLATFORM_DRIVER_NAME "synaptics_tcm" + +#define TOUCH_INPUT_NAME "synaptics_tcm_touch" +#define TOUCH_INPUT_PHYS_PATH "synaptics_tcm/touch_input" + +#define WAKEUP_GESTURE + +#define RD_CHUNK_SIZE 0 /* read length limit in bytes, 0 = unlimited */ +#define WR_CHUNK_SIZE 0 /* write length limit in bytes, 0 = unlimited */ + +#define MESSAGE_HEADER_SIZE 4 +#define MESSAGE_MARKER 0xa5 +#define MESSAGE_PADDING 0x5a + +#define LOGx(func, dev, log, ...) \ + func(dev, "%s: " log, __func__, ##__VA_ARGS__) + +#define LOGy(func, dev, log, ...) \ + func(dev, "%s (line %d): " log, __func__, __LINE__, ##__VA_ARGS__) + +#define LOGD(dev, log, ...) LOGx(dev_dbg, dev, log, ##__VA_ARGS__) +#define LOGI(dev, log, ...) LOGx(dev_info, dev, log, ##__VA_ARGS__) +#define LOGN(dev, log, ...) LOGx(dev_notice, dev, log, ##__VA_ARGS__) +#define LOGW(dev, log, ...) LOGy(dev_warn, dev, log, ##__VA_ARGS__) +#define LOGE(dev, log, ...) LOGy(dev_err, dev, log, ##__VA_ARGS__) + +#define INIT_BUFFER(buffer, is_clone) \ + mutex_init(&buffer.buf_mutex); \ + buffer.clone = is_clone + +#define LOCK_BUFFER(buffer) \ + mutex_lock(&buffer.buf_mutex) + +#define UNLOCK_BUFFER(buffer) \ + mutex_unlock(&buffer.buf_mutex) + +#define RELEASE_BUFFER(buffer) \ + do { \ + if (buffer.clone == false) { \ + kfree(buffer.buf); \ + buffer.buf_size = 0; \ + buffer.data_length = 0; \ + } \ + } while (0) + +#define MAX(a, b) \ + ({__typeof__(a) _a = (a); \ + __typeof__(b) _b = (b); \ + _a > _b ? _a : _b; }) + +#define MIN(a, b) \ + ({__typeof__(a) _a = (a); \ + __typeof__(b) _b = (b); \ + _a < _b ? _a : _b; }) + +#define STR(x) #x + +#define CONCAT(a, b) a##b + +#define SHOW_PROTOTYPE(m_name, a_name) \ +static ssize_t CONCAT(m_name##_sysfs, _##a_name##_show)(struct device *dev, \ + struct device_attribute *attr, char *buf); \ +\ +static struct device_attribute dev_attr_##a_name = \ + __ATTR(a_name, 0444, \ + CONCAT(m_name##_sysfs, _##a_name##_show), \ + syna_tcm_store_error) + +#define STORE_PROTOTYPE(m_name, a_name) \ +static ssize_t CONCAT(m_name##_sysfs, _##a_name##_store)(struct device *dev, \ + struct device_attribute *attr, const char *buf, size_t count); \ +\ +static struct device_attribute dev_attr_##a_name = \ + __ATTR(a_name, 0220, \ + syna_tcm_show_error, \ + CONCAT(m_name##_sysfs, _##a_name##_store)) + +#define SHOW_STORE_PROTOTYPE(m_name, a_name) \ +static ssize_t CONCAT(m_name##_sysfs, _##a_name##_show)(struct device *dev, \ + struct device_attribute *attr, char *buf); \ +\ +static ssize_t CONCAT(m_name##_sysfs, _##a_name##_store)(struct device *dev, \ + struct device_attribute *attr, const char *buf, size_t count); \ +\ +static struct device_attribute dev_attr_##a_name = \ + __ATTR(a_name, 0664, \ + CONCAT(m_name##_sysfs, _##a_name##_show), \ + CONCAT(m_name##_sysfs, _##a_name##_store)) + +#define ATTRIFY(a_name) (&dev_attr_##a_name) + +enum module_type { + TCM_TOUCH = 0, + TCM_DEVICE = 1, + TCM_TESTING = 2, + TCM_REFLASH = 3, + TCM_RECOVERY = 4, + TCM_ZEROFLASH = 5, + TCM_DIAGNOSTICS = 6, + TCM_LAST, +}; + +enum boot_mode { + MODE_APPLICATION = 0x01, + MODE_HOST_DOWNLOAD = 0x02, + MODE_BOOTLOADER = 0x0b, + MODE_TDDI_BOOTLOADER = 0x0c, + MODE_PRODUCTION_TEST = 0x0e, +}; + +enum boot_status { + BOOT_STATUS_OK = 0x00, + BOOT_STATUS_BOOTING = 0x01, + BOOT_STATUS_APP_BAD_DISPLAY_CRC = 0xfc, + BOOT_STATUS_BAD_DISPLAY_CONFIG = 0xfd, + BOOT_STATUS_BAD_APP_FIRMWARE = 0xfe, + BOOT_STATUS_WARM_BOOT = 0xff, +}; + +enum app_status { + APP_STATUS_OK = 0x00, + APP_STATUS_BOOTING = 0x01, + APP_STATUS_UPDATING = 0x02, + APP_STATUS_BAD_APP_CONFIG = 0xff, +}; + +enum firmware_mode { + FW_MODE_BOOTLOADER = 0, + FW_MODE_APPLICATION = 1, + FW_MODE_PRODUCTION_TEST = 2, +}; + +enum dynamic_config_id { + DC_UNKNOWN = 0x00, + DC_NO_DOZE, + DC_DISABLE_NOISE_MITIGATION, + DC_INHIBIT_FREQUENCY_SHIFT, + DC_REQUESTED_FREQUENCY, + DC_DISABLE_HSYNC, + DC_REZERO_ON_EXIT_DEEP_SLEEP, + DC_CHARGER_CONNECTED, + DC_NO_BASELINE_RELAXATION, + DC_IN_WAKEUP_GESTURE_MODE, + DC_STIMULUS_FINGERS, + DC_GRIP_SUPPRESSION_ENABLED, + DC_ENABLE_THICK_GLOVE, + DC_ENABLE_GLOVE, +}; + +enum command { + CMD_NONE = 0x00, + CMD_CONTINUE_WRITE = 0x01, + CMD_IDENTIFY = 0x02, + CMD_RESET = 0x04, + CMD_ENABLE_REPORT = 0x05, + CMD_DISABLE_REPORT = 0x06, + CMD_GET_BOOT_INFO = 0x10, + CMD_ERASE_FLASH = 0x11, + CMD_WRITE_FLASH = 0x12, + CMD_READ_FLASH = 0x13, + CMD_RUN_APPLICATION_FIRMWARE = 0x14, + CMD_SPI_MASTER_WRITE_THEN_READ = 0x15, + CMD_REBOOT_TO_ROM_BOOTLOADER = 0x16, + CMD_RUN_BOOTLOADER_FIRMWARE = 0x1f, + CMD_GET_APPLICATION_INFO = 0x20, + CMD_GET_STATIC_CONFIG = 0x21, + CMD_SET_STATIC_CONFIG = 0x22, + CMD_GET_DYNAMIC_CONFIG = 0x23, + CMD_SET_DYNAMIC_CONFIG = 0x24, + CMD_GET_TOUCH_REPORT_CONFIG = 0x25, + CMD_SET_TOUCH_REPORT_CONFIG = 0x26, + CMD_REZERO = 0x27, + CMD_COMMIT_CONFIG = 0x28, + CMD_DESCRIBE_DYNAMIC_CONFIG = 0x29, + CMD_PRODUCTION_TEST = 0x2a, + CMD_SET_CONFIG_ID = 0x2b, + CMD_ENTER_DEEP_SLEEP = 0x2c, + CMD_EXIT_DEEP_SLEEP = 0x2d, + CMD_GET_TOUCH_INFO = 0x2e, + CMD_GET_DATA_LOCATION = 0x2f, + CMD_DOWNLOAD_CONFIG = 0x30, + CMD_ENTER_PRODUCTION_TEST_MODE = 0x31, + CMD_GET_FEATURES = 0x32, +}; + +enum status_code { + STATUS_IDLE = 0x00, + STATUS_OK = 0x01, + STATUS_BUSY = 0x02, + STATUS_CONTINUED_READ = 0x03, + STATUS_NOT_EXECUTED_IN_DEEP_SLEEP = 0x0b, + STATUS_RECEIVE_BUFFER_OVERFLOW = 0x0c, + STATUS_PREVIOUS_COMMAND_PENDING = 0x0d, + STATUS_NOT_IMPLEMENTED = 0x0e, + STATUS_ERROR = 0x0f, + STATUS_INVALID = 0xff, +}; + +enum report_type { + REPORT_IDENTIFY = 0x10, + REPORT_TOUCH = 0x11, + REPORT_DELTA = 0x12, + REPORT_RAW = 0x13, + REPORT_STATUS = 0x1b, + REPORT_PRINTF = 0x82, + REPORT_HDL = 0xfe, +}; + +enum command_status { + CMD_IDLE = 0, + CMD_BUSY = 1, + CMD_ERROR = -1, +}; + +enum flash_area { + BOOTLOADER = 0, + BOOT_CONFIG, + APP_FIRMWARE, + APP_CONFIG, + DISP_CONFIG, + CUSTOM_OTP, + CUSTOM_LCM, + CUSTOM_OEM, + PPDT, +}; + +enum flash_data { + LCM_DATA = 1, + OEM_DATA, + PPDT_DATA, +}; + +enum helper_task { + HELP_NONE = 0, + HELP_RUN_APPLICATION_FIRMWARE, + HELP_SEND_RESET_NOTIFICATION, +}; + +struct syna_tcm_helper { + atomic_t task; + struct work_struct work; + struct workqueue_struct *workqueue; +}; + +struct syna_tcm_watchdog { + bool run; + unsigned char count; + struct delayed_work work; + struct workqueue_struct *workqueue; +}; + +struct syna_tcm_buffer { + bool clone; + unsigned char *buf; + unsigned int buf_size; + unsigned int data_length; + struct mutex buf_mutex; +}; + +struct syna_tcm_report { + unsigned char id; + struct syna_tcm_buffer buffer; +}; + +struct syna_tcm_identification { + unsigned char version; + unsigned char mode; + unsigned char part_number[16]; + unsigned char build_id[4]; + unsigned char max_write_size[2]; +}; + +struct syna_tcm_boot_info { + unsigned char version; + unsigned char status; + unsigned char asic_id[2]; + unsigned char write_block_size_words; + unsigned char erase_page_size_words[2]; + unsigned char max_write_payload_size[2]; + unsigned char last_reset_reason; + unsigned char pc_at_time_of_last_reset[2]; + unsigned char boot_config_start_block[2]; + unsigned char boot_config_size_blocks[2]; + unsigned char display_config_start_block[4]; + unsigned char display_config_length_blocks[2]; + unsigned char backup_display_config_start_block[4]; + unsigned char backup_display_config_length_blocks[2]; + unsigned char custom_otp_start_block[2]; + unsigned char custom_otp_length_blocks[2]; +}; + +struct syna_tcm_app_info { + unsigned char version[2]; + unsigned char status[2]; + unsigned char static_config_size[2]; + unsigned char dynamic_config_size[2]; + unsigned char app_config_start_write_block[2]; + unsigned char app_config_size[2]; + unsigned char max_touch_report_config_size[2]; + unsigned char max_touch_report_payload_size[2]; + unsigned char customer_config_id[16]; + unsigned char max_x[2]; + unsigned char max_y[2]; + unsigned char max_objects[2]; + unsigned char num_of_buttons[2]; + unsigned char num_of_image_rows[2]; + unsigned char num_of_image_cols[2]; + unsigned char has_hybrid_data[2]; +}; + +struct syna_tcm_touch_info { + unsigned char image_2d_scale_factor[4]; + unsigned char image_0d_scale_factor[4]; + unsigned char hybrid_x_scale_factor[4]; + unsigned char hybrid_y_scale_factor[4]; +}; + +struct syna_tcm_message_header { + unsigned char marker; + unsigned char code; + unsigned char length[2]; +}; + +struct syna_tcm_features { + unsigned char byte_0_reserved; + unsigned char byte_1_reserved; + unsigned char dual_firmware:1; + unsigned char byte_2_reserved:7; +} __packed; + +struct syna_tcm_hcd { + pid_t isr_pid; + atomic_t command_status; + atomic_t host_downloading; + wait_queue_head_t hdl_wq; + int irq; + bool init_okay; + bool do_polling; + bool in_suspend; + bool irq_enabled; + bool host_download_mode; + unsigned char fb_ready; + unsigned char command; + unsigned char async_report_id; + unsigned char status_report_code; + unsigned char response_code; + unsigned int read_length; + unsigned int payload_length; + unsigned int packrat_number; + unsigned int rd_chunk_size; + unsigned int wr_chunk_size; + unsigned int app_status; + struct platform_device *pdev; + struct regulator *pwr_reg; + struct regulator *bus_reg; + struct kobject *sysfs_dir; + struct kobject *dynamnic_config_sysfs_dir; + struct mutex extif_mutex; + struct mutex reset_mutex; + struct mutex irq_en_mutex; + struct mutex io_ctrl_mutex; + struct mutex rw_ctrl_mutex; + struct mutex command_mutex; + struct mutex identify_mutex; + struct delayed_work polling_work; + struct workqueue_struct *polling_workqueue; + struct task_struct *notifier_thread; +#if defined(CONFIG_DRM) || defined(CONFIG_FB) + struct notifier_block fb_notifier; +#endif + struct syna_tcm_buffer in; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_buffer temp; + struct syna_tcm_buffer config; + struct syna_tcm_report report; + struct syna_tcm_app_info app_info; + struct syna_tcm_boot_info boot_info; + struct syna_tcm_touch_info touch_info; + struct syna_tcm_identification id_info; + struct syna_tcm_helper helper; + struct syna_tcm_watchdog watchdog; + struct syna_tcm_features features; + const struct syna_tcm_hw_interface *hw_if; + int (*reset)(struct syna_tcm_hcd *tcm_hcd, bool hw, bool update_wd); + int (*sleep)(struct syna_tcm_hcd *tcm_hcd, bool en); + int (*identify)(struct syna_tcm_hcd *tcm_hcd, bool id); + int (*enable_irq)(struct syna_tcm_hcd *tcm_hcd, bool en, bool ns); + int (*switch_mode)(struct syna_tcm_hcd *tcm_hcd, + enum firmware_mode mode); + int (*read_message)(struct syna_tcm_hcd *tcm_hcd, + unsigned char *in_buf, unsigned int length); + int (*write_message)(struct syna_tcm_hcd *tcm_hcd, + unsigned char command, unsigned char *payload, + unsigned int length, unsigned char **resp_buf, + unsigned int *resp_buf_size, unsigned int *resp_length, + unsigned char *response_code, + unsigned int polling_delay_ms); + int (*get_dynamic_config)(struct syna_tcm_hcd *tcm_hcd, + enum dynamic_config_id id, unsigned short *value); + int (*set_dynamic_config)(struct syna_tcm_hcd *tcm_hcd, + enum dynamic_config_id id, unsigned short value); + int (*get_data_location)(struct syna_tcm_hcd *tcm_hcd, + enum flash_area area, unsigned int *addr, + unsigned int *length); + int (*read_flash_data)(enum flash_area area, bool run_app_firmware, + struct syna_tcm_buffer *output); + void (*report_touch)(void); + void (*update_watchdog)(struct syna_tcm_hcd *tcm_hcd, bool en); +}; + +struct syna_tcm_module_cb { + enum module_type type; + int (*init)(struct syna_tcm_hcd *tcm_hcd); + int (*remove)(struct syna_tcm_hcd *tcm_hcd); + int (*syncbox)(struct syna_tcm_hcd *tcm_hcd); + int (*asyncbox)(struct syna_tcm_hcd *tcm_hcd); + int (*reset)(struct syna_tcm_hcd *tcm_hcd); + int (*suspend)(struct syna_tcm_hcd *tcm_hcd); + int (*resume)(struct syna_tcm_hcd *tcm_hcd); + int (*early_suspend)(struct syna_tcm_hcd *tcm_hcd); +}; + +struct syna_tcm_module_handler { + bool insert; + bool detach; + struct list_head link; + struct syna_tcm_module_cb *mod_cb; +}; + +struct syna_tcm_module_pool { + bool initialized; + bool queue_work; + struct mutex mutex; + struct list_head list; + struct work_struct work; + struct workqueue_struct *workqueue; + struct syna_tcm_hcd *tcm_hcd; +}; + +struct syna_tcm_bus_io { + unsigned char type; + int (*rmi_read)(struct syna_tcm_hcd *tcm_hcd, unsigned short addr, + unsigned char *data, unsigned int length); + int (*rmi_write)(struct syna_tcm_hcd *tcm_hcd, unsigned short addr, + unsigned char *data, unsigned int length); + int (*read)(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length); + int (*write)(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length); +}; + +struct syna_tcm_hw_interface { + struct syna_tcm_board_data *bdata; + const struct syna_tcm_bus_io *bus_io; +}; + +int syna_tcm_bus_init(void); + +void syna_tcm_bus_exit(void); + +int syna_tcm_add_module(struct syna_tcm_module_cb *mod_cb, bool insert); + +static inline int syna_tcm_rmi_read(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + return tcm_hcd->hw_if->bus_io->rmi_read(tcm_hcd, addr, data, length); +} + +static inline int syna_tcm_rmi_write(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + return tcm_hcd->hw_if->bus_io->rmi_write(tcm_hcd, addr, data, length); +} + +static inline int syna_tcm_read(struct syna_tcm_hcd *tcm_hcd, + unsigned char *data, unsigned int length) +{ + return tcm_hcd->hw_if->bus_io->read(tcm_hcd, data, length); +} + +static inline int syna_tcm_write(struct syna_tcm_hcd *tcm_hcd, + unsigned char *data, unsigned int length) +{ + return tcm_hcd->hw_if->bus_io->write(tcm_hcd, data, length); +} + +static inline ssize_t syna_tcm_show_error(struct device *dev, + struct device_attribute *attr, char *buf) +{ + pr_err("%s: Attribute not readable\n", + __func__); + + return -EPERM; +} + +static inline ssize_t syna_tcm_store_error(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + pr_err("%s: Attribute not writable\n", + __func__); + + return -EPERM; +} + +static inline int secure_memcpy(unsigned char *dest, unsigned int dest_size, + const unsigned char *src, unsigned int src_size, + unsigned int count) +{ + if (dest == NULL || src == NULL) + return -EINVAL; + + if (count > dest_size || count > src_size) { + pr_err("%s: src_size = %d, dest_size = %d, count = %d\n", + __func__, src_size, dest_size, count); + return -EINVAL; + } + + memcpy((void *)dest, (const void *)src, count); + + return 0; +} + +static inline int syna_tcm_realloc_mem(struct syna_tcm_hcd *tcm_hcd, + struct syna_tcm_buffer *buffer, unsigned int size) +{ + int retval; + unsigned char *temp; + + if (size > buffer->buf_size) { + temp = buffer->buf; + + buffer->buf = kmalloc(size, GFP_KERNEL); + if (!(buffer->buf)) { + dev_err(tcm_hcd->pdev->dev.parent, + "%s: Failed to allocate memory\n", + __func__); + kfree(temp); + buffer->buf_size = 0; + return -ENOMEM; + } + + retval = secure_memcpy(buffer->buf, + size, + temp, + buffer->buf_size, + buffer->buf_size); + if (retval < 0) { + dev_err(tcm_hcd->pdev->dev.parent, + "%s: Failed to copy data\n", + __func__); + kfree(temp); + kfree(buffer->buf); + buffer->buf_size = 0; + return retval; + } + + kfree(temp); + buffer->buf_size = size; + } + + return 0; +} + +static inline int syna_tcm_alloc_mem(struct syna_tcm_hcd *tcm_hcd, + struct syna_tcm_buffer *buffer, unsigned int size) +{ + if (size > buffer->buf_size) { + kfree(buffer->buf); + buffer->buf = kmalloc(size, GFP_KERNEL); + if (!(buffer->buf)) { + dev_err(tcm_hcd->pdev->dev.parent, + "%s: Failed to allocate memory\n", + __func__); + dev_err(tcm_hcd->pdev->dev.parent, + "%s: Allocation size = %d\n", + __func__, size); + buffer->buf_size = 0; + buffer->data_length = 0; + return -ENOMEM; + } + buffer->buf_size = size; + } + + memset(buffer->buf, 0x00, buffer->buf_size); + buffer->data_length = 0; + + return 0; +} + +static inline unsigned int le2_to_uint(const unsigned char *src) +{ + return (unsigned int)src[0] + + (unsigned int)src[1] * 0x100; +} + +static inline unsigned int le4_to_uint(const unsigned char *src) +{ + return (unsigned int)src[0] + + (unsigned int)src[1] * 0x100 + + (unsigned int)src[2] * 0x10000 + + (unsigned int)src[3] * 0x1000000; +} + +static inline unsigned int ceil_div(unsigned int dividend, + unsigned int divisor) +{ + return (dividend + divisor - 1) / divisor; +} + +#endif diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_device.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_device.c new file mode 100644 index 000000000000..97de087fde1b --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_device.c @@ -0,0 +1,704 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include +#include "synaptics_tcm_core.h" + +#define CHAR_DEVICE_NAME "tcm" + +#define CONCURRENT true + +#define DEVICE_IOC_MAGIC 's' +#define DEVICE_IOC_RESET _IO(DEVICE_IOC_MAGIC, 0) /* 0x00007300 */ +#define DEVICE_IOC_IRQ _IOW(DEVICE_IOC_MAGIC, 1, int) /* 0x40047301 */ +#define DEVICE_IOC_RAW _IOW(DEVICE_IOC_MAGIC, 2, int) /* 0x40047302 */ +#define DEVICE_IOC_CONCURRENT _IOW(DEVICE_IOC_MAGIC, 3, int) /* 0x40047303 */ + +struct device_hcd { + dev_t dev_num; + bool raw_mode; + bool concurrent; + unsigned int ref_count; + struct cdev char_dev; + struct class *class; + struct device *device; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_buffer report; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(device_remove_complete); + +static struct device_hcd *device_hcd; + +static int rmidev_major_num; + +static void device_capture_touch_report(unsigned int count) +{ + int retval; + unsigned char id; + unsigned int idx; + unsigned int size; + unsigned char *data; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + static bool report; + static unsigned int offset; + static unsigned int remaining_size; + + if (count < 2) + return; + + data = &device_hcd->resp.buf[0]; + + if (data[0] != MESSAGE_MARKER) + return; + + id = data[1]; + + size = 0; + + LOCK_BUFFER(device_hcd->report); + + switch (id) { + case REPORT_TOUCH: + if (count >= 4) { + remaining_size = le2_to_uint(&data[2]); + } else { + report = false; + goto exit; + } + retval = syna_tcm_alloc_mem(tcm_hcd, + &device_hcd->report, + remaining_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for report.buf\n"); + report = false; + goto exit; + } + idx = 4; + size = count - idx; + offset = 0; + report = true; + break; + case STATUS_CONTINUED_READ: + if (report == false) + goto exit; + if (count >= 2) { + idx = 2; + size = count - idx; + } + break; + default: + goto exit; + } + + if (size) { + size = MIN(size, remaining_size); + retval = secure_memcpy(&device_hcd->report.buf[offset], + device_hcd->report.buf_size - offset, + &data[idx], + count - idx, + size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy touch report data\n"); + report = false; + goto exit; + } else { + offset += size; + remaining_size -= size; + device_hcd->report.data_length += size; + } + } + + if (remaining_size) + goto exit; + + LOCK_BUFFER(tcm_hcd->report.buffer); + + tcm_hcd->report.buffer.buf = device_hcd->report.buf; + tcm_hcd->report.buffer.buf_size = device_hcd->report.buf_size; + tcm_hcd->report.buffer.data_length = device_hcd->report.data_length; + + tcm_hcd->report_touch(); + + UNLOCK_BUFFER(tcm_hcd->report.buffer); + + report = false; + +exit: + UNLOCK_BUFFER(device_hcd->report); +} + +static int device_capture_touch_report_config(unsigned int count) +{ + int retval; + unsigned int size; + unsigned int buf_size; + unsigned char *data; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + if (device_hcd->raw_mode) { + if (count < 3) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid write data\n"); + return -EINVAL; + } + + size = le2_to_uint(&device_hcd->out.buf[1]); + + if (count - 3 < size) { + LOGE(tcm_hcd->pdev->dev.parent, + "Incomplete write data\n"); + return -EINVAL; + } + + if (!size) + return 0; + + data = &device_hcd->out.buf[3]; + buf_size = device_hcd->out.buf_size - 3; + } else { + size = count - 1; + + if (!size) + return 0; + + data = &device_hcd->out.buf[1]; + buf_size = device_hcd->out.buf_size - 1; + } + + LOCK_BUFFER(tcm_hcd->config); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &tcm_hcd->config, + size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for tcm_hcd->config.buf\n"); + UNLOCK_BUFFER(tcm_hcd->config); + return retval; + } + + retval = secure_memcpy(tcm_hcd->config.buf, + tcm_hcd->config.buf_size, + data, + buf_size, + size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy touch report config data\n"); + UNLOCK_BUFFER(tcm_hcd->config); + return retval; + } + + tcm_hcd->config.data_length = size; + + UNLOCK_BUFFER(tcm_hcd->config); + + return 0; +} + +#ifdef HAVE_UNLOCKED_IOCTL +static long device_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +#else +static int device_ioctl(struct inode *inp, struct file *filp, unsigned int cmd, + unsigned long arg) +#endif +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = 0; + + switch (cmd) { + case DEVICE_IOC_RESET: + retval = tcm_hcd->reset(tcm_hcd, false, true); + break; + case DEVICE_IOC_IRQ: + if (arg == 0) + retval = tcm_hcd->enable_irq(tcm_hcd, false, false); + else if (arg == 1) + retval = tcm_hcd->enable_irq(tcm_hcd, true, NULL); + break; + case DEVICE_IOC_RAW: + if (arg == 0) + device_hcd->raw_mode = false; + else if (arg == 1) + device_hcd->raw_mode = true; + break; + case DEVICE_IOC_CONCURRENT: + if (arg == 0) + device_hcd->concurrent = false; + else if (arg == 1) + device_hcd->concurrent = true; + break; + default: + retval = -ENOTTY; + break; + } + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static loff_t device_llseek(struct file *filp, loff_t off, int whence) +{ + return -EINVAL; +} + +static ssize_t device_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + if (count == 0) + return 0; + + mutex_lock(&tcm_hcd->extif_mutex); + + LOCK_BUFFER(device_hcd->resp); + + if (device_hcd->raw_mode) { + retval = syna_tcm_alloc_mem(tcm_hcd, + &device_hcd->resp, + count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for resp.buf\n"); + UNLOCK_BUFFER(device_hcd->resp); + goto exit; + } + + retval = tcm_hcd->read_message(tcm_hcd, + device_hcd->resp.buf, + count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read message\n"); + UNLOCK_BUFFER(device_hcd->resp); + goto exit; + } + } else { + if (count != device_hcd->resp.data_length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid length information\n"); + UNLOCK_BUFFER(device_hcd->resp); + retval = -EINVAL; + goto exit; + } + } + + if (copy_to_user(buf, device_hcd->resp.buf, count)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy data to user space\n"); + UNLOCK_BUFFER(device_hcd->resp); + retval = -EINVAL; + goto exit; + } + + if (!device_hcd->concurrent) + goto skip_concurrent; + + if (tcm_hcd->report_touch == NULL) { + LOGE(tcm_hcd->pdev->dev.parent, + "Unable to report touch\n"); + device_hcd->concurrent = false; + } + + if (device_hcd->raw_mode) + device_capture_touch_report(count); + +skip_concurrent: + UNLOCK_BUFFER(device_hcd->resp); + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t device_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + if (count == 0) + return 0; + + mutex_lock(&tcm_hcd->extif_mutex); + + LOCK_BUFFER(device_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &device_hcd->out, + count == 1 ? count + 1 : count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for device_hcd->out.buf\n"); + UNLOCK_BUFFER(device_hcd->out); + goto exit; + } + + if (copy_from_user(device_hcd->out.buf, buf, count)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy data from user space\n"); + UNLOCK_BUFFER(device_hcd->out); + retval = -EINVAL; + goto exit; + } + + LOCK_BUFFER(device_hcd->resp); + + if (device_hcd->raw_mode) { + retval = tcm_hcd->write_message(tcm_hcd, + device_hcd->out.buf[0], + &device_hcd->out.buf[1], + count - 1, + NULL, + NULL, + NULL, + NULL, + 0); + } else { + mutex_lock(&tcm_hcd->reset_mutex); + retval = tcm_hcd->write_message(tcm_hcd, + device_hcd->out.buf[0], + &device_hcd->out.buf[1], + count - 1, + &device_hcd->resp.buf, + &device_hcd->resp.buf_size, + &device_hcd->resp.data_length, + NULL, + 0); + mutex_unlock(&tcm_hcd->reset_mutex); + } + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command 0x%02x\n", + device_hcd->out.buf[0]); + UNLOCK_BUFFER(device_hcd->resp); + UNLOCK_BUFFER(device_hcd->out); + goto exit; + } + + if (count && device_hcd->out.buf[0] == CMD_SET_TOUCH_REPORT_CONFIG) { + retval = device_capture_touch_report_config(count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to capture touch report config\n"); + } + } + + UNLOCK_BUFFER(device_hcd->out); + + if (device_hcd->raw_mode) + retval = count; + else + retval = device_hcd->resp.data_length; + + UNLOCK_BUFFER(device_hcd->resp); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static int device_open(struct inode *inp, struct file *filp) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (device_hcd->ref_count < 1) { + device_hcd->ref_count++; + retval = 0; + } else { + retval = -EACCES; + } + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static int device_release(struct inode *inp, struct file *filp) +{ + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (device_hcd->ref_count) + device_hcd->ref_count--; + + mutex_unlock(&tcm_hcd->extif_mutex); + + return 0; +} + +static char *device_devnode(struct device *dev, umode_t *mode) +{ + if (!mode) + return NULL; + + /* S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH; */ + *mode = 0666; + + return kasprintf(GFP_KERNEL, "%s/%s", PLATFORM_DRIVER_NAME, + dev_name(dev)); +} + +static int device_create_class(void) +{ + struct syna_tcm_hcd *tcm_hcd = device_hcd->tcm_hcd; + + if (device_hcd->class != NULL) + return 0; + + device_hcd->class = class_create(THIS_MODULE, PLATFORM_DRIVER_NAME); + + if (IS_ERR(device_hcd->class)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create class\n"); + return -ENODEV; + } + + device_hcd->class->devnode = device_devnode; + + return 0; +} + +static const struct file_operations device_fops = { + .owner = THIS_MODULE, +#ifdef HAVE_UNLOCKED_IOCTL + .unlocked_ioctl = device_ioctl, +#ifdef HAVE_COMPAT_IOCTL + .compat_ioctl = device_ioctl, +#endif +#else + .ioctl = device_ioctl, +#endif + .llseek = device_llseek, + .read = device_read, + .write = device_write, + .open = device_open, + .release = device_release, +}; + +static int device_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + dev_t dev_num; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + device_hcd = kzalloc(sizeof(*device_hcd), GFP_KERNEL); + if (!device_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for device_hcd\n"); + return -ENOMEM; + } + + device_hcd->tcm_hcd = tcm_hcd; + + device_hcd->concurrent = CONCURRENT; + + INIT_BUFFER(device_hcd->out, false); + INIT_BUFFER(device_hcd->resp, false); + INIT_BUFFER(device_hcd->report, false); + + if (rmidev_major_num) { + dev_num = MKDEV(rmidev_major_num, 0); + retval = register_chrdev_region(dev_num, 1, + PLATFORM_DRIVER_NAME); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to register char device\n"); + goto err_register_chrdev_region; + } + } else { + retval = alloc_chrdev_region(&dev_num, 0, 1, + PLATFORM_DRIVER_NAME); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate char device\n"); + goto err_alloc_chrdev_region; + } + + rmidev_major_num = MAJOR(dev_num); + } + + device_hcd->dev_num = dev_num; + + cdev_init(&device_hcd->char_dev, &device_fops); + + retval = cdev_add(&device_hcd->char_dev, dev_num, 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add char device\n"); + goto err_add_chardev; + } + + retval = device_create_class(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create class\n"); + goto err_create_class; + } + + device_hcd->device = device_create(device_hcd->class, NULL, + device_hcd->dev_num, NULL, CHAR_DEVICE_NAME"%d", + MINOR(device_hcd->dev_num)); + if (IS_ERR(device_hcd->device)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create device\n"); + retval = -ENODEV; + goto err_create_device; + } + + if (bdata->irq_gpio >= 0) { + retval = gpio_export(bdata->irq_gpio, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to export GPIO\n"); + } else { + retval = gpio_export_link(&tcm_hcd->pdev->dev, + "attn", bdata->irq_gpio); + if (retval < 0) + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to export GPIO link\n"); + } + } + + return 0; + +err_create_device: + class_destroy(device_hcd->class); + +err_create_class: + cdev_del(&device_hcd->char_dev); + +err_add_chardev: + unregister_chrdev_region(dev_num, 1); + +err_alloc_chrdev_region: +err_register_chrdev_region: + RELEASE_BUFFER(device_hcd->report); + RELEASE_BUFFER(device_hcd->resp); + RELEASE_BUFFER(device_hcd->out); + + kfree(device_hcd); + device_hcd = NULL; + + return retval; +} + +static int device_remove(struct syna_tcm_hcd *tcm_hcd) +{ + if (!device_hcd) + goto exit; + + device_destroy(device_hcd->class, device_hcd->dev_num); + + class_destroy(device_hcd->class); + + cdev_del(&device_hcd->char_dev); + + unregister_chrdev_region(device_hcd->dev_num, 1); + + RELEASE_BUFFER(device_hcd->report); + RELEASE_BUFFER(device_hcd->resp); + RELEASE_BUFFER(device_hcd->out); + + kfree(device_hcd); + device_hcd = NULL; + +exit: + complete(&device_remove_complete); + + return 0; +} + +static int device_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!device_hcd) { + retval = device_init(tcm_hcd); + return retval; + } + + return 0; +} + +static struct syna_tcm_module_cb device_module = { + .type = TCM_DEVICE, + .init = device_init, + .remove = device_remove, + .syncbox = NULL, + .asyncbox = NULL, + .reset = device_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init device_module_init(void) +{ + return syna_tcm_add_module(&device_module, true); +} + +static void __exit device_module_exit(void) +{ + syna_tcm_add_module(&device_module, false); + + wait_for_completion(&device_remove_complete); +} + +module_init(device_module_init); +module_exit(device_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Device Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_diagnostics.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_diagnostics.c new file mode 100644 index 000000000000..0f8570a07565 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_diagnostics.c @@ -0,0 +1,564 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include "synaptics_tcm_core.h" + +#define SYSFS_DIR_NAME "diagnostics" + +enum pingpong_state { + PING = 0, + PONG = 1, +}; + +struct diag_hcd { + pid_t pid; + unsigned char report_type; + enum pingpong_state state; + struct kobject *sysfs_dir; + struct siginfo sigio; + struct task_struct *task; + struct syna_tcm_buffer ping; + struct syna_tcm_buffer pong; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(diag_remove_complete); + +static struct diag_hcd *diag_hcd; + +STORE_PROTOTYPE(diag, pid); +SHOW_PROTOTYPE(diag, size); +STORE_PROTOTYPE(diag, type); +SHOW_PROTOTYPE(diag, rows); +SHOW_PROTOTYPE(diag, cols); +SHOW_PROTOTYPE(diag, hybrid); +SHOW_PROTOTYPE(diag, buttons); + +static struct device_attribute *attrs[] = { + ATTRIFY(pid), + ATTRIFY(size), + ATTRIFY(type), + ATTRIFY(rows), + ATTRIFY(cols), + ATTRIFY(hybrid), + ATTRIFY(buttons), +}; + +static ssize_t diag_sysfs_data_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static struct bin_attribute bin_attr = { + .attr = { + .name = "data", + .mode = 0444, + }, + .size = 0, + .read = diag_sysfs_data_show, +}; + +static ssize_t diag_sysfs_pid_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int retval; + unsigned int input; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + diag_hcd->pid = input; + + if (diag_hcd->pid) { + diag_hcd->task = pid_task(find_vpid(diag_hcd->pid), + PIDTYPE_PID); + if (!diag_hcd->task) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to locate task\n"); + retval = -EINVAL; + goto exit; + } + } + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (diag_hcd->state == PING) { + LOCK_BUFFER(diag_hcd->ping); + + retval = snprintf(buf, PAGE_SIZE, + "%u\n", + diag_hcd->ping.data_length); + + UNLOCK_BUFFER(diag_hcd->ping); + } else { + LOCK_BUFFER(diag_hcd->pong); + + retval = snprintf(buf, PAGE_SIZE, + "%u\n", + diag_hcd->pong.data_length); + + UNLOCK_BUFFER(diag_hcd->pong); + } + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_type_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned int input; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + diag_hcd->report_type = (unsigned char)input; + + mutex_unlock(&tcm_hcd->extif_mutex); + + return count; +} + +static ssize_t diag_sysfs_rows_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + unsigned int rows; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + retval = -ENODEV; + goto exit; + } + + app_info = &tcm_hcd->app_info; + rows = le2_to_uint(app_info->num_of_image_rows); + + retval = snprintf(buf, PAGE_SIZE, "%u\n", rows); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_cols_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + unsigned int cols; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + retval = -ENODEV; + goto exit; + } + + app_info = &tcm_hcd->app_info; + cols = le2_to_uint(app_info->num_of_image_cols); + + retval = snprintf(buf, PAGE_SIZE, "%u\n", cols); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_hybrid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + unsigned int hybrid; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + retval = -ENODEV; + goto exit; + } + + app_info = &tcm_hcd->app_info; + hybrid = le2_to_uint(app_info->has_hybrid_data); + + retval = snprintf(buf, PAGE_SIZE, "%u\n", hybrid); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_buttons_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + unsigned int buttons; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + retval = -ENODEV; + goto exit; + } + + app_info = &tcm_hcd->app_info; + buttons = le2_to_uint(app_info->num_of_buttons); + + retval = snprintf(buf, PAGE_SIZE, "%u\n", buttons); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t diag_sysfs_data_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + unsigned int readlen; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = 0; + + if (diag_hcd->state == PING) { + LOCK_BUFFER(diag_hcd->ping); + + if (diag_hcd->ping.data_length == 0) { + readlen = 0; + goto exit; + } + + readlen = MIN(count, diag_hcd->ping.data_length - pos); + + if (diag_hcd->ping.data_length) { + retval = secure_memcpy(buf, + count, + &diag_hcd->ping.buf[pos], + diag_hcd->ping.buf_size - pos, + readlen); + } + + UNLOCK_BUFFER(diag_hcd->ping); + } else { + LOCK_BUFFER(diag_hcd->pong); + + if (diag_hcd->pong.data_length == 0) { + readlen = 0; + goto exit; + } + + readlen = MIN(count, diag_hcd->pong.data_length - pos); + + if (diag_hcd->pong.data_length) { + retval = secure_memcpy(buf, + count, + &diag_hcd->pong.buf[pos], + diag_hcd->pong.buf_size - pos, + readlen); + } + + UNLOCK_BUFFER(diag_hcd->pong); + } + +exit: + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy report data\n"); + } else { + retval = readlen; + } + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static void diag_report(void) +{ + int retval; + static enum pingpong_state state = PING; + struct syna_tcm_hcd *tcm_hcd = diag_hcd->tcm_hcd; + + if (state == PING) { + LOCK_BUFFER(diag_hcd->ping); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &diag_hcd->ping, + tcm_hcd->report.buffer.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for ping.buf\n"); + UNLOCK_BUFFER(diag_hcd->ping); + return; + } + + retval = secure_memcpy(diag_hcd->ping.buf, + diag_hcd->ping.buf_size, + tcm_hcd->report.buffer.buf, + tcm_hcd->report.buffer.buf_size, + tcm_hcd->report.buffer.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy report data\n"); + UNLOCK_BUFFER(diag_hcd->ping); + return; + } + + diag_hcd->ping.data_length = tcm_hcd->report.buffer.data_length; + + UNLOCK_BUFFER(diag_hcd->ping); + + diag_hcd->state = state; + state = PONG; + } else { + LOCK_BUFFER(diag_hcd->pong); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &diag_hcd->pong, + tcm_hcd->report.buffer.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for pong.buf\n"); + UNLOCK_BUFFER(diag_hcd->pong); + return; + } + + retval = secure_memcpy(diag_hcd->pong.buf, + diag_hcd->pong.buf_size, + tcm_hcd->report.buffer.buf, + tcm_hcd->report.buffer.buf_size, + tcm_hcd->report.buffer.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy report data\n"); + UNLOCK_BUFFER(diag_hcd->pong); + return; + } + + diag_hcd->pong.data_length = tcm_hcd->report.buffer.data_length; + + UNLOCK_BUFFER(diag_hcd->pong); + + diag_hcd->state = state; + state = PING; + } + + if (diag_hcd->pid) + send_sig_info(SIGIO, &diag_hcd->sigio, diag_hcd->task); +} + +static int diag_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + int idx; + + diag_hcd = kzalloc(sizeof(*diag_hcd), GFP_KERNEL); + if (!diag_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for diag_hcd\n"); + return -ENOMEM; + } + + diag_hcd->tcm_hcd = tcm_hcd; + diag_hcd->state = PING; + + INIT_BUFFER(diag_hcd->ping, false); + INIT_BUFFER(diag_hcd->pong, false); + + memset(&diag_hcd->sigio, 0x00, sizeof(diag_hcd->sigio)); + diag_hcd->sigio.si_signo = SIGIO; + diag_hcd->sigio.si_code = SI_USER; + + diag_hcd->sysfs_dir = kobject_create_and_add(SYSFS_DIR_NAME, + tcm_hcd->sysfs_dir); + if (!diag_hcd->sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dir; + } + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + retval = sysfs_create_file(diag_hcd->sysfs_dir, + &(*attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs file\n"); + goto err_sysfs_create_file; + } + } + + retval = sysfs_create_bin_file(diag_hcd->sysfs_dir, &bin_attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs bin file\n"); + goto err_sysfs_create_bin_file; + } + + return 0; + +err_sysfs_create_bin_file: +err_sysfs_create_file: + for (idx--; idx >= 0; idx--) + sysfs_remove_file(diag_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(diag_hcd->sysfs_dir); + +err_sysfs_create_dir: + RELEASE_BUFFER(diag_hcd->pong); + RELEASE_BUFFER(diag_hcd->ping); + + kfree(diag_hcd); + diag_hcd = NULL; + + return retval; +} + +static int diag_remove(struct syna_tcm_hcd *tcm_hcd) +{ + int idx; + + if (!diag_hcd) + goto exit; + + sysfs_remove_bin_file(diag_hcd->sysfs_dir, &bin_attr); + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) + sysfs_remove_file(diag_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(diag_hcd->sysfs_dir); + + RELEASE_BUFFER(diag_hcd->pong); + RELEASE_BUFFER(diag_hcd->ping); + + kfree(diag_hcd); + diag_hcd = NULL; + +exit: + complete(&diag_remove_complete); + + return 0; +} + +static int diag_syncbox(struct syna_tcm_hcd *tcm_hcd) +{ + if (!diag_hcd) + return 0; + + if (tcm_hcd->report.id == diag_hcd->report_type) + diag_report(); + + return 0; +} + +static int diag_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!diag_hcd) { + retval = diag_init(tcm_hcd); + return retval; + } + + return 0; +} + +static struct syna_tcm_module_cb diag_module = { + .type = TCM_DIAGNOSTICS, + .init = diag_init, + .remove = diag_remove, + .syncbox = diag_syncbox, + .asyncbox = NULL, + .reset = diag_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init diag_module_init(void) +{ + return syna_tcm_add_module(&diag_module, true); +} + +static void __exit diag_module_exit(void) +{ + syna_tcm_add_module(&diag_module, false); + + wait_for_completion(&diag_remove_complete); +} + +module_init(diag_module_init); +module_exit(diag_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Diagnostics Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_i2c.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_i2c.c new file mode 100644 index 000000000000..913ef8b8ae8e --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_i2c.c @@ -0,0 +1,496 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include "synaptics_tcm_core.h" + +#define XFER_ATTEMPTS 10 + +static unsigned char *buf; + +static unsigned int buf_size; + +static struct syna_tcm_bus_io bus_io; + +static struct syna_tcm_hw_interface hw_if; + +static struct platform_device *syna_tcm_i2c_device; + +#ifdef CONFIG_OF +static int parse_dt(struct device *dev, struct syna_tcm_board_data *bdata) +{ + int retval; + u32 value; + struct property *prop; + struct device_node *np = dev->of_node; + const char *name; + + prop = of_find_property(np, "synaptics,irq-gpio", NULL); + if (prop && prop->length) { + bdata->irq_gpio = of_get_named_gpio_flags(np, + "synaptics,irq-gpio", 0, + (enum of_gpio_flags *)&bdata->irq_flags); + } else { + bdata->irq_gpio = -1; + } + + retval = of_property_read_u32(np, "synaptics,irq-on-state", &value); + if (retval < 0) + bdata->irq_on_state = 0; + else + bdata->irq_on_state = value; + + retval = of_property_read_string(np, "synaptics,pwr-reg-name", &name); + if (retval < 0) + bdata->pwr_reg_name = NULL; + else + bdata->pwr_reg_name = name; + + retval = of_property_read_string(np, "synaptics,bus-reg-name", &name); + if (retval < 0) + bdata->bus_reg_name = NULL; + else + bdata->bus_reg_name = name; + + prop = of_find_property(np, "synaptics,power-gpio", NULL); + if (prop && prop->length) { + bdata->power_gpio = of_get_named_gpio_flags(np, + "synaptics,power-gpio", 0, NULL); + } else { + bdata->power_gpio = -1; + } + + prop = of_find_property(np, "synaptics,power-on-state", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,power-on-state", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,power-on-state\n"); + return retval; + } + bdata->power_on_state = value; + } else { + bdata->power_on_state = 0; + } + + prop = of_find_property(np, "synaptics,power-delay-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,power-delay-ms", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,power-delay-ms\n"); + return retval; + } + bdata->power_delay_ms = value; + } else { + bdata->power_delay_ms = 0; + } + + prop = of_find_property(np, "synaptics,reset-gpio", NULL); + if (prop && prop->length) { + bdata->reset_gpio = of_get_named_gpio_flags(np, + "synaptics,reset-gpio", 0, NULL); + } else { + bdata->reset_gpio = -1; + } + + prop = of_find_property(np, "synaptics,reset-on-state", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-on-state", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,reset-on-state\n"); + return retval; + } + bdata->reset_on_state = value; + } else { + bdata->reset_on_state = 0; + } + + prop = of_find_property(np, "synaptics,reset-active-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-active-ms", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,reset-active-ms\n"); + return retval; + } + bdata->reset_active_ms = value; + } else { + bdata->reset_active_ms = 0; + } + + prop = of_find_property(np, "synaptics,reset-delay-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-delay-ms", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,reset-delay-ms\n"); + return retval; + } + bdata->reset_delay_ms = value; + } else { + bdata->reset_delay_ms = 0; + } + + prop = of_find_property(np, "synaptics,x-flip", NULL); + bdata->x_flip = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,y-flip", NULL); + bdata->y_flip = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,swap-axes", NULL); + bdata->swap_axes = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,ubl-i2c-addr", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,ubl-i2c-addr", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,ubl-i2c-addr\n"); + return retval; + } + bdata->ubl_i2c_addr = value; + } else { + bdata->ubl_i2c_addr = 0; + } + + return 0; +} +#endif + +static int syna_tcm_i2c_alloc_mem(struct syna_tcm_hcd *tcm_hcd, + unsigned int size) +{ + struct i2c_client *i2c = to_i2c_client(tcm_hcd->pdev->dev.parent); + + if (size > buf_size) { + if (buf_size) + kfree(buf); + buf = kmalloc(size, GFP_KERNEL); + if (!buf) { + LOGE(&i2c->dev, + "Failed to allocate memory for buf\n"); + buf_size = 0; + return -ENOMEM; + } + buf_size = size; + } + + return 0; +} + +static int syna_tcm_i2c_rmi_read(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + int retval; + unsigned char address; + unsigned int attempt; + struct i2c_msg msg[2]; + struct i2c_client *i2c = to_i2c_client(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + address = (unsigned char)addr; + + msg[0].addr = bdata->ubl_i2c_addr; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &address; + + msg[1].addr = bdata->ubl_i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = length; + msg[1].buf = data; + + for (attempt = 0; attempt < XFER_ATTEMPTS; attempt++) { + if (i2c_transfer(i2c->adapter, msg, 2) == 2) { + retval = length; + goto exit; + } + LOGE(&i2c->dev, + "Transfer attempt %d failed\n", + attempt + 1); + + if (attempt + 1 == XFER_ATTEMPTS) { + retval = -EIO; + goto exit; + } + + msleep(20); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_i2c_rmi_write(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + int retval; + unsigned int attempt; + unsigned int byte_count; + struct i2c_msg msg; + struct i2c_client *i2c = to_i2c_client(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + byte_count = length + 1; + + retval = syna_tcm_i2c_alloc_mem(tcm_hcd, byte_count); + if (retval < 0) { + LOGE(&i2c->dev, + "Failed to allocate memory\n"); + goto exit; + } + + buf[0] = (unsigned char)addr; + retval = secure_memcpy(&buf[1], + buf_size - 1, + data, + length, + length); + if (retval < 0) { + LOGE(&i2c->dev, + "Failed to copy write data\n"); + goto exit; + } + + msg.addr = bdata->ubl_i2c_addr; + msg.flags = 0; + msg.len = byte_count; + msg.buf = buf; + + for (attempt = 0; attempt < XFER_ATTEMPTS; attempt++) { + if (i2c_transfer(i2c->adapter, &msg, 1) == 1) { + retval = length; + goto exit; + } + LOGE(&i2c->dev, + "Transfer attempt %d failed\n", + attempt + 1); + + if (attempt + 1 == XFER_ATTEMPTS) { + retval = -EIO; + goto exit; + } + + msleep(20); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_i2c_read(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length) +{ + int retval; + unsigned int attempt; + struct i2c_msg msg; + struct i2c_client *i2c = to_i2c_client(tcm_hcd->pdev->dev.parent); + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + msg.addr = i2c->addr; + msg.flags = I2C_M_RD; + msg.len = length; + msg.buf = data; + + for (attempt = 0; attempt < XFER_ATTEMPTS; attempt++) { + if (i2c_transfer(i2c->adapter, &msg, 1) == 1) { + retval = length; + goto exit; + } + LOGE(&i2c->dev, + "Transfer attempt %d failed\n", + attempt + 1); + + if (attempt + 1 == XFER_ATTEMPTS) { + retval = -EIO; + goto exit; + } + + msleep(20); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_i2c_write(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length) +{ + int retval; + unsigned int attempt; + struct i2c_msg msg; + struct i2c_client *i2c = to_i2c_client(tcm_hcd->pdev->dev.parent); + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + msg.addr = i2c->addr; + msg.flags = 0; + msg.len = length; + msg.buf = data; + + for (attempt = 0; attempt < XFER_ATTEMPTS; attempt++) { + if (i2c_transfer(i2c->adapter, &msg, 1) == 1) { + retval = length; + goto exit; + } + LOGE(&i2c->dev, + "Transfer attempt %d failed\n", + attempt + 1); + + if (attempt + 1 == XFER_ATTEMPTS) { + retval = -EIO; + goto exit; + } + + msleep(20); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *dev_id) +{ + int retval; + + syna_tcm_i2c_device = platform_device_alloc(PLATFORM_DRIVER_NAME, 0); + if (!syna_tcm_i2c_device) { + LOGE(&i2c->dev, + "Failed to allocate platform device\n"); + return -ENOMEM; + } + +#ifdef CONFIG_OF + hw_if.bdata = devm_kzalloc(&i2c->dev, sizeof(*hw_if.bdata), GFP_KERNEL); + if (!hw_if.bdata) { + LOGE(&i2c->dev, + "Failed to allocate memory for board data\n"); + return -ENOMEM; + } + parse_dt(&i2c->dev, hw_if.bdata); +#else + hw_if.bdata = i2c->dev.platform_data; +#endif + + bus_io.type = BUS_I2C; + bus_io.read = syna_tcm_i2c_read; + bus_io.write = syna_tcm_i2c_write; + bus_io.rmi_read = syna_tcm_i2c_rmi_read; + bus_io.rmi_write = syna_tcm_i2c_rmi_write; + + hw_if.bus_io = &bus_io; + + syna_tcm_i2c_device->dev.parent = &i2c->dev; + syna_tcm_i2c_device->dev.platform_data = &hw_if; + + retval = platform_device_add(syna_tcm_i2c_device); + if (retval < 0) { + LOGE(&i2c->dev, + "Failed to add platform device\n"); + return retval; + } + + return 0; +} + +static int syna_tcm_i2c_remove(struct i2c_client *i2c) +{ + syna_tcm_i2c_device->dev.platform_data = NULL; + + platform_device_unregister(syna_tcm_i2c_device); + + return 0; +} + +static const struct i2c_device_id syna_tcm_id_table[] = { + {I2C_MODULE_NAME, 0}, + {}, +}; +MODULE_DEVICE_TABLE(i2c, syna_tcm_id_table); + +#ifdef CONFIG_OF +static const struct of_device_id syna_tcm_of_match_table[] = { + { + .compatible = "synaptics,tcm-i2c", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, syna_tcm_of_match_table); +#else +#define syna_tcm_of_match_table NULL +#endif + +static struct i2c_driver syna_tcm_i2c_driver = { + .driver = { + .name = I2C_MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = syna_tcm_of_match_table, + }, + .probe = syna_tcm_i2c_probe, + .remove = syna_tcm_i2c_remove, + .id_table = syna_tcm_id_table, +}; + +int syna_tcm_bus_init(void) +{ + return i2c_add_driver(&syna_tcm_i2c_driver); +} +EXPORT_SYMBOL(syna_tcm_bus_init); + +void syna_tcm_bus_exit(void) +{ + kfree(buf); + + i2c_del_driver(&syna_tcm_i2c_driver); +} +EXPORT_SYMBOL(syna_tcm_bus_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM I2C Bus Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_recovery.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_recovery.c new file mode 100644 index 000000000000..027facbcad79 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_recovery.c @@ -0,0 +1,898 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include "synaptics_tcm_core.h" + +#define SET_UP_RECOVERY_MODE true + +#define ENABLE_SYSFS_INTERFACE true + +#define SYSFS_DIR_NAME "recovery" + +#define IHEX_BUF_SIZE (2048 * 1024) + +#define DATA_BUF_SIZE (512 * 1024) + +#define IHEX_RECORD_SIZE 14 + +#define PDT_START_ADDR 0x00e9 + +#define UBL_FN_NUMBER 0x35 + +#define F35_CHUNK_SIZE 16 + +#define F35_CHUNK_SIZE_WORDS 8 + +#define F35_ERASE_ALL_WAIT_MS 5000 + +#define F35_ERASE_ALL_POLL_MS 100 + +#define F35_DATA5_OFFSET 5 + +#define F35_CTRL3_OFFSET 18 + +#define F35_RESET_COMMAND 16 + +#define F35_ERASE_ALL_COMMAND 3 + +#define F35_WRITE_CHUNK_COMMAND 2 + +#define F35_READ_FLASH_STATUS_COMMAND 1 + +struct rmi_pdt_entry { + unsigned char query_base_addr; + unsigned char command_base_addr; + unsigned char control_base_addr; + unsigned char data_base_addr; + unsigned char intr_src_count:3; + unsigned char reserved_1:2; + unsigned char fn_version:2; + unsigned char reserved_2:1; + unsigned char fn_number; +} __packed; + +struct rmi_addr { + unsigned short query_base; + unsigned short command_base; + unsigned short control_base; + unsigned short data_base; +}; + +struct recovery_hcd { + bool set_up_recovery_mode; + unsigned char chunk_buf[F35_CHUNK_SIZE + 3]; + unsigned char out_buf[3]; + unsigned char *ihex_buf; + unsigned char *data_buf; + unsigned int ihex_size; + unsigned int ihex_records; + unsigned int data_entries; + struct kobject *sysfs_dir; + struct rmi_addr f35_addr; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(recovery_remove_complete); + +static struct recovery_hcd *recovery_hcd; + +static int recovery_do_recovery(void); + +STORE_PROTOTYPE(recovery, recovery); + +static struct device_attribute *attrs[] = { + ATTRIFY(recovery), +}; + +static ssize_t recovery_sysfs_ihex_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static struct bin_attribute bin_attr = { + .attr = { + .name = "ihex", + .mode = 0220, + }, + .size = 0, + .write = recovery_sysfs_ihex_store, +}; + +static ssize_t recovery_sysfs_recovery_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int retval; + unsigned int input; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + if (input == 1) + recovery_hcd->set_up_recovery_mode = true; + else if (input == 2) + recovery_hcd->set_up_recovery_mode = false; + else + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + if (recovery_hcd->ihex_size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get ihex data\n"); + retval = -EINVAL; + goto exit; + } + + if (recovery_hcd->ihex_size % IHEX_RECORD_SIZE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid ihex data\n"); + retval = -EINVAL; + goto exit; + } + + recovery_hcd->ihex_records = recovery_hcd->ihex_size / IHEX_RECORD_SIZE; + + retval = recovery_do_recovery(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do recovery\n"); + goto exit; + } + + retval = count; + +exit: + recovery_hcd->set_up_recovery_mode = SET_UP_RECOVERY_MODE; + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t recovery_sysfs_ihex_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = secure_memcpy(&recovery_hcd->ihex_buf[pos], + IHEX_BUF_SIZE - pos, + buf, + count, + count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy ihex data\n"); + recovery_hcd->ihex_size = 0; + goto exit; + } + + recovery_hcd->ihex_size = pos + count; + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static int recovery_device_reset(void) +{ + int retval; + unsigned char command; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + command = F35_RESET_COMMAND; + + retval = syna_tcm_rmi_write(tcm_hcd, + recovery_hcd->f35_addr.control_base + F35_CTRL3_OFFSET, + &command, + sizeof(command)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write F$35 command\n"); + return retval; + } + + msleep(bdata->reset_delay_ms); + + return 0; +} + +static int recovery_add_data_entry(unsigned char data) +{ + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + if (recovery_hcd->data_entries >= DATA_BUF_SIZE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Reached data buffer size limit\n"); + return -EINVAL; + } + + recovery_hcd->data_buf[recovery_hcd->data_entries++] = data; + + return 0; +} + +static int recovery_add_padding(unsigned int *words) +{ + int retval; + unsigned int padding; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + padding = (F35_CHUNK_SIZE_WORDS - *words % F35_CHUNK_SIZE_WORDS); + padding %= F35_CHUNK_SIZE_WORDS; + + while (padding) { + retval = recovery_add_data_entry(0xff); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + + retval = recovery_add_data_entry(0xff); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + + (*words)++; + padding--; + } + + return 0; +} + +static int recovery_parse_ihex(void) +{ + int retval; + unsigned char colon; + unsigned char *buf; + unsigned int addr; + unsigned int type; + unsigned int addrl; + unsigned int addrh; + unsigned int data0; + unsigned int data1; + unsigned int count; + unsigned int words; + unsigned int offset; + unsigned int record; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + words = 0; + + offset = 0; + + buf = recovery_hcd->ihex_buf; + + recovery_hcd->data_entries = 0; + + for (record = 0; record < recovery_hcd->ihex_records; record++) { + buf[(record + 1) * IHEX_RECORD_SIZE - 1] = 0x00; + retval = sscanf(&buf[record * IHEX_RECORD_SIZE], + "%c%02x%02x%02x%02x%02x%02x", + &colon, + &count, + &addrh, + &addrl, + &type, + &data0, + &data1); + if (retval != 7) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read ihex record\n"); + return -EINVAL; + } + + if (type == 0x00) { + if ((words % F35_CHUNK_SIZE_WORDS) == 0) { + addr = (addrh << 8) + addrl; + addr += offset; + addr >>= 4; + + retval = recovery_add_data_entry(addr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + + retval = recovery_add_data_entry(addr >> 8); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + } + + retval = recovery_add_data_entry(data0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + + retval = recovery_add_data_entry(data1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add data entry\n"); + return retval; + } + + words++; + } else if (type == 0x02) { + retval = recovery_add_padding(&words); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add padding\n"); + return retval; + } + + offset = (data0 << 8) + data1; + offset <<= 4; + } + } + + retval = recovery_add_padding(&words); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to add padding\n"); + return retval; + } + + return 0; +} + +static int recovery_check_status(void) +{ + int retval; + unsigned char status; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + retval = syna_tcm_rmi_read(tcm_hcd, + recovery_hcd->f35_addr.data_base, + &status, + sizeof(status)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read status\n"); + return retval; + } + + status = status & 0x1f; + + if (status != 0x00) { + LOGE(tcm_hcd->pdev->dev.parent, + "Recovery mode status = 0x%02x\n", + status); + return -EINVAL; + } + + return 0; +} + +static int recovery_write_flash(void) +{ + int retval; + unsigned char *data_ptr; + unsigned int chunk_buf_size; + unsigned int chunk_data_size; + unsigned int entries_written; + unsigned int entries_to_write; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + entries_written = 0; + + data_ptr = recovery_hcd->data_buf; + + chunk_buf_size = sizeof(recovery_hcd->chunk_buf); + + chunk_data_size = chunk_buf_size - 1; + + recovery_hcd->chunk_buf[chunk_buf_size - 1] = F35_WRITE_CHUNK_COMMAND; + + while (entries_written < recovery_hcd->data_entries) { + entries_to_write = F35_CHUNK_SIZE + 2; + + retval = secure_memcpy(recovery_hcd->chunk_buf, + chunk_buf_size - 1, + data_ptr, + recovery_hcd->data_entries - entries_written, + entries_to_write); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy chunk data\n"); + return retval; + } + + retval = syna_tcm_rmi_write(tcm_hcd, + recovery_hcd->f35_addr.control_base, + recovery_hcd->chunk_buf, + chunk_buf_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write chunk data\n"); + return retval; + } + + data_ptr += entries_to_write; + entries_written += entries_to_write; + } + + retval = recovery_check_status(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get no error recovery mode status\n"); + return retval; + } + + return 0; +} + +static int recovery_poll_erase_completion(void) +{ + int retval; + unsigned char status; + unsigned char command; + unsigned char data_base; + unsigned int timeout; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + timeout = F35_ERASE_ALL_WAIT_MS; + + data_base = recovery_hcd->f35_addr.data_base; + + do { + command = F35_READ_FLASH_STATUS_COMMAND; + + retval = syna_tcm_rmi_write(tcm_hcd, + recovery_hcd->f35_addr.command_base, + &command, + sizeof(command)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write F$35 command\n"); + return retval; + } + + do { + retval = syna_tcm_rmi_read(tcm_hcd, + recovery_hcd->f35_addr.command_base, + &command, + sizeof(command)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read command status\n"); + return retval; + } + + if (command == 0x00) + break; + + if (timeout == 0) + break; + + msleep(F35_ERASE_ALL_POLL_MS); + timeout -= F35_ERASE_ALL_POLL_MS; + } while (true); + + if (command != 0 && timeout == 0) { + retval = -EINVAL; + goto exit; + } + + retval = syna_tcm_rmi_read(tcm_hcd, + data_base + F35_DATA5_OFFSET, + &status, + sizeof(status)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read flash status\n"); + return retval; + } + + if ((status & 0x01) == 0x00) + break; + + if (timeout == 0) { + retval = -EINVAL; + goto exit; + } + + msleep(F35_ERASE_ALL_POLL_MS); + timeout -= F35_ERASE_ALL_POLL_MS; + } while (true); + + retval = 0; + +exit: + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get erase completion\n"); + } + + return retval; +} + +static int recovery_erase_flash(void) +{ + int retval; + unsigned char command; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + command = F35_ERASE_ALL_COMMAND; + + retval = syna_tcm_rmi_write(tcm_hcd, + recovery_hcd->f35_addr.control_base + F35_CTRL3_OFFSET, + &command, + sizeof(command)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write F$35 command\n"); + return retval; + } + + if (recovery_hcd->f35_addr.command_base) { + retval = recovery_poll_erase_completion(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to wait for erase completion\n"); + return retval; + } + } else { + msleep(F35_ERASE_ALL_WAIT_MS); + } + + retval = recovery_check_status(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get no error recovery mode status\n"); + return retval; + } + + return 0; +} + +static int recovery_set_up_recovery_mode(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + retval = tcm_hcd->identify(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + return retval; + } + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) { + retval = tcm_hcd->switch_mode(tcm_hcd, FW_MODE_BOOTLOADER); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter bootloader mode\n"); + return retval; + } + } + + retval = tcm_hcd->write_message(tcm_hcd, + recovery_hcd->out_buf[0], + &recovery_hcd->out_buf[1], + 2, + NULL, + NULL, + NULL, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_REBOOT_TO_ROM_BOOTLOADER)); + return retval; + } + + msleep(bdata->reset_delay_ms); + + return 0; +} + +static int recovery_do_recovery(void) +{ + int retval; + struct rmi_pdt_entry p_entry; + struct syna_tcm_hcd *tcm_hcd = recovery_hcd->tcm_hcd; + + retval = recovery_parse_ihex(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to parse ihex data\n"); + return retval; + } + + if (recovery_hcd->set_up_recovery_mode) { + retval = recovery_set_up_recovery_mode(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up recovery mode\n"); + return retval; + } + } + + tcm_hcd->update_watchdog(tcm_hcd, false); + + retval = syna_tcm_rmi_read(tcm_hcd, + PDT_START_ADDR, + (unsigned char *)&p_entry, + sizeof(p_entry)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read PDT entry\n"); + return retval; + } + + if (p_entry.fn_number != UBL_FN_NUMBER) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to find F$35\n"); + return -ENODEV; + } + + recovery_hcd->f35_addr.query_base = p_entry.query_base_addr; + recovery_hcd->f35_addr.command_base = p_entry.command_base_addr; + recovery_hcd->f35_addr.control_base = p_entry.control_base_addr; + recovery_hcd->f35_addr.data_base = p_entry.data_base_addr; + + LOGN(tcm_hcd->pdev->dev.parent, + "Start of recovery\n"); + + retval = recovery_erase_flash(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to erase flash\n"); + return retval; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Flash erased\n"); + + retval = recovery_write_flash(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to flash\n"); + return retval; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Flash written\n"); + + retval = recovery_device_reset(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + return retval; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "End of recovery\n"); + + if (recovery_hcd->set_up_recovery_mode) + return 0; + + tcm_hcd->update_watchdog(tcm_hcd, true); + + retval = tcm_hcd->enable_irq(tcm_hcd, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable interrupt\n"); + return retval; + } + + retval = tcm_hcd->identify(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + return retval; + } + + if (tcm_hcd->id_info.mode != MODE_APPLICATION) { + retval = tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + return retval; + } + } + + return 0; +} + +static int recovery_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + int idx; + + recovery_hcd = kzalloc(sizeof(*recovery_hcd), GFP_KERNEL); + if (!recovery_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for recovery_hcd\n"); + return -ENOMEM; + } + + recovery_hcd->ihex_buf = kzalloc(IHEX_BUF_SIZE, GFP_KERNEL); + if (!recovery_hcd->ihex_buf) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for ihex_buf\n"); + goto err_allocate_ihex_buf; + } + + recovery_hcd->data_buf = kzalloc(DATA_BUF_SIZE, GFP_KERNEL); + if (!recovery_hcd->data_buf) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for data_buf\n"); + goto err_allocate_data_buf; + } + + recovery_hcd->tcm_hcd = tcm_hcd; + + recovery_hcd->set_up_recovery_mode = SET_UP_RECOVERY_MODE; + + recovery_hcd->out_buf[0] = CMD_REBOOT_TO_ROM_BOOTLOADER; + recovery_hcd->out_buf[1] = 0; + recovery_hcd->out_buf[2] = 0; + + if (!ENABLE_SYSFS_INTERFACE) + return 0; + + recovery_hcd->sysfs_dir = kobject_create_and_add(SYSFS_DIR_NAME, + tcm_hcd->sysfs_dir); + if (!recovery_hcd->sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dir; + } + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + retval = sysfs_create_file(recovery_hcd->sysfs_dir, + &(*attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs file\n"); + goto err_sysfs_create_file; + } + } + + retval = sysfs_create_bin_file(recovery_hcd->sysfs_dir, &bin_attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs bin file\n"); + goto err_sysfs_create_bin_file; + } + + return 0; + +err_sysfs_create_bin_file: +err_sysfs_create_file: + for (idx--; idx >= 0; idx--) + sysfs_remove_file(recovery_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(recovery_hcd->sysfs_dir); + +err_sysfs_create_dir: + kfree(recovery_hcd->data_buf); +err_allocate_data_buf: + kfree(recovery_hcd->ihex_buf); +err_allocate_ihex_buf: + kfree(recovery_hcd); + recovery_hcd = NULL; + + return retval; +} + +static int recovery_remove(struct syna_tcm_hcd *tcm_hcd) +{ + int idx; + + if (!recovery_hcd) + goto exit; + + if (ENABLE_SYSFS_INTERFACE) { + sysfs_remove_bin_file(recovery_hcd->sysfs_dir, &bin_attr); + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + sysfs_remove_file(recovery_hcd->sysfs_dir, + &(*attrs[idx]).attr); + } + + kobject_put(recovery_hcd->sysfs_dir); + } + + kfree(recovery_hcd->data_buf); + kfree(recovery_hcd->ihex_buf); + kfree(recovery_hcd); + recovery_hcd = NULL; + +exit: + complete(&recovery_remove_complete); + + return 0; +} + +static int recovery_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!recovery_hcd) { + retval = recovery_init(tcm_hcd); + return retval; + } + + return 0; +} + +static struct syna_tcm_module_cb recovery_module = { + .type = TCM_RECOVERY, + .init = recovery_init, + .remove = recovery_remove, + .syncbox = NULL, + .asyncbox = NULL, + .reset = recovery_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init recovery_module_init(void) +{ + return syna_tcm_add_module(&recovery_module, true); +} + +static void __exit recovery_module_exit(void) +{ + syna_tcm_add_module(&recovery_module, false); + + wait_for_completion(&recovery_remove_complete); +} + +module_init(recovery_module_init); +module_exit(recovery_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Recovery Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c new file mode 100644 index 000000000000..2e622fca191e --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c @@ -0,0 +1,2184 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include "synaptics_tcm_core.h" + +#define STARTUP_REFLASH + +#define FORCE_REFLASH false + +#define ENABLE_SYSFS_INTERFACE true + +#define SYSFS_DIR_NAME "reflash" + +#define CUSTOM_DIR_NAME "custom" + +#define FW_IMAGE_NAME "synaptics/firmware.img" + +#define BOOT_CONFIG_ID "BOOT_CONFIG" + +#define APP_CODE_ID "APP_CODE" + +#define PROD_TEST_ID "APP_PROD_TEST" + +#define APP_CONFIG_ID "APP_CONFIG" + +#define DISP_CONFIG_ID "DISPLAY" + +#define FB_READY_COUNT 2 + +#define FB_READY_WAIT_MS 100 + +#define FB_READY_TIMEOUT_S 30 + +#define IMAGE_FILE_MAGIC_VALUE 0x4818472b + +#define FLASH_AREA_MAGIC_VALUE 0x7c05e516 + +#define BOOT_CONFIG_SIZE 8 + +#define BOOT_CONFIG_SLOTS 16 + +#define IMAGE_BUF_SIZE (512 * 1024) + +#define ERASE_FLASH_DELAY_MS 500 + +#define WRITE_FLASH_DELAY_MS 20 + +#define REFLASH (1 << 0) + +#define FORCE_UPDATE (1 << 1) + +#define APP_CFG_UPDATE (1 << 2) + +#define DISP_CFG_UPDATE (1 << 3) + +#define BOOT_CFG_UPDATE (1 << 4) + +#define BOOT_CFG_LOCKDOWN (1 << 5) + +#define reflash_write(p_name) \ +static int reflash_write_##p_name(void) \ +{ \ + int retval; \ + unsigned int size; \ + unsigned int flash_addr; \ + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; \ + const unsigned char *data; \ +\ + data = reflash_hcd->image_info.p_name.data; \ + size = reflash_hcd->image_info.p_name.size; \ + flash_addr = reflash_hcd->image_info.p_name.flash_addr; \ +\ + retval = reflash_write_flash(flash_addr, data, size); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to write to flash\n"); \ + return retval; \ + } \ +\ + return 0; \ +} + +#define reflash_erase(p_name) \ +static int reflash_erase_##p_name(void) \ +{ \ + int retval; \ + unsigned int size; \ + unsigned int flash_addr; \ + unsigned int page_start; \ + unsigned int page_count; \ + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; \ +\ + flash_addr = reflash_hcd->image_info.p_name.flash_addr; \ +\ + page_start = flash_addr / reflash_hcd->page_size; \ +\ + size = reflash_hcd->image_info.p_name.size; \ + page_count = ceil_div(size, reflash_hcd->page_size); \ +\ + LOGD(tcm_hcd->pdev->dev.parent, \ + "Page start = %d\n", \ + page_start); \ +\ + LOGD(tcm_hcd->pdev->dev.parent, \ + "Page count = %d\n", \ + page_count); \ +\ + retval = reflash_erase_flash(page_start, page_count); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to erase flash pages\n"); \ + return retval; \ + } \ +\ + return 0; \ +} + +#define reflash_update(p_name) \ +static int reflash_update_##p_name(bool reset) \ +{ \ + int retval; \ + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; \ +\ + retval = reflash_set_up_flash_access(); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to set up flash access\n"); \ + return retval; \ + } \ +\ + tcm_hcd->update_watchdog(tcm_hcd, false); \ +\ + retval = reflash_check_##p_name(); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed "#p_name" partition check\n"); \ + reset = true; \ + goto reset; \ + } \ +\ + retval = reflash_erase_##p_name(); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to erase "#p_name" partition\n"); \ + reset = true; \ + goto reset; \ + } \ +\ + LOGN(tcm_hcd->pdev->dev.parent, \ + "Partition erased ("#p_name")\n"); \ +\ + retval = reflash_write_##p_name(); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to write "#p_name" partition\n"); \ + reset = true; \ + goto reset; \ + } \ +\ + LOGN(tcm_hcd->pdev->dev.parent, \ + "Partition written ("#p_name")\n"); \ +\ + retval = 0; \ +\ +reset: \ + if (!reset) \ + goto exit; \ +\ + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to do reset\n"); \ + } \ +\ +exit: \ + tcm_hcd->update_watchdog(tcm_hcd, true); \ +\ + return retval; \ +} + +#define reflash_show_data() \ +{ \ + LOCK_BUFFER(reflash_hcd->read); \ +\ + readlen = MIN(count, reflash_hcd->read.data_length - pos); \ +\ + retval = secure_memcpy(buf, \ + count, \ + &reflash_hcd->read.buf[pos], \ + reflash_hcd->read.buf_size - pos, \ + readlen); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to copy read data\n"); \ + } else { \ + retval = readlen; \ + } \ +\ + UNLOCK_BUFFER(reflash_hcd->read); \ +} + +enum update_area { + NONE = 0, + FIRMWARE_CONFIG, + CONFIG_ONLY, +}; + +struct app_config_header { + unsigned short magic_value[4]; + unsigned char checksum[4]; + unsigned char length[2]; + unsigned char build_id[4]; + unsigned char customer_config_id[16]; +}; + +struct area_descriptor { + unsigned char magic_value[4]; + unsigned char id_string[16]; + unsigned char flags[4]; + unsigned char flash_addr_words[4]; + unsigned char length[4]; + unsigned char checksum[4]; +}; + +struct block_data { + const unsigned char *data; + unsigned int size; + unsigned int flash_addr; +}; + +struct image_info { + struct block_data boot_config; + struct block_data app_firmware; + struct block_data prod_test_firmware; + struct block_data app_config; + struct block_data disp_config; +}; + +struct image_header { + unsigned char magic_value[4]; + unsigned char num_of_areas[4]; +}; + +struct boot_config { + union { + unsigned char i2c_address; + struct { + unsigned char cpha:1; + unsigned char cpol:1; + unsigned char word0_b2__7:6; + } __packed; + }; + unsigned char attn_polarity:1; + unsigned char attn_drive:2; + unsigned char attn_pullup:1; + unsigned char word0_b12__14:3; + unsigned char used:1; + unsigned short customer_part_id; + unsigned short boot_timeout; + unsigned short continue_on_reset:1; + unsigned short word3_b1__15:15; +} __packed; + +struct reflash_hcd { + bool force_update; + bool disp_cfg_update; + const unsigned char *image; + unsigned char *image_buf; + unsigned int image_size; + unsigned int page_size; + unsigned int write_block_size; + unsigned int max_write_payload_size; + const struct firmware *fw_entry; + struct mutex reflash_mutex; + struct kobject *sysfs_dir; + struct kobject *custom_dir; + struct work_struct work; + struct workqueue_struct *workqueue; + struct image_info image_info; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_buffer read; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(reflash_remove_complete); + +static struct reflash_hcd *reflash_hcd; + +static int reflash_get_fw_image(void); + +static int reflash_read_data(enum flash_area area, bool run_app_firmware, + struct syna_tcm_buffer *output); + +static int reflash_update_custom_otp(const unsigned char *data, + unsigned int offset, unsigned int datalen); + +static int reflash_update_custom_lcm(const unsigned char *data, + unsigned int offset, unsigned int datalen); + +static int reflash_update_custom_oem(const unsigned char *data, + unsigned int offset, unsigned int datalen); + +static int reflash_update_boot_config(bool lock); + +static int reflash_update_app_config(bool reset); + +static int reflash_update_disp_config(bool reset); + +static int reflash_do_reflash(void); + +STORE_PROTOTYPE(reflash, reflash); + +static struct device_attribute *attrs[] = { + ATTRIFY(reflash), +}; + +static ssize_t reflash_sysfs_image_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_lockdown_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_lockdown_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_lcm_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_lcm_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_oem_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static ssize_t reflash_sysfs_oem_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static struct bin_attribute bin_attrs[] = { + { + .attr = { + .name = "image", + .mode = 0220, + }, + .size = 0, + .write = reflash_sysfs_image_store, + }, + { + .attr = { + .name = "lockdown", + .mode = 0664, + }, + .size = 0, + .read = reflash_sysfs_lockdown_show, + .write = reflash_sysfs_lockdown_store, + }, + { + .attr = { + .name = "lcm", + .mode = 0664, + }, + .size = 0, + .read = reflash_sysfs_lcm_show, + .write = reflash_sysfs_lcm_store, + }, + { + .attr = { + .name = "oem", + .mode = 0664, + }, + .size = 0, + .read = reflash_sysfs_oem_show, + .write = reflash_sysfs_oem_store, + }, +}; + +static ssize_t reflash_sysfs_reflash_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int retval; + unsigned int input; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (kstrtouint(buf, 10, &input)) + return -EINVAL; + + mutex_lock(&tcm_hcd->extif_mutex); + + pm_stay_awake(&tcm_hcd->pdev->dev); + + mutex_lock(&reflash_hcd->reflash_mutex); + + if (reflash_hcd->image_size != 0) + reflash_hcd->image = reflash_hcd->image_buf; + + reflash_hcd->force_update = input & FORCE_UPDATE ? true : false; + + if (input & REFLASH || input & FORCE_UPDATE) { + retval = reflash_do_reflash(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reflash\n"); + goto exit; + } + } + + if ((input & ~(REFLASH | FORCE_UPDATE)) == 0) { + retval = count; + goto exit; + } + + retval = reflash_get_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get firmware image\n"); + goto exit; + } + + if (input & BOOT_CFG_LOCKDOWN) { + retval = reflash_update_boot_config(true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to lockdown boot config\n"); + goto exit; + } + } else if (input & BOOT_CFG_UPDATE) { + retval = reflash_update_boot_config(false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to update boot config\n"); + goto exit; + } + } + + if (input & REFLASH || input & FORCE_UPDATE) { + retval = count; + goto exit; + } + + if (input & DISP_CFG_UPDATE) { + if (input & APP_CFG_UPDATE) + retval = reflash_update_disp_config(false); + else + retval = reflash_update_disp_config(true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash display config\n"); + goto exit; + } + } + + if (input & APP_CFG_UPDATE) { + retval = reflash_update_app_config(true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash application config\n"); + goto exit; + } + } + + retval = count; + +exit: + if (reflash_hcd->fw_entry) { + release_firmware(reflash_hcd->fw_entry); + reflash_hcd->fw_entry = NULL; + } + + reflash_hcd->image = NULL; + reflash_hcd->image_size = 0; + reflash_hcd->force_update = FORCE_REFLASH; + + mutex_unlock(&reflash_hcd->reflash_mutex); + + pm_relax(&tcm_hcd->pdev->dev); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_image_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = secure_memcpy(&reflash_hcd->image_buf[pos], + IMAGE_BUF_SIZE - pos, + buf, + count, + count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy firmware image data\n"); + reflash_hcd->image_size = 0; + goto exit; + } + + reflash_hcd->image_size = pos + count; + + retval = count; + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_lockdown_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + unsigned int readlen; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_read_data(CUSTOM_OTP, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read lockdown data\n"); + goto exit; + } + + reflash_show_data(); + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_lockdown_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + pm_stay_awake(&tcm_hcd->pdev->dev); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_update_custom_otp(buf, pos, count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to update custom OTP data\n"); + goto exit; + } + + retval = count; + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + pm_relax(&tcm_hcd->pdev->dev); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_lcm_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + unsigned int readlen; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_read_data(CUSTOM_LCM, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read LCM data\n"); + goto exit; + } + + reflash_show_data(); + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_lcm_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + pm_stay_awake(&tcm_hcd->pdev->dev); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_update_custom_lcm(buf, pos, count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to update custom LCM data\n"); + goto exit; + } + + retval = count; + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + pm_relax(&tcm_hcd->pdev->dev); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_oem_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + unsigned int readlen; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_read_data(CUSTOM_OEM, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read OEM data\n"); + goto exit; + } + + reflash_show_data(); + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t reflash_sysfs_oem_store(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + pm_stay_awake(&tcm_hcd->pdev->dev); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_update_custom_oem(buf, pos, count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to update custom OEM data\n"); + goto exit; + } + + retval = count; + +exit: + mutex_unlock(&reflash_hcd->reflash_mutex); + + pm_relax(&tcm_hcd->pdev->dev); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static int reflash_set_up_flash_access(void) +{ + int retval; + unsigned int temp; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = tcm_hcd->identify(tcm_hcd, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + return retval; + } + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) { + retval = tcm_hcd->switch_mode(tcm_hcd, FW_MODE_BOOTLOADER); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter bootloader mode\n"); + return retval; + } + } + + temp = tcm_hcd->boot_info.write_block_size_words; + reflash_hcd->write_block_size = temp * 2; + + temp = le2_to_uint(tcm_hcd->boot_info.erase_page_size_words); + reflash_hcd->page_size = temp * 2; + + temp = le2_to_uint(tcm_hcd->boot_info.max_write_payload_size); + reflash_hcd->max_write_payload_size = temp; + + LOGD(tcm_hcd->pdev->dev.parent, + "Write block size = %d\n", + reflash_hcd->write_block_size); + + LOGD(tcm_hcd->pdev->dev.parent, + "Page size = %d\n", + reflash_hcd->page_size); + + LOGD(tcm_hcd->pdev->dev.parent, + "Max write payload size = %d\n", + reflash_hcd->max_write_payload_size); + + if (reflash_hcd->write_block_size > (tcm_hcd->wr_chunk_size - 5)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Write size greater than available chunk space\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_parse_fw_image(void) +{ + unsigned int idx; + unsigned int addr; + unsigned int offset; + unsigned int length; + unsigned int checksum; + unsigned int flash_addr; + unsigned int magic_value; + unsigned int num_of_areas; + struct image_header *header; + struct image_info *image_info; + struct area_descriptor *descriptor; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + const unsigned char *image; + const unsigned char *content; + + image = reflash_hcd->image; + image_info = &reflash_hcd->image_info; + header = (struct image_header *)image; + + reflash_hcd->disp_cfg_update = false; + + magic_value = le4_to_uint(header->magic_value); + if (magic_value != IMAGE_FILE_MAGIC_VALUE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid image file magic value\n"); + return -EINVAL; + } + + memset(image_info, 0x00, sizeof(*image_info)); + + offset = sizeof(*header); + num_of_areas = le4_to_uint(header->num_of_areas); + + for (idx = 0; idx < num_of_areas; idx++) { + addr = le4_to_uint(image + offset); + descriptor = (struct area_descriptor *)(image + addr); + offset += 4; + + magic_value = le4_to_uint(descriptor->magic_value); + if (magic_value != FLASH_AREA_MAGIC_VALUE) + continue; + + length = le4_to_uint(descriptor->length); + content = (unsigned char *)descriptor + sizeof(*descriptor); + flash_addr = le4_to_uint(descriptor->flash_addr_words) * 2; + checksum = le4_to_uint(descriptor->checksum); + + if (!memcmp((char *)descriptor->id_string, + BOOT_CONFIG_ID, + strlen(BOOT_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Boot config checksum error\n"); + return -EINVAL; + } + image_info->boot_config.size = length; + image_info->boot_config.data = content; + image_info->boot_config.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Boot config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Boot config flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + APP_CODE_ID, + strlen(APP_CODE_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "APP firmware checksum error\n"); + return -EINVAL; + } + image_info->app_firmware.size = length; + image_info->app_firmware.data = content; + image_info->app_firmware.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Application firmware size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Application firmware flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + PROD_TEST_ID, + strlen(PROD_TEST_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Production test checksum error\n"); + return -EINVAL; + } + image_info->prod_test_firmware.size = length; + image_info->prod_test_firmware.data = content; + image_info->prod_test_firmware.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Production test firmware size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Production test flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + APP_CONFIG_ID, + strlen(APP_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Application config checksum error\n"); + return -EINVAL; + } + image_info->app_config.size = length; + image_info->app_config.data = content; + image_info->app_config.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Application config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Application config flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + DISP_CONFIG_ID, + strlen(DISP_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Display config checksum error\n"); + return -EINVAL; + } + reflash_hcd->disp_cfg_update = true; + image_info->disp_config.size = length; + image_info->disp_config.data = content; + image_info->disp_config.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Display config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Display config flash address = 0x%08x\n", + flash_addr); + } + } + + return 0; +} + +static int reflash_get_fw_image(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image == NULL) { + retval = request_firmware(&reflash_hcd->fw_entry, FW_IMAGE_NAME, + tcm_hcd->pdev->dev.parent); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to request %s\n", + FW_IMAGE_NAME); + return retval; + } + + LOGD(tcm_hcd->pdev->dev.parent, + "Firmware image size = %d\n", + (unsigned int)reflash_hcd->fw_entry->size); + + reflash_hcd->image = reflash_hcd->fw_entry->data; + reflash_hcd->image_size = reflash_hcd->fw_entry->size; + } + + retval = reflash_parse_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to parse firmware image\n"); + return retval; + } + + return 0; +} + +static enum update_area reflash_compare_id_info(void) +{ + enum update_area update_area; + unsigned int idx; + unsigned int image_fw_id; + unsigned int device_fw_id; + unsigned char *image_config_id; + unsigned char *device_config_id; + struct app_config_header *header; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + const unsigned char *app_config_data; + + update_area = NONE; + + if (reflash_hcd->image_info.app_config.size < sizeof(*header)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid application config in image file\n"); + goto exit; + } + + app_config_data = reflash_hcd->image_info.app_config.data; + header = (struct app_config_header *)app_config_data; + + if (reflash_hcd->force_update) { + update_area = FIRMWARE_CONFIG; + goto exit; + } + + if (tcm_hcd->id_info.mode != MODE_APPLICATION) { + update_area = FIRMWARE_CONFIG; + goto exit; + } + + image_fw_id = le4_to_uint(header->build_id); + device_fw_id = tcm_hcd->packrat_number; + + if (image_fw_id > device_fw_id) { + LOGN(tcm_hcd->pdev->dev.parent, + "Image firmware ID newer than device firmware ID\n"); + update_area = FIRMWARE_CONFIG; + goto exit; + } else if (image_fw_id < device_fw_id) { + LOGN(tcm_hcd->pdev->dev.parent, + "Image firmware ID older than device firmware ID\n"); + update_area = NONE; + goto exit; + } + + image_config_id = header->customer_config_id; + device_config_id = tcm_hcd->app_info.customer_config_id; + + for (idx = 0; idx < 16; idx++) { + if (image_config_id[idx] > device_config_id[idx]) { + LOGN(tcm_hcd->pdev->dev.parent, + "Image config ID newer than device's ID\n"); + update_area = CONFIG_ONLY; + goto exit; + } else if (image_config_id[idx] < device_config_id[idx]) { + LOGN(tcm_hcd->pdev->dev.parent, + "Image config ID older than device's ID\n"); + update_area = NONE; + goto exit; + } + } + + update_area = NONE; + +exit: + if (update_area == NONE) { + LOGN(tcm_hcd->pdev->dev.parent, + "No need to do reflash\n"); + } else { + LOGN(tcm_hcd->pdev->dev.parent, + "Updating %s\n", + update_area == FIRMWARE_CONFIG ? + "firmware and config" : + "config only"); + } + + return update_area; +} + +static int reflash_read_flash(unsigned int address, unsigned char *data, + unsigned int datalen) +{ + int retval; + unsigned int length_words; + unsigned int flash_addr_words; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + LOCK_BUFFER(reflash_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &reflash_hcd->out, + 6); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for reflash_hcd->out.buf\n"); + UNLOCK_BUFFER(reflash_hcd->out); + return retval; + } + + length_words = datalen / 2; + flash_addr_words = address / 2; + + reflash_hcd->out.buf[0] = (unsigned char)flash_addr_words; + reflash_hcd->out.buf[1] = (unsigned char)(flash_addr_words >> 8); + reflash_hcd->out.buf[2] = (unsigned char)(flash_addr_words >> 16); + reflash_hcd->out.buf[3] = (unsigned char)(flash_addr_words >> 24); + reflash_hcd->out.buf[4] = (unsigned char)length_words; + reflash_hcd->out.buf[5] = (unsigned char)(length_words >> 8); + + LOCK_BUFFER(reflash_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_READ_FLASH, + reflash_hcd->out.buf, + 6, + &reflash_hcd->resp.buf, + &reflash_hcd->resp.buf_size, + &reflash_hcd->resp.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_READ_FLASH)); + UNLOCK_BUFFER(reflash_hcd->resp); + UNLOCK_BUFFER(reflash_hcd->out); + return retval; + } + + UNLOCK_BUFFER(reflash_hcd->out); + + if (reflash_hcd->resp.data_length != datalen) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read requested length\n"); + UNLOCK_BUFFER(reflash_hcd->resp); + return -EIO; + } + + retval = secure_memcpy(data, + datalen, + reflash_hcd->resp.buf, + reflash_hcd->resp.buf_size, + datalen); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy read data\n"); + UNLOCK_BUFFER(reflash_hcd->resp); + return retval; + } + + UNLOCK_BUFFER(reflash_hcd->resp); + + return 0; +} + +static int reflash_read_data(enum flash_area area, bool run_app_firmware, + struct syna_tcm_buffer *output) +{ + int retval; + unsigned int temp; + unsigned int addr; + unsigned int length; + struct syna_tcm_app_info *app_info; + struct syna_tcm_boot_info *boot_info; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + switch (area) { + case CUSTOM_LCM: + case CUSTOM_OEM: + case PPDT: + retval = tcm_hcd->get_data_location(tcm_hcd, + area, + &addr, + &length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get data location\n"); + return retval; + } + break; + default: + break; + } + + retval = reflash_set_up_flash_access(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up flash access\n"); + return retval; + } + + app_info = &tcm_hcd->app_info; + boot_info = &tcm_hcd->boot_info; + + switch (area) { + case BOOT_CONFIG: + temp = le2_to_uint(boot_info->boot_config_start_block); + addr = temp * reflash_hcd->write_block_size; + length = BOOT_CONFIG_SIZE * BOOT_CONFIG_SLOTS; + break; + case APP_CONFIG: + temp = le2_to_uint(app_info->app_config_start_write_block); + addr = temp * reflash_hcd->write_block_size; + length = le2_to_uint(app_info->app_config_size); + break; + case DISP_CONFIG: + temp = le4_to_uint(boot_info->display_config_start_block); + addr = temp * reflash_hcd->write_block_size; + temp = le2_to_uint(boot_info->display_config_length_blocks); + length = temp * reflash_hcd->write_block_size; + break; + case CUSTOM_OTP: + temp = le2_to_uint(boot_info->custom_otp_start_block); + addr = temp * reflash_hcd->write_block_size; + temp = le2_to_uint(boot_info->custom_otp_length_blocks); + length = temp * reflash_hcd->write_block_size; + break; + case CUSTOM_LCM: + case CUSTOM_OEM: + case PPDT: + addr *= reflash_hcd->write_block_size; + length *= reflash_hcd->write_block_size; + break; + default: + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid data area\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (addr == 0 || length == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Data area unavailable\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + LOCK_BUFFER(reflash_hcd->read); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &reflash_hcd->read, + length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for read.buf\n"); + UNLOCK_BUFFER(reflash_hcd->read); + goto run_app_firmware; + } + + retval = reflash_read_flash(addr, reflash_hcd->read.buf, length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read from flash\n"); + UNLOCK_BUFFER(reflash_hcd->read); + goto run_app_firmware; + } + + reflash_hcd->read.data_length = length; + + if (output != NULL) { + retval = syna_tcm_alloc_mem(tcm_hcd, + output, + length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for output->buf\n"); + UNLOCK_BUFFER(reflash_hcd->read); + goto run_app_firmware; + } + + retval = secure_memcpy(output->buf, + output->buf_size, + reflash_hcd->read.buf, + reflash_hcd->read.buf_size, + length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy read data\n"); + UNLOCK_BUFFER(reflash_hcd->read); + goto run_app_firmware; + } + + output->data_length = length; + } + + UNLOCK_BUFFER(reflash_hcd->read); + + retval = 0; + +run_app_firmware: + if (!run_app_firmware) + goto exit; + + if (tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + } + +exit: + return retval; +} + +static int reflash_check_boot_config(void) +{ + unsigned int temp; + unsigned int image_addr; + unsigned int device_addr; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image_info.boot_config.size < BOOT_CONFIG_SIZE) { + LOGE(tcm_hcd->pdev->dev.parent, + "No valid boot config in image file\n"); + return -EINVAL; + } + + image_addr = reflash_hcd->image_info.boot_config.flash_addr; + + temp = le2_to_uint(tcm_hcd->boot_info.boot_config_start_block); + device_addr = temp * reflash_hcd->write_block_size; + + if (image_addr != device_addr) { + LOGE(tcm_hcd->pdev->dev.parent, + "Flash address mismatch\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_check_app_config(void) +{ + unsigned int temp; + unsigned int image_addr; + unsigned int image_size; + unsigned int device_addr; + unsigned int device_size; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image_info.app_config.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No application config in image file\n"); + return -EINVAL; + } + + image_addr = reflash_hcd->image_info.app_config.flash_addr; + image_size = reflash_hcd->image_info.app_config.size; + + temp = le2_to_uint(tcm_hcd->app_info.app_config_start_write_block); + device_addr = temp * reflash_hcd->write_block_size; + device_size = le2_to_uint(tcm_hcd->app_info.app_config_size); + + if (device_addr == 0 && device_size == 0) + return 0; + + if (image_addr != device_addr) { + LOGE(tcm_hcd->pdev->dev.parent, + "Flash address mismatch\n"); + return -EINVAL; + } + + if (image_size != device_size) { + LOGE(tcm_hcd->pdev->dev.parent, + "Config size mismatch\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_check_disp_config(void) +{ + unsigned int temp; + unsigned int image_addr; + unsigned int image_size; + unsigned int device_addr; + unsigned int device_size; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image_info.disp_config.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No display config in image file\n"); + return -EINVAL; + } + + image_addr = reflash_hcd->image_info.disp_config.flash_addr; + image_size = reflash_hcd->image_info.disp_config.size; + + temp = le4_to_uint(tcm_hcd->boot_info.display_config_start_block); + device_addr = temp * reflash_hcd->write_block_size; + + temp = le2_to_uint(tcm_hcd->boot_info.display_config_length_blocks); + device_size = temp * reflash_hcd->write_block_size; + + if (image_addr != device_addr) { + LOGE(tcm_hcd->pdev->dev.parent, + "Flash address mismatch\n"); + return -EINVAL; + } + + if (image_size != device_size) { + LOGE(tcm_hcd->pdev->dev.parent, + "Config size mismatch\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_check_prod_test_firmware(void) +{ + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image_info.prod_test_firmware.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No production test firmware in image file\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_check_app_firmware(void) +{ + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + if (reflash_hcd->image_info.app_firmware.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No application firmware in image file\n"); + return -EINVAL; + } + + return 0; +} + +static int reflash_write_flash(unsigned int address, const unsigned char *data, + unsigned int datalen) +{ + int retval; + unsigned int offset; + unsigned int w_length; + unsigned int xfer_length; + unsigned int remaining_length; + unsigned int flash_address; + unsigned int block_address; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + w_length = tcm_hcd->wr_chunk_size - 5; + + w_length = w_length - (w_length % reflash_hcd->write_block_size); + + w_length = MIN(w_length, reflash_hcd->max_write_payload_size); + + offset = 0; + + remaining_length = datalen; + + LOCK_BUFFER(reflash_hcd->out); + LOCK_BUFFER(reflash_hcd->resp); + + while (remaining_length) { + if (remaining_length > w_length) + xfer_length = w_length; + else + xfer_length = remaining_length; + + retval = syna_tcm_alloc_mem(tcm_hcd, + &reflash_hcd->out, + xfer_length + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + UNLOCK_BUFFER(reflash_hcd->resp); + UNLOCK_BUFFER(reflash_hcd->out); + return retval; + } + + flash_address = address + offset; + block_address = flash_address / reflash_hcd->write_block_size; + reflash_hcd->out.buf[0] = (unsigned char)block_address; + reflash_hcd->out.buf[1] = (unsigned char)(block_address >> 8); + + retval = secure_memcpy(&reflash_hcd->out.buf[2], + reflash_hcd->out.buf_size - 2, + &data[offset], + datalen - offset, + xfer_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy write data\n"); + UNLOCK_BUFFER(reflash_hcd->resp); + UNLOCK_BUFFER(reflash_hcd->out); + return retval; + } + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_WRITE_FLASH, + reflash_hcd->out.buf, + xfer_length + 2, + &reflash_hcd->resp.buf, + &reflash_hcd->resp.buf_size, + &reflash_hcd->resp.data_length, + NULL, + WRITE_FLASH_DELAY_MS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_WRITE_FLASH)); + LOGE(tcm_hcd->pdev->dev.parent, + "Flash address = 0x%08x\n", + flash_address); + LOGE(tcm_hcd->pdev->dev.parent, + "Data length = %d\n", + xfer_length); + UNLOCK_BUFFER(reflash_hcd->resp); + UNLOCK_BUFFER(reflash_hcd->out); + return retval; + } + + offset += xfer_length; + remaining_length -= xfer_length; + } + + UNLOCK_BUFFER(reflash_hcd->resp); + UNLOCK_BUFFER(reflash_hcd->out); + + return 0; +} + +reflash_write(app_config) + +reflash_write(disp_config) + +reflash_write(prod_test_firmware) + +reflash_write(app_firmware) + +static int reflash_erase_flash(unsigned int page_start, unsigned int page_count) +{ + int retval; + unsigned char out_buf[2]; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + out_buf[0] = (unsigned char)page_start; + out_buf[1] = (unsigned char)page_count; + + LOCK_BUFFER(reflash_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_ERASE_FLASH, + out_buf, + sizeof(out_buf), + &reflash_hcd->resp.buf, + &reflash_hcd->resp.buf_size, + &reflash_hcd->resp.data_length, + NULL, + ERASE_FLASH_DELAY_MS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_ERASE_FLASH)); + UNLOCK_BUFFER(reflash_hcd->resp); + return retval; + } + + UNLOCK_BUFFER(reflash_hcd->resp); + + return 0; +} + +reflash_erase(app_config) + +reflash_erase(disp_config) + +reflash_erase(prod_test_firmware) + +reflash_erase(app_firmware) + +static int reflash_update_custom_otp(const unsigned char *data, + unsigned int offset, unsigned int datalen) +{ + int retval; + unsigned int temp; + unsigned int addr; + unsigned int length; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = reflash_set_up_flash_access(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up flash access\n"); + return retval; + } + + tcm_hcd->update_watchdog(tcm_hcd, false); + + temp = le2_to_uint(tcm_hcd->boot_info.custom_otp_start_block); + addr = temp * reflash_hcd->write_block_size; + + temp = le2_to_uint(tcm_hcd->boot_info.custom_otp_length_blocks); + length = temp * reflash_hcd->write_block_size; + + if (addr == 0 || length == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Data area unavailable\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (datalen + offset > length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid data length\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + retval = reflash_write_flash(addr + offset, + data, + datalen); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to flash\n"); + goto run_app_firmware; + } + + retval = 0; + +run_app_firmware: + if (tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + } + + tcm_hcd->update_watchdog(tcm_hcd, true); + + return retval; +} + +static int reflash_update_custom_lcm(const unsigned char *data, + unsigned int offset, unsigned int datalen) +{ + int retval; + unsigned int addr; + unsigned int length; + unsigned int page_start; + unsigned int page_count; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = tcm_hcd->get_data_location(tcm_hcd, + CUSTOM_LCM, + &addr, + &length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get data location\n"); + return retval; + } + + retval = reflash_set_up_flash_access(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up flash access\n"); + return retval; + } + + tcm_hcd->update_watchdog(tcm_hcd, false); + + addr *= reflash_hcd->write_block_size; + length *= reflash_hcd->write_block_size; + + if (addr == 0 || length == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Data area unavailable\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (datalen + offset > length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid data length\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (offset == 0) { + page_start = addr / reflash_hcd->page_size; + + page_count = ceil_div(length, reflash_hcd->page_size); + + retval = reflash_erase_flash(page_start, page_count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to erase flash pages\n"); + goto run_app_firmware; + } + } + + retval = reflash_write_flash(addr + offset, + data, + datalen); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to flash\n"); + goto run_app_firmware; + } + + retval = 0; + +run_app_firmware: + if (tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + } + + tcm_hcd->update_watchdog(tcm_hcd, true); + + return retval; +} + +static int reflash_update_custom_oem(const unsigned char *data, + unsigned int offset, unsigned int datalen) +{ + int retval; + unsigned int addr; + unsigned int length; + unsigned int page_start; + unsigned int page_count; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = tcm_hcd->get_data_location(tcm_hcd, + CUSTOM_OEM, + &addr, + &length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get data location\n"); + return retval; + } + + retval = reflash_set_up_flash_access(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up flash access\n"); + return retval; + } + + tcm_hcd->update_watchdog(tcm_hcd, false); + + addr *= reflash_hcd->write_block_size; + length *= reflash_hcd->write_block_size; + + if (addr == 0 || length == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Data area unavailable\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (datalen + offset > length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid data length\n"); + retval = -EINVAL; + goto run_app_firmware; + } + + if (offset == 0) { + page_start = addr / reflash_hcd->page_size; + + page_count = ceil_div(length, reflash_hcd->page_size); + + retval = reflash_erase_flash(page_start, page_count); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to erase flash pages\n"); + goto run_app_firmware; + } + } + + retval = reflash_write_flash(addr + offset, + data, + datalen); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to flash\n"); + goto run_app_firmware; + } + + retval = 0; + +run_app_firmware: + if (tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + } + + tcm_hcd->update_watchdog(tcm_hcd, true); + + return retval; +} + +static int reflash_update_boot_config(bool lock) +{ + int retval; + unsigned char slot_used; + unsigned int idx; + unsigned int addr; + struct boot_config *data; + struct boot_config *last_slot; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = reflash_set_up_flash_access(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up flash access\n"); + return retval; + } + + tcm_hcd->update_watchdog(tcm_hcd, false); + + retval = reflash_check_boot_config(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed boot_config partition check\n"); + goto reset; + } + + retval = reflash_read_data(BOOT_CONFIG, false, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read boot config\n"); + goto reset; + } + + LOCK_BUFFER(reflash_hcd->read); + + data = (struct boot_config *)reflash_hcd->read.buf; + last_slot = data + (BOOT_CONFIG_SLOTS - 1); + slot_used = tcm_hcd->id_info.mode == MODE_TDDI_BOOTLOADER ? 0 : 1; + + if (last_slot->used == slot_used) { + LOGE(tcm_hcd->pdev->dev.parent, + "Boot config already locked down\n"); + UNLOCK_BUFFER(reflash_hcd->read); + goto reset; + } + + if (lock) { + idx = BOOT_CONFIG_SLOTS - 1; + } else { + for (idx = 0; idx < BOOT_CONFIG_SLOTS; idx++) { + if (data->used == slot_used) { + data++; + continue; + } else { + break; + } + } + } + + UNLOCK_BUFFER(reflash_hcd->read); + + if (idx == BOOT_CONFIG_SLOTS) { + LOGE(tcm_hcd->pdev->dev.parent, + "No free boot config slot available\n"); + goto reset; + } + + addr += idx * BOOT_CONFIG_SIZE; + + retval = reflash_write_flash(addr, + reflash_hcd->image_info.boot_config.data, + BOOT_CONFIG_SIZE); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write to flash\n"); + goto reset; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Slot %d updated with new boot config\n", + idx); + + retval = 0; + +reset: + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + + tcm_hcd->update_watchdog(tcm_hcd, true); + + return retval; +} + +reflash_update(app_config) + +reflash_update(disp_config) + +reflash_update(prod_test_firmware) + +reflash_update(app_firmware) + +static int reflash_do_reflash(void) +{ + int retval; + enum update_area update_area; + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + + retval = reflash_get_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get firmware image\n"); + goto exit; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Start of reflash\n"); + + update_area = reflash_compare_id_info(); + + switch (update_area) { + case FIRMWARE_CONFIG: + retval = reflash_update_app_firmware(false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash application firmware\n"); + goto exit; + } + memset(&tcm_hcd->app_info, 0x00, sizeof(tcm_hcd->app_info)); + if (tcm_hcd->features.dual_firmware) { + retval = reflash_update_prod_test_firmware(false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash production test\n"); + goto exit; + } + } + case CONFIG_ONLY: + if (reflash_hcd->disp_cfg_update) { + retval = reflash_update_disp_config(false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash display config\n"); + goto exit; + } + } + retval = reflash_update_app_config(true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to reflash application config\n"); + goto exit; + } + break; + case NONE: + default: + break; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "End of reflash\n"); + + retval = 0; + +exit: + if (reflash_hcd->fw_entry) { + release_firmware(reflash_hcd->fw_entry); + reflash_hcd->fw_entry = NULL; + reflash_hcd->image = NULL; + reflash_hcd->image_size = 0; + } + + return retval; +} + +#ifdef STARTUP_REFLASH +static void reflash_startup_work(struct work_struct *work) +{ + int retval; +#if defined(CONFIG_DRM) || defined(CONFIG_FB) + unsigned int timeout; +#endif + struct syna_tcm_hcd *tcm_hcd = reflash_hcd->tcm_hcd; + +#if defined(CONFIG_DRM) || defined(CONFIG_FB) + timeout = FB_READY_TIMEOUT_S * 1000 / FB_READY_WAIT_MS; + + while (tcm_hcd->fb_ready != FB_READY_COUNT) { + if (timeout == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Timed out waiting for FB ready\n"); + return; + } + msleep(FB_READY_WAIT_MS); + timeout--; + } +#endif + + pm_stay_awake(&tcm_hcd->pdev->dev); + + mutex_lock(&reflash_hcd->reflash_mutex); + + retval = reflash_do_reflash(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reflash\n"); + } + + mutex_unlock(&reflash_hcd->reflash_mutex); + + pm_relax(&tcm_hcd->pdev->dev); +} +#endif + +static int reflash_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + int idx; + + reflash_hcd = kzalloc(sizeof(*reflash_hcd), GFP_KERNEL); + if (!reflash_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for reflash_hcd\n"); + return -ENOMEM; + } + + reflash_hcd->image_buf = kzalloc(IMAGE_BUF_SIZE, GFP_KERNEL); + if (!reflash_hcd->image_buf) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for image_buf\n"); + goto err_allocate_memory; + } + + reflash_hcd->tcm_hcd = tcm_hcd; + + reflash_hcd->force_update = FORCE_REFLASH; + + mutex_init(&reflash_hcd->reflash_mutex); + + INIT_BUFFER(reflash_hcd->out, false); + INIT_BUFFER(reflash_hcd->resp, false); + INIT_BUFFER(reflash_hcd->read, false); + +#ifdef STARTUP_REFLASH + reflash_hcd->workqueue = + create_singlethread_workqueue("syna_tcm_reflash"); + INIT_WORK(&reflash_hcd->work, reflash_startup_work); + queue_work(reflash_hcd->workqueue, &reflash_hcd->work); +#endif + + if (!ENABLE_SYSFS_INTERFACE) + return 0; + + reflash_hcd->sysfs_dir = kobject_create_and_add(SYSFS_DIR_NAME, + tcm_hcd->sysfs_dir); + if (!reflash_hcd->sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dir; + } + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + retval = sysfs_create_file(reflash_hcd->sysfs_dir, + &(*attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs file\n"); + goto err_sysfs_create_file; + } + } + + retval = sysfs_create_bin_file(reflash_hcd->sysfs_dir, &bin_attrs[0]); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs bin file\n"); + goto err_sysfs_create_bin_file; + } + + reflash_hcd->custom_dir = kobject_create_and_add(CUSTOM_DIR_NAME, + reflash_hcd->sysfs_dir); + if (!reflash_hcd->custom_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create custom sysfs directory\n"); + retval = -EINVAL; + goto err_custom_sysfs_create_dir; + } + + for (idx = 1; idx < ARRAY_SIZE(bin_attrs); idx++) { + retval = sysfs_create_bin_file(reflash_hcd->custom_dir, + &bin_attrs[idx]); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs bin file\n"); + goto err_custom_sysfs_create_bin_file; + } + } + + tcm_hcd->read_flash_data = reflash_read_data; + + return 0; + +err_custom_sysfs_create_bin_file: + for (idx--; idx > 0; idx--) + sysfs_remove_bin_file(reflash_hcd->custom_dir, &bin_attrs[idx]); + + kobject_put(reflash_hcd->custom_dir); + + idx = ARRAY_SIZE(attrs); + +err_custom_sysfs_create_dir: + sysfs_remove_bin_file(reflash_hcd->sysfs_dir, &bin_attrs[0]); + +err_sysfs_create_bin_file: +err_sysfs_create_file: + for (idx--; idx >= 0; idx--) + sysfs_remove_file(reflash_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(reflash_hcd->sysfs_dir); + +err_sysfs_create_dir: +err_allocate_memory: + kfree(reflash_hcd->image_buf); + + RELEASE_BUFFER(reflash_hcd->read); + RELEASE_BUFFER(reflash_hcd->resp); + RELEASE_BUFFER(reflash_hcd->out); + + kfree(reflash_hcd); + reflash_hcd = NULL; + + return retval; +} + +static int reflash_remove(struct syna_tcm_hcd *tcm_hcd) +{ + int idx; + + if (!reflash_hcd) + goto exit; + + tcm_hcd->read_flash_data = NULL; + + if (ENABLE_SYSFS_INTERFACE) { + for (idx = 1; idx < ARRAY_SIZE(bin_attrs); idx++) { + sysfs_remove_bin_file(reflash_hcd->custom_dir, + &bin_attrs[idx]); + } + + kobject_put(reflash_hcd->custom_dir); + + sysfs_remove_bin_file(reflash_hcd->sysfs_dir, &bin_attrs[0]); + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + sysfs_remove_file(reflash_hcd->sysfs_dir, + &(*attrs[idx]).attr); + } + + kobject_put(reflash_hcd->sysfs_dir); + } + +#ifdef STARTUP_REFLASH + cancel_work_sync(&reflash_hcd->work); + flush_workqueue(reflash_hcd->workqueue); + destroy_workqueue(reflash_hcd->workqueue); +#endif + + kfree(reflash_hcd->image_buf); + + RELEASE_BUFFER(reflash_hcd->read); + RELEASE_BUFFER(reflash_hcd->resp); + RELEASE_BUFFER(reflash_hcd->out); + + kfree(reflash_hcd); + reflash_hcd = NULL; + +exit: + complete(&reflash_remove_complete); + + return 0; +} + +static int reflash_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!reflash_hcd) { + retval = reflash_init(tcm_hcd); + return retval; + } + + return 0; +} + +static struct syna_tcm_module_cb reflash_module = { + .type = TCM_REFLASH, + .init = reflash_init, + .remove = reflash_remove, + .syncbox = NULL, + .asyncbox = NULL, + .reset = reflash_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init reflash_module_init(void) +{ + return syna_tcm_add_module(&reflash_module, true); +} + +static void __exit reflash_module_exit(void) +{ + syna_tcm_add_module(&reflash_module, false); + + wait_for_completion(&reflash_remove_complete); +} + +module_init(reflash_module_init); +module_exit(reflash_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Reflash Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_spi.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_spi.c new file mode 100644 index 000000000000..e54269c0f333 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_spi.c @@ -0,0 +1,670 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include "synaptics_tcm_core.h" + +static unsigned char *buf; + +static unsigned int buf_size; + +static struct spi_transfer *xfer; + +static struct syna_tcm_bus_io bus_io; + +static struct syna_tcm_hw_interface hw_if; + +static struct platform_device *syna_tcm_spi_device; + +#ifdef CONFIG_OF +static int parse_dt(struct device *dev, struct syna_tcm_board_data *bdata) +{ + int retval; + u32 value; + struct property *prop; + struct device_node *np = dev->of_node; + const char *name; + + prop = of_find_property(np, "synaptics,irq-gpio", NULL); + if (prop && prop->length) { + bdata->irq_gpio = of_get_named_gpio_flags(np, + "synaptics,irq-gpio", 0, + (enum of_gpio_flags *)&bdata->irq_flags); + } else { + bdata->irq_gpio = -1; + } + + retval = of_property_read_u32(np, "synaptics,irq-on-state", &value); + if (retval < 0) + bdata->irq_on_state = 0; + else + bdata->irq_on_state = value; + + retval = of_property_read_string(np, "synaptics,pwr-reg-name", &name); + if (retval < 0) + bdata->pwr_reg_name = NULL; + else + bdata->pwr_reg_name = name; + + retval = of_property_read_string(np, "synaptics,bus-reg-name", &name); + if (retval < 0) + bdata->bus_reg_name = NULL; + else + bdata->bus_reg_name = name; + + prop = of_find_property(np, "synaptics,power-gpio", NULL); + if (prop && prop->length) { + bdata->power_gpio = of_get_named_gpio_flags(np, + "synaptics,power-gpio", 0, NULL); + } else { + bdata->power_gpio = -1; + } + + prop = of_find_property(np, "synaptics,power-on-state", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,power-on-state", + &value); + if (retval < 0) { + LOGE(dev, + "Failed to read synaptics,power-on-state\n"); + return retval; + } + bdata->power_on_state = value; + } else { + bdata->power_on_state = 0; + } + + prop = of_find_property(np, "synaptics,power-delay-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,power-delay-ms", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,power-delay-ms\n"); + return retval; + } + bdata->power_delay_ms = value; + } else { + bdata->power_delay_ms = 0; + } + + prop = of_find_property(np, "synaptics,reset-gpio", NULL); + if (prop && prop->length) { + bdata->reset_gpio = of_get_named_gpio_flags(np, + "synaptics,reset-gpio", 0, NULL); + } else { + bdata->reset_gpio = -1; + } + + prop = of_find_property(np, "synaptics,reset-on-state", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-on-state", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,reset-on-state\n"); + return retval; + } + bdata->reset_on_state = value; + } else { + bdata->reset_on_state = 0; + } + + prop = of_find_property(np, "synaptics,reset-active-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-active-ms", + &value); + if (retval < 0) { + LOGE(dev, "Failed to read synaptics,reset-active-ms\n"); + return retval; + } + bdata->reset_active_ms = value; + } else { + bdata->reset_active_ms = 0; + } + + prop = of_find_property(np, "synaptics,reset-delay-ms", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,reset-delay-ms", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,reset-delay-ms\n"); + return retval; + } + bdata->reset_delay_ms = value; + } else { + bdata->reset_delay_ms = 0; + } + + prop = of_find_property(np, "synaptics,x-flip", NULL); + bdata->x_flip = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,y-flip", NULL); + bdata->y_flip = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,swap-axes", NULL); + bdata->swap_axes = prop > 0 ? true : false; + + prop = of_find_property(np, "synaptics,byte-delay-us", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,byte-delay-us", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,byte-delay-us\n"); + return retval; + } + bdata->byte_delay_us = value; + } else { + bdata->byte_delay_us = 0; + } + + prop = of_find_property(np, "synaptics,block-delay-us", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,block-delay-us", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,block-delay-us\n"); + return retval; + } + bdata->block_delay_us = value; + } else { + bdata->block_delay_us = 0; + } + + prop = of_find_property(np, "synaptics,spi-mode", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,spi-mode", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,spi-mode\n"); + return retval; + } + bdata->spi_mode = value; + + } else { + bdata->spi_mode = 0; + } + + prop = of_find_property(np, "synaptics,ubl-max-freq", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,ubl-max-freq", + &value); + if (retval < 0) { + LOGE(dev, "Unable to read synaptics,ubl-max-freq\n"); + return retval; + } + bdata->ubl_max_freq = value; + } else { + bdata->ubl_max_freq = 0; + } + + prop = of_find_property(np, "synaptics,ubl-byte-delay-us", NULL); + if (prop && prop->length) { + retval = of_property_read_u32(np, "synaptics,ubl-byte-delay-us", + &value); + if (retval < 0) { + LOGE(dev, + "Unable to read synaptics,ubl-byte-delay-us\n"); + return retval; + } + bdata->ubl_byte_delay_us = value; + } else { + bdata->ubl_byte_delay_us = 0; + } + + return 0; +} +#endif + +static int syna_tcm_spi_alloc_mem(struct syna_tcm_hcd *tcm_hcd, + unsigned int count, unsigned int size) +{ + static unsigned int xfer_count; + struct spi_device *spi = to_spi_device(tcm_hcd->pdev->dev.parent); + + if (count > xfer_count) { + kfree(xfer); + xfer = kcalloc(count, sizeof(*xfer), GFP_KERNEL); + if (!xfer) { + LOGE(&spi->dev, + "Failed to allocate memory for xfer\n"); + xfer_count = 0; + return -ENOMEM; + } + xfer_count = count; + } else { + memset(xfer, 0, count * sizeof(*xfer)); + } + + if (size > buf_size) { + if (buf_size) + kfree(buf); + buf = kmalloc(size, GFP_KERNEL); + if (!buf) { + LOGE(&spi->dev, + "Failed to allocate memory for buf\n"); + buf_size = 0; + return -ENOMEM; + } + buf_size = size; + } + + return 0; +} + +static int syna_tcm_spi_rmi_read(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + int retval; + unsigned int idx; + unsigned int mode; + unsigned int byte_count; + struct spi_message msg; + struct spi_device *spi = to_spi_device(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + spi_message_init(&msg); + + byte_count = length + 2; + + if (bdata->ubl_byte_delay_us == 0) + retval = syna_tcm_spi_alloc_mem(tcm_hcd, 2, byte_count); + else + retval = syna_tcm_spi_alloc_mem(tcm_hcd, byte_count, 3); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to allocate memory\n"); + goto exit; + } + + buf[0] = (unsigned char)(addr >> 8) | 0x80; + buf[1] = (unsigned char)addr; + + if (bdata->ubl_byte_delay_us == 0) { + xfer[0].len = 2; + xfer[0].tx_buf = buf; + xfer[0].speed_hz = bdata->ubl_max_freq; + spi_message_add_tail(&xfer[0], &msg); + memset(&buf[2], 0xff, length); + xfer[1].len = length; + xfer[1].tx_buf = &buf[2]; + xfer[1].rx_buf = data; + if (bdata->block_delay_us) + xfer[1].delay_usecs = bdata->block_delay_us; + xfer[1].speed_hz = bdata->ubl_max_freq; + spi_message_add_tail(&xfer[1], &msg); + } else { + buf[2] = 0xff; + for (idx = 0; idx < byte_count; idx++) { + xfer[idx].len = 1; + if (idx < 2) { + xfer[idx].tx_buf = &buf[idx]; + } else { + xfer[idx].tx_buf = &buf[2]; + xfer[idx].rx_buf = &data[idx - 2]; + } + xfer[idx].delay_usecs = bdata->ubl_byte_delay_us; + if (bdata->block_delay_us && (idx == byte_count - 1)) + xfer[idx].delay_usecs = bdata->block_delay_us; + xfer[idx].speed_hz = bdata->ubl_max_freq; + spi_message_add_tail(&xfer[idx], &msg); + } + } + + mode = spi->mode; + spi->mode = SPI_MODE_3; + + retval = spi_sync(spi, &msg); + if (retval == 0) { + retval = length; + } else { + LOGE(&spi->dev, + "Failed to complete SPI transfer, error = %d\n", + retval); + } + + spi->mode = mode; + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_spi_rmi_write(struct syna_tcm_hcd *tcm_hcd, + unsigned short addr, unsigned char *data, unsigned int length) +{ + int retval; + unsigned int mode; + unsigned int byte_count; + struct spi_message msg; + struct spi_device *spi = to_spi_device(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + spi_message_init(&msg); + + byte_count = length + 2; + + retval = syna_tcm_spi_alloc_mem(tcm_hcd, 1, byte_count); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to allocate memory\n"); + goto exit; + } + + buf[0] = (unsigned char)(addr >> 8) & ~0x80; + buf[1] = (unsigned char)addr; + retval = secure_memcpy(&buf[2], + buf_size - 2, + data, + length, + length); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to copy write data\n"); + goto exit; + } + + xfer[0].len = byte_count; + xfer[0].tx_buf = buf; + if (bdata->block_delay_us) + xfer[0].delay_usecs = bdata->block_delay_us; + spi_message_add_tail(&xfer[0], &msg); + + mode = spi->mode; + spi->mode = SPI_MODE_3; + + retval = spi_sync(spi, &msg); + if (retval == 0) { + retval = length; + } else { + LOGE(&spi->dev, + "Failed to complete SPI transfer, error = %d\n", + retval); + } + + spi->mode = mode; + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_spi_read(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length) +{ + int retval; + unsigned int idx; + struct spi_message msg; + struct spi_device *spi = to_spi_device(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + spi_message_init(&msg); + + if (bdata->byte_delay_us == 0) + retval = syna_tcm_spi_alloc_mem(tcm_hcd, 1, length); + else + retval = syna_tcm_spi_alloc_mem(tcm_hcd, length, 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory\n"); + goto exit; + } + + if (bdata->byte_delay_us == 0) { + memset(buf, 0xff, length); + xfer[0].len = length; + xfer[0].tx_buf = buf; + xfer[0].rx_buf = data; + if (bdata->block_delay_us) + xfer[0].delay_usecs = bdata->block_delay_us; + spi_message_add_tail(&xfer[0], &msg); + } else { + buf[0] = 0xff; + for (idx = 0; idx < length; idx++) { + xfer[idx].len = 1; + xfer[idx].tx_buf = buf; + xfer[idx].rx_buf = &data[idx]; + xfer[idx].delay_usecs = bdata->byte_delay_us; + if (bdata->block_delay_us && (idx == length - 1)) + xfer[idx].delay_usecs = bdata->block_delay_us; + spi_message_add_tail(&xfer[idx], &msg); + } + } + + retval = spi_sync(spi, &msg); + if (retval == 0) { + retval = length; + } else { + LOGE(&spi->dev, + "Failed to complete SPI transfer, error = %d\n", + retval); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_spi_write(struct syna_tcm_hcd *tcm_hcd, unsigned char *data, + unsigned int length) +{ + int retval; + unsigned int idx; + struct spi_message msg; + struct spi_device *spi = to_spi_device(tcm_hcd->pdev->dev.parent); + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + mutex_lock(&tcm_hcd->io_ctrl_mutex); + + spi_message_init(&msg); + + if (bdata->byte_delay_us == 0) + retval = syna_tcm_spi_alloc_mem(tcm_hcd, 1, 0); + else + retval = syna_tcm_spi_alloc_mem(tcm_hcd, length, 0); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to allocate memory\n"); + goto exit; + } + + if (bdata->byte_delay_us == 0) { + xfer[0].len = length; + xfer[0].tx_buf = data; + if (bdata->block_delay_us) + xfer[0].delay_usecs = bdata->block_delay_us; + spi_message_add_tail(&xfer[0], &msg); + } else { + for (idx = 0; idx < length; idx++) { + xfer[idx].len = 1; + xfer[idx].tx_buf = &data[idx]; + xfer[idx].delay_usecs = bdata->byte_delay_us; + if (bdata->block_delay_us && (idx == length - 1)) + xfer[idx].delay_usecs = bdata->block_delay_us; + spi_message_add_tail(&xfer[idx], &msg); + } + } + + retval = spi_sync(spi, &msg); + if (retval == 0) { + retval = length; + } else { + LOGE(&spi->dev, + "Failed to complete SPI transfer, error = %d\n", + retval); + } + +exit: + mutex_unlock(&tcm_hcd->io_ctrl_mutex); + + return retval; +} + +static int syna_tcm_spi_probe(struct spi_device *spi) +{ + int retval; + + if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) { + LOGE(&spi->dev, + "Full duplex not supported by host\n"); + return -EIO; + } + + syna_tcm_spi_device = platform_device_alloc(PLATFORM_DRIVER_NAME, 0); + if (!syna_tcm_spi_device) { + LOGE(&spi->dev, + "Failed to allocate platform device\n"); + return -ENOMEM; + } + +#ifdef CONFIG_OF + hw_if.bdata = devm_kzalloc(&spi->dev, sizeof(*hw_if.bdata), GFP_KERNEL); + if (!hw_if.bdata) { + LOGE(&spi->dev, + "Failed to allocate memory for board data\n"); + return -ENOMEM; + } + parse_dt(&spi->dev, hw_if.bdata); +#else + hw_if.bdata = spi->dev.platform_data; +#endif + + switch (hw_if.bdata->spi_mode) { + case 0: + spi->mode = SPI_MODE_0; + break; + case 1: + spi->mode = SPI_MODE_1; + break; + case 2: + spi->mode = SPI_MODE_2; + break; + case 3: + spi->mode = SPI_MODE_3; + break; + } + + bus_io.type = BUS_SPI; + bus_io.read = syna_tcm_spi_read; + bus_io.write = syna_tcm_spi_write; + bus_io.rmi_read = syna_tcm_spi_rmi_read; + bus_io.rmi_write = syna_tcm_spi_rmi_write; + + hw_if.bus_io = &bus_io; + + spi->bits_per_word = 8; + + retval = spi_setup(spi); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to set up SPI protocol driver\n"); + return retval; + } + + syna_tcm_spi_device->dev.parent = &spi->dev; + syna_tcm_spi_device->dev.platform_data = &hw_if; + + retval = platform_device_add(syna_tcm_spi_device); + if (retval < 0) { + LOGE(&spi->dev, + "Failed to add platform device\n"); + return retval; + } + + return 0; +} + +static int syna_tcm_spi_remove(struct spi_device *spi) +{ + syna_tcm_spi_device->dev.platform_data = NULL; + + platform_device_unregister(syna_tcm_spi_device); + + return 0; +} + +static const struct spi_device_id syna_tcm_id_table[] = { + {SPI_MODULE_NAME, 0}, + {}, +}; +MODULE_DEVICE_TABLE(spi, syna_tcm_id_table); + +#ifdef CONFIG_OF +static const struct of_device_id syna_tcm_of_match_table[] = { + { + .compatible = "synaptics,tcm-spi", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, syna_tcm_of_match_table); +#else +#define syna_tcm_of_match_table NULL +#endif + +static struct spi_driver syna_tcm_spi_driver = { + .driver = { + .name = SPI_MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = syna_tcm_of_match_table, + }, + .probe = syna_tcm_spi_probe, + .remove = syna_tcm_spi_remove, + .id_table = syna_tcm_id_table, +}; + +int syna_tcm_bus_init(void) +{ + return spi_register_driver(&syna_tcm_spi_driver); +} +EXPORT_SYMBOL(syna_tcm_bus_init); + +void syna_tcm_bus_exit(void) +{ + kfree(buf); + + kfree(xfer); + + spi_unregister_driver(&syna_tcm_spi_driver); +} +EXPORT_SYMBOL(syna_tcm_bus_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM SPI Bus Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.c new file mode 100644 index 000000000000..b1921f779c72 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.c @@ -0,0 +1,1938 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include "synaptics_tcm_core.h" +#include "synaptics_tcm_testing.h" + +#define SYSFS_DIR_NAME "testing" + +#define REPORT_TIMEOUT_MS 500 + +#define testing_sysfs_show(t_name) \ +static ssize_t testing_sysfs_##t_name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + int retval; \ + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; \ +\ + mutex_lock(&tcm_hcd->extif_mutex); \ +\ + retval = testing_##t_name(); \ + if (retval < 0) { \ + LOGE(tcm_hcd->pdev->dev.parent, \ + "Failed to do "#t_name" test\n"); \ + goto exit; \ + } \ +\ + retval = snprintf(buf, PAGE_SIZE, \ + "%s\n", \ + testing_hcd->result ? "Passed" : "Failed"); \ +\ +exit: \ + mutex_unlock(&tcm_hcd->extif_mutex); \ +\ + return retval; \ +} + +enum test_code { + TEST_TRX_TRX_SHORTS = 0, + TEST_TRX_SENSOR_OPENS = 1, + TEST_TRX_GROUND_SHORTS = 2, + TEST_DYNAMIC_RANGE = 7, + TEST_OPEN_SHORT_DETECTOR = 8, + TEST_NOISE = 10, + TEST_PT11 = 11, + TEST_PT12 = 12, + TEST_PT13 = 13, + TEST_DYNAMIC_RANGE_DOZE = 14, + TEST_NOISE_DOZE = 15, +}; + +struct testing_hcd { + bool result; + unsigned char report_type; + unsigned int report_index; + unsigned int num_of_reports; + struct kobject *sysfs_dir; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_buffer report; + struct syna_tcm_buffer process; + struct syna_tcm_buffer output; + struct syna_tcm_hcd *tcm_hcd; + int (*collect_reports)(enum report_type report_type, + unsigned int num_of_reports); +}; + +DECLARE_COMPLETION(report_complete); + +DECLARE_COMPLETION(testing_remove_complete); + +static struct testing_hcd *testing_hcd; + +static int testing_dynamic_range(void); + +static int testing_dynamic_range_lpwg(void); + +static int testing_dynamic_range_doze(void); + +static int testing_noise(void); + +static int testing_noise_lpwg(void); + +static int testing_noise_doze(void); + +static int testing_open_short_detector(void); + +static int testing_pt11(void); + +static int testing_pt12(void); + +static int testing_pt13(void); + +static int testing_reset_open(void); + +static int testing_lockdown(void); + +static int testing_trx(enum test_code test_code); + +SHOW_PROTOTYPE(testing, dynamic_range); +SHOW_PROTOTYPE(testing, dynamic_range_lpwg); +SHOW_PROTOTYPE(testing, dynamic_range_doze); +SHOW_PROTOTYPE(testing, noise); +SHOW_PROTOTYPE(testing, noise_lpwg); +SHOW_PROTOTYPE(testing, noise_doze); +SHOW_PROTOTYPE(testing, open_short_detector); +SHOW_PROTOTYPE(testing, pt11); +SHOW_PROTOTYPE(testing, pt12); +SHOW_PROTOTYPE(testing, pt13); +SHOW_PROTOTYPE(testing, reset_open); +SHOW_PROTOTYPE(testing, lockdown); +SHOW_PROTOTYPE(testing, trx_trx_shorts); +SHOW_PROTOTYPE(testing, trx_sensor_opens); +SHOW_PROTOTYPE(testing, trx_ground_shorts); +SHOW_PROTOTYPE(testing, size); + +static struct device_attribute *attrs[] = { + ATTRIFY(dynamic_range), + ATTRIFY(dynamic_range_lpwg), + ATTRIFY(dynamic_range_doze), + ATTRIFY(noise), + ATTRIFY(noise_lpwg), + ATTRIFY(noise_doze), + ATTRIFY(open_short_detector), + ATTRIFY(pt11), + ATTRIFY(pt12), + ATTRIFY(pt13), + ATTRIFY(reset_open), + ATTRIFY(lockdown), + ATTRIFY(trx_trx_shorts), + ATTRIFY(trx_sensor_opens), + ATTRIFY(trx_ground_shorts), + ATTRIFY(size), +}; + +static ssize_t testing_sysfs_data_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count); + +static struct bin_attribute bin_attr = { + .attr = { + .name = "data", + .mode = 0444, + }, + .size = 0, + .read = testing_sysfs_data_show, +}; + +testing_sysfs_show(dynamic_range) + +testing_sysfs_show(dynamic_range_lpwg) + +testing_sysfs_show(dynamic_range_doze) + +testing_sysfs_show(noise) + +testing_sysfs_show(noise_lpwg) + +testing_sysfs_show(noise_doze) + +testing_sysfs_show(open_short_detector) + +testing_sysfs_show(pt11) + +testing_sysfs_show(pt12) + +testing_sysfs_show(pt13) + +testing_sysfs_show(reset_open) + +testing_sysfs_show(lockdown) + +static ssize_t testing_sysfs_trx_trx_shorts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = testing_trx(TEST_TRX_TRX_SHORTS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do TRX-TRX shorts test\n"); + goto exit; + } + + retval = snprintf(buf, PAGE_SIZE, + "%s\n", + testing_hcd->result ? "Passed" : "Failed"); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t testing_sysfs_trx_sensor_opens_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = testing_trx(TEST_TRX_SENSOR_OPENS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do TRX-sensor opens test\n"); + goto exit; + } + + retval = snprintf(buf, PAGE_SIZE, + "%s\n", + testing_hcd->result ? "Passed" : "Failed"); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t testing_sysfs_trx_ground_shorts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + retval = testing_trx(TEST_TRX_GROUND_SHORTS); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do TRX-ground shorts test\n"); + goto exit; + } + + retval = snprintf(buf, PAGE_SIZE, + "%s\n", + testing_hcd->result ? "Passed" : "Failed"); + +exit: + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t testing_sysfs_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + LOCK_BUFFER(testing_hcd->output); + + retval = snprintf(buf, PAGE_SIZE, + "%u\n", + testing_hcd->output.data_length); + + UNLOCK_BUFFER(testing_hcd->output); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static ssize_t testing_sysfs_data_show(struct file *data_file, + struct kobject *kobj, struct bin_attribute *attributes, + char *buf, loff_t pos, size_t count) +{ + int retval; + unsigned int readlen; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + mutex_lock(&tcm_hcd->extif_mutex); + + LOCK_BUFFER(testing_hcd->output); + + readlen = MIN(count, testing_hcd->output.data_length - pos); + + retval = secure_memcpy(buf, + count, + &testing_hcd->output.buf[pos], + testing_hcd->output.buf_size - pos, + readlen); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy report data\n"); + } else { + retval = readlen; + } + + UNLOCK_BUFFER(testing_hcd->output); + + mutex_unlock(&tcm_hcd->extif_mutex); + + return retval; +} + +static int testing_run_prod_test_item(enum test_code test_code) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + if (tcm_hcd->features.dual_firmware && + tcm_hcd->id_info.mode != MODE_PRODUCTION_TEST) { + retval = tcm_hcd->switch_mode(tcm_hcd, FW_MODE_PRODUCTION_TEST); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run production test firmware\n"); + return retval; + } + } else if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGE(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + return -ENODEV; + } + + LOCK_BUFFER(testing_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->out, + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for testing_hcd->out.buf\n"); + UNLOCK_BUFFER(testing_hcd->out); + return retval; + } + + testing_hcd->out.buf[0] = test_code; + + LOCK_BUFFER(testing_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_PRODUCTION_TEST, + testing_hcd->out.buf, + 1, + &testing_hcd->resp.buf, + &testing_hcd->resp.buf_size, + &testing_hcd->resp.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_PRODUCTION_TEST)); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + return retval; + } + + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + + return 0; +} + +static int testing_collect_reports(enum report_type report_type, + unsigned int num_of_reports) +{ + int retval; + bool completed; + unsigned int timeout; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + testing_hcd->report_index = 0; + testing_hcd->report_type = report_type; + testing_hcd->num_of_reports = num_of_reports; + + reinit_completion(&report_complete); + + LOCK_BUFFER(testing_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->out, + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for testing_hcd->out.buf\n"); + UNLOCK_BUFFER(testing_hcd->out); + goto exit; + } + + testing_hcd->out.buf[0] = testing_hcd->report_type; + + LOCK_BUFFER(testing_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_ENABLE_REPORT, + testing_hcd->out.buf, + 1, + &testing_hcd->resp.buf, + &testing_hcd->resp.buf_size, + &testing_hcd->resp.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_ENABLE_REPORT)); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + goto exit; + } + + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + + completed = false; + timeout = REPORT_TIMEOUT_MS * num_of_reports; + + retval = wait_for_completion_timeout(&report_complete, + msecs_to_jiffies(timeout)); + if (retval == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Timed out waiting for report collection\n"); + } else { + completed = true; + } + + LOCK_BUFFER(testing_hcd->out); + + testing_hcd->out.buf[0] = testing_hcd->report_type; + + LOCK_BUFFER(testing_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_DISABLE_REPORT, + testing_hcd->out.buf, + 1, + &testing_hcd->resp.buf, + &testing_hcd->resp.buf_size, + &testing_hcd->resp.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_DISABLE_REPORT)); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + goto exit; + } + + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->out); + + if (completed) + retval = 0; + else + retval = -EIO; + +exit: + testing_hcd->report_type = 0; + + return retval; +} + +static void testing_get_frame_size_words(unsigned int *size, bool image_only) +{ + unsigned int rows; + unsigned int cols; + unsigned int hybrid; + unsigned int buttons; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + hybrid = le2_to_uint(app_info->has_hybrid_data); + buttons = le2_to_uint(app_info->num_of_buttons); + + *size = rows * cols; + + if (!image_only) { + if (hybrid) + *size += rows + cols; + *size += buttons; + } +} + +static void testing_doze_frame_output(unsigned int rows, unsigned int cols) +{ + int retval; + unsigned int data_size; + unsigned int header_size; + unsigned int output_size; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + header_size = 2; + + data_size = rows * cols; + + if (le2_to_uint(app_info->num_of_buttons)) + data_size++; + + output_size = header_size + data_size * 2; + + LOCK_BUFFER(testing_hcd->output); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->output, + output_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for testing_hcd->output.buf\n"); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + testing_hcd->output.buf[0] = rows; + testing_hcd->output.buf[1] = cols; + + output_size = header_size; + + LOCK_BUFFER(testing_hcd->resp); + + retval = secure_memcpy(testing_hcd->output.buf + header_size, + testing_hcd->output.buf_size - header_size, + testing_hcd->resp.buf, + testing_hcd->resp.buf_size, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy test data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + output_size += testing_hcd->resp.data_length; + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_hcd->output.data_length = output_size; + + UNLOCK_BUFFER(testing_hcd->output); +} + +static void testing_standard_frame_output(bool image_only) +{ + int retval; + unsigned int data_size; + unsigned int header_size; + unsigned int output_size; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + testing_get_frame_size_words(&data_size, image_only); + + header_size = sizeof(app_info->num_of_buttons) + + sizeof(app_info->num_of_image_rows) + + sizeof(app_info->num_of_image_cols) + + sizeof(app_info->has_hybrid_data); + + output_size = header_size + data_size * 2; + + LOCK_BUFFER(testing_hcd->output); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->output, + output_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for testing_hcd->output.buf\n"); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + retval = secure_memcpy(testing_hcd->output.buf, + testing_hcd->output.buf_size, + &app_info->num_of_buttons[0], + header_size, + header_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy header data\n"); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + output_size = header_size; + + LOCK_BUFFER(testing_hcd->resp); + + retval = secure_memcpy(testing_hcd->output.buf + header_size, + testing_hcd->output.buf_size - header_size, + testing_hcd->resp.buf, + testing_hcd->resp.buf_size, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy test data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + output_size += testing_hcd->resp.data_length; + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_hcd->output.data_length = output_size; + + UNLOCK_BUFFER(testing_hcd->output); +} + +static int testing_dynamic_range_doze(void) +{ + int retval; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int data; + unsigned int rows; + unsigned int cols; + unsigned int data_size; + unsigned int limits_rows; + unsigned int limits_cols; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + cols = le2_to_uint(app_info->num_of_image_cols); + + retval = testing_run_prod_test_item(TEST_DYNAMIC_RANGE_DOZE); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + data_size = testing_hcd->resp.data_length / 2; + + if (le2_to_uint(app_info->num_of_buttons)) + data_size--; + + if (data_size % cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid max number of rows per burst\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + rows = data_size / cols; + + limits_rows = ARRAY_SIZE(drt_hi_limits); + limits_cols = ARRAY_SIZE(drt_hi_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(drt_lo_limits); + limits_cols = ARRAY_SIZE(drt_lo_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = le2_to_uint(&buf[idx * 2]); + if (data > drt_hi_limits[row][col] || + data < drt_lo_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_doze_frame_output(rows, cols); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_dynamic_range_lpwg(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable wakeup gesture mode\n"); + return retval; + } + + retval = testing_dynamic_range(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do dynamic range test\n"); + return retval; + } + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable wakeup gesture mode\n"); + return retval; + } + + return 0; +} + +static int testing_dynamic_range(void) +{ + int retval; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int data; + unsigned int rows; + unsigned int cols; + unsigned int limits_rows; + unsigned int limits_cols; + unsigned int frame_size_words; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + + testing_get_frame_size_words(&frame_size_words, false); + + retval = testing_run_prod_test_item(TEST_DYNAMIC_RANGE); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (frame_size_words != testing_hcd->resp.data_length / 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Frame size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(drt_hi_limits); + limits_cols = ARRAY_SIZE(drt_hi_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(drt_lo_limits); + limits_cols = ARRAY_SIZE(drt_lo_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = le2_to_uint(&buf[idx * 2]); + if (data > drt_hi_limits[row][col] || + data < drt_lo_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_standard_frame_output(false); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_noise_doze(void) +{ + int retval; + short data; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int data_size; + unsigned int limits_rows; + unsigned int limits_cols; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + cols = le2_to_uint(app_info->num_of_image_cols); + + retval = testing_run_prod_test_item(TEST_NOISE_DOZE); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + data_size = testing_hcd->resp.data_length / 2; + + if (le2_to_uint(app_info->num_of_buttons)) + data_size--; + + if (data_size % cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid max number of rows per burst\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + rows = data_size / cols; + + limits_rows = ARRAY_SIZE(noise_limits); + limits_cols = ARRAY_SIZE(noise_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = (short)le2_to_uint(&buf[idx * 2]); + if (data > noise_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_doze_frame_output(rows, cols); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_noise_lpwg(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable wakeup gesture mode\n"); + return retval; + } + + retval = testing_noise(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do noise test\n"); + return retval; + } + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable wakeup gesture mode\n"); + return retval; + } + + return 0; +} + +static int testing_noise(void) +{ + int retval; + short data; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int limits_rows; + unsigned int limits_cols; + unsigned int frame_size_words; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + + testing_get_frame_size_words(&frame_size_words, false); + + retval = testing_run_prod_test_item(TEST_NOISE); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (frame_size_words != testing_hcd->resp.data_length / 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Frame size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(noise_limits); + limits_cols = ARRAY_SIZE(noise_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = (short)le2_to_uint(&buf[idx * 2]); + if (data > noise_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_standard_frame_output(false); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static void testing_open_short_detector_output(void) +{ + int retval; + unsigned int rows; + unsigned int cols; + unsigned int data_size; + unsigned int header_size; + unsigned int output_size; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + data_size = (rows * cols + 7) / 8; + + header_size = sizeof(app_info->num_of_buttons) + + sizeof(app_info->num_of_image_rows) + + sizeof(app_info->num_of_image_cols) + + sizeof(app_info->has_hybrid_data); + + output_size = header_size + data_size * 2; + + LOCK_BUFFER(testing_hcd->output); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->output, + output_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for output.buf\n"); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + retval = secure_memcpy(testing_hcd->output.buf, + testing_hcd->output.buf_size, + &app_info->num_of_buttons[0], + header_size, + header_size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy header data\n"); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + output_size = header_size; + + LOCK_BUFFER(testing_hcd->resp); + + retval = secure_memcpy(testing_hcd->output.buf + header_size, + testing_hcd->output.buf_size - header_size, + testing_hcd->resp.buf, + testing_hcd->resp.buf_size, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy test data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + output_size += testing_hcd->resp.data_length; + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_hcd->output.data_length = output_size; + + UNLOCK_BUFFER(testing_hcd->output); +} + +static int testing_open_short_detector(void) +{ + int retval; + unsigned int bit; + unsigned int byte; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int data_size; + unsigned char *data; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + data_size = (rows * cols + 7) / 8; + + retval = testing_run_prod_test_item(TEST_OPEN_SHORT_DETECTOR); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (data_size * 2 != testing_hcd->resp.data_length) { + LOGE(tcm_hcd->pdev->dev.parent, + "Data size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + testing_hcd->result = true; + + bit = 0; + byte = 0; + data = &testing_hcd->resp.buf[0]; + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + if (data[byte] & (1 << bit)) { + testing_hcd->result = false; + break; + } + if (bit++ > 7) { + bit = 0; + byte++; + } + } + } + + if (testing_hcd->result == true) { + bit = 0; + byte = 0; + data = &testing_hcd->resp.buf[data_size]; + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + if (data[byte] & (1 << bit)) { + testing_hcd->result = false; + break; + } + if (bit++ > 7) { + bit = 0; + byte++; + } + } + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_open_short_detector_output(); + + retval = 0; + +exit: + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + + return retval; +} + +static int testing_pt11(void) +{ + int retval; + short data; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int limits_rows; + unsigned int limits_cols; + unsigned int image_size_words; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + + testing_get_frame_size_words(&image_size_words, true); + + retval = testing_run_prod_test_item(TEST_PT11); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (image_size_words != testing_hcd->resp.data_length / 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Image size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(pt11_hi_limits); + limits_cols = ARRAY_SIZE(pt11_hi_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(pt11_lo_limits); + limits_cols = ARRAY_SIZE(pt11_lo_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = (short)le2_to_uint(&buf[idx * 2]); + if (data > pt11_hi_limits[row][col] || + data < pt11_lo_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_standard_frame_output(true); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_pt12(void) +{ + int retval; + short data; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int limits_rows; + unsigned int limits_cols; + unsigned int image_size_words; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + + testing_get_frame_size_words(&image_size_words, true); + + retval = testing_run_prod_test_item(TEST_PT12); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (image_size_words != testing_hcd->resp.data_length / 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Image size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(pt12_limits); + limits_cols = ARRAY_SIZE(pt12_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = (short)le2_to_uint(&buf[idx * 2]); + if (data < pt12_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_standard_frame_output(true); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_pt13(void) +{ + int retval; + short data; + unsigned char *buf; + unsigned int idx; + unsigned int row; + unsigned int col; + unsigned int rows; + unsigned int cols; + unsigned int limits_rows; + unsigned int limits_cols; + unsigned int image_size_words; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + app_info = &tcm_hcd->app_info; + + rows = le2_to_uint(app_info->num_of_image_rows); + cols = le2_to_uint(app_info->num_of_image_cols); + + testing_get_frame_size_words(&image_size_words, true); + + retval = testing_run_prod_test_item(TEST_PT13); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + if (image_size_words != testing_hcd->resp.data_length / 2) { + LOGE(tcm_hcd->pdev->dev.parent, + "Image size mismatch\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + limits_rows = ARRAY_SIZE(pt13_limits); + limits_cols = ARRAY_SIZE(pt13_limits[0]); + + if (rows > limits_rows || cols > limits_cols) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + retval = -EINVAL; + goto exit; + } + + idx = 0; + buf = testing_hcd->resp.buf; + testing_hcd->result = true; + + for (row = 0; row < rows; row++) { + for (col = 0; col < cols; col++) { + data = (short)le2_to_uint(&buf[idx * 2]); + if (data < pt13_limits[row][col]) { + testing_hcd->result = false; + break; + } + idx++; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_standard_frame_output(true); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static int testing_reset_open(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (bdata->reset_gpio < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Hardware reset unavailable\n"); + return -EINVAL; + } + + mutex_lock(&tcm_hcd->reset_mutex); + + tcm_hcd->update_watchdog(tcm_hcd, false); + + gpio_set_value(bdata->reset_gpio, bdata->reset_on_state); + msleep(bdata->reset_active_ms); + gpio_set_value(bdata->reset_gpio, !bdata->reset_on_state); + msleep(bdata->reset_delay_ms); + + tcm_hcd->update_watchdog(tcm_hcd, true); + + mutex_unlock(&tcm_hcd->reset_mutex); + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) { + retval = tcm_hcd->switch_mode(tcm_hcd, FW_MODE_BOOTLOADER); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enter bootloader mode\n"); + return retval; + } + } else { + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + goto run_app_firmware; + } + } + + if (tcm_hcd->boot_info.last_reset_reason == reset_open_limit) + testing_hcd->result = true; + else + testing_hcd->result = false; + + retval = 0; + +run_app_firmware: + if (tcm_hcd->switch_mode(tcm_hcd, FW_MODE_APPLICATION) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run application firmware\n"); + } + + return retval; +} + +static void testing_lockdown_output(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + LOCK_BUFFER(testing_hcd->output); + LOCK_BUFFER(testing_hcd->resp); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->output, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for output.buf\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + retval = secure_memcpy(testing_hcd->output.buf, + testing_hcd->output.buf_size, + testing_hcd->resp.buf, + testing_hcd->resp.buf_size, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy test data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + testing_hcd->output.data_length = testing_hcd->resp.data_length; + + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); +} + +static int testing_lockdown(void) +{ + int retval; + unsigned int idx; + unsigned int lockdown_size; + unsigned int limits_size; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + if (tcm_hcd->read_flash_data == NULL) { + LOGE(tcm_hcd->pdev->dev.parent, + "Unable to read from flash\n"); + return -EINVAL; + } + + LOCK_BUFFER(testing_hcd->resp); + + retval = tcm_hcd->read_flash_data(CUSTOM_OTP, true, &testing_hcd->resp); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read lockdown data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + return retval; + } + + lockdown_size = testing_hcd->resp.data_length; + + limits_size = sizeof(lockdown_limits) / sizeof(*lockdown_limits); + + if (lockdown_size != limits_size) { + LOGE(tcm_hcd->pdev->dev.parent, + "Mismatching limits data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + return -EINVAL; + } + + testing_hcd->result = true; + + for (idx = 0; idx < lockdown_size; idx++) { + if (testing_hcd->resp.buf[idx] != lockdown_limits[idx]) { + testing_hcd->result = false; + break; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_lockdown_output(); + + return 0; +} + +static void testing_trx_output(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + LOCK_BUFFER(testing_hcd->output); + LOCK_BUFFER(testing_hcd->resp); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->output, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for output.buf\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + retval = secure_memcpy(testing_hcd->output.buf, + testing_hcd->output.buf_size, + testing_hcd->resp.buf, + testing_hcd->resp.buf_size, + testing_hcd->resp.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy test data\n"); + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); + return; + } + + testing_hcd->output.data_length = testing_hcd->resp.data_length; + + UNLOCK_BUFFER(testing_hcd->resp); + UNLOCK_BUFFER(testing_hcd->output); +} + +static int testing_trx(enum test_code test_code) +{ + int retval; + unsigned char pass_vector; + unsigned int idx; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + switch (test_code) { + case TEST_TRX_TRX_SHORTS: + case TEST_TRX_GROUND_SHORTS: + pass_vector = 0xff; + break; + case TEST_TRX_SENSOR_OPENS: + pass_vector = 0x00; + break; + default: + return -EINVAL; + } + + retval = testing_run_prod_test_item(test_code); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to run test\n"); + goto exit; + } + + LOCK_BUFFER(testing_hcd->resp); + + testing_hcd->result = true; + + for (idx = 0; idx < testing_hcd->resp.data_length; idx++) { + if (testing_hcd->resp.buf[idx] != pass_vector) { + testing_hcd->result = false; + break; + } + } + + UNLOCK_BUFFER(testing_hcd->resp); + + testing_trx_output(); + + retval = 0; + +exit: + if (tcm_hcd->features.dual_firmware) { + if (tcm_hcd->reset(tcm_hcd, false, true) < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do reset\n"); + } + } + + return retval; +} + +static void testing_report(void) +{ + int retval; + unsigned int offset; + unsigned int report_size; + struct syna_tcm_hcd *tcm_hcd = testing_hcd->tcm_hcd; + + report_size = tcm_hcd->report.buffer.data_length; + + LOCK_BUFFER(testing_hcd->report); + + if (testing_hcd->report_index == 0) { + retval = syna_tcm_alloc_mem(tcm_hcd, + &testing_hcd->report, + report_size * testing_hcd->num_of_reports); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for report.buf\n"); + UNLOCK_BUFFER(testing_hcd->report); + return; + } + } + + if (testing_hcd->report_index < testing_hcd->num_of_reports) { + offset = report_size * testing_hcd->report_index; + + retval = secure_memcpy(testing_hcd->report.buf + offset, + testing_hcd->report.buf_size - offset, + tcm_hcd->report.buffer.buf, + tcm_hcd->report.buffer.buf_size, + tcm_hcd->report.buffer.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy report data\n"); + UNLOCK_BUFFER(testing_hcd->report); + return; + } + + testing_hcd->report_index++; + testing_hcd->report.data_length += report_size; + } + + UNLOCK_BUFFER(testing_hcd->report); + + if (testing_hcd->report_index == testing_hcd->num_of_reports) + complete(&report_complete); +} + +static int testing_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + int idx; + + testing_hcd = kzalloc(sizeof(*testing_hcd), GFP_KERNEL); + if (!testing_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for testing_hcd\n"); + return -ENOMEM; + } + + testing_hcd->tcm_hcd = tcm_hcd; + + testing_hcd->collect_reports = testing_collect_reports; + + INIT_BUFFER(testing_hcd->out, false); + INIT_BUFFER(testing_hcd->resp, false); + INIT_BUFFER(testing_hcd->report, false); + INIT_BUFFER(testing_hcd->process, false); + INIT_BUFFER(testing_hcd->output, false); + + testing_hcd->sysfs_dir = kobject_create_and_add(SYSFS_DIR_NAME, + tcm_hcd->sysfs_dir); + if (!testing_hcd->sysfs_dir) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs directory\n"); + retval = -EINVAL; + goto err_sysfs_create_dir; + } + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) { + retval = sysfs_create_file(testing_hcd->sysfs_dir, + &(*attrs[idx]).attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs file\n"); + goto err_sysfs_create_file; + } + } + + retval = sysfs_create_bin_file(testing_hcd->sysfs_dir, &bin_attr); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to create sysfs bin file\n"); + goto err_sysfs_create_bin_file; + } + + return 0; + +err_sysfs_create_bin_file: +err_sysfs_create_file: + for (idx--; idx >= 0; idx--) + sysfs_remove_file(testing_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(testing_hcd->sysfs_dir); + +err_sysfs_create_dir: + RELEASE_BUFFER(testing_hcd->output); + RELEASE_BUFFER(testing_hcd->process); + RELEASE_BUFFER(testing_hcd->report); + RELEASE_BUFFER(testing_hcd->resp); + RELEASE_BUFFER(testing_hcd->out); + + kfree(testing_hcd); + testing_hcd = NULL; + + return retval; +} + +static int testing_remove(struct syna_tcm_hcd *tcm_hcd) +{ + int idx; + + if (!testing_hcd) + goto exit; + + sysfs_remove_bin_file(testing_hcd->sysfs_dir, &bin_attr); + + for (idx = 0; idx < ARRAY_SIZE(attrs); idx++) + sysfs_remove_file(testing_hcd->sysfs_dir, &(*attrs[idx]).attr); + + kobject_put(testing_hcd->sysfs_dir); + + RELEASE_BUFFER(testing_hcd->output); + RELEASE_BUFFER(testing_hcd->process); + RELEASE_BUFFER(testing_hcd->report); + RELEASE_BUFFER(testing_hcd->resp); + RELEASE_BUFFER(testing_hcd->out); + + kfree(testing_hcd); + testing_hcd = NULL; + +exit: + complete(&testing_remove_complete); + + return 0; +} + +static int testing_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!testing_hcd) { + retval = testing_init(tcm_hcd); + return retval; + } + + return 0; +} + +static int testing_syncbox(struct syna_tcm_hcd *tcm_hcd) +{ + if (!testing_hcd) + return 0; + + if (tcm_hcd->report.id == testing_hcd->report_type) + testing_report(); + + return 0; +} + +static struct syna_tcm_module_cb testing_module = { + .type = TCM_TESTING, + .init = testing_init, + .remove = testing_remove, + .syncbox = testing_syncbox, + .asyncbox = NULL, + .reset = testing_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init testing_module_init(void) +{ + return syna_tcm_add_module(&testing_module, true); +} + +static void __exit testing_module_exit(void) +{ + syna_tcm_add_module(&testing_module, false); + + wait_for_completion(&testing_remove_complete); +} + +module_init(testing_module_init); +module_exit(testing_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Testing Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.h b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.h new file mode 100644 index 000000000000..c5a39a589672 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_testing.h @@ -0,0 +1,85 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#ifndef _SYNAPTICS_TCM_TESTING_H_ +#define _SYNAPTICS_TCM_TESTING_H_ + +static const unsigned short drt_hi_limits[32][32] = { + {0}, +}; + +static const unsigned short drt_lo_limits[32][32] = { + {0,}, +}; + +static const unsigned short noise_limits[32][32] = { + {0,}, +}; + +static const short pt11_hi_limits[32][32] = { + {0,}, +}; + +static const short pt11_lo_limits[32][32] = { + {0,}, +}; + +static const short pt12_limits[32][32] = { + {0,}, +}; + +static const short pt13_limits[32][32] = { + {0,}, +}; + +static const unsigned char lockdown_limits[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +static const unsigned char reset_open_limit = 0x13; + +#endif diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_touch.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_touch.c new file mode 100644 index 000000000000..c354ecdb8c92 --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_touch.c @@ -0,0 +1,1265 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include "synaptics_tcm_core.h" + +#define TYPE_B_PROTOCOL + +#define USE_DEFAULT_TOUCH_REPORT_CONFIG + +#define TOUCH_REPORT_CONFIG_SIZE 128 + +enum touch_status { + LIFT = 0, + FINGER = 1, + GLOVED_FINGER = 2, + NOP = -1, +}; + +enum touch_report_code { + TOUCH_END = 0, + TOUCH_FOREACH_ACTIVE_OBJECT, + TOUCH_FOREACH_OBJECT, + TOUCH_FOREACH_END, + TOUCH_PAD_TO_NEXT_BYTE, + TOUCH_TIMESTAMP, + TOUCH_OBJECT_N_INDEX, + TOUCH_OBJECT_N_CLASSIFICATION, + TOUCH_OBJECT_N_X_POSITION, + TOUCH_OBJECT_N_Y_POSITION, + TOUCH_OBJECT_N_Z, + TOUCH_OBJECT_N_X_WIDTH, + TOUCH_OBJECT_N_Y_WIDTH, + TOUCH_OBJECT_N_TX_POSITION_TIXELS, + TOUCH_OBJECT_N_RX_POSITION_TIXELS, + TOUCH_0D_BUTTONS_STATE, + TOUCH_GESTURE_DOUBLE_TAP, + TOUCH_FRAME_RATE, + TOUCH_POWER_IM, + TOUCH_CID_IM, + TOUCH_RAIL_IM, + TOUCH_CID_VARIANCE_IM, + TOUCH_NSM_FREQUENCY, + TOUCH_NSM_STATE, + TOUCH_NUM_OF_ACTIVE_OBJECTS, + TOUCH_NUM_OF_CPU_CYCLES_USED_SINCE_LAST_FRAME, + TOUCH_TUNING_GAUSSIAN_WIDTHS = 0x80, + TOUCH_TUNING_SMALL_OBJECT_PARAMS, + TOUCH_TUNING_0D_BUTTONS_VARIANCE, +}; + +struct object_data { + unsigned char status; + unsigned int x_pos; + unsigned int y_pos; + unsigned int x_width; + unsigned int y_width; + unsigned int z; + unsigned int tx_pos; + unsigned int rx_pos; +}; + +struct input_params { + unsigned int max_x; + unsigned int max_y; + unsigned int max_objects; +}; + +struct touch_data { + struct object_data *object_data; + unsigned int timestamp; + unsigned int buttons_state; + unsigned int gesture_double_tap; + unsigned int frame_rate; + unsigned int power_im; + unsigned int cid_im; + unsigned int rail_im; + unsigned int cid_variance_im; + unsigned int nsm_frequency; + unsigned int nsm_state; + unsigned int num_of_active_objects; + unsigned int num_of_cpu_cycles; +}; + +struct touch_hcd { + bool irq_wake; + bool report_touch; + bool suspend_touch; + unsigned char *prev_status; + unsigned int max_x; + unsigned int max_y; + unsigned int max_objects; + struct mutex report_mutex; + struct input_dev *input_dev; + struct touch_data touch_data; + struct input_params input_params; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(touch_remove_complete); + +static struct touch_hcd *touch_hcd; + +/** + * touch_free_objects() - Free all touch objects + * + * Report finger lift events to the input subsystem for all touch objects. + */ +static void touch_free_objects(void) +{ +#ifdef TYPE_B_PROTOCOL + unsigned int idx; +#endif + + if (touch_hcd->input_dev == NULL) + return; + + mutex_lock(&touch_hcd->report_mutex); + +#ifdef TYPE_B_PROTOCOL + for (idx = 0; idx < touch_hcd->max_objects; idx++) { + input_mt_slot(touch_hcd->input_dev, idx); + input_mt_report_slot_state(touch_hcd->input_dev, + MT_TOOL_FINGER, 0); + } +#endif + input_report_key(touch_hcd->input_dev, + BTN_TOUCH, 0); + input_report_key(touch_hcd->input_dev, + BTN_TOOL_FINGER, 0); +#ifndef TYPE_B_PROTOCOL + input_mt_sync(touch_hcd->input_dev); +#endif + input_sync(touch_hcd->input_dev); + + mutex_unlock(&touch_hcd->report_mutex); +} + +/** + * touch_get_report_data() - Retrieve data from touch report + * + * Retrieve data from the touch report based on the bit offset and bit length + * information from the touch report configuration. + */ +static int touch_get_report_data(unsigned int offset, + unsigned int bits, unsigned int *data) +{ + unsigned char mask; + unsigned char byte_data; + unsigned int output_data; + unsigned int bit_offset; + unsigned int byte_offset; + unsigned int data_bits; + unsigned int available_bits; + unsigned int remaining_bits; + unsigned char *touch_report; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + + if (bits == 0 || bits > 32) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid number of bits\n"); + return -EINVAL; + } + + if (offset + bits > tcm_hcd->report.buffer.data_length * 8) { + *data = 0; + return 0; + } + + touch_report = tcm_hcd->report.buffer.buf; + + output_data = 0; + remaining_bits = bits; + + bit_offset = offset % 8; + byte_offset = offset / 8; + + while (remaining_bits) { + byte_data = touch_report[byte_offset]; + byte_data >>= bit_offset; + + available_bits = 8 - bit_offset; + data_bits = MIN(available_bits, remaining_bits); + mask = 0xff >> (8 - data_bits); + + byte_data &= mask; + + output_data |= byte_data << (bits - remaining_bits); + + bit_offset = 0; + byte_offset += 1; + remaining_bits -= data_bits; + } + + *data = output_data; + + return 0; +} + +/** + * touch_parse_report() - Parse touch report + * + * Traverse through the touch report configuration and parse the touch report + * generated by the device accordingly to retrieve the touch data. + */ +static int touch_parse_report(void) +{ + int retval; + bool active_only; + bool num_of_active_objects; + unsigned char code; + unsigned int size; + unsigned int idx; + unsigned int obj; + unsigned int next; + unsigned int data; + unsigned int bits; + unsigned int offset; + unsigned int objects; + unsigned int active_objects; + unsigned int report_size; + unsigned int config_size; + unsigned char *config_data; + struct touch_data *touch_data; + struct object_data *object_data; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + static unsigned int end_of_foreach; + + touch_data = &touch_hcd->touch_data; + object_data = touch_hcd->touch_data.object_data; + + config_data = tcm_hcd->config.buf; + config_size = tcm_hcd->config.data_length; + + report_size = tcm_hcd->report.buffer.data_length; + + size = sizeof(*object_data) * touch_hcd->max_objects; + memset(touch_hcd->touch_data.object_data, 0x00, size); + + num_of_active_objects = false; + + idx = 0; + offset = 0; + objects = 0; + while (idx < config_size) { + code = config_data[idx++]; + switch (code) { + case TOUCH_END: + goto exit; + case TOUCH_FOREACH_ACTIVE_OBJECT: + obj = 0; + next = idx; + active_only = true; + break; + case TOUCH_FOREACH_OBJECT: + obj = 0; + next = idx; + active_only = false; + break; + case TOUCH_FOREACH_END: + end_of_foreach = idx; + if (active_only) { + if (num_of_active_objects) { + objects++; + if (objects < active_objects) + idx = next; + } else if (offset < report_size * 8) { + idx = next; + } + } else { + obj++; + if (obj < touch_hcd->max_objects) + idx = next; + } + break; + case TOUCH_PAD_TO_NEXT_BYTE: + offset = ceil_div(offset, 8) * 8; + break; + case TOUCH_TIMESTAMP: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get timestamp\n"); + return retval; + } + touch_data->timestamp = data; + offset += bits; + break; + case TOUCH_OBJECT_N_INDEX: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &obj); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object index\n"); + return retval; + } + offset += bits; + break; + case TOUCH_OBJECT_N_CLASSIFICATION: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get classification data\n"); + return retval; + } + object_data[obj].status = data; + offset += bits; + break; + case TOUCH_OBJECT_N_X_POSITION: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object x position\n"); + return retval; + } + object_data[obj].x_pos = data; + offset += bits; + break; + case TOUCH_OBJECT_N_Y_POSITION: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object y position\n"); + return retval; + } + object_data[obj].y_pos = data; + offset += bits; + break; + case TOUCH_OBJECT_N_Z: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object z\n"); + return retval; + } + object_data[obj].z = data; + offset += bits; + break; + case TOUCH_OBJECT_N_X_WIDTH: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object x width\n"); + return retval; + } + object_data[obj].x_width = data; + offset += bits; + break; + case TOUCH_OBJECT_N_Y_WIDTH: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object y width\n"); + return retval; + } + object_data[obj].y_width = data; + offset += bits; + break; + case TOUCH_OBJECT_N_TX_POSITION_TIXELS: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object tx position\n"); + return retval; + } + object_data[obj].tx_pos = data; + offset += bits; + break; + case TOUCH_OBJECT_N_RX_POSITION_TIXELS: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get object rx position\n"); + return retval; + } + object_data[obj].rx_pos = data; + offset += bits; + break; + case TOUCH_0D_BUTTONS_STATE: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get 0D buttons state\n"); + return retval; + } + touch_data->buttons_state = data; + offset += bits; + break; + case TOUCH_GESTURE_DOUBLE_TAP: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get gesture double tap\n"); + return retval; + } + touch_data->gesture_double_tap = data; + offset += bits; + break; + case TOUCH_FRAME_RATE: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get frame rate\n"); + return retval; + } + touch_data->frame_rate = data; + offset += bits; + break; + case TOUCH_POWER_IM: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get power IM\n"); + return retval; + } + touch_data->power_im = data; + offset += bits; + break; + case TOUCH_CID_IM: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get CID IM\n"); + return retval; + } + touch_data->cid_im = data; + offset += bits; + break; + case TOUCH_RAIL_IM: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get rail IM\n"); + return retval; + } + touch_data->rail_im = data; + offset += bits; + break; + case TOUCH_CID_VARIANCE_IM: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get CID variance IM\n"); + return retval; + } + touch_data->cid_variance_im = data; + offset += bits; + break; + case TOUCH_NSM_FREQUENCY: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get NSM frequency\n"); + return retval; + } + touch_data->nsm_frequency = data; + offset += bits; + break; + case TOUCH_NSM_STATE: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get NSM state\n"); + return retval; + } + touch_data->nsm_state = data; + offset += bits; + break; + case TOUCH_NUM_OF_ACTIVE_OBJECTS: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get number of objects\n"); + return retval; + } + active_objects = data; + num_of_active_objects = true; + touch_data->num_of_active_objects = data; + offset += bits; + if (touch_data->num_of_active_objects == 0) + idx = end_of_foreach; + break; + case TOUCH_NUM_OF_CPU_CYCLES_USED_SINCE_LAST_FRAME: + bits = config_data[idx++]; + retval = touch_get_report_data(offset, bits, &data); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get number of CPU cycles\n"); + return retval; + } + touch_data->num_of_cpu_cycles = data; + offset += bits; + break; + case TOUCH_TUNING_GAUSSIAN_WIDTHS: + bits = config_data[idx++]; + offset += bits; + break; + case TOUCH_TUNING_SMALL_OBJECT_PARAMS: + bits = config_data[idx++]; + offset += bits; + break; + case TOUCH_TUNING_0D_BUTTONS_VARIANCE: + bits = config_data[idx++]; + offset += bits; + break; + } + } + +exit: + return 0; +} + +/** + * touch_report() - Report touch events + * + * Retrieve data from the touch report generated by the device and report touch + * events to the input subsystem. + */ +static void touch_report(void) +{ + int retval; + unsigned int idx; + unsigned int x; + unsigned int y; + unsigned int temp; + unsigned int status; + unsigned int touch_count; + struct touch_data *touch_data; + struct object_data *object_data; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + if (!touch_hcd->report_touch) + return; + + if (touch_hcd->input_dev == NULL) + return; + + mutex_lock(&touch_hcd->report_mutex); + + retval = touch_parse_report(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to parse touch report\n"); + goto exit; + } + + touch_data = &touch_hcd->touch_data; + object_data = touch_hcd->touch_data.object_data; + +#ifdef WAKEUP_GESTURE + if (touch_data->gesture_double_tap && tcm_hcd->in_suspend) { + input_report_key(touch_hcd->input_dev, KEY_WAKEUP, 1); + input_sync(touch_hcd->input_dev); + input_report_key(touch_hcd->input_dev, KEY_WAKEUP, 0); + input_sync(touch_hcd->input_dev); + } +#endif + + if (tcm_hcd->in_suspend) + goto exit; + + touch_count = 0; + + for (idx = 0; idx < touch_hcd->max_objects; idx++) { + if (touch_hcd->prev_status[idx] == LIFT && + object_data[idx].status == LIFT) + status = NOP; + else + status = object_data[idx].status; + + switch (status) { + case LIFT: +#ifdef TYPE_B_PROTOCOL + input_mt_slot(touch_hcd->input_dev, idx); + input_mt_report_slot_state(touch_hcd->input_dev, + MT_TOOL_FINGER, 0); +#endif + break; + case FINGER: + case GLOVED_FINGER: + x = object_data[idx].x_pos; + y = object_data[idx].y_pos; + if (bdata->swap_axes) { + temp = x; + x = y; + y = temp; + } + if (bdata->x_flip) + x = touch_hcd->input_params.max_x - x; + if (bdata->y_flip) + y = touch_hcd->input_params.max_y - y; +#ifdef TYPE_B_PROTOCOL + input_mt_slot(touch_hcd->input_dev, idx); + input_mt_report_slot_state(touch_hcd->input_dev, + MT_TOOL_FINGER, 1); +#endif + input_report_key(touch_hcd->input_dev, + BTN_TOUCH, 1); + input_report_key(touch_hcd->input_dev, + BTN_TOOL_FINGER, 1); + input_report_abs(touch_hcd->input_dev, + ABS_MT_POSITION_X, x); + input_report_abs(touch_hcd->input_dev, + ABS_MT_POSITION_Y, y); +#ifndef TYPE_B_PROTOCOL + input_mt_sync(touch_hcd->input_dev); +#endif + LOGD(tcm_hcd->pdev->dev.parent, + "Finger %d: x = %d, y = %d\n", + idx, x, y); + touch_count++; + break; + default: + break; + } + + touch_hcd->prev_status[idx] = object_data[idx].status; + } + + if (touch_count == 0) { + input_report_key(touch_hcd->input_dev, + BTN_TOUCH, 0); + input_report_key(touch_hcd->input_dev, + BTN_TOOL_FINGER, 0); +#ifndef TYPE_B_PROTOCOL + input_mt_sync(touch_hcd->input_dev); +#endif + } + + input_sync(touch_hcd->input_dev); + +exit: + mutex_unlock(&touch_hcd->report_mutex); +} + +/** + * touch_set_input_params() - Set input parameters + * + * Set the input parameters of the input device based on the information + * retrieved from the application information packet. In addition, set up an + * array for tracking the status of touch objects. + */ +static int touch_set_input_params(void) +{ + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + + input_set_abs_params(touch_hcd->input_dev, + ABS_MT_POSITION_X, 0, touch_hcd->max_x, 0, 0); + input_set_abs_params(touch_hcd->input_dev, + ABS_MT_POSITION_Y, 0, touch_hcd->max_y, 0, 0); + + input_mt_init_slots(touch_hcd->input_dev, touch_hcd->max_objects, + INPUT_MT_DIRECT); + + touch_hcd->input_params.max_x = touch_hcd->max_x; + touch_hcd->input_params.max_y = touch_hcd->max_y; + touch_hcd->input_params.max_objects = touch_hcd->max_objects; + + if (touch_hcd->max_objects == 0) + return 0; + + kfree(touch_hcd->prev_status); + touch_hcd->prev_status = kzalloc(touch_hcd->max_objects, GFP_KERNEL); + if (!touch_hcd->prev_status) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for prev_status\n"); + return -ENOMEM; + } + + return 0; +} + +/** + * touch_get_input_params() - Get input parameters + * + * Retrieve the input parameters to register with the input subsystem for + * the input device from the application information packet. In addition, + * the touch report configuration is retrieved and stored. + */ +static int touch_get_input_params(void) +{ + int retval; + unsigned int temp; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; + + app_info = &tcm_hcd->app_info; + touch_hcd->max_x = le2_to_uint(app_info->max_x); + touch_hcd->max_y = le2_to_uint(app_info->max_y); + touch_hcd->max_objects = le2_to_uint(app_info->max_objects); + + if (bdata->swap_axes) { + temp = touch_hcd->max_x; + touch_hcd->max_x = touch_hcd->max_y; + touch_hcd->max_y = temp; + } + + LOCK_BUFFER(tcm_hcd->config); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_GET_TOUCH_REPORT_CONFIG, + NULL, + 0, + &tcm_hcd->config.buf, + &tcm_hcd->config.buf_size, + &tcm_hcd->config.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_GET_TOUCH_REPORT_CONFIG)); + UNLOCK_BUFFER(tcm_hcd->config); + return retval; + } + + UNLOCK_BUFFER(tcm_hcd->config); + + return 0; +} + +/** + * touch_set_input_dev() - Set up input device + * + * Allocate an input device, configure the input device based on the particular + * input events to be reported, and register the input device with the input + * subsystem. + */ +static int touch_set_input_dev(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + + touch_hcd->input_dev = input_allocate_device(); + if (touch_hcd->input_dev == NULL) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate input device\n"); + return -ENODEV; + } + + touch_hcd->input_dev->name = TOUCH_INPUT_NAME; + touch_hcd->input_dev->phys = TOUCH_INPUT_PHYS_PATH; + touch_hcd->input_dev->id.product = SYNAPTICS_TCM_ID_PRODUCT; + touch_hcd->input_dev->id.version = SYNAPTICS_TCM_ID_VERSION; + touch_hcd->input_dev->dev.parent = tcm_hcd->pdev->dev.parent; + input_set_drvdata(touch_hcd->input_dev, tcm_hcd); + + set_bit(EV_SYN, touch_hcd->input_dev->evbit); + set_bit(EV_KEY, touch_hcd->input_dev->evbit); + set_bit(EV_ABS, touch_hcd->input_dev->evbit); + set_bit(BTN_TOUCH, touch_hcd->input_dev->keybit); + set_bit(BTN_TOOL_FINGER, touch_hcd->input_dev->keybit); +#ifdef INPUT_PROP_DIRECT + set_bit(INPUT_PROP_DIRECT, touch_hcd->input_dev->propbit); +#endif + +#ifdef WAKEUP_GESTURE + set_bit(KEY_WAKEUP, touch_hcd->input_dev->keybit); + input_set_capability(touch_hcd->input_dev, EV_KEY, KEY_WAKEUP); +#endif + + retval = touch_set_input_params(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set input parameters\n"); + input_free_device(touch_hcd->input_dev); + touch_hcd->input_dev = NULL; + return retval; + } + + retval = input_register_device(touch_hcd->input_dev); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to register input device\n"); + input_free_device(touch_hcd->input_dev); + touch_hcd->input_dev = NULL; + return retval; + } + + return 0; +} + +/** + * touch_set_report_config() - Set touch report configuration + * + * Send the SET_TOUCH_REPORT_CONFIG command to configure the format and content + * of the touch report. + */ +static int touch_set_report_config(void) +{ + int retval; + unsigned int idx; + unsigned int length; + struct syna_tcm_app_info *app_info; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + +#ifdef USE_DEFAULT_TOUCH_REPORT_CONFIG + return 0; +#endif + + app_info = &tcm_hcd->app_info; + length = le2_to_uint(app_info->max_touch_report_config_size); + + if (length < TOUCH_REPORT_CONFIG_SIZE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid maximum touch report config size\n"); + return -EINVAL; + } + + LOCK_BUFFER(touch_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &touch_hcd->out, + length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for touch_hcd->out.buf\n"); + UNLOCK_BUFFER(touch_hcd->out); + return retval; + } + + idx = 0; +#ifdef WAKEUP_GESTURE + touch_hcd->out.buf[idx++] = TOUCH_GESTURE_DOUBLE_TAP; + touch_hcd->out.buf[idx++] = 8; +#endif + touch_hcd->out.buf[idx++] = TOUCH_FOREACH_ACTIVE_OBJECT; + touch_hcd->out.buf[idx++] = TOUCH_OBJECT_N_INDEX; + touch_hcd->out.buf[idx++] = 4; + touch_hcd->out.buf[idx++] = TOUCH_OBJECT_N_CLASSIFICATION; + touch_hcd->out.buf[idx++] = 4; + touch_hcd->out.buf[idx++] = TOUCH_OBJECT_N_X_POSITION; + touch_hcd->out.buf[idx++] = 12; + touch_hcd->out.buf[idx++] = TOUCH_OBJECT_N_Y_POSITION; + touch_hcd->out.buf[idx++] = 12; + touch_hcd->out.buf[idx++] = TOUCH_FOREACH_END; + touch_hcd->out.buf[idx++] = TOUCH_END; + + LOCK_BUFFER(touch_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_SET_TOUCH_REPORT_CONFIG, + touch_hcd->out.buf, + length, + &touch_hcd->resp.buf, + &touch_hcd->resp.buf_size, + &touch_hcd->resp.data_length, + NULL, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_SET_TOUCH_REPORT_CONFIG)); + UNLOCK_BUFFER(touch_hcd->resp); + UNLOCK_BUFFER(touch_hcd->out); + return retval; + } + + UNLOCK_BUFFER(touch_hcd->resp); + UNLOCK_BUFFER(touch_hcd->out); + + return 0; +} + +/** + * touch_check_input_params() - Check input parameters + * + * Check if any of the input parameters registered with the input subsystem for + * the input device has changed. + */ +static int touch_check_input_params(void) +{ + unsigned int size; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + + if (touch_hcd->max_x == 0 && touch_hcd->max_y == 0) + return 0; + + if (touch_hcd->input_params.max_objects != touch_hcd->max_objects) { + kfree(touch_hcd->touch_data.object_data); + size = sizeof(*touch_hcd->touch_data.object_data); + size *= touch_hcd->max_objects; + touch_hcd->touch_data.object_data = kzalloc(size, GFP_KERNEL); + if (!touch_hcd->touch_data.object_data) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for object_data\n"); + return -ENOMEM; + } + return 1; + } + + if (touch_hcd->input_params.max_x != touch_hcd->max_x) + return 1; + + if (touch_hcd->input_params.max_y != touch_hcd->max_y) + return 1; + + return 0; +} + +/** + * touch_set_input_reporting() - Configure touch report and set up new input + * device if necessary + * + * After a device reset event, configure the touch report and set up a new input + * device if any of the input parameters has changed after the device reset. + */ +static int touch_set_input_reporting(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = touch_hcd->tcm_hcd; + + if (tcm_hcd->id_info.mode != MODE_APPLICATION || + tcm_hcd->app_status != APP_STATUS_OK) { + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware not running\n"); + return 0; + } + + touch_hcd->report_touch = false; + + touch_free_objects(); + + mutex_lock(&touch_hcd->report_mutex); + + retval = touch_set_report_config(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set report config\n"); + goto exit; + } + + retval = touch_get_input_params(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get input parameters\n"); + goto exit; + } + + retval = touch_check_input_params(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to check input parameters\n"); + goto exit; + } else if (retval == 0) { + LOGN(tcm_hcd->pdev->dev.parent, + "Input parameters unchanged\n"); + goto exit; + } + + if (touch_hcd->input_dev != NULL) { + input_unregister_device(touch_hcd->input_dev); + touch_hcd->input_dev = NULL; + } + + retval = touch_set_input_dev(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up input device\n"); + goto exit; + } + +exit: + mutex_unlock(&touch_hcd->report_mutex); + + touch_hcd->report_touch = retval < 0 ? false : true; + + return retval; +} + +static int touch_init(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + touch_hcd = kzalloc(sizeof(*touch_hcd), GFP_KERNEL); + if (!touch_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for touch_hcd\n"); + return -ENOMEM; + } + + touch_hcd->tcm_hcd = tcm_hcd; + + mutex_init(&touch_hcd->report_mutex); + + INIT_BUFFER(touch_hcd->out, false); + INIT_BUFFER(touch_hcd->resp, false); + + retval = touch_set_input_reporting(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up input reporting\n"); + goto err_set_input_reporting; + } + + tcm_hcd->report_touch = touch_report; + + return 0; + +err_set_input_reporting: + kfree(touch_hcd->touch_data.object_data); + kfree(touch_hcd->prev_status); + + RELEASE_BUFFER(touch_hcd->resp); + RELEASE_BUFFER(touch_hcd->out); + + kfree(touch_hcd); + touch_hcd = NULL; + + return retval; +} + +static int touch_remove(struct syna_tcm_hcd *tcm_hcd) +{ + if (!touch_hcd) + goto exit; + + tcm_hcd->report_touch = NULL; + + input_unregister_device(touch_hcd->input_dev); + + kfree(touch_hcd->touch_data.object_data); + kfree(touch_hcd->prev_status); + + RELEASE_BUFFER(touch_hcd->resp); + RELEASE_BUFFER(touch_hcd->out); + + kfree(touch_hcd); + touch_hcd = NULL; + +exit: + complete(&touch_remove_complete); + + return 0; +} + +static int touch_syncbox(struct syna_tcm_hcd *tcm_hcd) +{ + if (!touch_hcd) + return 0; + + switch (tcm_hcd->report.id) { + case REPORT_IDENTIFY: + touch_free_objects(); + break; + case REPORT_TOUCH: + if (!touch_hcd->suspend_touch) + touch_report(); + break; + default: + break; + } + + return 0; +} + +static int touch_asyncbox(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!touch_hcd) + return 0; + + switch (tcm_hcd->async_report_id) { + case REPORT_IDENTIFY: + if (tcm_hcd->id_info.mode != MODE_APPLICATION) + break; + retval = tcm_hcd->identify(tcm_hcd, false); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to do identification\n"); + return retval; + } + retval = touch_set_input_reporting(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up input reporting\n"); + return retval; + } + break; + default: + break; + } + + return 0; +} + +static int touch_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!touch_hcd) { + retval = touch_init(tcm_hcd); + return retval; + } + + if (tcm_hcd->id_info.mode == MODE_APPLICATION) { + retval = touch_set_input_reporting(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to set up input reporting\n"); + return retval; + } + } + + return 0; +} + +static int touch_early_suspend(struct syna_tcm_hcd *tcm_hcd) +{ + if (!touch_hcd) + return 0; + + touch_hcd->suspend_touch = true; + + touch_free_objects(); + + return 0; +} + +static int touch_suspend(struct syna_tcm_hcd *tcm_hcd) +{ +#ifdef WAKEUP_GESTURE + int retval; +#endif + + if (!touch_hcd) + return 0; + + touch_hcd->suspend_touch = true; + + touch_free_objects(); + +#ifdef WAKEUP_GESTURE + if (!touch_hcd->irq_wake) { + enable_irq_wake(tcm_hcd->irq); + touch_hcd->irq_wake = true; + } + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 1); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable wakeup gesture mode\n"); + return retval; + } +#endif + + return 0; +} + +static int touch_resume(struct syna_tcm_hcd *tcm_hcd) +{ +#ifdef WAKEUP_GESTURE + int retval; +#endif + + if (!touch_hcd) + return 0; + + touch_hcd->suspend_touch = false; + +#ifdef WAKEUP_GESTURE + if (touch_hcd->irq_wake) { + disable_irq_wake(tcm_hcd->irq); + touch_hcd->irq_wake = false; + } + + retval = tcm_hcd->set_dynamic_config(tcm_hcd, + DC_IN_WAKEUP_GESTURE_MODE, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable wakeup gesture mode\n"); + return retval; + } +#endif + + return 0; +} + +static struct syna_tcm_module_cb touch_module = { + .type = TCM_TOUCH, + .init = touch_init, + .remove = touch_remove, + .syncbox = touch_syncbox, + .asyncbox = touch_asyncbox, + .reset = touch_reset, + .suspend = touch_suspend, + .resume = touch_resume, + .early_suspend = touch_early_suspend, +}; + +static int __init touch_module_init(void) +{ + return syna_tcm_add_module(&touch_module, true); +} + +static void __exit touch_module_exit(void) +{ + syna_tcm_add_module(&touch_module, false); + + wait_for_completion(&touch_remove_complete); +} + +module_init(touch_module_init); +module_exit(touch_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Touch Module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_zeroflash.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_zeroflash.c new file mode 100644 index 000000000000..5e8295477cdb --- /dev/null +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_zeroflash.c @@ -0,0 +1,1012 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#include +#include +#include +#include "synaptics_tcm_core.h" + +#define FW_IMAGE_NAME "synaptics/hdl_firmware.img" + +#define BOOT_CONFIG_ID "BOOT_CONFIG" + +#define F35_APP_CODE_ID "F35_APP_CODE" + +#define APP_CONFIG_ID "APP_CONFIG" + +#define DISP_CONFIG_ID "DISPLAY" + +#define IMAGE_FILE_MAGIC_VALUE 0x4818472b + +#define FLASH_AREA_MAGIC_VALUE 0x7c05e516 + +#define PDT_START_ADDR 0x00e9 + +#define PDT_END_ADDR 0x00ee + +#define UBL_FN_NUMBER 0x35 + +#define F35_CTRL3_OFFSET 18 + +#define F35_CTRL7_OFFSET 22 + +#define F35_WRITE_FW_TO_PMEM_COMMAND 4 + +#define RESET_TO_HDL_DELAY_MS 12 + +#define DOWNLOAD_RETRY_COUNT 10 + +enum f35_error_code { + SUCCESS = 0, + UNKNOWN_FLASH_PRESENT, + MAGIC_NUMBER_NOT_PRESENT, + INVALID_BLOCK_NUMBER, + BLOCK_NOT_ERASED, + NO_FLASH_PRESENT, + CHECKSUM_FAILURE, + WRITE_FAILURE, + INVALID_COMMAND, + IN_DEBUG_MODE, + INVALID_HEADER, + REQUESTING_FIRMWARE, + INVALID_CONFIGURATION, + DISABLE_BLOCK_PROTECT_FAILURE, +}; + +enum config_download { + HDL_INVALID = 0, + HDL_TOUCH_CONFIG, + HDL_DISPLAY_CONFIG, + HDL_DISPLAY_CONFIG_TO_RAM, +}; + +struct area_descriptor { + unsigned char magic_value[4]; + unsigned char id_string[16]; + unsigned char flags[4]; + unsigned char flash_addr_words[4]; + unsigned char length[4]; + unsigned char checksum[4]; +}; + +struct block_data { + const unsigned char *data; + unsigned int size; + unsigned int flash_addr; +}; + +struct image_info { + unsigned int packrat_number; + struct block_data boot_config; + struct block_data app_firmware; + struct block_data app_config; + struct block_data disp_config; +}; + +struct image_header { + unsigned char magic_value[4]; + unsigned char num_of_areas[4]; +}; + +struct rmi_f35_query { + unsigned char version:4; + unsigned char has_debug_mode:1; + unsigned char has_data5:1; + unsigned char has_query1:1; + unsigned char has_query2:1; + unsigned char chunk_size; + unsigned char has_ctrl7:1; + unsigned char has_host_download:1; + unsigned char has_spi_master:1; + unsigned char advanced_recovery_mode:1; + unsigned char reserved:4; +} __packed; + +struct rmi_f35_data { + unsigned char error_code:5; + unsigned char recovery_mode_forced:1; + unsigned char nvm_programmed:1; + unsigned char in_recovery:1; +} __packed; + +struct rmi_pdt_entry { + unsigned char query_base_addr; + unsigned char command_base_addr; + unsigned char control_base_addr; + unsigned char data_base_addr; + unsigned char intr_src_count:3; + unsigned char reserved_1:2; + unsigned char fn_version:2; + unsigned char reserved_2:1; + unsigned char fn_number; +} __packed; + +struct rmi_addr { + unsigned short query_base; + unsigned short command_base; + unsigned short control_base; + unsigned short data_base; +}; + +struct firmware_status { + unsigned short invalid_static_config:1; + unsigned short need_disp_config:1; + unsigned short need_app_config:1; + unsigned short hdl_version:4; + unsigned short reserved:9; +} __packed; + +struct zeroflash_hcd { + bool has_hdl; + bool f35_ready; + const unsigned char *image; + unsigned char *buf; + const struct firmware *fw_entry; + struct work_struct config_work; + struct work_struct firmware_work; + struct workqueue_struct *workqueue; + struct rmi_addr f35_addr; + struct image_info image_info; + struct firmware_status fw_status; + struct syna_tcm_buffer out; + struct syna_tcm_buffer resp; + struct syna_tcm_hcd *tcm_hcd; +}; + +DECLARE_COMPLETION(zeroflash_remove_complete); + +static struct zeroflash_hcd *zeroflash_hcd; + +static int zeroflash_check_uboot(void) +{ + int retval; + unsigned char fn_number; + struct rmi_f35_query query; + struct rmi_pdt_entry p_entry; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + + retval = syna_tcm_rmi_read(tcm_hcd, + PDT_END_ADDR, + &fn_number, + sizeof(fn_number)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read RMI function number\n"); + return retval; + } + + LOGD(tcm_hcd->pdev->dev.parent, + "Found F$%02x\n", + fn_number); + + if (fn_number != UBL_FN_NUMBER) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to find F$35\n"); + return -ENODEV; + } + + if (zeroflash_hcd->f35_ready) + return 0; + + retval = syna_tcm_rmi_read(tcm_hcd, + PDT_START_ADDR, + (unsigned char *)&p_entry, + sizeof(p_entry)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read PDT entry\n"); + return retval; + } + + zeroflash_hcd->f35_addr.query_base = p_entry.query_base_addr; + zeroflash_hcd->f35_addr.command_base = p_entry.command_base_addr; + zeroflash_hcd->f35_addr.control_base = p_entry.control_base_addr; + zeroflash_hcd->f35_addr.data_base = p_entry.data_base_addr; + + retval = syna_tcm_rmi_read(tcm_hcd, + zeroflash_hcd->f35_addr.query_base, + (unsigned char *)&query, + sizeof(query)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read F$35 query\n"); + return retval; + } + + zeroflash_hcd->f35_ready = true; + + if (query.has_query2 && query.has_ctrl7 && query.has_host_download) { + zeroflash_hcd->has_hdl = true; + } else { + LOGE(tcm_hcd->pdev->dev.parent, + "Host download not supported\n"); + zeroflash_hcd->has_hdl = false; + return -ENODEV; + } + + return 0; +} + +static int zeroflash_parse_fw_image(void) +{ + unsigned int idx; + unsigned int addr; + unsigned int offset; + unsigned int length; + unsigned int checksum; + unsigned int flash_addr; + unsigned int magic_value; + unsigned int num_of_areas; + struct image_header *header; + struct image_info *image_info; + struct area_descriptor *descriptor; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + const unsigned char *image; + const unsigned char *content; + + image = zeroflash_hcd->image; + image_info = &zeroflash_hcd->image_info; + header = (struct image_header *)image; + + magic_value = le4_to_uint(header->magic_value); + if (magic_value != IMAGE_FILE_MAGIC_VALUE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid image file magic value\n"); + return -EINVAL; + } + + memset(image_info, 0x00, sizeof(*image_info)); + + offset = sizeof(*header); + num_of_areas = le4_to_uint(header->num_of_areas); + + for (idx = 0; idx < num_of_areas; idx++) { + addr = le4_to_uint(image + offset); + descriptor = (struct area_descriptor *)(image + addr); + offset += 4; + + magic_value = le4_to_uint(descriptor->magic_value); + if (magic_value != FLASH_AREA_MAGIC_VALUE) + continue; + + length = le4_to_uint(descriptor->length); + content = (unsigned char *)descriptor + sizeof(*descriptor); + flash_addr = le4_to_uint(descriptor->flash_addr_words) * 2; + checksum = le4_to_uint(descriptor->checksum); + + if (!memcmp((char *)descriptor->id_string, + BOOT_CONFIG_ID, + strlen(BOOT_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Boot config checksum error\n"); + return -EINVAL; + } + image_info->boot_config.size = length; + image_info->boot_config.data = content; + image_info->boot_config.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Boot config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Boot config flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + F35_APP_CODE_ID, + strlen(F35_APP_CODE_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "APP firmware checksum error\n"); + return -EINVAL; + } + image_info->app_firmware.size = length; + image_info->app_firmware.data = content; + image_info->app_firmware.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Application firmware size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Application firmware flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + APP_CONFIG_ID, + strlen(APP_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Application config checksum error\n"); + return -EINVAL; + } + image_info->app_config.size = length; + image_info->app_config.data = content; + image_info->app_config.flash_addr = flash_addr; + image_info->packrat_number = le4_to_uint(&content[14]); + LOGD(tcm_hcd->pdev->dev.parent, + "Application config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Application config flash address = 0x%08x\n", + flash_addr); + } else if (!memcmp((char *)descriptor->id_string, + DISP_CONFIG_ID, + strlen(DISP_CONFIG_ID))) { + if (checksum != (crc32(~0, content, length) ^ ~0)) { + LOGE(tcm_hcd->pdev->dev.parent, + "Display config checksum error\n"); + return -EINVAL; + } + image_info->disp_config.size = length; + image_info->disp_config.data = content; + image_info->disp_config.flash_addr = flash_addr; + LOGD(tcm_hcd->pdev->dev.parent, + "Display config size = %d\n", + length); + LOGD(tcm_hcd->pdev->dev.parent, + "Display config flash address = 0x%08x\n", + flash_addr); + } + } + + return 0; +} + +static int zeroflash_get_fw_image(void) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + + if (zeroflash_hcd->fw_entry != NULL) + return 0; + + do { + retval = request_firmware(&zeroflash_hcd->fw_entry, + FW_IMAGE_NAME, + tcm_hcd->pdev->dev.parent); + if (retval < 0) { + LOGD(tcm_hcd->pdev->dev.parent, + "Failed to request %s\n", + FW_IMAGE_NAME); + msleep(100); + } else { + break; + } + } while (1); + + LOGD(tcm_hcd->pdev->dev.parent, + "Firmware image size = %d\n", + (unsigned int)zeroflash_hcd->fw_entry->size); + + zeroflash_hcd->image = zeroflash_hcd->fw_entry->data; + + retval = zeroflash_parse_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to parse firmware image\n"); + release_firmware(zeroflash_hcd->fw_entry); + zeroflash_hcd->fw_entry = NULL; + zeroflash_hcd->image = NULL; + return retval; + } + + return 0; +} + +static void zeroflash_download_config(void) +{ + struct firmware_status *fw_status; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + + fw_status = &zeroflash_hcd->fw_status; + + if (!fw_status->need_app_config && !fw_status->need_disp_config) { + if (atomic_read(&tcm_hcd->helper.task) == HELP_NONE) { + atomic_set(&tcm_hcd->helper.task, + HELP_SEND_RESET_NOTIFICATION); + queue_work(tcm_hcd->helper.workqueue, + &tcm_hcd->helper.work); + } + atomic_set(&tcm_hcd->host_downloading, 0); + return; + } + + queue_work(zeroflash_hcd->workqueue, &zeroflash_hcd->config_work); +} + +static void zeroflash_download_firmware(void) +{ + queue_work(zeroflash_hcd->workqueue, &zeroflash_hcd->firmware_work); +} + +static int zeroflash_download_disp_config(void) +{ + int retval; + unsigned char response_code; + struct image_info *image_info; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + static unsigned int retry_count; + + LOGN(tcm_hcd->pdev->dev.parent, + "Downloading display config\n"); + + image_info = &zeroflash_hcd->image_info; + + if (image_info->disp_config.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No display config in image file\n"); + return -EINVAL; + } + + LOCK_BUFFER(zeroflash_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &zeroflash_hcd->out, + image_info->disp_config.size + 2); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + goto unlock_out; + } + + switch (zeroflash_hcd->fw_status.hdl_version) { + case 0: + zeroflash_hcd->out.buf[0] = 1; + break; + case 1: + zeroflash_hcd->out.buf[0] = 2; + break; + default: + retval = -EINVAL; + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid HDL version (%d)\n", + zeroflash_hcd->fw_status.hdl_version); + goto unlock_out; + } + + zeroflash_hcd->out.buf[1] = HDL_DISPLAY_CONFIG; + + retval = secure_memcpy(&zeroflash_hcd->out.buf[2], + zeroflash_hcd->out.buf_size - 2, + image_info->disp_config.data, + image_info->disp_config.size, + image_info->disp_config.size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy display config data\n"); + goto unlock_out; + } + + zeroflash_hcd->out.data_length = image_info->disp_config.size + 2; + + LOCK_BUFFER(zeroflash_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_DOWNLOAD_CONFIG, + zeroflash_hcd->out.buf, + zeroflash_hcd->out.data_length, + &zeroflash_hcd->resp.buf, + &zeroflash_hcd->resp.buf_size, + &zeroflash_hcd->resp.data_length, + &response_code, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_DOWNLOAD_CONFIG)); + if (response_code != STATUS_ERROR) + goto unlock_resp; + retry_count++; + if (DOWNLOAD_RETRY_COUNT && retry_count > DOWNLOAD_RETRY_COUNT) + goto unlock_resp; + } else { + retry_count = 0; + } + + retval = secure_memcpy((unsigned char *)&zeroflash_hcd->fw_status, + sizeof(zeroflash_hcd->fw_status), + zeroflash_hcd->resp.buf, + zeroflash_hcd->resp.buf_size, + sizeof(zeroflash_hcd->fw_status)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy firmware status\n"); + goto unlock_resp; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Display config downloaded\n"); + + retval = 0; + +unlock_resp: + UNLOCK_BUFFER(zeroflash_hcd->resp); + +unlock_out: + UNLOCK_BUFFER(zeroflash_hcd->out); + + return retval; +} + +static int zeroflash_download_app_config(void) +{ + int retval; + unsigned char padding; + unsigned char response_code; + struct image_info *image_info; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + static unsigned int retry_count; + + LOGN(tcm_hcd->pdev->dev.parent, + "Downloading application config\n"); + + image_info = &zeroflash_hcd->image_info; + + if (image_info->app_config.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No application config in image file\n"); + return -EINVAL; + } + + padding = image_info->app_config.size % 8; + if (padding) + padding = 8 - padding; + + LOCK_BUFFER(zeroflash_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &zeroflash_hcd->out, + image_info->app_config.size + 2 + padding); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + goto unlock_out; + } + + switch (zeroflash_hcd->fw_status.hdl_version) { + case 0: + zeroflash_hcd->out.buf[0] = 1; + break; + case 1: + zeroflash_hcd->out.buf[0] = 2; + break; + default: + retval = -EINVAL; + LOGE(tcm_hcd->pdev->dev.parent, + "Invalid HDL version (%d)\n", + zeroflash_hcd->fw_status.hdl_version); + goto unlock_out; + } + + zeroflash_hcd->out.buf[1] = HDL_TOUCH_CONFIG; + + retval = secure_memcpy(&zeroflash_hcd->out.buf[2], + zeroflash_hcd->out.buf_size - 2, + image_info->app_config.data, + image_info->app_config.size, + image_info->app_config.size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy application config data\n"); + goto unlock_out; + } + + zeroflash_hcd->out.data_length = image_info->app_config.size + 2; + zeroflash_hcd->out.data_length += padding; + + LOCK_BUFFER(zeroflash_hcd->resp); + + retval = tcm_hcd->write_message(tcm_hcd, + CMD_DOWNLOAD_CONFIG, + zeroflash_hcd->out.buf, + zeroflash_hcd->out.data_length, + &zeroflash_hcd->resp.buf, + &zeroflash_hcd->resp.buf_size, + &zeroflash_hcd->resp.data_length, + &response_code, + 0); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write command %s\n", + STR(CMD_DOWNLOAD_CONFIG)); + if (response_code != STATUS_ERROR) + goto unlock_resp; + retry_count++; + if (DOWNLOAD_RETRY_COUNT && retry_count > DOWNLOAD_RETRY_COUNT) + goto unlock_resp; + } else { + retry_count = 0; + } + + retval = secure_memcpy((unsigned char *)&zeroflash_hcd->fw_status, + sizeof(zeroflash_hcd->fw_status), + zeroflash_hcd->resp.buf, + zeroflash_hcd->resp.buf_size, + sizeof(zeroflash_hcd->fw_status)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy firmware status\n"); + goto unlock_resp; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Application config downloaded\n"); + + retval = 0; + +unlock_resp: + UNLOCK_BUFFER(zeroflash_hcd->resp); + +unlock_out: + UNLOCK_BUFFER(zeroflash_hcd->out); + + return retval; +} + +static void zeroflash_download_config_work(struct work_struct *work) +{ + int retval; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + + retval = zeroflash_get_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get firmware image\n"); + return; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Start of config download\n"); + + if (zeroflash_hcd->fw_status.need_app_config) { + retval = zeroflash_download_app_config(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to download application config\n"); + return; + } + goto exit; + } + + if (zeroflash_hcd->fw_status.need_disp_config) { + retval = zeroflash_download_disp_config(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to download display config\n"); + return; + } + goto exit; + } + +exit: + LOGN(tcm_hcd->pdev->dev.parent, + "End of config download\n"); + + zeroflash_download_config(); +} + +static int zeroflash_download_app_fw(void) +{ + int retval; + unsigned char command; + struct image_info *image_info; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; +#if RESET_TO_HDL_DELAY_MS + const struct syna_tcm_board_data *bdata = tcm_hcd->hw_if->bdata; +#endif + + LOGN(tcm_hcd->pdev->dev.parent, + "Downloading application firmware\n"); + + image_info = &zeroflash_hcd->image_info; + + if (image_info->app_firmware.size == 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "No application firmware in image file\n"); + return -EINVAL; + } + + LOCK_BUFFER(zeroflash_hcd->out); + + retval = syna_tcm_alloc_mem(tcm_hcd, + &zeroflash_hcd->out, + image_info->app_firmware.size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for out.buf\n"); + UNLOCK_BUFFER(zeroflash_hcd->out); + return retval; + } + + retval = secure_memcpy(zeroflash_hcd->out.buf, + zeroflash_hcd->out.buf_size, + image_info->app_firmware.data, + image_info->app_firmware.size, + image_info->app_firmware.size); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy application firmware data\n"); + UNLOCK_BUFFER(zeroflash_hcd->out); + return retval; + } + + zeroflash_hcd->out.data_length = image_info->app_firmware.size; + + command = F35_WRITE_FW_TO_PMEM_COMMAND; + +#if RESET_TO_HDL_DELAY_MS + gpio_set_value(bdata->reset_gpio, bdata->reset_on_state); + msleep(bdata->reset_active_ms); + gpio_set_value(bdata->reset_gpio, !bdata->reset_on_state); + msleep(RESET_TO_HDL_DELAY_MS); +#endif + + retval = syna_tcm_rmi_write(tcm_hcd, + zeroflash_hcd->f35_addr.control_base + F35_CTRL3_OFFSET, + &command, + sizeof(command)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write F$35 command\n"); + UNLOCK_BUFFER(zeroflash_hcd->out); + return retval; + } + + retval = syna_tcm_rmi_write(tcm_hcd, + zeroflash_hcd->f35_addr.control_base + F35_CTRL7_OFFSET, + zeroflash_hcd->out.buf, + zeroflash_hcd->out.data_length); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to write application firmware data\n"); + UNLOCK_BUFFER(zeroflash_hcd->out); + return retval; + } + + UNLOCK_BUFFER(zeroflash_hcd->out); + + LOGN(tcm_hcd->pdev->dev.parent, + "Application firmware downloaded\n"); + + return 0; +} + +static void zeroflash_download_firmware_work(struct work_struct *work) +{ + int retval; + struct rmi_f35_data data; + struct syna_tcm_hcd *tcm_hcd = zeroflash_hcd->tcm_hcd; + static unsigned int retry_count; + + retval = zeroflash_check_uboot(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Microbootloader support unavailable\n"); + goto exit; + } + + atomic_set(&tcm_hcd->host_downloading, 1); + + retval = syna_tcm_rmi_read(tcm_hcd, + zeroflash_hcd->f35_addr.data_base, + (unsigned char *)&data, + sizeof(data)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to read F$35 data\n"); + goto exit; + } + + if (data.error_code != REQUESTING_FIRMWARE) { + LOGE(tcm_hcd->pdev->dev.parent, + "Microbootloader error code = 0x%02x\n", + data.error_code); + if (data.error_code != CHECKSUM_FAILURE) { + retval = -EIO; + goto exit; + } else { + retry_count++; + } + } else { + retry_count = 0; + } + + retval = zeroflash_get_fw_image(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to get firmware image\n"); + goto exit; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "Start of firmware download\n"); + + retval = zeroflash_download_app_fw(); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to download application firmware\n"); + goto exit; + } + + LOGN(tcm_hcd->pdev->dev.parent, + "End of firmware download\n"); + +exit: + if (retval < 0) + retry_count++; + + if (DOWNLOAD_RETRY_COUNT && retry_count > DOWNLOAD_RETRY_COUNT) { + retval = tcm_hcd->enable_irq(tcm_hcd, false, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable interrupt\n"); + } + } else { + retval = tcm_hcd->enable_irq(tcm_hcd, true, NULL); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to enable interrupt\n"); + } + } +} + +static int zeroflash_init(struct syna_tcm_hcd *tcm_hcd) +{ + zeroflash_hcd = kzalloc(sizeof(*zeroflash_hcd), GFP_KERNEL); + if (!zeroflash_hcd) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to allocate memory for zeroflash_hcd\n"); + return -ENOMEM; + } + + zeroflash_hcd->tcm_hcd = tcm_hcd; + + INIT_BUFFER(zeroflash_hcd->out, false); + INIT_BUFFER(zeroflash_hcd->resp, false); + + zeroflash_hcd->workqueue = + create_singlethread_workqueue("syna_tcm_zeroflash"); + INIT_WORK(&zeroflash_hcd->config_work, + zeroflash_download_config_work); + INIT_WORK(&zeroflash_hcd->firmware_work, + zeroflash_download_firmware_work); + + if (tcm_hcd->init_okay == false && + tcm_hcd->hw_if->bus_io->type == BUS_SPI) + zeroflash_download_firmware(); + + return 0; +} + +static int zeroflash_remove(struct syna_tcm_hcd *tcm_hcd) +{ + if (!zeroflash_hcd) + goto exit; + + if (zeroflash_hcd->fw_entry) + release_firmware(zeroflash_hcd->fw_entry); + + cancel_work_sync(&zeroflash_hcd->config_work); + cancel_work_sync(&zeroflash_hcd->firmware_work); + flush_workqueue(zeroflash_hcd->workqueue); + destroy_workqueue(zeroflash_hcd->workqueue); + + RELEASE_BUFFER(zeroflash_hcd->resp); + RELEASE_BUFFER(zeroflash_hcd->out); + + kfree(zeroflash_hcd); + zeroflash_hcd = NULL; + +exit: + complete(&zeroflash_remove_complete); + + return 0; +} + +static int zeroflash_syncbox(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + unsigned char *fw_status; + + if (!zeroflash_hcd) + return 0; + + switch (tcm_hcd->report.id) { + case REPORT_STATUS: + fw_status = (unsigned char *)&zeroflash_hcd->fw_status; + retval = secure_memcpy(fw_status, + sizeof(zeroflash_hcd->fw_status), + tcm_hcd->report.buffer.buf, + tcm_hcd->report.buffer.buf_size, + sizeof(zeroflash_hcd->fw_status)); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to copy firmware status\n"); + return retval; + } + zeroflash_download_config(); + break; + case REPORT_HDL: + retval = tcm_hcd->enable_irq(tcm_hcd, false, true); + if (retval < 0) { + LOGE(tcm_hcd->pdev->dev.parent, + "Failed to disable interrupt\n"); + return retval; + } + zeroflash_download_firmware(); + break; + default: + break; + } + + return 0; +} + +static int zeroflash_reset(struct syna_tcm_hcd *tcm_hcd) +{ + int retval; + + if (!zeroflash_hcd) { + retval = zeroflash_init(tcm_hcd); + return retval; + } + + return 0; +} + +static struct syna_tcm_module_cb zeroflash_module = { + .type = TCM_ZEROFLASH, + .init = zeroflash_init, + .remove = zeroflash_remove, + .syncbox = zeroflash_syncbox, + .asyncbox = NULL, + .reset = zeroflash_reset, + .suspend = NULL, + .resume = NULL, + .early_suspend = NULL, +}; + +static int __init zeroflash_module_init(void) +{ + return syna_tcm_add_module(&zeroflash_module, true); +} + +static void __exit zeroflash_module_exit(void) +{ + syna_tcm_add_module(&zeroflash_module, false); + + wait_for_completion(&zeroflash_remove_complete); +} + +module_init(zeroflash_module_init); +module_exit(zeroflash_module_exit); + +MODULE_AUTHOR("Synaptics, Inc."); +MODULE_DESCRIPTION("Synaptics TCM Zeroflash Module"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/input/synaptics_tcm.h b/include/linux/input/synaptics_tcm.h new file mode 100644 index 000000000000..256f0478521c --- /dev/null +++ b/include/linux/input/synaptics_tcm.h @@ -0,0 +1,63 @@ +/* + * Synaptics TCM touchscreen driver + * + * Copyright (C) 2017-2019 Synaptics Incorporated. All rights reserved. + * + * Copyright (C) 2017-2019 Scott Lin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND SYNAPTICS + * EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, + * AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS. + * IN NO EVENT SHALL SYNAPTICS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION + * WITH THE USE OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED + * AND BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF COMPETENT JURISDICTION DOES + * NOT PERMIT THE DISCLAIMER OF DIRECT DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' + * TOTAL CUMULATIVE LIABILITY TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. + * DOLLARS. + */ + +#ifndef _SYNAPTICS_TCM_H_ +#define _SYNAPTICS_TCM_H_ + +#define I2C_MODULE_NAME "synaptics_tcm_i2c" +#define SPI_MODULE_NAME "synaptics_tcm_spi" + +struct syna_tcm_board_data { + bool x_flip; + bool y_flip; + bool swap_axes; + int irq_gpio; + int irq_on_state; + int power_gpio; + int power_on_state; + int reset_gpio; + int reset_on_state; + unsigned int spi_mode; + unsigned int power_delay_ms; + unsigned int reset_delay_ms; + unsigned int reset_active_ms; + unsigned int byte_delay_us; + unsigned int block_delay_us; + unsigned int ubl_i2c_addr; + unsigned int ubl_max_freq; + unsigned int ubl_byte_delay_us; + unsigned long irq_flags; + const char *pwr_reg_name; + const char *bus_reg_name; +}; + +#endif -- GitLab From 5b2a8ec35d02fab55352940f7fda2fec8d69f8a5 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 10 Jan 2019 11:46:21 +0530 Subject: [PATCH 0812/1286] msm: boot markers: Add boot markers driver Add boot marker driver and make support for boot stats. Change-Id: Ie37cb7c5b44a391eb180499cf86ac50fcbbb544b Signed-off-by: Venkata Rao Kakani --- drivers/soc/qcom/Kconfig | 10 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/boot_marker.c | 238 +++++++++++++++++++++++++++++++++ drivers/soc/qcom/boot_stats.c | 76 ++++++++--- include/soc/qcom/boot_stats.h | 35 ++++- 5 files changed, 342 insertions(+), 18 deletions(-) create mode 100644 drivers/soc/qcom/boot_marker.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8430d3dea0b..4f9ffcde0718 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -421,6 +421,16 @@ config MSM_BOOT_STATS This figures are reported in mpm sleep clock cycles and have a resolution of 31 bits as 1 bit is used as an overflow check. +config MSM_BOOT_TIME_MARKER + bool "Use MSM boot time marker reporting" + depends on MSM_BOOT_STATS + help + Use this to mark msm boot kpi for measurement. + An instrumentation for boot time measurement. + To create an entry, call "place_marker" function. + At userspace, write marker name to "/sys/kernel/debug/bootkpi/kpi_values" + If unsure, say N + config MSM_CORE_HANG_DETECT tristate "MSM Core Hang Detection Support" help diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index a4104f1fae16..794f5cec5da1 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_QCOM_SCM) += scm.o obj-$(CONFIG_QCOM_EARLY_RANDOM) += early_random.o obj-$(CONFIG_SOC_BUS) += socinfo.o obj-$(CONFIG_MSM_BOOT_STATS) += boot_stats.o +obj-$(CONFIG_MSM_BOOT_TIME_MARKER) += boot_marker.o obj-$(CONFIG_MSM_CORE_HANG_DETECT) += core_hang_detect.o obj-$(CONFIG_QCOM_DCC_V2) += dcc_v2.o obj-$(CONFIG_MSM_GLADIATOR_HANG_DETECT) += gladiator_hang_detect.o diff --git a/drivers/soc/qcom/boot_marker.c b/drivers/soc/qcom/boot_marker.c new file mode 100644 index 000000000000..b7a442c84a98 --- /dev/null +++ b/drivers/soc/qcom/boot_marker.c @@ -0,0 +1,238 @@ +/* Copyright (c) 2016, 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_STRING_LEN 256 +#define BOOT_MARKER_MAX_LEN 40 + +struct boot_marker { + char marker_name[BOOT_MARKER_MAX_LEN]; + unsigned long long int timer_value; + struct list_head list; + struct mutex lock; +}; + +static struct dentry *dent_bkpi, *dent_bkpi_status, *dent_mpm_timer; +static struct boot_marker boot_marker_list; + +static void _create_boot_marker(const char *name, + unsigned long long int timer_value) +{ + struct boot_marker *new_boot_marker; + + pr_debug("%-41s:%llu.%03llu seconds\n", name, + timer_value/TIMER_KHZ, + ((timer_value % TIMER_KHZ) + * 1000) / TIMER_KHZ); + + new_boot_marker = kmalloc(sizeof(*new_boot_marker), GFP_KERNEL); + if (!new_boot_marker) + return; + + strlcpy(new_boot_marker->marker_name, name, + sizeof(new_boot_marker->marker_name)); + new_boot_marker->timer_value = timer_value; + + mutex_lock(&boot_marker_list.lock); + list_add_tail(&(new_boot_marker->list), &(boot_marker_list.list)); + mutex_unlock(&boot_marker_list.lock); +} + +static void set_bootloader_stats(void) +{ + _create_boot_marker("M - APPSBL Start - ", + readl_relaxed(&boot_stats->bootloader_start)); + _create_boot_marker("M - APPSBL Display Init - ", + readl_relaxed(&boot_stats->bootloader_display)); + _create_boot_marker("M - APPSBL Early-Domain Start - ", + readl_relaxed(&boot_stats->bootloader_early_domain_start)); + _create_boot_marker("D - APPSBL Kernel Load Time - ", + readl_relaxed(&boot_stats->bootloader_load_kernel)); + _create_boot_marker("D - APPSBL Kernel Auth Time - ", + readl_relaxed(&boot_stats->bootloader_checksum)); + _create_boot_marker("M - APPSBL End - ", + readl_relaxed(&boot_stats->bootloader_end)); +} + +void place_marker(const char *name) +{ + _create_boot_marker((char *) name, msm_timer_get_sclk_ticks()); +} +EXPORT_SYMBOL(place_marker); + +static ssize_t bootkpi_reader(struct file *fp, char __user *user_buffer, + size_t count, loff_t *position) +{ + int rc = 0; + char *buf; + int temp = 0; + struct boot_marker *marker; + + buf = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mutex_lock(&boot_marker_list.lock); + list_for_each_entry(marker, &boot_marker_list.list, list) { + temp += scnprintf(buf + temp, PAGE_SIZE - temp, + "%-41s:%llu.%03llu seconds\n", + marker->marker_name, + marker->timer_value/TIMER_KHZ, + (((marker->timer_value % TIMER_KHZ) + * 1000) / TIMER_KHZ)); + } + mutex_unlock(&boot_marker_list.lock); + rc = simple_read_from_buffer(user_buffer, count, position, buf, temp); + kfree(buf); + return rc; +} + +static ssize_t bootkpi_writer(struct file *fp, const char __user *user_buffer, + size_t count, loff_t *position) +{ + int rc = 0; + char buf[MAX_STRING_LEN]; + + if (count > MAX_STRING_LEN) + return -EINVAL; + rc = simple_write_to_buffer(buf, + sizeof(buf) - 1, position, user_buffer, count); + if (rc < 0) + return rc; + buf[rc] = '\0'; + place_marker(buf); + return rc; +} + +static int bootkpi_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations fops_bkpi = { + .owner = THIS_MODULE, + .open = bootkpi_open, + .read = bootkpi_reader, + .write = bootkpi_writer, +}; + +static ssize_t mpm_timer_read(struct file *fp, char __user *user_buffer, + size_t count, loff_t *position) +{ + unsigned long long int timer_value; + int rc = 0; + char buf[100]; + int temp = 0; + + timer_value = msm_timer_get_sclk_ticks(); + + temp = scnprintf(buf, sizeof(buf), "%llu.%03llu seconds\n", + timer_value/TIMER_KHZ, + (((timer_value % TIMER_KHZ) * 1000) / TIMER_KHZ)); + + rc = simple_read_from_buffer(user_buffer, count, position, buf, temp); + + return rc; +} + +static int mpm_timer_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int mpm_timer_mmap(struct file *file, struct vm_area_struct *vma) +{ + phys_addr_t addr = msm_timer_get_pa(); + + if (vma->vm_flags & VM_WRITE) + return -EPERM; + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + return vm_iomap_memory(vma, addr, PAGE_SIZE); +} + +static const struct file_operations fops_mpm_timer = { + .owner = THIS_MODULE, + .open = mpm_timer_open, + .read = mpm_timer_read, + .mmap = mpm_timer_mmap, +}; + +static int __init init_bootkpi(void) +{ + dent_bkpi = debugfs_create_dir("bootkpi", NULL); + if (IS_ERR_OR_NULL(dent_bkpi)) + return -ENODEV; + + dent_bkpi_status = debugfs_create_file_unsafe("kpi_values", + 0666, dent_bkpi, NULL, &fops_bkpi); + if (IS_ERR_OR_NULL(dent_bkpi_status)) { + debugfs_remove(dent_bkpi); + dent_bkpi = NULL; + pr_err("boot_marker: Could not create 'kpi_values' debugfs file\n"); + return -ENODEV; + } + + dent_mpm_timer = debugfs_create_file("mpm_timer", + 0444, dent_bkpi, NULL, &fops_mpm_timer); + if (IS_ERR_OR_NULL(dent_mpm_timer)) { + debugfs_remove(dent_bkpi_status); + dent_bkpi_status = NULL; + debugfs_remove(dent_bkpi); + dent_bkpi = NULL; + pr_err("boot_marker: Could not create 'mpm_timer' debugfs file\n"); + return -ENODEV; + } + + INIT_LIST_HEAD(&boot_marker_list.list); + mutex_init(&boot_marker_list.lock); + set_bootloader_stats(); + return 0; +} +subsys_initcall(init_bootkpi); + +static void __exit exit_bootkpi(void) +{ + struct boot_marker *marker; + struct boot_marker *temp_addr; + + debugfs_remove_recursive(dent_bkpi); + mutex_lock(&boot_marker_list.lock); + list_for_each_entry_safe(marker, temp_addr, &boot_marker_list.list, + list) { + list_del(&marker->list); + kfree(marker); + } + mutex_unlock(&boot_marker_list.lock); + boot_stats_exit(); +} +module_exit(exit_bootkpi); + +MODULE_DESCRIPTION("MSM boot key performance indicators"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/qcom/boot_stats.c b/drivers/soc/qcom/boot_stats.c index c392df226914..2938cf41586f 100644 --- a/drivers/soc/qcom/boot_stats.c +++ b/drivers/soc/qcom/boot_stats.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2017 The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,17 +22,12 @@ #include #include #include - -struct boot_stats { - uint32_t bootloader_start; - uint32_t bootloader_end; - uint32_t bootloader_display; - uint32_t bootloader_load_kernel; -}; +#include static void __iomem *mpm_counter_base; +static phys_addr_t mpm_counter_pa; static uint32_t mpm_counter_freq; -static struct boot_stats __iomem *boot_stats; +struct boot_stats __iomem *boot_stats; static int mpm_parse_dt(void) { @@ -75,17 +70,58 @@ static int mpm_parse_dt(void) static void print_boot_stats(void) { pr_info("KPI: Bootloader start count = %u\n", - readl_relaxed(&boot_stats->bootloader_start)); + readl_relaxed(&boot_stats->bootloader_start)); pr_info("KPI: Bootloader end count = %u\n", - readl_relaxed(&boot_stats->bootloader_end)); + readl_relaxed(&boot_stats->bootloader_end)); pr_info("KPI: Bootloader display count = %u\n", - readl_relaxed(&boot_stats->bootloader_display)); + readl_relaxed(&boot_stats->bootloader_display)); pr_info("KPI: Bootloader load kernel count = %u\n", - readl_relaxed(&boot_stats->bootloader_load_kernel)); + readl_relaxed(&boot_stats->bootloader_load_kernel)); pr_info("KPI: Kernel MPM timestamp = %u\n", - readl_relaxed(mpm_counter_base)); + readl_relaxed(mpm_counter_base)); pr_info("KPI: Kernel MPM Clock frequency = %u\n", - mpm_counter_freq); + mpm_counter_freq); +} + +unsigned long long int msm_timer_get_sclk_ticks(void) +{ + unsigned long long int t1, t2; + int loop_count = 10; + int loop_zero_count = 3; + u64 tmp = USEC_PER_SEC; + void __iomem *sclk_tick; + + do_div(tmp, TIMER_KHZ); + tmp /= (loop_zero_count-1); + sclk_tick = mpm_counter_base; + if (!sclk_tick) + return -EINVAL; + while (loop_zero_count--) { + t1 = __raw_readl_no_log(sclk_tick); + do { + udelay(1); + t2 = t1; + t1 = __raw_readl_no_log(sclk_tick); + } while ((t2 != t1) && --loop_count); + if (!loop_count) { + pr_err("boot_stats: SCLK did not stabilize\n"); + return 0; + } + if (t1) + break; + + udelay(tmp); + } + if (!loop_zero_count) { + pr_err("boot_stats: SCLK reads zero\n"); + return 0; + } + return t1; +} + +phys_addr_t msm_timer_get_pa(void) +{ + return mpm_counter_pa; } int boot_stats_init(void) @@ -98,9 +134,15 @@ int boot_stats_init(void) print_boot_stats(); - iounmap(boot_stats); - iounmap(mpm_counter_base); + if (!(boot_marker_enabled())) + boot_stats_exit(); return 0; } +int boot_stats_exit(void) +{ + iounmap(boot_stats); + iounmap(mpm_counter_base); + return 0; +} diff --git a/include/soc/qcom/boot_stats.h b/include/soc/qcom/boot_stats.h index 28950cbf3941..d9b6fc803439 100644 --- a/include/soc/qcom/boot_stats.h +++ b/include/soc/qcom/boot_stats.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,7 +11,40 @@ */ #ifdef CONFIG_MSM_BOOT_STATS + +#define TIMER_KHZ 32768 +extern struct boot_stats __iomem *boot_stats; + +struct boot_stats { + uint32_t bootloader_start; + uint32_t bootloader_end; + uint32_t bootloader_display; + uint32_t bootloader_load_kernel; + uint32_t load_kernel_start; + uint32_t load_kernel_end; +#ifdef CONFIG_MSM_BOOT_TIME_MARKER + uint32_t bootloader_early_domain_start; + uint32_t bootloader_checksum; +#endif +}; + int boot_stats_init(void); +int boot_stats_exit(void); +unsigned long long int msm_timer_get_sclk_ticks(void); +phys_addr_t msm_timer_get_pa(void); #else static inline int boot_stats_init(void) { return 0; } +static inline unsigned long long int msm_timer_get_sclk_ticks(void) +{ + return 0; +} +static inline phys_addr_t msm_timer_get_pa(void) { return 0; } +#endif + +#ifdef CONFIG_MSM_BOOT_TIME_MARKER +static inline int boot_marker_enabled(void) { return 1; } +void place_marker(const char *name); +#else +static inline void place_marker(char *name) { }; +static inline int boot_marker_enabled(void) { return 0; } #endif -- GitLab From 719a78fe74534b2d92c9e011050e1c3585bb8c9c Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 10 Jan 2019 11:19:46 +0530 Subject: [PATCH 0813/1286] boot markers: msm: place markers for kernel end mark kernel end boot markers for boot kpi measurement. Change-Id: I22fae99bd2678c3c111ecf481ae1d03542928779 Signed-off-by: Venkata Rao Kakani --- init/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/init/main.c b/init/main.c index c4a45145e102..fa1f183b950e 100644 --- a/init/main.c +++ b/init/main.c @@ -94,6 +94,7 @@ #include #include #include +#include static int kernel_init(void *); @@ -1007,6 +1008,7 @@ static int __ref kernel_init(void *unused) numa_default_policy(); rcu_end_inkernel_boot(); + place_marker("M : Kernel End"); if (ramdisk_execute_command) { ret = run_init_process(ramdisk_execute_command); -- GitLab From f16837717c63d323406626d56ba2b1f0b1add8fe Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 10 Jan 2019 11:14:33 +0530 Subject: [PATCH 0814/1286] defconfig: msm: sa6155p: Enable boot markers Enable boot markers feature for sa6155p. Change-Id: I09d6b3c1d6fd88185321748941efec48237aa65e Signed-off-by: Venkata Rao Kakani --- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index c6ab2f95c01c..100c4304d6be 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -572,6 +572,7 @@ CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y +CONFIG_MSM_BOOT_TIME_MARKER=y CONFIG_QCOM_DCC_V2=y CONFIG_QCOM_SECURE_BUFFER=y CONFIG_QCOM_EUD=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index c420758e5ae7..bbdaae00c6f6 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -595,6 +595,7 @@ CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y +CONFIG_MSM_BOOT_TIME_MARKER=y CONFIG_MSM_CORE_HANG_DETECT=y CONFIG_QCOM_DCC_V2=y CONFIG_MSM_GLADIATOR_HANG_DETECT=y -- GitLab From 5d480245fe99ed4858a28ff802552f73c251703e Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Fri, 4 Jan 2019 17:01:03 +0530 Subject: [PATCH 0815/1286] msm: camera: compilation fix in isp Fix the compilation issue due to improper pointer assignment. Change-Id: I14de543656e943b15a4878735325b2df2b5dba19 Signed-off-by: Abhishek Jain --- drivers/media/platform/msm/camera_v2/isp/msm_isp.c | 4 ++-- drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c | 4 ++-- drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c index 0216a1edc2ba..dba4b7e38977 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -668,7 +668,7 @@ int vfe_hw_probe(struct platform_device *pdev) ISP_DBG("%s: device id = %d\n", __func__, pdev->id); vfe_dev->pdev = pdev; - hw_info = &vfe_dev->hw_info; + hw_info = vfe_dev->hw_info; rc = vfe_dev->hw_info->vfe_ops.platform_ops.get_platform_data(vfe_dev); if (rc < 0) { diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c index f81f65828a1e..b1fe6bdbb5b3 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2372,7 +2372,7 @@ static void msm_isp_input_disable(struct vfe_device *vfe_dev, int cmd_type) vfe_dev->hw_info->vfe_ops.core_ops.update_camif_state( vfe_dev, DISABLE_CAMIF); } - hw_info = &vfe_dev->hw_info; + hw_info = vfe_dev->hw_info; /* * halt and reset hardware if all streams are disabled, in this case * ispif is halted immediately as well diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c index ccf4de7cbf1c..60372f85044d 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2156,7 +2156,7 @@ irqreturn_t msm_isp_process_irq(int irq_num, void *data) ping_pong_status = vfe_dev->hw_info->vfe_ops.axi_ops.get_pingpong_status(vfe_dev); - hw_info = &vfe_dev->hw_info; + hw_info = vfe_dev->hw_info; /* Get the dual IRQ status in dual mode*/ if (vfe_dev->dual_vfe_sync_mode) hw_info->vfe_ops.irq_ops.read_and_clear_dual_irq_status( -- GitLab From d48a8bb6eb118f32c276990fe68a7683adef94ff Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 14 Dec 2018 12:36:24 +0530 Subject: [PATCH 0816/1286] clk: qcom: rcg2: Add support for hardware control mode Add a flag to indicate to support and enable hardware control mode of an RCG. Change-Id: I21194a463441ea13b7575a4174b1f96504b42b1e Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 197ba2ce6f28..0595c0a66e7e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -177,6 +177,7 @@ struct clk_rcg2 { u8 flags; #define FORCE_ENABLE_RCG BIT(0) #define DFS_ENABLE_RCG BIT(1) +#define HW_CLK_CTRL_MODE BIT(2) }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 63bbb49afc17..bd21c1743385 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -446,6 +446,8 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; + if (rcg->flags & HW_CLK_CTRL_MODE) + cfg |= CFG_HW_CLK_CTRL_MASK; ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, mask, cfg); if (ret) @@ -609,6 +611,9 @@ static int clk_rcg2_prepare(struct clk_hw *hw) u32 cfg; int ret; + if (rcg->flags & HW_CLK_CTRL_MODE) + return 0; + ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); if (ret) return ret; -- GitLab From 8f926c73d64b7fe0240610cf6554c15c38cc7ffc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 14 Dec 2018 14:39:04 +0530 Subject: [PATCH 0817/1286] clk: qcom: dispcc: Add hardware control mode for MDP clock Add RCG flag for MDP clock to support hardware control mode for switching the RCG source. Change-Id: I296364b3e5c0e50d1be9f4b393c26deb867f1290 Signed-off-by: Taniya Das --- drivers/clk/qcom/dispcc-sm8150.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/dispcc-sm8150.c b/drivers/clk/qcom/dispcc-sm8150.c index 526cc5a78b68..e18a12843f07 100644 --- a/drivers/clk/qcom/dispcc-sm8150.c +++ b/drivers/clk/qcom/dispcc-sm8150.c @@ -722,6 +722,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .parent_map = disp_cc_parent_map_5, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .enable_safe_config = true, + .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_names = disp_cc_parent_names_5, -- GitLab From 4c5ca3e85c8df0bcab8f6597ad3f687c815d5d49 Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Wed, 9 Jan 2019 15:21:16 +0530 Subject: [PATCH 0818/1286] defconfig: trinket: Enable camera driver support for trinket Changes to add variables in defconfig to enable camera driver support for trinket. Signed-off-by: Abhishek Jain Change-Id: Ib161354a052f7ec23f165b1c41574723ff7c91de --- arch/arm64/configs/vendor/trinket_defconfig | 30 ++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..6d12d2971551 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -381,7 +381,33 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SPECTRA_CAMERA=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSMB_CAMERA=y +CONFIG_MSMB_CAMERA_DEBUG=y +CONFIG_MSM_CAMERA_SENSOR=y +CONFIG_MSM_CPP=y +CONFIG_MSM_CCI=y +CONFIG_MSM_CSI20_HEADER=y +CONFIG_MSM_CSI22_HEADER=y +CONFIG_MSM_CSI30_HEADER=y +CONFIG_MSM_CSI31_HEADER=y +CONFIG_MSM_CSIPHY=y +CONFIG_MSM_CSID=y +CONFIG_MSM_EEPROM=y +CONFIG_MSM_ISPIF=y +CONFIG_IMX134=y +CONFIG_IMX132=y +CONFIG_OV9724=y +CONFIG_OV5648=y +CONFIG_GC0339=y +CONFIG_OV8825=y +CONFIG_OV8865=y +CONFIG_s5k4e1=y +CONFIG_OV12830=y +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y +CONFIG_MSMB_JPEG=y +CONFIG_MSM_FD=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y @@ -462,8 +488,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y CONFIG_LEDS_QPNP_FLASH_V2=y CONFIG_LEDS_QPNP_HAPTICS=y CONFIG_LEDS_QTI_TRI_LED=y -- GitLab From 62dd783d6af94073856f670ad8aa1bbdb53fcd93 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sun, 4 Nov 2018 00:21:02 +0530 Subject: [PATCH 0819/1286] clk: Move VDD voltage voting from core clock to top clock Current vdd voting happens from top to core (clock on which the rate has been requested), which has issues with sources which are slewing. In the cases where the PLLs are slewing the RCGs should have the voltage already maintained for the new frequency before the PLLs are slewed. Modify clk_core_set_rate_nolock() so that it votes for all new frequency voltages for the core clock and each of its parent clocks before physically changing any rates. Change-Id: Idf02bedcfb05a37e0c944ebe36d2dcf9032ae0d8 Signed-off-by: Taniya Das --- drivers/clk/clk.c | 98 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 83 insertions(+), 15 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index e562c92b63c9..3c7945e50a31 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -65,7 +65,9 @@ struct clk_core { unsigned long rate; unsigned long req_rate; unsigned long new_rate; + unsigned long old_rate; struct clk_core *new_parent; + struct clk_core *old_parent; struct clk_core *new_child; unsigned long flags; bool orphan; @@ -1793,7 +1795,7 @@ static int clk_change_rate(struct clk_core *core) struct clk_core *parent = NULL; int rc = 0; - old_rate = core->rate; + core->old_rate = old_rate = core->rate; if (core->new_parent) { parent = core->new_parent; @@ -1803,6 +1805,8 @@ static int clk_change_rate(struct clk_core *core) best_parent_rate = core->parent->rate; } + core->old_parent = core->parent; + if (core->flags & CLK_SET_RATE_UNGATE) { unsigned long flags; @@ -1814,15 +1818,9 @@ static int clk_change_rate(struct clk_core *core) trace_clk_set_rate(core, core->new_rate); - /* Enforce vdd requirements for new frequency. */ - if (core->prepare_count) { - rc = clk_vote_rate_vdd(core, core->new_rate); - if (rc) - goto out; - } - if (core->new_parent && core->new_parent != core->parent) { old_parent = __clk_set_parent_before(core, core->new_parent); + core->old_parent = old_parent; trace_clk_set_parent(core, core->new_parent); if (core->ops->set_rate_and_parent) { @@ -1850,10 +1848,6 @@ static int clk_change_rate(struct clk_core *core) trace_clk_set_rate_complete(core, core->new_rate); - /* Release vdd requirements for old frequency. */ - if (core->prepare_count) - clk_unvote_rate_vdd(core, old_rate); - core->rate = clk_recalc(core, best_parent_rate); if (core->flags & CLK_SET_RATE_UNGATE) { @@ -1894,14 +1888,78 @@ static int clk_change_rate(struct clk_core *core) return rc; err_set_rate: - if (core->prepare_count) - clk_unvote_rate_vdd(core, core->new_rate); -out: trace_clk_set_rate_complete(core, core->new_rate); return rc; } +static int vote_vdd_up(struct clk_core *core) +{ + struct clk_core *parent = NULL; + int ret, cur_level, next_level; + + /* sanity */ + if (IS_ERR_OR_NULL(core)) + return 0; + + if (core->vdd_class) { + cur_level = clk_find_vdd_level(core, core->rate); + next_level = clk_find_vdd_level(core, core->new_rate); + if (cur_level == next_level) + return 0; + } + + /* save parent rate, if it exists */ + if (core->new_parent) + parent = core->new_parent; + else if (core->parent) + parent = core->parent; + + if (core->prepare_count && core->new_rate) { + ret = clk_vote_rate_vdd(core, core->new_rate); + if (ret) + return ret; + } + + vote_vdd_up(parent); + + return 0; +} + +static int vote_vdd_down(struct clk_core *core) +{ + struct clk_core *parent; + unsigned long rate; + int cur_level, old_level; + + /* sanity */ + if (IS_ERR_OR_NULL(core)) + return 0; + + rate = core->old_rate; + + /* New rate set was a failure */ + if (DIV_ROUND_CLOSEST(core->rate, 1000) != + DIV_ROUND_CLOSEST(core->new_rate, 1000)) + rate = core->new_rate; + + if (core->vdd_class) { + cur_level = clk_find_vdd_level(core, core->rate); + old_level = clk_find_vdd_level(core, core->old_rate); + if ((cur_level == old_level) + || !core->vdd_class->level_votes[old_level]) + return 0; + } + + parent = core->old_parent; + + if (core->prepare_count && rate) + clk_unvote_rate_vdd(core, rate); + + vote_vdd_down(parent); + + return 0; +} static int clk_core_set_rate_nolock(struct clk_core *core, unsigned long req_rate) { @@ -1933,17 +1991,27 @@ static int clk_core_set_rate_nolock(struct clk_core *core, return -EBUSY; } + /* Enforce the VDD for new frequency */ + ret = vote_vdd_up(core); + if (ret) + return ret; + /* change the rates */ ret = clk_change_rate(top); if (ret) { pr_err("%s: failed to set %s clock to run at %lu\n", __func__, top->name, req_rate); clk_propagate_rate_change(top, ABORT_RATE_CHANGE); + /* Release vdd requirements for new frequency. */ + vote_vdd_down(core); return ret; } core->req_rate = req_rate; + /* Release vdd requirements for old frequency. */ + vote_vdd_down(core); + return ret; } -- GitLab From 95b44dbb8d67ee752988c7fb66dd440a7086daf6 Mon Sep 17 00:00:00 2001 From: Tanya Dixit Date: Thu, 10 Jan 2019 17:42:28 +0530 Subject: [PATCH 0820/1286] sound: dt-bindings: Add dt-bindings for swr wakeup irq property Add a new swr wakeup irq property to differentiate between interrupt from TLMM and QGIC. Change-Id: I2142266d00e3b792088a1a3b9513d4e1b33ed525 Signed-off-by: Tanya Dixit --- Documentation/devicetree/bindings/sound/wcd_codec.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/wcd_codec.txt b/Documentation/devicetree/bindings/sound/wcd_codec.txt index 32f8fd594c04..7f3183e8a97f 100644 --- a/Documentation/devicetree/bindings/sound/wcd_codec.txt +++ b/Documentation/devicetree/bindings/sound/wcd_codec.txt @@ -540,6 +540,10 @@ Required properties: - qcom,tx-swr-gpios: phandle for SWR data and clock GPIOs of TX macro - qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro +Optional Properties: + - qcom,swr-wakeup-irq: Specifies whether the interrupt line is on GPIO + or GQIC + Example: &bolero { -- GitLab From 64bc23408823601914103eac4a04bb8937b4f929 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 20 Dec 2018 18:11:43 +0530 Subject: [PATCH 0821/1286] ARM: dts: msm: Enable cx ipeak support for TRINKET Enable the v2 version of the cx ipeak driver. Configure the register address space as per TRINKET. CRs-Fixed: 2370730 Change-Id: I621479e2aa4f45cdc5acee4f1e5ef139cca9344f Signed-off-by: Vikash Garodia --- arch/arm64/boot/dts/qcom/trinket.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 46d0db74b139..f311acd262a9 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2101,6 +2101,11 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xc00c>; + }; }; #include "pmi632.dtsi" -- GitLab From 25b792e422f660e58f72376f76487a6d41bb3191 Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Thu, 10 Jan 2019 17:02:11 +0530 Subject: [PATCH 0822/1286] ARM: dts: msm: Add audio DT changes to support trinket Add changes to support audio on trinket target. Change-Id: Ic6083675db9b107dd1980e6ce5c86de026493df9 Signed-off-by: Aditya Bavanari --- .../boot/dts/qcom/trinket-audio-overlay.dtsi | 353 +++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-audio.dtsi | 140 +++++++ .../boot/dts/qcom/trinket-idp-overlay.dts | 1 + arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 369 +++++++++++++++++- arch/arm64/boot/dts/qcom/trinket.dtsi | 14 + 5 files changed, 876 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-audio.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi new file mode 100644 index 000000000000..9a81ce36b919 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&bolero { + qcom,num-macros = <4>; + qcom,va-without-decimation; + tx_macro: tx-macro@0a460000 { + compatible = "qcom,tx-macro"; + reg = <0x0a460000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-swr-gpios = <&tx_swr_gpios>; + qcom,tx-dmic-sample-rate = <2400000>; + swr2: tx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <3>; + swrm-io-base = <0x0a470000 0x0>; + interrupts = <0 184 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-wakeup-irq = <&tlmm 107 0>; + qcom,swr-wakeup-required = <1>; + qcom,swr-num-ports = <5>; + qcom,swr-port-mapping = <1 PCM_OUT1 0xF>, + <2 ADC1 0x1>, <2 ADC2 0x2>, + <3 ADC3 0x1>, <3 ADC4 0x2>, + <4 DMIC0 0x1>, <4 DMIC1 0x2>, + <4 DMIC2 0x4>, <4 DMIC3 0x8>, + <5 DMIC4 0x1>, <5 DMIC5 0x2>, + <5 DMIC6 0x4>, <5 DMIC7 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + wcd937x_tx_slave: wcd937x-tx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0 0x01170223>; + }; + }; + }; + + rx_macro: rx-macro@0a440000 { + compatible = "qcom,rx-macro"; + reg = <0x0a440000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a041020>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <2>; + swrm-io-base = <0x0a450000 0x0>; + interrupts = <0 188 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <5>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + wcd937x_rx_slave: wcd937x-rx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0 0x01170224>; + }; + }; + }; + + wsa_macro: wsa-macro@0a480000 { + compatible = "qcom,wsa-macro"; + reg = <0x0a480000 0x0>; + clock-names = "wsa_core_clk", "wsa_npl_clk"; + clocks = <&clock_audio_wsa_1 0>, + <&clock_audio_wsa_2 0>; + qcom,wsa-swr-gpios = <&wsa_swr_gpios>; + qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; + swr0: wsa_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <1>; + swrm-io-base = <0xa4900000 0x0>; + interrupts = <0 79 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr-num-dev = <1>; + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + }; + }; + + va_macro: va-macro@0a4a0000 { + compatible = "qcom,va-macro"; + reg = <0x0a4a0000 0x0>; + clock-names = "va_core_clk"; + clocks = <&clock_audio_va 0>; + }; + + wcd937x_codec: wcd937x-codec { + compatible = "qcom,wcd937x-codec"; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, + <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, + <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, + <4 DSD_R 0x2 0 DSD_R>; + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, + <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>, + <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>, + <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>, + <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, + <3 DMIC5 0x8 0 DMIC7>; + + qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>; + qcom,rx-slave = <&wcd937x_rx_slave>; + qcom,tx-slave = <&wcd937x_tx_slave>; + + cdc-vdd-ldo-rxtx-supply = <&L9A>; + qcom,cdc-vdd-ldo-rxtx-voltage = <1800000 1800000>; + qcom,cdc-vdd-ldo-rxtx-current = <25000>; + + cdc-vddpx-1-supply = <&L9A>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-buck-supply = <&L14A>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-mic-bias-supply = <&L15A>; + qcom,cdc-vdd-mic-bias-voltage = <3104000 3104000>; + qcom,cdc-vdd-mic-bias-current = <25000>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx", + "cdc-vddpx-1", + "cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; + }; +}; + +&sm6150_snd { + qcom,model = "trinket-idp-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + qcom,ext-disp-audio-rx = <0>; + qcom,wcn-btfm = <0>; + qcom,audio-routing = + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "TX DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "TX DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "TX DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "TX DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "WSA_SPK1 OUT", "VA_MCLK", + "WSA_SPK2 OUT", "VA_MCLK"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,codec-max-aux-devs = <1>; + qcom,codec-aux-devs = <&wcd937x_codec>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, + <&bolero>; +}; + +&soc { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + }; + + wsa_swr_gpios: wsa_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>; + pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + }; + + tx_swr_gpios: tx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + }; + + wsa_spkr_en1: wsa_spkr_en1_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wcd937x_rst_gpio: msm_cdc_pinctrl@120 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd937x_reset_active>; + pinctrl-1 = <&wcd937x_reset_sleep>; + }; + + clock_audio_wsa_1: wsa_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x309>; + #clock-cells = <1>; + }; + + clock_audio_wsa_2: wsa_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30A>; + #clock-cells = <1>; + }; + + clock_audio_va: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30B>; + #clock-cells = <1>; + }; + + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-audio.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio.dtsi new file mode 100644 index 000000000000..cd4808674fa6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-audio.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + iommus = <&apps_smmu 0x0041 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&soc { + qcom,avtimer@0a22e000 { + compatible = "qcom,avtimer"; + reg = <0x0a22e00c 0x4>, + <0x0a22e010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <192>; + qcom,clk-mult = <10>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + tx_macro: tx-macro@0a460000 { + swr2: tx_swr_master { + }; + }; + + rx_macro: rx-macro@0a440000 { + swr1: rx_swr_master { + }; + }; + + wsa_macro: wsa-macro@0a480000 { + swr0: wsa_swr_master { + }; + }; + }; + }; +}; + +&q6core { + sm6150_snd: sound { + compatible = "qcom,sm6150-asoc-snd"; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,wcn-btfm = <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, + <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, + <&wsa_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>; + asoc-cpu-names = "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.16400", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-cdc-dma-dev.45056", + "msm-dai-cdc-dma-dev.45057", + "msm-dai-cdc-dma-dev.45058", + "msm-dai-cdc-dma-dev.45059", + "msm-dai-cdc-dma-dev.45061", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts index ee4dc2b9d74c..9a7815bd42c4 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts @@ -15,6 +15,7 @@ #include #include "trinket-idp.dtsi" +#include "trinket-audio-overlay.dtsi" / { model = "IDP"; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 1a25be5ab4a6..1ecf910f971b 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -609,6 +609,373 @@ }; }; + fsa_usbc_ana_en_n@124 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio18"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio18"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio19"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio19"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio19"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio19"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd937x_reset_active: wcd937x_reset_active { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <16>; + output-high; + }; + }; + + wcd937x_reset_sleep: wcd937x_reset_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio125"; + function = "DMIC0_CLK"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio125"; + function = "DMIC0_CLK"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio126"; + function = "DMIC0_DATA"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio126"; + function = "DMIC0_DATA"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic23_clk_active: dmic23_clk_active { + mux { + pins = "gpio127"; + function = "DMIC1_CLK"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic23_clk_sleep: dmic23_clk_sleep { + mux { + pins = "gpio127"; + function = "DMIC1_CLK"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic23_data_active: dmic23_data_active { + mux { + pins = "gpio128"; + function = "DMIC1_DATA"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic23_data_sleep: dmic23_data_sleep { + mux { + pins = "gpio128"; + function = "DMIC1_DATA"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + tx_swr_clk_sleep: tx_swr_clk_sleep { + mux { + pins = "gpio106"; + function = "swr_tx"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_clk_active: tx_swr_clk_active { + mux { + pins = "gpio106"; + function = "swr_tx"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + tx_swr_data1_sleep: tx_swr_data1_sleep { + mux { + pins = "gpio107"; + function = "swr_tx"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_data1_active: tx_swr_data1_active { + mux { + pins = "gpio107"; + function = "swr_tx"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + tx_swr_data2_sleep: tx_swr_data2_sleep { + mux { + pins = "gpio108"; + function = "swr_tx"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_data2_active: tx_swr_data2_active { + mux { + pins = "gpio108"; + function = "swr_tx"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + rx_swr_clk_sleep: rx_swr_clk_sleep { + mux { + pins = "gpio110"; + function = "swr_rx"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + rx_swr_clk_active: rx_swr_clk_active { + mux { + pins = "gpio110"; + function = "swr_rx"; + }; + + config { + pins = "gpio110"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + + rx_swr_data_sleep: rx_swr_data_sleep { + mux { + pins = "gpio111", "gpio112"; + function = "swr_rx"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + rx_swr_data_active: rx_swr_data_active { + mux { + pins = "gpio111", "gpio112"; + function = "swr_rx"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <8>; + bias-bus-hold; + }; + }; + /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 46d0db74b139..a62642cb84eb 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -35,6 +35,9 @@ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + swr0 = &swr0; + swr1 = &swr1; + swr2 = &swr2; }; cpus { @@ -2329,4 +2332,15 @@ status = "ok"; }; +&qupv3_se1_i2c { + status = "ok"; + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + pinctrl-names = "default"; + pinctrl-0 = <&fsa_usbc_ana_en>; + }; +}; + +#include "trinket-audio.dtsi" #include "trinket-thermal.dtsi" -- GitLab From fe194d7477492e3ea9660b40351805a7b34ef3bc Mon Sep 17 00:00:00 2001 From: Konstantin Dorfman Date: Thu, 10 Jan 2019 11:07:46 +0200 Subject: [PATCH 0823/1286] rpmsg: glink: fix destroy channel endpoint logic When rpmsg client driver destroys last channel endpoint, remove rpmsg device is triggered. In both cases (destroy endpoint and remove device) a glink close command sent to the remote peer. This change, when for removing rpmsg device endpoint already destroyed will avoid sending second glink close command. Change-Id: I0135e2626f4ede7a380308944f7c273d18e223bf Signed-off-by: Konstantin Dorfman --- drivers/rpmsg/qcom_glink_native.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 3847eb11407f..65d005c2cc95 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2017, Linaro Ltd - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1388,6 +1388,10 @@ static void qcom_glink_destroy_ept(struct rpmsg_endpoint *ept) unsigned long flags; spin_lock_irqsave(&channel->recv_lock, flags); + if (!channel->ept.cb) { + spin_unlock_irqrestore(&channel->recv_lock, flags); + return; + } channel->ept.cb = NULL; spin_unlock_irqrestore(&channel->recv_lock, flags); -- GitLab From 0ee973342d243edaaf70a8f04f6e1c3a2776f668 Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Thu, 15 Nov 2018 09:01:33 +0530 Subject: [PATCH 0824/1286] clk: qcom: Add debug clock controller for TRINKET Add debug mux structure with inputs for measuring the clocks on TRINKET. Change-Id: I2462cee8b690a218758f3b7fb0e4b4e70f460c8d Signed-off-by: Diptanshu Jamgade Signed-off-by: Odelu Kukatla --- .../bindings/clock/qcom,debugcc.txt | 3 +- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/debugcc-trinket.c | 719 ++++++++++++++++++ 4 files changed, 730 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/qcom/debugcc-trinket.c diff --git a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt index 8e88ee435a10..500c7ef288e4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt @@ -6,7 +6,8 @@ Required properties : "qcom,debugcc-qcs405", "qcom,debugcc-sm6150", "qcom,debugcc-sdmmagpie" - "qcom,debugcc-sdxprairie". + "qcom,debugcc-sdxprairie", + "qcom,debugcc-trinket". - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. - qcom,camcc: phandle to the Camera CC device node. diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 043ce96117f4..08f8e2e0b92c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -538,3 +538,11 @@ config SM_DISPCC_TRINKET TRINKET devices. Say Y if you want to support display devices and functionality such as splash screen. + +config SM_DEBUGCC_TRINKET + tristate "TRINKET Debug Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the debug clock controller on Qualcomm Technologies, Inc + TRINKET devices. + Say Y if you want to support the clock measurement functionality. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 19b20faf7f36..f06caae54a54 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_SM_DEBUGCC_TRINKET) += debugcc-trinket.o obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o diff --git a/drivers/clk/qcom/debugcc-trinket.c b/drivers/clk/qcom/debugcc-trinket.c new file mode 100644 index 000000000000..780fbb380934 --- /dev/null +++ b/drivers/clk/qcom/debugcc-trinket.c @@ -0,0 +1,719 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-debug.h" + +static struct measure_clk_data debug_mux_priv = { + .ctl_reg = 0x62038, + .status_reg = 0x6203C, + .xo_div4_cbcr = 0x28008, +}; + +static const char *const debug_mux_parent_names[] = { + "snoc_clk", + "bimc_clk", + "pnoc_clk", + "disp_cc_mdss_ahb_clk", + "disp_cc_mdss_byte0_clk", + "disp_cc_mdss_byte0_intf_clk", + "disp_cc_mdss_dp_aux_clk", + "disp_cc_mdss_dp_crypto_clk", + "disp_cc_mdss_dp_link_clk", + "disp_cc_mdss_dp_link_intf_clk", + "disp_cc_mdss_dp_pixel_clk", + "disp_cc_mdss_esc0_clk", + "disp_cc_mdss_mdp_clk", + "disp_cc_mdss_mdp_lut_clk", + "disp_cc_mdss_non_gdsc_ahb_clk", + "disp_cc_mdss_pclk0_clk", + "disp_cc_mdss_rot_clk", + "disp_cc_mdss_vsync_clk", + "disp_cc_sleep_clk", + "disp_cc_xo_clk", + "gcc_ahb2phy_csi_clk", + "gcc_ahb2phy_usb_clk", + "gcc_apc_vs_clk", + "gcc_boot_rom_ahb_clk", + "gcc_camera_ahb_clk", + "gcc_camera_xo_clk", + "gcc_camss_cci_ahb_clk", + "gcc_camss_cci_clk", + "gcc_camss_cphy_csid0_clk", + "gcc_camss_cphy_csid1_clk", + "gcc_camss_cphy_csid2_clk", + "gcc_camss_cphy_csid3_clk", + "gcc_camss_cpp_ahb_clk", + "gcc_camss_cpp_axi_clk", + "gcc_camss_cpp_clk", + "gcc_camss_cpp_tsctr_clk", + "gcc_camss_cpp_vbif_ahb_clk", + "gcc_camss_csi0_ahb_clk", + "gcc_camss_csi0_clk", + "gcc_camss_csi0phytimer_clk", + "gcc_camss_csi0pix_clk", + "gcc_camss_csi0rdi_clk", + "gcc_camss_csi1_ahb_clk", + "gcc_camss_csi1_clk", + "gcc_camss_csi1phytimer_clk", + "gcc_camss_csi1pix_clk", + "gcc_camss_csi1rdi_clk", + "gcc_camss_csi2_ahb_clk", + "gcc_camss_csi2_clk", + "gcc_camss_csi2phytimer_clk", + "gcc_camss_csi2pix_clk", + "gcc_camss_csi2rdi_clk", + "gcc_camss_csi3_ahb_clk", + "gcc_camss_csi3_clk", + "gcc_camss_csi3pix_clk", + "gcc_camss_csi3rdi_clk", + "gcc_camss_csi_vfe0_clk", + "gcc_camss_csi_vfe1_clk", + "gcc_camss_csiphy0_clk", + "gcc_camss_csiphy1_clk", + "gcc_camss_csiphy2_clk", + "gcc_camss_csiphy3_clk", + "gcc_camss_gp0_clk", + "gcc_camss_gp1_clk", + "gcc_camss_ispif_ahb_clk", + "gcc_camss_jpeg_ahb_clk", + "gcc_camss_jpeg_axi_clk", + "gcc_camss_jpeg_clk", + "gcc_camss_jpeg_tsctr_clk", + "gcc_camss_mclk0_clk", + "gcc_camss_mclk1_clk", + "gcc_camss_mclk2_clk", + "gcc_camss_mclk3_clk", + "gcc_camss_micro_ahb_clk", + "gcc_camss_throttle_nrt_axi_clk", + "gcc_camss_throttle_rt_axi_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_vfe0_ahb_clk", + "gcc_camss_vfe0_clk", + "gcc_camss_vfe0_stream_clk", + "gcc_camss_vfe1_ahb_clk", + "gcc_camss_vfe1_clk", + "gcc_camss_vfe1_stream_clk", + "gcc_camss_vfe_tsctr_clk", + "gcc_camss_vfe_vbif_ahb_clk", + "gcc_camss_vfe_vbif_axi_clk", + "gcc_ce1_ahb_clk", + "gcc_ce1_axi_clk", + "gcc_ce1_clk", + "gcc_cfg_noc_usb3_prim_axi_clk", + "gcc_cpuss_ahb_clk", + "gcc_cpuss_gnoc_clk", + "gcc_cpuss_throttle_core_clk", + "gcc_cpuss_throttle_xo_clk", + "gcc_disp_ahb_clk", + "gcc_disp_gpll0_div_clk_src", + "gcc_disp_hf_axi_clk", + "gcc_disp_throttle_core_clk", + "gcc_disp_xo_clk", + "gcc_gp1_clk", + "gcc_gp2_clk", + "gcc_gp3_clk", + "gcc_gpu_cfg_ahb_clk", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gcc_gpu_throttle_core_clk", + "gcc_gpu_throttle_xo_clk", + "gcc_mss_vs_clk", + "gcc_pdm2_clk", + "gcc_pdm_ahb_clk", + "gcc_pdm_xo4_clk", + "gcc_prng_ahb_clk", + "gcc_qmip_camera_nrt_ahb_clk", + "gcc_qmip_camera_rt_ahb_clk", + "gcc_qmip_cpuss_cfg_ahb_clk", + "gcc_qmip_disp_ahb_clk", + "gcc_qmip_gpu_cfg_ahb_clk", + "gcc_qmip_video_vcodec_ahb_clk", + "gcc_qupv3_wrap0_core_2x_clk", + "gcc_qupv3_wrap0_core_clk", + "gcc_qupv3_wrap0_s0_clk", + "gcc_qupv3_wrap0_s1_clk", + "gcc_qupv3_wrap0_s2_clk", + "gcc_qupv3_wrap0_s3_clk", + "gcc_qupv3_wrap0_s4_clk", + "gcc_qupv3_wrap0_s5_clk", + "gcc_qupv3_wrap1_core_2x_clk", + "gcc_qupv3_wrap1_core_clk", + "gcc_qupv3_wrap1_s0_clk", + "gcc_qupv3_wrap1_s1_clk", + "gcc_qupv3_wrap1_s2_clk", + "gcc_qupv3_wrap1_s3_clk", + "gcc_qupv3_wrap1_s4_clk", + "gcc_qupv3_wrap1_s5_clk", + "gcc_qupv3_wrap_0_m_ahb_clk", + "gcc_qupv3_wrap_0_s_ahb_clk", + "gcc_qupv3_wrap_1_m_ahb_clk", + "gcc_qupv3_wrap_1_s_ahb_clk", + "gcc_sdcc1_ahb_clk", + "gcc_sdcc1_apps_clk", + "gcc_sdcc1_ice_core_clk", + "gcc_sdcc2_ahb_clk", + "gcc_sdcc2_apps_clk", + "gcc_sys_noc_cpuss_ahb_clk", + "gcc_sys_noc_ufs_phy_axi_clk", + "gcc_sys_noc_usb3_prim_axi_clk", + "gcc_ufs_phy_ahb_clk", + "gcc_ufs_phy_axi_clk", + "gcc_ufs_phy_ice_core_clk", + "gcc_ufs_phy_phy_aux_clk", + "gcc_ufs_phy_rx_symbol_0_clk", + "gcc_ufs_phy_tx_symbol_0_clk", + "gcc_ufs_phy_unipro_core_clk", + "gcc_usb30_prim_master_clk", + "gcc_usb30_prim_mock_utmi_clk", + "gcc_usb30_prim_sleep_clk", + "gcc_usb3_prim_phy_com_aux_clk", + "gcc_usb3_prim_phy_pipe_clk", + "gcc_vdda_vs_clk", + "gcc_vddcx_vs_clk", + "gcc_vddmx_vs_clk", + "gcc_video_ahb_clk", + "gcc_video_axi0_clk", + "gcc_video_throttle_core_clk", + "gcc_video_xo_clk", + "gcc_vs_ctrl_ahb_clk", + "gcc_vs_ctrl_clk", + "gcc_wcss_vs_clk", + "gpu_cc_ahb_clk", + "gpu_cc_crc_ahb_clk", + "gpu_cc_cx_apb_clk", + "gpu_cc_cx_gfx3d_clk", + "gpu_cc_cx_gfx3d_slv_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_cx_snoc_dvm_clk", + "gpu_cc_cxo_aon_clk", + "gpu_cc_cxo_clk", + "gpu_cc_gx_cxo_clk", + "gpu_cc_gx_gfx3d_clk", + "gpu_cc_sleep_clk", + "video_cc_apb_clk", + "video_cc_at_clk", + "video_cc_sleep_clk", + "video_cc_vcodec0_axi_clk", + "video_cc_vcodec0_core_clk", + "video_cc_venus_ahb_clk", + "video_cc_venus_ctl_axi_clk", + "video_cc_venus_ctl_core_clk", + "video_cc_xo_clk", +}; + +static struct clk_debug_mux gcc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x62000, + .post_div_offset = 0x30000, + .cbcr_offset = 0x30004, + .src_sel_mask = 0x3FF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + MUX_SRC_LIST( + { "snoc_clk", 0x7, 1, GCC, + 0x7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "bimc_clk", 0x97, 1, GCC, + 0x97, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "pnoc_clk", 0x11, 1, GCC, + 0x11, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "disp_cc_mdss_ahb_clk", 0x41, 1, DISP_CC, + 0x1A, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_byte0_clk", 0x41, 1, DISP_CC, + 0x12, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_byte0_intf_clk", 0x41, 1, DISP_CC, + 0x13, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_dp_aux_clk", 0x41, 1, DISP_CC, + 0x19, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_dp_crypto_clk", 0x41, 1, DISP_CC, + 0x17, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_dp_link_clk", 0x41, 1, DISP_CC, + 0x15, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_dp_link_intf_clk", 0x41, 1, DISP_CC, + 0x16, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_dp_pixel_clk", 0x41, 1, DISP_CC, + 0x18, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_esc0_clk", 0x41, 1, DISP_CC, + 0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_mdp_clk", 0x41, 1, DISP_CC, + 0xE, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_mdp_lut_clk", 0x41, 1, DISP_CC, + 0x10, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_non_gdsc_ahb_clk", 0x41, 1, DISP_CC, + 0x1B, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_pclk0_clk", 0x41, 1, DISP_CC, + 0xD, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_rot_clk", 0x41, 1, DISP_CC, + 0xF, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_mdss_vsync_clk", 0x41, 1, DISP_CC, + 0x11, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_sleep_clk", 0x41, 1, DISP_CC, + 0x24, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "disp_cc_xo_clk", 0x41, 1, DISP_CC, + 0x23, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, + { "gcc_ahb2phy_csi_clk", 0x5F, 1, GCC, + 0x5F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ahb2phy_usb_clk", 0x60, 1, GCC, + 0x60, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_apc_vs_clk", 0xBF, 1, GCC, + 0xBF, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_boot_rom_ahb_clk", 0x72, 1, GCC, + 0x72, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camera_ahb_clk", 0x36, 1, GCC, + 0x36, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camera_xo_clk", 0x3E, 1, GCC, + 0x3E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cci_ahb_clk", 0x11F, 1, GCC, + 0x11F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cci_clk", 0x11E, 1, GCC, + 0x11E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cphy_csid0_clk", 0x13A, 1, GCC, + 0x13A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cphy_csid1_clk", 0x140, 1, GCC, + 0x140, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cphy_csid2_clk", 0x145, 1, GCC, + 0x145, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cphy_csid3_clk", 0x14B, 1, GCC, + 0x14B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cpp_ahb_clk", 0x154, 1, GCC, + 0x154, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cpp_axi_clk", 0x156, 1, GCC, + 0x156, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cpp_clk", 0x153, 1, GCC, + 0x153, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cpp_tsctr_clk", 0x158, 1, GCC, + 0x158, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_cpp_vbif_ahb_clk", 0x155, 1, GCC, + 0x155, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi0_ahb_clk", 0x13B, 1, GCC, + 0x13B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi0_clk", 0x139, 1, GCC, + 0x139, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi0phytimer_clk", 0x120, 1, GCC, + 0x120, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi0pix_clk", 0x13D, 1, GCC, + 0x13D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi0rdi_clk", 0x13C, 1, GCC, + 0x13C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi1_ahb_clk", 0x141, 1, GCC, + 0x141, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi1_clk", 0x13F, 1, GCC, + 0x13F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi1phytimer_clk", 0x121, 1, GCC, + 0x121, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi1pix_clk", 0x143, 1, GCC, + 0x143, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi1rdi_clk", 0x142, 1, GCC, + 0x142, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi2_ahb_clk", 0x146, 1, GCC, + 0x146, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi2_clk", 0x144, 1, GCC, + 0x144, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi2phytimer_clk", 0x122, 1, GCC, + 0x122, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi2pix_clk", 0x148, 1, GCC, + 0x148, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi2rdi_clk", 0x147, 1, GCC, + 0x147, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi3_ahb_clk", 0x14C, 1, GCC, + 0x14C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi3_clk", 0x14A, 1, GCC, + 0x14A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi3pix_clk", 0x14E, 1, GCC, + 0x14E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi3rdi_clk", 0x14D, 1, GCC, + 0x14D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi_vfe0_clk", 0x12E, 1, GCC, + 0x12E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csi_vfe1_clk", 0x12F, 1, GCC, + 0x12F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csiphy0_clk", 0x135, 1, GCC, + 0x135, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csiphy1_clk", 0x136, 1, GCC, + 0x136, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csiphy2_clk", 0x137, 1, GCC, + 0x137, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_csiphy3_clk", 0x138, 1, GCC, + 0x138, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_gp0_clk", 0x118, 1, GCC, + 0x118, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_gp1_clk", 0x119, 1, GCC, + 0x119, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_ispif_ahb_clk", 0x134, 1, GCC, + 0x134, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_jpeg_ahb_clk", 0x124, 1, GCC, + 0x124, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_jpeg_axi_clk", 0x125, 1, GCC, + 0x125, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_jpeg_clk", 0x123, 1, GCC, + 0x123, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_jpeg_tsctr_clk", 0x127, 1, GCC, + 0x127, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_mclk0_clk", 0x11A, 1, GCC, + 0x11A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_mclk1_clk", 0x11B, 1, GCC, + 0x11B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_mclk2_clk", 0x11C, 1, GCC, + 0x11C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_mclk3_clk", 0x11D, 1, GCC, + 0x11D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_micro_ahb_clk", 0x152, 1, GCC, + 0x152, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_throttle_nrt_axi_clk", 0x150, 1, GCC, + 0x150, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_throttle_rt_axi_clk", 0x151, 1, GCC, + 0x151, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_top_ahb_clk", 0x14F, 1, GCC, + 0x14F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe0_ahb_clk", 0x12A, 1, GCC, + 0x12A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe0_clk", 0x128, 1, GCC, + 0x128, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe0_stream_clk", 0x129, 1, GCC, + 0x129, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe1_ahb_clk", 0x12D, 1, GCC, + 0x12D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe1_clk", 0x12B, 1, GCC, + 0x12B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe1_stream_clk", 0x12C, 1, GCC, + 0x12C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe_tsctr_clk", 0x133, 1, GCC, + 0x133, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe_vbif_ahb_clk", 0x130, 1, GCC, + 0x130, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_camss_vfe_vbif_axi_clk", 0x131, 1, GCC, + 0x131, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ce1_ahb_clk", 0x82, 1, GCC, + 0x82, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ce1_axi_clk", 0x81, 1, GCC, + 0x81, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ce1_clk", 0x80, 1, GCC, + 0x80, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", 0x1D, 1, GCC, + 0x1D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_cpuss_ahb_clk", 0xA5, 1, GCC, + 0xA5, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_cpuss_gnoc_clk", 0xA6, 1, GCC, + 0xA6, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_cpuss_throttle_core_clk", 0xAE, 1, GCC, + 0xAE, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_cpuss_throttle_xo_clk", 0xAD, 1, GCC, + 0xAD, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_disp_ahb_clk", 0x37, 1, GCC, + 0x37, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_disp_gpll0_div_clk_src", 0x46, 1, GCC, + 0x46, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_disp_hf_axi_clk", 0x3C, 1, GCC, + 0x3C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_disp_throttle_core_clk", 0x48, 1, GCC, + 0x48, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_disp_xo_clk", 0x3F, 1, GCC, + 0x3F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gp1_clk", 0xB6, 1, GCC, + 0xB6, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gp2_clk", 0xB7, 1, GCC, + 0xB7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gp3_clk", 0xB8, 1, GCC, + 0xB8, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_cfg_ahb_clk", 0xDB, 1, GCC, + 0xDB, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_gpll0_clk_src", 0xE1, 1, GCC, + 0xE1, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_gpll0_div_clk_src", 0xE2, 1, GCC, + 0xE2, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_memnoc_gfx_clk", 0xDE, 1, GCC, + 0xDE, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_snoc_dvm_gfx_clk", 0xE0, 1, GCC, + 0xE0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_throttle_core_clk", 0xE5, 1, GCC, + 0xE5, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_gpu_throttle_xo_clk", 0xE4, 1, GCC, + 0xE4, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_mss_vs_clk", 0xBE, 1, GCC, + 0xBE, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_pdm2_clk", 0x6F, 1, GCC, + 0x6F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_pdm_ahb_clk", 0x6D, 1, GCC, + 0x6D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_pdm_xo4_clk", 0x6E, 1, GCC, + 0x6E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_prng_ahb_clk", 0x70, 1, GCC, + 0x70, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_camera_nrt_ahb_clk", 0x39, 1, GCC, + 0x39, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_camera_rt_ahb_clk", 0x47, 1, GCC, + 0x47, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_cpuss_cfg_ahb_clk", 0xAC, 1, GCC, + 0xAC, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_disp_ahb_clk", 0x3A, 1, GCC, + 0x3A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_gpu_cfg_ahb_clk", 0xE3, 1, GCC, + 0xE3, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qmip_video_vcodec_ahb_clk", 0x38, 1, GCC, + 0x38, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_core_2x_clk", 0x66, 1, GCC, + 0x66, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_core_clk", 0x65, 1, GCC, + 0x65, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s0_clk", 0x67, 1, GCC, + 0x67, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s1_clk", 0x68, 1, GCC, + 0x68, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s2_clk", 0x69, 1, GCC, + 0x69, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s3_clk", 0x6A, 1, GCC, + 0x6A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s4_clk", 0x6B, 1, GCC, + 0x6B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap0_s5_clk", 0x6C, 1, GCC, + 0x6C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_core_2x_clk", 0xED, 1, GCC, + 0xED, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_core_clk", 0xEC, 1, GCC, + 0xEC, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s0_clk", 0xEE, 1, GCC, + 0xEE, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s1_clk", 0xEF, 1, GCC, + 0xEF, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s2_clk", 0xF0, 1, GCC, + 0xF0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s3_clk", 0xF1, 1, GCC, + 0xF1, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s4_clk", 0xF2, 1, GCC, + 0xF2, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap1_s5_clk", 0xF3, 1, GCC, + 0xF3, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", 0x63, 1, GCC, + 0x63, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", 0x64, 1, GCC, + 0x64, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", 0xEA, 1, GCC, + 0xEA, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", 0xEB, 1, GCC, + 0xEB, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sdcc1_ahb_clk", 0xE8, 1, GCC, + 0xE8, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sdcc1_apps_clk", 0xE7, 1, GCC, + 0xE7, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sdcc1_ice_core_clk", 0xE9, 1, GCC, + 0xE9, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sdcc2_ahb_clk", 0x62, 1, GCC, + 0x62, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sdcc2_apps_clk", 0x61, 1, GCC, + 0x61, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sys_noc_cpuss_ahb_clk", 0x9, 1, GCC, + 0x9, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sys_noc_ufs_phy_axi_clk", 0x19, 1, GCC, + 0x19, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_sys_noc_usb3_prim_axi_clk", 0x18, 1, GCC, + 0x18, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_ahb_clk", 0x10F, 1, GCC, + 0x10F, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_axi_clk", 0x10E, 1, GCC, + 0x10E, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_ice_core_clk", 0x115, 1, GCC, + 0x115, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_phy_aux_clk", 0x116, 1, GCC, + 0x116, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_rx_symbol_0_clk", 0x111, 1, GCC, + 0x111, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_tx_symbol_0_clk", 0x110, 1, GCC, + 0x110, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_ufs_phy_unipro_core_clk", 0x114, 1, GCC, + 0x114, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_usb30_prim_master_clk", 0x58, 1, GCC, + 0x58, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_usb30_prim_mock_utmi_clk", 0x5A, 1, GCC, + 0x5A, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_usb30_prim_sleep_clk", 0x59, 1, GCC, + 0x59, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_usb3_prim_phy_com_aux_clk", 0x5B, 1, GCC, + 0x5B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_usb3_prim_phy_pipe_clk", 0x5C, 1, GCC, + 0x5C, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_vdda_vs_clk", 0xBB, 1, GCC, + 0xBB, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_vddcx_vs_clk", 0xB9, 1, GCC, + 0xB9, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_vddmx_vs_clk", 0xBA, 1, GCC, + 0xBA, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_video_ahb_clk", 0x35, 1, GCC, + 0x35, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_video_axi0_clk", 0x3B, 1, GCC, + 0x3B, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_video_throttle_core_clk", 0x49, 1, GCC, + 0x49, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_video_xo_clk", 0x3D, 1, GCC, + 0x3D, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_vs_ctrl_ahb_clk", 0xBD, 1, GCC, + 0xBD, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_vs_ctrl_clk", 0xBC, 1, GCC, + 0xBC, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gcc_wcss_vs_clk", 0xC0, 1, GCC, + 0xC0, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, + { "gpu_cc_ahb_clk", 0xDD, 1, GPU_CC, + 0x10, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_crc_ahb_clk", 0xDD, 1, GPU_CC, + 0x11, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cx_apb_clk", 0xDD, 1, GPU_CC, + 0x14, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cx_gfx3d_clk", 0xDD, 1, GPU_CC, + 0x1A, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cx_gfx3d_slv_clk", 0xDD, 1, GPU_CC, + 0x1B, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cx_gmu_clk", 0xDD, 1, GPU_CC, + 0x18, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cx_snoc_dvm_clk", 0xDD, 1, GPU_CC, + 0x15, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cxo_aon_clk", 0xDD, 1, GPU_CC, + 0xA, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_cxo_clk", 0xDD, 1, GPU_CC, + 0x19, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_gx_cxo_clk", 0xDD, 1, GPU_CC, + 0xE, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_gx_gfx3d_clk", 0xDD, 1, GPU_CC, + 0xB, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "gpu_cc_sleep_clk", 0xDD, 1, GPU_CC, + 0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "video_cc_apb_clk", 0x42, 1, VIDEO_CC, + 0x8, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_at_clk", 0x42, 1, VIDEO_CC, + 0xB, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_sleep_clk", 0x42, 1, VIDEO_CC, + 0xD, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_vcodec0_axi_clk", 0x42, 1, VIDEO_CC, + 0x6, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_vcodec0_core_clk", 0x42, 1, VIDEO_CC, + 0x3, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_venus_ahb_clk", 0x42, 1, VIDEO_CC, + 0x9, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_venus_ctl_axi_clk", 0x42, 1, VIDEO_CC, + 0x5, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_venus_ctl_core_clk", 0x42, 1, VIDEO_CC, + 0x1, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + { "video_cc_xo_clk", 0x42, 1, VIDEO_CC, + 0xC, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, + ), + .hw.init = &(struct clk_init_data){ + .name = "gcc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = debug_mux_parent_names, + .num_parents = ARRAY_SIZE(debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const struct of_device_id clk_debug_match_table[] = { + { .compatible = "qcom,debugcc-trinket" }, + { } +}; + +static int map_debug_bases(struct platform_device *pdev, char *base, int cc) +{ + if (!of_get_property(pdev->dev.of_node, base, NULL)) { + pr_err("error in of_get prop\n"); + return -ENODEV; + } + + gcc_debug_mux.regmap[cc] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + base); + if (IS_ERR(gcc_debug_mux.regmap[cc])) { + pr_err("Failed to map %s (ret=%ld)\n", base, + PTR_ERR(gcc_debug_mux.regmap[cc])); + return PTR_ERR(gcc_debug_mux.regmap[cc]); + } + + return 0; +} + +static int clk_debug_trinket_probe(struct platform_device *pdev) +{ + struct clk *clk; + int ret; + + clk = devm_clk_get(&pdev->dev, "cxo"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock\n"); + return PTR_ERR(clk); + } + + debug_mux_priv.cxo = clk; + + gcc_debug_mux.regmap = devm_kcalloc(&pdev->dev, MAX_NUM_CC, + sizeof(*gcc_debug_mux.regmap), GFP_KERNEL); + if (!gcc_debug_mux.regmap) + return -ENOMEM; + + ret = map_debug_bases(pdev, "qcom,gcc", GCC); + if (ret) + return ret; + + ret = map_debug_bases(pdev, "qcom,videocc", VIDEO_CC); + if (ret) + return ret; + + ret = map_debug_bases(pdev, "qcom,gpucc", GPU_CC); + if (ret) + return ret; + + ret = map_debug_bases(pdev, "qcom,dispcc", DISP_CC); + if (ret) + return ret; + + clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); + return PTR_ERR(clk); + } + + ret = clk_debug_measure_register(&gcc_debug_mux.hw); + if (ret) + dev_err(&pdev->dev, "Could not register Measure clock\n"); + + return ret; +} + +static struct platform_driver clk_debug_driver = { + .probe = clk_debug_trinket_probe, + .driver = { + .name = "debugcc-trinket", + .of_match_table = clk_debug_match_table, + }, +}; + +int __init clk_debug_trinket_init(void) +{ + return platform_driver_register(&clk_debug_driver); +} +fs_initcall(clk_debug_trinket_init); + +MODULE_DESCRIPTION("QTI DEBUG CC TRINKET Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:debugcc-trinket"); -- GitLab From 8e322965e0f58148b1efa99e0b2266947950231d Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 16 Dec 2018 16:58:32 +0530 Subject: [PATCH 0825/1286] ARM: dts: msm: Update the clock controller nodes for TRINKET Update the RPMCC, GCC, GPUCC, VIDEOCC, DIPSCC and DEBUGCC clock controller device nodes to register the actual clock controller drivers. Change-Id: I958f82fb789ff50cfd6f33e558dec948ac5d2e1b Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/trinket.dtsi | 62 +++++++++++++++++++-------- 1 file changed, 44 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 46d0db74b139..fccd7f7dabc6 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -724,38 +724,64 @@ }; }; + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <1>; + }; + }; + clock_rpmcc: qcom,rpmcc { - compatible = "qcom,dummycc"; - clock-output-names = "rpmcc_clocks"; + compatible = "qcom,rpmcc-trinket"; #clock-cells = <1>; }; - clock_gcc: qcom,gcc { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + clock_gcc: qcom,gcc@1400000 { + compatible = "qcom,gcc-trinket", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; #clock-cells = <1>; #reset-cells = <1>; }; - clock_videocc: qcom,videocc { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + clock_videocc: qcom,videocc@5b00000 { + compatible = "qcom,videocc-trinket", "syscon"; + reg = <0x5b00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; - #reset-cells = <1>; }; - clock_dispcc: qcom,dispcc { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + clock_dispcc: qcom,dispcc@5f00000 { + compatible = "qcom,dispcc-trinket", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; - #reset-cells = <1>; }; - clock_gpucc: qcom,gpupcc { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + clock_gpucc: qcom,gpupcc@5990000 { + compatible = "qcom,gpucc-trinket", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-trinket"; + qcom,gcc = <&clock_gcc>; + qcom,videocc = <&clock_videocc>; + qcom,dispcc = <&clock_dispcc>; + qcom,gpucc = <&clock_gpucc>; + clock-names = "cxo"; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; #clock-cells = <1>; - #reset-cells = <1>; }; clock_cpucc: qcom,cpucc { -- GitLab From 210918ec4d2a9339bd334bc65c555c120f640995 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 10 Jan 2019 21:54:52 +0530 Subject: [PATCH 0826/1286] defconfig: Enable clock controller drivers for TRINKET Enable RPMCC, GCC, GPUCC, VIDEOCC, DISPCC and DEBUGCC clock controller drivers support. Change-Id: If777c57b7dcbcae147dc40f1bce7b8568f11834b Signed-off-by: Odelu Kukatla --- arch/arm64/configs/vendor/trinket-perf_defconfig | 7 +++++++ arch/arm64/configs/vendor/trinket_defconfig | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..28078f2b932f 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -474,8 +474,14 @@ CONFIG_RMNET_IPA3=y CONFIG_RNDIS_IPA=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m +CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_CLOCK_CPU_OSM=y +CONFIG_SM_GCC_TRINKET=y +CONFIG_SM_GPUCC_TRINKET=y +CONFIG_SM_VIDEOCC_TRINKET=y +CONFIG_SM_DISPCC_TRINKET=y +CONFIG_SM_DEBUGCC_TRINKET=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_MAILBOX=y @@ -496,6 +502,7 @@ CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_MEMORY_DUMP_V2=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..115a75f86318 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -496,8 +496,14 @@ CONFIG_RMNET_IPA3=y CONFIG_RNDIS_IPA=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m +CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_CLOCK_CPU_OSM=y +CONFIG_SM_GCC_TRINKET=y +CONFIG_SM_GPUCC_TRINKET=y +CONFIG_SM_VIDEOCC_TRINKET=y +CONFIG_SM_DISPCC_TRINKET=y +CONFIG_SM_DEBUGCC_TRINKET=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_MAILBOX=y @@ -518,6 +524,7 @@ CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y CONFIG_MSM_SPM=y CONFIG_MSM_L2_SPM=y CONFIG_QCOM_MEMORY_DUMP_V2=y -- GitLab From 9f8d514de7b107da41494666bf0d7bc56a7bcc11 Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Wed, 9 Jan 2019 14:53:54 -0800 Subject: [PATCH 0827/1286] msm: ipa: Read q6 smem region size from dts IPA Q6 smem region size should be read from dts instead of hardcoded value. Change-Id: I6b45e6b9cd17802ac14a8d2f7ac717f60c010945 Signed-off-by: Ghanim Fodi --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index d272026b4efd..055027ea36db 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -6515,6 +6515,7 @@ static int ipa_smmu_ap_cb_probe(struct device *dev) const u32 *add_map; void *smem_addr; size_t smem_size; + u32 ipa_smem_size = 0; int ret; int i; unsigned long iova_p; @@ -6644,10 +6645,19 @@ static int ipa_smmu_ap_cb_probe(struct device *dev) } } + ret = of_property_read_u32(dev->of_node, "qcom,ipa-q6-smem-size", + &ipa_smem_size); + if (ret) { + IPADBG("ipa q6 smem size (default) = %zu\n", IPA_SMEM_SIZE); + ipa_smem_size = IPA_SMEM_SIZE; + } else { + IPADBG("ipa q6 smem size = %zu\n", ipa_smem_size); + } + /* map SMEM memory for IPA table accesses */ ret = qcom_smem_alloc(SMEM_MODEM, SMEM_IPA_FILTER_TABLE, - IPA_SMEM_SIZE); + ipa_smem_size); if (ret < 0 && ret != -EEXIST) { IPAERR("unable to allocate smem MODEM entry\n"); @@ -6662,11 +6672,14 @@ static int ipa_smmu_ap_cb_probe(struct device *dev) cb->valid = false; return -EFAULT; } + if (smem_size != ipa_smem_size) + IPAERR("unexpected read q6 smem size %zu %zu\n", + smem_size, ipa_smem_size); iova = qcom_smem_virt_to_phys(smem_addr); pa = iova; - IPA_SMMU_ROUND_TO_PAGE(iova, pa, IPA_SMEM_SIZE, + IPA_SMMU_ROUND_TO_PAGE(iova, pa, ipa_smem_size, iova_p, pa_p, size_p); IPADBG("mapping 0x%lx to 0x%pa size %d\n", iova_p, &pa_p, size_p); -- GitLab From 7c6988af832f34658e8cc66c9d5d7edc19a1b7f5 Mon Sep 17 00:00:00 2001 From: David Collins Date: Thu, 10 Jan 2019 11:32:16 -0800 Subject: [PATCH 0828/1286] ARM: dts: msm: add pmxprairie VREF RGMII regulator device for sdxprairie Add an rpmh-regulator device for the VREF_RGMII peripheral found in pmxprairie PMIC chips. This is needed for EMAC use cases. Change-Id: I28cd8d82b4af654e2742df153725eec44964244c Signed-off-by: David Collins --- arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi index 3328a31e8ce0..c6077a23628a 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -441,4 +441,14 @@ qcom,init-mode = ; }; }; + + rpmh-regulator-vrefe2 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "vrefe2"; + pmxprairie_vref_rgmii: regulator-pmxprairie-rgmii { + regulator-name = "pmxprairie_vref_rgmii"; + qcom,set = ; + }; + }; }; -- GitLab From 5933ef60d5d8881fc2c5fa2b5435cbf5a88dde82 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 9 Jan 2019 16:03:58 -0800 Subject: [PATCH 0829/1286] mhi: core: keep MHI in M0 while entering suspend During MHI suspend, host must keep MHI wake asserted to prevent device from entering any other low power states. CRs-Fixed: 2361072 Change-Id: Ib68ec62294eab4727c6bb8e356b6aa59b9ca99cf Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_pm.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index 61dd644b8b5d..cedb4b10d0b9 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -931,24 +931,23 @@ int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), msecs_to_jiffies(mhi_cntrl->timeout_ms)); - read_lock_bh(&mhi_cntrl->pm_lock); - mhi_cntrl->wake_put(mhi_cntrl, false); - read_unlock_bh(&mhi_cntrl->pm_lock); - if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { MHI_ERR( "Did not enter M0||M1 state, cur_state:%s pm_state:%s\n", TO_MHI_STATE_STR(mhi_cntrl->dev_state), to_mhi_pm_state_str(mhi_cntrl->pm_state)); - return -EIO; + ret = -EIO; + goto error_m0_entry; } write_lock_irq(&mhi_cntrl->pm_lock); - if (atomic_read(&mhi_cntrl->dev_wake)) { + /* we're asserting wake so count would be @ least 1 */ + if (atomic_read(&mhi_cntrl->dev_wake) > 1) { MHI_VERB("Busy, aborting M3\n"); write_unlock_irq(&mhi_cntrl->pm_lock); - return -EBUSY; + ret = -EBUSY; + goto error_m0_entry; } /* anytime after this, we will resume thru runtime pm framework */ @@ -959,11 +958,14 @@ int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) MHI_ERR("Error setting to pm_state:%s from pm_state:%s\n", to_mhi_pm_state_str(MHI_PM_M3_ENTER), to_mhi_pm_state_str(mhi_cntrl->pm_state)); - return -EIO; + + ret = -EIO; + goto error_m0_entry; } /* set dev to M3 and wait for completion */ mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3); + mhi_cntrl->wake_put(mhi_cntrl, false); write_unlock_irq(&mhi_cntrl->pm_lock); MHI_LOG("Wait for M3 completion\n"); @@ -988,6 +990,13 @@ int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) } return 0; + +error_m0_entry: + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return ret; } EXPORT_SYMBOL(mhi_pm_suspend); -- GitLab From c14384a3244364b47c506f0a71fa81693af2fefc Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 3 Jan 2019 11:58:00 -0800 Subject: [PATCH 0830/1286] dt-bindings: pcie: add entry for PCIe PHY status bit The bit for PCIe PHY status varies for each PCIe core. Therefore, add a DT entry to specify which bit to should be checked for PCIe PHY status. Change-Id: If40322d2c131681608a627c51b5130e04f5a0320 Signed-off-by: Tony Truong --- Documentation/devicetree/bindings/pci/msm_pcie.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index da1519fa3b62..9464e99359b0 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -30,6 +30,7 @@ Required properties: - perst-gpio: PERST GPIO specified by PCIe spec. - wake-gpio: WAKE GPIO specified by PCIe spec. - phy-status-offset: Offset from PCIe PHY base to check if PCIe PHY is up. + - phy-status-bit: BIT to check PCIe PHY status. - pcie_rc: PCI node is a sub-node of PCIe controller node. node. This node holds root complex specific configurations and properties. - -supply: phandle to the regulator device tree node. @@ -281,6 +282,7 @@ Example: qcom,wr-halt-size = <0xa>; /* 1KB */ qcom,slv-addr-space-size = <0x1000000>; /* 16MB */ qcom,phy-status-offset = <0x800>; + qcom,phy-status-status = <6>; qcom,phy-power-down-offset = <0x840>; qcom,cpl-timeout = <0x2>; -- GitLab From f19445a2305db9c58cfc4ab400d8a426054c32de Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 28 Nov 2018 15:03:30 -0800 Subject: [PATCH 0831/1286] msm: pcie: remove legacy arm32 IRQ support Kernel 4.14 no longer requires arm32 specific support for PCIe INTx interrupts. Therefore remove all arm32 IRQ support. Change-Id: I92df6084184d2d4310a6903dda12e3b27e840a79 Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index bf29447498d6..6c8d06c0cf0e 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -888,17 +888,6 @@ static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev); static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable); -#ifdef CONFIG_ARM -static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev) -{ - pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); -} -#else -static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev) -{ -} -#endif - static inline void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value) { writel_relaxed(value, base + offset); @@ -4383,7 +4372,6 @@ int msm_pcie_enumerate(u32 rc_idx) bus = bridge->bus; - msm_pcie_fixup_irqs(dev); pci_assign_unassigned_bus_resources(bus); pci_bus_add_devices(bus); -- GitLab From 51d0318d91f38947bc419d887d80189ba0bdda90 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 3 Jan 2019 12:05:17 -0800 Subject: [PATCH 0832/1286] msm: pcie: add support for varying PCIe PHY status bit Status bit for PCIe PHY varies for each PCIe core. Add the support to check the correct status bit for each of them. Update sa8155 and sm8150 with PCIe PHY status bit. Change-Id: Iba583eeb3ef41c12381bee7ff2d6dd1d4cdb5fba Signed-off-by: Tony Truong --- arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi | 4 +++- drivers/pci/host/pci-msm.c | 22 ++++++++++++++++++++-- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi b/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi index 1dc11652bfca..ad28c5319249 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -189,6 +189,7 @@ qcom,slv-addr-space-size = <0x20000000>; qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x804>; qcom,boot-option = <0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index 0066be6ccd29..e1753d4cf23d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -173,6 +173,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x840>; qcom,boot-option = <0x1>; @@ -489,6 +490,7 @@ qcom,slv-addr-space-size = <0x20000000>; qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0xa40>; qcom,boot-option = <0x1>; diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index e7343111e4f5..bf29447498d6 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -590,6 +590,7 @@ struct msm_pcie_dev_t { uint32_t wr_halt_size; uint32_t slv_addr_space_size; uint32_t phy_status_offset; + uint32_t phy_status_bit; uint32_t phy_power_down_offset; uint32_t cpl_timeout; uint32_t current_bdf; @@ -1001,7 +1002,8 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev) static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) { - if (readl_relaxed(dev->phy + dev->phy_status_offset) & BIT(6)) + if (readl_relaxed(dev->phy + dev->phy_status_offset) & + BIT(dev->phy_status_bit)) return false; else return true; @@ -1241,6 +1243,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) dev->slv_addr_space_size); PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n", dev->phy_status_offset); + PCIE_DBG_FS(dev, "phy_status_bit: %u\n", + dev->phy_status_bit); PCIE_DBG_FS(dev, "phy_power_down_offset: 0x%x\n", dev->phy_power_down_offset); PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n", @@ -5563,6 +5567,20 @@ static int msm_pcie_probe(struct platform_device *pdev) rc_idx, msm_pcie_dev[rc_idx].phy_status_offset); } + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,phy-status-bit", + &msm_pcie_dev[rc_idx].phy_status_bit); + if (ret) { + PCIE_ERR(&msm_pcie_dev[rc_idx], + "RC%d: failed to get PCIe PHY status bit.\n", + rc_idx); + goto decrease_rc_num; + } else { + PCIE_DBG(&msm_pcie_dev[rc_idx], + "RC%d: phy-status-bit: 0x%x.\n", + rc_idx, msm_pcie_dev[rc_idx].phy_status_bit); + } + msm_pcie_dev[rc_idx].phy_power_down_offset = 0; ret = of_property_read_u32(pdev->dev.of_node, "qcom,phy-power-down-offset", -- GitLab From 8c3e78e5c269c8611be0d8b59ce75a4c22d94628 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 11 Dec 2018 13:17:42 -0800 Subject: [PATCH 0833/1286] msm: pcie: remove IO/MEM resource in PCIe root complex driver PCIe root complex driver ioremaps IO and MEM resource but does nothing with them. When MEM space is very large (ex: 1GB), PCIe root bus driver fails to ioremap it. Therefore, remove the ioremap of IO and MEM in PCIe root complex driver. Change-Id: If333d2d785c9d36bc8156fe84f6671ba98de8ab3 Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 6c8d06c0cf0e..0cdb9b8b218a 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -289,8 +289,6 @@ enum msm_pcie_res { MSM_PCIE_RES_ELBI, MSM_PCIE_RES_IATU, MSM_PCIE_RES_CONF, - MSM_PCIE_RES_IO, - MSM_PCIE_RES_BARS, MSM_PCIE_RES_TCSR, MSM_PCIE_MAX_RES, }; @@ -538,15 +536,11 @@ struct msm_pcie_dev_t { void __iomem *iatu; void __iomem *dm_core; void __iomem *conf; - void __iomem *bars; void __iomem *tcsr; uint32_t axi_bar_start; uint32_t axi_bar_end; - struct resource *dev_mem_res; - struct resource *dev_io_res; - uint32_t wake_n; uint32_t vreg_n; uint32_t gpio_n; @@ -852,8 +846,6 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { {"elbi", NULL, NULL}, {"iatu", NULL, NULL}, {"conf", NULL, NULL}, - {"io", NULL, NULL}, - {"bars", NULL, NULL}, {"tcsr", NULL, NULL} }; @@ -3711,11 +3703,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, dev->iatu = dev->res[MSM_PCIE_RES_IATU].base; dev->dm_core = dev->res[MSM_PCIE_RES_DM_CORE].base; dev->conf = dev->res[MSM_PCIE_RES_CONF].base; - dev->bars = dev->res[MSM_PCIE_RES_BARS].base; dev->tcsr = dev->res[MSM_PCIE_RES_TCSR].base; - dev->dev_mem_res = dev->res[MSM_PCIE_RES_BARS].resource; - dev->dev_io_res = dev->res[MSM_PCIE_RES_IO].resource; - dev->dev_io_res->flags = IORESOURCE_IO; out: kfree(clkfreq); @@ -3732,10 +3720,7 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) dev->iatu = NULL; dev->dm_core = NULL; dev->conf = NULL; - dev->bars = NULL; dev->tcsr = NULL; - dev->dev_mem_res = NULL; - dev->dev_io_res = NULL; } static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) -- GitLab From 410254eb6111a07562e6653aff5313786addbf99 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 4 Dec 2018 17:41:15 -0800 Subject: [PATCH 0834/1286] defconfig: enable PCIe host driver for sdxprairie Enable PCIe root complex and MSI driver for sdxprairie. Change-Id: Ibbce4f67e31fe421652d021abd612c18216f84a1 Signed-off-by: Tony Truong --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 06757e3b2072..a51fc4ac7ff3 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -31,6 +31,8 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_SDXPRAIRIE=y # CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y CONFIG_PREEMPT=y CONFIG_CMA=y CONFIG_SECCOMP=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index ea92f25481b0..f8f3ceae66a9 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -31,6 +31,8 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_SDXPRAIRIE=y # CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y CONFIG_PREEMPT=y CONFIG_CMA=y CONFIG_SECCOMP=y -- GitLab From 80930678aa642b8840a7671e7a378fb0cffd36a3 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Thu, 10 Jan 2019 15:33:36 -0800 Subject: [PATCH 0835/1286] rpmsg: glink: spi: Fix reuseable intent leak Reusuable intents are not freed on channel release, add handling to free the local intents and destroy the intent idr structures in the channel release work. Change-Id: I4b314513737815d60eae2079c3c53828638ab372 Signed-off-by: Chris Lew --- drivers/rpmsg/qcom_glink_spi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/rpmsg/qcom_glink_spi.c b/drivers/rpmsg/qcom_glink_spi.c index 75ece8260302..3f195846e8e7 100644 --- a/drivers/rpmsg/qcom_glink_spi.c +++ b/drivers/rpmsg/qcom_glink_spi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -355,12 +355,21 @@ glink_spi_alloc_channel(struct glink_spi *glink, const char *name) static void glink_spi_channel_release(struct kref *ref) { struct glink_spi_channel *channel; + struct glink_spi_rx_intent *tmp; + int iid; channel = container_of(ref, struct glink_spi_channel, refcount); CH_INFO(channel, "\n"); mutex_lock(&channel->intent_lock); + idr_for_each_entry(&channel->liids, tmp, iid) { + kfree(tmp->data); + kfree(tmp); + } idr_destroy(&channel->liids); + + idr_for_each_entry(&channel->riids, tmp, iid) + kfree(tmp); idr_destroy(&channel->riids); mutex_unlock(&channel->intent_lock); @@ -2410,9 +2419,9 @@ static void glink_spi_remove(struct glink_spi *glink) } /* Release any defunct local channels, waiting for close-req */ - idr_for_each_entry(&glink->lcids, channel, cid) { + idr_for_each_entry(&glink->rcids, channel, cid) { kref_put(&channel->refcount, glink_spi_channel_release); - idr_remove(&glink->lcids, cid); + idr_remove(&glink->rcids, cid); } idr_destroy(&glink->lcids); -- GitLab From 79038b826de2434901d1a79337c0e7c53871b36f Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Mon, 12 Feb 2018 18:06:53 -0800 Subject: [PATCH 0836/1286] usb: f_gsi: Instantiate all gsi protocols upon module init commit cc5d01e10248 ("usb: gadget: gsi: Defer freeing memory on free_inst if in use") overwrite file pointer private data in gsi_ctrl_dev_open(). If char device node gets re-opened container_of in gsi_ctrl_dev_open() may result into unmapped memory access. Since this commit is trying to fix use after free issue therefore allocate all gsi protocol instances upon module init. Update protocol id and create misc device node upon set_instance. Also allocate one ipc_log context with NUM_LOG_PAGES as 15. Add protocol id as part of the log in order to distinguishe different protocol logging. This change fixes warnings when enum usb_prot_id and enum ipa_usb_teth_prot related assignment used. warning: implicit conversion from enumeration type 'enum usb_prot_id' to different enumeration type 'enum ipa_usb_teth_prot' [-Wenum-conversion] Change-Id: I784fb1e3a36b45e8cdca6747ec9fe9bae5a3f5ad Signed-off-by: Hemant Kumar Signed-off-by: Mayank Rana --- drivers/usb/gadget/function/f_gsi.c | 360 ++++++++++------------------ drivers/usb/gadget/function/f_gsi.h | 33 +-- 2 files changed, 135 insertions(+), 258 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 2c76d2c833e9..b598ea4fd2f4 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -36,20 +36,41 @@ module_param(gsi_host_addr, charp, 0644); MODULE_PARM_DESC(gsi_host_addr, "QC Host Ethernet Address"); static struct workqueue_struct *ipa_usb_wq; -static struct gsi_inst_status { - struct mutex gsi_lock; - bool inst_exist; - struct gsi_opts *opts; -} inst_status[IPA_USB_MAX_TETH_PROT_SIZE]; - -#define MAX_CDEV_INSTANCES 3 +static struct f_gsi *__gsi[IPA_USB_MAX_TETH_PROT_SIZE]; +static void *ipc_log_ctxt; + +#define NUM_LOG_PAGES 15 +#define log_event_err(x, ...) do { \ + if (gsi) { \ + ipc_log_string(ipc_log_ctxt, "id%d:"x, gsi->prot_id, \ + ##__VA_ARGS__); \ + pr_err("id%d:"x, gsi->prot_id, ##__VA_ARGS__); \ + } \ +} while (0) + +#define log_event_dbg(x, ...) do { \ + if (gsi) { \ + ipc_log_string(ipc_log_ctxt, "id%d:"x, gsi->prot_id, \ + ##__VA_ARGS__); \ + pr_debug("id%d:"x, gsi->prot_id, ##__VA_ARGS__); \ + } \ +} while (0) + +#define log_event_info(x, ...) do { \ + if (gsi) { \ + ipc_log_string(ipc_log_ctxt, "id%d:"x, gsi->prot_id, \ + ##__VA_ARGS__); \ + pr_info("id%d:"x, gsi->prot_id, ##__VA_ARGS__); \ + } \ +} while (0) + +#define MAX_CDEV_INSTANCES 6 static int major; static struct class *gsi_class; static DEFINE_IDA(gsi_ida); /* Deregister misc device and free instance structures */ -static void gsi_inst_clean(struct gsi_opts *opts); static void gsi_rndis_ipa_reset_trigger(struct gsi_data_port *d_port); static void ipa_disconnect_handler(struct gsi_data_port *d_port); static int gsi_ctrl_send_notification(struct f_gsi *gsi); @@ -225,11 +246,7 @@ static struct f_gsi *get_connected_gsi(void) int i; for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) { - if (inst_status[i].opts) - connected_gsi = inst_status[i].opts->gsi; - else - continue; - + connected_gsi = __gsi[i]; if (connected_gsi && atomic_read(&connected_gsi->connected)) { gsi_connected = true; break; @@ -391,10 +408,10 @@ static int usb_gsi_debugfs_init(void) debugfs_create_file("remote_wakeup_enable", 0600, debugfs.debugfs_root, - inst_status, &fops_usb_gsi_rw); + __gsi, &fops_usb_gsi_rw); debugfs_create_file("remote_wakeup_interval", 0600, debugfs.debugfs_root, - inst_status, + __gsi, &fops_usb_gsi_rw_timer); return 0; } @@ -522,7 +539,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) (gsi->prot_id != IPA_USB_DIAG) ? IPA_CLIENT_USB_CONS : IPA_CLIENT_USB_DPL_CONS; in_params->ipa_ep_cfg.mode.mode = IPA_BASIC; - in_params->teth_prot = gsi->prot_id; + in_params->teth_prot = (int)gsi->prot_id; in_params->gevntcount_low_addr = gsi_channel_info.gevntcount_low_addr; in_params->gevntcount_hi_addr = @@ -563,7 +580,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) log_event_dbg("%s: USB GSI OUT OPS Completed", __func__); out_params->client = IPA_CLIENT_USB_PROD; out_params->ipa_ep_cfg.mode.mode = IPA_BASIC; - out_params->teth_prot = gsi->prot_id; + out_params->teth_prot = (int)gsi->prot_id; out_params->gevntcount_low_addr = gsi_channel_info.gevntcount_low_addr; out_params->gevntcount_hi_addr = @@ -611,7 +628,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) conn_params->usb_to_ipa_xferrscidx_valid = (gsi->prot_id != IPA_USB_DIAG) ? true : false; conn_params->ipa_to_usb_xferrscidx_valid = true; - conn_params->teth_prot = gsi->prot_id; + conn_params->teth_prot = (int)gsi->prot_id; conn_params->teth_prot_params.max_xfer_size_bytes_to_dev = 23700; conn_params->teth_prot_params.max_xfer_size_bytes_to_dev = d_port->out_aggr_size; @@ -732,7 +749,7 @@ static void ipa_disconnect_work_handler(struct gsi_data_port *d_port) log_event_dbg("%s: Calling xdci_disconnect", __func__); ret = ipa_usb_xdci_disconnect(gsi->d_port.out_channel_handle, - gsi->d_port.in_channel_handle, gsi->prot_id); + gsi->d_port.in_channel_handle, (int)gsi->prot_id); if (ret) log_event_err("%s: IPA disconnect failed %d", __func__, ret); @@ -775,7 +792,8 @@ static int ipa_suspend_work_handler(struct gsi_data_port *d_port) log_event_dbg("%s: Calling xdci_suspend", __func__); ret = ipa_usb_xdci_suspend(gsi->d_port.out_channel_handle, - gsi->d_port.in_channel_handle, gsi->prot_id, + gsi->d_port.in_channel_handle, + (int)gsi->prot_id, usb_gsi_remote_wakeup_allowed(f)); if (!ret) { d_port->sm_state = STATE_SUSPENDED; @@ -809,7 +827,7 @@ static void ipa_resume_work_handler(struct gsi_data_port *d_port) ret = ipa_usb_xdci_resume(gsi->d_port.out_channel_handle, gsi->d_port.in_channel_handle, - gsi->prot_id); + (int)gsi->prot_id); if (ret) log_event_dbg("%s: xdci_resume ret %d", __func__, ret); @@ -1163,68 +1181,43 @@ static int gsi_ctrl_dev_open(struct inode *ip, struct file *fp) struct gsi_ctrl_port *c_port = container_of(ip->i_cdev, struct gsi_ctrl_port, cdev); struct f_gsi *gsi; - struct gsi_inst_status *inst_cur; if (!c_port) { pr_err_ratelimited("%s: gsi ctrl port %pK", __func__, c_port); return -ENODEV; } - gsi = container_of(c_port, struct f_gsi, c_port); - inst_cur = &inst_status[gsi->prot_id]; - log_event_dbg("%s: open ctrl dev %s", __func__, c_port->name); - - mutex_lock(&inst_cur->gsi_lock); - - fp->private_data = &gsi->prot_id; + gsi = c_port_to_gsi(c_port); - if (!inst_cur->inst_exist) { - mutex_unlock(&inst_cur->gsi_lock); - log_event_err("%s: [prot_id = %d], GSI instance freed already\n", - __func__, gsi->prot_id); - return -ENODEV; - } + log_event_dbg("%s: open ctrl dev %s", __func__, c_port->name); if (c_port->is_open) { - mutex_unlock(&inst_cur->gsi_lock); log_event_err("%s: Already opened\n", __func__); return -EBUSY; } + fp->private_data = &c_port->cdev; c_port->is_open = true; - mutex_unlock(&inst_cur->gsi_lock); - return 0; } static int gsi_ctrl_dev_release(struct inode *ip, struct file *fp) { - enum ipa_usb_teth_prot prot_id = - *(enum ipa_usb_teth_prot *)(fp->private_data); - struct gsi_inst_status *inst_cur = &inst_status[prot_id]; + struct gsi_ctrl_port *c_port = container_of(ip->i_cdev, + struct gsi_ctrl_port, cdev); struct f_gsi *gsi; - mutex_lock(&inst_cur->gsi_lock); - - if (unlikely(inst_cur->inst_exist == false)) { - if (inst_cur->opts) { - /* GSI instance clean up */ - gsi_inst_clean(inst_cur->opts); - inst_cur->opts = NULL; - } - mutex_unlock(&inst_cur->gsi_lock); - pr_err_ratelimited("%s: prot_id:%d: delayed free memory\n", - __func__, prot_id); + if (!c_port) { + pr_err_ratelimited("%s: gsi ctrl port NULL", __func__); return -ENODEV; } - inst_cur->opts->gsi->c_port.is_open = false; - gsi = inst_cur->opts->gsi; - mutex_unlock(&inst_cur->gsi_lock); + gsi = c_port_to_gsi(c_port); - log_event_dbg("close ctrl dev %s\n", - inst_cur->opts->gsi->c_port.name); + log_event_dbg("close ctrl dev %s\n", c_port->name); + + c_port->is_open = false; return 0; } @@ -1232,33 +1225,23 @@ static int gsi_ctrl_dev_release(struct inode *ip, struct file *fp) static ssize_t gsi_ctrl_dev_read(struct file *fp, char __user *buf, size_t count, loff_t *pos) { - struct gsi_ctrl_port *c_port; + struct gsi_ctrl_port *c_port = container_of(fp->private_data, + struct gsi_ctrl_port, + cdev); struct gsi_ctrl_pkt *cpkt = NULL; - enum ipa_usb_teth_prot prot_id = - *(enum ipa_usb_teth_prot *)(fp->private_data); - struct gsi_inst_status *inst_cur = &inst_status[prot_id]; - struct f_gsi *gsi; unsigned long flags; int ret = 0; + struct f_gsi *gsi; - pr_debug("%s: Enter %zu", __func__, count); - - mutex_lock(&inst_cur->gsi_lock); - if (unlikely(inst_cur->inst_exist == false)) { - mutex_unlock(&inst_cur->gsi_lock); - pr_err_ratelimited("%s: free_inst is called and being freed\n", - __func__); - return -ENODEV; - } - mutex_unlock(&inst_cur->gsi_lock); - - gsi = inst_cur->opts->gsi; - c_port = &inst_cur->opts->gsi->c_port; if (!c_port) { - log_event_err("%s: gsi ctrl port %pK", __func__, c_port); + pr_err_ratelimited("%s: gsi ctrl port NULL", __func__); return -ENODEV; } + gsi = c_port_to_gsi(c_port); + + log_event_dbg("%s: Enter %zu", __func__, count); + if (count > GSI_MAX_CTRL_PKT_SIZE) { log_event_err("Large buff size %zu, should be %d", count, GSI_MAX_CTRL_PKT_SIZE); @@ -1321,34 +1304,32 @@ static ssize_t gsi_ctrl_dev_write(struct file *fp, const char __user *buf, int ret = 0; unsigned long flags; struct gsi_ctrl_pkt *cpkt; - struct gsi_ctrl_port *c_port; - struct usb_request *req; - enum ipa_usb_teth_prot prot_id = - *(enum ipa_usb_teth_prot *)(fp->private_data); - struct gsi_inst_status *inst_cur = &inst_status[prot_id]; struct f_gsi *gsi; + struct gsi_ctrl_port *c_port = container_of(fp->private_data, + struct gsi_ctrl_port, + cdev); - pr_debug("Enter %zu", count); - - mutex_lock(&inst_cur->gsi_lock); - if (unlikely(inst_cur->inst_exist == false)) { - mutex_unlock(&inst_cur->gsi_lock); - pr_err_ratelimited("%s: free_inst is called and being freed\n", - __func__); + if (!c_port) { + pr_err_ratelimited("%s: gsi ctrl port NULL", __func__); return -ENODEV; } - mutex_unlock(&inst_cur->gsi_lock); - gsi = inst_cur->opts->gsi; - c_port = &gsi->c_port; - req = c_port->notify_req; + if (!c_port->notify_req) { + pr_err_ratelimited("%s: gsi ctrl port notify_req NULL", + __func__); + return -ENODEV; + } - if (!c_port || !req || !req->buf) { - log_event_err("%s: c_port %pK req %p req->buf %p", - __func__, c_port, req, req ? req->buf : req); + if (!c_port->notify_req->buf) { + pr_err_ratelimited("%s: gsi ctrl port notify_req->buf", + __func__); return -ENODEV; } + gsi = c_port_to_gsi(c_port); + + log_event_dbg("%s: Enter %zu", __func__, count); + if (!count || count > GSI_MAX_CTRL_PKT_SIZE) { log_event_err("error: ctrl pkt length %zu", count); return -EINVAL; @@ -1399,34 +1380,23 @@ static ssize_t gsi_ctrl_dev_write(struct file *fp, const char __user *buf, static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) { - struct gsi_ctrl_port *c_port; + struct gsi_ctrl_port *c_port = container_of(fp->private_data, + struct gsi_ctrl_port, + cdev); struct f_gsi *gsi; struct gsi_ctrl_pkt *cpkt; struct ep_info info; struct data_buf_info data_info = {0}; - enum ipa_usb_teth_prot prot_id = - *(enum ipa_usb_teth_prot *)(fp->private_data); - struct gsi_inst_status *inst_cur = &inst_status[prot_id]; int val, ret = 0; unsigned long flags; - mutex_lock(&inst_cur->gsi_lock); - if (unlikely(inst_cur->inst_exist == false)) { - mutex_unlock(&inst_cur->gsi_lock); - pr_err_ratelimited("%s: free_inst is called and being freed\n", - __func__); - return -ENODEV; - } - mutex_unlock(&inst_cur->gsi_lock); - - gsi = inst_cur->opts->gsi; - c_port = &gsi->c_port; - if (!c_port) { - log_event_err("%s: gsi ctrl port %pK", __func__, c_port); + pr_err_ratelimited("%s: gsi ctrl port NULL", __func__); return -ENODEV; } + gsi = c_port_to_gsi(c_port); + switch (cmd) { case QTI_CTRL_MODEM_OFFLINE: if (gsi->prot_id == IPA_USB_DIAG) { @@ -1574,30 +1544,20 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, static unsigned int gsi_ctrl_dev_poll(struct file *fp, poll_table *wait) { - struct gsi_ctrl_port *c_port; - enum ipa_usb_teth_prot prot_id = - *(enum ipa_usb_teth_prot *)(fp->private_data); - struct gsi_inst_status *inst_cur = &inst_status[prot_id]; - struct f_gsi *gsi; + struct gsi_ctrl_port *c_port = container_of(fp->private_data, + struct gsi_ctrl_port, + cdev); unsigned long flags; unsigned int mask = 0; + struct f_gsi *gsi; - mutex_lock(&inst_cur->gsi_lock); - if (unlikely(inst_cur->inst_exist == false)) { - mutex_unlock(&inst_cur->gsi_lock); - pr_err_ratelimited("%s: free_inst is called and being freed\n", - __func__); - return -ENODEV; - } - mutex_unlock(&inst_cur->gsi_lock); - - gsi = inst_cur->opts->gsi; - c_port = &inst_cur->opts->gsi->c_port; if (!c_port) { - log_event_err("%s: gsi ctrl port %pK", __func__, c_port); + pr_err_ratelimited("%s: gsi ctrl port NULL", __func__); return -ENODEV; } + gsi = c_port_to_gsi(c_port); + poll_wait(fp, &c_port->read_wq, wait); spin_lock_irqsave(&c_port->lock, flags); @@ -1643,11 +1603,6 @@ static int gsi_function_ctrl_port_init(struct f_gsi *gsi) struct device *dev; bool ctrl_dev_create = true; - if (!gsi) { - log_event_err("%s: gsi prot ctx is NULL", __func__); - return -EINVAL; - } - INIT_LIST_HEAD(&gsi->c_port.cpkt_req_q); INIT_LIST_HEAD(&gsi->c_port.cpkt_resp_q); @@ -3182,7 +3137,7 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) } gsi->d_port.ipa_usb_notify_cb = ipa_usb_notify_cb; - status = ipa_usb_init_teth_prot(gsi->prot_id, + status = ipa_usb_init_teth_prot((int)gsi->prot_id, &gsi->d_port.ipa_init_params, gsi->d_port.ipa_usb_notify_cb, gsi); if (status) { @@ -3224,7 +3179,7 @@ static void gsi_unbind(struct usb_configuration *c, struct usb_function *f) * with ipa driver shall not fail due to unexpected state. */ drain_workqueue(gsi->d_port.ipa_usb_wq); - ipa_usb_deinit_teth_prot(gsi->prot_id); + ipa_usb_deinit_teth_prot((int)gsi->prot_id); if (gsi->prot_id == IPA_USB_RNDIS) { gsi->d_port.sm_state = STATE_UNINITIALIZED; @@ -3245,7 +3200,9 @@ static void gsi_unbind(struct usb_configuration *c, struct usb_function *f) static void gsi_free_func(struct usb_function *f) { - pr_debug("%s\n", __func__); + struct f_gsi *gsi = func_to_gsi(f); + + log_event_dbg("%s\n", __func__); } static int gsi_bind_config(struct f_gsi *gsi) @@ -3299,21 +3256,15 @@ static int gsi_bind_config(struct f_gsi *gsi) return status; } -static struct f_gsi *gsi_function_init(enum ipa_usb_teth_prot prot_id) +static struct f_gsi *gsi_function_init(void) { struct f_gsi *gsi; int ret = 0; - if (prot_id >= IPA_USB_MAX_TETH_PROT_SIZE) { - pr_err("%s: invalid prot id %d", __func__, prot_id); - ret = -EINVAL; - goto error; - } - gsi = kzalloc(sizeof(*gsi), GFP_KERNEL); if (!gsi) { ret = -ENOMEM; - goto error; + return ERR_PTR(ret); } spin_lock_init(&gsi->d_port.lock); @@ -3323,21 +3274,12 @@ static struct f_gsi *gsi_function_init(enum ipa_usb_teth_prot prot_id) gsi->d_port.in_channel_handle = -EINVAL; gsi->d_port.out_channel_handle = -EINVAL; - gsi->prot_id = prot_id; - gsi->d_port.ipa_usb_wq = ipa_usb_wq; - ret = gsi_function_ctrl_port_init(gsi); - if (ret) { - kfree(gsi); - goto error; - } gsi->gsi_rw_timer_interval = DEFAULT_RW_TIMER_INTERVAL; setup_timer(&gsi->gsi_rw_timer, gsi_rw_timer_func, (unsigned long) gsi); return gsi; -error: - return ERR_PTR(ret); } static void gsi_opts_release(struct config_item *item) @@ -3548,30 +3490,12 @@ static struct config_item_type gsi_func_rndis_type = { .ct_owner = THIS_MODULE, }; -static void gsi_inst_clean(struct gsi_opts *opts) -{ - if (opts->gsi->c_port.cdev.dev) { - struct cdev *cdev = &opts->gsi->c_port.cdev; - int minor = MINOR(cdev->dev); - - device_destroy(gsi_class, cdev->dev); - cdev_del(cdev); - cdev->dev = 0; - ida_simple_remove(&gsi_ida, minor); - } - - kfree(opts->gsi); - kfree(opts); -} - static int gsi_set_inst_name(struct usb_function_instance *fi, const char *name) { - int prot_id, name_len; + int prot_id, name_len, ret = 0; + struct gsi_opts *opts; struct f_gsi *gsi; - char gsi_inst_name[MAX_INST_NAME_LEN + sizeof("gsi.") + 1]; - void *ipc_log_ctxt; - struct gsi_opts *opts, *opts_prev; opts = container_of(fi, struct gsi_opts, func_inst); @@ -3586,73 +3510,34 @@ static int gsi_set_inst_name(struct usb_function_instance *fi, return -EINVAL; } - mutex_lock(&inst_status[prot_id].gsi_lock); - opts_prev = inst_status[prot_id].opts; - if (opts_prev) { - mutex_unlock(&inst_status[prot_id].gsi_lock); - pr_err("%s: prot_id = %d, prev inst do not freed yet\n", - __func__, prot_id); - return -EBUSY; - } - mutex_unlock(&inst_status[prot_id].gsi_lock); - if (prot_id == IPA_USB_RNDIS) config_group_init_type_name(&opts->func_inst.group, "", &gsi_func_rndis_type); - gsi = gsi_function_init(prot_id); - if (IS_ERR(gsi)) - return PTR_ERR(gsi); - - opts->gsi = gsi; - /* - * create instance name with prefixing "gsi." to differentiate - * ipc log debugfs entry - */ - snprintf(gsi_inst_name, sizeof(gsi_inst_name), "gsi.%s", name); - ipc_log_ctxt = ipc_log_context_create(NUM_LOG_PAGES, gsi_inst_name, 0); - if (!ipc_log_ctxt) - pr_err("%s: Err allocating ipc_log_ctxt for prot:%s\n", - __func__, gsi_inst_name); - opts->gsi->ipc_log_ctxt = ipc_log_ctxt; - - /* Set instance status */ - mutex_lock(&inst_status[prot_id].gsi_lock); - inst_status[prot_id].inst_exist = true; - inst_status[prot_id].opts = opts; - mutex_unlock(&inst_status[prot_id].gsi_lock); - - return 0; + gsi = opts->gsi = __gsi[prot_id]; + opts->gsi->prot_id = prot_id; + ret = gsi_function_ctrl_port_init(opts->gsi); + if (ret) + log_event_err("%s:ctrl port init failed for %s instance\n", + __func__, name); + return ret; } static void gsi_free_inst(struct usb_function_instance *f) { struct gsi_opts *opts = container_of(f, struct gsi_opts, func_inst); - enum ipa_usb_teth_prot prot_id; - struct f_gsi *gsi; - if (!opts->gsi) - return; + if (opts && opts->gsi && opts->gsi->c_port.cdev.dev) { + struct cdev *cdev = &opts->gsi->c_port.cdev; + int minor = MINOR(cdev->dev); - prot_id = opts->gsi->prot_id; - gsi = opts->gsi; - mutex_lock(&inst_status[prot_id].gsi_lock); - if (opts->gsi->c_port.is_open) { - /* Mark instance exist as false */ - inst_status[prot_id].inst_exist = false; - mutex_unlock(&inst_status[prot_id].gsi_lock); - log_event_err( - "%s: [prot_id = %d] Dev is open, free mem when dev close\n", - __func__, prot_id); - return; + device_destroy(gsi_class, cdev->dev); + cdev_del(cdev); + cdev->dev = 0; + ida_simple_remove(&gsi_ida, minor); } - ipc_log_context_destroy(opts->gsi->ipc_log_ctxt); - /* Clear instance status */ - gsi_inst_clean(opts); - inst_status[prot_id].inst_exist = false; - inst_status[prot_id].opts = NULL; - mutex_unlock(&inst_status[prot_id].gsi_lock); + kfree(opts); } static struct usb_function_instance *gsi_alloc_inst(void) @@ -3702,8 +3587,15 @@ static int fgsi_init(void) return -ENOMEM; } - for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) - mutex_init(&inst_status[i].gsi_lock); + for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) { + __gsi[i] = gsi_function_init(); + if (IS_ERR(__gsi[i])) + return PTR_ERR(__gsi[i]); + } + + ipc_log_ctxt = ipc_log_context_create(NUM_LOG_PAGES, "usb_gsi", 0); + if (!ipc_log_ctxt) + pr_err("%s: Err allocating ipc_log_ctxt\n", __func__); gsi_class = class_create(THIS_MODULE, "gsi_usb"); if (IS_ERR(gsi_class)) { @@ -3730,8 +3622,16 @@ module_init(fgsi_init); static void __exit fgsi_exit(void) { + int i; + if (ipa_usb_wq) destroy_workqueue(ipa_usb_wq); + if (ipc_log_ctxt) + ipc_log_context_destroy(ipc_log_ctxt); + + for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) + kfree(__gsi[i]); + usb_function_unregister(&gsiusb_func); if (major) { diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index be1260e81bc3..589427f48fbe 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -86,28 +86,6 @@ #define EVT_IPA_SUSPEND 9 #define EVT_RESUMED 10 -#define NUM_LOG_PAGES 10 -#define log_event_err(x, ...) do { \ - if (gsi) { \ - ipc_log_string(gsi->ipc_log_ctxt, x, ##__VA_ARGS__); \ - pr_err(x, ##__VA_ARGS__); \ - } \ -} while (0) - -#define log_event_dbg(x, ...) do { \ - if (gsi) { \ - ipc_log_string(gsi->ipc_log_ctxt, x, ##__VA_ARGS__); \ - pr_debug(x, ##__VA_ARGS__); \ - } \ -} while (0) - -#define log_event_info(x, ...) do { \ - if (gsi) { \ - ipc_log_string(gsi->ipc_log_ctxt, x, ##__VA_ARGS__); \ - pr_info(x, ##__VA_ARGS__); \ - } \ -} while (0) - enum connection_state { STATE_UNINITIALIZED, STATE_INITIALIZED, @@ -279,7 +257,6 @@ struct f_gsi { struct gsi_data_port d_port; struct gsi_ctrl_port c_port; - void *ipc_log_ctxt; bool rmnet_dtr_status; /* To test remote wakeup using debugfs */ @@ -323,15 +300,15 @@ static enum ipa_usb_teth_prot name_to_prot_id(const char *name) if (!name) goto error; - if (!strncasecmp(name, "rndis", strlen("rndis"))) + if (!strncasecmp(name, "rndis", MAX_INST_NAME_LEN)) return IPA_USB_RNDIS; - if (!strncasecmp(name, "ecm", strlen("ecm"))) + if (!strncasecmp(name, "ecm", MAX_INST_NAME_LEN)) return IPA_USB_ECM; - if (!strncasecmp(name, "rmnet", strlen("rmnet"))) + if (!strncasecmp(name, "rmnet", MAX_INST_NAME_LEN)) return IPA_USB_RMNET; - if (!strncasecmp(name, "mbim", strlen("mbim"))) + if (!strncasecmp(name, "mbim", MAX_INST_NAME_LEN)) return IPA_USB_MBIM; - if (!strncasecmp(name, "dpl", strlen("dpl"))) + if (!strncasecmp(name, "dpl", MAX_INST_NAME_LEN)) return IPA_USB_DIAG; error: -- GitLab From 37a2d5895819aa991659a6bc04e941cc48328629 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 3 Jan 2018 16:21:02 -0800 Subject: [PATCH 0837/1286] usb: f_gsi: Add ethernet as extended protocol for rmnet and dpl For some targets rmnet and DPL data path goes over ethernet device. Treat such rmnet and DPL as extended protocols and pass instance name as gsi.function_name.extended_prot_name. Extended protocol id is used to perform ethernet device specific operations for data path. Define and use usb_prot_id enum which includes IPA accelerated protocol ids as well as extended non-accelerated protocol ids. Create new control device node for rmnet and DPL extended protocol instances. Change-Id: I1a0a04151d83e1cddf49aa2254e4ea862e2504d8 Signed-off-by: Hemant Kumar Signed-off-by: Mayank Rana --- drivers/usb/gadget/Kconfig | 1 + drivers/usb/gadget/function/f_gsi.c | 241 ++++++++++++++++++++-------- drivers/usb/gadget/function/f_gsi.h | 39 ++++- 3 files changed, 207 insertions(+), 74 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index e3fd6dfc346a..a59710ccf390 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -589,6 +589,7 @@ config USB_CONFIGFS_F_GSI bool "USB GSI function" select USB_F_GSI select USB_RNDIS + select USB_U_ETHER depends on USB_CONFIGFS help The GSI function supports the IPA Generic Software Interface found diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index b598ea4fd2f4..95278bcc60b7 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -36,7 +36,7 @@ module_param(gsi_host_addr, charp, 0644); MODULE_PARM_DESC(gsi_host_addr, "QC Host Ethernet Address"); static struct workqueue_struct *ipa_usb_wq; -static struct f_gsi *__gsi[IPA_USB_MAX_TETH_PROT_SIZE]; +static struct f_gsi *__gsi[USB_PROT_MAX]; static void *ipc_log_ctxt; #define NUM_LOG_PAGES 15 @@ -79,6 +79,15 @@ static void gsi_free_trb_buffer(struct f_gsi *gsi); static struct gsi_ctrl_pkt *gsi_ctrl_pkt_alloc(unsigned int len, gfp_t flags); static void gsi_ctrl_pkt_free(struct gsi_ctrl_pkt *pkt); +static inline bool is_ext_prot_ether(int prot_id) +{ + if (prot_id == USB_PROT_RMNET_ETHER || + prot_id == USB_PROT_DPL_ETHER) + return true; + + return false; +} + static inline bool usb_gsi_remote_wakeup_allowed(struct usb_function *f) { bool remote_wakeup_allowed; @@ -451,7 +460,7 @@ int ipa_usb_notify_cb(enum ipa_usb_notify_event event, log_event_err("%s: Set net_ready_trigger", __func__); gsi->d_port.net_ready_trigger = true; - if (gsi->prot_id == IPA_USB_ECM) { + if (gsi->prot_id == USB_PROT_ECM_IPA) { cpkt_notify_connect = gsi_ctrl_pkt_alloc(0, GFP_ATOMIC); if (IS_ERR(cpkt_notify_connect)) { spin_unlock_irqrestore(&gsi->d_port.lock, @@ -485,7 +494,7 @@ int ipa_usb_notify_cb(enum ipa_usb_notify_event event, * Do not post EVT_CONNECTED for RNDIS. * Data path for RNDIS is enabled on EVT_HOST_READY. */ - if (gsi->prot_id != IPA_USB_RNDIS) { + if (gsi->prot_id != USB_PROT_RNDIS_IPA) { post_event(&gsi->d_port, EVT_CONNECTED); queue_work(gsi->d_port.ipa_usb_wq, &gsi->d_port.usb_ipa_w); @@ -536,7 +545,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) log_event_dbg("%s: USB GSI IN OPS Completed", __func__); in_params->client = - (gsi->prot_id != IPA_USB_DIAG) ? IPA_CLIENT_USB_CONS : + (gsi->prot_id != USB_PROT_DIAG_IPA) ? IPA_CLIENT_USB_CONS : IPA_CLIENT_USB_DPL_CONS; in_params->ipa_ep_cfg.mode.mode = IPA_BASIC; in_params->teth_prot = (int)gsi->prot_id; @@ -626,7 +635,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) conn_params->usb_to_ipa_xferrscidx = d_port->out_xfer_rsc_index; conn_params->usb_to_ipa_xferrscidx_valid = - (gsi->prot_id != IPA_USB_DIAG) ? true : false; + (gsi->prot_id != USB_PROT_DIAG_IPA) ? true : false; conn_params->ipa_to_usb_xferrscidx_valid = true; conn_params->teth_prot = (int)gsi->prot_id; conn_params->teth_prot_params.max_xfer_size_bytes_to_dev = 23700; @@ -671,7 +680,7 @@ static int ipa_connect_channels(struct gsi_data_port *d_port) d_port->in_request.db_reg_phs_addr_msb = ipa_in_channel_out_params.db_reg_phs_addr_msb; - if (gsi->prot_id != IPA_USB_DIAG) { + if (gsi->prot_id != USB_PROT_DIAG_IPA) { d_port->out_channel_handle = ipa_out_channel_out_params.clnt_hdl; d_port->out_request.db_reg_phs_addr_lsb = @@ -1399,7 +1408,8 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, switch (cmd) { case QTI_CTRL_MODEM_OFFLINE: - if (gsi->prot_id == IPA_USB_DIAG) { + if (gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) { log_event_dbg("%s:Modem Offline not handled", __func__); goto exit_ioctl; } @@ -1417,7 +1427,8 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, gsi_ctrl_send_notification(gsi); break; case QTI_CTRL_MODEM_ONLINE: - if (gsi->prot_id == IPA_USB_DIAG) { + if (gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) { log_event_dbg("%s:Modem Online not handled", __func__); goto exit_ioctl; } @@ -1426,7 +1437,8 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, break; case QTI_CTRL_GET_LINE_STATE: val = atomic_read(&gsi->connected); - if (gsi->prot_id == IPA_USB_RMNET) + if (gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_RMNET_ETHER) val = gsi->rmnet_dtr_status; ret = copy_to_user((void __user *)arg, &val, sizeof(val)); @@ -1447,7 +1459,8 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, break; } - if (gsi->prot_id == IPA_USB_DIAG && + if ((gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) && (gsi->d_port.in_channel_handle == -EINVAL)) { ret = -EAGAIN; break; @@ -1462,7 +1475,8 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, info.ph_ep_info.ep_type = GSI_MBIM_DATA_EP_TYPE_HSUSB; info.ph_ep_info.peripheral_iface_id = gsi->data_id; info.ipa_ep_pair.cons_pipe_num = - (gsi->prot_id == IPA_USB_DIAG) ? -1 : + (gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) ? -1 : gsi->d_port.out_channel_handle; info.ipa_ep_pair.prod_pipe_num = gsi->d_port.in_channel_handle; @@ -1598,10 +1612,10 @@ static unsigned int gsi_xfer_bitrate(struct usb_gadget *g) static int gsi_function_ctrl_port_init(struct f_gsi *gsi) { int ret; + char *cdev_name = NULL; int sz = GSI_CTRL_NAME_LEN; int minor; struct device *dev; - bool ctrl_dev_create = true; INIT_LIST_HEAD(&gsi->c_port.cpkt_req_q); INIT_LIST_HEAD(&gsi->c_port.cpkt_resp_q); @@ -1610,17 +1624,30 @@ static int gsi_function_ctrl_port_init(struct f_gsi *gsi) init_waitqueue_head(&gsi->c_port.read_wq); - if (gsi->prot_id == IPA_USB_RMNET) - strlcat(gsi->c_port.name, GSI_RMNET_CTRL_NAME, sz); - else if (gsi->prot_id == IPA_USB_MBIM) - strlcat(gsi->c_port.name, GSI_MBIM_CTRL_NAME, sz); - else if (gsi->prot_id == IPA_USB_DIAG) - strlcat(gsi->c_port.name, GSI_DPL_CTRL_NAME, sz); - else - ctrl_dev_create = false; + switch (gsi->prot_id) { + case USB_PROT_RMNET_IPA: + cdev_name = GSI_RMNET_CTRL_NAME; + break; + case USB_PROT_RMNET_ETHER: + cdev_name = ETHER_RMNET_CTRL_NAME; + break; + case USB_PROT_MBIM_IPA: + cdev_name = GSI_MBIM_CTRL_NAME; + break; + case USB_PROT_DIAG_IPA: + cdev_name = GSI_DPL_CTRL_NAME; + break; + case USB_PROT_DPL_ETHER: + cdev_name = ETHER_DPL_CTRL_NAME; + break; + default: + break; + } - if (!ctrl_dev_create) + if (!cdev_name) return 0; + else + strlcat(gsi->c_port.name, cdev_name, sz); minor = ida_simple_get(&gsi_ida, 0, MAX_CDEV_INSTANCES, GFP_KERNEL); if (minor < 0) { @@ -1809,7 +1836,7 @@ static int gsi_ctrl_send_notification(struct f_gsi *gsi) event->wValue = cpu_to_le16(0); event->wLength = cpu_to_le16(0); - if (gsi->prot_id == IPA_USB_RNDIS) { + if (gsi->prot_id == USB_PROT_RNDIS_IPA) { data = req->buf; data[0] = cpu_to_le32(1); data[1] = cpu_to_le32(0); @@ -2034,7 +2061,7 @@ gsi_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) /* read the request; process it later */ value = w_length; req->context = gsi; - if (gsi->prot_id == IPA_USB_RNDIS) + if (gsi->prot_id == USB_PROT_RNDIS_IPA) req->complete = gsi_rndis_command_complete; else req->complete = gsi_ctrl_cmd_complete; @@ -2046,7 +2073,7 @@ gsi_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) if (w_value || w_index != id) goto invalid; - if (gsi->prot_id == IPA_USB_RNDIS) { + if (gsi->prot_id == USB_PROT_RNDIS_IPA) { /* return the result */ buf = rndis_get_next_response(gsi->params, &n); if (buf) { @@ -2082,7 +2109,8 @@ gsi_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8) | USB_CDC_REQ_SET_CONTROL_LINE_STATE: line_state = (w_value & GSI_CTRL_DTR ? true : false); - if (gsi->prot_id == IPA_USB_RMNET) + if (gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_RMNET_ETHER) gsi->rmnet_dtr_status = line_state; log_event_dbg("%s: USB_CDC_REQ_SET_CONTROL_LINE_STATE DTR:%d\n", __func__, line_state); @@ -2179,9 +2207,10 @@ static int gsi_get_alt(struct usb_function *f, unsigned int intf) struct f_gsi *gsi = func_to_gsi(f); /* RNDIS, RMNET and DPL only support alt 0*/ - if (intf == gsi->ctrl_id || gsi->prot_id == IPA_USB_RNDIS || - gsi->prot_id == IPA_USB_RMNET || - gsi->prot_id == IPA_USB_DIAG) + if (intf == gsi->ctrl_id || gsi->prot_id == USB_PROT_RNDIS_IPA || + gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_DIAG_IPA || + is_ext_prot_ether(gsi->prot_id)) return 0; else if (intf == gsi->data_id) return gsi->data_interface_up; @@ -2300,7 +2329,8 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, log_event_dbg("intf=%u, alt=%u", intf, alt); /* Control interface has only altsetting 0 */ - if (intf == gsi->ctrl_id || gsi->prot_id == IPA_USB_RMNET) { + if (intf == gsi->ctrl_id || gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_RMNET_ETHER) { if (alt != 0) goto fail; @@ -2334,10 +2364,11 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, if (intf == gsi->data_id) { gsi->d_port.net_ready_trigger = false; /* for rndis and rmnet alt is always 0 update alt accordingly */ - if (gsi->prot_id == IPA_USB_RNDIS || - gsi->prot_id == IPA_USB_RMNET || - gsi->prot_id == IPA_USB_DIAG) - alt = 1; + if (gsi->prot_id == USB_PROT_RNDIS_IPA || + gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_DIAG_IPA || + is_ext_prot_ether(gsi->prot_id)) + alt = 1; if (alt > 1) goto notify_ep_disable; @@ -2364,8 +2395,9 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, } /* Configure EPs for GSI */ - if (gsi->d_port.in_ep) { - if (gsi->prot_id == IPA_USB_DIAG) + if (gsi->d_port.in_ep && + gsi->prot_id <= USB_PROT_DIAG_IPA) { + if (gsi->prot_id == USB_PROT_DIAG_IPA) gsi->d_port.in_ep->ep_intr_num = 3; else gsi->d_port.in_ep->ep_intr_num = 2; @@ -2374,7 +2406,8 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, GSI_EP_OP_CONFIG); } - if (gsi->d_port.out_ep) { + if (gsi->d_port.out_ep && + gsi->prot_id <= USB_PROT_DIAG_IPA) { gsi->d_port.out_ep->ep_intr_num = 1; usb_gsi_ep_op(gsi->d_port.out_ep, &gsi->d_port.out_request, @@ -2383,7 +2416,17 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, gsi->d_port.gadget = cdev->gadget; - if (gsi->prot_id == IPA_USB_RNDIS) { + if (is_ext_prot_ether(gsi->prot_id)) { + net = gether_connect(&gsi->d_port.gether_port); + if (IS_ERR(net)) { + pr_err("%s:gether_connect err:%ld\n", + __func__, PTR_ERR(net)); + goto notify_ep_disable; + } + gsi->d_port.gether_port.cdc_filter = 0; + } + + if (gsi->prot_id == USB_PROT_RNDIS_IPA) { gsi_rndis_open(gsi); net = gsi_rndis_get_netdev("rndis0"); if (IS_ERR(net)) @@ -2395,7 +2438,7 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, &gsi->d_port.cdc_filter); } - if (gsi->prot_id == IPA_USB_ECM) + if (gsi->prot_id == USB_PROT_ECM_IPA) gsi->d_port.cdc_filter = DEFAULT_FILTER; /* @@ -2403,7 +2446,7 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, * handler which is invoked when the host sends the * GEN_CURRENT_PACKET_FILTER message. */ - if (gsi->prot_id != IPA_USB_RNDIS) + if (gsi->prot_id != USB_PROT_RNDIS_IPA) post_event(&gsi->d_port, EVT_CONNECT_IN_PROGRESS); queue_work(gsi->d_port.ipa_usb_wq, @@ -2424,7 +2467,8 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, atomic_set(&gsi->connected, 1); /* send 0 len pkt to qti to notify state change */ - if (gsi->prot_id == IPA_USB_DIAG) + if (gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) gsi_ctrl_send_cpkt_tomodem(gsi, NULL, 0); return 0; @@ -2445,10 +2489,11 @@ static void gsi_disable(struct usb_function *f) del_timer(&gsi->gsi_rw_timer); gsi->debugfs_rw_timer_enable = 0; - if (gsi->prot_id == IPA_USB_RNDIS) + if (gsi->prot_id == USB_PROT_RNDIS_IPA) rndis_uninit(gsi->params); - if (gsi->prot_id == IPA_USB_RMNET) + if (gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_RMNET_ETHER) gsi->rmnet_dtr_status = false; /* Disable Control Path */ @@ -2473,6 +2518,12 @@ static void gsi_disable(struct usb_function *f) gsi->host_supports_flow_control = false; log_event_dbg("%s deactivated", gsi->function.name); + + if (is_ext_prot_ether(gsi->prot_id)) { + gether_disconnect(&gsi->d_port.gether_port); + return; + } + ipa_disconnect_handler(&gsi->d_port); post_event(&gsi->d_port, EVT_DISCONNECTED); queue_work(gsi->d_port.ipa_usb_wq, &gsi->d_port.usb_ipa_w); @@ -2542,7 +2593,7 @@ static void gsi_resume(struct usb_function *f) * Check whether host supports flow_control are not. If yes * Trigger state machine explicitly on resume. */ - if (gsi->prot_id == IPA_USB_RNDIS && + if (gsi->prot_id == USB_PROT_RNDIS_IPA && !usb_gsi_remote_wakeup_allowed(f) && gsi->host_supports_flow_control) rndis_flow_control(gsi->params, false); @@ -2657,7 +2708,7 @@ static int gsi_update_function_bind_params(struct f_gsi *gsi, info->data_nop_desc->bInterfaceNumber = gsi->data_id; /* allocate instance-specific endpoints */ - if (info->fs_in_desc) { + if (info->fs_in_desc && gsi->prot_id <= USB_PROT_DIAG_IPA) { ep = usb_ep_autoconfig_by_name(cdev->gadget, info->fs_in_desc, info->in_epname); if (!ep) @@ -2665,9 +2716,17 @@ static int gsi_update_function_bind_params(struct f_gsi *gsi, gsi->d_port.in_ep = ep; msm_ep_config(gsi->d_port.in_ep, NULL); ep->driver_data = cdev; /* claim */ + } else { + if (info->fs_in_desc) { + ep = usb_ep_autoconfig(cdev->gadget, info->fs_in_desc); + if (!ep) + goto fail; + gsi->d_port.in_ep = ep; + ep->driver_data = cdev; /* claim */ + } } - if (info->fs_out_desc) { + if (info->fs_out_desc && gsi->prot_id <= USB_PROT_DIAG_IPA) { ep = usb_ep_autoconfig_by_name(cdev->gadget, info->fs_out_desc, info->out_epname); if (!ep) @@ -2675,6 +2734,14 @@ static int gsi_update_function_bind_params(struct f_gsi *gsi, gsi->d_port.out_ep = ep; msm_ep_config(gsi->d_port.out_ep, NULL); ep->driver_data = cdev; /* claim */ + } else { + if (info->fs_out_desc) { + ep = usb_ep_autoconfig(cdev->gadget, info->fs_out_desc); + if (!ep) + goto fail; + gsi->d_port.out_ep = ep; + ep->driver_data = cdev; /* claim */ + } } if (info->fs_notify_desc) { @@ -2801,14 +2868,17 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) struct gsi_function_bind_info info = {0}; struct f_gsi *gsi = func_to_gsi(f); struct rndis_params *params; + struct net_device *net; + char *name = NULL; int status; __u8 class; __u8 subclass; __u8 proto; - if (gsi->prot_id == IPA_USB_RMNET || - gsi->prot_id == IPA_USB_DIAG) + if (gsi->prot_id == USB_PROT_RMNET_IPA || + gsi->prot_id == USB_PROT_DIAG_IPA || + is_ext_prot_ether(gsi->prot_id)) gsi->ctrl_id = -ENODEV; else { status = gsi->ctrl_id = usb_interface_id(c, f); @@ -2821,7 +2891,7 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) goto fail; switch (gsi->prot_id) { - case IPA_USB_RNDIS: + case USB_PROT_RNDIS_IPA: info.string_defs = rndis_gsi_string_defs; info.ctrl_desc = &rndis_gsi_control_intf; info.ctrl_str_idx = 0; @@ -2971,7 +3041,7 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) info.ctrl_desc->bInterfaceProtocol = proto; break; - case IPA_USB_MBIM: + case USB_PROT_MBIM_IPA: info.string_defs = mbim_gsi_string_defs; info.ctrl_desc = &mbim_gsi_control_intf; info.ctrl_str_idx = 0; @@ -3018,7 +3088,8 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) c->bConfigurationValue + '0'; } break; - case IPA_USB_RMNET: + case USB_PROT_RMNET_IPA: + case USB_PROT_RMNET_ETHER: info.string_defs = rmnet_gsi_string_defs; info.data_desc = &rmnet_gsi_interface_desc; info.data_str_idx = 0; @@ -3043,8 +3114,9 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) info.out_req_buf_len = GSI_OUT_RMNET_BUF_LEN; info.out_req_num_buf = GSI_NUM_OUT_BUFFERS; info.notify_buf_len = sizeof(struct usb_cdc_notification); + name = "usb_rmnet"; break; - case IPA_USB_ECM: + case USB_PROT_ECM_IPA: info.string_defs = ecm_gsi_string_defs; info.ctrl_desc = &ecm_gsi_control_intf; info.ctrl_str_idx = 0; @@ -3097,7 +3169,8 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) gsi->d_port.ipa_init_params.host_ethaddr[5]); info.string_defs[1].s = gsi->ethaddr; break; - case IPA_USB_DIAG: + case USB_PROT_DIAG_IPA: + case USB_PROT_DPL_ETHER: info.string_defs = qdss_gsi_string_defs; info.data_desc = &qdss_gsi_data_intf_desc; info.data_str_idx = 0; @@ -3112,6 +3185,7 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) info.in_req_buf_len = 16384; info.in_req_num_buf = GSI_NUM_IN_BUFFERS; info.notify_buf_len = sizeof(struct usb_cdc_notification); + name = "dpl_usb"; break; default: log_event_err("%s: Invalid prot id %d", __func__, @@ -3123,6 +3197,29 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) if (status) goto dereg_rndis; + if (is_ext_prot_ether(gsi->prot_id)) { + if (!name) + return -EINVAL; + + gsi->d_port.gether_port.in_ep = gsi->d_port.in_ep; + gsi->d_port.gether_port.out_ep = gsi->d_port.out_ep; + net = gether_setup_name_default(name); + if (IS_ERR(net)) { + pr_err("%s: gether_setup failed\n", __func__); + return PTR_ERR(net); + } + gsi->d_port.gether_port.ioport = netdev_priv(net); + gether_set_gadget(net, c->cdev->gadget); + status = gether_register_netdev(net); + if (status < 0) { + pr_err("%s: gether_register_netdev failed\n", + __func__); + free_netdev(net); + return status; + } + goto skip_ipa_init; + } + status = ipa_register_ipa_ready_cb(ipa_ready_callback, gsi); if (!status) { log_event_info("%s: ipa is not ready", __func__); @@ -3148,6 +3245,7 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) gsi->d_port.sm_state = STATE_INITIALIZED; +skip_ipa_init: DBG(cdev, "%s: %s speed IN/%s OUT/%s NOTIFY/%s\n", f->name, gadget_is_superspeed(c->cdev->gadget) ? "super" : @@ -3170,6 +3268,12 @@ static void gsi_unbind(struct usb_configuration *c, struct usb_function *f) { struct f_gsi *gsi = func_to_gsi(f); + if (is_ext_prot_ether(gsi->prot_id)) { + gether_cleanup(gsi->d_port.gether_port.ioport); + gsi->d_port.gether_port.ioport = NULL; + goto skip_ipa_dinit; + } + /* * Use drain_workqueue to accomplish below conditions: * 1. Make sure that any running work completed @@ -3181,12 +3285,13 @@ static void gsi_unbind(struct usb_configuration *c, struct usb_function *f) drain_workqueue(gsi->d_port.ipa_usb_wq); ipa_usb_deinit_teth_prot((int)gsi->prot_id); - if (gsi->prot_id == IPA_USB_RNDIS) { +skip_ipa_dinit: + if (gsi->prot_id == USB_PROT_RNDIS_IPA) { gsi->d_port.sm_state = STATE_UNINITIALIZED; rndis_deregister(gsi->params); } - if (gsi->prot_id == IPA_USB_MBIM) + if (gsi->prot_id == USB_PROT_MBIM_IPA) mbim_gsi_ext_config_desc.function.subCompatibleID[0] = 0; usb_free_all_descriptors(f); @@ -3208,33 +3313,34 @@ static void gsi_free_func(struct usb_function *f) static int gsi_bind_config(struct f_gsi *gsi) { int status = 0; - enum ipa_usb_teth_prot prot_id = gsi->prot_id; - log_event_dbg("%s: prot id %d", __func__, prot_id); + log_event_dbg("%s: prot id %d", __func__, gsi->prot_id); - switch (prot_id) { - case IPA_USB_RNDIS: + switch (gsi->prot_id) { + case USB_PROT_RNDIS_IPA: gsi->function.name = "rndis"; gsi->function.strings = rndis_gsi_strings; break; - case IPA_USB_ECM: + case USB_PROT_ECM_IPA: gsi->function.name = "cdc_ethernet"; gsi->function.strings = ecm_gsi_strings; break; - case IPA_USB_RMNET: + case USB_PROT_RMNET_IPA: + case USB_PROT_RMNET_ETHER: gsi->function.name = "rmnet"; gsi->function.strings = rmnet_gsi_strings; break; - case IPA_USB_MBIM: + case USB_PROT_MBIM_IPA: gsi->function.name = "mbim"; gsi->function.strings = mbim_gsi_strings; break; - case IPA_USB_DIAG: + case USB_PROT_DIAG_IPA: + case USB_PROT_DPL_ETHER: gsi->function.name = "dpl"; gsi->function.strings = qdss_gsi_strings; break; default: - log_event_err("%s: invalid prot id %d", __func__, prot_id); + log_event_err("%s: invalid prot id %d", __func__, gsi->prot_id); return -EINVAL; } @@ -3493,9 +3599,10 @@ static struct config_item_type gsi_func_rndis_type = { static int gsi_set_inst_name(struct usb_function_instance *fi, const char *name) { - int prot_id, name_len, ret = 0; + int name_len, ret = 0; struct gsi_opts *opts; struct f_gsi *gsi; + enum usb_prot_id prot_id; opts = container_of(fi, struct gsi_opts, func_inst); @@ -3510,7 +3617,7 @@ static int gsi_set_inst_name(struct usb_function_instance *fi, return -EINVAL; } - if (prot_id == IPA_USB_RNDIS) + if (prot_id == USB_PROT_RNDIS_IPA) config_group_init_type_name(&opts->func_inst.group, "", &gsi_func_rndis_type); @@ -3587,7 +3694,7 @@ static int fgsi_init(void) return -ENOMEM; } - for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) { + for (i = 0; i < USB_PROT_MAX; i++) { __gsi[i] = gsi_function_init(); if (IS_ERR(__gsi[i])) return PTR_ERR(__gsi[i]); @@ -3629,7 +3736,7 @@ static void __exit fgsi_exit(void) if (ipc_log_ctxt) ipc_log_context_destroy(ipc_log_ctxt); - for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++) + for (i = 0; i < USB_PROT_MAX; i++) kfree(__gsi[i]); usb_function_unregister(&gsiusb_func); diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index 589427f48fbe..b6d447a5d4a7 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -28,9 +28,14 @@ #include #include +#include "u_ether.h" + #define GSI_RMNET_CTRL_NAME "rmnet_ctrl" #define GSI_MBIM_CTRL_NAME "android_mbim" #define GSI_DPL_CTRL_NAME "dpl_ctrl" +#define ETHER_RMNET_CTRL_NAME "rmnet_ctrl0" +#define ETHER_DPL_CTRL_NAME "dpl_ctrl0" + #define GSI_CTRL_NAME_LEN (sizeof(GSI_MBIM_CTRL_NAME)+2) #define GSI_MAX_CTRL_PKT_SIZE 8192 #define GSI_CTRL_DTR (1 << 0) @@ -118,6 +123,21 @@ enum rndis_class_id { RNDIS_ID_MAX, }; +enum usb_prot_id { + /* accelerated: redefined from ipa_usb.h, do not change order */ + USB_PROT_RNDIS_IPA, + USB_PROT_ECM_IPA, + USB_PROT_RMNET_IPA, + USB_PROT_MBIM_IPA, + USB_PROT_DIAG_IPA, + + /* non-accelerated */ + USB_PROT_RMNET_ETHER, + USB_PROT_DPL_ETHER, + + USB_PROT_MAX, +}; + #define MAXQUEUELEN 128 struct event_queue { u8 event[MAXQUEUELEN]; @@ -232,6 +252,7 @@ struct gsi_data_port { enum connection_state sm_state; struct event_queue evt_q; wait_queue_head_t wait_for_ipa_ready; + struct gether gether_port; /* Track these for debugfs */ struct ipa_usb_xdci_chan_params ipa_in_channel_params; @@ -241,7 +262,7 @@ struct gsi_data_port { struct f_gsi { struct usb_function function; - enum ipa_usb_teth_prot prot_id; + enum usb_prot_id prot_id; int ctrl_id; int data_id; u32 vendorID; @@ -295,21 +316,25 @@ static inline struct gsi_opts *to_gsi_opts(struct config_item *item) func_inst.group); } -static enum ipa_usb_teth_prot name_to_prot_id(const char *name) +static enum usb_prot_id name_to_prot_id(const char *name) { if (!name) goto error; if (!strncasecmp(name, "rndis", MAX_INST_NAME_LEN)) - return IPA_USB_RNDIS; + return USB_PROT_RNDIS_IPA; if (!strncasecmp(name, "ecm", MAX_INST_NAME_LEN)) - return IPA_USB_ECM; + return USB_PROT_ECM_IPA; if (!strncasecmp(name, "rmnet", MAX_INST_NAME_LEN)) - return IPA_USB_RMNET; + return USB_PROT_RMNET_IPA; if (!strncasecmp(name, "mbim", MAX_INST_NAME_LEN)) - return IPA_USB_MBIM; + return USB_PROT_MBIM_IPA; if (!strncasecmp(name, "dpl", MAX_INST_NAME_LEN)) - return IPA_USB_DIAG; + return USB_PROT_DIAG_IPA; + if (!strncasecmp(name, "rmnet.ether", MAX_INST_NAME_LEN)) + return USB_PROT_RMNET_ETHER; + if (!strncasecmp(name, "dpl.ether", MAX_INST_NAME_LEN)) + return USB_PROT_DPL_ETHER; error: return -EINVAL; -- GitLab From ef02260a620dfe5ba679cc5410dd87093ac876bd Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Tue, 29 May 2018 17:41:03 -0700 Subject: [PATCH 0838/1286] usb: gadget: f_gsi: Fix return type for name_to_prot_id() name_to_prot_id() returns -EINVAL for error case when return type is enum usb_prot_id. This return type is compared against < 0 without type casting to integer which returns false. As a result invalid prot_id is indexed for __gsi array. Fix the issue by changing return type to int. Change-Id: I0d833d59e95e2257255e841913a2eed5204c6ef5 Signed-off-by: Hemant Kumar --- drivers/usb/gadget/function/f_gsi.c | 3 +-- drivers/usb/gadget/function/f_gsi.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 95278bcc60b7..9e2cc09b1e12 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -3599,10 +3599,9 @@ static struct config_item_type gsi_func_rndis_type = { static int gsi_set_inst_name(struct usb_function_instance *fi, const char *name) { - int name_len, ret = 0; + int name_len, prot_id, ret = 0; struct gsi_opts *opts; struct f_gsi *gsi; - enum usb_prot_id prot_id; opts = container_of(fi, struct gsi_opts, func_inst); diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index b6d447a5d4a7..835235a951a7 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -316,7 +316,7 @@ static inline struct gsi_opts *to_gsi_opts(struct config_item *item) func_inst.group); } -static enum usb_prot_id name_to_prot_id(const char *name) +static int name_to_prot_id(const char *name) { if (!name) goto error; -- GitLab From 5a83d02cbbb15c6ef9fe193a1cea003e585b093c Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 15 Feb 2018 18:48:27 -0800 Subject: [PATCH 0839/1286] usb: gadget: f_gsi: Add support for gps function driver gps usb functionality is implemented using qmi packets. User space entity sends and receives QMI packets using misc device named /dev/gps. Change-Id: I73af1caa9b272597909199022739390274a4b034 Signed-off-by: Hemant Kumar --- drivers/usb/gadget/function/f_gsi.c | 40 ++++++++++++- drivers/usb/gadget/function/f_gsi.h | 91 +++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 9e2cc09b1e12..6ef5ccd9bc02 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -1640,6 +1640,9 @@ static int gsi_function_ctrl_port_init(struct f_gsi *gsi) case USB_PROT_DPL_ETHER: cdev_name = ETHER_DPL_CTRL_NAME; break; + case USB_PROT_GPS_CTRL: + cdev_name = GSI_GPS_CTRL_NAME; + break; default: break; } @@ -2544,6 +2547,11 @@ static void gsi_suspend(struct usb_function *f) return; } + if (!gsi->data_interface_up) { + log_event_dbg("%s: suspend done\n", __func__); + return; + } + block_db = true; usb_gsi_ep_op(gsi->d_port.in_ep, (void *)&block_db, GSI_EP_OP_SET_CLR_BLOCK_DBL); @@ -2587,6 +2595,11 @@ static void gsi_resume(struct usb_function *f) /* Check any pending cpkt, and queue immediately on resume */ gsi_ctrl_send_notification(gsi); + if (!gsi->data_interface_up) { + log_event_dbg("%s: resume done\n", __func__); + return; + } + /* * Linux host does not send RNDIS_MSG_INIT or non-zero * RNDIS_MESSAGE_PACKET_FILTER after performing bus resume. @@ -2886,9 +2899,11 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) goto fail; } - status = gsi->data_id = usb_interface_id(c, f); - if (status < 0) - goto fail; + if (gsi->prot_id != USB_PROT_GPS_CTRL) { + status = gsi->data_id = usb_interface_id(c, f); + if (status < 0) + goto fail; + } switch (gsi->prot_id) { case USB_PROT_RNDIS_IPA: @@ -3187,6 +3202,18 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) info.notify_buf_len = sizeof(struct usb_cdc_notification); name = "dpl_usb"; break; + case USB_PROT_GPS_CTRL: + info.string_defs = gps_string_defs; + info.ctrl_str_idx = 0; + info.ctrl_desc = &gps_interface_desc; + info.fs_notify_desc = &gps_fs_notify_desc; + info.hs_notify_desc = &gps_hs_notify_desc; + info.ss_notify_desc = &gps_ss_notify_desc; + info.fs_desc_hdr = gps_fs_function; + info.hs_desc_hdr = gps_hs_function; + info.ss_desc_hdr = gps_ss_function; + info.notify_buf_len = sizeof(struct usb_cdc_notification); + break; default: log_event_err("%s: Invalid prot id %d", __func__, gsi->prot_id); @@ -3197,6 +3224,9 @@ static int gsi_bind(struct usb_configuration *c, struct usb_function *f) if (status) goto dereg_rndis; + if (gsi->prot_id == USB_PROT_GPS_CTRL) + goto skip_ipa_init; + if (is_ext_prot_ether(gsi->prot_id)) { if (!name) return -EINVAL; @@ -3339,6 +3369,10 @@ static int gsi_bind_config(struct f_gsi *gsi) gsi->function.name = "dpl"; gsi->function.strings = qdss_gsi_strings; break; + case USB_PROT_GPS_CTRL: + gsi->function.name = "gps"; + gsi->function.strings = gps_strings; + break; default: log_event_err("%s: invalid prot id %d", __func__, gsi->prot_id); return -EINVAL; diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index 835235a951a7..fa37c548e63c 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -35,6 +35,7 @@ #define GSI_DPL_CTRL_NAME "dpl_ctrl" #define ETHER_RMNET_CTRL_NAME "rmnet_ctrl0" #define ETHER_DPL_CTRL_NAME "dpl_ctrl0" +#define GSI_GPS_CTRL_NAME "gps" #define GSI_CTRL_NAME_LEN (sizeof(GSI_MBIM_CTRL_NAME)+2) #define GSI_MAX_CTRL_PKT_SIZE 8192 @@ -134,6 +135,7 @@ enum usb_prot_id { /* non-accelerated */ USB_PROT_RMNET_ETHER, USB_PROT_DPL_ETHER, + USB_PROT_GPS_CTRL, USB_PROT_MAX, }; @@ -335,6 +337,8 @@ static int name_to_prot_id(const char *name) return USB_PROT_RMNET_ETHER; if (!strncasecmp(name, "dpl.ether", MAX_INST_NAME_LEN)) return USB_PROT_DPL_ETHER; + if (!strncasecmp(name, "gps", MAX_INST_NAME_LEN)) + return USB_PROT_GPS_CTRL; error: return -EINVAL; @@ -1434,4 +1438,91 @@ static struct usb_gadget_strings *qdss_gsi_strings[] = { &qdss_gsi_string_table, NULL, }; + +/* gps device descriptor */ +static struct usb_interface_descriptor gps_interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, + .bInterfaceSubClass = USB_CLASS_VENDOR_SPEC, + .bInterfaceProtocol = USB_CLASS_VENDOR_SPEC, + /* .iInterface = DYNAMIC */ +}; + +/* Full speed support */ +static struct usb_endpoint_descriptor gps_fs_notify_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .bInterval = 1 << LOG2_STATUS_INTERVAL_MSEC, +}; + +static struct usb_descriptor_header *gps_fs_function[] = { + (struct usb_descriptor_header *) &gps_interface_desc, + (struct usb_descriptor_header *) &gps_fs_notify_desc, + NULL, +}; + +/* High speed support */ +static struct usb_endpoint_descriptor gps_hs_notify_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .bInterval = LOG2_STATUS_INTERVAL_MSEC + 4, +}; + +static struct usb_descriptor_header *gps_hs_function[] = { + (struct usb_descriptor_header *) &gps_interface_desc, + (struct usb_descriptor_header *) &gps_hs_notify_desc, + NULL, +}; + +/* Super speed support */ +static struct usb_endpoint_descriptor gps_ss_notify_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .bInterval = LOG2_STATUS_INTERVAL_MSEC + 4, +}; + +static struct usb_ss_ep_comp_descriptor gps_ss_notify_comp_desc = { + .bLength = sizeof(gps_ss_notify_comp_desc), + .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, + + /* the following 3 values can be tweaked if necessary */ + /* .bMaxBurst = 0, */ + /* .bmAttributes = 0, */ + .wBytesPerInterval = cpu_to_le16(MAX_NOTIFY_SIZE), +}; + +static struct usb_descriptor_header *gps_ss_function[] = { + (struct usb_descriptor_header *) &gps_interface_desc, + (struct usb_descriptor_header *) &gps_ss_notify_desc, + (struct usb_descriptor_header *) &gps_ss_notify_comp_desc, + NULL, +}; + +/* String descriptors */ + +static struct usb_string gps_string_defs[] = { + [0].s = "GPS", + { } /* end of list */ +}; + +static struct usb_gadget_strings gps_string_table = { + .language = 0x0409, /* en-us */ + .strings = gps_string_defs, +}; + +static struct usb_gadget_strings *gps_strings[] = { + &gps_string_table, + NULL, +}; #endif -- GitLab From efd6cf622cbedd1617d39fcd99af5ceebb7f7005 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 23 May 2018 11:49:43 +0530 Subject: [PATCH 0840/1286] usb: f_gsi: Add EP_LOOKUP for USB_PROT_GPS_CTRL Add EP_LOOKUP for gps control channel and update the ep_type as USB and interface id used for GPS function so that user space Qmuxbridge process will use this info and update the response in DPM_OPEN_QMI Request for QMI communication. Change-Id: I45f640d952bdb513eb45c69711e61b2c2708f541 Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/function/f_gsi.c | 41 ++++++++++++++++++----------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 6ef5ccd9bc02..ca27089f743c 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -1466,27 +1466,36 @@ static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd, break; } - if (gsi->d_port.in_channel_handle == -EINVAL && - gsi->d_port.out_channel_handle == -EINVAL) { - ret = -EAGAIN; - break; + if (gsi->prot_id != USB_PROT_GPS_CTRL) { + if (gsi->d_port.in_channel_handle == -EINVAL && + gsi->d_port.out_channel_handle == -EINVAL) { + ret = -EAGAIN; + break; + } + info.ph_ep_info.ep_type = GSI_MBIM_DATA_EP_TYPE_HSUSB; + info.ph_ep_info.peripheral_iface_id = gsi->data_id; + } else { + info.ph_ep_info.ep_type = GSI_MBIM_DATA_EP_TYPE_HSUSB; + info.ph_ep_info.peripheral_iface_id = gsi->ctrl_id; } - info.ph_ep_info.ep_type = GSI_MBIM_DATA_EP_TYPE_HSUSB; - info.ph_ep_info.peripheral_iface_id = gsi->data_id; - info.ipa_ep_pair.cons_pipe_num = - (gsi->prot_id == USB_PROT_DIAG_IPA || - gsi->prot_id == USB_PROT_DPL_ETHER) ? -1 : - gsi->d_port.out_channel_handle; - info.ipa_ep_pair.prod_pipe_num = gsi->d_port.in_channel_handle; - log_event_dbg("%s: prot id :%d ep_type:%d intf:%d", __func__, gsi->prot_id, info.ph_ep_info.ep_type, info.ph_ep_info.peripheral_iface_id); - - log_event_dbg("%s: ipa_cons_idx:%d ipa_prod_idx:%d", - __func__, info.ipa_ep_pair.cons_pipe_num, - info.ipa_ep_pair.prod_pipe_num); + if (gsi->prot_id != USB_PROT_GPS_CTRL) { + info.ipa_ep_pair.cons_pipe_num = + (gsi->prot_id == USB_PROT_DIAG_IPA || + gsi->prot_id == USB_PROT_DPL_ETHER) ? -1 : + gsi->d_port.out_channel_handle; + info.ipa_ep_pair.prod_pipe_num = + gsi->d_port.in_channel_handle; + + + log_event_dbg("%s: ipa_cons_idx:%d ipa_prod_idx:%d", + __func__, + info.ipa_ep_pair.cons_pipe_num, + info.ipa_ep_pair.prod_pipe_num); + } ret = copy_to_user((void __user *)arg, &info, sizeof(info)); -- GitLab From b3784517f201f2630dd26e8a6db7dbb68f2d344f Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 27 Apr 2018 18:00:09 +0530 Subject: [PATCH 0841/1286] usb: f_gsi: Increase GPS EP maxpacket size to 64bytes Currently usb driver is using 8 bytes request on interrupt endpoint for all CDC functions. GPS host driver is expecting short packet/zero length packet on interrupt endpoint and failing the transfer with 8 bytes maxpacket. Increase the maxpacket size to 64 bytes so that host ends the transfer with a short packet. Change-Id: Icc9919fbd633468d3cc7d4d8ab1945730cdc7c06 Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/function/f_gsi.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h index fa37c548e63c..fe27ec77a486 100644 --- a/drivers/usb/gadget/function/f_gsi.h +++ b/drivers/usb/gadget/function/f_gsi.h @@ -348,6 +348,7 @@ static int name_to_prot_id(const char *name) #define LOG2_STATUS_INTERVAL_MSEC 5 #define MAX_NOTIFY_SIZE sizeof(struct usb_cdc_notification) +#define GPS_MAX_NOTIFY_SIZE 64 /* rmnet device descriptors */ @@ -1456,7 +1457,7 @@ static struct usb_endpoint_descriptor gps_fs_notify_desc = { .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_INT, - .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .wMaxPacketSize = cpu_to_le16(GPS_MAX_NOTIFY_SIZE), .bInterval = 1 << LOG2_STATUS_INTERVAL_MSEC, }; @@ -1472,7 +1473,7 @@ static struct usb_endpoint_descriptor gps_hs_notify_desc = { .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_INT, - .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .wMaxPacketSize = cpu_to_le16(GPS_MAX_NOTIFY_SIZE), .bInterval = LOG2_STATUS_INTERVAL_MSEC + 4, }; @@ -1488,7 +1489,7 @@ static struct usb_endpoint_descriptor gps_ss_notify_desc = { .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_INT, - .wMaxPacketSize = cpu_to_le16(MAX_NOTIFY_SIZE), + .wMaxPacketSize = cpu_to_le16(GPS_MAX_NOTIFY_SIZE), .bInterval = LOG2_STATUS_INTERVAL_MSEC + 4, }; @@ -1499,7 +1500,7 @@ static struct usb_ss_ep_comp_descriptor gps_ss_notify_comp_desc = { /* the following 3 values can be tweaked if necessary */ /* .bMaxBurst = 0, */ /* .bmAttributes = 0, */ - .wBytesPerInterval = cpu_to_le16(MAX_NOTIFY_SIZE), + .wBytesPerInterval = cpu_to_le16(GPS_MAX_NOTIFY_SIZE), }; static struct usb_descriptor_header *gps_ss_function[] = { -- GitLab From e594cb26a624e26fa67b7cc6344cc94d5964825f Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 1 Jun 2018 12:59:53 +0530 Subject: [PATCH 0842/1286] usb: gsi: Fix runtime PM usage count for MBIM interface GSI Driver get the usage count in work handler when set_alt 1 happens and this counter will decrement in disconnect work due to cable disconnect or in gsi_suspend for suspended state. In this case set alt to 0 came for MBIM interface and clear the data_interface_up flag. After that suspend happens and does not decrement the counter in gsi_suspend. This causes a mismatch of usage count and usb not entering to low power mode. Fix this by checking for USB_PROT_GPS_CTRL instead of data_interface_up. Change-Id: Iaabf3de46ed72e33980d1e3e386e8ca0ae651c74 Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/function/f_gsi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index ca27089f743c..62e833de5f23 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -2556,7 +2556,11 @@ static void gsi_suspend(struct usb_function *f) return; } - if (!gsi->data_interface_up) { + /* + * GPS doesn't use any data interface, hence bail out as there is no + * GSI specific handling needed. + */ + if (gsi->prot_id == USB_PROT_GPS_CTRL) { log_event_dbg("%s: suspend done\n", __func__); return; } @@ -2604,7 +2608,7 @@ static void gsi_resume(struct usb_function *f) /* Check any pending cpkt, and queue immediately on resume */ gsi_ctrl_send_notification(gsi); - if (!gsi->data_interface_up) { + if (gsi->prot_id == USB_PROT_GPS_CTRL) { log_event_dbg("%s: resume done\n", __func__); return; } -- GitLab From a20b8823c225da269f2e07cf762c6f5fbe818550 Mon Sep 17 00:00:00 2001 From: Devdutt Patnaik Date: Tue, 26 Jan 2016 14:38:01 -0800 Subject: [PATCH 0843/1286] usb: f_gsi: Ignore supsend/resume events if data interface is not selected Usually the GSI disconnect handler is invoked on disconnect and bus suspend (with remote wakeup disabled) conditions. However, for functions such as MBIM that support alternate data interface, suspend/resume handling becomes a no-op if the data interface is not selected. One such example is disabling/enabling network device from device manager or host sending set_alt 0 before suspend. This operation explicitly disables data interface, remains the state in STATE_CONNECT_IN_PROGRESS. After that when set_alt 1 comes from the host ipa_work_handler does enable the data interface in this state. Hence post the disconnect event in set_alt 0 handling and subsequent suspend/resume operations become no-ops. Change-Id: Idaf240ed5253f61880c05a1b11d87d4979d474c9 Signed-off-by: Devdutt Patnaik Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/function/f_gsi.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 62e833de5f23..2a0f5fb81a57 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -2468,8 +2468,13 @@ static int gsi_set_alt(struct usb_function *f, unsigned int intf, if (alt == 0 && ((gsi->d_port.in_ep && !gsi->d_port.in_ep->driver_data) || (gsi->d_port.out_ep && - !gsi->d_port.out_ep->driver_data))) + !gsi->d_port.out_ep->driver_data))) { ipa_disconnect_handler(&gsi->d_port); + post_event(&gsi->d_port, EVT_DISCONNECTED); + queue_work(gsi->d_port.ipa_usb_wq, + &gsi->d_port.usb_ipa_w); + log_event_dbg("%s: Disconnecting\n", __func__); + } gsi->data_interface_up = alt; log_event_dbg("DATA_INTERFACE id = %d, status = %d", @@ -2556,11 +2561,11 @@ static void gsi_suspend(struct usb_function *f) return; } - /* - * GPS doesn't use any data interface, hence bail out as there is no - * GSI specific handling needed. + /* For functions such as MBIM that support alternate data + * interface, suspend/resume handling becomes a no-op if the + * data interface is not selected. */ - if (gsi->prot_id == USB_PROT_GPS_CTRL) { + if (!gsi->data_interface_up) { log_event_dbg("%s: suspend done\n", __func__); return; } @@ -2608,7 +2613,7 @@ static void gsi_resume(struct usb_function *f) /* Check any pending cpkt, and queue immediately on resume */ gsi_ctrl_send_notification(gsi); - if (gsi->prot_id == USB_PROT_GPS_CTRL) { + if (!gsi->data_interface_up) { log_event_dbg("%s: resume done\n", __func__); return; } -- GitLab From 4337dd029c6880b77e2f2f025a9bf479c793e80d Mon Sep 17 00:00:00 2001 From: Cong Tang Date: Fri, 4 Jan 2019 11:42:59 +0800 Subject: [PATCH 0844/1286] ARM: dts: disable spi to solve gpio conflict Enable qupv3_se3_spi will cause soundcard probing failure due to GPIO conflict, disable it. Change-Id: Iaa35143abbff1509c0cae0876d1dcd607c9adfd3 Signed-off-by: Han Lu --- arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi b/arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi index 243ea1da6e4d..41693fb43e33 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -39,7 +39,7 @@ }; &qupv3_se3_spi { - status = "ok"; + status = "disabled"; }; &qupv3_se4_i2c { -- GitLab From fbdf15156040b9372c37d70b005e5f6d2c99e0df Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 9 Jan 2019 14:06:34 +0800 Subject: [PATCH 0845/1286] ARM: dts: msm: Add charger configuration for QRD Trinket interposer Add charger/QG/smb1355 configuration and battery profile for QRD Trinket interposer device to make sure battery charging can work properly. Change-Id: I8641703112b127e6e5df660edcad258580452be8 Signed-off-by: Fenglin Wu --- .../qcom/sm6150-interposer-trinket-qrd.dtsi | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi index 8c290200e04c..74548d5cffdb 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -27,6 +27,49 @@ }; }; +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + &soc { gpio_keys { compatible = "gpio-keys"; @@ -44,4 +87,57 @@ gpio-key,wakeup; }; }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; }; -- GitLab From 5cdfe2afc82b460518e9c8a82bac3c8ac76aac11 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 8 Jan 2019 12:08:24 -0800 Subject: [PATCH 0846/1286] defconfig: sdxprairie: Enable DIAG char driver Enable the DIAG char driver and USB transport to provide diagnostic communication to peripherals and user space clients. Change-Id: Ia4db595dc54a9bb3e684792b104c7d231fa46f70 Signed-off-by: Chris Lew --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 2399756ed133..c1cb5020847e 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -210,6 +210,7 @@ CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_HS=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MSM_V2=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 485c6bb27c7f..8cd017e96a22 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -198,6 +198,7 @@ CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_MSM_HS=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MSM_V2=y -- GitLab From afe299d3008c820c256cdedb10984f09dadd151f Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Mon, 22 Oct 2018 19:33:56 +0530 Subject: [PATCH 0847/1286] ARM: dts: msm: add support for sharp wuxga panel on sm6150 Add support for sharp split link wuxga panel in video mode on sm6150 platform. Change-Id: I23b9c8c5f92b441d25074ac0cea7d2410c87c95b Signed-off-by: Tharun Raj Soma --- ...si-panel-sharp-split-link-wuxga-video.dtsi | 74 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sm6150-idp.dtsi | 11 ++- .../boot/dts/qcom/sm6150-sde-display.dtsi | 33 ++++++++- arch/arm64/boot/dts/qcom/sm6150-sde.dtsi | 1 + 4 files changed, 117 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi new file mode 100644 index 000000000000..b778066a0950 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi @@ -0,0 +1,74 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sharp_split_link_wuxga_video: + qcom,mdss_dsi_sharp_split_link_wuxga_video { + qcom,mdss-dsi-panel-name = + "sharp split link video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 5>, <1 120>; + qcom,mdss-pan-physical-width-dimension = <83>; + qcom,mdss-pan-physical-height-dimension = <133>; + qcom,split-link-enabled; + qcom,sublinks-count = <2>; + qcom,lanes-per-sublink = <2>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <600>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <54>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <6>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [05 01 00 00 a0 00 02 11 00]; + qcom,mdss-dsi-post-panel-on-command = + [05 01 00 00 a0 00 02 29 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 02 00 02 28 00 + 05 01 00 00 a0 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-timings = + [00 24 07 08 0e 14 07 09 07 03 04 00]; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6150-idp.dtsi b/arch/arm64/boot/dts/qcom/sm6150-idp.dtsi index e114d6fae8a6..af7da0a89d94 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-idp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -384,3 +384,12 @@ qcom,platform-te-gpio = <&tlmm 90 0>; qcom,platform-reset-gpio = <&tlmm 91 0>; }; + +&dsi_sharp_split_link_wuxga_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi index 83a9ead4c847..5121eccfc693 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi @@ -19,6 +19,7 @@ #include "dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi" #include "dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi" #include "dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi" +#include "dsi-panel-sharp-split-link-wuxga-video.dtsi" #include &soc { @@ -194,6 +195,17 @@ qcom,dsi-panel = <&dsi_td4330_truly_cmd>; }; + dsi_sharp_split_link_wuxga_vid_display: qcom,dsi-display@9 { + label = "dsi_sharp_split_link_wuxga_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_split_link_wuxga_video>; + }; + sde_dsi: qcom,dsi-display { compatible = "qcom,dsi-display"; @@ -223,7 +235,8 @@ &dsi_rm69298_truly_amoled_vid_display &dsi_rm69298_truly_amoled_cmd_display &dsi_td4330_truly_vid_display - &dsi_td4330_truly_cmd_display>; + &dsi_td4330_truly_cmd_display + &dsi_sharp_split_link_wuxga_vid_display>; }; sde_wb: qcom,wb-display@0 { @@ -486,3 +499,21 @@ }; }; }; + +&dsi_sharp_split_link_wuxga_video { + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x35>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 08 0a 06 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi index a0eee26dd2b0..0ea8d505c73f 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde.dtsi @@ -388,6 +388,7 @@ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,split-link-supported; qcom,ctrl-supply-entries { #address-cells = <1>; -- GitLab From b2c4d945cff564592386deab04164397de77fa60 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 12 Dec 2018 14:17:30 -0800 Subject: [PATCH 0848/1286] mhi: core: fix 32-bit compilation errors Fix compile errors related to arm32 platforms. CRs-Fixed: 2378639 Change-Id: I6fd41673ff90a6902514d26d5af9e190d171c7a9 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_internal.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index 5165ffdc1904..8fac51e20928 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -221,7 +221,7 @@ extern struct bus_type mhi_bus_type; #define BHIE_RXVECSTATUS_STATUS_ERROR (0x03) /* convert ticks to micro seconds by dividing by 19.2 */ -#define TIME_TICKS_TO_US(x) (((x) * 10) / 192) +#define TIME_TICKS_TO_US(x) (div_u64((x) * 10, 192)) struct mhi_event_ctxt { u32 reserved : 8; @@ -330,7 +330,7 @@ enum mhi_cmd_type { | (ieot << 9) | (ieob << 8) | chain) /* rsc transfer descriptor macros */ -#define MHI_RSCTRE_DATA_PTR(ptr, len) ((len << 48) | ptr) +#define MHI_RSCTRE_DATA_PTR(ptr, len) (((u64)len << 48) | ptr) #define MHI_RSCTRE_DATA_DWORD0(cookie) (cookie) #define MHI_RSCTRE_DATA_DWORD1 (MHI_PKT_TYPE_COALESCING << 16) -- GitLab From 1a7a681ca48ea22dd1a3350f2d8217f35e7b917b Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Wed, 26 Dec 2018 17:56:26 +0530 Subject: [PATCH 0849/1286] sched/fair: Skip pulling tasks from cpu marked for active balancing Idle/newly idle cpu finds busiest runqueue to pull tasks from it. It is possible that, the busiest cpu might have already marked for active_balance by other cpu. But current balancing cpu still finds it as busiest cpu and tries to pull tasks from it. Which may have subtle impact, if higher capacity cpu has marked busy cpu for active balance, and before active balance kicks in by the busy cpu, the lower capacity cpu pulling tasks from the busy cpu ruins the higher capacity cpu's active balance. Fix this, by skipping the cpu which is undergoing active_balance for finding busiest queue and do not detach tasks if busiest cpu marked for active balance. Change-Id: If3ebe1a026cf62f055bb42c3f3ed62f3624c704a Signed-off-by: Lingutla Chandrasekhar --- kernel/sched/fair.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index b1d38be9bfdc..36479e15d966 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -10697,6 +10697,13 @@ static struct rq *find_busiest_queue(struct lb_env *env, continue; } + /* + * Ignore cpu, which is undergoing active_balance and doesn't + * have more than 2 tasks. + */ + if (rq->active_balance && rq->nr_running <= 2) + continue; + capacity = capacity_of(i); /* @@ -10920,8 +10927,14 @@ static int load_balance(int this_cpu, struct rq *this_rq, more_balance: rq_lock_irqsave(busiest, &rf); - /* The world might have changed. Validate assumptions */ - if (busiest->nr_running <= 1) { + /* + * The world might have changed. Validate assumptions. + * And also, if the busiest cpu is undergoing active_balance, + * it doesn't need help if it has less than 2 tasks on it. + */ + + if (busiest->nr_running <= 1 || + (busiest->active_balance && busiest->nr_running <= 2)) { rq_unlock_irqrestore(busiest, &rf); env.flags &= ~LBF_ALL_PINNED; goto no_move; -- GitLab From 46cbab8a8c6fdf884364e4b2e03277b4af8cf869 Mon Sep 17 00:00:00 2001 From: Manikanta Kanamarlapudi Date: Sun, 7 Oct 2018 16:46:11 +0530 Subject: [PATCH 0850/1286] msm: vidc: Configure work mode 2 based on rate control Existing code sets work mode as 1 for all encoder usecases. For VBR and MBR cases, work mode is required to be 2. Hence set the same based on RC mode. Change-Id: I0842ddd23750395a84ec87ffa76677675128e301 Signed-off-by: Manikanta Kanamarlapudi --- drivers/media/platform/msm/vidc/msm_vidc_clocks.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c index 53753dcb4409..37341da96661 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1265,7 +1265,15 @@ static int msm_vidc_decide_work_mode_ar50(struct msm_vidc_inst *inst) break; } } else if (inst->session_type == MSM_VIDC_ENCODER) { + u32 rc_mode = 0; + pdata.video_work_mode = VIDC_WORK_MODE_1; + rc_mode = msm_comm_g_ctrl_for_id(inst, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE); + if (rc_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR || + rc_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_MBR || + rc_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_MBR_VFR) + pdata.video_work_mode = VIDC_WORK_MODE_2; } else { return -EINVAL; } -- GitLab From 5cdff737480184aacf3f3dc1136761306136b6cd Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Mon, 10 Dec 2018 18:25:14 +0800 Subject: [PATCH 0851/1286] input: touchscreen: synaptics_tcm: disable the LPGW Do the following configuration for the new-gen synaptics touchscreen. 1. Disable the Low Power Gesture Wake. 2. Disable "Reset_ON_RESUME". 3. Enable the firmware upgrade when startup. Change-Id: I302bd00bdbff8506eb10210eb9ee66f1bc06c329 Signed-off-by: Fei Mao --- .../input/touchscreen/synaptics_tcm/synaptics_tcm_core.c | 2 +- .../input/touchscreen/synaptics_tcm/synaptics_tcm_core.h | 2 +- .../input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c index 70ce96a250f0..39c6d98668bd 100644 --- a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.c @@ -36,7 +36,7 @@ #include #include "synaptics_tcm_core.h" -#define RESET_ON_RESUME +/* #define RESET_ON_RESUME */ /* #define RESUME_EARLY_UNBLANK */ diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h index 09d7078cbae4..79c5e76f594d 100644 --- a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_core.h @@ -58,7 +58,7 @@ #define TOUCH_INPUT_NAME "synaptics_tcm_touch" #define TOUCH_INPUT_PHYS_PATH "synaptics_tcm/touch_input" -#define WAKEUP_GESTURE +/* #define WAKEUP_GESTURE */ #define RD_CHUNK_SIZE 0 /* read length limit in bytes, 0 = unlimited */ #define WR_CHUNK_SIZE 0 /* write length limit in bytes, 0 = unlimited */ diff --git a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c index 2e622fca191e..3217b58b0092 100644 --- a/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c +++ b/drivers/input/touchscreen/synaptics_tcm/synaptics_tcm_reflash.c @@ -44,7 +44,7 @@ #define CUSTOM_DIR_NAME "custom" -#define FW_IMAGE_NAME "synaptics/firmware.img" +#define FW_IMAGE_NAME "synaptics_firmware.img" #define BOOT_CONFIG_ID "BOOT_CONFIG" @@ -60,7 +60,7 @@ #define FB_READY_WAIT_MS 100 -#define FB_READY_TIMEOUT_S 30 +#define FB_READY_TIMEOUT_S 80 #define IMAGE_FILE_MAGIC_VALUE 0x4818472b @@ -1945,7 +1945,7 @@ static void reflash_startup_work(struct work_struct *work) #if defined(CONFIG_DRM) || defined(CONFIG_FB) timeout = FB_READY_TIMEOUT_S * 1000 / FB_READY_WAIT_MS; - while (tcm_hcd->fb_ready != FB_READY_COUNT) { + while (tcm_hcd->fb_ready != FB_READY_COUNT - 1) { if (timeout == 0) { LOGE(tcm_hcd->pdev->dev.parent, "Timed out waiting for FB ready\n"); -- GitLab From 24b697e7729e8106c6c01b3fdbf864504958d66e Mon Sep 17 00:00:00 2001 From: Shefali Jain Date: Fri, 11 Jan 2019 11:48:45 +0530 Subject: [PATCH 0852/1286] defconfig: Enable Debug CC for QCS405 Enable Debug clock controller driver support for perf image. Change-Id: I8eacb5398b22a035947226a1e46cba211340f363 Signed-off-by: Shefali Jain --- arch/arm/configs/vendor/qcs405-perf_defconfig | 1 + arch/arm64/configs/vendor/qcs405-perf_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 3fac1d1d4389..72a60ce8c2a2 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -385,6 +385,7 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_MDM_GCC_QCS405=y +CONFIG_MDM_DEBUGCC_QCS405=y CONFIG_CLOCK_CPU_QCS405=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index be4aab11a9aa..962a560bf307 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -409,6 +409,7 @@ CONFIG_QCOM_MDSS_PLL=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_MDM_GCC_QCS405=y +CONFIG_MDM_DEBUGCC_QCS405=y CONFIG_CLOCK_CPU_QCS405=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y -- GitLab From bb77f833460bb221ecd450feba6d2d28bcd7e96b Mon Sep 17 00:00:00 2001 From: Sahil Chandna Date: Thu, 20 Dec 2018 16:39:48 +0530 Subject: [PATCH 0853/1286] power: fg-alg: Improve the accuracy of capacity learning algorithm Capacity learning algorithm updates the capacity of battery with every charge cycle that qualify the criterion for learning. Improve the accuracy of capacity learning algorithm by adding the capacity from rounded off part of the SOC to the learned capacity value. Change-Id: Ibd5f062de919bf22b06eb3cbf6e5d0fc89f343e8 Signed-off-by: Sahil Chandna --- drivers/power/supply/qcom/fg-alg.c | 56 ++++++++++++++++++------------ drivers/power/supply/qcom/fg-alg.h | 2 ++ 2 files changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/power/supply/qcom/fg-alg.c b/drivers/power/supply/qcom/fg-alg.c index f97dbaf1244e..6e6b83c3b11b 100644 --- a/drivers/power/supply/qcom/fg-alg.c +++ b/drivers/power/supply/qcom/fg-alg.c @@ -372,20 +372,20 @@ static void cap_learning_post_process(struct cap_learning *cl) /** * cap_wt_learning_process_full_data - * @cl: Capacity learning object - * @batt_soc_pct: Battery State of Charge in percent - * @cc_soc_delta_pct: percentage change in cc_soc * @delta_batt_soc_pct: percentage change in battery State of Charge + * @batt_soc_msb: MSB of battery State of Charge * * Calculates the final learnt capacity when * weighted capacity learning is enabled. * */ static int cap_wt_learning_process_full_data(struct cap_learning *cl, - int batt_soc_pct, int cc_soc_delta_pct, - int delta_batt_soc_pct) + int delta_batt_soc_pct, + int batt_soc_msb) { - int64_t delta_cap_uah, del_cap_uah, total_cap_uah, + int64_t del_cap_uah, total_cap_uah, res_cap_uah, wt_learnt_cap_uah; + int delta_batt_soc_msb, res_batt_soc_msb; /* If the delta is < 10%, then skip processing full data */ if (delta_batt_soc_pct < cl->dt.min_delta_batt_soc) { @@ -393,23 +393,27 @@ static int cap_wt_learning_process_full_data(struct cap_learning *cl, return -ERANGE; } - delta_cap_uah = div64_s64(cl->learned_cap_uah * cc_soc_delta_pct, 100); - /* Learnt Capacity from end Battery SOC to 100 % */ + delta_batt_soc_msb = batt_soc_msb - cl->init_batt_soc_msb; + res_batt_soc_msb = FULL_SOC_RAW - batt_soc_msb; + /* Learnt Capacity from end Battery SOC MSB to FULL_SOC_RAW */ res_cap_uah = div64_s64(cl->learned_cap_uah * - (100 - batt_soc_pct), 100); - total_cap_uah = cl->init_cap_uah + delta_cap_uah + res_cap_uah; + res_batt_soc_msb, FULL_SOC_RAW); + total_cap_uah = cl->init_cap_uah + cl->delta_cap_uah + res_cap_uah; /* * difference in capacity learnt in this * charge cycle and previous learnt capacity */ del_cap_uah = total_cap_uah - cl->learned_cap_uah; - /* Applying weight based on change in battery SOC */ - wt_learnt_cap_uah = div64_s64(del_cap_uah * delta_batt_soc_pct, - 100); + /* Applying weight based on change in battery SOC MSB */ + wt_learnt_cap_uah = div64_s64(del_cap_uah * delta_batt_soc_msb, + FULL_SOC_RAW); cl->final_cap_uah = cl->learned_cap_uah + wt_learnt_cap_uah; - pr_debug("cc_soc_delta_pct=%d total_cap_uah=%lld\n", - cc_soc_delta_pct, cl->final_cap_uah); + pr_debug("wt_learnt_cap_uah=%lld, del_cap_uah=%lld\n", + wt_learnt_cap_uah, del_cap_uah); + pr_debug("init_cap_uah=%lld, total_cap_uah=%lld, res_cap_uah=%lld, delta_cap_uah=%lld\n", + cl->init_cap_uah, cl->final_cap_uah, + res_cap_uah, cl->delta_cap_uah); return 0; } @@ -425,8 +429,9 @@ static int cap_wt_learning_process_full_data(struct cap_learning *cl, static int cap_learning_process_full_data(struct cap_learning *cl, int batt_soc_msb) { - int rc, cc_soc_sw, cc_soc_delta_pct, delta_batt_soc_pct, batt_soc_pct; - int64_t delta_cap_uah; + int rc, cc_soc_sw, cc_soc_delta_pct, delta_batt_soc_pct, batt_soc_pct, + cc_soc_fraction; + int64_t cc_soc_cap_uah, cc_soc_fraction_uah; rc = cl->get_cc_soc(cl->data, &cc_soc_sw); if (rc < 0) { @@ -437,13 +442,18 @@ static int cap_learning_process_full_data(struct cap_learning *cl, batt_soc_pct = DIV_ROUND_CLOSEST(batt_soc_msb * 100, FULL_SOC_RAW); delta_batt_soc_pct = batt_soc_pct - cl->init_batt_soc; cc_soc_delta_pct = - div64_s64((int64_t)(cc_soc_sw - cl->init_cc_soc_sw) * 100, - cl->cc_soc_max); + div_s64_rem((int64_t)(cc_soc_sw - cl->init_cc_soc_sw) * 100, + cl->cc_soc_max, &cc_soc_fraction); + cc_soc_fraction_uah = div64_s64(cl->learned_cap_uah * + cc_soc_fraction, (int64_t)cl->cc_soc_max * 100); + cc_soc_cap_uah = div64_s64(cl->learned_cap_uah * cc_soc_delta_pct, 100); + cl->delta_cap_uah = cc_soc_cap_uah + cc_soc_fraction_uah; + pr_debug("cc_soc_delta_pct=%d, cc_soc_cap_uah=%lld, cc_soc_fraction_uah=%lld\n", + cc_soc_delta_pct, cc_soc_cap_uah, cc_soc_fraction_uah); if (cl->dt.cl_wt_enable) { - rc = cap_wt_learning_process_full_data(cl, batt_soc_pct, - cc_soc_delta_pct, - delta_batt_soc_pct); + rc = cap_wt_learning_process_full_data(cl, delta_batt_soc_pct, + batt_soc_msb); return rc; } @@ -453,8 +463,7 @@ static int cap_learning_process_full_data(struct cap_learning *cl, return -ERANGE; } - delta_cap_uah = div64_s64(cl->learned_cap_uah * cc_soc_delta_pct, 100); - cl->final_cap_uah = cl->init_cap_uah + delta_cap_uah; + cl->final_cap_uah = cl->init_cap_uah + cl->delta_cap_uah; pr_debug("Current cc_soc=%d cc_soc_delta_pct=%d total_cap_uah=%lld\n", cc_soc_sw, cc_soc_delta_pct, cl->final_cap_uah); return 0; @@ -509,6 +518,7 @@ static int cap_learning_begin(struct cap_learning *cl, u32 batt_soc) cl->init_cc_soc_sw = cc_soc_sw; cl->init_batt_soc = batt_soc_pct; + cl->init_batt_soc_msb = batt_soc_msb; pr_debug("Capacity learning started @ battery SOC %d init_cc_soc_sw:%d\n", batt_soc_msb, cl->init_cc_soc_sw); out: diff --git a/drivers/power/supply/qcom/fg-alg.h b/drivers/power/supply/qcom/fg-alg.h index ce62199a93f4..c7dae87e9a31 100644 --- a/drivers/power/supply/qcom/fg-alg.h +++ b/drivers/power/supply/qcom/fg-alg.h @@ -57,10 +57,12 @@ struct cap_learning { int init_cc_soc_sw; int cc_soc_max; int init_batt_soc; + int init_batt_soc_msb; int64_t nom_cap_uah; int64_t init_cap_uah; int64_t final_cap_uah; int64_t learned_cap_uah; + int64_t delta_cap_uah; bool active; struct mutex lock; struct cl_params dt; -- GitLab From 1e72609e666f639b1276401cce3a9c34832b1950 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Fri, 11 Jan 2019 14:01:30 +0530 Subject: [PATCH 0854/1286] ARM: dts: msm: Disable S1 for USB on Trinket Since S1 is not enabled for IPA, SMMU faults are seen for transactions between IPA and USB. Hence disable S1 for USB. Change-Id: I13d5447069df2615673ed60d47737c9e756c3f27 Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-usb.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index 6f0247706c10..ce6da358228b 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -21,7 +21,6 @@ reg = <0x4e00000 0x100000>; reg-names = "core_base"; - iommus = <&apps_smmu 0x100 0x0>; #address-cells = <1>; #size-cells = <1>; ranges; -- GitLab From 6976cb5697c36870fcc639cc54d90f86133a7eaa Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Thu, 10 Jan 2019 08:47:20 +0530 Subject: [PATCH 0855/1286] defconfig: msm: Disable ETM in the trinket perf config Disable ETM in the perf defconfig to avoid power/perf issues. Change-Id: I367840100f635b7ec793a827dbbb18b91c447c22 Signed-off-by: Mao Jinlong --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..23ada991455c 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -589,7 +589,6 @@ CONFIG_IPC_LOGGING=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y CONFIG_CORESIGHT_STM=y CONFIG_CORESIGHT_CTI=y -- GitLab From 4de2c084e727c27aeec0fedd047a6b500eca684d Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 11 Jan 2019 15:47:30 +0530 Subject: [PATCH 0856/1286] drivers: iio: adc: Update check for PMIC revid in VADC probe Update check for value of PMIC revid returned to avoid null pointer dereference. Change-Id: I2fadae8dbf9541dd40ea4896e656b7edeccc37d2 Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-spmi-adc5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index d8f2801cf9d2..95bd8714c546 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -1007,7 +1007,7 @@ static int adc_probe(struct platform_device *pdev) revid_dev_node = of_parse_phandle(node, "qcom,pmic-revid", 0); if (revid_dev_node) { pmic_rev_id = get_revid_data(revid_dev_node); - if (!(IS_ERR(pmic_rev_id))) + if (!(IS_ERR_OR_NULL(pmic_rev_id))) skip_usb_wa = skip_usb_in_wa(pmic_rev_id); else { pr_err("Unable to get revid\n"); -- GitLab From 210a5d2047ee377c65327170c51539ca8c1685de Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Fri, 11 Jan 2019 17:24:09 +0530 Subject: [PATCH 0857/1286] clk: qcom: Add support for GCC_CAMSS_MICRO_BCR Camera driver needs GCC_CAMSS_MICRO_BCR so add support for the same. Change-Id: I3b7778ce654e298b4c325c8b35b2b11d5b755e9b Signed-off-by: Diptanshu Jamgade --- drivers/clk/qcom/gcc-trinket.c | 1 + include/dt-bindings/clock/qcom,gcc-trinket.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-trinket.c b/drivers/clk/qcom/gcc-trinket.c index 7537714650ae..0ec89b65695a 100644 --- a/drivers/clk/qcom/gcc-trinket.c +++ b/drivers/clk/qcom/gcc-trinket.c @@ -4407,6 +4407,7 @@ static const struct qcom_reset_map gcc_trinket_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, }; static struct clk_dfs gcc_dfs_clocks[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-trinket.h b/include/dt-bindings/clock/qcom,gcc-trinket.h index 5ade908c851c..5e5d53427c0c 100644 --- a/include/dt-bindings/clock/qcom,gcc-trinket.h +++ b/include/dt-bindings/clock/qcom,gcc-trinket.h @@ -237,5 +237,6 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 4 #define GCC_USB3_PHY_PRIM_SP0_BCR 5 #define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6 +#define GCC_CAMSS_MICRO_BCR 7 #endif -- GitLab From 5aaed2a01e8ea7f3347efe1cafc41261ae534ed3 Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Fri, 11 Jan 2019 17:29:55 +0530 Subject: [PATCH 0858/1286] defconfig: trinket: enable default key driver Enables default key driver which is needed for metadata encryption which encrypts the file system metadata. Change-Id: I0a43b3b275cddff13c377b1aae392c7532ecf38d Signed-off-by: Ramandeep Trehan --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..385f85b94f07 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -266,6 +266,7 @@ CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..7ff15c26cc09 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -277,6 +277,7 @@ CONFIG_SCSI_UFS_QCOM=y CONFIG_SCSI_UFSHCD_CMD_LOGGING=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y -- GitLab From 1e9f5e121c9ffeaecbb4a35ef847baf7e07f660f Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 11 Jan 2019 18:31:06 +0530 Subject: [PATCH 0859/1286] ARM: dts: msm: Modify the divclk frequency to 9.6Mhz for pm6125 Modify the divclk frequency from 19.2Mhz to 9.6Mhz as per the audio codec requirement for trinket. Change-Id: I06c06f760a1285acd46644bfd03da3529e266445 Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index ea684eacf411..ac8767944d94 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -136,7 +136,7 @@ clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; assigned-clocks = <&pm6125_clkdiv 1>; - assigned-clock-rates = <19200000>; + assigned-clock-rates = <9600000>; }; pm6125_gpios: pinctrl@c000 { -- GitLab From 0a5cdf453f987d3257ae0f799537e1962878ea3a Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Wed, 9 Jan 2019 19:10:21 +0530 Subject: [PATCH 0860/1286] ARM: dts: msm: fix minimum voltage value for L13A in sdmmagpie L13A is at higher voltage in display ON cases. This change adjusts minimum voltage value for L13A based on power grid specification. Change-Id: Ib488e672e71fcd28cc96c433fd40cd5859804897 Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index 5c40e6904004..35e82da1a3db 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -35,7 +35,7 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1696000>; + qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1904000>; qcom,supply-enable-load = <32000>; qcom,supply-disable-load = <80>; @@ -68,7 +68,7 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1696000>; + qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1904000>; qcom,supply-enable-load = <32000>; qcom,supply-disable-load = <80>; @@ -82,7 +82,7 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1696000>; + qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1904000>; qcom,supply-enable-load = <32000>; qcom,supply-disable-load = <80>; -- GitLab From 53957c19263b773e718d632070db4ae2f779b95c Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Fri, 11 Jan 2019 16:16:25 +0200 Subject: [PATCH 0861/1286] wil6210: add support for pci linkdown recovery Some platforms can notify on pci linkdown events. Add pci linkdown recovery flow, invoked upon pci linkdown notification. A new wil6210 status flag is added, wil_status_pci_linkdown, to prevent pci suspend / resume until the recovery is completed. After the pci link is recovered in the platform pci recovery callback the device is being reset and the the interface and AP mode states are restored. Change-Id: I6e0f434d52704120c683c51fb4d664eccca16f01 Signed-off-by: Maya Erez --- drivers/net/wireless/ath/wil6210/main.c | 32 +++-- drivers/net/wireless/ath/wil6210/pcie_bus.c | 110 +++++++++++++++++- drivers/net/wireless/ath/wil6210/pm.c | 6 + drivers/net/wireless/ath/wil6210/wil6210.h | 6 + .../net/wireless/ath/wil6210/wil_platform.h | 9 ++ 5 files changed, 152 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 33e42598e15b..5c307fe5088a 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -536,23 +536,16 @@ bool wil_is_recovery_blocked(struct wil6210_priv *wil) return no_fw_recovery && (wil->recovery_state == fw_recovery_pending); } -static void wil_fw_error_worker(struct work_struct *work) +void wil_fw_recovery(struct wil6210_priv *wil) { - struct wil6210_priv *wil = container_of(work, struct wil6210_priv, - fw_error_worker); struct net_device *ndev = wil->main_ndev; struct wireless_dev *wdev; - wil_dbg_misc(wil, "fw error worker\n"); - - if (!ndev || !(ndev->flags & IFF_UP)) { - wil_info(wil, "No recovery - interface is down\n"); - return; - } + wil_dbg_misc(wil, "fw recovery\n"); wdev = ndev->ieee80211_ptr; - /* increment @recovery_count if less then WIL6210_FW_RECOVERY_TO + /* increment @recovery_count if less than WIL6210_FW_RECOVERY_TO * passed since last recovery attempt */ if (time_is_after_jiffies(wil->last_fw_recovery + @@ -612,6 +605,22 @@ static void wil_fw_error_worker(struct work_struct *work) rtnl_unlock(); } +static void wil_fw_error_worker(struct work_struct *work) +{ + struct wil6210_priv *wil = container_of(work, struct wil6210_priv, + fw_error_worker); + struct net_device *ndev = wil->main_ndev; + + wil_dbg_misc(wil, "fw error worker\n"); + + if (!ndev || !(ndev->flags & IFF_UP)) { + wil_info(wil, "No recovery - interface is down\n"); + return; + } + + wil_fw_recovery(wil); +} + static int wil_find_free_ring(struct wil6210_priv *wil) { int i; @@ -724,6 +733,8 @@ int wil_priv_init(struct wil6210_priv *wil) INIT_WORK(&wil->wmi_event_worker, wmi_event_worker); INIT_WORK(&wil->fw_error_worker, wil_fw_error_worker); + INIT_WORK(&wil->pci_linkdown_recovery_worker, + wil_pci_linkdown_recovery_worker); INIT_LIST_HEAD(&wil->pending_wmi_ev); spin_lock_init(&wil->wmi_ev_lock); @@ -839,6 +850,7 @@ void wil_priv_deinit(struct wil6210_priv *wil) wil_set_recovery_state(wil, fw_recovery_idle); cancel_work_sync(&wil->fw_error_worker); + cancel_work_sync(&wil->pci_linkdown_recovery_worker); wmi_event_flush(wil); destroy_workqueue(wil->wq_service); destroy_workqueue(wil->wmi_wq); diff --git a/drivers/net/wireless/ath/wil6210/pcie_bus.c b/drivers/net/wireless/ath/wil6210/pcie_bus.c index a3b8558ac68a..bb0d0c85a7b2 100644 --- a/drivers/net/wireless/ath/wil6210/pcie_bus.c +++ b/drivers/net/wireless/ath/wil6210/pcie_bus.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -298,6 +298,108 @@ static int wil_platform_rop_fw_recovery(void *wil_handle) return 0; } +void wil_pci_linkdown_recovery_worker(struct work_struct *work) +{ + struct wil6210_priv *wil = container_of(work, struct wil6210_priv, + pci_linkdown_recovery_worker); + int rc, i; + struct wil6210_vif *vif; + struct net_device *ndev = wil->main_ndev; + + wil_dbg_misc(wil, "starting pci_linkdown recovery\n"); + + rtnl_lock(); + mutex_lock(&wil->mutex); + down_write(&wil->mem_lock); + clear_bit(wil_status_fwready, wil->status); + set_bit(wil_status_pci_linkdown, wil->status); + set_bit(wil_status_resetting, wil->status); + up_write(&wil->mem_lock); + + if (test_and_clear_bit(wil_status_napi_en, wil->status)) { + napi_disable(&wil->napi_rx); + napi_disable(&wil->napi_tx); + } + + mutex_unlock(&wil->mutex); + rtnl_unlock(); + + mutex_lock(&wil->mutex); + + mutex_lock(&wil->vif_mutex); + wil_ftm_stop_operations(wil); + wil_p2p_stop_radio_operations(wil); + wil_abort_scan_all_vifs(wil, false); + mutex_unlock(&wil->vif_mutex); + + for (i = 0; i < wil->max_vifs; i++) { + vif = wil->vifs[i]; + if (vif) { + cancel_work_sync(&vif->disconnect_worker); + wil6210_disconnect(vif, NULL, + WLAN_REASON_DEAUTH_LEAVING); + } + } + + wmi_event_flush(wil); + flush_workqueue(wil->wq_service); + flush_workqueue(wil->wmi_wq); + + /* Recover PCIe */ + if (wil->platform_ops.pci_linkdown_recovery) { + rc = wil->platform_ops.pci_linkdown_recovery( + wil->platform_handle); + if (rc) { + wil_err(wil, + "platform device failed to recover from pci linkdown (%d)\n", + rc); + mutex_unlock(&wil->mutex); + goto out; + } + } else { + wil_err(wil, + "platform device doesn't support pci_linkdown recovery\n"); + mutex_unlock(&wil->mutex); + goto out; + } + + if (!ndev || !(ndev->flags & IFF_UP)) { + wil_reset(wil, false); + mutex_unlock(&wil->mutex); + } else { + mutex_unlock(&wil->mutex); + wil->recovery_state = fw_recovery_pending; + wil_fw_recovery(wil); + } + +out: + return; +} + +static int wil_platform_rop_notify(void *wil_handle, + enum wil_platform_notif notif) +{ + struct wil6210_priv *wil = wil_handle; + + if (!wil) + return -EINVAL; + + switch (notif) { + case WIL_PLATFORM_NOTIF_PCI_LINKDOWN: + wil_info(wil, "received WIL_PLATFORM_NOTIF_PCI_LINKDOWN\n"); + clear_bit(wil_status_fwready, wil->status); + set_bit(wil_status_resetting, wil->status); + set_bit(wil_status_pci_linkdown, wil->status); + + schedule_work(&wil->pci_linkdown_recovery_worker); + break; + default: + break; + } + + return 0; +} + static void wil_platform_ops_uninit(struct wil6210_priv *wil) { if (wil->platform_ops.uninit) @@ -313,6 +415,7 @@ static int wil_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) const struct wil_platform_rops rops = { .ramdump = wil_platform_rop_ramdump, .fw_recovery = wil_platform_rop_fw_recovery, + .notify = wil_platform_rop_notify, }; u32 bar_size = pci_resource_len(pdev, 0); int dma_addr_size[] = {64, 48, 40, 32}; /* keep descending order */ @@ -560,6 +663,11 @@ static int wil6210_resume(struct device *dev, bool is_runtime) struct wil6210_priv *wil = pci_get_drvdata(pdev); bool keep_radio_on, active_ifaces; + if (test_bit(wil_status_pci_linkdown, wil->status)) { + wil_dbg_pm(wil, "ignore resume during pci linkdown\n"); + return 0; + } + wil_dbg_pm(wil, "resume: %s\n", is_runtime ? "runtime" : "system"); mutex_lock(&wil->vif_mutex); diff --git a/drivers/net/wireless/ath/wil6210/pm.c b/drivers/net/wireless/ath/wil6210/pm.c index 8b33b1391da0..7c34cd1836ec 100644 --- a/drivers/net/wireless/ath/wil6210/pm.c +++ b/drivers/net/wireless/ath/wil6210/pm.c @@ -101,6 +101,12 @@ int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime) goto out; } + if (test_bit(wil_status_pci_linkdown, wil->status)) { + wil_dbg_pm(wil, "Delay suspend during pci linkdown\n"); + rc = -EBUSY; + goto out; + } + mutex_lock(&wil->vif_mutex); active_ifaces = wil_has_active_ifaces(wil, true, false); mutex_unlock(&wil->vif_mutex); diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index 22cddb2f3df4..99a572f6a91e 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -661,6 +661,7 @@ enum { /* for wil6210_priv.status */ wil_status_suspending, /* suspend in progress */ wil_status_suspended, /* suspend completed, device is suspended */ wil_status_resuming, /* resume in progress */ + wil_status_pci_linkdown, /* pci linkdown occurred */ wil_status_last /* keep last */ }; @@ -1074,6 +1075,8 @@ struct wil6210_priv { u32 max_ampdu_size; struct wil_fw_stats_global fw_stats_global; + + struct work_struct pci_linkdown_recovery_worker; }; #define wil_to_wiphy(i) (i->wiphy) @@ -1365,6 +1368,9 @@ void wil_disconnect_worker(struct work_struct *work); void wil_init_txrx_ops(struct wil6210_priv *wil); +void wil_fw_recovery(struct wil6210_priv *wil); +void wil_pci_linkdown_recovery_worker(struct work_struct *work); + /* TX API */ int wil_ring_init_tx(struct wil6210_vif *vif, int cid); int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); diff --git a/drivers/net/wireless/ath/wil6210/wil_platform.h b/drivers/net/wireless/ath/wil6210/wil_platform.h index bca090611477..e31d132d0b85 100644 --- a/drivers/net/wireless/ath/wil6210/wil_platform.h +++ b/drivers/net/wireless/ath/wil6210/wil_platform.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014-2017 Qualcomm Atheros, Inc. + * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -27,6 +28,10 @@ enum wil_platform_event { WIL_PLATFORM_EVT_POST_SUSPEND = 4, }; +enum wil_platform_notif { + WIL_PLATFORM_NOTIF_PCI_LINKDOWN = 0, +}; + enum wil_platform_features { WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL = 0, WIL_PLATFORM_FEATURE_TRIPLE_MSI = 1, @@ -52,6 +57,7 @@ struct wil_platform_ops { int (*notify)(void *handle, enum wil_platform_event evt); int (*get_capa)(void *handle); void (*set_features)(void *handle, int features); + int (*pci_linkdown_recovery)(void *handle); }; /** @@ -63,10 +69,13 @@ struct wil_platform_ops { * @fw_recovery: start a firmware recovery process. Called as * part of a crash recovery process which may include other * related platform subsystems. + * @notify: get notifications from the Platform driver, such as + * pci linkdown */ struct wil_platform_rops { int (*ramdump)(void *wil_handle, void *buf, uint32_t size); int (*fw_recovery)(void *wil_handle); + int (*notify)(void *wil_handle, enum wil_platform_notif notif); }; /** -- GitLab From ff7669a17be34bd2c98b9745180fbbd13d4227f6 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 20 Nov 2018 15:23:47 -0800 Subject: [PATCH 0862/1286] msm: kgsl: Program QDSS registers to access via coresight interface On a6xx, we need to provide access to ISDB registers in QDSS register space for making an OpenCL profiling tool based on ISDB. This change maps the registers and provides support for accessing the registers through adb. Change-Id: I4da8c186d8216e4f00d2f87d9c1089772f00e584 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- .../devicetree/bindings/gpu/adreno.txt | 7 +- drivers/gpu/msm/a6xx_reg.h | 24 +++ drivers/gpu/msm/adreno.c | 23 +++ drivers/gpu/msm/adreno.h | 6 + drivers/gpu/msm/adreno_a6xx.c | 157 +++++++++++++++++- drivers/gpu/msm/adreno_coresight.c | 82 ++++----- 6 files changed, 257 insertions(+), 42 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt index 5e374fb6a9b1..e01dacc1a943 100644 --- a/Documentation/devicetree/bindings/gpu/adreno.txt +++ b/Documentation/devicetree/bindings/gpu/adreno.txt @@ -8,7 +8,8 @@ Required properties: - reg: Specifies the register base address and size, the shader memory base address and size (if it exists), base address and size of the CX_DBGC block (if it exists), and the base address and - size of the CX_MISC block (if it exists). + size of the CX_MISC block (if it exists), and the base address and size of + QDSS_GFX block (if it exists). - reg-names: Resource names used for the physical address of device registers and shader memory. "kgsl_3d0_reg_memory" gives the physical address and length of device registers while "kgsl_3d0_shader_memory" gives @@ -17,7 +18,9 @@ Required properties: registers used for various configuration options. If specified, "kgsl_3d0_cx_dbgc_memory" gives the physical address and length of the CX DBGC block. If specified, "cx_misc" gives - the physical address and length of the CX_MISC block. + the physical address and length of the CX_MISC block. If specified, + "qdss_gfx" provides the physical address and length of the + QDSS_GFX_DBG block. - interrupts: Interrupt mapping for GPU IRQ. - interrupt-names: String property to describe the name of the interrupt. - qcom,id: An integer used as an identification number for the device. diff --git a/drivers/gpu/msm/a6xx_reg.h b/drivers/gpu/msm/a6xx_reg.h index 17fa6d11e969..129cd2f6609c 100644 --- a/drivers/gpu/msm/a6xx_reg.h +++ b/drivers/gpu/msm/a6xx_reg.h @@ -532,6 +532,30 @@ #define A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0011c #define A6XX_RBBM_CLOCK_HYST_HLSQ 0x0011d +/* ISDB SP0 and SP1 registers */ +#define A6XX_SP0_ISDB_ISDB_EN 0xf40001 +#define A6XX_SP0_ISDB_ISDB_BRKPT_CFG 0xf40005 +#define A6XX_SP0_ISDB_ISDB_SHADER_ID_CFG 0xf40006 +#define A6XX_SP0_ISDB_ISDB_WAVE_ID_CFG 0xf40007 +#define A6XX_SP0_ISDB_ISDB_SAC_CFG 0xf40024 +#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_0 0xf40020 +#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_1 0xf40021 +#define A6XX_SP0_ISDB_ISDB_SAC_MASK_0 0xf40022 +#define A6XX_SP0_ISDB_ISDB_SAC_MASK_1 0xf40023 +#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_CTRL 0xf44000 +#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_X 0xf44001 +#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Y 0xf44002 +#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Z 0xf44003 +#define A6XX_SP1_ISDB_ISDB_EN 0xf40401 +#define A6XX_SP1_ISDB_ISDB_SAC_CFG 0xf40424 +#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_0 0xf40420 +#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_1 0xf40421 +#define A6XX_SP1_ISDB_ISDB_SAC_MASK_0 0xf40422 +#define A6XX_SP1_ISDB_ISDB_SAC_MASK_1 0xf40423 +#define A6XX_SP1_ISDB_ISDB_SHADER_ID_CFG 0xf40406 +#define A6XX_SP1_ISDB_ISDB_WAVE_ID_CFG 0xf40407 +#define A6XX_SP1_ISDB_ISDB_BRKPT_CFG 0xf40405 + /* DBGC_CFG registers */ #define A6XX_DBGC_CFG_DBGBUS_SEL_A 0x600 #define A6XX_DBGC_CFG_DBGBUS_SEL_B 0x601 diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 8062d8a181ea..7442cb02b902 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1240,6 +1240,26 @@ static void adreno_cx_misc_probe(struct kgsl_device *device) res->start, adreno_dev->cx_misc_len); } +static void adreno_qdss_dbg_probe(struct kgsl_device *device) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + struct resource *res; + + res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM, + "qdss_gfx"); + + if (res == NULL) + return; + + adreno_dev->qdss_gfx_base = res->start - device->reg_phys; + adreno_dev->qdss_gfx_len = resource_size(res); + adreno_dev->qdss_gfx_virt = devm_ioremap(device->dev, res->start, + resource_size(res)); + + if (adreno_dev->qdss_gfx_virt == NULL) + KGSL_DRV_WARN(device, "qdss_gfx ioremap failed\n"); +} + static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev) { unsigned int val; @@ -1375,6 +1395,9 @@ static int adreno_probe(struct platform_device *pdev) /* Probe for the optional CX_MISC block */ adreno_cx_misc_probe(device); + /*Probe for the optional QDSS_GFX_DBG block*/ + adreno_qdss_dbg_probe(device); + /* * qcom,iommu-secure-id is used to identify MMUs that can handle secure * content but that is only part of the story - the GPU also has to be diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index c51c19f8b3ca..12091fb8566b 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -443,6 +443,9 @@ enum gpu_coresight_sources { * @chipid: Chip ID specific to the GPU * @gmem_base: Base physical address of GMEM * @gmem_size: GMEM size + * @qdss_gfx_base: Base physical address of QDSS_GFX_DBG registers for Coresight + * @qdss_gfx_len: QDSS_GFX_DBG register size + * @qdss_gfx_virt: Pointer to virtual address of QDSS_GFX_DBG regiter * @cx_misc_len: Length of the CX MISC register block * @cx_misc_virt: Pointer where the CX MISC block is mapped * @gpucore: Pointer to the adreno_gpu_core structure @@ -522,6 +525,9 @@ struct adreno_device { unsigned int chipid; unsigned long gmem_base; unsigned long gmem_size; + unsigned long qdss_gfx_base; + unsigned long qdss_gfx_len; + void __iomem *qdss_gfx_virt; unsigned long cx_dbgc_base; unsigned int cx_dbgc_len; void __iomem *cx_dbgc_virt; diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index cc1ea393a3af..8f84834912d9 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -1784,6 +1784,75 @@ static struct adreno_irq a6xx_irq = { .mask = A6XX_INT_MASK, }; +static bool adreno_is_qdss_dbg_register(struct kgsl_device *device, + unsigned int offsetwords) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + + return adreno_dev->qdss_gfx_virt && + (offsetwords >= (adreno_dev->qdss_gfx_base >> 2)) && + (offsetwords < (adreno_dev->qdss_gfx_base + + adreno_dev->qdss_gfx_len) >> 2); +} + + +static void adreno_qdss_gfx_dbg_regread(struct kgsl_device *device, + unsigned int offsetwords, unsigned int *value) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + unsigned int qdss_gfx_offset; + + if (!adreno_is_qdss_dbg_register(device, offsetwords)) + return; + + qdss_gfx_offset = (offsetwords << 2) - adreno_dev->qdss_gfx_base; + *value = __raw_readl(adreno_dev->qdss_gfx_virt + qdss_gfx_offset); + + /* + * ensure this read finishes before the next one. + * i.e. act like normal readl() + */ + rmb(); +} + +static void adreno_qdss_gfx_dbg_regwrite(struct kgsl_device *device, + unsigned int offsetwords, unsigned int value) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + unsigned int qdss_gfx_offset; + + if (!adreno_is_qdss_dbg_register(device, offsetwords)) + return; + + qdss_gfx_offset = (offsetwords << 2) - adreno_dev->qdss_gfx_base; + trace_kgsl_regwrite(device, offsetwords, value); + + /* + * ensure previous writes post before this one, + * i.e. act like normal writel() + */ + wmb(); + __raw_writel(value, adreno_dev->qdss_gfx_virt + qdss_gfx_offset); +} + +static void adreno_gx_regread(struct kgsl_device *device, + unsigned int offsetwords, unsigned int *value) +{ + if (adreno_is_qdss_dbg_register(device, offsetwords)) + adreno_qdss_gfx_dbg_regread(device, offsetwords, value); + else + kgsl_regread(device, offsetwords, value); +} + +static void adreno_gx_regwrite(struct kgsl_device *device, + unsigned int offsetwords, unsigned int value) +{ + if (adreno_is_qdss_dbg_register(device, offsetwords)) + adreno_qdss_gfx_dbg_regwrite(device, offsetwords, value); + else + kgsl_regwrite(device, offsetwords, value); +} + static struct adreno_coresight_register a6xx_coresight_regs[] = { { A6XX_DBGC_CFG_DBGBUS_SEL_A }, { A6XX_DBGC_CFG_DBGBUS_SEL_B }, @@ -1837,6 +1906,28 @@ static struct adreno_coresight_register a6xx_coresight_regs[] = { { A6XX_DBGC_PERF_ATB_DRAIN_CMD }, { A6XX_DBGC_ECO_CNTL }, { A6XX_DBGC_AHB_DBG_CNTL }, + { A6XX_SP0_ISDB_ISDB_EN }, + { A6XX_SP0_ISDB_ISDB_SAC_CFG }, + { A6XX_SP0_ISDB_ISDB_SAC_ADDR_0 }, + { A6XX_SP0_ISDB_ISDB_SAC_ADDR_1 }, + { A6XX_SP0_ISDB_ISDB_SAC_MASK_0 }, + { A6XX_SP0_ISDB_ISDB_SAC_MASK_1 }, + { A6XX_SP0_ISDB_ISDB_SHADER_ID_CFG }, + { A6XX_SP0_ISDB_ISDB_WAVE_ID_CFG }, + { A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_CTRL }, + { A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_X }, + { A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Y }, + { A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Z }, + { A6XX_SP0_ISDB_ISDB_BRKPT_CFG }, + { A6XX_SP1_ISDB_ISDB_EN }, + { A6XX_SP1_ISDB_ISDB_SAC_CFG }, + { A6XX_SP1_ISDB_ISDB_SAC_ADDR_0 }, + { A6XX_SP1_ISDB_ISDB_SAC_ADDR_1 }, + { A6XX_SP1_ISDB_ISDB_SAC_MASK_0 }, + { A6XX_SP1_ISDB_ISDB_SAC_MASK_1 }, + { A6XX_SP1_ISDB_ISDB_SHADER_ID_CFG }, + { A6XX_SP1_ISDB_ISDB_WAVE_ID_CFG }, + { A6XX_SP1_ISDB_ISDB_BRKPT_CFG }, }; static struct adreno_coresight_register a6xx_coresight_regs_cx[] = { @@ -1948,6 +2039,46 @@ static ADRENO_CORESIGHT_ATTR(perf_atb_trig_intf_sel_1, static ADRENO_CORESIGHT_ATTR(perf_atb_drain_cmd, &a6xx_coresight_regs[49]); static ADRENO_CORESIGHT_ATTR(eco_cntl, &a6xx_coresight_regs[50]); static ADRENO_CORESIGHT_ATTR(ahb_dbg_cntl, &a6xx_coresight_regs[51]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_en, &a6xx_coresight_regs[52]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_cfg, &a6xx_coresight_regs[53]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_addr_0, + &a6xx_coresight_regs[54]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_addr_1, + &a6xx_coresight_regs[55]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_mask_0, + &a6xx_coresight_regs[56]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_sac_mask_1, + &a6xx_coresight_regs[57]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_shader_id_cfg, + &a6xx_coresight_regs[58]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_wave_id_cfg, + &a6xx_coresight_regs[59]); +static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_ctrl, + &a6xx_coresight_regs[60]); +static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_x, + &a6xx_coresight_regs[61]); +static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_y, + &a6xx_coresight_regs[62]); +static ADRENO_CORESIGHT_ATTR(hlsq_isdb_isdb_hlsq_isdb_cl_wgid_z, + &a6xx_coresight_regs[63]); +static ADRENO_CORESIGHT_ATTR(sp0_isdb_isdb_brkpt_cfg, &a6xx_coresight_regs[64]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_en, &a6xx_coresight_regs[65]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_cfg, &a6xx_coresight_regs[66]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_addr_0, + &a6xx_coresight_regs[67]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_addr_1, + &a6xx_coresight_regs[68]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_mask_0, + &a6xx_coresight_regs[69]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_sac_mask_1, + &a6xx_coresight_regs[70]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_shader_id_cfg, + &a6xx_coresight_regs[71]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_wave_id_cfg, + &a6xx_coresight_regs[72]); +static ADRENO_CORESIGHT_ATTR(sp1_isdb_isdb_brkpt_cfg, + &a6xx_coresight_regs[73]); + /*CX debug registers*/ static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_a, @@ -2108,6 +2239,28 @@ static struct attribute *a6xx_coresight_attrs[] = { &coresight_attr_perf_atb_drain_cmd.attr.attr, &coresight_attr_eco_cntl.attr.attr, &coresight_attr_ahb_dbg_cntl.attr.attr, + &coresight_attr_sp0_isdb_isdb_en.attr.attr, + &coresight_attr_sp0_isdb_isdb_sac_cfg.attr.attr, + &coresight_attr_sp0_isdb_isdb_sac_addr_0.attr.attr, + &coresight_attr_sp0_isdb_isdb_sac_addr_1.attr.attr, + &coresight_attr_sp0_isdb_isdb_sac_mask_0.attr.attr, + &coresight_attr_sp0_isdb_isdb_sac_mask_1.attr.attr, + &coresight_attr_sp0_isdb_isdb_shader_id_cfg.attr.attr, + &coresight_attr_sp0_isdb_isdb_wave_id_cfg.attr.attr, + &coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_ctrl.attr.attr, + &coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_x.attr.attr, + &coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_y.attr.attr, + &coresight_attr_hlsq_isdb_isdb_hlsq_isdb_cl_wgid_z.attr.attr, + &coresight_attr_sp0_isdb_isdb_brkpt_cfg.attr.attr, + &coresight_attr_sp1_isdb_isdb_en.attr.attr, + &coresight_attr_sp1_isdb_isdb_sac_cfg.attr.attr, + &coresight_attr_sp1_isdb_isdb_sac_addr_0.attr.attr, + &coresight_attr_sp1_isdb_isdb_sac_addr_1.attr.attr, + &coresight_attr_sp1_isdb_isdb_sac_mask_0.attr.attr, + &coresight_attr_sp1_isdb_isdb_sac_mask_1.attr.attr, + &coresight_attr_sp1_isdb_isdb_shader_id_cfg.attr.attr, + &coresight_attr_sp1_isdb_isdb_wave_id_cfg.attr.attr, + &coresight_attr_sp1_isdb_isdb_brkpt_cfg.attr.attr, NULL, }; @@ -2190,8 +2343,8 @@ static struct adreno_coresight a6xx_coresight = { .registers = a6xx_coresight_regs, .count = ARRAY_SIZE(a6xx_coresight_regs), .groups = a6xx_coresight_groups, - .read = kgsl_regread, - .write = kgsl_regwrite, + .read = adreno_gx_regread, + .write = adreno_gx_regwrite, }; static struct adreno_coresight a6xx_coresight_cx = { diff --git a/drivers/gpu/msm/adreno_coresight.c b/drivers/gpu/msm/adreno_coresight.c index 5eff50df196f..0ad075768b66 100644 --- a/drivers/gpu/msm/adreno_coresight.c +++ b/drivers/gpu/msm/adreno_coresight.c @@ -34,49 +34,53 @@ ssize_t adreno_coresight_show_register(struct device *dev, struct kgsl_device *device = dev_get_drvdata(dev->parent); struct adreno_device *adreno_dev; struct adreno_coresight_attr *cattr = TO_ADRENO_CORESIGHT_ATTR(attr); - bool is_cx; + struct adreno_gpudev *gpudev; + struct adreno_coresight *coresight; + int cs_id; if (device == NULL) return -EINVAL; adreno_dev = ADRENO_DEVICE(device); + gpudev = ADRENO_GPU_DEVICE(adreno_dev); + + cs_id = adreno_coresight_identify(dev_name(dev)); + + if (cs_id < 0) + return -ENODEV; + + coresight = gpudev->coresight[cs_id]; if (cattr->reg == NULL) return -EINVAL; - is_cx = adreno_is_cx_dbgc_register(device, cattr->reg->offset); /* * Return the current value of the register if coresight is enabled, * otherwise report 0 */ mutex_lock(&device->mutex); - if ((is_cx && test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv)) - || (!is_cx && test_bit(ADRENO_DEVICE_CORESIGHT, - &adreno_dev->priv))) { - /* - * If the device isn't power collapsed read the actual value - * from the hardware - otherwise return the cached value - */ - - if (device->state == KGSL_STATE_ACTIVE || - device->state == KGSL_STATE_NAP) { - if (!kgsl_active_count_get(device)) { - if (!is_cx) - kgsl_regread(device, cattr->reg->offset, - &cattr->reg->value); - else - adreno_cx_dbgc_regread(device, - cattr->reg->offset, - &cattr->reg->value); - kgsl_active_count_put(device); - } - } + if (!(test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv) + || test_bit(ADRENO_DEVICE_CORESIGHT, + &adreno_dev->priv))) + goto out; + /* + * If the device isn't power collapsed read the actual value + * from the hardware - otherwise return the cached value + */ - val = cattr->reg->value; + if (device->state == KGSL_STATE_ACTIVE || + device->state == KGSL_STATE_NAP) { + if (!kgsl_active_count_get(device)) { + coresight->read(device, + cattr->reg->offset, &cattr->reg->value); + kgsl_active_count_put(device); + } } - mutex_unlock(&device->mutex); +out: + val = cattr->reg->value; + mutex_unlock(&device->mutex); return snprintf(buf, PAGE_SIZE, "0x%X\n", val); } @@ -86,18 +90,26 @@ ssize_t adreno_coresight_store_register(struct device *dev, struct kgsl_device *device = dev_get_drvdata(dev->parent); struct adreno_device *adreno_dev; struct adreno_coresight_attr *cattr = TO_ADRENO_CORESIGHT_ATTR(attr); + struct adreno_gpudev *gpudev; + struct adreno_coresight *coresight; unsigned long val; - int ret, is_cx; + int ret, cs_id; if (device == NULL) return -EINVAL; adreno_dev = ADRENO_DEVICE(device); + gpudev = ADRENO_GPU_DEVICE(adreno_dev); if (cattr->reg == NULL) return -EINVAL; - is_cx = adreno_is_cx_dbgc_register(device, cattr->reg->offset); + cs_id = adreno_coresight_identify(dev_name(dev)); + + if (cs_id < 0) + return -ENODEV; + + coresight = gpudev->coresight[cs_id]; ret = kstrtoul(buf, 0, &val); if (ret) @@ -106,9 +118,9 @@ ssize_t adreno_coresight_store_register(struct device *dev, mutex_lock(&device->mutex); /* Ignore writes while coresight is off */ - if (!((is_cx && test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv)) - || (!is_cx && test_bit(ADRENO_DEVICE_CORESIGHT, - &adreno_dev->priv)))) + if (!(test_bit(ADRENO_DEVICE_CORESIGHT_CX, &adreno_dev->priv) + || test_bit(ADRENO_DEVICE_CORESIGHT, + &adreno_dev->priv))) goto out; cattr->reg->value = val; @@ -117,14 +129,8 @@ ssize_t adreno_coresight_store_register(struct device *dev, if (device->state == KGSL_STATE_ACTIVE || device->state == KGSL_STATE_NAP) { if (!kgsl_active_count_get(device)) { - if (!is_cx) - kgsl_regwrite(device, cattr->reg->offset, - cattr->reg->value); - else - adreno_cx_dbgc_regwrite(device, - cattr->reg->offset, - cattr->reg->value); - + coresight->write(device, + cattr->reg->offset, cattr->reg->value); kgsl_active_count_put(device); } } -- GitLab From b9847def0d392e59a2a867439939f3108679a906 Mon Sep 17 00:00:00 2001 From: Shaikh Shadul Date: Thu, 10 Jan 2019 19:05:58 +0530 Subject: [PATCH 0863/1286] ARM: dts: msm: add sensors device node for trinket Add sensors device node for exercising sensors use case and time syncing with ADSP clock. Change-Id: I1af3d62a88d20a59b97e62247518e34b914d5e76 Signed-off-by: Shaikh Shadul --- arch/arm64/boot/dts/qcom/trinket.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 672384504d8f..8d9870738086 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2131,6 +2131,11 @@ compatible = "qcom,cx-ipeak-v2"; reg = <0x3ed000 0xc00c>; }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + }; }; #include "pmi632.dtsi" -- GitLab From 93f84934290b22de7e3ce93d45a10672b32b064b Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 3 Jan 2019 14:33:11 +0530 Subject: [PATCH 0864/1286] ARM: dts: msm: Configure cx ipeak for video for TRINKET The cx ipeak configuration provides the threshold frequency. Video driver updates a register to notify about it being running at or beyond the threshold frequency. CRs-Fixed: 2370730 Change-Id: I50706a855877c0d3db15c2059e12227171348e5f Signed-off-by: Vikash Garodia --- arch/arm64/boot/dts/qcom/trinket.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 672384504d8f..fbe7a6d3e873 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2414,5 +2414,10 @@ }; }; +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; + qcom,clock-freq-threshold = <460000000>; +}; + #include "trinket-audio.dtsi" #include "trinket-thermal.dtsi" -- GitLab From 6f6113f081fadf9d346a2fbc3df160f56b9f0107 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Thu, 3 Jan 2019 17:23:05 -0800 Subject: [PATCH 0865/1286] defconfig: sdxprairie: enable MHI host stack for sdxprairie chipset MHI host driver allows users to communicate to MHI compatible devices over PCIe bus. CRs-Fixed: 2378639 Change-Id: I805b7451edf7cdab561e1e624a6197f297037cc2 Signed-off-by: Sujeev Dias --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 06757e3b2072..55138258021d 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -161,6 +161,8 @@ CONFIG_RFKILL=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index ea92f25481b0..6744c4203992 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -148,6 +148,9 @@ CONFIG_RFKILL=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y -- GitLab From e653f0f29af81b6e3f01b645ac01d56e0c76d8a7 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 9 Jan 2019 21:56:36 -0500 Subject: [PATCH 0866/1286] msm: ipa: create debugfs root during pre-init Create debugfs root for IPA during driver pre-init since the ethernet offload subsystem init need to create sub-directories under it. CRs-Fixed: 2304918 Change-Id: Id2f2e43ae23d0cacb8c4d2bafd219cffbaf50774 Signed-off-by: Jinesh K. Jayakumar --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 4 +++- drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c | 23 +++++++++++++------ drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 5 ++-- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index d272026b4efd..2fbaa10eadd0 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -4901,7 +4901,7 @@ static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p, ipa3_register_panic_hdlr(); - ipa3_debugfs_init(); + ipa3_debugfs_post_init(); mutex_lock(&ipa3_ctx->lock); ipa3_ctx->ipa_initialization_complete = true; @@ -5649,6 +5649,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, goto fail_device_create; } + ipa3_debugfs_pre_init(); + /* Create a wakeup source. */ wakeup_source_init(&ipa3_ctx->w_lock, "IPA_WS"); spin_lock_init(&ipa3_ctx->wakelock_ref_cnt.spinlock); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c index ab742dd9ae5d..f09f8585dd1f 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2272,16 +2272,24 @@ static const struct ipa3_debugfs_file debugfs_files[] = { } }; -void ipa3_debugfs_init(void) +void ipa3_debugfs_pre_init(void) +{ + dent = debugfs_create_dir("ipa", 0); + if (IS_ERR_OR_NULL(dent)) { + IPAERR("fail to create folder in debug_fs.\n"); + dent = NULL; + } +} + +void ipa3_debugfs_post_init(void) { const size_t debugfs_files_num = sizeof(debugfs_files) / sizeof(struct ipa3_debugfs_file); size_t i; struct dentry *file; - dent = debugfs_create_dir("ipa", 0); - if (IS_ERR(dent)) { - IPAERR("fail to create folder in debug_fs.\n"); + if (IS_ERR_OR_NULL(dent)) { + IPAERR("debugs root not created\n"); return; } @@ -2358,7 +2366,7 @@ void ipa3_debugfs_init(void) void ipa3_debugfs_remove(void) { - if (IS_ERR(dent)) { + if (dent == NULL) { IPAERR("Debugfs:folder was not created.\n"); return; } @@ -2376,6 +2384,7 @@ struct dentry *ipa_debugfs_get_root(void) EXPORT_SYMBOL(ipa_debugfs_get_root); #else /* !CONFIG_DEBUG_FS */ -void ipa3_debugfs_init(void) {} +void ipa3_debugfs_pre_init(void) {} +void ipa3_debugfs_post_init(void) {} void ipa3_debugfs_remove(void) {} #endif diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index bb3272770f65..643719c2fd4c 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2434,7 +2434,8 @@ int ipa3_generate_hw_rule(enum ipa_ip_type ip, int ipa3_init_hw(void); struct ipa3_rt_tbl *__ipa3_find_rt_tbl(enum ipa_ip_type ip, const char *name); int ipa3_set_single_ndp_per_mbim(bool enable); -void ipa3_debugfs_init(void); +void ipa3_debugfs_pre_init(void); +void ipa3_debugfs_post_init(void); void ipa3_debugfs_remove(void); void ipa3_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size); -- GitLab From 91110ff4ed6eadf47773f373570e11141d5eefa9 Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Fri, 11 Jan 2019 14:18:31 -0800 Subject: [PATCH 0867/1286] ARM: dts: msm: Include qcom,skip-init for apps smmu on sdxprairie In the case of no access control, HLOS ends up trampling over hypervisor registers as the hypervisor context banks are not already taken into account while computing the total number of non-secure context banks.Hence include qcom,skip-init property for apps smmu for sdxprairie to skip the context bank reset thereby preventing the hypervisor registers from being overwritten. Change-Id: Ia454ce6d2903ec1027c4bffe5b25d904532875bc Signed-off-by: Swathi Sridhar --- arch/arm64/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi index 65fee9dff61a..7185473263bd 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,6 +20,7 @@ <0x15022000 0x20>; reg-names = "base", "tcu-base"; #iommu-cells = <2>; + qcom,skip-init; qcom,use-3-lvl-tables; #global-interrupts = <1>; #size-cells = <1>; -- GitLab From 5755ad781efa9a22d4c38d32fea2ed93794d2a3d Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Tue, 18 Dec 2018 19:38:32 -0800 Subject: [PATCH 0868/1286] msm: camera: Validate packet params against cpu buffer length Modifying validate packet in cam utils and its callers to provide cpu buffer length which is used in validation of number of cmd buffers, io configs and patches. Change-Id: Ia180264b787bb8ab91154448809076d7c0c31e29 Signed-off-by: Mukund Madhusudan Atre --- .../msm/camera/cam_cdm/cam_cdm_virtual_core.c | 8 ++ .../msm/camera/cam_core/cam_context_utils.c | 17 +++ .../msm/camera/cam_core/cam_hw_mgr_intf.h | 2 + .../camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 17 ++- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 3 + .../msm/camera/cam_isp/cam_isp_context.c | 40 ++++-- .../cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 3 +- .../hw_utils/cam_isp_packet_parser.c | 15 ++- .../camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 8 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 13 +- .../cam_actuator/cam_actuator_core.c | 41 +++--- .../cam_csiphy/cam_csiphy_core.c | 33 +++-- .../cam_eeprom/cam_eeprom_core.c | 80 ++++++++++- .../cam_flash/cam_flash_core.c | 124 ++++++++++++------ .../cam_sensor_module/cam_ois/cam_ois_core.c | 44 ++++--- .../cam_sensor_module/cam_ois/cam_ois_core.h | 2 + .../cam_sensor/cam_sensor_core.c | 72 ++++++---- .../cam_sensor_utils/cam_sensor_util.c | 112 +++++++++++++++- .../cam_sensor_utils/cam_sensor_util.h | 3 +- .../msm/camera/cam_utils/cam_packet_util.c | 89 +++++++++++-- .../msm/camera/cam_utils/cam_packet_util.h | 5 +- 21 files changed, 571 insertions(+), 160 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_cdm/cam_cdm_virtual_core.c b/drivers/media/platform/msm/camera/cam_cdm/cam_cdm_virtual_core.c index 9021ecabb27c..5ea2a00b6092 100644 --- a/drivers/media/platform/msm/camera/cam_cdm/cam_cdm_virtual_core.c +++ b/drivers/media/platform/msm/camera/cam_cdm/cam_cdm_virtual_core.c @@ -118,6 +118,14 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, if ((!rc) && (vaddr_ptr) && (len) && (len >= cdm_cmd->cmd[i].offset)) { + + + if ((len - cdm_cmd->cmd[i].offset) <= + cdm_cmd->cmd[i].len) { + CAM_ERR(CAM_CDM, "Not enough buffer"); + rc = -EINVAL; + break; + } CAM_DBG(CAM_CDM, "hdl=%x vaddr=%pK offset=%d cmdlen=%d:%zu", cdm_cmd->cmd[i].bl_addr.mem_handle, diff --git a/drivers/media/platform/msm/camera/cam_core/cam_context_utils.c b/drivers/media/platform/msm/camera/cam_core/cam_context_utils.c index 1c17fc7720ca..a1b9e08e5821 100644 --- a/drivers/media/platform/msm/camera/cam_core/cam_context_utils.c +++ b/drivers/media/platform/msm/camera/cam_core/cam_context_utils.c @@ -303,6 +303,12 @@ int32_t cam_context_config_dev_to_hw( return rc; } + if ((len < sizeof(struct cam_packet)) || + (cmd->offset >= (len - sizeof(struct cam_packet)))) { + CAM_ERR(CAM_CTXT, "Not enough buf"); + return -EINVAL; + + } packet = (struct cam_packet *) ((uint8_t *)packet_addr + (uint32_t)cmd->offset); @@ -333,6 +339,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, uintptr_t packet_addr; struct cam_packet *packet; size_t len = 0; + size_t remain_len = 0; int32_t i = 0, j = 0; if (!ctx || !cmd) { @@ -378,6 +385,15 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, goto free_req; } + remain_len = len; + if ((len < sizeof(struct cam_packet)) || + ((size_t)cmd->offset >= len - sizeof(struct cam_packet))) { + CAM_ERR(CAM_CTXT, "invalid buff length: %zu or offset", len); + rc = -EINVAL; + goto free_cpu_buf; + } + + remain_len -= (size_t)cmd->offset; packet = (struct cam_packet *) ((uint8_t *)packet_addr + (uint32_t)cmd->offset); @@ -395,6 +411,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, /* preprocess the configuration */ memset(&cfg, 0, sizeof(cfg)); cfg.packet = packet; + cfg.remain_len = remain_len; cfg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; cfg.max_hw_update_entries = CAM_CTX_CFG_MAX; cfg.num_hw_update_entries = req->num_hw_update_entries; diff --git a/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h index fd30f115cc0c..b5d49de43e8e 100644 --- a/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h +++ b/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h @@ -153,6 +153,7 @@ struct cam_hw_mgr_dump_pf_data { * struct cam_hw_prepare_update_args - Payload for prepare command * * @packet: CSL packet from user mode driver + * @remain_len Remaining length of CPU buffer after config offset * @ctxt_to_hw_map: HW context from the acquire * @max_hw_update_entries: Maximum hardware update entries supported * @hw_update_entries: Actual hardware update configuration (returned) @@ -169,6 +170,7 @@ struct cam_hw_mgr_dump_pf_data { */ struct cam_hw_prepare_update_args { struct cam_packet *packet; + size_t remain_len; void *ctxt_to_hw_map; uint32_t max_hw_update_entries; struct cam_hw_update_entry *hw_update_entries; diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index 645249cb58a9..72ec78fb2059 100644 --- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -30,7 +30,8 @@ static struct cam_fd_hw_mgr g_fd_hw_mgr; -static int cam_fd_mgr_util_packet_validate(struct cam_packet *packet) +static int cam_fd_mgr_util_packet_validate(struct cam_packet *packet, + size_t remain_len) { struct cam_cmd_buf_desc *cmd_desc = NULL; int i, rc; @@ -50,7 +51,7 @@ static int cam_fd_mgr_util_packet_validate(struct cam_packet *packet) packet->patch_offset, packet->num_patches, packet->kmd_cmd_buf_offset, packet->kmd_cmd_buf_index); - if (cam_packet_util_validate_packet(packet)) { + if (cam_packet_util_validate_packet(packet, remain_len)) { CAM_ERR(CAM_FD, "invalid packet:%d %d %d %d %d", packet->kmd_cmd_buf_index, packet->num_cmd_buf, packet->cmd_buf_offset, @@ -611,7 +612,14 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, rc); goto rel_cpu_buf; } - + if (io_cfg[i].offsets[plane] >= size) { + CAM_ERR(CAM_FD, + "Invalid cpu buf %d %d %d", + io_cfg[i].direction, + io_cfg[i].resource_type, plane); + rc = -EINVAL; + goto rel_cpu_buf; + } cpu_addr[plane] += io_cfg[i].offsets[plane]; } @@ -1592,7 +1600,8 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, goto error; } - rc = cam_fd_mgr_util_packet_validate(prepare->packet); + rc = cam_fd_mgr_util_packet_validate(prepare->packet, + prepare->remain_len); if (rc) { CAM_ERR(CAM_FD, "Error in packet validation %d", rc); goto error; diff --git a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 1ba78fb9a8a7..fbbbbc76e93e 100644 --- a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -3974,6 +3974,9 @@ static int cam_icp_mgr_prepare_hw_update(void *hw_mgr_priv, packet = prepare_args->packet; + if (cam_packet_util_validate_packet(packet, prepare_args->remain_len)) + return -EINVAL; + rc = cam_icp_mgr_pkt_validation(packet); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c index 320beb7bd946..03e3f0703586 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c @@ -129,6 +129,8 @@ static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) size_t len = 0; uint32_t *buf_addr; uint32_t *buf_start, *buf_end; + size_t remain_len = 0; + bool need_put = false; for (i = 0; i < req_isp->num_cfg; i++) { rc = cam_packet_util_get_cmd_mem_addr( @@ -138,20 +140,31 @@ static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) "Failed to get_cmd_mem_addr, rc=%d", rc); } else { - buf_start = (uint32_t *)((uint8_t *) buf_addr + - req_isp->cfg[i].offset); - buf_end = (uint32_t *)((uint8_t *) buf_start + - req_isp->cfg[i].len - 1); - if (len < (buf_end - buf_start + 1)) { - CAM_ERR(CAM_ISP, - "Invalid len %lld buf_start-end=%d", - len, (buf_end - buf_start + 1)); + if (req_isp->cfg[i].offset >= len) { + CAM_ERR(CAM_ISP, "Invalid offset"); + need_put = true; + goto put; + } + remain_len = len - req_isp->cfg[i].offset; + + if (req_isp->cfg[i].len > remain_len) { + CAM_ERR(CAM_ISP, "Invalid offset"); + need_put = true; + } +put: + if (need_put) { if (cam_mem_put_cpu_buf(req_isp->cfg[i].handle)) CAM_WARN(CAM_ISP, "Failed to put cpu buf: 0x%x", req_isp->cfg[i].handle); + need_put = false; continue; } + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + req_isp->cfg[i].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + req_isp->cfg[i].len - 1); cam_cdm_util_dump_cmd_buf(buf_start, buf_end); if (cam_mem_put_cpu_buf(req_isp->cfg[i].handle)) CAM_WARN(CAM_ISP, "Failed to put cpu buf: 0x%x", @@ -2557,6 +2570,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( uintptr_t packet_addr; struct cam_packet *packet; size_t len = 0; + size_t remain_len = 0; struct cam_hw_prepare_update_args cfg; struct cam_req_mgr_add_request add_req; struct cam_isp_context *ctx_isp = @@ -2590,6 +2604,15 @@ static int __cam_isp_ctx_config_dev_in_top_state( goto free_req; } + remain_len = len; + if ((len < sizeof(struct cam_packet)) || + ((size_t)cmd->offset >= len - sizeof(struct cam_packet))) { + CAM_ERR(CAM_ISP, "invalid buff length: %zu or offset", len); + rc = -EINVAL; + goto free_cpu_buf; + } + + remain_len -= (size_t)cmd->offset; packet = (struct cam_packet *)(packet_addr + (uint32_t)cmd->offset); CAM_DBG(CAM_ISP, "pack_handle %llx", cmd->packet_handle); CAM_DBG(CAM_ISP, "packet address is 0x%zx", packet_addr); @@ -2612,6 +2635,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( /* preprocess the configuration */ memset(&cfg, 0, sizeof(cfg)); cfg.packet = packet; + cfg.remain_len = remain_len; cfg.ctxt_to_hw_map = ctx_isp->hw_ctx; cfg.max_hw_update_entries = CAM_ISP_CTX_CFG_MAX; cfg.hw_update_entries = req_isp->cfg; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 7488dd09882b..1f896e56604a 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -3636,7 +3636,8 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, ctx = (struct cam_ife_hw_mgr_ctx *) prepare->ctxt_to_hw_map; hw_mgr = (struct cam_ife_hw_mgr *)hw_mgr_priv; - rc = cam_packet_util_validate_packet(prepare->packet); + rc = cam_packet_util_validate_packet(prepare->packet, + prepare->remain_len); if (rc) return rc; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index f4ef12f5fdee..b30a1f797748 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -105,7 +105,7 @@ static int cam_isp_update_dual_config( struct cam_isp_hw_dual_isp_update_args dual_isp_update_args; uint32_t outport_id; uint32_t ports_plane_idx; - size_t len = 0; + size_t len = 0, remain_len = 0; uint32_t *cpu_addr; uint32_t i, j; @@ -117,9 +117,22 @@ static int cam_isp_update_dual_config( if (rc) return rc; + if ((len < sizeof(struct cam_isp_dual_config)) || + (cmd_desc->offset >= + (len - sizeof(struct cam_isp_dual_config)))) { + CAM_ERR(CAM_UTIL, "not enough buffer provided"); + return -EINVAL; + } + remain_len = len - cmd_desc->offset; cpu_addr += (cmd_desc->offset / 4); dual_config = (struct cam_isp_dual_config *)cpu_addr; + if ((dual_config->num_ports * + sizeof(struct cam_isp_dual_stripe_config)) > + (remain_len - offsetof(struct cam_isp_dual_config, stripes))) { + CAM_ERR(CAM_UTIL, "not enough buffer for all the dual configs"); + return -EINVAL; + } for (i = 0; i < dual_config->num_ports; i++) { if (i >= CAM_ISP_IFE_OUT_RES_MAX) { diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 66dc18dab185..1bf1db8cf77b 100644 --- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -279,6 +279,12 @@ static int cam_jpeg_insert_cdm_change_base( "unable to get src buf info for cmd buf: %d", rc); return rc; } + + if (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset >= + ch_base_len) { + CAM_ERR(CAM_JPEG, "Not enough buf"); + return -EINVAL; + } CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d", (void *)iova_addr, ch_base_len, config_args->hw_update_entries[CAM_JPEG_CHBASE].offset); @@ -726,7 +732,7 @@ static int cam_jpeg_mgr_prepare_hw_update(void *hw_mgr_priv, return -EINVAL; } - rc = cam_packet_util_validate_packet(packet); + rc = cam_packet_util_validate_packet(packet, prepare_args->remain_len); if (rc) { CAM_ERR(CAM_JPEG, "invalid packet %d", rc); return rc; diff --git a/drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c index 0c236462b7f5..e037a29bb9cd 100644 --- a/drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -83,7 +83,8 @@ static int cam_lrme_mgr_util_get_device(struct cam_lrme_hw_mgr *hw_mgr, return 0; } -static int cam_lrme_mgr_util_packet_validate(struct cam_packet *packet) +static int cam_lrme_mgr_util_packet_validate(struct cam_packet *packet, + size_t remain_len) { struct cam_cmd_buf_desc *cmd_desc = NULL; int i, rc; @@ -105,7 +106,7 @@ static int cam_lrme_mgr_util_packet_validate(struct cam_packet *packet) packet->patch_offset, packet->num_patches, packet->kmd_cmd_buf_offset, packet->kmd_cmd_buf_index); - if (cam_packet_util_validate_packet(packet)) { + if (cam_packet_util_validate_packet(packet, remain_len)) { CAM_ERR(CAM_LRME, "invalid packet:%d %d %d %d %d", packet->kmd_cmd_buf_index, packet->num_cmd_buf, packet->cmd_buf_offset, @@ -186,6 +187,12 @@ static int cam_lrme_mgr_util_prepare_io_buffer(int32_t iommu_hdl, return -ENOMEM; } + if ((size_t)io_cfg[i].offsets[plane] >= size) { + CAM_ERR(CAM_LRME, "Invalid plane offset: %zu", + (size_t)io_cfg[i].offsets[plane]); + return -EINVAL; + } + io_addr[plane] += io_cfg[i].offsets[plane]; CAM_DBG(CAM_LRME, "IO Address[%d][%d] : %llu", @@ -841,7 +848,7 @@ static int cam_lrme_mgr_hw_prepare_update(void *hw_mgr_priv, goto error; } - rc = cam_lrme_mgr_util_packet_validate(args->packet); + rc = cam_lrme_mgr_util_packet_validate(args->packet, args->remain_len); if (rc) { CAM_ERR(CAM_LRME, "Error in packet validation %d", rc); goto error; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c index 2e533981edf7..f6f562c79093 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -17,6 +17,7 @@ #include "cam_trace.h" #include "cam_res_mgr_api.h" #include "cam_common_util.h" +#include "cam_packet_util.h" int32_t cam_actuator_construct_default_power_setting( struct cam_sensor_power_ctrl_t *power_info) @@ -214,12 +215,12 @@ static int32_t cam_actuator_i2c_modes_util( } int32_t cam_actuator_slaveInfo_pkt_parser(struct cam_actuator_ctrl_t *a_ctrl, - uint32_t *cmd_buf) + uint32_t *cmd_buf, size_t len) { int32_t rc = 0; struct cam_cmd_i2c_info *i2c_info; - if (!a_ctrl || !cmd_buf) { + if (!a_ctrl || !cmd_buf || (len < sizeof(struct cam_cmd_i2c_info))) { CAM_ERR(CAM_ACTUATOR, "Invalid Args"); return -EINVAL; } @@ -413,7 +414,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, int32_t i = 0; uint32_t total_cmd_buf_in_bytes = 0; size_t len_of_buff = 0; - size_t remaining_len_of_buff = 0; + size_t remain_len = 0; uint32_t *offset = NULL; uint32_t *cmd_buf = NULL; uintptr_t generic_ptr; @@ -451,7 +452,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, return rc; } - remaining_len_of_buff = len_of_buff; + remain_len = len_of_buff; if ((sizeof(struct cam_packet) > len_of_buff) || ((size_t)config.offset >= len_of_buff - sizeof(struct cam_packet))) { @@ -462,19 +463,17 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, goto rel_pkt_buf; } - remaining_len_of_buff -= config.offset; + remain_len -= (size_t)config.offset; csl_packet = (struct cam_packet *) (generic_pkt_ptr + (uint32_t)config.offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_ACTUATOR, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_ACTUATOR, "Invalid packet params"); rc = -EINVAL; goto rel_pkt_buf; } - remaining_len_of_buff -= sizeof(struct cam_packet); CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", csl_packet->header.op_code); if ((csl_packet->header.op_code & 0xFFFFFF) != @@ -491,15 +490,6 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (csl_packet->header.request_id > a_ctrl->last_flush_req) a_ctrl->last_flush_req = 0; - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_ACTUATOR, - "InVal len: %zu", remaining_len_of_buff); - rc = -EINVAL; - goto rel_pkt_buf; - } - switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_ACTUATOR_PACKET_OPCODE_INIT: offset = (uint32_t *)&csl_packet->payload; @@ -522,6 +512,15 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "invalid cmd buf"); goto rel_cmd_buf; } + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > (len_of_buff - + sizeof(struct common_header)))) { + CAM_ERR(CAM_ACTUATOR, + "Invalid length for sensor cmd"); + rc = -EINVAL; + goto rel_cmd_buf; + } + remain_len = len_of_buff - cmd_desc[i].offset; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); cmm_hdr = (struct common_header *)cmd_buf; @@ -530,7 +529,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_DBG(CAM_ACTUATOR, "Received slave info buffer"); rc = cam_actuator_slaveInfo_pkt_parser( - a_ctrl, cmd_buf); + a_ctrl, cmd_buf, remain_len); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed to parse slave info: %d", rc); @@ -544,7 +543,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, rc = cam_sensor_update_power_settings( cmd_buf, total_cmd_buf_in_bytes, - power_info); + power_info, remain_len); if (rc) { CAM_ERR(CAM_ACTUATOR, "Failed:parse power settings: %d", diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 095665c03290..6d73edd9ff25 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -15,6 +15,8 @@ #include "cam_csiphy_dev.h" #include "cam_csiphy_soc.h" #include "cam_common_util.h" +#include "cam_packet_util.h" + #include #include @@ -165,7 +167,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, uint32_t *cmd_buf = NULL; struct cam_csiphy_info *cam_cmd_csiphy_info = NULL; size_t len; - size_t remaining_len_of_buff; + size_t remain_len; if (!cfg_dev || !csiphy_dev) { CAM_ERR(CAM_CSIPHY, "Invalid Args"); @@ -179,7 +181,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, return rc; } - remaining_len_of_buff = len; + remain_len = len; if ((sizeof(struct cam_packet) > len) || ((size_t)cfg_dev->offset >= len - sizeof(struct cam_packet))) { CAM_ERR(CAM_CSIPHY, @@ -189,24 +191,13 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, goto rel_pkt_buf; } - remaining_len_of_buff -= cfg_dev->offset; + remain_len -= (size_t)cfg_dev->offset; csl_packet = (struct cam_packet *) (generic_pkt_ptr + (uint32_t)cfg_dev->offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_CSIPHY, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); - rc = -EINVAL; - goto rel_pkt_buf; - } - - remaining_len_of_buff -= sizeof(struct cam_packet); - - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_CSIPHY, "InVal len: %zu", remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_CSIPHY, "Invalid packet params"); rc = -EINVAL; goto rel_pkt_buf; } @@ -223,6 +214,14 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, goto rel_pkt_buf; } + if ((len < sizeof(struct cam_csiphy_info)) || + (cmd_desc->offset > (len - sizeof(struct cam_csiphy_info)))) { + CAM_ERR(CAM_CSIPHY, + "Not enough buffer provided for cam_cisphy_info"); + rc = -EINVAL; + goto rel_pkt_buf; + } + cmd_buf = (uint32_t *)generic_ptr; cmd_buf += cmd_desc->offset / 4; cam_cmd_csiphy_info = (struct cam_csiphy_info *)cmd_buf; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index ab4ea76c23d7..b2ef241e4f44 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -18,6 +18,7 @@ #include "cam_eeprom_soc.h" #include "cam_debug_util.h" #include "cam_common_util.h" +#include "cam_packet_util.h" /** * cam_eeprom_read_memory() - read map data into buffer @@ -412,7 +413,7 @@ static int32_t cam_eeprom_update_slaveInfo(struct cam_eeprom_ctrl_t *e_ctrl, static int32_t cam_eeprom_parse_memory_map( struct cam_eeprom_memory_block_t *data, void *cmd_buf, int cmd_length, uint16_t *cmd_length_bytes, - int *num_map) + int *num_map, size_t remain_buf_len) { int32_t rc = 0; int32_t cnt = 0; @@ -426,8 +427,21 @@ static int32_t cam_eeprom_parse_memory_map( struct cam_cmd_i2c_continuous_rd *i2c_cont_rd = NULL; struct cam_cmd_conditional_wait *i2c_poll = NULL; struct cam_cmd_unconditional_wait *i2c_uncond_wait = NULL; + size_t validate_size = 0; generic_op_code = cmm_hdr->third_byte; + + if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR) + validate_size = sizeof(struct cam_cmd_i2c_random_wr); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD) + validate_size = sizeof(struct cam_cmd_i2c_continuous_rd); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_WAIT) + validate_size = sizeof(struct cam_cmd_unconditional_wait); + + if (remain_buf_len < validate_size) { + CAM_ERR(CAM_EEPROM, "not enough buffer"); + return -EINVAL; + } switch (cmm_hdr->cmd_type) { case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: i2c_random_wr = (struct cam_cmd_i2c_random_wr *)cmd_buf; @@ -534,6 +548,7 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, uint32_t *cmd_buf = NULL; uintptr_t generic_pkt_addr; size_t pkt_len = 0; + size_t remain_len = 0; uint32_t total_cmd_buf_in_bytes = 0; uint32_t processed_cmd_buf_in_bytes = 0; struct common_header *cmm_hdr = NULL; @@ -577,13 +592,40 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, rc = -EINVAL; goto rel_cmd_buf; } + + if ((pkt_len < sizeof(struct common_header)) || + (cmd_desc[i].offset > (pkt_len - + sizeof(struct common_header)))) { + CAM_ERR(CAM_EEPROM, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } + remain_len = pkt_len - cmd_desc[i].offset; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + + if (total_cmd_buf_in_bytes > remain_len) { + CAM_ERR(CAM_EEPROM, "Not enough buffer for command"); + rc = -EINVAL; + goto rel_cmd_buf; + } /* Loop through multiple cmd formats in one cmd buffer */ while (processed_cmd_buf_in_bytes < total_cmd_buf_in_bytes) { + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct common_header)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto rel_cmd_buf; + } cmm_hdr = (struct common_header *)cmd_buf; switch (cmm_hdr->cmd_type) { case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto rel_cmd_buf; + } /* Configure the following map slave address */ map[num_map + 1].saddr = i2c_info->slave_addr; rc = cam_eeprom_update_slaveInfo(e_ctrl, @@ -599,7 +641,9 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, case CAMERA_SENSOR_CMD_TYPE_PWR_DOWN: cmd_length_in_bytes = total_cmd_buf_in_bytes; rc = cam_sensor_update_power_settings(cmd_buf, - cmd_length_in_bytes, power_info); + cmd_length_in_bytes, power_info, + (remain_len - + processed_cmd_buf_in_bytes)); processed_cmd_buf_in_bytes += cmd_length_in_bytes; cmd_buf += cmd_length_in_bytes/ @@ -616,7 +660,9 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, rc = cam_eeprom_parse_memory_map( &e_ctrl->cal_data, cmd_buf, total_cmd_buf_in_bytes, - &cmd_length_in_bytes, &num_map); + &cmd_length_in_bytes, &num_map, + (remain_len - + processed_cmd_buf_in_bytes)); processed_cmd_buf_in_bytes += cmd_length_in_bytes; cmd_buf += cmd_length_in_bytes/sizeof(uint32_t); @@ -658,6 +704,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, uintptr_t buf_addr; size_t buf_size; uint8_t *read_buffer; + size_t remain_len = 0; io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) &csl_packet->payload + @@ -676,7 +723,13 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, rc); return rc; } + if (buf_size <= io_cfg->offsets[0]) { + CAM_ERR(CAM_EEPROM, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } + remain_len = buf_size - io_cfg->offsets[0]; CAM_DBG(CAM_EEPROM, "buf_addr : %pK, buf_size : %zu\n", (void *)buf_addr, buf_size); @@ -689,7 +742,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, } read_buffer += io_cfg->offsets[0]; - if (buf_size < e_ctrl->cal_data.num_data) { + if (remain_len < e_ctrl->cal_data.num_data) { CAM_ERR(CAM_EEPROM, "failed to copy, Invalid size"); rc = -EINVAL; @@ -733,6 +786,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) struct cam_config_dev_cmd dev_config; uintptr_t generic_pkt_addr; size_t pkt_len; + size_t remain_len = 0; struct cam_packet *csl_packet = NULL; struct cam_eeprom_soc_private *soc_private = (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; @@ -752,16 +806,28 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) return rc; } - if (dev_config.offset > pkt_len) { + remain_len = pkt_len; + if ((sizeof(struct cam_packet) > pkt_len) || + ((size_t)dev_config.offset >= pkt_len - + sizeof(struct cam_packet))) { CAM_ERR(CAM_EEPROM, - "Offset is out of bound: off: %lld, %zu", - dev_config.offset, pkt_len); + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), pkt_len); rc = -EINVAL; goto release_buf; } + remain_len -= (size_t)dev_config.offset; csl_packet = (struct cam_packet *) (generic_pkt_addr + (uint32_t)dev_config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_EEPROM, "Invalid packet params"); + rc = -EINVAL; + goto release_buf; + } + switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_EEPROM_PACKET_OPCODE_INIT: if (e_ctrl->userspace_probe == false) { diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c index 842e7e841153..5201feeadc08 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_flash/cam_flash_core.c @@ -16,6 +16,7 @@ #include "cam_flash_core.h" #include "cam_res_mgr_api.h" #include "cam_common_util.h" +#include "cam_packet_util.h" static int cam_flash_prepare(struct cam_flash_ctrl *flash_ctrl, bool regulator_enable) @@ -625,11 +626,15 @@ static int cam_flash_pmic_delete_req(struct cam_flash_ctrl *fctrl, } static int32_t cam_flash_slaveInfo_pkt_parser(struct cam_flash_ctrl *fctrl, - uint32_t *cmd_buf) + uint32_t *cmd_buf, size_t len) { int32_t rc = 0; struct cam_cmd_i2c_info *i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + if (len < sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + return -EINVAL; + } if (fctrl->io_master_info.master_type == CCI_MASTER) { fctrl->io_master_info.cci_client->cci_i2c_master = fctrl->cci_i2c_master; @@ -904,7 +909,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) uint32_t *offset = NULL; uint32_t frm_offset = 0; size_t len_of_buffer; - size_t remaining_len_of_buff; + size_t remain_len; struct cam_flash_init *flash_init = NULL; struct common_header *cmn_hdr = NULL; struct cam_control *ioctl_ctrl = NULL; @@ -935,7 +940,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "Failed in getting the packet : %d", rc); return rc; } - remaining_len_of_buff = len_of_buffer; + remain_len = len_of_buffer; if ((sizeof(struct cam_packet) > len_of_buffer) || ((size_t)config.offset >= len_of_buffer - sizeof(struct cam_packet))) { @@ -945,14 +950,13 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) return -EINVAL; } - remaining_len_of_buff -= config.offset; + remain_len -= (size_t)config.offset; /* Add offset to the flash csl header */ csl_packet = (struct cam_packet *)(generic_ptr + config.offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_FLASH, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_FLASH, "Invalid packet params"); return -EINVAL; } @@ -969,14 +973,6 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (csl_packet->header.request_id > fctrl->last_flush_req) fctrl->last_flush_req = 0; - remaining_len_of_buff -= sizeof(struct cam_packet); - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_FLASH, "InVal len: %zu", remaining_len_of_buff); - return -EINVAL; - } - switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { /* INIT packet*/ @@ -1001,6 +997,15 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "invalid cmd buf"); return -EINVAL; } + + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc[i].offset > + (len_of_buffer - + sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "invalid cmd buf length"); + return -EINVAL; + } + remain_len = len_of_buffer - cmd_desc[i].offset; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); cmn_hdr = (struct common_header *)cmd_buf; @@ -1011,6 +1016,12 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) total_cmd_buf_in_bytes); switch (cmn_hdr->cmd_type) { case CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO: + if (len_of_buffer < + sizeof(struct cam_flash_init)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + return -EINVAL; + } + flash_init = (struct cam_flash_init *)cmd_buf; fctrl->flash_type = flash_init->flash_type; cmd_length_in_bytes = @@ -1022,7 +1033,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) break; case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: rc = cam_flash_slaveInfo_pkt_parser( - fctrl, cmd_buf); + fctrl, cmd_buf, remain_len); if (rc < 0) { CAM_ERR(CAM_FLASH, "Failed parsing slave info: rc: %d", @@ -1045,7 +1056,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = cam_sensor_update_power_settings( cmd_buf, total_cmd_buf_in_bytes, - &fctrl->power_info); + &fctrl->power_info, remain_len); processed_cmd_buf_in_bytes += cmd_length_in_bytes; cmd_buf += cmd_length_in_bytes/ @@ -1243,7 +1254,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) uint32_t *offset = NULL; uint32_t frm_offset = 0; size_t len_of_buffer; - size_t remaining_len_of_buff; + size_t remain_len; struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; @@ -1283,7 +1294,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) return rc; } - remaining_len_of_buff = len_of_buffer; + remain_len = len_of_buffer; if ((sizeof(struct cam_packet) > len_of_buffer) || ((size_t)config.offset >= len_of_buffer - sizeof(struct cam_packet))) { @@ -1294,14 +1305,13 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) goto rel_pkt_buf; } - remaining_len_of_buff -= config.offset; + remain_len -= (size_t)config.offset; /* Add offset to the flash csl header */ csl_packet = (struct cam_packet *)(generic_ptr + config.offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_FLASH, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_FLASH, "Invalid packet params"); rc = -EINVAL; goto rel_pkt_buf; } @@ -1320,16 +1330,6 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (csl_packet->header.request_id > fctrl->last_flush_req) fctrl->last_flush_req = 0; - remaining_len_of_buff -= sizeof(struct cam_packet); - - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_FLASH, "InVal len: %zu", remaining_len_of_buff); - rc = -EINVAL; - goto rel_pkt_buf; - } - switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_FLASH_PACKET_OPCODE_INIT: { /* INIT packet*/ @@ -1342,7 +1342,14 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); goto rel_pkt_buf; } - + if ((len_of_buffer < sizeof(struct cam_flash_init)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct cam_flash_init)))) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_pkt_buf; + } + remain_len = len_of_buffer - cmd_desc->offset; cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); cam_flash_info = (struct cam_flash_init *)cmd_buf; @@ -1372,6 +1379,12 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) case CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE: { CAM_DBG(CAM_FLASH, "INIT_FIRE Operation"); + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } + flash_operation_info = (struct cam_flash_set_on_off *) cmd_buf; if (!flash_operation_info) { @@ -1444,13 +1457,21 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) goto rel_pkt_buf; } + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "not enough buffer"); + rc = -EINVAL; + goto rel_pkt_buf; + } + remain_len = len_of_buffer - cmd_desc->offset; + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); if (!cmd_buf) { rc = -EINVAL; goto rel_cmd_buf; } - cmn_hdr = (struct common_header *)cmd_buf; switch (cmn_hdr->cmd_type) { @@ -1465,6 +1486,11 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) flash_data->cmn_attr.is_settings_valid = false; goto rel_cmd_buf; } + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } flash_operation_info = (struct cam_flash_set_on_off *) cmd_buf; @@ -1514,6 +1540,15 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); goto rel_pkt_buf; } + + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_pkt_buf; + } + remain_len = len_of_buffer - cmd_desc->offset; cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); cmn_hdr = (struct common_header *)cmd_buf; @@ -1521,6 +1556,11 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) switch (cmn_hdr->cmd_type) { case CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET: { CAM_DBG(CAM_FLASH, "Widget Flash Operation"); + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_pkt_buf; + } flash_operation_info = (struct cam_flash_set_on_off *) cmd_buf; if (!flash_operation_info) { @@ -1557,6 +1597,11 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) case CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR: { int query_curr_ma = 0; + if (remain_len < sizeof(struct cam_flash_query_curr)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } flash_query_info = (struct cam_flash_query_curr *)cmd_buf; @@ -1583,6 +1628,11 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) } case CAMERA_SENSOR_FLASH_CMD_TYPE_RER: { rc = 0; + if (remain_len < sizeof(struct cam_flash_set_rer)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + goto rel_cmd_buf; + } flash_rer_info = (struct cam_flash_set_rer *)cmd_buf; if (!flash_rer_info) { CAM_ERR(CAM_FLASH, diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c index 8e51cd95e448..8f8ddca8c668 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c @@ -19,6 +19,7 @@ #include "cam_debug_util.h" #include "cam_res_mgr_api.h" #include "cam_common_util.h" +#include "cam_packet_util.h" int32_t cam_ois_construct_default_power_setting( struct cam_sensor_power_ctrl_t *power_info) @@ -256,12 +257,12 @@ static int cam_ois_apply_settings(struct cam_ois_ctrl_t *o_ctrl, } static int cam_ois_slaveInfo_pkt_parser(struct cam_ois_ctrl_t *o_ctrl, - uint32_t *cmd_buf) + uint32_t *cmd_buf, size_t len) { int32_t rc = 0; struct cam_cmd_ois_info *ois_info; - if (!o_ctrl || !cmd_buf) { + if (!o_ctrl || !cmd_buf || len < sizeof(struct cam_cmd_ois_info)) { CAM_ERR(CAM_OIS, "Invalid Args"); return -EINVAL; } @@ -274,7 +275,8 @@ static int cam_ois_slaveInfo_pkt_parser(struct cam_ois_ctrl_t *o_ctrl, ois_info->slave_addr >> 1; o_ctrl->ois_fw_flag = ois_info->ois_fw_flag; o_ctrl->is_ois_calib = ois_info->is_ois_calib; - memcpy(o_ctrl->ois_name, ois_info->ois_name, 32); + memcpy(o_ctrl->ois_name, ois_info->ois_name, OIS_NAME_LEN); + o_ctrl->ois_name[OIS_NAME_LEN - 1] = '\0'; o_ctrl->io_master_info.cci_client->retries = 3; o_ctrl->io_master_info.cci_client->id_map = 0; memcpy(&(o_ctrl->opcode), &(ois_info->opcode), @@ -433,7 +435,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) struct cam_cmd_buf_desc *cmd_desc = NULL; uintptr_t generic_pkt_addr; size_t pkt_len; - size_t remaining_len_of_buff = 0; + size_t remain_len = 0; struct cam_packet *csl_packet = NULL; size_t len_of_buff = 0; uint32_t *offset = NULL, *cmd_buf; @@ -454,7 +456,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) return rc; } - remaining_len_of_buff = pkt_len; + remain_len = pkt_len; if ((sizeof(struct cam_packet) > pkt_len) || ((size_t)dev_config.offset >= pkt_len - sizeof(struct cam_packet))) { @@ -465,27 +467,17 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) goto rel_pkt; } - remaining_len_of_buff -= dev_config.offset; + remain_len -= (size_t)dev_config.offset; csl_packet = (struct cam_packet *) (generic_pkt_addr + (uint32_t)dev_config.offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_OIS, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_OIS, "Invalid packet params"); rc = -EINVAL; goto rel_pkt; } - remaining_len_of_buff -= sizeof(struct cam_packet); - - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_OIS, "InVal len: %zu", remaining_len_of_buff); - rc = -EINVAL; - goto rel_pkt; - } switch (csl_packet->header.op_code & 0xFFFFFF) { case CAM_OIS_PACKET_OPCODE_INIT: @@ -512,13 +504,23 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) rc = -EINVAL; goto rel_cmd_buf; } + + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > (len_of_buff - + sizeof(struct common_header)))) { + CAM_ERR(CAM_OIS, + "Invalid length for sensor cmd"); + rc = -EINVAL; + goto rel_cmd_buf; + } + remain_len = len_of_buff - cmd_desc[i].offset; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); cmm_hdr = (struct common_header *)cmd_buf; switch (cmm_hdr->cmd_type) { case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: rc = cam_ois_slaveInfo_pkt_parser( - o_ctrl, cmd_buf); + o_ctrl, cmd_buf, remain_len); if (rc < 0) { CAM_ERR(CAM_OIS, "Failed in parsing slave info"); @@ -532,7 +534,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) rc = cam_sensor_update_power_settings( cmd_buf, total_cmd_buf_in_bytes, - power_info); + power_info, remain_len); if (rc) { CAM_ERR(CAM_OIS, "Failed: parse power settings"); diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.h index d6f0ec564508..61fd2ec235d7 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.h +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.h @@ -16,6 +16,8 @@ #include #include "cam_ois_dev.h" +#define OIS_NAME_LEN 32 + /** * @power_info: power setting info to control the power * diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c index edd0cd28bd00..304d25f13265 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -17,6 +17,8 @@ #include "cam_soc_util.h" #include "cam_trace.h" #include "cam_common_util.h" +#include "cam_packet_util.h" + static void cam_sensor_update_req_mgr( struct cam_sensor_ctrl_t *s_ctrl, @@ -94,7 +96,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, struct cam_cmd_buf_desc *cmd_desc = NULL; struct i2c_settings_array *i2c_reg_settings = NULL; size_t len_of_buff = 0; - size_t remaining_len_of_buff = 0; + size_t remain_len = 0; uint32_t *offset = NULL; struct cam_config_dev_cmd config; struct i2c_data_settings *i2c_data = NULL; @@ -120,7 +122,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, return rc; } - remaining_len_of_buff = len_of_buff; + remain_len = len_of_buff; if ((sizeof(struct cam_packet) > len_of_buff) || ((size_t)config.offset >= len_of_buff - sizeof(struct cam_packet))) { @@ -131,19 +133,17 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, goto rel_pkt_buf; } - remaining_len_of_buff -= config.offset; + remain_len -= (size_t)config.offset; csl_packet = (struct cam_packet *)(generic_ptr + (uint32_t)config.offset); - if (((size_t)(csl_packet->header.size) > remaining_len_of_buff)) { - CAM_ERR(CAM_SENSOR, - "Inval pkt_header_size: %zu, len:of_buff: %zu", - csl_packet->header.size, remaining_len_of_buff); + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_SENSOR, "Invalid packet params"); rc = -EINVAL; goto rel_pkt_buf; - } - remaining_len_of_buff -= sizeof(struct cam_packet); + } if ((csl_packet->header.op_code & 0xFFFFFF) != CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG && @@ -241,14 +241,6 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, goto rel_pkt_buf; } - if ((sizeof(struct cam_cmd_buf_desc) > remaining_len_of_buff) || - (csl_packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc) > - remaining_len_of_buff)) { - CAM_ERR(CAM_SENSOR, "InVal len: %zu", remaining_len_of_buff); - rc = -EINVAL; - goto rel_pkt_buf; - } - offset = (uint32_t *)&csl_packet->payload; offset += csl_packet->cmd_buf_offset / 4; cmd_desc = (struct cam_cmd_buf_desc *)(offset); @@ -391,7 +383,7 @@ int32_t cam_sensor_update_slave_info(struct cam_cmd_probe *probe_info, int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, struct cam_sensor_ctrl_t *s_ctrl, - int32_t cmd_buf_num, int cmd_buf_length) + int32_t cmd_buf_num, uint32_t cmd_buf_length, size_t remain_len) { int32_t rc = 0; @@ -400,6 +392,13 @@ int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, struct cam_cmd_i2c_info *i2c_info = NULL; struct cam_cmd_probe *probe_info; + if (remain_len < + (sizeof(struct cam_cmd_i2c_info) + + sizeof(struct cam_cmd_probe))) { + CAM_ERR(CAM_SENSOR, + "not enough buffer for cam_cmd_i2c_info"); + return -EINVAL; + } i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; rc = cam_sensor_update_i2c_info(i2c_info, s_ctrl); if (rc < 0) { @@ -418,7 +417,8 @@ int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, break; case 1: { rc = cam_sensor_update_power_settings(cmd_buf, - cmd_buf_length, &s_ctrl->sensordata->power_info); + cmd_buf_length, &s_ctrl->sensordata->power_info, + remain_len); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed in updating power settings"); @@ -439,10 +439,11 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) uint32_t *cmd_buf; void *ptr; size_t len; - struct cam_packet *pkt; - struct cam_cmd_buf_desc *cmd_desc; + struct cam_packet *pkt = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; uintptr_t cmd_buf1 = 0; uintptr_t packet = 0; + size_t remain_len = 0; rc = cam_mem_get_cpu_buf(handle, &packet, &len); @@ -450,7 +451,21 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) CAM_ERR(CAM_SENSOR, "Failed to get the command Buffer"); return -EINVAL; } + pkt = (struct cam_packet *)packet; + if (pkt == NULL) { + CAM_ERR(CAM_SENSOR, "packet pos is invalid"); + rc = -EINVAL; + goto rel_pkt_buf; + } + + if ((len < sizeof(struct cam_packet)) || + (pkt->cmd_buf_offset >= (len - sizeof(struct cam_packet)))) { + CAM_ERR(CAM_SENSOR, "Not enough buf provided"); + rc = -EINVAL; + goto rel_pkt_buf; + } + cmd_desc = (struct cam_cmd_buf_desc *) ((uint32_t *)&pkt->payload + pkt->cmd_buf_offset/4); if (cmd_desc == NULL) { @@ -475,12 +490,25 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) "Failed to parse the command Buffer Header"); goto rel_pkt_buf; } + if (cmd_desc[i].offset >= len) { + CAM_ERR(CAM_SENSOR, + "offset past length of buffer"); + rc = -EINVAL; + goto rel_pkt_buf; + } + remain_len = len - cmd_desc[i].offset; + if (cmd_desc[i].length > remain_len) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided for cmd"); + rc = -EINVAL; + goto rel_pkt_buf; + } cmd_buf = (uint32_t *)cmd_buf1; cmd_buf += cmd_desc[i].offset/4; ptr = (void *) cmd_buf; rc = cam_handle_cmd_buffers_for_probe(ptr, s_ctrl, - i, cmd_desc[i].length); + i, cmd_desc[i].length, remain_len); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to parse the command Buffer Header"); diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index a308c08010f5..09cbe2801b2e 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -298,6 +298,8 @@ int cam_sensor_i2c_command_parser( size_t len_of_buff = 0; uintptr_t generic_ptr; uint16_t cmd_length_in_bytes = 0; + size_t remain_len = 0; + size_t tot_size = 0; for (i = 0; i < num_cmd_buffers; i++) { uint32_t *cmd_buf = NULL; @@ -325,10 +327,29 @@ int cam_sensor_i2c_command_parser( cmd_desc[i].mem_handle, rc, len_of_buff); return rc; } + + remain_len = len_of_buff; + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > + (len_of_buff - sizeof(struct common_header)))) { + CAM_ERR(CAM_SENSOR, "buffer provided too small"); + return -EINVAL; + } cmd_buf = (uint32_t *)generic_ptr; cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + if (remain_len < cmd_desc[i].length) { + CAM_ERR(CAM_SENSOR, "buffer provided too small"); + return -EINVAL; + } + while (byte_cnt < cmd_desc[i].length) { + if ((remain_len - byte_cnt) < + sizeof(struct common_header)) { + CAM_ERR(CAM_SENSOR, "Not enough buffer"); + rc = -EINVAL; + goto rel_buf; + } cmm_hdr = (struct common_header *)cmd_buf; generic_op_code = cmm_hdr->third_byte; switch (cmm_hdr->cmd_type) { @@ -338,6 +359,24 @@ int cam_sensor_i2c_command_parser( *cam_cmd_i2c_random_wr = (struct cam_cmd_i2c_random_wr *)cmd_buf; + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_i2c_random_wr)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto rel_buf; + } + tot_size = sizeof(struct i2c_rdwr_header) + + (sizeof(struct i2c_random_wr_payload) * + cam_cmd_i2c_random_wr->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto rel_buf; + } + rc = cam_sensor_handle_random_write( cam_cmd_i2c_random_wr, i2c_reg_settings, @@ -345,6 +384,7 @@ int cam_sensor_i2c_command_parser( if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed in random write %d", rc); + rc = -EINVAL; goto rel_buf; } @@ -360,6 +400,26 @@ int cam_sensor_i2c_command_parser( (struct cam_cmd_i2c_continuous_wr *) cmd_buf; + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_i2c_continuous_wr)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto rel_buf; + } + + tot_size = sizeof(struct i2c_rdwr_header) + + sizeof(cam_cmd_i2c_continuous_wr->reg_addr) + + (sizeof(struct cam_cmd_read) * + cam_cmd_i2c_continuous_wr->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto rel_buf; + } + rc = cam_sensor_handle_continuous_write( cam_cmd_i2c_continuous_wr, i2c_reg_settings, @@ -376,11 +436,17 @@ int cam_sensor_i2c_command_parser( break; } case CAMERA_SENSOR_CMD_TYPE_WAIT: { + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_unconditional_wait)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto rel_buf; + } if (generic_op_code == CAMERA_SENSOR_WAIT_OP_HW_UCND || generic_op_code == CAMERA_SENSOR_WAIT_OP_SW_UCND) { - rc = cam_sensor_handle_delay( &cmd_buf, generic_op_code, i2c_reg_settings, j, &byte_cnt, @@ -413,12 +479,19 @@ int cam_sensor_i2c_command_parser( break; } case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: { + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto rel_buf; + } rc = cam_sensor_handle_slave_info( io_master, cmd_buf); if (rc) { CAM_ERR(CAM_SENSOR, - "Handle slave info failed with rc: %d", - rc); + "Handle slave info failed with rc: %d", + rc); goto rel_buf; } cmd_length_in_bytes = @@ -761,8 +834,32 @@ int cam_sensor_util_request_gpio_table( return rc; } + +static int32_t cam_sensor_validate(void *ptr, size_t remain_buf) +{ + struct common_header *cmm_hdr = (struct common_header *)ptr; + size_t validate_size = 0; + + if (remain_buf < sizeof(struct common_header)) + return -EINVAL; + + if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_PWR_UP || + cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_PWR_DOWN) + validate_size = sizeof(struct cam_cmd_power); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_WAIT) + validate_size = sizeof(struct cam_cmd_unconditional_wait); + + if (remain_buf < validate_size) { + CAM_ERR(CAM_SENSOR, "Invalid cmd_buf len %zu min %zu", + remain_buf, validate_size); + return -EINVAL; + } + return 0; +} + int32_t cam_sensor_update_power_settings(void *cmd_buf, - int cmd_length, struct cam_sensor_power_ctrl_t *power_info) + uint32_t cmd_length, struct cam_sensor_power_ctrl_t *power_info, + size_t cmd_buf_len) { int32_t rc = 0, tot_size = 0, last_cmd_type = 0; int32_t i = 0, pwr_up = 0, pwr_down = 0; @@ -771,7 +868,8 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, struct cam_cmd_power *pwr_cmd = (struct cam_cmd_power *)cmd_buf; struct common_header *cmm_hdr = (struct common_header *)cmd_buf; - if (!pwr_cmd || !cmd_length) { + if (!pwr_cmd || !cmd_length || cmd_buf_len < (size_t)cmd_length || + cam_sensor_validate(cmd_buf, cmd_buf_len)) { CAM_ERR(CAM_SENSOR, "Invalid Args: pwr_cmd %pK, cmd_length: %d", pwr_cmd, cmd_length); return -EINVAL; @@ -798,6 +896,10 @@ int32_t cam_sensor_update_power_settings(void *cmd_buf, } while (tot_size < cmd_length) { + if (cam_sensor_validate(ptr, (cmd_length - tot_size))) { + rc = -EINVAL; + goto free_power_settings; + } if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_PWR_UP) { struct cam_cmd_power *pwr_cmd = diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h index 583ddb14243b..54b962923231 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h @@ -60,7 +60,8 @@ int msm_camera_fill_vreg_params(struct cam_hw_soc_info *soc_info, uint16_t power_setting_size); int32_t cam_sensor_update_power_settings(void *cmd_buf, - int cmd_length, struct cam_sensor_power_ctrl_t *power_info); + uint32_t cmd_length, struct cam_sensor_power_ctrl_t *power_info, + size_t cmd_buf_len); int cam_sensor_bob_pwm_mode_switch(struct cam_hw_soc_info *soc_info, int bob_reg_idx, bool flag); diff --git a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c index e4bcfe28fcb4..797bab2e8056 100644 --- a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c +++ b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.c @@ -50,23 +50,44 @@ int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc) return 0; } -int cam_packet_util_validate_packet(struct cam_packet *packet) +int cam_packet_util_validate_packet(struct cam_packet *packet, + size_t remain_len) { + size_t sum_cmd_desc = 0; + size_t sum_io_cfgs = 0; + size_t sum_patch_desc = 0; + size_t pkt_wo_payload = 0; + if (!packet) return -EINVAL; + if ((size_t)packet->header.size > remain_len) { + CAM_ERR(CAM_UTIL, + "Invalid packet size: %zu, CPU buf length: %zu", + (size_t)packet->header.size, remain_len); + return -EINVAL; + } + + CAM_DBG(CAM_UTIL, "num cmd buf:%d num of io config:%d kmd buf index:%d", packet->num_cmd_buf, packet->num_io_configs, packet->kmd_cmd_buf_index); - if ((packet->kmd_cmd_buf_index >= packet->num_cmd_buf) || - (!packet->header.size) || - (packet->cmd_buf_offset > packet->header.size) || - (packet->io_configs_offset > packet->header.size)) { - CAM_ERR(CAM_UTIL, "invalid packet:%d %d %d %d %d", - packet->kmd_cmd_buf_index, - packet->num_cmd_buf, packet->cmd_buf_offset, - packet->io_configs_offset, packet->header.size); + sum_cmd_desc = packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc); + sum_io_cfgs = packet->num_io_configs * sizeof(struct cam_buf_io_cfg); + sum_patch_desc = packet->num_patches * sizeof(struct cam_patch_desc); + pkt_wo_payload = offsetof(struct cam_packet, payload); + + if ((!packet->header.size) || + ((pkt_wo_payload + (size_t)packet->cmd_buf_offset + + sum_cmd_desc) > (size_t)packet->header.size) || + ((pkt_wo_payload + (size_t)packet->io_configs_offset + + sum_io_cfgs) > (size_t)packet->header.size) || + ((pkt_wo_payload + (size_t)packet->patch_offset + + sum_patch_desc) > (size_t)packet->header.size)) { + CAM_ERR(CAM_UTIL, "params not within mem len:%zu %zu %zu %zu", + (size_t)packet->header.size, sum_cmd_desc, + sum_io_cfgs, sum_patch_desc); return -EINVAL; } @@ -78,6 +99,7 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, { int rc = 0; size_t len = 0; + size_t remain_len = 0; struct cam_cmd_buf_desc *cmd_desc; uint32_t *cpu_addr; @@ -86,6 +108,13 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, return -EINVAL; } + if ((packet->kmd_cmd_buf_index < 0) || + (packet->kmd_cmd_buf_index > packet->num_cmd_buf)) { + CAM_ERR(CAM_UTIL, "Invalid kmd buf index: %d", + packet->kmd_cmd_buf_index); + return -EINVAL; + } + /* Take first command descriptor and add offset to it for kmd*/ cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *) &packet->payload + packet->cmd_buf_offset); @@ -100,13 +129,23 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, if (rc) return rc; - if (len < cmd_desc->size) { + remain_len = len; + if (((size_t)cmd_desc->offset >= len) || + ((size_t)cmd_desc->size >= (len - (size_t)cmd_desc->offset))) { CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d", len, cmd_desc->size); rc = -EINVAL; goto rel_kmd_buf; } + remain_len -= (size_t)cmd_desc->offset; + if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) { + CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu", + (size_t)packet->kmd_cmd_buf_offset); + rc = -EINVAL; + goto rel_kmd_buf; + } + cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4); CAM_DBG(CAM_UTIL, "total size %d, cmd size: %d, KMD buffer size: %d", cmd_desc->size, cmd_desc->length, @@ -176,6 +215,20 @@ int cam_packet_util_process_patches(struct cam_packet *packet, patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset, patch_desc[i].src_buf_hdl, patch_desc[i].src_offset); + if ((size_t)patch_desc[i].src_offset >= src_buf_size) { + CAM_ERR(CAM_UTIL, + "Invalid src buf patch offset"); + return -EINVAL; + } + + if ((dst_buf_len < sizeof(void *)) || + ((dst_buf_len - sizeof(void *)) < + (size_t)patch_desc[i].dst_offset)) { + CAM_ERR(CAM_UTIL, + "Invalid dst buf patch offset"); + return -EINVAL; + } + dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr + patch_desc[i].dst_offset); temp += patch_desc[i].src_offset; @@ -201,6 +254,7 @@ int cam_packet_util_process_generic_cmd_buffer( int rc; uintptr_t cpu_addr = 0; size_t buf_size; + size_t remain_len = 0; uint32_t *blob_ptr; uint32_t blob_type, blob_size, blob_block_size, len_read; @@ -223,6 +277,21 @@ int cam_packet_util_process_generic_cmd_buffer( return rc; } + remain_len = buf_size; + if ((buf_size < sizeof(uint32_t)) || + ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) { + CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu", + (size_t)cmd_buf->offset); + goto rel_cmd_buf; + } + remain_len -= (size_t)cmd_buf->offset; + + if (remain_len < (size_t)cmd_buf->length) { + CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu", + (size_t)cmd_buf->length); + goto rel_cmd_buf; + } + blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) + cmd_buf->offset); diff --git a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h index b2315232262d..9418a3e7e583 100644 --- a/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h +++ b/drivers/media/platform/msm/camera/cam_utils/cam_packet_util.h @@ -59,10 +59,13 @@ int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr, * * @packet: Packet to be validated * + * @remain_len: CPU buff length after config offset + * * @return: 0 for success * -EINVAL for Fail */ -int cam_packet_util_validate_packet(struct cam_packet *packet); +int cam_packet_util_validate_packet(struct cam_packet *packet, + size_t remain_len); /** * cam_packet_util_validate_cmd_desc() -- GitLab From d34722b6caf3041e8b10c58fdbb2b6a460ec9dad Mon Sep 17 00:00:00 2001 From: jiad Date: Sat, 12 Jan 2019 09:03:57 +0800 Subject: [PATCH 0869/1286] cnss2: Remove 0 MSI data check MSI data 0 shall be valid after pci_alloc_irq_vectors() and irq_get_msi_desc() return successful. Thus remove the 0 MSI data check. Change-Id: I5596a76353050a67104a35a2d44d957ae600fd85 Signed-off-by: jiad --- drivers/net/wireless/cnss2/pci.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index 057d16159498..696a2d23d9da 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -1713,11 +1713,6 @@ static int cnss_pci_enable_msi(struct cnss_pci_data *pci_priv) } pci_priv->msi_ep_base_data = msi_desc->msg.data; - if (!pci_priv->msi_ep_base_data) { - cnss_pr_err("Got 0 MSI base data!\n"); - CNSS_ASSERT(0); - } - cnss_pr_dbg("MSI base data is %d\n", pci_priv->msi_ep_base_data); return 0; -- GitLab From be97fd7616cf7d29f539e06c5b9e7ecb69a693a4 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Fri, 11 Jan 2019 17:35:48 -0800 Subject: [PATCH 0870/1286] mhi: dev: netdev: remove support for MHI ADPL channels ADPL no longer supported by mhi netdev driver, removing support for it. CRs-Fixed: 2361266 Change-Id: I5b5de69bf0f0ed02c1d52e4c9c488880520a99eb Signed-off-by: Sujeev Dias --- drivers/bus/mhi/devices/mhi_netdev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 12932c0afed4..485d9d430860 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -917,7 +917,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, static const struct mhi_device_id mhi_netdev_match_table[] = { { .chan = "IP_HW0" }, - { .chan = "IP_HW_ADPL" }, { .chan = "IP_HW0_RSC" }, {}, }; -- GitLab From d421d752a2000570c642ca492d20a712db9e03ba Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Fri, 11 Jan 2019 18:17:47 -0800 Subject: [PATCH 0871/1286] defconfig: enable DEVTMPFS on sdxprairie target Enable DEVTMPFS on sdxprairie target for proper systemd mounting. Change-Id: Ic4881f24ce1a026398a6b3e8594f8de4b52cc2ba Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 06757e3b2072..9fa15282eed2 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -158,6 +158,7 @@ CONFIG_CFG80211_DEBUGFS=y CONFIG_CFG80211_INTERNAL_REGDB=y CONFIG_CFG80211_WEXT=y CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=12 diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index ea92f25481b0..beb779f82061 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -145,6 +145,7 @@ CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_CFG80211=y CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=12 -- GitLab From 4c0aab468cea7c26124fd7860440d1bc75fdc327 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 12 Dec 2018 19:46:35 -0800 Subject: [PATCH 0872/1286] ARM: dts: msm: update MHI configuration for sm8150-sdxprairie modem Update devicetree node to reflect sdxprairie modem by adding support for new hardware channels. CRs-Fixed: 2361266 Change-Id: I193ac555d389ce0a821b9e2e0fbd603292352557 Signed-off-by: Sujeev Dias --- arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi | 255 +++++++++++++++++- arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi | 86 +++++- .../boot/dts/qcom/sm8150-sdxprairie.dtsi | 53 +++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 +- 4 files changed, 371 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi index 3a6f369fef0c..d16c5077d639 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,7 +21,7 @@ qcom,smmu-cfg = <0x3>; /* mhi bus specific settings */ - mhi,max-channels = <106>; + mhi,max-channels = <110>; mhi,timeout = <2000>; #address-cells = <1>; @@ -328,11 +328,33 @@ mhi,num-elements = <512>; mhi,event-ring = <5>; mhi,chan-dir = <2>; - mhi,data-type = <1>; + mhi,data-type = <4>; mhi,doorbell-mode = <3>; mhi,ee = <0x4>; }; + mhi_chan@102 { + reg = <102>; + label = "IP_HW_ADPL"; + mhi,event-ring = <6>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@103 { + reg = <103>; + label = "IP_HW_QDSS"; + mhi,num-elements = <128>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + mhi_chan@104 { reg = <104>; label = "IP_HW_OFFLOAD_0"; @@ -340,7 +362,6 @@ mhi,chan-dir = <1>; mhi,data-type = <3>; mhi,ee = <0x4>; - mhi,offload-chan; }; mhi_chan@105 { @@ -353,6 +374,27 @@ mhi,offload-chan; mhi,lpm-notify; }; + + mhi_chan@107 { + reg = <107>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <10>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@108 { + reg = <108>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <11>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; }; mhi_events { @@ -409,6 +451,76 @@ mhi,hw-ev; mhi,client-manage; }; + + mhi_event@6 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <102>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <8>; + mhi,chan = <103>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@8 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <9>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@9 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <10>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@10 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <11>; + mhi,chan = <107>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@11 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <12>; + mhi,chan = <108>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; }; mhi_devices { @@ -417,13 +529,14 @@ mhi,chan = "IP_HW0"; mhi,interface-name = "rmnet_mhi"; mhi,mru = <0x4000>; + mhi,chan-skb; }; - mhi_netdev_1: mhi_rmnet@1 { + mhi_rmnet@1 { reg = <0x1>; - mhi,chan = "IP_HW_ADPL"; - mhi,interface-name = "rmnet_mhi"; - mhi,mru = <0x4000>; + mhi,chan = "IP_HW0_RSC"; + mhi,mru = <0x8000>; + mhi,rsc-parent = <&mhi_netdev_0>; }; }; }; @@ -445,7 +558,7 @@ <45 512 1200000000 650000000>; /* mhi bus specific settings */ - mhi,max-channels = <106>; + mhi,max-channels = <110>; mhi,timeout = <2000>; #address-cells = <1>; @@ -752,11 +865,33 @@ mhi,num-elements = <512>; mhi,event-ring = <5>; mhi,chan-dir = <2>; - mhi,data-type = <1>; + mhi,data-type = <4>; mhi,doorbell-mode = <3>; mhi,ee = <0x4>; }; + mhi_chan@102 { + reg = <102>; + label = "IP_HW_ADPL"; + mhi,event-ring = <6>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@103 { + reg = <103>; + label = "IP_HW_QDSS"; + mhi,num-elements = <128>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + mhi_chan@104 { reg = <104>; label = "IP_HW_OFFLOAD_0"; @@ -777,6 +912,27 @@ mhi,offload-chan; mhi,lpm-notify; }; + + mhi_chan@107 { + reg = <107>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <10>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@108 { + reg = <108>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <11>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; }; mhi_events { @@ -833,6 +989,76 @@ mhi,hw-ev; mhi,client-manage; }; + + mhi_event@6 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <102>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <8>; + mhi,chan = <103>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@8 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <9>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@9 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <10>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@10 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <11>; + mhi,chan = <107>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@11 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <12>; + mhi,chan = <108>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; }; mhi_devices { @@ -841,13 +1067,14 @@ mhi,chan = "IP_HW0"; mhi,interface-name = "rmnet_mhi"; mhi,mru = <0x4000>; + mhi,chan-skb; }; - mhi_netdev_3: mhi_rmnet@1 { + mhi_rmnet@1 { reg = <0x1>; - mhi,chan = "IP_HW_ADPL"; - mhi,interface-name = "rmnet_mhi"; - mhi,mru = <0x4000>; + mhi,chan = "IP_HW0_RSC"; + mhi,mru = <0x8000>; + mhi,rsc-parent = <&mhi_netdev_0>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi index 86fcb7b67c67..bc31ed0bd1aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,6 +48,26 @@ mhi_chan@101 { status = "disabled"; }; + + mhi_chan@102 { + status = "disabled"; + }; + + mhi_chan@103 { + status = "disabled"; + }; + + mhi_chan@104 { + mhi,offload-chan; + }; + + mhi_chan@107 { + status = "disabled"; + }; + + mhi_chan@108 { + status = "disabled"; + }; }; mhi_events { @@ -74,6 +94,30 @@ mhi,client-manage; mhi,offload; }; + + mhi_events@6 { + status = "disabled"; + }; + + mhi_events@7 { + status = "disabled"; + }; + + mhi_events@8 { + status = "disabled"; + }; + + mhi_events@9 { + status = "disabled"; + }; + + mhi_events@10 { + status = "disabled"; + }; + + mhi_events@11 { + status = "disabled"; + }; }; }; @@ -98,6 +142,22 @@ mhi_chan@101 { status = "disabled"; }; + + mhi_chan@102 { + status = "disabled"; + }; + + mhi_chan@103 { + status = "disabled"; + }; + + mhi_chan@107 { + status = "disabled"; + }; + + mhi_chan@108 { + status = "disabled"; + }; }; mhi_events { @@ -124,6 +184,30 @@ mhi,client-manage; mhi,offload; }; + + mhi_events@6 { + status = "disabled"; + }; + + mhi_events@7 { + status = "disabled"; + }; + + mhi_events@8 { + status = "disabled"; + }; + + mhi_events@9 { + status = "disabled"; + }; + + mhi_events@10 { + status = "disabled"; + }; + + mhi_events@11 { + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index 9a03f62d737f..2e1f72c85d16 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -21,22 +21,57 @@ qcom,proxy-reg-names = "vdd_cx"; }; -&mhi_1 { +&mhi_0 { esoc-names = "mdm"; esoc-0 = <&mdm3>; qcom,smmu-cfg = <0x1d>; qcom,addr-win = <0x0 0x20000000 0x0 0x2fffffff>; - mhi_chan@25 { - status = "disabled"; - }; + mhi_channels { + mhi_chan@25 { + status = "disabled"; + }; - mhi_chan@104 { - status = "disabled"; - }; + mhi_chan@80 { + reg = <80>; + label = "AUDIO_VOICE_0"; + mhi,event-ring = <0>; + mhi,chan-dir = <0>; + mhi,ee = <0x4>; + mhi,data-type = <3>; + mhi,offload-chan; + status = "ok"; + }; - mhi_chan@105 { - status = "disabled"; + mhi_chan@104 { + label = "IP_HW0_RSC"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <5>; + mhi,doorbell-mode = <3>; + mhi,chan-type = <3>; + }; + + mhi_chan@105 { + label = "IP_HW_MHIP_0"; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW_MHIP_0"; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; }; mhi_devices { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b7bdd1f560aa..65d05dcccf08 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -54,9 +54,7 @@ mhi0 = &mhi_0; mhi1 = &mhi_1; mhi_netdev0 = &mhi_netdev_0; - mhi_netdev1 = &mhi_netdev_1; mhi_netdev2 = &mhi_netdev_2; - mhi_netdev3 = &mhi_netdev_3; }; aliases { -- GitLab From 34e7e9978308e61111f95dd26ddf12cf804a4732 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 25 Nov 2018 01:02:10 +0530 Subject: [PATCH 0873/1286] ARM: dts: msm: Introduce bus topology for TRINKET Bus topology is the representation of bus connections in SOC and is required for the bus driver to serve the bandwidth requests from clients. Change-Id: I90e64561093ce95ae41ab6a843d637e867dcbe28 Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/trinket-bus.dtsi | 1099 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + include/dt-bindings/msm/msm-bus-ids.h | 47 + 3 files changed, 1147 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-bus.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-bus.dtsi b/arch/arm64/boot/dts/qcom/trinket-bus.dtsi new file mode 100644 index 000000000000..915059d9db0f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-bus.dtsi @@ -0,0 +1,1099 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x1880000 0x60200>, + <0x4480000 0x80000>, + <0x1900000 0x8200>, + <0x1880000 0x60200>; + reg-names = "sys_noc-base", "bimc-base", "config_noc-base", + "qup_virt-base"; + + /*Buses*/ + + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,bypass-qos-prg; + qcom,util-fact = <161>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>, + <&clock_rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_config_noc: fab-config_noc { + cell-id = ; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>, + <&clock_rpmcc CNOC_MSMBUS_A_CLK>; + }; + + fab_qup_virt: fab-qup_virt { + cell-id = ; + label = "fab-qup_virt"; + qcom,fab-dev; + qcom,base-name = "qup_virt-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc RPM_SMD_QUP_CLK>, + <&clock_rpmcc RPM_SMD_QUP_A_CLK>; + }; + + fab_sys_noc: fab-sys_noc { + cell-id = ; + label = "fab-sys_noc"; + qcom,fab-dev; + qcom,base-name = "sys_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + qcom,base-offset = <0x15000>; + qcom,qos-off = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>, + <&clock_rpmcc SNOC_MSMBUS_A_CLK>; + }; + + /*Masters*/ + + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc_rt: mas-snoc-bimc-rt { + cell-id = ; + label = "mas-snoc-bimc-rt"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc_nrt: mas-snoc-bimc-nrt { + cell-id = ; + label = "mas-snoc-bimc-nrt"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc: mas-snoc-bimc { + cell-id = ; + label = "mas-snoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_gpu_cdsp_bimc: mas-gpu-cdsp-bimc { + cell-id = ; + label = "mas-gpu-cdsp-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = ; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <6>; + qcom,prio-rd = <6>; + qcom,prio-wr = <6>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cnoc: mas-snoc-cnoc { + cell-id = ; + label = "mas-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_rt_throttle_cfg + &slv_qhs_cdsp_throttle_cfg &slv_qhs_sdc2 + &slv_qhs_sdc1 &slv_qhs_ufs_mem_cfg + &slv_qhs_qm_cfg &slv_qhs_tlmm_east + &slv_qhs_bimc_cfg &slv_qhs_qm_mpu_cfg + &slv_qhs_camera_nrt_throttle_cfg + &slv_qhs_tlmm_west &slv_qhs_qdss_cfg + &slv_qhs_pdm &slv_qhs_ipa_cfg + &slv_qhs_display_throttle_cfg &slv_qhs_tcsr + &slv_qhs_mesg_ram &slv_qhs_pmic_arb + &slv_qhs_lpass &slv_qhs_venus_cfg + &slv_qhs_gpu_cfg &slv_qhs_imem_cfg + &slv_snoc_cfg &slv_srvc_cnoc + &slv_qhs_venus_throttle_cfg &slv_qhs_prng + &slv_qhs_vsense_ctrl_cfg &slv_qhs_crypto0_cfg + &slv_qhs_pimem_cfg &slv_qhs_usb3 + &slv_qhs_qup0 &slv_qhs_qup1 + &slv_qhs_camera_ss_cfg &slv_qhs_clk_ctl>; + qcom,bus-dev = <&fab_config_noc>; + qcom,mas-rpm-id = ; + }; + + mas_crypto_c0: mas-crypto-c0 { + cell-id = ; + label = "mas-crypto-c0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <22>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qup_core_master_0: mas-qup-core-master-0 { + cell-id = ; + label = "mas-qup-core-master-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qup_core_slave_0>; + qcom,bus-dev = <&fab_qup_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qup_core_master_1: mas-qup-core-master-1 { + cell-id = ; + label = "mas-qup-core-master-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qup_core_slave_1>; + qcom,bus-dev = <&fab_qup_virt>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cfg: mas-snoc-cfg { + cell-id = ; + label = "mas-snoc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_anoc_snoc: mas-anoc-snoc { + cell-id = ; + label = "mas-anoc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_snoc_bimc + &slv_snoc_cnoc &slv_xs_sys_tcu_cfg + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = ; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_snoc_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_cpp: mas-qxm-cpp { + cell-id = ; + label = "mas-qxm-cpp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <15>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc CPP_MMNRT_MSMBUS_CLK>, + <&clock_rpmcc CPP_MMNRT_MSMBUS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_jpeg: mas-qxm-jpeg { + cell-id = ; + label = "mas-qxm-jpeg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc JPEG_MMNRT_MSMBUS_CLK>, + <&clock_rpmcc JPEG_MMNRT_MSMBUS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_mdp0: mas-qxm-mdp0 { + cell-id = ; + label = "mas-qxm-mdp0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc MDP_MMRT_MSMBUS_CLK>, + <&clock_rpmcc MDP_MMRT_MSMBUS_A_CLK>; + qcom,connections = <&slv_snoc_bimc_rt>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_pimem: mas-qxm-pimem { + cell-id = ; + label = "mas-qxm-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <20>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_qxs_imem &slv_snoc_bimc>; + qcom,prio1 = <0>; + qcom,prio0 = <0>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <9>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc VENUS_MMNRT_MSMBUS_CLK>, + <&clock_rpmcc VENUS_MMNRT_MSMBUS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <13>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc ARM9_MMNRT_MSMBUS_CLK>, + <&clock_rpmcc ARM9_MMNRT_MSMBUS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + + }; + + mas_qxm_vfe0: mas-qxm-vfe0 { + cell-id = ; + label = "mas-qxm-vfe0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <10>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_snoc_bimc_rt>; + qcom,util-fact = <153>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc VFE_MMRT_MSMBUS_CLK>, + <&clock_rpmcc VFE_MMRT_MSMBUS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qup0: mas-qhm-qup0 { + cell-id = ; + label = "mas-qhm-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc QUP0_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc QUP0_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qup1: mas-qhm-qup1 { + cell-id = ; + label = "mas-qhm-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc QUP1_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc QUP1_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_spdm: mas-qhm-spdm { + cell-id = ; + label = "mas-qhm-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_anoc_snoc>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_ipa: mas-qxm-ipa { + cell-id = ; + label = "mas-qxm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_dap: mas-xm-dap { + cell-id = ; + label = "mas-xm-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_anoc_snoc>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc DAP_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc DAP_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_sdc1: mas-xm-sdc1 { + cell-id = ; + label = "mas-xm-sdc1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <17>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC1_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc SDC1_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_sdc2: mas-xm-sdc2 { + cell-id = ; + label = "mas-xm-sdc2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <23>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC2_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc SDC2_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_ufs_mem: mas-xm-ufs-mem { + cell-id = ; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <25>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc RPM_SMD_SNOC_LPASS_CLK>, + <&clock_rpmcc RPM_SMD_SNOC_LPASS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_usb3_0: mas-xm-usb3-0 { + cell-id = ; + label = "mas-xm-usb3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <24>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio1 = <2>; + qcom,prio0 = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qnm_gpu: mas-qnm-gpu { + cell-id = ; + label = "mas-qnm-gpu"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <16>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_gpu_cdsp_bimc>; + qcom,prio1 = <0>; + qcom,prio0 = <0>; + qcom,util-fact = <161>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + + }; + + /*Slaves*/ + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = ; + label = "slv-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_bimc_cfg:slv-qhs-bimc-cfg { + cell-id = ; + label = "slv-qhs-bimc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-throtle-cfg { + cell-id = ; + label = "slv-qhs-camera-nrt-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_rt_throttle_cfg:slv-qhs-camera-rt-throttle-cfg { + cell-id = ; + label = "slv-qhs-camera-rt-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_ss_cfg:slv-qhs-camera-ss-cfg { + cell-id = ; + label = "slv-qhs-camera-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_cdsp_throttle_cfg:slv-qhs-cdsp-throttle-cfg { + cell-id = ; + label = "slv-qhs-cdsp-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg { + cell-id = ; + label = "slv-qhs-display-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_gpu_cfg:slv-qhs-gpu-cfg { + cell-id = ; + label = "slv-qhs-gpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_ipa_cfg:slv-qhs-ipa-cfg { + cell-id = ; + label = "slv-qhs-ipa-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_lpass:slv-qhs-lpass { + cell-id = ; + label = "slv-qhs-lpass"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_mesg_ram:slv-qhs-mesg-ram { + cell-id = ; + label = "slv-qhs-mesg-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pdm:slv-qhs-pdm { + cell-id = ; + label = "slv-qhs-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { + cell-id = ; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pmic_arb:slv-qhs-pmic-arb { + cell-id = ; + label = "slv-qhs-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qm_cfg:slv-qhs-qm-cfg { + cell-id = ; + label = "slv-qhs-qm-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg { + cell-id = ; + label = "slv-qhs-qm-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qup0:slv-qhs-qup0 { + cell-id = ; + label = "slv-qhs-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qup1:slv-qhs-qup1 { + cell-id = ; + label = "slv-qhs-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_sdc1:slv-qhs-sdc1 { + cell-id = ; + label = "slv-qhs-sdc1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc + SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_sdc2:slv-qhs-sdc2 { + cell-id = ; + label = "slv-qhs-sdc2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc + SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_snoc_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_east:slv-qhs-tlmm-east { + cell-id = ; + label = "slv-qhs-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_usb3:slv-qhs-usb3 { + cell-id = ; + label = "slv-qhs-usb3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_venus_cfg:slv-qhs-venus-cfg { + cell-id = ; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg { + cell-id = ; + label = "slv-qhs-venus-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg { + cell-id = ; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qup_core_slave_0:slv-qup-core-slave-0 { + cell-id = ; + label = "slv-qup-core-slave-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_qup_virt>; + qcom,slv-rpm-id = ; + }; + + slv_qup_core_slave_1:slv-qup-core-slave-1 { + cell-id = ; + label = "slv-qup-core-slave-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_qup_virt>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc_nrt:slv-snoc-bimc-nrt { + cell-id = ; + label = "slv-snoc-bimc-nrt"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_bimc_nrt>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc_rt:slv-snoc-bimc-rt { + cell-id = ; + label = "slv-snoc-bimc-rt"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_bimc_rt>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cnoc:slv-snoc-cnoc { + cell-id = ; + label = "slv-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qxs_pimem:slv-qxs-pimem { + cell-id = ; + label = "slv-qxs-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc:slv-snoc-bimc { + cell-id = ; + label = "slv-snoc-bimc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_anoc_snoc:slv-anoc-snoc { + cell-id = ; + label = "slv-anoc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_anoc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpu_cdsp_bimc:slv-gpu-cdsp-bimc { + cell-id = ; + label = "slv-gpu-cdsp-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,util-fact = <161>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_gpu_cdsp_bimc>; + qcom,slv-rpm-id = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 9713539bb513..e60f8243c71f 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2174,6 +2174,7 @@ #include "trinket-vidc.dtsi" #include "trinket-pm.dtsi" #include "trinket-gpu.dtsi" +#include "trinket-bus.dtsi" &pm6125_vadc { pinctrl-names = "default"; diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h index e13a1db1e421..c3f7f56f6cb5 100644 --- a/include/dt-bindings/msm/msm-bus-ids.h +++ b/include/dt-bindings/msm/msm-bus-ids.h @@ -46,6 +46,7 @@ #define MSM_BUS_FAB_CAMNOC_VIRT 6154 #define MSM_BUS_FAB_COMP_NOC 6155 #define MSM_BUS_FAB_GEM_NOC 6156 +#define MSM_BUS_FAB_QUP_VIRT 6157 #define MSM_BUS_FAB_MC_VIRT_DISPLAY 26000 #define MSM_BUS_FAB_MEM_NOC_DISPLAY 26001 @@ -299,6 +300,11 @@ #define MSM_BUS_MASTER_MEM_NOC_PCIE_SNOC 177 #define MSM_BUS_MASTER_CAMNOC_RT_UNCOMP 178 #define MSM_BUS_MASTER_CAMNOC_NRT_UNCOMP 179 +#define MSM_BUS_MASTER_SNOC_BIMC_RT 180 +#define MSM_BUS_MASTER_SNOC_BIMC_NRT 181 +#define MSM_BUS_MASTER_GPU_CDSP_PROC 182 +#define MSM_BUS_MASTER_QUP_CORE_0 183 +#define MSM_BUS_MASTER_QUP_CORE_1 184 #define MSM_BUS_MASTER_LLCC_DISPLAY 20000 #define MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001 @@ -682,6 +688,14 @@ #define MSM_BUS_SLAVE_ANOC_IPA 812 #define MSM_BUS_SLAVE_ECC_CFG 813 #define MSM_BUS_SLAVE_SPMI_VGI_COEX 814 +#define MSM_BUS_SLAVE_GPU_CFG 815 +#define MSM_BUS_SLAVE_QUP_CORE_0 816 +#define MSM_BUS_SLAVE_QUP_CORE_1 817 +#define MSM_BUS_SLAVE_SNOC_BIMC_NRT 818 +#define MSM_BUS_SLAVE_SNOC_BIMC_RT 819 +#define MSM_BUS_SLAVE_GPU_CDSP_BIMC 820 +#define MSM_BUS_SLAVE_QM_MPU_CFG 821 +#define MSM_BUS_SLAVE_CDSP_THROTTLE_CFG 822 #define MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512 #define MSM_BUS_SLAVE_LLCC_DISPLAY 20513 @@ -744,6 +758,7 @@ #define ICBID_MASTER_BLSP_2 39 #define ICBID_MASTER_USB_HSIC 40 #define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_QUP_1 ICBID_MASTER_BLSP_1 #define ICBID_MASTER_USB_HS 42 #define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS #define ICBID_MASTER_PNOC_CFG 43 @@ -869,6 +884,16 @@ #define ICBID_MASTER_LPASS_LPAIF 159 #define ICBID_MASTER_LPASS_LEC 160 #define ICBID_MASTER_LPASS_ANOC_BIMC 161 +#define ICBID_MASTER_MCDMA_NAV_CE 162 +#define ICBID_MASTER_SNOC_BIMC_RT 163 +#define ICBID_MASTER_SNOC_BIMC_NRT 164 +#define ICBID_MASTER_GPU_CDSP_PROC 165 +#define ICBID_MASTER_QUP_0 166 +#define ICBID_MASTER_UFS_MEM 167 +#define ICBID_MASTER_VIDEO_PROC 168 +#define ICBID_MASTER_LPASS_DMA 169 +#define ICBID_MASTER_QUP_CORE_0 170 +#define ICBID_MASTER_QUP_CORE_1 171 #define ICBID_SLAVE_EBI1 0 #define ICBID_SLAVE_APPSS_L2 1 @@ -917,6 +942,7 @@ #define ICBID_SLAVE_BLSP_2 37 #define ICBID_SLAVE_USB_HSIC 38 #define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_QUP_1 ICBID_SLAVE_BLSP_1 #define ICBID_SLAVE_USB_HS 40 #define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS #define ICBID_SLAVE_PDM 41 @@ -1129,4 +1155,25 @@ #define ICBID_SLAVE_PCNOC_S_10 245 #define ICBID_SLAVE_PCNOC_S_11 246 #define ICBID_SLAVE_LPASS_ANOC_BIMC 247 +#define ICBID_SLAVE_SNOC_BIMC_NRT 259 +#define ICBID_SLAVE_SNOC_BIMC_RT 260 +#define ICBID_SLAVE_QUP_0 261 +#define ICBID_SLAVE_UFS_MEM_CFG 262 +#define ICBID_SLAVE_VSENSE_CTRL_CFG 263 +#define ICBID_SLAVE_QUP_CORE_0 264 +#define ICBID_SLAVE_QUP_CORE_1 265 +#define ICBID_SLAVE_GPU_CDSP_BIMC 266 +#define ICBID_SLAVE_AHB2PHY_CSI 267 +#define ICBID_SLAVE_AHB2PHY_USB 268 +#define CBID_SLAVE_AHB2PHY_VREF 269 +#define ICBID_SLAVE_APSS_THROTTLE_CFG 270 +#define ICBID_SLAVE_CAMERA_NRT_THROTTLE_CFG 271 +#define ICBID_SLAVE_CDSP_THROTTLE_CFG 272 +#define ICBID_SLAVE_DDR_PHY_CFG 273 +#define ICBID_SLAVE_DDR_SS_CFG 274 +#define ICBID_SLAVE_GPU_CFG 275 +#define ICBID_SLAVE_GPU_THROTTLE_CFG 276 +#define ICBID_SLAVE_MAPSS 277 +#define ICBID_SLAVE_MDSP_MPU_CFG 278 +#define ICBID_SLAVE_CAMERA_RT_THROTTLE_CFG 279 #endif -- GitLab From 07f6991071d4c8c60e10735cd5fe525d80d848de Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 8 Jan 2019 15:30:21 +0530 Subject: [PATCH 0874/1286] msm: msm_bus: Add node clock support for each bus node node_a_clk support is required for each master/slave to get the clock handle and vote for required frequency. Change-Id: Ib01d74af7ba2b5e85e6e57b3b3ade5c260990c2c Signed-off-by: Odelu Kukatla --- drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c b/drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c index a6edab0a720b..142668598631 100644 --- a/drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c +++ b/drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2016, 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -656,6 +656,15 @@ static int get_bus_node_device_data( of_node_put(qos_clk_node); } + node_device->clk[ACTIVE_CTX].clk = of_clk_get_by_name(dev_node, + "node_a_clk"); + + if (IS_ERR_OR_NULL(node_device->clk[ACTIVE_CTX].clk)) + dev_dbg(&pdev->dev, + "%s:Failed to get bus clk for bus%d ctx%d", + __func__, node_device->node_info->id, + ACTIVE_CTX); + node_device->clk[DUAL_CTX].clk = of_clk_get_by_name(dev_node, "node_clk"); -- GitLab From 0817a956385b5d962af2e3017bc0173dff4f62b4 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Sat, 12 Jan 2019 14:16:16 +0530 Subject: [PATCH 0875/1286] ARM: dts: msm: add display support for TRINKET Add changes required to enable support for display on TRINKET. Change-Id: I16d07feae140b1c372b487445cb8c209c649cadb Signed-off-by: Shubhashree Dhar Signed-off-by: Tharun Raj Soma --- .../boot/dts/qcom/trinket-idp-overlay.dts | 4 + arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 20 + arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 56 +++ .../boot/dts/qcom/trinket-sde-display.dtsi | 183 ++++++++ arch/arm64/boot/dts/qcom/trinket-sde-pll.dtsi | 41 ++ arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 393 ++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 2 + 7 files changed, 699 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-sde-pll.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-sde.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts index 9a7815bd42c4..fcde40c18b76 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts @@ -23,3 +23,7 @@ qcom,msm-id = <394 0x10000>; qcom,board-id = <34 0>; }; + +&dsi_td4330_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index c19a1a0c795b..9561076739c3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -13,6 +13,7 @@ #include #include "trinket-thermal-overlay.dtsi" +#include "trinket-sde-display.dtsi" &qupv3_se1_i2c { status = "ok"; @@ -179,3 +180,22 @@ status = "ok"; }; + +&dsi_td4330_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_td4330_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 89 0>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 1ecf910f971b..df5bda4e0c8c 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -976,6 +976,62 @@ }; }; + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio89"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio89"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { diff --git a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi new file mode 100644 index 000000000000..1ca88a6df603 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi @@ -0,0 +1,183 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi" +#include "dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + dsi_td4330_truly_vid_display: qcom,dsi-display@0 { + label = "dsi_td4330_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_video>; + }; + + dsi_td4330_truly_cmd_display: qcom,dsi-display@1 { + label = "dsi_td4330_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_cmd>; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, + <&mdss_dsi0_pll PIX0_MUX_CLK>; + clock-names = "src_byte_clk0", "src_pixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 89 0>; + + vddio-supply = <&L9A>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_td4330_truly_vid_display + &dsi_td4330_truly_cmd_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; + +&dsi_td4330_truly_cmd { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 1F 09 0B 06 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_td4330_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 1F 09 0B 06 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-sde-pll.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde-pll.dtsi new file mode 100644 index 000000000000..cffbb243153f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-sde-pll.dtsi @@ -0,0 +1,41 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@5e94400 { + compatible = "qcom,mdss_dsi_pll_14nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "pll_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi new file mode 100644 index 000000000000..3569a84cdaeb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -0,0 +1,393 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x84208>, + <0x5eb0000 0x2008>, + <0x5eac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 307000000 19200000 307000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* interrupt config */ + interrupts = <0 186 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x400 0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x0 + 0x0 0x0 0x0>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "cwb", "none", + "none", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi"; + + qcom,sde-pp-off = <0x71000 0x71800>; + qcom,sde-pp-slave = <0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000 0x27000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 1 5>; + qcom,sde-sspp-excl-rect = <1 1 1>; + qcom,sde-sspp-smart-dma-priority = <3 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 0 0 0 0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>, <0x2b4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-wb-linewidth = <2160>; + qcom,sde-mixer-blendstages = <0x5>; + qcom,sde-highest-bank-bit = <0x1>; + qcom,sde-ubwc-version = <0x100>; + qcom,sde-ubwc-swizzle = <1>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <4100000>; + qcom,sde-max-bw-high-kbps = <4100000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x0000401>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-inverse-pma; + }; + + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x401 0x0>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@5e00000 { + compatible = "qcom,sde_rotator"; + reg = <0x5e00000 0xac000>; + reg-names = "mdp_phys"; + status = "disabled"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x1>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x402 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x403 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L18A>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>; + reg-names = "dsi_phy", "phy_clamp_base"; + vdda-0p9-supply = <&L4A>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index e60f8243c71f..4423ab8572ef 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2175,6 +2175,8 @@ #include "trinket-pm.dtsi" #include "trinket-gpu.dtsi" #include "trinket-bus.dtsi" +#include "trinket-sde-pll.dtsi" +#include "trinket-sde.dtsi" &pm6125_vadc { pinctrl-names = "default"; -- GitLab From def20151bbd2e517e984bd40377adc3488c775db Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 11 Jan 2019 12:15:21 +0530 Subject: [PATCH 0876/1286] ARM: dts: msm: add support for frequency scaling in trinket target Add support for cpu and device frequency scaling in trinket target. Change-Id: I25d49c610a885373f7d96324e2cf36464a369017 Signed-off-by: Santosh Mardi --- arch/arm64/boot/dts/qcom/trinket.dtsi | 136 ++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 8d9870738086..856b8979f610 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -24,6 +24,9 @@ #include #include +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + / { model = "Qualcomm Technologies, Inc. TRINKET"; compatible = "qcom,trinket"; @@ -2136,6 +2139,139 @@ compatible = "qcom,msm-ssc-sensors"; status = "ok"; }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1721 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1721 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 864000 MHZ_TO_MBPS( 300, 4) >, + < 1305600 MHZ_TO_MBPS( 547, 4) >, + < 1420000 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >; + }; + + cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x24>; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 451, 4) >, + < 1401600 MHZ_TO_MBPS(1017, 4) >, + < 1804800 MHZ_TO_MBPS(1555, 4) >, + < 2016000 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 614400 MHZ_TO_MBPS( 300, 4) >, + < 1017600 MHZ_TO_MBPS( 451, 4) >, + < 1420000 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 300, 4) >, + < 1056000 MHZ_TO_MBPS( 547, 4) >, + < 1401680 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >, + < 2016000 MHZ_TO_MBPS(1804, 4) >; + }; }; #include "pmi632.dtsi" -- GitLab From 777e5c9bc47d31f9df07c15fa6bfff113ccd8bb1 Mon Sep 17 00:00:00 2001 From: AnilKumar Chimata Date: Fri, 11 Jan 2019 12:40:13 +0530 Subject: [PATCH 0877/1286] qseecom: Fix stack overflow issue During qseecom load app, module checks whether the app is already loaded or not, during this call flow stack pointer is passed to caller APIs which leads to stack overflow. Hence memory allocation is moved to Heap. Change-Id: Iae39edce890f69cd751159754caed5bc29f2be67 Signed-off-by: AnilKumar Chimata --- drivers/misc/qseecom.c | 80 ++++++++++++++++++++++++++++-------------- 1 file changed, 53 insertions(+), 27 deletions(-) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 58058addcc97..784755659d0a 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -2424,7 +2424,7 @@ static void __qseecom_reentrancy_check_if_this_app_blocked( } } -static int __qseecom_check_app_exists(struct qseecom_check_app_ireq req, +static int __qseecom_check_app_exists(struct qseecom_check_app_ireq *req, uint32_t *app_id) { int32_t ret; @@ -2443,7 +2443,7 @@ static int __qseecom_check_app_exists(struct qseecom_check_app_ireq req, spin_lock_irqsave(&qseecom.registered_app_list_lock, flags); list_for_each_entry(entry, &qseecom.registered_app_list_head, list) { - if (!strcmp(entry->app_name, req.app_name)) { + if (!strcmp(entry->app_name, req->app_name)) { found_app = true; break; } @@ -2458,7 +2458,7 @@ static int __qseecom_check_app_exists(struct qseecom_check_app_ireq req, memset((void *)&resp, 0, sizeof(resp)); /* SCM_CALL to check if app_id for the mentioned app exists */ - ret = qseecom_scm_call(SCM_SVC_TZSCHEDULER, 1, &req, + ret = qseecom_scm_call(SCM_SVC_TZSCHEDULER, 1, req, sizeof(struct qseecom_check_app_ireq), &resp, sizeof(resp)); if (ret) { @@ -2499,19 +2499,24 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) size_t len; struct qseecom_command_scm_resp resp; - struct qseecom_check_app_ireq req; + struct qseecom_check_app_ireq *req = NULL; struct qseecom_load_app_ireq load_req; struct qseecom_load_app_64bit_ireq load_req_64bit; void *cmd_buf = NULL; size_t cmd_len; bool first_time = false; + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + /* Copy the relevant information needed for loading the image */ if (copy_from_user(&load_img_req, (void __user *)argp, sizeof(struct qseecom_load_img_req))) { pr_err("copy_from_user failed\n"); - return -EFAULT; + ret = -EFAULT; + goto req_free; } /* Check and load cmnlib */ @@ -2521,7 +2526,8 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) ret = qseecom_load_commonlib_image(data, "cmnlib"); if (ret) { pr_err("failed to load cmnlib\n"); - return -EIO; + ret = -EIO; + goto req_free; } qseecom.commonlib_loaded = true; pr_debug("cmnlib is loaded\n"); @@ -2532,7 +2538,8 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) ret = qseecom_load_commonlib_image(data, "cmnlib64"); if (ret) { pr_err("failed to load cmnlib64\n"); - return -EIO; + ret = -EIO; + goto req_free; } qseecom.commonlib64_loaded = true; pr_debug("cmnlib64 is loaded\n"); @@ -2544,7 +2551,7 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) ret = __qseecom_register_bus_bandwidth_needs(data, MEDIUM); mutex_unlock(&qsee_bw_mutex); if (ret) - return ret; + goto req_free; } /* Vote for the SFPB clock */ @@ -2552,9 +2559,9 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) if (ret) goto enable_clk_err; - req.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; + req->qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; load_img_req.img_name[MAX_APP_NAME_SIZE-1] = '\0'; - strlcpy(req.app_name, load_img_req.img_name, MAX_APP_NAME_SIZE); + strlcpy(req->app_name, load_img_req.img_name, MAX_APP_NAME_SIZE); ret = __qseecom_check_app_exists(req, &app_id); if (ret < 0) @@ -2562,14 +2569,14 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) if (app_id) { pr_debug("App id %d (%s) already exists\n", app_id, - (char *)(req.app_name)); + (char *)(req->app_name)); spin_lock_irqsave(&qseecom.registered_app_list_lock, flags); list_for_each_entry(entry, &qseecom.registered_app_list_head, list){ if (entry->app_id == app_id) { if (entry->ref_cnt == U32_MAX) { pr_err("App %d (%s) ref_cnt overflow\n", - app_id, req.app_name); + app_id, req->app_name); ret = -EINVAL; goto loadapp_err; } @@ -2731,6 +2738,8 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) qseecom_unregister_bus_bandwidth_needs(data); mutex_unlock(&qsee_bw_mutex); } +req_free: + kfree(req); return ret; } @@ -4565,7 +4574,7 @@ int qseecom_start_app(struct qseecom_handle **handle, int32_t ret = 0; unsigned long flags = 0; struct qseecom_dev_handle *data = NULL; - struct qseecom_check_app_ireq app_ireq; + struct qseecom_check_app_ireq *app_ireq = NULL; struct qseecom_registered_app_list *entry = NULL; struct qseecom_registered_kclient_list *kclient_entry = NULL; bool found_app = false; @@ -4614,25 +4623,31 @@ int qseecom_start_app(struct qseecom_handle **handle, mutex_lock(&app_access_lock); - app_ireq.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; - strlcpy(app_ireq.app_name, app_name, MAX_APP_NAME_SIZE); + app_ireq = kzalloc(sizeof(*app_ireq), GFP_KERNEL); + if (!app_ireq) { + ret = -ENOMEM; + goto err; + } + + app_ireq->qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; + strlcpy(app_ireq->app_name, app_name, MAX_APP_NAME_SIZE); ret = __qseecom_check_app_exists(app_ireq, &app_id); if (ret) - goto err; + goto app_ireq_free; strlcpy(data->client.app_name, app_name, MAX_APP_NAME_SIZE); if (app_id) { pr_warn("App id %d for [%s] app exists\n", app_id, - (char *)app_ireq.app_name); + (char *)app_ireq->app_name); spin_lock_irqsave(&qseecom.registered_app_list_lock, flags); list_for_each_entry(entry, &qseecom.registered_app_list_head, list){ if (entry->app_id == app_id) { if (entry->ref_cnt == U32_MAX) { pr_err("App %d (%s) ref_cnt overflow\n", - app_id, app_ireq.app_name); + app_id, app_ireq->app_name); ret = -EINVAL; - goto err; + goto app_ireq_free; } entry->ref_cnt++; found_app = true; @@ -4643,15 +4658,16 @@ int qseecom_start_app(struct qseecom_handle **handle, &qseecom.registered_app_list_lock, flags); if (!found_app) pr_warn("App_id %d [%s] was loaded but not registered\n", - ret, (char *)app_ireq.app_name); + ret, (char *)app_ireq->app_name); } else { /* load the app and get the app_id */ pr_debug("%s: Loading app for the first time'\n", qseecom.pdev->init_name); ret = __qseecom_load_fw(data, app_name, &app_id); if (ret < 0) - goto err; + goto app_ireq_free; } + kfree(app_ireq); data->client.app_id = app_id; if (!found_app) { entry = kmalloc(sizeof(*entry), GFP_KERNEL); @@ -4708,6 +4724,8 @@ int qseecom_start_app(struct qseecom_handle **handle, mutex_unlock(&app_access_lock); return 0; +app_ireq_free: + kfree(app_ireq); err: if (va) __qseecom_free_coherent_buf(size, va, pa); @@ -5516,8 +5534,8 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, { int32_t ret = 0; - struct qseecom_qseos_app_load_query *query_req; - struct qseecom_check_app_ireq req; + struct qseecom_qseos_app_load_query *query_req = NULL; + struct qseecom_check_app_ireq *req = NULL; struct qseecom_registered_app_list *entry = NULL; unsigned long flags = 0; uint32_t app_arch = 0, app_id = 0; @@ -5528,6 +5546,12 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, if (!query_req) return -ENOMEM; + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) { + ret = -ENOMEM; + goto query_req_exit; + } + /* Copy the relevant information needed for loading the image */ if (copy_from_user(query_req, (void __user *)argp, sizeof(struct qseecom_qseos_app_load_query))) { @@ -5536,9 +5560,9 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, goto exit_free; } - req.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; + req->qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND; query_req->app_name[MAX_APP_NAME_SIZE-1] = '\0'; - strlcpy(req.app_name, query_req->app_name, MAX_APP_NAME_SIZE); + strlcpy(req->app_name, query_req->app_name, MAX_APP_NAME_SIZE); ret = __qseecom_check_app_exists(req, &app_id); if (ret) { @@ -5547,7 +5571,7 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, } if (app_id) { pr_debug("App id %d (%s) already exists\n", app_id, - (char *)(req.app_name)); + (char *)(req->app_name)); spin_lock_irqsave(&qseecom.registered_app_list_lock, flags); list_for_each_entry(entry, &qseecom.registered_app_list_head, list){ @@ -5555,7 +5579,7 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, app_arch = entry->app_arch; if (entry->ref_cnt == U32_MAX) { pr_err("App %d (%s) ref_cnt overflow\n", - app_id, req.app_name); + app_id, req->app_name); ret = -EINVAL; goto exit_free; } @@ -5615,6 +5639,8 @@ static int qseecom_query_app_loaded(struct qseecom_dev_handle *data, } exit_free: + kfree(req); +query_req_exit: kfree(query_req); return ret; /* app not loaded */ -- GitLab From 12e6c73b8c345d5e5ad9e554d8d1d9151e097d5a Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 10 Jan 2019 13:22:52 +0530 Subject: [PATCH 0878/1286] msm: ipa3: Check IPA initialized in modem SSR events In local modem SSR events not checking if IPA is initialized or not. Added check to see IPA is initialized. Change-Id: Ica21a148e5c11cc14e5e4c3bcbd609572b588386 Signed-off-by: Praveen Kurapati --- drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index 5eb90be72f99..80ad8c949163 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2818,6 +2818,11 @@ static int ipa3_lcl_mdm_ssr_notifier_cb(struct notifier_block *this, if (!ipa3_rmnet_ctx.ipa_rmnet_ssr) return NOTIFY_DONE; + if (!ipa3_ctx) { + IPAWANERR_RL("ipa3_ctx was not initialized\n"); + return NOTIFY_DONE; + } + if (ipa3_ctx->platform_type == IPA_PLAT_TYPE_APQ) { IPAWANERR("Local modem SSR event=%lu on APQ platform\n", code); @@ -4332,6 +4337,10 @@ static int __init ipa3_wwan_init(void) struct ipa_tether_device_info *teth_ptr = NULL; void *ssr_hdl; + if (!ipa3_ctx) { + IPAWANERR_RL("ipa3_ctx was not initialized\n"); + return -EINVAL; + } rmnet_ipa3_ctx = kzalloc(sizeof(*rmnet_ipa3_ctx), GFP_KERNEL); if (!rmnet_ipa3_ctx) -- GitLab From 197568ca5724899700a1729d5b333b0ea49914c4 Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Mon, 7 Jan 2019 16:01:37 -0800 Subject: [PATCH 0879/1286] msm: IPA: reset GSI channel on wdi_disconnect In WDI3, wlan host driver will provide initial credit only one time for TX after wdi_connect, we cannot reset the GSI channel on wdi_disable case, since we will lost the credit info. If SAP is enabled but no client has been connected, the GSI state will be remained on allocated state, GSI channel reset is still required/valid in this case. Change-Id: I270849a00790a464ab47a7ab1cac995c0d7a550a Signed-off-by: Bojun Pan --- drivers/platform/msm/gsi/gsi.c | 10 ++++++-- drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c | 27 ++++++++------------ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index ad6a69cb6c29..c003f4a631e6 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2959,7 +2959,13 @@ int gsi_reset_channel(unsigned long chan_hdl) ctx = &gsi_ctx->chan[chan_hdl]; - if (ctx->state != GSI_CHAN_STATE_STOPPED) { + /* + * In WDI3 case, if SAP enabled but no client connected, + * GSI will be in allocated state. When SAP disabled, + * gsi_reset_channel will be called and reset is needed. + */ + if (ctx->state != GSI_CHAN_STATE_STOPPED && + ctx->state != GSI_CHAN_STATE_ALLOCATED) { GSIERR("bad state %d\n", ctx->state); return -GSI_STATUS_UNSUPPORTED_OP; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c index dbd6e06a6e5b..053adc78e272 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -503,6 +503,11 @@ int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx) ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx]; /* tear down tx pipe */ + result = ipa3_reset_gsi_channel(ipa_ep_idx_tx); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + return result; + } result = gsi_reset_evt_ring(ep_tx->gsi_evt_ring_hdl); if (result != GSI_STATUS_SUCCESS) { IPAERR("failed to reset evt ring: %d.\n", result); @@ -518,6 +523,11 @@ int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx) IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx); /* tear down rx pipe */ + result = ipa3_reset_gsi_channel(ipa_ep_idx_rx); + if (result != GSI_STATUS_SUCCESS) { + IPAERR("failed to reset gsi channel: %d.\n", result); + return result; + } result = gsi_reset_evt_ring(ep_rx->gsi_evt_ring_hdl); if (result != GSI_STATUS_SUCCESS) { IPAERR("failed to reset evt ring: %d.\n", result); @@ -664,21 +674,6 @@ int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx) goto fail; } - /* reset gsi rx channel */ - result = ipa3_reset_gsi_channel(ipa_ep_idx_rx); - if (result != GSI_STATUS_SUCCESS) { - IPAERR("failed to reset gsi channel: %d.\n", result); - result = -EFAULT; - goto fail; - } - /* reset gsi tx channel */ - result = ipa3_reset_gsi_channel(ipa_ep_idx_tx); - if (result != GSI_STATUS_SUCCESS) { - IPAERR("failed to reset gsi channel: %d.\n", result); - result = -EFAULT; - goto fail; - } - if (disable_force_clear) ipa3_disable_force_clear(ipa_ep_idx_rx); -- GitLab From 6e7458a4e2f36e8afcd0c65efe14913e8c73dde4 Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Sun, 13 Jan 2019 19:31:47 +0200 Subject: [PATCH 0880/1286] msm_11ad: support pcie linkdown recovery Register for MSM pci notifications and handle pci linkdown event. The recovery will be triggered by the 11ad device in its context. As part of the recovery flow PCI RC is being suspended and resumed and the 11ad device is being restarted. Change-Id: Icb0105e8f2c41f82a05e4bf4f2f42b3246d9cafe Signed-off-by: Maya Erez --- drivers/platform/msm/msm_11ad/msm_11ad.c | 135 +++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/drivers/platform/msm/msm_11ad/msm_11ad.c b/drivers/platform/msm/msm_11ad/msm_11ad.c index bd9d2e5cc052..88f56265476a 100644 --- a/drivers/platform/msm/msm_11ad/msm_11ad.c +++ b/drivers/platform/msm/msm_11ad/msm_11ad.c @@ -96,6 +96,8 @@ struct msm11ad_ctx { u32 rc_index; /* PCIE root complex index */ struct pci_dev *pcidev; struct pci_saved_state *pristine_state; + struct pci_saved_state *golden_state; + struct msm_pcie_register_event pci_event; /* SMMU */ bool use_smmu; /* have SMMU enabled? */ @@ -592,6 +594,72 @@ static int msm_11ad_suspend_power_off(void *handle) return rc; } +static int ops_pci_linkdown_recovery(void *handle) +{ + struct msm11ad_ctx *ctx = handle; + struct pci_dev *pcidev; + int rc; + + if (!ctx) { + pr_err("11ad pci_linkdown_recovery: No context\n"); + return -ENODEV; + } + + pcidev = ctx->pcidev; + + /* suspend */ + dev_dbg(ctx->dev, "11ad pci_linkdown_recovery, suspend the device\n"); + pci_disable_device(pcidev); + rc = msm_pcie_pm_control(MSM_PCIE_SUSPEND, pcidev->bus->number, + pcidev, NULL, 0); + if (rc) { + dev_err(ctx->dev, "msm_pcie_pm_control(SUSPEND) failed: %d\n", + rc); + goto out; + } + + rc = msm_11ad_turn_device_power_off(ctx); + if (rc) { + dev_err(ctx->dev, "failed to turn off device: %d\n", + rc); + goto out; + } + + /* resume */ + rc = msm_11ad_turn_device_power_on(ctx); + if (rc) + goto out; + + rc = msm_pcie_pm_control(MSM_PCIE_RESUME, pcidev->bus->number, + pcidev, NULL, 0); + if (rc) { + dev_err(ctx->dev, "msm_pcie_pm_control(RESUME) failed: %d\n", + rc); + goto err_disable_power; + } + + pci_set_power_state(pcidev, PCI_D0); + + if (ctx->golden_state) + pci_load_saved_state(pcidev, ctx->golden_state); + pci_restore_state(pcidev); + + rc = pci_enable_device(pcidev); + if (rc) { + dev_err(ctx->dev, "pci_enable_device failed (%d)\n", rc); + goto err_disable_power; + } + + pci_set_master(pcidev); + +out: + return rc; + +err_disable_power: + msm_11ad_turn_device_power_off(ctx); + return rc; +} + static int ops_suspend(void *handle, bool keep_device_power) { struct msm11ad_ctx *ctx = handle; @@ -997,6 +1065,32 @@ static void msm_11ad_init_cpu_boost(struct msm11ad_ctx *ctx) } } +static void msm_11ad_pci_event_cb(struct msm_pcie_notify *notify) +{ + struct pci_dev *pcidev = notify->user; + struct msm11ad_ctx *ctx = pcidev2ctx(pcidev); + + if (!ctx) + return; + + if (!ctx->rops.notify || !ctx->wil_handle) { + dev_info(ctx->dev, + "no registered notif CB, cannot hadle pci notifications\n"); + return; + } + + switch (notify->event) { + case MSM_PCIE_EVENT_LINKDOWN: + dev_err(ctx->dev, "PCIe linkdown\n"); + ctx->rops.notify(ctx->wil_handle, + WIL_PLATFORM_NOTIF_PCI_LINKDOWN); + break; + default: + break; + } + +} + static int msm_11ad_probe(struct platform_device *pdev) { struct msm11ad_ctx *ctx; @@ -1007,6 +1101,7 @@ static int msm_11ad_probe(struct platform_device *pdev) u32 smmu_mapping[2]; int rc, i; bool pcidev_found = false; + struct msm_pcie_register_event *pci_event; ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -1230,6 +1325,29 @@ static int msm_11ad_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ctx); device_disable_async_suspend(&pcidev->dev); + /* Save golden config space for pci linkdown recovery */ + rc = pci_save_state(pcidev); + if (rc) { + dev_err(ctx->dev, "pci_save_state failed :%d\n", rc); + goto out_suspend; + } + ctx->golden_state = pci_store_saved_state(pcidev); + + pci_event = &ctx->pci_event; + pci_event->events = MSM_PCIE_EVENT_LINKDOWN; + pci_event->user = ctx->pcidev; + pci_event->mode = MSM_PCIE_TRIGGER_CALLBACK; + pci_event->options = MSM_PCIE_CONFIG_NO_RECOVERY; + pci_event->callback = msm_11ad_pci_event_cb; + + rc = msm_pcie_register_event(pci_event); + if (rc) { + dev_err(ctx->dev, "failed to register msm pcie event: %d\n", + rc); + kfree(ctx->golden_state); + goto out_suspend; + } + list_add_tail(&ctx->list, &dev_list); msm_11ad_suspend_power_off(ctx); @@ -1265,11 +1383,13 @@ static int msm_11ad_remove(struct platform_device *pdev) { struct msm11ad_ctx *ctx = platform_get_drvdata(pdev); + msm_pcie_deregister_event(&ctx->pci_event); msm_11ad_ssr_deinit(ctx); list_del(&ctx->list); dev_info(ctx->dev, "%s: pdev %pK pcidev %pK\n", __func__, pdev, ctx->pcidev); kfree(ctx->pristine_state); + kfree(ctx->golden_state); pci_dev_put(ctx->pcidev); if (ctx->gpio_en >= 0) { @@ -1466,6 +1586,7 @@ static int ops_notify(void *handle, enum wil_platform_event evt) { struct msm11ad_ctx *ctx = (struct msm11ad_ctx *)handle; int rc = 0; + struct pci_dev *pcidev = ctx->pcidev; switch (evt) { case WIL_PLATFORM_EVT_FW_CRASH: @@ -1494,6 +1615,19 @@ static int ops_notify(void *handle, enum wil_platform_event evt) if (ctx->features & BIT(WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL)) msm_11ad_disable_clk(ctx, &ctx->rf_clk3); + + /* + * Save golden config space for pci linkdown recovery. + * golden_state is also saved after enumeration, free the old + * saved state before reallocating + */ + rc = pci_save_state(pcidev); + if (rc) { + dev_err(ctx->dev, "pci_save_state failed :%d\n", rc); + return rc; + } + kfree(ctx->golden_state); + ctx->golden_state = pci_store_saved_state(pcidev); break; default: pr_debug("%s: Unhandled event %d\n", __func__, evt); @@ -1568,6 +1702,7 @@ void *msm_11ad_dev_init(struct device *dev, struct wil_platform_ops *ops, ops->notify = ops_notify; ops->get_capa = ops_get_capa; ops->set_features = ops_set_features; + ops->pci_linkdown_recovery = ops_pci_linkdown_recovery; return ctx; } -- GitLab From 7a713f4dcdaa2eeb134004778b855727a421570e Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 24 Dec 2018 15:40:41 +0800 Subject: [PATCH 0881/1286] ARM: dts: msm: Remove inclusion of qrd base dtsi from trinker-interposer Trinker-interposer does not depend on qrd base dtsi, so remove the inclusion of qrd base dtsi. Change-Id: I511c29dc0661f702beaddedba53df36b4937f5f7 Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi index 8c290200e04c..ef0c5f386ce5 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include "sm6150-qrd.dtsi" #include #include -- GitLab From 90b05949844eddf0f76f70f0939d0bcfddb77627 Mon Sep 17 00:00:00 2001 From: Liangliang Lu Date: Mon, 14 Jan 2019 11:03:41 +0800 Subject: [PATCH 0882/1286] ARM: dts: msm: Add USB extcon handle for trinket QRD As extcon handle has been removed from Trinket base dtsi file, add extcon handle to corresponding QRD file. This extcon handle is used to receive USB vbus and ID related notifications. Change-Id: I2294cea45d5eb04ee377c45fc55c1276f5b3519b Signed-off-by: Liangliang Lu --- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 88756d7fe46a..ec41e7be9591 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -172,3 +172,7 @@ status = "ok"; }; + +&usb0 { + extcon = <&pmi632_charger>; +}; -- GitLab From 58e4f4b734beecd00615b6efd07f40e78b2b6c5c Mon Sep 17 00:00:00 2001 From: Tingwei Zhang Date: Mon, 14 Jan 2019 11:23:12 +0800 Subject: [PATCH 0883/1286] ARM: dts: msm: Correct SHRM address for DCC on Kona SHRM address in DCC link list is not correct. Update to correct value. Change-Id: Ifcdc6e3b610697f8d5e1d7c9af5ad73dbb8f5e28 Signed-off-by: Tingwei Zhang --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a6ef88ff11f4..a5715debc70c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3345,7 +3345,7 @@ , , , - , + , , , , -- GitLab From ebff0655a7c73e1acf651df213b7654e54ca9d1b Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 14 Jan 2019 12:31:46 +0800 Subject: [PATCH 0884/1286] input: touchscreen: st: update firmware without userhelper When CONFIG_FW_LOADER_USER_HELPER is set, request_firmware() falls back to the usermode helper for loading via udev which cause too long timeout (60 seconds) when the direct loading fails. By this patch, the fts firmware is updated via the request_firmware_direct but not request_firmware, which can save that uncessage timeout during every bootup. That is critical during off-mode charging. CRs-Fixed: 2236297 Change-Id: Icbebd1a5a3bbe8dc4a90aab467b4d6c614cb9edf Signed-off-by: John Zhao --- drivers/input/touchscreen/st/fts_lib/ftsFlash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/st/fts_lib/ftsFlash.c b/drivers/input/touchscreen/st/fts_lib/ftsFlash.c index 513c44dd31f9..27274222f745 100644 --- a/drivers/input/touchscreen/st/fts_lib/ftsFlash.c +++ b/drivers/input/touchscreen/st/fts_lib/ftsFlash.c @@ -144,7 +144,7 @@ int getFWdata(const char *pathToFile, u8 **data, int *size, int from) dev = getDev(); if (dev != NULL) { - res = request_firmware(&fw, pathToFile, dev); + res = request_firmware_direct(&fw, pathToFile, dev); if (res == 0) { *size = fw->size; *data = (u8 *)kmalloc_array((*size), sizeof(u8), -- GitLab From f7a39d051a10aa61809d7c0af8ab7fbbe9ba072d Mon Sep 17 00:00:00 2001 From: Tanya Dixit Date: Fri, 11 Jan 2019 17:12:15 +0530 Subject: [PATCH 0885/1286] ARM: dts: msm: Add audio DT changes for tashalite on trinket Add changes to support audio on tashalite for trinket target. Change-Id: Iff8963d8e945ff404fb35164ad637e7f46223db0 Signed-off-by: Aditya Bavanari --- .../boot/dts/qcom/trinket-audio-overlay.dtsi | 107 ++++++++++++ arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 144 ++++++++++++++++ .../trinket-tasha-codec-audio-overlay.dtsi | 57 +++++++ .../boot/dts/qcom/trinket-tasha-codec.dtsi | 159 ++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-wcd.dtsi | 29 ++++ 5 files changed, 496 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-wcd.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi index 9a81ce36b919..8dce48a95559 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -350,4 +350,111 @@ qcom,codec-lpass-clk-id = <0x30D>; #clock-cells = <1>; }; + + wcd9xxx_intc: wcd9xxx-irq { + status = "disabled"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + wcd_rst_gpio: tasha_rst_gpio { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_cdc_reset_active>; + pinctrl-1 = <&tasha_cdc_reset_sleep>; + }; + + clock_audio_native: audio_ext_clk_native { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + #clock-cells = <1>; + qcom,lpass-mclk-id = <0x116>; + qcom,codec-mclk-clk-freq = <11289600>; + qcom,audio-ref-clk-gpio = <&tlmm 112 0>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&audio_ref_clk_sleep>; + pinctrl-1 = <&audio_ref_clk_active>; + }; + + clock_audio: audio_ext_clk { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&tasha_mclk_default>; + pinctrl-1 = <&tasha_mclk_default>; + qcom,audio-ref-clk-gpio = <&pm6125_gpios 1 0>; + clock-names = "osr_clk"; + clocks = <&pm6125_clkdiv>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + }; + + dbu1: dbu1 { + compatible = "regulator-fixed"; + regulator-name = "dbu1"; + startup-delay-us = <0>; + enable-active-high; + }; +}; + +&slim_aud { + wcd9335: tasha_codec { + status = "disabled"; + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 a0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + clocks = <&clock_audio AUDIO_PMI_CLK>, + <&clock_audio_native AUDIO_LPASS_MCLK_1>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + cdc-vdd-buck-supply = <&dbu1>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&dbu1>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <200000>; + + cdc-vdd-tx-h-supply = <&dbu1>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&dbu1>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddio-1-supply = <&dbu1>; + qcom,cdc-vddio-1-voltage = <1800000 1800000>; + qcom,cdc-vddio-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 1ecf910f971b..621f8654381a 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -712,6 +712,137 @@ }; }; + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + tasha_cdc_reset_active: lpi_cdc_reset_active { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <16>; + output-high; + }; + }; + + tasha_cdc_reset_sleep: lpi_cdc_reset_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + /* Tasha WSA speaker reset pins */ + tasha_spkr_1_sd_n { + tasha_spkr_1_sd_n_sleep: tasha_spkr_1_sd_n_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + tasha_spkr_1_sd_n_active: tasha_spkr_1_sd_n_active { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + tasha_spkr_2_sd_n { + tasha_spkr_2_sd_n_sleep: tasha_spkr_2_sd_n_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + tasha_spkr_2_sd_n_active: tasha_spkr_2_sd_n_active { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + audio_ref_clk_active: audio_ref_clk_active { + mux { + pins = "gpio112"; + function = "func2"; + }; + + config { + pins = "gpio112"; + drive-strength = <8>; + bias-disable; + output-low; + }; + }; + + audio_ref_clk_sleep: audio_ref_clk_sleep { + mux { + pins = "gpio112"; + function = "func2"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + }; + }; + wcd937x_reset_active: wcd937x_reset_active { mux { pins = "gpio120"; @@ -1161,3 +1292,16 @@ }; }; }; + +&pm6125_gpios { + tasha_mclk { + tasha_mclk_default: tasha_mclk_default{ + pins = "gpio1"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi new file mode 100644 index 000000000000..d60aee9206f7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi @@ -0,0 +1,57 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "trinket-audio-overlay.dtsi" +#include "trinket-wcd.dtsi" + +&bolero { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&cdc_dmic01_gpios { + status = "disabled"; +}; + +&cdc_dmic23_gpios { + status = "disabled"; +}; + +&slim_aud { + status = "okay"; +}; + +&dai_slim { + status = "okay"; +}; + +&wcd9335 { + status = "okay"; +}; + +&clock_audio { + status = "okay"; +}; + +&clock_audio_native { + status = "okay"; +}; + +&wcd_rst_gpio { + status = "okay"; +}; + +&wcd9xxx_intc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi new file mode 100644 index 000000000000..d16b579d03e7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi @@ -0,0 +1,159 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "trinket-tasha-codec-audio-overlay.dtsi" + +&pm6125_div_clk { + status = "okay"; +}; + +&sm6150_snd { + qcom,model = "trinket-tashalite-snd-card"; + qcom,tasha_codec = <1>; + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, + <&pcm_noirq>, <&cpe3>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-cpe-lsm.3"; + asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_rx>, <&sb_5_tx>, + <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, + <&sb_8_rx>, <&sb_8_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16395", + "msm-dai-q6-dev.16396", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16400", "msm-dai-q6-dev.16401", + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mclk-freq = <9600000>; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_00211>, <&wsa881x_00212>, + <&wsa881x_00213>, <&wsa881x_00214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wsa_spkr_en2: wsa_spkr_en2_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; +}; + +&slim_aud { + status = "okay"; + tasha_codec { + swr3: swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr_master_id = <1>; + wsa881x_00211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_00212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + + wsa881x_00213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_00214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi b/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi new file mode 100644 index 000000000000..d8813c29304a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi @@ -0,0 +1,29 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_spkr_1_sd_n_active>; + pinctrl-1 = <&tasha_spkr_1_sd_n_sleep>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_spkr_2_sd_n_active>; + pinctrl-1 = <&tasha_spkr_2_sd_n_sleep>; + }; + }; +}; -- GitLab From 3b8749399c672ba4a07b86218bf9b66d1699000b Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Mon, 14 Jan 2019 11:59:36 +0530 Subject: [PATCH 0886/1286] Kconfig: add avtimer config for trinket Avtimer driver is used by camera to get timestamp from ADSP on trinket. Add required config so to enable it in defconfig. Change-Id: Ida097b0eb125f395ed7b34db0ad67a72ebdb5091 Signed-off-by: Laxminath Kasam --- drivers/soc/qcom/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8430d3dea0b..9683543ed8d0 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -702,6 +702,15 @@ config MSM_EVENT_TIMER monitor events that require the core to be awake and ready to handle the event. +config MSM_AVTIMER + tristate "Avtimer Driver" + default n + help + This driver gets the Q6 out of power collapsed state + and exposes ioctl control to read avtimer tick. + Enables camera to use for VT call to get avtimer + timestamp. + config MSM_PM depends on PM select MSM_IDLE_STATS if DEBUG_FS -- GitLab From 3236a0f892df8dfb4fd850cc8872fad19f22fb8a Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Mon, 14 Jan 2019 12:01:38 +0530 Subject: [PATCH 0887/1286] defconfig: Enable avtimer config for trinket On trinket, camera uses avtimer to query timestamp. Enable respective config for trinket target. Change-Id: Ic8a2b7db5402425f9c07f703ee7dd1dc42550354 Signed-off-by: Laxminath Kasam --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..2a5f3113712c 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -530,6 +530,7 @@ CONFIG_QTI_RPM_STATS_LOG=y CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y CONFIG_MSM_PM=y CONFIG_QCOM_FSA4480_I2C=y CONFIG_MSM_PERFORMANCE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..8e9f2e8423b0 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -558,6 +558,7 @@ CONFIG_QTI_RPM_STATS_LOG=y CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y CONFIG_MSM_PM=y CONFIG_QCOM_FSA4480_I2C=y CONFIG_MSM_PERFORMANCE=y -- GitLab From 5160078f94e86b33f0724537017a2076cdc32a67 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Thu, 3 Jan 2019 10:52:14 +0530 Subject: [PATCH 0888/1286] devfreq: return error code when governor start fails If there is a failure in starting hw monitor required for memlat governor, return the error code to devfreq framework so that the framework will make sure the governor is switched back to previous governor. Change-Id: I76705725fc8b94d5341b1b8af7c1bd2b79e7642a Signed-off-by: Santosh Mardi --- drivers/devfreq/governor_memlat.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/devfreq/governor_memlat.c b/drivers/devfreq/governor_memlat.c index 409154e770f2..50c66252ba78 100644 --- a/drivers/devfreq/governor_memlat.c +++ b/drivers/devfreq/governor_memlat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -195,7 +195,8 @@ static int gov_start(struct devfreq *df) node->orig_data = df->data; df->data = node; - if (start_monitor(df)) + ret = start_monitor(df); + if (ret) goto err_start; ret = sysfs_create_group(&df->dev.kobj, node->attr_grp); -- GitLab From 40a2069b7404e33f8c32c06c8110f25cb8ed62ef Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Fri, 11 Jan 2019 15:58:57 +0530 Subject: [PATCH 0889/1286] ARM: dts: msm: Disable Cx ipeak limit management for SA8155 Cx ipeak limit management controls CDSP and AIX subsystem clocks in concurrency to limit overall current on Cx to under buck limit. The feature is necessary on SM8150 while it's not needed due to higher buck limit on SA8155. This change disables Cx limit management for SA8155 by removing corresponding properties from SA8155 device tree. Change-Id: I7c8d6f8e80effa5de635103fa481be38e7ebb074 Acked-by: Sreekanth Gande Signed-off-by: Tharun Kumar Merugu --- arch/arm64/boot/dts/qcom/sa8155.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index 0b096c05ba64..37cc7aafcd47 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -202,6 +202,11 @@ status = "ok"; }; +&msm_cdsp_rm { + /delete-property/ qcom,compute-cx-limit-en; + /delete-property/ qcom,compute-priority-mode; +}; + &thermal_zones { aoss0-lowf { cooling-maps { -- GitLab From cebecef1564cb8fa2f6ece187b11fc1fe2fa6754 Mon Sep 17 00:00:00 2001 From: Mangesh Kunchamwar Date: Thu, 10 Jan 2019 15:50:19 +0530 Subject: [PATCH 0890/1286] clk: dt-bindings: Add support for LPASS core hw clk Add clock id for LPASS core hardware clock resource. Change-Id: I0a2ef3ce93f39717c022051bade37204a1b5dcf9 Signed-off-by: Mangesh Kunchamwar Signed-off-by: Vatsal Bucha --- include/dt-bindings/clock/qcom,audio-ext-clk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/qcom,audio-ext-clk.h b/include/dt-bindings/clock/qcom,audio-ext-clk.h index 090c7ee77903..7168a2dcb2b1 100644 --- a/include/dt-bindings/clock/qcom,audio-ext-clk.h +++ b/include/dt-bindings/clock/qcom,audio-ext-clk.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,7 +23,7 @@ #define AUDIO_LPASS_MCLK_5 6 #define AUDIO_LPASS_MCLK_6 7 #define AUDIO_LPASS_MCLK_7 8 -#define AUDIO_LPASS_NPA_RSC_ISLAND 9 +#define AUDIO_LPASS_CORE_HW_VOTE 9 #define AUDIO_EXTERNAL_PLL 10 #endif -- GitLab From b5700178c40587e1d4678bed1a6b0a22c1a6f6f1 Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Mon, 14 Jan 2019 13:54:44 +0530 Subject: [PATCH 0891/1286] msm: vidc: fix KCFI errors Fix errors reported after enabling Kernel Control Flow Integrity (KCFI) on kernel code. This is a security mechanism that disallows changes to the original control flow of a compiled binary. Change-Id: I1e1e901c5889d9928411dc785da88e1eac378560 Signed-off-by: Govindaraj Rajagopal --- .../platform/msm/vidc/hfi_response_handler.c | 61 ++++++++++++------- 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/msm/vidc/hfi_response_handler.c b/drivers/media/platform/msm/vidc/hfi_response_handler.c index 236ae0072fcd..f3dbaef88508 100644 --- a/drivers/media/platform/msm/vidc/hfi_response_handler.c +++ b/drivers/media/platform/msm/vidc/hfi_response_handler.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -366,9 +366,10 @@ static int hfi_process_session_error(u32 device_id, } static int hfi_process_event_notify(u32 device_id, - struct hfi_msg_event_notify_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_event_notify_packet *pkt = _pkt; dprintk(VIDC_DBG, "Received: EVENT_NOTIFY\n"); if (pkt->size < sizeof(struct hfi_msg_event_notify_packet)) { @@ -407,9 +408,10 @@ static int hfi_process_event_notify(u32 device_id, } static int hfi_process_sys_init_done(u32 device_id, - struct hfi_msg_sys_init_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_init_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; enum vidc_status status = VIDC_ERR_NONE; @@ -446,9 +448,10 @@ static int hfi_process_sys_init_done(u32 device_id, } static int hfi_process_sys_rel_resource_done(u32 device_id, - struct hfi_msg_sys_release_resource_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_release_resource_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; enum vidc_status status = VIDC_ERR_NONE; u32 pkt_size; @@ -1252,9 +1255,10 @@ static void hfi_process_sess_get_prop_buf_req( } static int hfi_process_session_prop_info(u32 device_id, - struct hfi_msg_session_property_info_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_property_info_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; struct buffer_requirements buff_req = { { {0} } }; @@ -1293,9 +1297,10 @@ static int hfi_process_session_prop_info(u32 device_id, } static int hfi_process_session_init_done(u32 device_id, - struct hfi_msg_sys_session_init_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_session_init_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; struct vidc_hal_session_init_done session_init_done = { {0} }; @@ -1320,9 +1325,10 @@ static int hfi_process_session_init_done(u32 device_id, } static int hfi_process_session_load_res_done(u32 device_id, - struct hfi_msg_session_load_resources_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_load_resources_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_LOAD_RESOURCES_DONE[%#x]\n", @@ -1348,9 +1354,10 @@ static int hfi_process_session_load_res_done(u32 device_id, } static int hfi_process_session_flush_done(u32 device_id, - struct hfi_msg_session_flush_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_flush_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_FLUSH_DONE[%#x]\n", @@ -1391,9 +1398,10 @@ static int hfi_process_session_flush_done(u32 device_id, } static int hfi_process_session_etb_done(u32 device_id, - struct hfi_msg_session_empty_buffer_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_empty_buffer_done_packet *pkt = _pkt; struct msm_vidc_cb_data_done data_done = {0}; struct hfi_picture_type *hfi_picture_type = NULL; @@ -1445,9 +1453,10 @@ static int hfi_process_session_etb_done(u32 device_id, } static int hfi_process_session_ftb_done( - u32 device_id, struct vidc_hal_msg_pkt_hdr *msg_hdr, + u32 device_id, void *_pkt, struct msm_vidc_cb_info *info) { + struct vidc_hal_msg_pkt_hdr *msg_hdr = _pkt; struct msm_vidc_cb_data_done data_done = {0}; bool is_decoder = false, is_encoder = false; @@ -1569,9 +1578,10 @@ static int hfi_process_session_ftb_done( } static int hfi_process_session_start_done(u32 device_id, - struct hfi_msg_session_start_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_start_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_START_DONE[%#x]\n", @@ -1595,9 +1605,10 @@ static int hfi_process_session_start_done(u32 device_id, } static int hfi_process_session_stop_done(u32 device_id, - struct hfi_msg_session_stop_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_stop_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_STOP_DONE[%#x]\n", @@ -1622,9 +1633,10 @@ static int hfi_process_session_stop_done(u32 device_id, } static int hfi_process_session_rel_res_done(u32 device_id, - struct hfi_msg_session_release_resources_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_release_resources_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_RELEASE_RESOURCES_DONE[%#x]\n", @@ -1649,9 +1661,10 @@ static int hfi_process_session_rel_res_done(u32 device_id, } static int hfi_process_session_rel_buf_done(u32 device_id, - struct hfi_msg_session_release_buffers_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_release_buffers_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; if (!pkt || pkt->size < @@ -1678,9 +1691,10 @@ static int hfi_process_session_rel_buf_done(u32 device_id, } static int hfi_process_session_register_buffer_done(u32 device_id, - struct hfi_msg_session_register_buffers_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_register_buffers_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; if (!pkt || pkt->size < @@ -1705,9 +1719,10 @@ static int hfi_process_session_register_buffer_done(u32 device_id, } static int hfi_process_session_unregister_buffer_done(u32 device_id, - struct hfi_msg_session_unregister_buffers_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_session_unregister_buffers_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; if (!pkt || pkt->size < @@ -1732,9 +1747,10 @@ static int hfi_process_session_unregister_buffer_done(u32 device_id, } static int hfi_process_session_end_done(u32 device_id, - struct hfi_msg_sys_session_end_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_session_end_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_END_DONE[%#x]\n", pkt->session_id); @@ -1757,9 +1773,10 @@ static int hfi_process_session_end_done(u32 device_id, } static int hfi_process_session_abort_done(u32 device_id, - struct hfi_msg_sys_session_abort_done_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_session_abort_done_packet *pkt = _pkt; struct msm_vidc_cb_cmd_done cmd_done = {0}; dprintk(VIDC_DBG, "RECEIVED: SESSION_ABORT_DONE[%#x]\n", @@ -1825,9 +1842,10 @@ static void hfi_process_sys_get_prop_image_version( } static int hfi_process_sys_property_info(u32 device_id, - struct hfi_msg_sys_property_info_packet *pkt, + void *_pkt, struct msm_vidc_cb_info *info) { + struct hfi_msg_sys_property_info_packet *pkt = _pkt; if (!pkt) { dprintk(VIDC_ERR, "%s: invalid param\n", __func__); return -EINVAL; @@ -1859,7 +1877,7 @@ static int hfi_process_sys_property_info(u32 device_id, } static int hfi_process_ignore(u32 device_id, - struct vidc_hal_msg_pkt_hdr *msg_hdr, + void *_pkt, struct msm_vidc_cb_info *info) { *info = (struct msm_vidc_cb_info) { @@ -1948,5 +1966,6 @@ int hfi_process_msg_packet(u32 device_id, struct vidc_hal_msg_pkt_hdr *msg_hdr, break; } - return pkt_func ? pkt_func(device_id, msg_hdr, info) : -ENOTSUPP; + return pkt_func ? + pkt_func(device_id, (void *)msg_hdr, info) : -ENOTSUPP; } -- GitLab From a895157030945ac6267ca534e9a59b40bcd5414d Mon Sep 17 00:00:00 2001 From: Arun Kumar Neelakantam Date: Mon, 7 Jan 2019 19:44:29 +0530 Subject: [PATCH 0892/1286] soc: qcom: glink_probe: Defer SSR unregister Calling SSR unregister for other peripherals from glink_ssr device remove call back results in deadlock if multiple SSRs happens in parallel. SSR unregister is defer to other worker to avoid notifier SRCU deadlock. Change-Id: Ifa5c461201eec4b4beb8bf405bd0a2904a2cc90f Signed-off-by: Arun Kumar Neelakantam --- drivers/soc/qcom/glink_probe.c | 37 +++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/glink_probe.c b/drivers/soc/qcom/glink_probe.c index e491c19aacfd..22b2e25b60c8 100644 --- a/drivers/soc/qcom/glink_probe.c +++ b/drivers/soc/qcom/glink_probe.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -77,6 +77,7 @@ struct glink_ssr { u32 seq_num; struct completion completion; + struct work_struct unreg_work; }; struct edge_info { @@ -94,6 +95,20 @@ struct edge_info { }; LIST_HEAD(edge_infos); +static void glink_ssr_ssr_unreg_work(struct work_struct *work) +{ + struct glink_ssr *ssr = container_of(work, struct glink_ssr, + unreg_work); + struct glink_ssr_nb *nb, *tmp; + + list_for_each_entry_safe(nb, tmp, &ssr->notify_list, list) { + subsys_notif_unregister_notifier(nb->ssr_register_handle, + &nb->nb); + kfree(nb); + } + kfree(ssr); +} + static int glink_ssr_ssr_cb(struct notifier_block *this, unsigned long code, void *data) { @@ -103,6 +118,9 @@ static int glink_ssr_ssr_cb(struct notifier_block *this, struct do_cleanup_msg msg; int ret; + if (!dev || !ssr->ept) + return NOTIFY_DONE; + if (code == SUBSYS_AFTER_SHUTDOWN) { ssr->seq_num++; reinit_completion(&ssr->completion); @@ -179,7 +197,7 @@ static void glink_ssr_init_notify(struct glink_ssr *ssr) if (!node) break; - nb = devm_kzalloc(dev, sizeof(*nb), GFP_KERNEL); + nb = kzalloc(sizeof(*nb), GFP_KERNEL); if (!nb) return; @@ -192,6 +210,7 @@ static void glink_ssr_init_notify(struct glink_ssr *ssr) if (ret < 0) { GLINK_ERR(dev, "no qcom,glink-label for %s\n", nb->ssr_label); + kfree(nb); continue; } @@ -202,6 +221,7 @@ static void glink_ssr_init_notify(struct glink_ssr *ssr) if (IS_ERR_OR_NULL(handle)) { GLINK_ERR(dev, "register fail for %s SSR notifier\n", nb->ssr_label); + kfree(nb); continue; } @@ -215,12 +235,13 @@ static int glink_ssr_probe(struct rpmsg_device *rpdev) { struct glink_ssr *ssr; - ssr = devm_kzalloc(&rpdev->dev, sizeof(*ssr), GFP_KERNEL); + ssr = kzalloc(sizeof(*ssr), GFP_KERNEL); if (!ssr) return -ENOMEM; INIT_LIST_HEAD(&ssr->notify_list); init_completion(&ssr->completion); + INIT_WORK(&ssr->unreg_work, glink_ssr_ssr_unreg_work); ssr->dev = &rpdev->dev; ssr->ept = rpdev->ept; @@ -235,14 +256,12 @@ static int glink_ssr_probe(struct rpmsg_device *rpdev) static void glink_ssr_remove(struct rpmsg_device *rpdev) { struct glink_ssr *ssr = dev_get_drvdata(&rpdev->dev); - struct glink_ssr_nb *nb; - - list_for_each_entry(nb, &ssr->notify_list, list) { - subsys_notif_unregister_notifier(nb->ssr_register_handle, - &nb->nb); - } + ssr->dev = NULL; + ssr->ept = NULL; dev_set_drvdata(&rpdev->dev, NULL); + + schedule_work(&ssr->unreg_work); } static const struct rpmsg_device_id glink_ssr_match[] = { -- GitLab From 56f42fa04c527604c5f33cef4deb5879c5a355c8 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Thu, 20 Dec 2018 23:14:43 +0530 Subject: [PATCH 0893/1286] ARM: dts: msm: Add clock node entry for LPASS hw vote Add support for LPASS core hw voting as clock node and expose clock ops for clients like LPI pinctrl driver to vote. LPI driver vote using this node before accessing LPASS TLMM registers. Change-Id: I5eb77e450c7fbe3c3d5a681edbe50a65d6dfdb2e Signed-off-by: Vatsal Bucha --- arch/arm64/boot/dts/qcom/sm6150-audio.dtsi | 9 ++++++++- arch/arm64/boot/dts/qcom/sm6150-lpi.dtsi | 5 ++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-audio.dtsi b/arch/arm64/boot/dts/qcom/sm6150-audio.dtsi index 3ba096bcfeb3..6dcc4d2842bd 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-audio.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,6 +12,7 @@ */ #include "msm-audio-lpass.dtsi" +#include "dt-bindings/clock/qcom,audio-ext-clk.h" &msm_audio_ion { iommus = <&apps_smmu 0x1721 0x0>; @@ -27,6 +28,12 @@ qcom,clk-div = <192>; qcom,clk-mult = <10>; }; + + lpass_core_hw_vote: lpass_core_hw_vote { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; }; &audio_apr { diff --git a/arch/arm64/boot/dts/qcom/sm6150-lpi.dtsi b/arch/arm64/boot/dts/qcom/sm6150-lpi.dtsi index 06d05f937577..0ba90fc4450f 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-lpi.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-lpi.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -35,6 +35,9 @@ <0x0001C000>, <0x0001D000>, <0x0001E000>, <0x0001F000>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + lpi_wcd934x_reset_active: lpi_wcd934x_reset_active { mux { pins = "gpio29"; -- GitLab From 46981d4c6add88ab87e824a7e0782a980e1ff83c Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 11 Jan 2019 14:04:21 +0530 Subject: [PATCH 0894/1286] ARM: dts: msm: Add the phandle of crypto core for PIL's on Trinket Add the phandle entry of bus master crypto core for PIL's like (lpass, turing, mss, venus) for Trinket. Change-Id: I3ecb78c663be2cd403ead9bd3c4f4bad6e56743b Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/trinket.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index e60f8243c71f..11bbdd820bb9 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1056,6 +1056,7 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; qcom,proxy-reg-names = "vdd_cx"; qcom,firmware-name = "modem"; @@ -1176,6 +1177,7 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>; clock-names = "xo"; @@ -1215,6 +1217,7 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>; clock-names = "xo"; @@ -2134,6 +2137,7 @@ vdd-supply = <&venus_gdsc>; qcom,proxy-reg-names = "vdd"; + qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, -- GitLab From cc1a80861e29a5c20d86128273ff265b779cbe8e Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Sun, 13 Jan 2019 21:00:16 +0530 Subject: [PATCH 0895/1286] power: smb5-lib: Cancel alarm_timer conditionally Cancel the alarm timer and work only if the charger termination workaround is enabled to avoid a NULL pointer exception. Change-Id: I573239db0f373d9188fc379653cedd305d2a552c Signed-off-by: Anirudh Ghayal --- drivers/power/supply/qcom/smb5-lib.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index c45a4bab3998..36a4c74f347a 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -1085,7 +1085,9 @@ static void smblib_uusb_removal(struct smb_charger *chg) false); cancel_delayed_work_sync(&chg->pl_enable_work); - alarm_cancel(&chg->chg_termination_alarm); + + if (chg->wa_flags & CHG_TERMINATION_WA) + alarm_cancel(&chg->chg_termination_alarm); if (chg->wa_flags & BOOST_BACK_WA) { data = chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data; @@ -5020,7 +5022,9 @@ static void typec_src_removal(struct smb_charger *chg) } cancel_delayed_work_sync(&chg->pl_enable_work); - alarm_cancel(&chg->chg_termination_alarm); + + if (chg->wa_flags & CHG_TERMINATION_WA) + alarm_cancel(&chg->chg_termination_alarm); /* reset input current limit voters */ vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, @@ -6455,11 +6459,13 @@ int smblib_deinit(struct smb_charger *chg) alarm_cancel(&chg->moisture_protection_alarm); cancel_work_sync(&chg->moisture_protection_work); } - alarm_cancel(&chg->chg_termination_alarm); + if (chg->wa_flags & CHG_TERMINATION_WA) { + alarm_cancel(&chg->chg_termination_alarm); + cancel_work_sync(&chg->chg_termination_work); + } cancel_work_sync(&chg->bms_update_work); cancel_work_sync(&chg->jeita_update_work); cancel_work_sync(&chg->pl_update_work); - cancel_work_sync(&chg->chg_termination_work); cancel_delayed_work_sync(&chg->clear_hdc_work); cancel_delayed_work_sync(&chg->icl_change_work); cancel_delayed_work_sync(&chg->pl_enable_work); -- GitLab From 0fc8d8baff986c36580e7f45d9bf4870c1811203 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Mon, 14 Jan 2019 17:45:14 +0530 Subject: [PATCH 0896/1286] ARM: dts: msm: Update WLAN configuration for trinket Adding smmu, sids, smp2p interrupts for error fatal and early indication and vreg configuration to enable wlan for trinket. Change-Id: Ib4f15528d5653002a98b6741df997f99add043fb Signed-off-by: Sandeep Singh --- arch/arm64/boot/dts/qcom/trinket.dtsi | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index c87f2f5764ac..f3644d9224da 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -794,10 +794,12 @@ }; icnss: qcom,icnss@C800000 { - status = "disabled"; compatible = "qcom,icnss"; - reg = <0xC800000 0x800000>; - reg-names = "membase"; + reg = <0xC800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; interrupts = <0 358 0 /* CE0 */ >, <0 359 0 /* CE1 */ >, <0 360 0 /* CE2 */ >, @@ -813,6 +815,18 @@ qcom,smmu-s1-bypass; qcom,wlan-msa-memory = <0x100000>; qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&L8A>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L17A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; arm64-cpu-erp { @@ -1722,6 +1736,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; qcom,smp2p-adsp { -- GitLab From acaf70232a152078e3c9720acbb741be8f1be29d Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Mon, 7 Jan 2019 15:39:56 +0530 Subject: [PATCH 0897/1286] power: qpnp-qg: Cap the FULL SOC to 99 FULL SOC is expected to be capped @ 99% for system SOC calculations. Change-Id: I5f99223ff55b1831793066c432d04ed60823881c Signed-off-by: Anirudh Ghayal --- drivers/power/supply/qcom/qpnp-qg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c index 4eb84527769d..d6951895f989 100644 --- a/drivers/power/supply/qcom/qpnp-qg.c +++ b/drivers/power/supply/qcom/qpnp-qg.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2818,6 +2818,7 @@ static int qg_determine_pon_soc(struct qpnp_qg *chip) pr_err("Failed to lookup FULL_SOC@PON rc=%d\n", rc); goto done; } + full_soc = CAP(0, 99, full_soc); rc = lookup_soc_ocv(&cutoff_soc, chip->dt.vbatt_cutoff_mv * 1000, @@ -2835,7 +2836,7 @@ static int qg_determine_pon_soc(struct qpnp_qg *chip) qg_dbg(chip, QG_DEBUG_PON, "v_float=%d v_cutoff=%d FULL_SOC=%d CUTOFF_SOC=%d PON_SYS_SOC=%d pon_soc=%d\n", chip->bp.float_volt_uv, chip->dt.vbatt_cutoff_mv * 1000, - full_soc, cutoff_soc, pon_soc, soc); + full_soc, cutoff_soc, soc, pon_soc); } done: if (rc < 0) { -- GitLab From 6f6e68da5cf7254ccc276bddbb440bedae6d5c78 Mon Sep 17 00:00:00 2001 From: jiad Date: Tue, 15 Jan 2019 02:00:04 +0800 Subject: [PATCH 0898/1286] defconfig: sdxprairie: Add memory dump v2 feature Add memory dump v2 feature support. Change-Id: I00b1ba99069a5c7b4e7c5fde1de519d8ebb02d14 Signed-off-by: jiad --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index baf64b1de4ef..e5a48296c7ce 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -327,6 +327,7 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index be0518d93bf0..8ba4048ecd11 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -317,6 +317,7 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y -- GitLab From f21e4eecb77a0e25d32fc95b6a4be2d71ee1cfb2 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Thu, 10 Jan 2019 11:57:52 -0800 Subject: [PATCH 0899/1286] ARM: dts: msm: Add device tree for sa8155 virtual machine pinctrl Add the initial device tree for sa8155 virtual machine pinctrl. This device tree will be needed to use tlmm GPIOs. Change-Id: I89ee787fc86943c2d050840b8763411daed3b406 Signed-off-by: Anant Goel --- .../boot/dts/qcom/sa8155-vm-pinctrl.dtsi | 25 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8155-vm.dtsi | 7 +++++- 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi new file mode 100644 index 000000000000..919fcc057493 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm8150-pinctrl"; + reg = <0x03000000 0xdc2000>; + reg-names = "pinctrl"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi index 1e1b9691bade..c5a9d7d583b2 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #include "skeleton64.dtsi" +#include +#include / { model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; @@ -67,6 +69,7 @@ &soc { #address-cells = <1>; #size-cells = <1>; + virtual-interrupt-parent = "gic"; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; @@ -157,3 +160,5 @@ qcom,client-id = "7815"; }; }; + +#include "sa8155-vm-pinctrl.dtsi" -- GitLab From da0b863566529f3b926923b7117d3f6cc1c79537 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Mon, 14 Jan 2019 11:24:00 -0800 Subject: [PATCH 0900/1286] power: qpnp-fg-gen4: Support configure skew in capacity learning algorithm Capacity learning algorithm takes in a parameter to configure skew if when specified by the user to offset the errors that can be accumulated based on the charging nature. Add a device tree parameter "qcom,cl-skew" to configure it. CRs-Fixed: 2380759 Change-Id: Ib50b175a6079261627e4038811980329e3c66668 Signed-off-by: Subbaraman Narayanamurthy --- .../devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt | 6 ++++++ drivers/power/supply/qcom/qpnp-fg-gen4.c | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt index c9ccd156c8f2..19ff4f5966fc 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt @@ -269,6 +269,12 @@ First Level Node - FG Gen4 device based on change in battery SOC during a charging cycle. If this is specified "qcom,cl-start-capacity" is not used. +- qcom,cl-skew + Usage: optional + Value type: + Definition: Skew in decipercentage which when specified will be applied + to the final learned capacity. + - qcom,hold-soc-while-full Usage: optional Value type: diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index e0bc018a0e59..bb0a7d9c37cc 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -4628,6 +4628,8 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) else chip->cl->dt.max_cap_limit = temp; + of_property_read_u32(node, "qcom,cl-skew", &chip->cl->dt.skew_decipct); + rc = of_property_read_u32(node, "qcom,fg-batt-temp-hot", &temp); if (rc < 0) chip->dt.batt_temp_hot_thresh = -EINVAL; -- GitLab From 79d02aa5d487c49e0b86e9d26012c6cd7606279b Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Fri, 11 Jan 2019 14:23:05 -0800 Subject: [PATCH 0901/1286] msm: ipa: Adjust resource allocations for IPA groups Adjust resource allocations for IPA groups per architecture team recommendations. Change-Id: I6e25a70800de2bfa6c7033774affea6302334b30 Signed-off-by: Ghanim Fodi --- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 2296eb4a6f6a..d9212957e057 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -395,7 +395,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { {0, 0}, {18, 18}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { - {0, 0}, {0, 63}, {0, 0}, {0, 0}, {0, 63}, {0, 0} }, + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { {0, 0}, {24, 24}, {0, 0}, {0, 0}, {8, 8}, {0, 0} }, }, @@ -408,7 +408,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = { {9, 9}, {14, 14}, {4, 4}, {4, 4}, {0, 0}, {0, 0} }, [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = { - {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0}, {0, 0} }, + {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 63}, {0, 0} }, [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = { {22, 22}, {16, 16}, {6, 6}, {2, 2}, {0, 0}, {0, 0} }, }, @@ -484,9 +484,9 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config [IPA_4_5] = { /* UL/DL/DPL_DST unused unused unused uC N/A */ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = { - {16, 16}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, + {16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} }, [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = { - {2, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 2}, {0, 0} }, + {2, 63}, {1, 63}, {1, 2}, {1, 2}, {0, 2}, {0, 0} }, }, [IPA_4_5_MHI] = { /* PCIE/DPL DDR DMA/CV2X QDSS uC N/A */ -- GitLab From c6efa3f2ea43c5b748224a6c5d3637852729516e Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Tue, 4 Dec 2018 14:30:01 -0800 Subject: [PATCH 0902/1286] ARM: dts: msm: Add GPU coresight properties for SM8150 Add GPU GX and CX coresight devicetree nodes. Define GPU coresight names, ATIDs, and their funnel connections. Include QDSS_GFX_DBG memory mapping in kgsl-3d0 node to access those registers through coresight interface. Change-Id: If3231029961788926793f9596f9dcda592825661 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- .../arm64/boot/dts/qcom/sm8150-coresight.dtsi | 57 +++++++++++++++++-- arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi | 35 +++++++++++- 2 files changed, 85 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi index 812a8e10ed34..2edf25562791 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi @@ -635,7 +635,6 @@ ports { #address-cells = <1>; #size-cells = <0>; - port@0 { reg = <0>; funnel_in2_out_funnel_merg: endpoint { @@ -643,18 +642,24 @@ <&funnel_merg_in_funnel_in2>; }; }; - port@1 { - reg = <2>; + reg = <1>; funnel_in2_in_funnel_apss_merg: endpoint { slave-mode; remote-endpoint = <&funnel_apss_merg_out_funnel_in2>; }; - }; port@2 { - reg = <4>; + reg = <2>; + funnel_in2_in_funnel_gfx: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gfx_out_funnel_in2>; + }; + }; + port@3 { + reg = <3>; funnel_in2_in_tpda_modem: endpoint { slave-mode; remote-endpoint = @@ -664,6 +669,48 @@ }; }; + funnel_gfx: funnel@0x6943000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6943000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_gfx>; + }; + }; + port@1 { + reg = <1>; + funnel_gfx_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_gfx>; + }; + }; + port@2 { + reg = <2>; + funnel_gfx_in_gfx_cx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_cx_out_funnel_gfx>; + }; + }; + }; + }; + tpda: tpda@6004000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b969>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi b/arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi index 4ef8eb9f00e5..4bde423f7a34 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi @@ -67,8 +67,9 @@ label = "kgsl-3d0"; compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; status = "ok"; - reg = <0x2c00000 0x40000>, <0x2c61000 0x800>; - reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; + reg = <0x2c00000 0x40000>, <0x2c61000 0x800>, + <0x6900000 0x44000>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "qdss_gfx"; interrupts = <0 300 0>; interrupt-names = "kgsl_3d0_irq"; qcom,id = <0>; @@ -147,6 +148,36 @@ cache-slice-names = "gpu", "gpuhtw"; cache-slices = <&llcc 12>, <&llcc 11>; + + qcom,gpu-coresights { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-coresight"; + + qcom,gpu-coresight@0 { + reg = <0>; + coresight-name = "coresight-gfx"; + coresight-atid = <50>; + port { + gfx_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gfx>; + }; + }; + }; + qcom,gpu-coresight@1 { + reg = <1>; + coresight-name = "coresight-gfx-cx"; + coresight-atid = <51>; + port { + gfx_cx_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gfx_cx>; + }; + }; + }; + }; + qcom,l3-pwrlevels { #address-cells = <1>; #size-cells = <0>; -- GitLab From efd1feba4e38136111140e176d41db8452dfd960 Mon Sep 17 00:00:00 2001 From: Junzhe Zou Date: Wed, 19 Dec 2018 17:40:17 -0800 Subject: [PATCH 0903/1286] msm: camera: ife: clean up HW manager sequence Correct stop sequence and add error handling in start. Change-Id: Icfc098c2b1870e99ad705a7168a38715bf4ae1f9 Signed-off-by: Junzhe Zou --- .../cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 57 +++++++++---------- 1 file changed, 26 insertions(+), 31 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 1f896e56604a..28e96a741bf7 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -2360,8 +2360,9 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, } } - CAM_DBG(CAM_ISP, "Enter ctx id:%d req_id:%lld num_hw_upd_entries %d", - ctx->ctx_index, cfg->request_id, cfg->num_hw_update_entries); + CAM_DBG(CAM_ISP, + "Enter ctx id:%d num_hw_upd_entries %d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); if (cfg->num_hw_update_entries > 0) { cdm_cmd = ctx->cdm_cmd; @@ -2408,7 +2409,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, } else { CAM_ERR(CAM_ISP, "No commands to config"); } - CAM_DBG(CAM_ISP, "Exit"); + CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); return rc; } @@ -2588,23 +2589,6 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) CAM_DBG(CAM_ISP, "Halting CSIDs"); - CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); - - /* IFE mux in resources */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { - cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); - } - - /* IFE bus rd resources */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { - cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); - } - - CAM_DBG(CAM_ISP, "Going to stop IFE Out"); - - /* IFE out resources */ - for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) - cam_ife_hw_mgr_stop_hw_res(&ctx->res_list_ife_out[i]); /* get master base index first */ for (i = 0; i < ctx->num_base; i++) { if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { @@ -2613,15 +2597,6 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) } } - CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); - - /* IFE mux in resources */ - list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { - cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); - } - - cam_tasklet_stop(ctx->common.tasklet_info); - /* * If Context does not have PIX resources and has only RDI resource * then take the first base index. @@ -2661,6 +2636,26 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) ctx->base[i].idx, csid_halt_type); } + CAM_DBG(CAM_ISP, "Going to stop IFE Out"); + + /* IFE out resources */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) + cam_ife_hw_mgr_stop_hw_res(&ctx->res_list_ife_out[i]); + + /* IFE bus rd resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); + + /* IFE mux in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + cam_tasklet_stop(ctx->common.tasklet_info); + cam_ife_mgr_pause_hw(ctx); if (stop_isp->stop_only) @@ -2982,7 +2977,6 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) deinit_hw: cam_ife_hw_mgr_deinit_hw(ctx); - ctx->init_done = false; tasklet_stop: cam_tasklet_stop(ctx->common.tasklet_info); @@ -3828,7 +3822,8 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, if (!io_cfg[i].mem_handle[j]) break; - if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + if (pf_buf_info && + GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == GET_FD_FROM_HANDLE(pf_buf_info)) { CAM_INFO(CAM_ISP, "Found PF at port: 0x%x mem 0x%x fd: 0x%x", -- GitLab From f8872ac1149ab2f21b243809c20b607933aa2208 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 9 Jan 2019 17:31:27 -0800 Subject: [PATCH 0904/1286] ARM: dts: msm: Enable bus suspend only for sm8150-sdx50m Bus suspend is enabled by default on secondary usb port for all sm8150 variants which is not required. Enable it only for sm8150-sdx50m. Change-Id: I11f0adde36ec2fd6d1d1c844243225a5bf813861 Signed-off-by: Hemant Kumar --- arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi | 8 +++++++- arch/arm64/boot/dts/qcom/sm8150-usb.dtsi | 3 +-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi index 86fcb7b67c67..87b39f37abf4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -487,3 +487,9 @@ no-map; }; }; + +&usb1 { + dwc3@a800000 { + snps,bus-suspend-enable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi index ec42091e8d01..69dc14ede189 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -420,7 +420,6 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - snps,bus-suspend-enable; usb-core-id = <1>; maximum-speed = "super-speed"; dr_mode = "otg"; -- GitLab From 7c3bed629e44aa3295dff890f0651acfd2aec847 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 8 Jan 2019 16:53:29 -0800 Subject: [PATCH 0905/1286] soc: qcom: ramdump: Rework multiple reader synchronization The synchronization for multiple readers makes it so that if a reader opens a ramdump_* node, and tries to close it without reading the contents, and while there is a ramdump in progress, then that thread will have to wait until the thread that initiated the response times out. This is because the implementation assumes that the only condition by which consumers can finish their work with the ramdump, and wake the ramdump thread is by reading the ramdump. This is not correct, as the ramdump node can also be closed at any time, including during the time that a ramdump is being read. Rework the implementation to consider both reading the ramdump, and closing the ramdump nodes as conditions that can result in waking the ramdump thread, and fix the synchronization so that if threads want to open/close the nodes, and there is a ramdump in progress, they need not wait for that ramdump to finish. Change-Id: I6135342492081092de58362387807da29c5568d7 Signed-off-by: Isaac J. Manjarres --- drivers/soc/qcom/ramdump.c | 76 +++++++++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 22 deletions(-) diff --git a/drivers/soc/qcom/ramdump.c b/drivers/soc/qcom/ramdump.c index 5364474976d7..62b020437d77 100644 --- a/drivers/soc/qcom/ramdump.c +++ b/drivers/soc/qcom/ramdump.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -52,7 +52,7 @@ struct ramdump_device { char name[256]; unsigned int consumers; - atomic_t readers_done; + atomic_t readers_left; int ramdump_status; struct completion ramdump_complete; @@ -90,6 +90,15 @@ static int ramdump_open(struct inode *inode, struct file *filep) return 0; } +static void reset_ramdump_entry(struct consumer_entry *entry) +{ + struct ramdump_device *rd_dev = entry->rd_dev; + + entry->data_ready = false; + if (atomic_dec_return(&rd_dev->readers_left) == 0) + complete(&rd_dev->ramdump_complete); +} + static int ramdump_release(struct inode *inode, struct file *filep) { @@ -98,6 +107,13 @@ static int ramdump_release(struct inode *inode, struct file *filep) struct consumer_entry *entry = filep->private_data; mutex_lock(&rd_dev->consumer_lock); + /* + * Avoid double decrementing in cases where we finish reading the dump + * and then close the file, but there are other readers that have not + * yet finished. + */ + if (entry->data_ready) + reset_ramdump_entry(entry); rd_dev->consumers--; list_del(&entry->list); mutex_unlock(&rd_dev->consumer_lock); @@ -257,11 +273,7 @@ static ssize_t ramdump_read(struct file *filep, char __user *buf, size_t count, kfree(finalbuf); *pos = 0; - entry->data_ready = false; - if (atomic_inc_return(&rd_dev->readers_done) == rd_dev->consumers) { - atomic_set(&rd_dev->readers_done, 0); - complete(&rd_dev->ramdump_complete); - } + reset_ramdump_entry(entry); return ret; } @@ -362,7 +374,7 @@ void *create_ramdump_device(const char *dev_name, struct device *parent) } mutex_init(&rd_dev->consumer_lock); - atomic_set(&rd_dev->readers_done, 0); + atomic_set(&rd_dev->readers_left, 0); cdev_init(&rd_dev->cdev, &ramdump_file_ops); ret = cdev_add(&rd_dev->cdev, MKDEV(MAJOR(ramdump_dev), minor), 1); @@ -410,13 +422,24 @@ static int _do_ramdump(void *handle, struct ramdump_segment *segments, Elf32_Ehdr *ehdr; unsigned long offset; + /* + * Acquire the consumer lock here, and hold the lock until we are done + * preparing the data structures required for the ramdump session, and + * have woken all readers. This essentially freezes the current readers + * when the lock is taken here, such that the readers at that time are + * the only ones that will participate in the ramdump session. After + * the current list of readers has been awoken, new readers that add + * themselves to the reader list will not participate in the current + * ramdump session. This allows for the lock to be free while the + * ramdump is occuring, which prevents stalling readers who want to + * close the ramdump node or new readers that want to open it. + */ mutex_lock(&rd_dev->consumer_lock); if (!rd_dev->consumers) { pr_err("Ramdump(%s): No consumers. Aborting..\n", rd_dev->name); mutex_unlock(&rd_dev->consumer_lock); return -EPIPE; } - mutex_unlock(&rd_dev->consumer_lock); if (rd_dev->complete_ramdump) { for (i = 0; i < nsegments-1; i++) @@ -432,8 +455,10 @@ static int _do_ramdump(void *handle, struct ramdump_segment *segments, sizeof(*phdr) * nsegments; ehdr = kzalloc(rd_dev->elfcore_size, GFP_KERNEL); rd_dev->elfcore_buf = (char *)ehdr; - if (!rd_dev->elfcore_buf) + if (!rd_dev->elfcore_buf) { + mutex_unlock(&rd_dev->consumer_lock); return -ENOMEM; + } memcpy(ehdr->e_ident, ELFMAG, SELFMAG); ehdr->e_ident[EI_CLASS] = ELFCLASS32; @@ -459,15 +484,16 @@ static int _do_ramdump(void *handle, struct ramdump_segment *segments, } } - mutex_lock(&rd_dev->consumer_lock); list_for_each_entry(entry, &rd_dev->consumer_list, list) entry->data_ready = true; rd_dev->ramdump_status = -1; reinit_completion(&rd_dev->ramdump_complete); + atomic_set(&rd_dev->readers_left, rd_dev->consumers); /* Tell userspace that the data is ready */ wake_up(&rd_dev->dump_wait_q); + mutex_unlock(&rd_dev->consumer_lock); /* Wait (with a timeout) to let the ramdump complete */ ret = wait_for_completion_timeout(&rd_dev->ramdump_complete, @@ -480,13 +506,9 @@ static int _do_ramdump(void *handle, struct ramdump_segment *segments, } else ret = (rd_dev->ramdump_status == 0) ? 0 : -EPIPE; - list_for_each_entry(entry, &rd_dev->consumer_list, list) - entry->data_ready = false; rd_dev->elfcore_size = 0; - atomic_set(&rd_dev->readers_done, 0); kfree(rd_dev->elfcore_buf); rd_dev->elfcore_buf = NULL; - mutex_unlock(&rd_dev->consumer_lock); return ret; } @@ -519,13 +541,24 @@ static int _do_minidump(void *handle, struct ramdump_segment *segments, struct elf_shdr *shdr; unsigned long offset, strtbl_off; + /* + * Acquire the consumer lock here, and hold the lock until we are done + * preparing the data structures required for the ramdump session, and + * have woken all readers. This essentially freezes the current readers + * when the lock is taken here, such that the readers at that time are + * the only ones that will participate in the ramdump session. After + * the current list of readers has been awoken, new readers that add + * themselves to the reader list will not participate in the current + * ramdump session. This allows for the lock to be free while the + * ramdump is occuring, which prevents stalling readers who want to + * close the ramdump node or new readers that want to open it. + */ mutex_lock(&rd_dev->consumer_lock); if (!rd_dev->consumers) { pr_err("Ramdump(%s): No consumers. Aborting..\n", rd_dev->name); mutex_unlock(&rd_dev->consumer_lock); return -EPIPE; } - mutex_unlock(&rd_dev->consumer_lock); rd_dev->segments = segments; rd_dev->nsegments = nsegments; @@ -534,8 +567,10 @@ static int _do_minidump(void *handle, struct ramdump_segment *segments, (sizeof(*shdr) * (nsegments + 2)) + MAX_STRTBL_SIZE; ehdr = kzalloc(rd_dev->elfcore_size, GFP_KERNEL); rd_dev->elfcore_buf = (char *)ehdr; - if (!rd_dev->elfcore_buf) + if (!rd_dev->elfcore_buf) { + mutex_unlock(&rd_dev->consumer_lock); return -ENOMEM; + } memcpy(ehdr->e_ident, ELFMAG, SELFMAG); ehdr->e_ident[EI_CLASS] = ELF_CLASS; @@ -576,15 +611,16 @@ static int _do_minidump(void *handle, struct ramdump_segment *segments, } ehdr->e_shnum = nsegments + 2; - mutex_lock(&rd_dev->consumer_lock); list_for_each_entry(entry, &rd_dev->consumer_list, list) entry->data_ready = true; rd_dev->ramdump_status = -1; reinit_completion(&rd_dev->ramdump_complete); + atomic_set(&rd_dev->readers_left, rd_dev->consumers); /* Tell userspace that the data is ready */ wake_up(&rd_dev->dump_wait_q); + mutex_unlock(&rd_dev->consumer_lock); /* Wait (with a timeout) to let the ramdump complete */ ret = wait_for_completion_timeout(&rd_dev->ramdump_complete, @@ -598,13 +634,9 @@ static int _do_minidump(void *handle, struct ramdump_segment *segments, ret = (rd_dev->ramdump_status == 0) ? 0 : -EPIPE; } - list_for_each_entry(entry, &rd_dev->consumer_list, list) - entry->data_ready = false; rd_dev->elfcore_size = 0; - atomic_set(&rd_dev->readers_done, 0); kfree(rd_dev->elfcore_buf); rd_dev->elfcore_buf = NULL; - mutex_unlock(&rd_dev->consumer_lock); return ret; } -- GitLab From 899898dc61b24f61b2ad94393290973d0cb9c950 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Tue, 18 Dec 2018 20:16:33 -0800 Subject: [PATCH 0906/1286] power: qpnp-fg-gen4: Support profile loading based on battery age level Add support for multiple profile loading based on battery age level. User can select a profile based on batt_age_level property runtime. If a valid profile exists for the battery age level, it will be loaded. By default, a profile with age level 0 will be loaded if the feature is enabled. Change-Id: Ic52bf77a15f4aa16f6d3da058b0b26043879e3a1 Signed-off-by: Subbaraman Narayanamurthy --- .../power/supply/qcom/qpnp-fg-gen4.txt | 8 + drivers/power/supply/qcom/qpnp-fg-gen4.c | 212 +++++++++++++----- 2 files changed, 159 insertions(+), 61 deletions(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt index c9ccd156c8f2..d89b3315ac9f 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt @@ -397,6 +397,14 @@ First Level Node - FG Gen4 device five pin battery is used. Based on this, time to full calculations would use the Rbatt calculated properly. +- qcom,multi-profile-load + Usage: optional + Value type: + Definition: A boolean property that when specified indicates that + multiple profile loading needs to be enabled. This requires + multiple battery profiles to be specified for a battery for + proper functionality. + ========================================================== Second Level Nodes - Peripherals managed by FG Gen4 driver ========================================================== diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index e0bc018a0e59..0920dcc85604 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -116,6 +116,8 @@ #define RCONN_OFFSET 0 #define ACT_BATT_CAP_WORD 285 #define ACT_BATT_CAP_OFFSET 0 +#define BATT_AGE_LEVEL_WORD 288 +#define BATT_AGE_LEVEL_OFFSET 0 #define CYCLE_COUNT_WORD 291 #define CYCLE_COUNT_OFFSET 0 #define PROFILE_INTEGRITY_WORD 299 @@ -190,6 +192,7 @@ struct fg_dt_props { bool linearize_soc; bool rapid_soc_dec_en; bool five_pin_battery; + bool multi_profile_load; int cutoff_volt_mv; int empty_volt_mv; int cutoff_curr_ma; @@ -249,6 +252,8 @@ struct fg_gen4_chip { int esr_nominal; int soh; int esr_soh_cycle_count; + int batt_age_level; + int last_batt_age_level; bool first_profile_load; bool ki_coeff_dischg_en; bool slope_limit_en; @@ -1323,7 +1328,7 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) struct device_node *node = fg->dev->of_node; struct device_node *batt_node, *profile_node; const char *data; - int rc, len, i, tuple_len; + int rc, len, i, tuple_len, avail_age_level = 0; batt_node = of_find_node_by_name(node, "qcom,battery-data"); if (!batt_node) { @@ -1331,8 +1336,13 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) return -ENXIO; } - profile_node = of_batterydata_get_best_profile(batt_node, - fg->batt_id_ohms / 1000, NULL); + if (chip->dt.multi_profile_load) + profile_node = of_batterydata_get_best_aged_profile(batt_node, + fg->batt_id_ohms / 1000, + chip->batt_age_level, &avail_age_level); + else + profile_node = of_batterydata_get_best_profile(batt_node, + fg->batt_id_ohms / 1000, NULL); if (IS_ERR(profile_node)) return PTR_ERR(profile_node); @@ -1341,6 +1351,13 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) return -ENODATA; } + if (chip->dt.multi_profile_load && + chip->batt_age_level != avail_age_level) { + fg_dbg(fg, FG_STATUS, "Batt_age_level %d doesn't exist, using %d\n", + chip->batt_age_level, avail_age_level); + chip->batt_age_level = avail_age_level; + } + rc = of_property_read_string(profile_node, "qcom,battery-type", &fg->bp.batt_type_str); if (rc < 0) { @@ -1687,6 +1704,10 @@ static bool is_profile_load_required(struct fg_gen4_chip *chip) FIRST_PROFILE_LOAD_BIT, }; + if (chip->dt.multi_profile_load && + (chip->batt_age_level != chip->last_batt_age_level)) + return true; + rc = fg_sram_read(fg, PROFILE_INTEGRITY_WORD, PROFILE_INTEGRITY_OFFSET, &val, 1, FG_IMA_DEFAULT); if (rc < 0) { @@ -1756,6 +1777,103 @@ static bool is_profile_load_required(struct fg_gen4_chip *chip) } #define SOC_READY_WAIT_TIME_MS 1000 +static int qpnp_fg_gen4_load_profile(struct fg_gen4_chip *chip) +{ + struct fg_dev *fg = &chip->fg; + u8 val, mask, buf[2]; + int rc; + bool normal_profile_load = false; + + /* + * This is used to determine if the profile is loaded normally i.e. + * either multi profile loading is disabled OR if it is enabled, then + * only loading the profile with battery age level 0 is considered. + */ + normal_profile_load = !chip->dt.multi_profile_load || + (chip->dt.multi_profile_load && + chip->batt_age_level == 0); + if (normal_profile_load) { + rc = fg_masked_write(fg, BATT_SOC_RESTART(fg), RESTART_GO_BIT, + 0); + if (rc < 0) { + pr_err("Error in writing to %04x, rc=%d\n", + BATT_SOC_RESTART(fg), rc); + return rc; + } + } + + /* load battery profile */ + rc = fg_sram_write(fg, PROFILE_LOAD_WORD, PROFILE_LOAD_OFFSET, + chip->batt_profile, PROFILE_LEN, FG_IMA_ATOMIC); + if (rc < 0) { + pr_err("Error in writing battery profile, rc:%d\n", rc); + return rc; + } + + if (normal_profile_load) { + /* Enable side loading for voltage and current */ + val = mask = BIT(0); + rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, + SYS_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in setting SYS_CONFIG_WORD[0], rc=%d\n", + rc); + return rc; + } + + /* Clear first logged main current ADC values */ + buf[0] = buf[1] = 0; + rc = fg_sram_write(fg, FIRST_LOG_CURRENT_v2_WORD, + FIRST_LOG_CURRENT_v2_OFFSET, buf, 2, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in clearing FIRST_LOG_CURRENT rc=%d\n", + rc); + return rc; + } + } + + /* Set the profile integrity bit */ + val = HLOS_RESTART_BIT | PROFILE_LOAD_BIT; + rc = fg_sram_write(fg, PROFILE_INTEGRITY_WORD, + PROFILE_INTEGRITY_OFFSET, &val, 1, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("failed to write profile integrity rc=%d\n", rc); + return rc; + } + + if (chip->dt.multi_profile_load && chip->batt_age_level >= 0) { + val = (u8)chip->batt_age_level; + rc = fg_sram_write(fg, BATT_AGE_LEVEL_WORD, + BATT_AGE_LEVEL_OFFSET, &val, 1, FG_IMA_ATOMIC); + if (rc < 0) { + pr_err("Error in writing batt_age_level, rc:%d\n", rc); + return rc; + } + } + + if (normal_profile_load) { + rc = fg_restart(fg, SOC_READY_WAIT_TIME_MS); + if (rc < 0) { + pr_err("Error in restarting FG, rc=%d\n", rc); + return rc; + } + + /* Clear side loading for voltage and current */ + val = 0; + mask = BIT(0); + rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, + SYS_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in clearing SYS_CONFIG_WORD[0], rc=%d\n", + rc); + return rc; + } + } + + return 0; +} + static void profile_load_work(struct work_struct *work) { struct fg_dev *fg = container_of(work, @@ -1764,7 +1882,7 @@ static void profile_load_work(struct work_struct *work) struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); int64_t nom_cap_uah; - u8 val, mask, buf[2]; + u8 val, buf[2]; int rc; vote(fg->awake_votable, PROFILE_LOAD, true, 0); @@ -1789,66 +1907,14 @@ static void profile_load_work(struct work_struct *work) if (!is_profile_load_required(chip)) goto done; - clear_cycle_count(chip->counter); + if (!chip->dt.multi_profile_load) + clear_cycle_count(chip->counter); fg_dbg(fg, FG_STATUS, "profile loading started\n"); - rc = fg_masked_write(fg, BATT_SOC_RESTART(fg), RESTART_GO_BIT, 0); - if (rc < 0) { - pr_err("Error in writing to %04x, rc=%d\n", - BATT_SOC_RESTART(fg), rc); - goto out; - } - /* load battery profile */ - rc = fg_sram_write(fg, PROFILE_LOAD_WORD, PROFILE_LOAD_OFFSET, - chip->batt_profile, PROFILE_LEN, FG_IMA_ATOMIC); - if (rc < 0) { - pr_err("Error in writing battery profile, rc:%d\n", rc); - goto out; - } - - /* Enable side loading for voltage and current */ - val = mask = BIT(0); - rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, - SYS_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in setting SYS_CONFIG_WORD[0], rc=%d\n", rc); - goto out; - } - - /* Clear first logged main current ADC values */ - buf[0] = buf[1] = 0; - rc = fg_sram_write(fg, FIRST_LOG_CURRENT_v2_WORD, - FIRST_LOG_CURRENT_v2_OFFSET, buf, 2, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in clearing FIRST_LOG_CURRENT rc=%d\n", rc); - goto out; - } - - /* Set the profile integrity bit */ - val = HLOS_RESTART_BIT | PROFILE_LOAD_BIT; - rc = fg_sram_write(fg, PROFILE_INTEGRITY_WORD, - PROFILE_INTEGRITY_OFFSET, &val, 1, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("failed to write profile integrity rc=%d\n", rc); - goto out; - } - - rc = fg_restart(fg, SOC_READY_WAIT_TIME_MS); - if (rc < 0) { - pr_err("Error in restarting FG, rc=%d\n", rc); - goto out; - } - - /* Clear side loading for voltage and current */ - val = 0; - mask = BIT(0); - rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, - SYS_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in clearing SYS_CONFIG_WORD[0], rc=%d\n", rc); + rc = qpnp_fg_gen4_load_profile(chip); + if (rc < 0) goto out; - } fg_dbg(fg, FG_STATUS, "SOC is ready\n"); fg->profile_load_status = PROFILE_LOADED; @@ -1900,6 +1966,8 @@ static void profile_load_work(struct work_struct *work) schedule_delayed_work(&chip->ttf->ttf_work, msecs_to_jiffies(10000)); fg_dbg(fg, FG_STATUS, "profile loaded successfully"); out: + if (chip->dt.multi_profile_load && rc < 0) + chip->batt_age_level = chip->last_batt_age_level; fg->soc_reporting_ready = true; vote(fg->awake_votable, ESR_FCC_VOTER, true, 0); schedule_delayed_work(&chip->pl_enable_work, msecs_to_jiffies(5000)); @@ -3509,6 +3577,9 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CC_STEP_SEL: pval->intval = chip->ttf->cc_step.sel; break; + case POWER_SUPPLY_PROP_BATT_AGE_LEVEL: + pval->intval = chip->batt_age_level; + break; default: pr_err("unsupported property %d\n", psp); rc = -EINVAL; @@ -3590,6 +3661,14 @@ static int fg_psy_set_property(struct power_supply *psy, chip->first_profile_load = false; } break; + case POWER_SUPPLY_PROP_BATT_AGE_LEVEL: + if (!chip->dt.multi_profile_load || pval->intval < 0 || + chip->batt_age_level == pval->intval) + return -EINVAL; + chip->last_batt_age_level = chip->batt_age_level; + chip->batt_age_level = pval->intval; + schedule_delayed_work(&fg->profile_load_work, 0); + break; default: break; } @@ -3608,6 +3687,7 @@ static int fg_property_is_writeable(struct power_supply *psy, case POWER_SUPPLY_PROP_ESR_NOMINAL: case POWER_SUPPLY_PROP_SOH: case POWER_SUPPLY_PROP_CLEAR_SOH: + case POWER_SUPPLY_PROP_BATT_AGE_LEVEL: return 1; default: break; @@ -3644,6 +3724,7 @@ static enum power_supply_property fg_psy_props[] = { POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, POWER_SUPPLY_PROP_CC_STEP, POWER_SUPPLY_PROP_CC_STEP_SEL, + POWER_SUPPLY_PROP_BATT_AGE_LEVEL, }; static const struct power_supply_desc fg_psy_desc = { @@ -4218,6 +4299,13 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) return rc; } + chip->batt_age_level = chip->last_batt_age_level = -EINVAL; + if (chip->dt.multi_profile_load) { + rc = fg_sram_read(fg, BATT_AGE_LEVEL_WORD, + BATT_AGE_LEVEL_OFFSET, &val, 1, FG_IMA_DEFAULT); + if (!rc) + chip->batt_age_level = chip->last_batt_age_level = val; + } return 0; } @@ -4699,6 +4787,8 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) chip->dt.five_pin_battery = of_property_read_bool(node, "qcom,five-pin-battery"); + chip->dt.multi_profile_load = of_property_read_bool(node, + "qcom,multi-profile-load"); return 0; } -- GitLab From 3f163f7586b7c317d2a552903d8ec3fd1e511a84 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Sun, 2 Dec 2018 00:45:41 +0530 Subject: [PATCH 0907/1286] regulator: qcom_pm8008: Regulator driver for the PM8008 PMIC PM8008 is a I2C based regulator PMIC supporting 7 LDOs(2 N600 and 5 P300). Add the PM8008 regulator driver to support PMIC regulator management via regulator framework. Change-Id: Ie8d96b50558b8dd3084134216dff6393bac16f71 Signed-off-by: Ashay Jaiswal --- .../regulator/qcom,pm8008-regulator.txt | 124 +++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/qcom_pm8008-regulator.c | 781 ++++++++++++++++++ 4 files changed, 915 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt create mode 100644 drivers/regulator/qcom_pm8008-regulator.c diff --git a/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt new file mode 100644 index 000000000000..c945e86b53a6 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulator.txt @@ -0,0 +1,124 @@ +Qualcomm Technologies, Inc. PM8008 Regulator + +PM8008 is an I2C based PMIC regulator chip. + +======================= +Required Node Structure +======================= + +============================================== +PM8008 chip specific device +============================================== +PM8008 chip specific properties: + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,pm8008-chip" + +- pinctrl-names: + Usage: required + Value type: + Definition: must be "default" + +- pinctrl-0: + Usage: required + Value type: + Definition: pinctrol handle for chip enable GPIO. + +- regulator sub-node: + Usage: required + Value type: + Definition: Chip enable regulator device to control chip enable + functionality. Must be "qcom,pm8008-chip-en". +Example: + qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + pinctrl-names = "default"; + pinctrl-0 = <&pincontrol handle>; // chip enable GPIO + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + +======================================================== +PM8008 regulator device +======================================================== +PM8008 chip regulator specific properties: + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,pm8008-regulator" + +- -supply: + Usage: optional + Value type: + Definition: Reference to parent regulator supplying the input pin, as + described in the data sheet. + Must be one of the following: + vdd_l1_l2-supply: supply for LDO1/LDO2 of PM8008 + vdd_l3_l4-supply: supply for LDO3/LDO4 of PM8008 + vdd_l5-supply: supply for LDO5 of PM8008 + vdd_l6-supply: supply for LDO6 of PM8008 + vdd_l7-supply: supply for LDO7 of PM8008 + +- pm8008_en-supply: + Usage: required + Value type: + Definition: Reference to PM8008 chip enable regulator, which manages + chip enable functionlity of PM8008. + +============================================================================ +Second Level Nodes - PM8008 regulator peripherals of PM8008 regulator device +============================================================================ + +- qcom,hpm-min-load: + Usage: optional + Value type: + Definition: Load current in uA which corresponds to the minimum load + which requires the regulator to be in high power mode. + +- qcom,min-dropout-voltage: + Usage: optional + Value type: + Definition: Specifies the minimum voltage in microvolts that the parent + supply regulator must output above the output of this + regulator. It is only meaningful if the corresponding parent + supply property has been specified in the first level node. + +- qcom,init-voltage + Usage: optional + Value type: + Definition: Specifies the initial voltage in microvolts to for a regulator. + +- qcom,strong-pd + Usage: optional + Value type: + Definition: Property if present enables strong pull-down. + +The content of each sub-node is defined by the standard binding for regulators - +see regulator.txt - with additional custom properties described below: + +Example: + + qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + + pm8008_en-supply = <&PM8008_EN>; + vdd_l1_l2-supply = <&parent-supply>; + ... + + L1: qcom,pm8008-l1@4000 { + reg = /bits/ 16 <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3100000>; + qcom,min-dropout-voltage = <100000>; + qcom,hpm-min-load = <10000>; + } + + ..... + }; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 51fe0658037e..dd881a9394c6 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -337,6 +337,15 @@ config REGULATOR_ISL6271A help This driver supports ISL6271A voltage regulator chip. +config REGULATOR_PM8008 + bool "Qualcomm Technologies Inc. PM8008 regulator driver" + depends on MFD_I2C_PMIC + help + Say Y here to support the PM8008 PMIC chip. + This driver controls PM8008 PMIC chip and the voltage + regulators found in Qualcomm Technologies Inc. PM8008 + PMIC. + config REGULATOR_LM363X tristate "TI LM363X voltage regulators" depends on MFD_TI_LMU diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 59af8b989e7b..63fe6cdf32f9 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_REGULATOR_QPNP_AMOLED) += qpnp-amoled-regulator.o obj-$(CONFIG_REGULATOR_QPNP_OLEDB) += qpnp-oledb-regulator.o obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o +obj-$(CONFIG_REGULATOR_PM8008) += qcom_pm8008-regulator.o obj-$(CONFIG_REGULATOR_PV88060) += pv88060-regulator.o obj-$(CONFIG_REGULATOR_PV88080) += pv88080-regulator.o obj-$(CONFIG_REGULATOR_PV88090) += pv88090-regulator.o diff --git a/drivers/regulator/qcom_pm8008-regulator.c b/drivers/regulator/qcom_pm8008-regulator.c new file mode 100644 index 000000000000..97174a4a0723 --- /dev/null +++ b/drivers/regulator/qcom_pm8008-regulator.c @@ -0,0 +1,781 @@ +/* Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "PM8008: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define pm8008_err(reg, message, ...) \ + pr_err("%s: " message, (reg)->rdesc.name, ##__VA_ARGS__) +#define pm8008_debug(reg, message, ...) \ + pr_debug("%s: " message, (reg)->rdesc.name, ##__VA_ARGS__) + +#define STARTUP_DELAY_USEC 20 +#define VSET_STEP_SIZE_MV 1 +#define VSET_STEP_MV 8 + +#define MISC_BASE 0x900 + +#define MISC_CHIP_ENABLE_REG (MISC_BASE + 0x50) +#define CHIP_ENABLE_BIT BIT(0) + +#define LDO_ENABLE_REG(base) (base + 0x46) +#define ENABLE_BIT BIT(7) + +#define LDO_STATUS1_REG(base) (base + 0x08) +#define VREG_READY_BIT BIT(7) +#define MODE_STATE_MASK GENMASK(1, 0) +#define MODE_STATE_NPM 3 +#define MODE_STATE_LPM 2 +#define MODE_STATE_BYPASS 0 + +#define LDO_VSET_LB_REG(base) (base + 0x40) + +#define LDO_VSET_VALID_LB_REG(base) (base + 0x42) + +#define LDO_MODE_CTL1_REG(base) (base + 0x45) +#define MODE_PRIMARY_MASK GENMASK(2, 0) +#define LDO_MODE_NPM 7 +#define LDO_MODE_LPM 4 +#define FORCED_BYPASS 2 + +#define LDO_STEPPER_CTL_REG(base) (base + 0x3b) +#define STEP_RATE_MASK GENMASK(1, 0) + +#define LDO_PD_CTL_REG(base) (base + 0xA0) +#define STRONG_PD_EN_BIT BIT(7) + +#define MAX_REG_NAME 20 +#define PM8008_MAX_LDO 7 + +struct pm8008_chip { + struct device *dev; + struct regmap *regmap; + struct regulator_dev *rdev; + struct regulator_desc rdesc; + +}; + +struct regulator_data { + char *name; + char *supply_name; + int hpm_min_load_ua; + int min_dropout_uv; +}; + +struct pm8008_regulator { + struct device *dev; + struct regmap *regmap; + struct regulator_desc rdesc; + struct regulator_dev *rdev; + struct regulator *parent_supply; + struct regulator *en_supply; + struct device_node *of_node; + u16 base; + int hpm_min_load_ua; + int min_dropout_uv; + int step_rate; +}; + +static struct regulator_data reg_data[] = { + /* name, parent, min load, headroom */ + {"pm8008_l1", "vdd_l1_l2", 10000, 225000}, + {"pm8008_l2", "vdd_l1_l2", 10000, 225000}, + {"pm8008_l3", "vdd_l3_l4", 10000, 200000}, + {"pm8008_l4", "vdd_l3_l4", 10000, 200000}, + {"pm8008_l5", "vdd_l5", 10000, 300000}, + {"pm8008_l6", "vdd_l6", 10000, 300000}, + {"pm8008_l7", "vdd_l7", 10000, 300000}, +}; + +/* common functions */ +static int pm8008_read(struct regmap *regmap, u16 reg, u8 *val, int count) +{ + int rc; + + rc = regmap_bulk_read(regmap, reg, val, count); + if (rc < 0) + pr_err("failed to read 0x%04x\n", reg); + + return rc; +} + +static int pm8008_write(struct regmap *regmap, u16 reg, u8 *val, int count) +{ + int rc; + + pr_debug("Writing 0x%02x to 0x%04x\n", val, reg); + rc = regmap_bulk_write(regmap, reg, val, count); + if (rc < 0) + pr_err("failed to write 0x%04x\n", reg); + + return rc; +} + +static int pm8008_masked_write(struct regmap *regmap, u16 reg, u8 mask, + u8 val) +{ + int rc; + + pr_debug("Writing 0x%02x to 0x%04x with mask 0x%02x\n", val, reg, mask); + rc = regmap_update_bits(regmap, reg, mask, val); + if (rc < 0) + pr_err("failed to write 0x%02x to 0x%04x with mask 0x%02x\n", + val, reg, mask); + + return rc; +} + +/* PM8008 LDO Regulator callbacks */ +static int pm8008_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + u8 vset_raw[2]; + int rc; + + rc = pm8008_read(pm8008_reg->regmap, + LDO_VSET_VALID_LB_REG(pm8008_reg->base), + vset_raw, 2); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to read regulator voltage rc=%d\n", rc); + return rc; + } + + pm8008_debug(pm8008_reg, "VSET read [%x][%x]\n", + vset_raw[1], vset_raw[0]); + return (vset_raw[1] << 8 | vset_raw[0]) * 1000; +} + +static int pm8008_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc; + u8 reg; + + rc = pm8008_read(pm8008_reg->regmap, + LDO_ENABLE_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + pm8008_err(pm8008_reg, "failed to read enable reg rc=%d\n", rc); + return rc; + } + + return !!(reg & ENABLE_BIT); +} + +static int pm8008_regulator_enable(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc, init_mv, delay_us, delay_ms, retry_count = 10; + u8 reg; + + rc = regulator_enable(pm8008_reg->en_supply); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to enable en_supply rc=%d\n", rc); + return rc; + } + + if (pm8008_reg->parent_supply) { + rc = regulator_enable(pm8008_reg->parent_supply); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to enable parent rc=%d\n", rc); + regulator_disable(pm8008_reg->en_supply); + return rc; + } + } + + rc = pm8008_masked_write(pm8008_reg->regmap, + LDO_ENABLE_REG(pm8008_reg->base), + ENABLE_BIT, ENABLE_BIT); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to enable regulator rc=%d\n", rc); + goto remove_vote; + } + + /* + * wait for VREG_OK + * Read voltage and calculate the delay. + */ + init_mv = pm8008_regulator_get_voltage(rdev) / 1000; + if (init_mv < 0) { + pm8008_err(pm8008_reg, + "failed to get regulator voltage rc=%d\n", rc); + goto out; + } + delay_us = STARTUP_DELAY_USEC + + DIV_ROUND_UP(init_mv * 1000, pm8008_reg->step_rate); + delay_ms = DIV_ROUND_UP(delay_us, 1000); + + /* Retry 10 times for VREG_OK before bailing out */ + while (retry_count--) { + if (delay_ms > 20) + msleep(delay_ms); + else + usleep_range(delay_us, delay_us + 100); + + rc = pm8008_read(pm8008_reg->regmap, + LDO_STATUS1_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to read regulator status rc=%d\n", rc); + goto out; + } + if (reg & VREG_READY_BIT) { + pm8008_debug(pm8008_reg, "regulator enabled\n"); + return 0; + } + } + + pm8008_err(pm8008_reg, + "failed to enable regulator VREG_READY not set\n"); +out: + pm8008_masked_write(pm8008_reg->regmap, + LDO_ENABLE_REG(pm8008_reg->base), ENABLE_BIT, 0); +remove_vote: + rc = regulator_disable(pm8008_reg->en_supply); + if (pm8008_reg->parent_supply) + rc |= regulator_disable(pm8008_reg->parent_supply); + if (rc < 0) + pm8008_err(pm8008_reg, + "failed to disable parent regulator rc=%d\n", rc); + + return -ETIME; +} + +static int pm8008_regulator_disable(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc; + + rc = pm8008_masked_write(pm8008_reg->regmap, + LDO_ENABLE_REG(pm8008_reg->base), + ENABLE_BIT, 0); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to disable regulator rc=%d\n", rc); + return rc; + } + + /* remove vote from chip enable regulator */ + rc = regulator_disable(pm8008_reg->en_supply); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to disable en_supply rc=%d\n", rc); + } + + /* remove voltage vote from parent regulator */ + if (pm8008_reg->parent_supply) { + rc = regulator_set_voltage(pm8008_reg->parent_supply, + 0, INT_MAX); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to remove parent voltage rc=%d\n", rc); + return rc; + } + rc = regulator_disable(pm8008_reg->parent_supply); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to disable parent rc=%d\n", rc); + return rc; + } + } + + pm8008_debug(pm8008_reg, "regulator disabled\n"); + return 0; +} + +static int pm8008_write_voltage(struct pm8008_regulator *pm8008_reg, int min_uv, + int max_uv) +{ + int rc = 0, mv; + u8 vset_raw[2]; + + mv = DIV_ROUND_UP(min_uv, 1000); + if (mv * 1000 > max_uv) { + pm8008_err(pm8008_reg, + "requested voltage above maximum limit\n"); + return -EINVAL; + } + + /* + * Each LSB of regulator is 1mV and the voltage setpoint + * should be multiple of 8mV(step). + */ + mv = DIV_ROUND_UP(DIV_ROUND_UP(mv, VSET_STEP_MV) * VSET_STEP_MV, + VSET_STEP_SIZE_MV); + + vset_raw[0] = mv & 0xff; + vset_raw[1] = (mv & 0xff00) >> 8; + rc = pm8008_write(pm8008_reg->regmap, LDO_VSET_LB_REG(pm8008_reg->base), + vset_raw, 2); + if (rc < 0) { + pm8008_err(pm8008_reg, "failed to write voltage rc=%d\n", rc); + return rc; + } + + pm8008_debug(pm8008_reg, "VSET=[%x][%x]\n", vset_raw[1], vset_raw[0]); + return 0; +} + +static int pm8008_regulator_set_voltage(struct regulator_dev *rdev, + int min_uv, int max_uv, unsigned int *selector) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc = 0; + + if (pm8008_reg->parent_supply) { + /* request on parent regulator with headroom */ + rc = regulator_set_voltage(pm8008_reg->parent_supply, + pm8008_reg->min_dropout_uv + min_uv, + INT_MAX); + if (rc < 0) { + pm8008_err(pm8008_reg, + "failed to request parent supply voltage rc=%d\n", + rc); + return rc; + } + } + + rc = pm8008_write_voltage(pm8008_reg, min_uv, max_uv); + if (rc < 0) { + /* remove parent's voltage vote */ + if (pm8008_reg->parent_supply) + regulator_set_voltage(pm8008_reg->parent_supply, + 0, INT_MAX); + } + + pm8008_debug(pm8008_reg, "voltage set to %d\n", min_uv); + return rc; +} + +static int pm8008_regulator_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc; + u8 val = LDO_MODE_LPM; + + if (mode == REGULATOR_MODE_NORMAL) + val = LDO_MODE_NPM; + else if (mode == REGULATOR_MODE_IDLE) + val = LDO_MODE_LPM; + + rc = pm8008_masked_write(pm8008_reg->regmap, + LDO_MODE_CTL1_REG(pm8008_reg->base), + MODE_PRIMARY_MASK, val); + if (!rc) + pm8008_debug(pm8008_reg, "mode set to %d\n", val); + + return rc; +} + +static unsigned int pm8008_regulator_get_mode(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int rc; + u8 reg; + + rc = pm8008_read(pm8008_reg->regmap, + LDO_STATUS1_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + pm8008_err(pm8008_reg, "failed to get mode rc=%d\n", rc); + return rc; + } + + return ((reg & MODE_STATE_MASK) == MODE_STATE_NPM) + ? REGULATOR_MODE_NORMAL : REGULATOR_MODE_IDLE; +} + +static int pm8008_regulator_set_load(struct regulator_dev *rdev, int load_uA) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + int mode; + + if (load_uA >= pm8008_reg->hpm_min_load_ua) + mode = REGULATOR_MODE_NORMAL; + else + mode = REGULATOR_MODE_IDLE; + + return pm8008_regulator_set_mode(rdev, mode); +} + +static int pm8008_regulator_set_voltage_time(struct regulator_dev *rdev, + int old_uV, int new_uv) +{ + struct pm8008_regulator *pm8008_reg = rdev_get_drvdata(rdev); + + return DIV_ROUND_UP(abs(new_uv - old_uV), pm8008_reg->step_rate); +} + +static struct regulator_ops pm8008_regulator_ops = { + .enable = pm8008_regulator_enable, + .disable = pm8008_regulator_disable, + .is_enabled = pm8008_regulator_is_enabled, + .set_voltage = pm8008_regulator_set_voltage, + .get_voltage = pm8008_regulator_get_voltage, + .set_mode = pm8008_regulator_set_mode, + .get_mode = pm8008_regulator_get_mode, + .set_load = pm8008_regulator_set_load, + .set_voltage_time = pm8008_regulator_set_voltage_time, +}; + +static int pm8008_register_ldo(struct pm8008_regulator *pm8008_reg, + const char *name) +{ + struct regulator_config reg_config = {}; + struct regulator_init_data *init_data; + struct device *dev = pm8008_reg->dev; + struct device_node *reg_node = pm8008_reg->of_node; + char buff[MAX_REG_NAME]; + int rc, i, init_voltage; + u8 reg; + + /* get regulator data */ + for (i = 0; i < PM8008_MAX_LDO; i++) + if (!strcmp(reg_data[i].name, name)) + break; + + if (i == PM8008_MAX_LDO) { + pr_err("Invalid regulator name %s\n", name); + return -EINVAL; + } + + rc = of_property_read_u16(reg_node, "reg", &pm8008_reg->base); + if (rc < 0) { + pr_err("%s: failed to get regulator base rc=%d\n", name, rc); + return rc; + } + + pm8008_reg->min_dropout_uv = reg_data[i].min_dropout_uv; + of_property_read_u32(reg_node, "qcom,min-dropout-voltage", + &pm8008_reg->min_dropout_uv); + + pm8008_reg->hpm_min_load_ua = reg_data[i].hpm_min_load_ua; + of_property_read_u32(reg_node, "qcom,hpm-min-load", + &pm8008_reg->hpm_min_load_ua); + init_voltage = -EINVAL; + of_property_read_u32(reg_node, "qcom,init-voltage", &init_voltage); + + if (of_property_read_bool(reg_node, "qcom,strong-pd")) { + rc = pm8008_masked_write(pm8008_reg->regmap, + LDO_PD_CTL_REG(pm8008_reg->base), + STRONG_PD_EN_BIT, STRONG_PD_EN_BIT); + if (rc < 0) { + pr_err("%s: failed to configure pull down rc=%d\n", + name, rc); + return rc; + } + } + + + /* get slew rate */ + rc = pm8008_read(pm8008_reg->regmap, + LDO_STEPPER_CTL_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + pr_err("%s: failed to read step rate configuration rc=%d\n", + name, rc); + return rc; + } + pm8008_reg->step_rate = 38400 >> (reg & STEP_RATE_MASK); + + scnprintf(buff, MAX_REG_NAME, "%s-supply", reg_data[i].supply_name); + if (of_find_property(dev->of_node, buff, NULL)) { + pm8008_reg->parent_supply = devm_regulator_get(dev, + reg_data[i].supply_name); + if (IS_ERR(pm8008_reg->parent_supply)) { + rc = PTR_ERR(pm8008_reg->parent_supply); + if (rc != -EPROBE_DEFER) + pr_err("%s: failed to get parent regulator rc=%d\n", + name, rc); + return rc; + } + } + + /* pm8008_en should be present otherwise fail the regulator probe */ + pm8008_reg->en_supply = devm_regulator_get(dev, "pm8008_en"); + if (IS_ERR(pm8008_reg->en_supply)) { + rc = PTR_ERR(pm8008_reg->en_supply); + pr_err("%s: failed to get chip_en supply\n", name); + return rc; + } + + init_data = of_get_regulator_init_data(dev, reg_node, + &pm8008_reg->rdesc); + if (init_data == NULL) { + pr_err("%s: failed to get regulator data\n", name); + return -ENODATA; + } + if (!init_data->constraints.name) { + pr_err("%s: regulator name missing\n", name); + return -EINVAL; + } + + /* configure the initial voltage for the regulator */ + if (init_voltage > 0) { + rc = pm8008_write_voltage(pm8008_reg, init_voltage, + init_data->constraints.max_uV); + if (rc < 0) + pr_err("%s: failed to set initial voltage rc=%d\n", + name, rc); + } + + init_data->constraints.input_uV = init_data->constraints.max_uV; + init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS + | REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_DRMS; + reg_config.dev = dev; + reg_config.init_data = init_data; + reg_config.driver_data = pm8008_reg; + reg_config.of_node = reg_node; + + pm8008_reg->rdesc.owner = THIS_MODULE; + pm8008_reg->rdesc.type = REGULATOR_VOLTAGE; + pm8008_reg->rdesc.ops = &pm8008_regulator_ops; + pm8008_reg->rdesc.name = init_data->constraints.name; + + pm8008_reg->rdev = devm_regulator_register(dev, &pm8008_reg->rdesc, + ®_config); + if (IS_ERR(pm8008_reg->rdev)) { + rc = PTR_ERR(pm8008_reg->rdev); + pr_err("%s: failed to register regulator rc=%d\n", + pm8008_reg->rdesc.name, rc); + return rc; + } + + pr_debug("%s regulator registered\n", name); + + return 0; +} + +/* PMIC probe and helper function */ +static int pm8008_parse_regulator(struct regmap *regmap, struct device *dev) +{ + int rc = 0; + const char *name; + struct device_node *child; + struct pm8008_regulator *pm8008_reg; + + /* parse each subnode and register regulator for regulator child */ + for_each_available_child_of_node(dev->of_node, child) { + pm8008_reg = devm_kzalloc(dev, sizeof(*pm8008_reg), GFP_KERNEL); + if (!pm8008_reg) + return -ENOMEM; + + pm8008_reg->regmap = regmap; + pm8008_reg->of_node = child; + pm8008_reg->dev = dev; + + rc = of_property_read_string(child, "regulator-name", &name); + if (rc) + continue; + + rc = pm8008_register_ldo(pm8008_reg, name); + if (rc < 0) { + pr_err("failed to register regulator %s rc=%d\n", + name, rc); + return rc; + } + } + + return 0; +} + +static int pm8008_regulator_probe(struct platform_device *pdev) +{ + int rc = 0; + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) { + pr_err("parent regmap is missing\n"); + return -EINVAL; + } + + rc = pm8008_parse_regulator(regmap, &pdev->dev); + if (rc < 0) { + pr_err("failed to parse device tree rc=%d\n", rc); + return rc; + } + + return 0; +} + +/* PM8008 chip enable regulator callbacks */ +static int pm8008_enable_regulator_enable(struct regulator_dev *rdev) +{ + struct pm8008_regulator *chip = rdev_get_drvdata(rdev); + int rc; + + rc = pm8008_masked_write(chip->regmap, MISC_CHIP_ENABLE_REG, + CHIP_ENABLE_BIT, CHIP_ENABLE_BIT); + if (rc < 0) { + pm8008_err(chip, "failed to enable chip rc=%d\n", rc); + return rc; + } + + pm8008_debug(chip, "regulator enabled\n"); + return 0; +} + +static int pm8008_enable_regulator_disable(struct regulator_dev *rdev) +{ + struct pm8008_regulator *chip = rdev_get_drvdata(rdev); + int rc; + + rc = pm8008_masked_write(chip->regmap, MISC_CHIP_ENABLE_REG, + CHIP_ENABLE_BIT, 0); + if (rc < 0) { + pm8008_err(chip, "failed to disable chip rc=%d\n", rc); + return rc; + } + + pm8008_debug(chip, "regulator disabled\n"); + return 0; +} + +static int pm8008_enable_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct pm8008_regulator *chip = rdev_get_drvdata(rdev); + int rc; + u8 reg; + + rc = pm8008_read(chip->regmap, MISC_CHIP_ENABLE_REG, ®, 1); + if (rc < 0) { + pm8008_err(chip, "failed to get chip state rc=%d\n", rc); + return rc; + } + + return !!(reg & CHIP_ENABLE_BIT); +} + +static struct regulator_ops pm8008_enable_reg_ops = { + .enable = pm8008_enable_regulator_enable, + .disable = pm8008_enable_regulator_disable, + .is_enabled = pm8008_enable_regulator_is_enabled, +}; + +static int pm8008_init_enable_regulator(struct pm8008_chip *chip) +{ + struct regulator_config cfg = {}; + int rc = 0; + + cfg.dev = chip->dev; + cfg.driver_data = chip; + + chip->rdesc.owner = THIS_MODULE; + chip->rdesc.type = REGULATOR_VOLTAGE; + chip->rdesc.ops = &pm8008_enable_reg_ops; + chip->rdesc.of_match = "qcom,pm8008-chip-en"; + chip->rdesc.name = "qcom,pm8008-chip-en"; + + chip->rdev = devm_regulator_register(chip->dev, &chip->rdesc, &cfg); + if (IS_ERR(chip->rdev)) { + rc = PTR_ERR(chip->rdev); + chip->rdev = NULL; + return rc; + } + + return 0; +} + +static int pm8008_chip_probe(struct platform_device *pdev) +{ + int rc = 0; + struct pm8008_chip *chip; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + pr_err("parent regmap is missing\n"); + return -EINVAL; + } + chip->dev = &pdev->dev; + + /* Register chip enable regulator */ + rc = pm8008_init_enable_regulator(chip); + if (rc < 0) { + pr_err("Failed to register chip enable regulator rc=%d\n", rc); + return rc; + } + + pr_debug("PM8008 chip registered\n"); + return 0; +} + +static int pm8008_chip_remove(struct platform_device *pdev) +{ + struct pm8008_chip *chip = platform_get_drvdata(pdev); + int rc; + + rc = pm8008_masked_write(chip->regmap, MISC_CHIP_ENABLE_REG, + CHIP_ENABLE_BIT, 0); + if (rc < 0) + pr_err("failed to disable chip rc=%d\n", rc); + + return 0; +} + +static const struct of_device_id pm8008_regulator_match_table[] = { + { + .compatible = "qcom,pm8008-regulator", + }, + { }, +}; + +static struct platform_driver pm8008_regulator_driver = { + .driver = { + .name = "qcom,pm8008-regulator", + .owner = THIS_MODULE, + .of_match_table = pm8008_regulator_match_table, + }, + .probe = pm8008_regulator_probe, +}; +module_platform_driver(pm8008_regulator_driver); + +static const struct of_device_id pm8008_chip_match_table[] = { + { + .compatible = "qcom,pm8008-chip", + }, + { }, +}; + +static struct platform_driver pm8008_chip_driver = { + .driver = { + .name = "qcom,pm8008-chip", + .owner = THIS_MODULE, + .of_match_table = pm8008_chip_match_table, + }, + .probe = pm8008_chip_probe, + .remove = pm8008_chip_remove, +}; +module_platform_driver(pm8008_chip_driver); + +MODULE_DESCRIPTION("QPNP PM8008 PMIC Regulator Driver"); +MODULE_LICENSE("GPL v2"); -- GitLab From 4490d6a3405003f06309315b40e49a3ca51cae32 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Wed, 9 Jan 2019 18:16:02 +0530 Subject: [PATCH 0908/1286] defconfig: Enable PM8008 support for trinket PM8008 is a regulator PMIC, enable PM8008 regulator driver for trinket. Change-Id: I9800b6877f1394e1f845a32967f5b0f7fd611500 Signed-off-by: Ashay Jaiswal --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index b80a7c986e05..ebc140b2bc05 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -355,6 +355,7 @@ CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_RPM_SMD=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 1d13cd92e4ed..6871175b8445 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -370,6 +370,7 @@ CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_RPM_SMD=y -- GitLab From eec3ebab3e843653881d53d4193a89879947ecd7 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Tue, 8 Jan 2019 00:24:09 +0530 Subject: [PATCH 0909/1286] ARM: dts: msm: add support for PM8008 PM8008 is a I2C based regulator PMIC supporting 7 LDOs, add corresponding PM8008 peripheral devices and regulator nodes. Change-Id: Ib32e8e9028ac5d08570670940bf3b9f300c1c67a Signed-off-by: Ashay Jaiswal --- arch/arm64/boot/dts/qcom/pm8008.dtsi | 108 ++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 65 ++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8008.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8008.dtsi b/arch/arm64/boot/dts/qcom/pm8008.dtsi new file mode 100644 index 000000000000..0167a29e88c5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8008.dtsi @@ -0,0 +1,108 @@ +/* Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; +}; + +qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + pm8008_en-supply = <&PM8008_EN>; + L1P: qcom,pm8008-l1@4000 { + reg = /bits/ 16 <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = /bits/ 16 <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,init-voltage = <1500000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = /bits/ 16 <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = /bits/ 16 <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = /bits/ 16 <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4400 { + reg = /bits/ 16 <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4400 { + reg = /bits/ 16 <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f666d1ce7553..45a160f23445 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2177,3 +2177,68 @@ }; #include "trinket-thermal.dtsi" + +&qupv3_se1_i2c { + status="ok"; + #include "pm8008.dtsi" +}; + +&tlmm { + pm8008_active: pm8008_active { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; +}; + +&pm8008_chip { + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; +}; + +&pm8008_regulators { + vdd_l1_l2-supply = <&S6A>; +}; + +&L1P { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +}; + +&L2P { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; +}; + +&L3P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L4P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L5P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L6P { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&L7P { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; -- GitLab From 15237d19434617687f6fa2ee1c37bb4caad5fe0f Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Thu, 27 Dec 2018 17:23:43 +0800 Subject: [PATCH 0910/1286] ARM: dts: msm: add Synaptics new Touch driver Add new Synaptics touch driver on SM6150 interposer platform for QRD Trinket device. Change-Id: I6a3464923c24ffe47e68349ce776dd6a3f527083 Signed-off-by: Fei Mao --- .../qcom/sm6150-interposer-trinket-qrd.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi index 9072991fb121..518b58557622 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -140,3 +140,30 @@ qcom,thermal-mitigation = <3000000 2500000 2000000 1500000 1000000 500000>; }; + +&qupv3_se1_i2c { + status = "ok"; + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <89 0x2008>; + synaptics,bus-reg-name = "vdd"; + synaptics,pwr-reg-name = "avdd"; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 89 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 88 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; +}; + -- GitLab From bacdc04d3340cdab3af8c01e6bd2e93f7fe40d60 Mon Sep 17 00:00:00 2001 From: Lior David Date: Tue, 15 Jan 2019 15:03:42 +0200 Subject: [PATCH 0911/1286] wil6210: fix return code of wmi_mgmt_tx and wmi_mgmt_tx_ext The functions that send management TX frame have 3 possible results: success and other side acknowledged receive (ACK=1), success and other side did not acknowledge receive(ACK=0) and failure to send the frame. The current implementation incorrectly reports the ACK=0 case as failure. Change-Id: Iacb3f54252f4d0b663c06b9909cfe43077b783b4 Signed-off-by: Lior David Signed-off-by: Alexei Avshalom Lazar --- drivers/net/wireless/ath/wil6210/cfg80211.c | 7 ++++++- drivers/net/wireless/ath/wil6210/wmi.c | 13 +++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/cfg80211.c b/drivers/net/wireless/ath/wil6210/cfg80211.c index a8a391c754c7..96d700e57d0a 100644 --- a/drivers/net/wireless/ath/wil6210/cfg80211.c +++ b/drivers/net/wireless/ath/wil6210/cfg80211.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -1567,7 +1567,12 @@ int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, params->wait); out: + /* when the sent packet was not acked by receiver(ACK=0), rc will + * be -EAGAIN. In this case this function needs to return success, + * the ACK=0 will be reflected in tx_status. + */ tx_status = (rc == 0); + rc = (rc == -EAGAIN) ? 0 : rc; cfg80211_mgmt_tx_status(wdev, cookie ? *cookie : 0, buf, len, tx_status, GFP_KERNEL); diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c index fc96e313b5da..13ed315f1c5b 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -3685,8 +3685,9 @@ int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len) rc = wmi_call(wil, WMI_SW_TX_REQ_CMDID, vif->mid, cmd, total, WMI_SW_TX_COMPLETE_EVENTID, &evt, sizeof(evt), 2000); if (!rc && evt.evt.status != WMI_FW_STATUS_SUCCESS) { - wil_err(wil, "mgmt_tx failed with status %d\n", evt.evt.status); - rc = -EINVAL; + wil_dbg_wmi(wil, "mgmt_tx failed with status %d\n", + evt.evt.status); + rc = -EAGAIN; } kfree(cmd); @@ -3738,9 +3739,9 @@ int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, rc = wmi_call(wil, WMI_SW_TX_REQ_EXT_CMDID, vif->mid, cmd, total, WMI_SW_TX_COMPLETE_EVENTID, &evt, sizeof(evt), 2000); if (!rc && evt.evt.status != WMI_FW_STATUS_SUCCESS) { - wil_err(wil, "mgmt_tx_ext failed with status %d\n", - evt.evt.status); - rc = -EINVAL; + wil_dbg_wmi(wil, "mgmt_tx_ext failed with status %d\n", + evt.evt.status); + rc = -EAGAIN; } kfree(cmd); -- GitLab From db77b14ed9af566e0abcb9db2d4c61a904621220 Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Tue, 15 Jan 2019 18:41:09 +0530 Subject: [PATCH 0912/1286] serial: msm_geni_serial: Correct memory access operation Serial driver is writing into register without considering the base address of UART and mistakenly passes the structure directly. This wrongly writes into register, hence correct it by passing actual base address. Change-Id: Ide30305915c7300f9cf4611e8ac4b4ec10c8d46b Signed-off-by: Mukesh Kumar Savaliya --- drivers/tty/serial/msm_geni_serial.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index bf25260f2e72..05beb1f7d4c1 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -983,7 +983,8 @@ static void stop_tx_sequencer(struct uart_port *uport) geni_write_reg_nolog(M_CMD_ABORT_EN, uport->membase, SE_GENI_M_IRQ_CLEAR); } - geni_write_reg_nolog(M_CMD_CANCEL_EN, uport, SE_GENI_M_IRQ_CLEAR); + geni_write_reg_nolog(M_CMD_CANCEL_EN, uport->membase, + SE_GENI_M_IRQ_CLEAR); /* * If we end up having to cancel an on-going Tx for non-console usecase * then it means there was some unsent data in the Tx FIFO, consequently -- GitLab From 51b5bdb3b77df1e11bfe2e47a323b8b79c9f4dee Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 3 Jan 2019 16:15:13 +0530 Subject: [PATCH 0913/1286] msm: ipa3: fix to off-by-one read issue There is off-by-one read issue in function ipa3_is_vlan_mode. Add fix to overcome this issue. Change-Id: If087a762166f09d8786352de680db6d46b70b794 Signed-off-by: Praveen Kurapati --- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 2296eb4a6f6a..dc8f42bb13b2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -6138,7 +6138,7 @@ int ipa3_is_vlan_mode(enum ipa_vlan_ifaces iface, bool *res) return -EINVAL; } - if (iface < 0 || iface > IPA_VLAN_IF_MAX) { + if (iface < 0 || iface >= IPA_VLAN_IF_MAX) { IPAERR("invalid iface %d\n", iface); return -EINVAL; } -- GitLab From 5516e794e187684317a1f4ca68b170005dd14c57 Mon Sep 17 00:00:00 2001 From: jiad Date: Sat, 12 Jan 2019 07:02:12 +0800 Subject: [PATCH 0914/1286] defconfig: sdxprairie: Enable CNSS WLAN platform driver Enable CNSS WLAN platform driver and add QCA6390 device support. Change-Id: I07fb0f2676cac267fbc966cb665564511d50d86d Signed-off-by: Jia Ding --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 3 +++ arch/arm/configs/vendor/sdxprairie_defconfig | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index baf64b1de4ef..c0a246e4bdc1 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -202,6 +202,9 @@ CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index be0518d93bf0..de8efc502d53 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -190,6 +190,10 @@ CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -- GitLab From 1ef51fa6bd212e9976785750b6bd27e7650b382c Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 9 Jan 2019 12:13:22 -0800 Subject: [PATCH 0915/1286] usb: pd: Fix unintentional discarding of outgoing VDM Currently when a VDM message arrives, any pending VDM TX message queued will be aborted. But this will inadvertently discard an initiated Discover Identity if an incoming message such as Attention arrives just before it. Since there is no TX response to Attention, the engine should have just been able to resume the Discover ID message. In general, only discard VDM TX messages when attempting to queue a new outgoing VDM. Change-Id: Ife42a19b8f909b0550b6bd44ed470e87a922d6e3 Signed-off-by: Jack Pham --- drivers/usb/pd/policy_engine.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c index 6bf1e8295024..77e7f5cd0b2c 100644 --- a/drivers/usb/pd/policy_engine.c +++ b/drivers/usb/pd/policy_engine.c @@ -1769,8 +1769,13 @@ int usbpd_send_vdm(struct usbpd *pd, u32 vdm_hdr, const u32 *vdos, int num_vdos) { struct vdm_tx *vdm_tx; - if (pd->vdm_tx) - return -EBUSY; + if (pd->vdm_tx) { + usbpd_warn(&pd->dev, "Discarding previously queued VDM tx (SVID:0x%04x)\n", + VDM_HDR_SVID(pd->vdm_tx->data[0])); + + kfree(pd->vdm_tx); + pd->vdm_tx = NULL; + } vdm_tx = kzalloc(sizeof(*vdm_tx), GFP_KERNEL); if (!vdm_tx) @@ -1854,17 +1859,13 @@ static void handle_vdm_rx(struct usbpd *pd, struct rx_msg *rx_msg) return; } - /* if this interrupts a previous exchange, abort queued response */ - if (cmd_type == SVDM_CMD_TYPE_INITIATOR && pd->vdm_tx) { - usbpd_dbg(&pd->dev, "Discarding previously queued SVDM tx (SVID:0x%04x)\n", - VDM_HDR_SVID(pd->vdm_tx->data[0])); - - kfree(pd->vdm_tx); - pd->vdm_tx = NULL; - } - if (handler && handler->svdm_received) { handler->svdm_received(handler, cmd, cmd_type, vdos, num_vdos); + + /* handle any previously queued TX */ + if (pd->vdm_tx && !pd->sm_queued) + kick_sm(pd, 0); + return; } -- GitLab From 454348e8809c1b6dd7f32218fe52596ff9eb60a3 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Thu, 3 Jan 2019 17:52:42 -0800 Subject: [PATCH 0916/1286] drivers: soc: qcom: Add LLCC driver support for SDXPRAIRIE target Add driver to support system cache driver on SDXPRAIRIE target. Change-Id: I3f028f5959dcd6a4cc574286b1c2fa498ebfdc65 Signed-off-by: Jeevan Shriram --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 3 +- drivers/soc/qcom/Kconfig | 10 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/llcc-sdxprairie.c | 101 ++++++++++++++++++ 4 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/llcc-sdxprairie.c diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 3ea859613223..f6a1dee6aa5d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -98,7 +98,8 @@ compatible devices: qcom,sm8150-llcc, qcom,sdmshrike-llcc, qcom,sm6150-llcc, - qcom,sdmmagpie-llcc + qcom,sdmmagpie-llcc, + qcom,sdxprairie-llcc Example: diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 01dad167e772..5baf1a167785 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -102,6 +102,16 @@ config QCOM_SDMMAGPIE_LLCC data required to configure LLCC so that clients can start using the LLCC slices. +config QCOM_SDXPRAIRIE_LLCC + tristate "Qualcomm Technologies, Inc. SDXPRAIRIE LLCC driver" + depends on QCOM_LLCC + help + This configuration option enables LLCC driver specific to SDXPRAIRIE. + Say 'Y' here to enable the LLCC driver for SDXPRAIRIE which provides + data required to configure LLCC so that clients can start using the + LLCC slices. + + config QCOM_LLCC_AMON tristate "Qualcomm Technologies, Inc. LLCC Activity Monitor(AMON) driver" depends on QCOM_LLCC diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 794f5cec5da1..5b618bd25480 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_LLCC) += llcc-core.o llcc-slice.o obj-$(CONFIG_QCOM_SM8150_LLCC) += llcc-sm8150.o obj-$(CONFIG_QCOM_SDMSHRIKE_LLCC) += llcc-sdmshrike.o +obj-$(CONFIG_QCOM_SDXPRAIRIE_LLCC) += llcc-sdxprairie.o obj-$(CONFIG_QCOM_SM6150_LLCC) += llcc-sm6150.o obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o obj-$(CONFIG_QCOM_SDMMAGPIE_LLCC) += llcc-sdmmagpie.o diff --git a/drivers/soc/qcom/llcc-sdxprairie.c b/drivers/soc/qcom/llcc-sdxprairie.c new file mode 100644 index 000000000000..ddc4c4c5e7d3 --- /dev/null +++ b/drivers/soc/qcom/llcc-sdxprairie.c @@ -0,0 +1,101 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +/* + * SCT entry contains of the following parameters + * name: Name of the client's use case for which the llcc slice is used + * uid: Unique id for the client's use case + * slice_id: llcc slice id for each client + * max_cap: The maximum capacity of the cache slice provided in KB + * priority: Priority of the client used to select victim line for replacement + * fixed_size: Determine of the slice has a fixed capacity + * bonus_ways: Bonus ways to be used by any slice, bonus way is used only if + * it't not a reserved way. + * res_ways: Reserved ways for the cache slice, the reserved ways cannot be used + * by any other client than the one its assigned to. + * cache_mode: Each slice operates as a cache, this controls the mode of the + * slice normal or TCM + * probe_target_ways: Determines what ways to probe for access hit. When + * configured to 1 only bonus and reseved ways are probed. + * when configured to 0 all ways in llcc are probed. + * dis_cap_alloc: Disable capacity based allocation for a client + * retain_on_pc: If this bit is set and client has maitained active vote + * then the ways assigned to this client are not flushed on power + * collapse. + * activate_on_init: Activate the slice immidiately after the SCT is programmed + */ +#define SCT_ENTRY(n, uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, rp, a) \ + { \ + .name = n, \ + .usecase_id = uid, \ + .slice_id = sid, \ + .max_cap = mc, \ + .priority = p, \ + .fixed_size = fs, \ + .bonus_ways = bway, \ + .res_ways = rway, \ + .cache_mode = cmod, \ + .probe_target_ways = ptw, \ + .dis_cap_alloc = dca, \ + .retain_on_pc = rp, \ + .activate_on_init = a, \ + } + +static struct llcc_slice_config sdxprairie_data[] = { + SCT_ENTRY("modem", 8, 8, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 1, 0), + SCT_ENTRY("modemhw", 9, 9, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 1, 0), + SCT_ENTRY("modem_vpe", 29, 29, 64, 1, 1, 0x3, 0x0, 0, 0, 0, 1, 0), + SCT_ENTRY("ap_tcm", 30, 30, 128, 3, 1, 0x0, 0x3, 1, 0, 0, 1, 0), + SCT_ENTRY("write_cache", 31, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 1, 0), +}; + +static int sdxprairie_qcom_llcc_probe(struct platform_device *pdev) +{ + return qcom_llcc_probe(pdev, sdxprairie_data, + ARRAY_SIZE(sdxprairie_data)); +} + +static const struct of_device_id sdxprairie_qcom_llcc_of_match[] = { + { .compatible = "qcom,sdxprairie-llcc", }, + { }, +}; + +static struct platform_driver sdxprairie_qcom_llcc_driver = { + .driver = { + .name = "sdxprairie-llcc", + .owner = THIS_MODULE, + .of_match_table = sdxprairie_qcom_llcc_of_match, + }, + .probe = sdxprairie_qcom_llcc_probe, + .remove = qcom_llcc_remove, +}; + +static int __init sdxprairie_init_qcom_llcc_init(void) +{ + return platform_driver_register(&sdxprairie_qcom_llcc_driver); +} +module_init(sdxprairie_init_qcom_llcc_init); + +static void __exit sdxprairie_exit_qcom_llcc_exit(void) +{ + platform_driver_unregister(&sdxprairie_qcom_llcc_driver); +} +module_exit(sdxprairie_exit_qcom_llcc_exit); + +MODULE_DESCRIPTION("QTI sdxprairie LLCC driver"); +MODULE_LICENSE("GPL v2"); -- GitLab From b46da9e75ef79ddf0f2c1504e6cff838307db9d5 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Mon, 14 Jan 2019 19:03:02 -0800 Subject: [PATCH 0917/1286] ARM: dts: msm: Add LLCC device tree node for sdxprairie target Add LLCC device tree node to enable LLCC driver for activation and de-activation of llcc slices on sdxprairie target. Change-Id: I9395514ec46afb225018cc4c43e453a0d276f8ba Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 02b950f748f9..28923cd2e252 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -433,6 +433,21 @@ status = "ok"; }; + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x50000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0>; + qcom,llcc-broadcast-off = <0x0>; + + llcc: qcom,sdxprairie-llcc { + compatible = "qcom,sdxprairie-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + }; + qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; -- GitLab From 88e5383c43d3185ccc638defc631d704e3ad93b8 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Thu, 3 Jan 2019 18:06:02 -0800 Subject: [PATCH 0918/1286] defconfig: enable LLCC driver on sdxprairie target Enable LLCC config options for sdxprairie target for clients to request system cache slices. Change-Id: I9cb8997811e90ae52ff4b9a50f2847b950064766 Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index baf64b1de4ef..bfcb1bda5518 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -324,6 +324,8 @@ CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index be0518d93bf0..8a871008a2f0 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -314,6 +314,8 @@ CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y -- GitLab From ad54648c6b5b090d3334c9844fae7f868bf1c7c4 Mon Sep 17 00:00:00 2001 From: David Dai Date: Fri, 11 Jan 2019 16:19:25 -0800 Subject: [PATCH 0919/1286] ARM: dts: msm: add IPA keepalive dev_bw device for sdxprairie Add a keepalive governor for IPA core clock since the gcc_aggre_noc_tbu2_clk moved under IPA clock domain. This is a workaround for a TCU hang that occurs when it tries to invalidate the IPA TBU during non-IPA usecases while the IPA clock is off. Change-Id: If42c18673ca93d1b6114ee924cf9aac391db35e7 Signed-off-by: David Dai --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 2fa03630eddd..d164ce407558 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -274,6 +274,15 @@ operating-points-v2 = <&keepalive_opp_table>; }; + ipa_keepalive: qcom,ipa_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <143 777>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + clock_rpmh: qcom,rpmh { compatible = "qcom,rpmh-clk-sdxprairie"; mboxes = <&apps_rsc 0>; -- GitLab From 43094d66962b0237dcecab79fca6cb824a32d9ab Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Mon, 14 Jan 2019 11:11:20 +0530 Subject: [PATCH 0920/1286] msm: jpeg: Support jpeg qos settings. Update the qos default settings for jpeg. Change-Id: I78460b625f77013b52cc1efd4cc39fcbe44f097f Signed-off-by: Abhishek Jain --- .../msm/camera_v2/jpeg_10/msm_jpeg_platform.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c index 5993ab91d8be..0352cfa0ad1e 100644 --- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c +++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016, 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -320,6 +320,15 @@ int msm_jpeg_platform_init(irqreturn_t (*handler)(int, void *), pgmn_dev->hw_version); pgmn_dev->state = MSM_JPEG_INIT; + rc = msm_jpeg_set_init_dt_parms(pgmn_dev, "qcom,vbif-qos-setting", + pgmn_dev->vbif_base); + if (rc == -ENOENT) + JPEG_DBG("%s: No qcom,vbif-qos-setting property\n", __func__); + else if (rc < 0) { + JPEG_PR_ERR("%s: vbif qos params set fail\n", __func__); + goto err_reg_enable; + } + return 0; err_reg_irq_fail: err_fail_set_vbif: -- GitLab From 2614a2567bf5abd691f77a1b5e97177990da8ed6 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 10 Jan 2019 11:51:48 +0530 Subject: [PATCH 0921/1286] ARM: dts: msm: Specify AMOLED regulator device for PM6150 Add AMOLED regulator device that controls OLEB/AB/IBB modules which powers the triple supply needed for AMOLED panels. Enable the device for SDMMAGPIE. Change-Id: I2f192dd3eddd9bf9e941d4184f33ca0c61f6657a Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 34 ++++++++++++++++++++- arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi | 4 +++ arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi | 6 +++- 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 665a8f860d59..da4099c50669 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -390,6 +390,38 @@ linux,default-trigger = "timer"; }; }; + + pm6150a_amoled: qcom,amoled { + compatible = "qcom,qpnp-amoled-regulator"; + status = "disabled"; + + oledb_vreg: oledb@e000 { + reg = <0xe000 0x100>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <4925000>; + regulator-max-microvolt = <8100000>; + qcom,swire-control; + }; + + ab_vreg: ab@de00 { + reg = <0xde00 0x100>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6100000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <5400000>; + qcom,swire-control; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi index b428a4ddcb38..d776127b0bb7 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi @@ -34,6 +34,10 @@ status = "ok"; }; +&pm6150a_amoled { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi index 9adac18507d8..f78baa775f2b 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -120,6 +120,10 @@ status = "ok"; }; +&pm6150a_amoled { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3"; -- GitLab From cc53a41874f369775866a7e31bda66f16d3bb3f2 Mon Sep 17 00:00:00 2001 From: Hardik Arya Date: Tue, 8 Jan 2019 11:48:54 +0530 Subject: [PATCH 0922/1286] diag: Assign dci_client_id properly while client registration Currently while doing dci client registration dci_client_id is assigned by incrementing previous id. Starting dci clients multiple times can make id equal to error types and dci client registration can fail. The patch assigns dci_client_id properly and un-assigns it while deinit of client. Change-Id: Idd13166f5edb680f8c97c538a76ce613af3a1e8e Signed-off-by: Hardik Arya --- drivers/char/diag/diag_dci.c | 32 ++++++++++++++++++++++---------- drivers/char/diag/diag_dci.h | 3 +-- drivers/char/diag/diagchar.h | 3 ++- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c index 2ff015779ff8..df68ffc55d61 100644 --- a/drivers/char/diag/diag_dci.c +++ b/drivers/char/diag/diag_dci.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2760,10 +2760,11 @@ static int diag_dci_init_ops_tbl(void) int diag_dci_init(void) { - int ret = 0; + int ret = 0, i; driver->dci_tag = 0; - driver->dci_client_id = 0; + for (i = 0; i < MAX_DCI_CLIENTS; i++) + driver->dci_client_id[i] = 0; driver->num_dci_client = 0; mutex_init(&driver->dci_mutex); mutex_init(&dci_log_mask_mutex); @@ -2959,8 +2960,8 @@ int diag_dci_register_client(struct diag_dci_reg_tbl_t *reg_entry) mutex_init(&new_entry->write_buf_mutex); new_entry->dci_log_mask = vzalloc(DCI_LOG_MASK_SIZE); if (!new_entry->dci_log_mask) { - pr_err("diag: Unable to create log mask for client, %d", - driver->dci_client_id); + pr_err("diag: Unable to create log mask for DCI client, tgid: %d\n", + current->tgid); goto fail_alloc; } create_dci_log_mask_tbl(new_entry->dci_log_mask, DCI_LOG_MASK_CLEAN); @@ -3009,17 +3010,24 @@ int diag_dci_register_client(struct diag_dci_reg_tbl_t *reg_entry) proc_buf->buf_curr = proc_buf->buf_primary; } - list_add_tail(&new_entry->track, &driver->dci_client_list); - driver->dci_client_id++; - new_entry->client_info.client_id = driver->dci_client_id; - reg_entry->client_id = driver->dci_client_id; + for (i = 0; i < MAX_DCI_CLIENTS; i++) { + if (driver->dci_client_id[i] == 0) + break; + } + + if (i == MAX_DCI_CLIENTS) + goto fail_alloc; + driver->dci_client_id[i] = 1; + new_entry->client_info.client_id = i+1; + reg_entry->client_id = i+1; driver->num_dci_client++; + list_add_tail(&new_entry->track, &driver->dci_client_list); if (driver->num_dci_client == 1) diag_update_proc_vote(DIAG_PROC_DCI, VOTE_UP, reg_entry->token); queue_work(driver->diag_real_time_wq, &driver->diag_real_time_work); mutex_unlock(&driver->dci_mutex); - return driver->dci_client_id; + return reg_entry->client_id; fail_alloc: if (new_entry) { @@ -3078,7 +3086,11 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry) */ if (!list_empty(&entry->track)) list_del(&entry->track); + + if (entry->client_info.client_id > MAX_DCI_CLIENTS) + return DIAG_DCI_NO_REG; driver->num_dci_client--; + driver->dci_client_id[entry->client_info.client_id - 1] = 0; /* * Clear the client's log and event masks, update the cumulative * masks and send the masks to peripherals diff --git a/drivers/char/diag/diag_dci.h b/drivers/char/diag/diag_dci.h index a5a6dc3f9ba4..24b8782d29dd 100644 --- a/drivers/char/diag/diag_dci.h +++ b/drivers/char/diag/diag_dci.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,7 +12,6 @@ #ifndef DIAG_DCI_H #define DIAG_DCI_H -#define MAX_DCI_CLIENTS 10 #define DCI_PKT_RSP_CODE 0x93 #define DCI_DELAYED_RSP_CODE 0x94 #define DCI_CONTROL_PKT_CODE 0x9A diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h index d48d34632558..7cb1d0c63243 100644 --- a/drivers/char/diag/diagchar.h +++ b/drivers/char/diag/diagchar.h @@ -292,6 +292,7 @@ do { \ #define DIAG_CNTL_TYPE 2 #define DIAG_DCI_TYPE 3 +#define MAX_DCI_CLIENTS 10 /* * List of diag ids * 0 is reserved for unknown diag id, 1 for apps, diag ids @@ -595,7 +596,7 @@ struct diagchar_dev { struct list_head dci_req_list; struct list_head dci_client_list; int dci_tag; - int dci_client_id; + int dci_client_id[MAX_DCI_CLIENTS]; struct mutex dci_mutex; int num_dci_client; unsigned char *apps_dci_buf; -- GitLab From 7cd899cc8ed429e7ca3b64d57394e39acc2f8fe9 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Thu, 10 Jan 2019 19:07:47 +0530 Subject: [PATCH 0923/1286] ARM: dts: msm: add bus scaling & gdsc info for apps smmu on trinket Add bus scaling and GDSC for APPS SMMU which are voted before accessing its address space. Change-Id: I1563f7b7bc76fd3ab7e3acb216bc76aa05b915e8 Signed-off-by: Charan Teja Reddy --- .../boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 89 ++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index d8f4149e6c81..b4c49dc1146c 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -11,6 +11,7 @@ */ #include +#include &soc { kgsl_smmu: kgsl-smmu@0x59a0000 { @@ -132,13 +133,42 @@ , , ; - + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; anoc_1_tbu: anoc_1_tbu@0xc785000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0xc785000 0x1000>, <0xc782200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; }; mm_rt_tbu: mm_rt_tbu@0xc789000 { @@ -147,6 +177,25 @@ <0xc782208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; }; mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { @@ -155,6 +204,25 @@ <0xc782210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; }; cdsp_tbu: cdsp_tbu@0xc791000 { @@ -163,6 +231,25 @@ <0xc782218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; }; }; -- GitLab From 80b5a98cd754e3036f0f9e51fe2b7137e59bc6bb Mon Sep 17 00:00:00 2001 From: Can Guo Date: Wed, 16 Jan 2019 13:51:15 +0800 Subject: [PATCH 0924/1286] scsi: ufs: fix race a condition between rls handler and err handler In below call stack, rls handler and err handler are both scheduled but rls handler is queued in front of err handler. In this scenario, rls handler is waiting for err handler to recovery the link back to active. However, as rls handler and err handler are on the same work queue, err handler can only be executed after rls handler returns. In order to avoid this race condition, rls work needs to return first when it finds the host state is no longer functional, which means err handler has been scheduled due to other reasons. B::v.f_/task_0xFFFFFFE2B3BC1180 ... -020|arch_local_irq_restore -020|__raw_spin_unlock_irqrestore -020|raw_spin_unlock_irqrestore -021|spin_unlock_irqrestore -021|ufshcd_hold -022|ufshcd_hold_all -023|ufshcd_wait_for_doorbell_clr -024|ufshcd_rls_handler -025|__read_once_size -025|static_key_count -025|static_key_false -025|trace_workqueue_execute_end -025|process_one_work -026|__read_once_size -026|list_empty -026|worker_thread -027|kthread -028|ret_from_fork ---|end of frame B::v.f_/task_0xFFFFFFE1D1674480 -000|__switch_to -001|__schedule -002|schedule -003|schedule_timeout -004|do_wait_for_common -005|wait_for_common -006|wait_for_completion -007|flush_work -008|ufshcd_link_recovery -009|ufshcd_uic_hibern8_exit -010|ufshcd_is_card_online -010|ufshcd_resume -011|ufshcd_system_resume -012|ufshcd_pltfrm_resume -013|platform_pm_resume -014|__read_once_size -014|static_key_count -014|static_key_false -014|trace_device_pm_callback_end -014|dpm_run_callback -015|device_resume ... ---|end of frame Change-Id: Ib5cb16b582e1605d8dea4b1c33acff8172339f50 Signed-off-by: Can Guo --- drivers/scsi/ufs/ufshcd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index fa15ebd825c1..0424a41bf886 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -2177,7 +2177,8 @@ int ufshcd_hold(struct ufs_hba *hba, bool async) spin_unlock_irqrestore(hba->host->host_lock, flags); flush_work(&hba->clk_gating.ungate_work); spin_lock_irqsave(hba->host->host_lock, flags); - goto start; + if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) + goto start; } break; case REQ_CLKS_OFF: -- GitLab From 4fe9d5d9ed7edc06c4f5950a03ba4bb0e64fa287 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 14 Jan 2019 17:23:12 +0530 Subject: [PATCH 0925/1286] soc: qcom: qmi: Remove txn idr entry in qmi handle release txn idr entry contains local pointer, which can go out of context if the calling function exits. Qmi handle can be released from other thread context(SSR), where iterating over pending transactions list if txn idr entry is not removed it results in crash in next iteration as the previous txn idr entry is not valid. CR-Fixed: 2373541 Change-Id: I0c96a575fb198115532de9977095f2c056742b33 Signed-off-by: Deepak Kumar Singh --- drivers/soc/qcom/qmi_interface.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index d6a419e47452..d940cca0a3dc 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -353,8 +353,12 @@ int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout) ret = wait_for_completion_timeout(&txn->completion, timeout); - if (txn->result == -ENETRESET) + mutex_lock(&txn->lock); + if (txn->result == -ENETRESET) { + mutex_unlock(&txn->lock); return txn->result; + } + mutex_unlock(&txn->lock); mutex_lock(&qmi->txn_lock); mutex_lock(&txn->lock); @@ -712,8 +716,11 @@ void qmi_handle_release(struct qmi_handle *qmi) mutex_lock(&qmi->txn_lock); idr_for_each_entry(&qmi->txns, txn, txn_id) { + mutex_lock(&txn->lock); + idr_remove(&qmi->txns, txn->id); txn->result = -ENETRESET; complete(&txn->completion); + mutex_unlock(&txn->lock); } mutex_unlock(&qmi->txn_lock); idr_destroy(&qmi->txns); -- GitLab From b91b29821531b649d310312af0a65ba8faa0da05 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Thu, 3 Jan 2019 17:47:14 +0530 Subject: [PATCH 0926/1286] msm: camera: Adds state variable in mem manager Add state variable for camera mem manager to show initialization status. Ensure that all operations are rejected before initialization. Change-Id: I1ddbaaf6fbed59e4804476562c97f6895d99e916 Signed-off-by: Trishansh Bhardwaj --- .../msm/camera/cam_req_mgr/cam_mem_mgr.c | 61 ++++++++++++++++++- .../msm/camera/cam_req_mgr/cam_mem_mgr.h | 8 ++- 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c index 8fd97a72e052..e3104bd20e1b 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,6 +25,7 @@ #include "cam_debug_util.h" static struct cam_mem_table tbl; +static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED); static int cam_mem_util_get_dma_dir(uint32_t flags) { @@ -146,6 +147,8 @@ int cam_mem_mgr_init(void) } mutex_init(&tbl.m_lock); + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED); + return 0; } @@ -186,6 +189,11 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, *len_ptr = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) return -EINVAL; @@ -231,6 +239,11 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) int idx; struct dma_buf *dmabuf = NULL; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!buf_handle || !vaddr_ptr || !len) return -EINVAL; @@ -275,6 +288,11 @@ int cam_mem_put_cpu_buf(int32_t buf_handle) int idx; struct dma_buf *dmabuf = NULL; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!buf_handle) return -EINVAL; @@ -316,6 +334,11 @@ int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) uint32_t cache_dir; unsigned long dmabuf_flag = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) return -EINVAL; @@ -605,6 +628,11 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) uintptr_t kvaddr = 0; size_t klen; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) { CAM_ERR(CAM_MEM, " Invalid argument"); return -EINVAL; @@ -722,6 +750,11 @@ int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd) dma_addr_t hw_vaddr = 0; size_t len = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd || (cmd->fd < 0)) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -929,6 +962,7 @@ static int cam_mem_mgr_cleanup_table(void) void cam_mem_mgr_deinit(void) { + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED); cam_mem_mgr_cleanup_table(); mutex_lock(&tbl.m_lock); bitmap_zero(tbl.bitmap, tbl.bits); @@ -1025,6 +1059,11 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) int idx; int rc; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!cmd) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -1073,6 +1112,11 @@ int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp || !out) { CAM_ERR(CAM_MEM, "Invalid params"); return -EINVAL; @@ -1193,6 +1237,11 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) int32_t idx; int rc; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; @@ -1241,6 +1290,11 @@ int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, int32_t smmu_hdl = 0; int32_t num_hdl = 0; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp || !out) { CAM_ERR(CAM_MEM, "Invalid param(s)"); return -EINVAL; @@ -1330,6 +1384,11 @@ int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) int rc; int32_t smmu_hdl; + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + if (!inp) { CAM_ERR(CAM_MEM, "Invalid argument"); return -EINVAL; diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h index 4c75b0e043ec..91d1c3917d6f 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_mem_mgr.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,6 +20,12 @@ #define CAM_MEM_BUFQ_MAX 1024 +/* Enum for possible mem mgr states */ +enum cam_mem_mgr_state { + CAM_MEM_MGR_UNINITIALIZED, + CAM_MEM_MGR_INITIALIZED, +}; + /*Enum for possible SMMU operations */ enum cam_smmu_mapping_client { CAM_SMMU_MAPPING_USER, -- GitLab From ac295a5259835d248509ba8246322e3f54be26ed Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Sun, 13 Jan 2019 12:49:34 +0530 Subject: [PATCH 0927/1286] iommu: arm-smmu: return EPROBE_DEFER when bus scaling is not available On some targets, rpm-adhoc driver is used instead of rpmh that uses fs_initcall for driver registration. Since smmu driver uses subsys_initcall, return EPROBE_DEFER when bus scaling is not available. Change-Id: I53359a4f013ce251eb3e5ce6bd6cf0b2979f7e5f Signed-off-by: Charan Teja Reddy --- drivers/iommu/arm-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 0e6e30008654..e63faa4b9a33 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -4328,7 +4328,7 @@ static int arm_smmu_init_bus_scaling(struct arm_smmu_power_resources *pwr) pwr->bus_client = msm_bus_scale_register_client(pwr->bus_dt_data); if (!pwr->bus_client) { dev_err(dev, "Bus client registration failed\n"); - return -EINVAL; + return -EPROBE_DEFER; } return 0; -- GitLab From 14ef85486151c128a08dc5a21a2fa8a7a6b4883b Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Tue, 11 Dec 2018 22:28:50 +0530 Subject: [PATCH 0928/1286] ARM: dts: msm: Fix GPIO mapping of SE9 SPI usecase on SM8150 SE9 SPI usecase on SM8150 was incorrectly mapped to GPIOs 38-41 instead of 39-42. Fix the same. Change-Id: Id8c226ad6c2d6f1acffc92797ab16e4c700b78bf Signed-off-by: Ajay Agarwal --- arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi index 6af0687eed0c..93e6f4ad5d1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1143,14 +1143,14 @@ qupv3_se9_spi_pins: qupv3_se9_spi_pins { qupv3_se9_spi_active: qupv3_se9_spi_active { mux { - pins = "gpio38", "gpio39", "gpio40", - "gpio41"; + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; function = "qup9"; }; config { - pins = "gpio38", "gpio39", "gpio40", - "gpio41"; + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; drive-strength = <6>; bias-disable; }; @@ -1158,14 +1158,14 @@ qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { mux { - pins = "gpio38", "gpio39", "gpio40", - "gpio41"; + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; function = "gpio"; }; config { - pins = "gpio38", "gpio39", "gpio40", - "gpio41"; + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; drive-strength = <6>; bias-disable; }; -- GitLab From a9f5ecbbe3a9d9b37cb8bc090d6d8a3a2fb78bf6 Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Wed, 16 Jan 2019 12:50:00 +0530 Subject: [PATCH 0929/1286] ARM: dts: msm: Disable IO Cohernecy in trinket fastRPC DT entries Hardware does not support SMMU IO coherency. Remove dma-coherent property from fastRPC context bank DT entries. Change-Id: I1943c7b1ddb83c2df8be8e4410c6b0b836b4810a Acked-by: Vishnu Karthik D Signed-off-by: Mohammed Nayeem Ur Rahman Signed-off-by: Tharun Kumar Merugu --- arch/arm64/boot/dts/qcom/trinket.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index d509f98982f0..740907ba6650 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1444,42 +1444,36 @@ compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C01 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb2 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C02 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb3 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C03 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb4 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C04 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb5 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C05 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb6 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C06 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb9 { @@ -1487,7 +1481,6 @@ label = "cdsprpc-smd"; qcom,secure-context-bank; iommus = <&apps_smmu 0x0C09 0x0>; - dma-coherent; }; qcom,msm_fastrpc_compute_cb10 { @@ -1497,7 +1490,6 @@ <&apps_smmu 0x0044 0x0>; shared-sid = <2>; shared-cb = <5>; - dma-coherent; }; }; -- GitLab From 0ac4a5252119e2c53cc0fd5ef9a9aac54fcfe136 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Wed, 16 Jan 2019 14:25:14 +0530 Subject: [PATCH 0930/1286] ARM: dts: msm: Add label for reserved memory on sm6150 Add label for reserved memory device tree node on sm6150. Change-Id: Ic25c8841474182581123d4a013a1a64a137af664 Signed-off-by: Vijayanand Jitta --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 2e5c7a08f10d..796ab2dd5763 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -498,7 +498,7 @@ }; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; -- GitLab From edb77fec129e8c8b1a255e615ac9747b65f5b5cc Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 11 Jan 2019 19:44:36 +0530 Subject: [PATCH 0931/1286] ARM: dts: msm: Add new platforms for Trinket SoC Add below platforms supported with Trinket SoC: 1. Trinket IDP with External Audio codec. 2. Trinket IDP with External Audio Codec over USB type C. 3. Trinket IDP with Audio over USB type C. Change-Id: I99fa9c38dfd536b25313d4862a26e1a721aa547d Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/Makefile | 13 ++++++++-- .../trinket-external-codec-idp-overlay.dts | 26 +++++++++++++++++++ .../dts/qcom/trinket-external-codec-idp.dts | 22 ++++++++++++++++ ...rinket-usbc-external-codec-idp-overlay.dts | 26 +++++++++++++++++++ .../qcom/trinket-usbc-external-codec-idp.dts | 22 ++++++++++++++++ .../dts/qcom/trinket-usbc-idp-overlay.dts | 26 +++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts | 22 ++++++++++++++++ 7 files changed, 155 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b4b15e938ad7..adace640973d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -197,15 +197,24 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_TRINKET) += \ trinket-rumi-overlay.dtbo \ trinket-idp-overlay.dtbo \ - trinket-qrd-overlay.dtbo + trinket-qrd-overlay.dtbo \ + trinket-external-codec-idp-overlay.dtbo \ + trinket-usbc-external-codec-idp-overlay.dtbo \ + trinket-usbc-idp-overlay.dtbo trinket-rumi-overlay.dtbo-base := trinket.dtb trinket-idp-overlay.dtbo-base := trinket.dtb trinket-qrd-overlay.dtbo-base := trinket.dtb +trinket-external-codec-idp-overlay.dtbo-base := trinket.dtb +trinket-usbc-external-codec-idp-overlay.dtbo-base := trinket.dtb +trinket-usbc-idp-overlay.dtbo-base := trinket.dtb else dtb-$(CONFIG_ARCH_TRINKET) += trinket-rumi.dtb \ trinket-idp.dtb \ - trinket-qrd.dtb + trinket-qrd.dtb \ + trinket-external-codec-idp.dtb \ + trinket-usbc-external-codec-idp.dtb \ + trinket-usbc-idp.dtb endif dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ diff --git a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..c8fe133cb177 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" + +/ { + model = "Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 1>; +}; + diff --git a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts new file mode 100644 index 000000000000..97e8a31ea423 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..f69f9ba4dbac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" + +/ { + model = "USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 3>; +}; + diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp.dts new file mode 100644 index 000000000000..0ae4e76e5254 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts new file mode 100644 index 000000000000..6fc501c8e333 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 2>; +}; + diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts new file mode 100644 index 000000000000..8f1fc5827f06 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket USBC Audio IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 2>; +}; -- GitLab From 745ba3f4fb378bc6f85d755e2fced781622975ae Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sat, 12 Jan 2019 10:17:56 +0530 Subject: [PATCH 0932/1286] ARM: dts: msm: Populate OPP table for GFX clock on TRINKET OPP table population for gfx3d clock source is required for GPU thermal mitigation so add support for the same. Change-Id: I9bd67420010a15e30951632574f0f1df9942951a Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f6ab706410d6..ac583fec6109 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -776,6 +776,7 @@ reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; #clock-cells = <1>; }; -- GitLab From 6afeec39993161533598a608f5a16105e1d0ea90 Mon Sep 17 00:00:00 2001 From: Mangesh Kunchamwar Date: Thu, 10 Jan 2019 15:53:40 +0530 Subject: [PATCH 0933/1286] ARM: dts: msm: add support for LPASS core hw clock in QCS405 Add clock node for lpass core hardware clock. Change-Id: Ibb946afa04a2d19e8ec509cc560dd5d575b51628 Signed-off-by: Mangesh Kunchamwar --- arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-audio.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi | 6 +++--- 10 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi index 397c26b81bd9..e7ae31f13006 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -16,8 +16,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi index 70a584a99e2c..b7f681e9a043 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,8 +48,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-audio.dtsi b/arch/arm64/boot/dts/qcom/qcs405-audio.dtsi index d250938810b7..7a94f6db3905 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-audio.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -38,9 +38,9 @@ }; &q6core { - lpass_npa_rsc_island: island_lpass_npa_rsc { + lpass_core_hw_vote: vote_lpass_core_hw { compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <9>; + qcom,codec-ext-clk-src = ; #clock-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi index c0bf27143dc8..2707d5b4b995 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,8 +48,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi index 1cec8d27fe5c..c1df3ff51001 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,8 +48,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi index 98b961ddf71d..2ddd66b5d879 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,8 +48,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi b/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi index 2c88cca239b7..ef7a3c487e9b 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-lpi.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,8 +28,8 @@ <0x00000170>, <0x00000180>, <0x00000190>, <0x00000200>, <0x00000210>; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; cdc_dmic01_clk_active: dmic01_clk_active { mux { pins = "gpio8"; diff --git a/arch/arm64/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi index 5517e6373c25..3d7f604320c3 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,8 +48,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi index 791a07bf60e5..1d30aa2a049c 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,8 +28,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi index 7afa564a38af..b6a6314022a1 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -64,8 +64,8 @@ &q6core { bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "island_lpass_npa_rsc"; - clocks = <&lpass_npa_rsc_island 0>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; qcom,num-macros = <2>; }; }; -- GitLab From 1af61b7c846fdbf99cfa7cc6469294a3282bf606 Mon Sep 17 00:00:00 2001 From: Venkata Jagadeesh Garaga Date: Thu, 10 Jan 2019 15:53:27 +0530 Subject: [PATCH 0934/1286] ARM: dts: msm: Add bluetooth node for trinket - Bluetooth functionality is provided by wcn3990/wcn3950. - Add device tree entry having various voltage regulators - Add uart node for bt - Add slimbus code entry Change-Id: I7b4af7cfa1623bd933bd7b2b2cbb23043517da9e Signed-off-by: Venkata Jagadeesh Garaga --- arch/arm64/boot/dts/qcom/trinket.dtsi | 32 ++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f6ab706410d6..646f8749fdf0 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1906,6 +1906,24 @@ <&apps_smmu 0x01B4 0x0011>; }; + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm6125_l9>; + qca,bt-vdd-core-supply = <&pm6125_l17>; + qca,bt-vdd-pa-supply = <&pm6125_l23>; + qca,bt-vdd-xtal-supply = <&pm6125_l16>; + + qca,bt-vdd-io-voltage-level = <1700000 1900000>; /* IO */ + qca,bt-vdd-core-voltage-level = <1245000 1350000>; /* RFA */ + qca,bt-vdd-pa-voltage-level = <3200000 3400000>; /*chain0 */ + qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; /* XO */ + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + }; + slim_aud: slim@a2c0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; @@ -1936,13 +1954,21 @@ reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 403 0>, <0 404 0>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - status = "disabled"; + status = "ok"; qcom,iommu-s1-bypass; iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; iommus = <&apps_smmu 0x73 0x0>; }; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; }; sdcc1_ice: sdcc1ice@4748000{ @@ -2578,6 +2604,10 @@ status = "ok"; }; +&qupv3_se9_4uart { + status = "ok"; +}; + &qupv3_se1_i2c { status = "ok"; fsa4480: fsa4480@43 { -- GitLab From 0f1759130df4060d66b28413fed22d50522646c1 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Fri, 11 Jan 2019 16:39:52 +0530 Subject: [PATCH 0935/1286] qcom-geni-se: Geni common driver ICB vote logic changes Use separate DDR and Corex/2x paths to put ICB vote. Geni common driver aggregates the avg bandwidth put by individual drivers to vote for DDR path bus bandwidth and for corex/core2x separately. Common driver takes Instantaneous bandwidth put by individual drivers also into consideration to put vote to ICB driver for required bandwidth. Change-Id: I0c729ea1590a8759b3985cfd0d81ecd57a795a85 Signed-off-by: Prudhvi Yarlagadda --- .../bindings/platform/msm/qcom-geni-se.txt | 3 + arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi | 17 +- drivers/platform/msm/qcom-geni-se.c | 333 ++++++++++++++++-- include/linux/qcom-geni-se.h | 13 +- 4 files changed, 328 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt b/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt index 7da95f8b795f..a42f491fd9d7 100644 --- a/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt +++ b/Documentation/devicetree/bindings/platform/msm/qcom-geni-se.txt @@ -13,6 +13,9 @@ Required properties: Optional properties: - qcom,iommu-s1-bypass: Boolean flag to bypass IOMMU stage 1 translation. +- qcom,msm-bus,num-paths: Number of paths to put vote for. +- qcom,msm-bus,vectors-bus-ids: Master and slave Endpoint IDs for DDR + and Corex/2x paths. Optional subnodes: qcom,iommu_qupv3_geni_se_cb: Child node representing the QUPV3 context diff --git a/arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi b/arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi index e6fbbcc666b8..519d1ec43563 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,8 +31,12 @@ qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x04ac0000 0x2000>; - qcom,bus-mas-id = ; - qcom,bus-slv-id = ; + + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,iommu-s1-bypass; iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { @@ -227,8 +231,11 @@ qupv3_1: qcom,qupv3_1_geni_se@4cc0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x04cc0000 0x2000>; - qcom,bus-mas-id = ; - qcom,bus-slv-id = ; + + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; qcom,iommu-s1-bypass; iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { diff --git a/drivers/platform/msm/qcom-geni-se.c b/drivers/platform/msm/qcom-geni-se.c index c836af21b510..3136ae9036d3 100644 --- a/drivers/platform/msm/qcom-geni-se.c +++ b/drivers/platform/msm/qcom-geni-se.c @@ -44,6 +44,11 @@ static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, 100000000, 150000000, 200000000, 236000000}; +struct bus_vectors { + int src; + int dst; +}; + /** * @struct geni_se_device - Data structure to represent the QUPv3 Core * @dev: Device pointer of the QUPv3 core. @@ -53,18 +58,32 @@ static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, * @iommu_s1_bypass: Bypass IOMMU stage 1 translation. * @base: Base address of this instance of QUPv3 core. * @bus_bw: Client handle to the bus bandwidth request. + * @bus_bw_noc: Client handle to the QUP clock and DDR path bus + bandwidth request. * @bus_mas_id: Master Endpoint ID for bus BW request. * @bus_slv_id: Slave Endpoint ID for bus BW request. * @geni_dev_lock: Lock to protect the bus ab & ib values, list. * @ab_list_head: Sorted resource list based on average bus BW. * @ib_list_head: Sorted resource list based on instantaneous bus BW. + * @ab_list_head_noc: Sorted resource list based on average DDR path bus BW. + * @ib_list_head_noc: Sorted resource list based on instantaneous DDR path + bus BW. * @cur_ab: Current Bus Average BW request value. * @cur_ib: Current Bus Instantaneous BW request value. + * @cur_ab_noc: Current DDR Bus Average BW request value. + * @cur_ib_noc: Current DDR Bus Instantaneous BW request value. * @bus_bw_set: Clock plan for the bus driver. + * @bus_bw_set_noc: Clock plan for DDR path. * @cur_bus_bw_idx: Current index within the bus clock plan. + * @cur_bus_bw_idx_noc: Current index within the DDR path clock plan. * @num_clk_levels: Number of valid clock levels in clk_perf_tbl. * @clk_perf_tbl: Table of clock frequency input to Serial Engine clock. - * @log_ctx: Logging context to hold the debug information + * @log_ctx: Logging context to hold the debug information. + * @vectors: Structure to store Master End and Slave End IDs for + QUPv3 clock and DDR path bus BW request. + * @num_paths: Two paths. QUPv3 clock and DDR paths. + * @num_usecases: One usecase to vote for both QUPv3 clock and DDR paths. + * @pdata: To register our client handle with the ICB driver. */ struct geni_se_device { struct device *dev; @@ -74,19 +93,31 @@ struct geni_se_device { bool iommu_s1_bypass; void __iomem *base; struct msm_bus_client_handle *bus_bw; + uint32_t bus_bw_noc; u32 bus_mas_id; u32 bus_slv_id; struct mutex geni_dev_lock; struct list_head ab_list_head; struct list_head ib_list_head; + struct list_head ab_list_head_noc; + struct list_head ib_list_head_noc; unsigned long cur_ab; unsigned long cur_ib; + unsigned long cur_ab_noc; + unsigned long cur_ib_noc; int bus_bw_set_size; + int bus_bw_set_size_noc; unsigned long *bus_bw_set; + unsigned long *bus_bw_set_noc; int cur_bus_bw_idx; + int cur_bus_bw_idx_noc; unsigned int num_clk_levels; unsigned long *clk_perf_tbl; void *log_ctx; + struct bus_vectors *vectors; + int num_paths; + int num_usecases; + struct msm_bus_scale_pdata *pdata; }; /* Offset of QUPV3 Hardware Version Register */ @@ -651,11 +682,37 @@ static bool geni_se_check_bus_bw(struct geni_se_device *geni_se_dev) return bus_bw_update; } +static bool geni_se_check_bus_bw_noc(struct geni_se_device *geni_se_dev) +{ + int i; + int new_bus_bw_idx = geni_se_dev->bus_bw_set_size_noc - 1; + unsigned long new_bus_bw; + bool bus_bw_update = false; + + new_bus_bw = max(geni_se_dev->cur_ib_noc, geni_se_dev->cur_ab_noc) / + DEFAULT_BUS_WIDTH; + + for (i = 0; i < geni_se_dev->bus_bw_set_size_noc; i++) { + if (geni_se_dev->bus_bw_set_noc[i] >= new_bus_bw) { + new_bus_bw_idx = i; + break; + } + } + + if (geni_se_dev->cur_bus_bw_idx_noc != new_bus_bw_idx) { + geni_se_dev->cur_bus_bw_idx_noc = new_bus_bw_idx; + bus_bw_update = true; + } + + return bus_bw_update; +} + static int geni_se_rmv_ab_ib(struct geni_se_device *geni_se_dev, struct se_geni_rsc *rsc) { struct se_geni_rsc *tmp; bool bus_bw_update = false; + bool bus_bw_update_noc = false; int ret = 0; if (unlikely(list_empty(&rsc->ab_list) || list_empty(&rsc->ib_list))) @@ -674,14 +731,51 @@ static int geni_se_rmv_ab_ib(struct geni_se_device *geni_se_dev, geni_se_dev->cur_ib = 0; bus_bw_update = geni_se_check_bus_bw(geni_se_dev); - if (bus_bw_update) + + if (geni_se_dev->num_paths == 2) { + geni_se_dev->pdata->usecase[1].vectors[0].ab = + geni_se_dev->cur_ab; + geni_se_dev->pdata->usecase[1].vectors[0].ib = + geni_se_dev->cur_ib; + } + + if (bus_bw_update && geni_se_dev->num_paths != 2) { ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, geni_se_dev->cur_ab, geni_se_dev->cur_ib); - GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, + GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, "%s: %s: cur_ab_ib(%lu:%lu) req_ab_ib(%lu:%lu) %d\n", __func__, dev_name(rsc->ctrl_dev), geni_se_dev->cur_ab, geni_se_dev->cur_ib, rsc->ab, rsc->ib, bus_bw_update); + } + + if (geni_se_dev->num_paths == 2) { + if (unlikely(list_empty(&rsc->ab_list_noc) || + list_empty(&rsc->ib_list_noc))) + return -EINVAL; + + list_del_init(&rsc->ab_list_noc); + geni_se_dev->cur_ab_noc -= rsc->ab_noc; + + list_del_init(&rsc->ib_list_noc); + tmp = list_first_entry_or_null(&geni_se_dev->ib_list_head_noc, + struct se_geni_rsc, ib_list_noc); + if (tmp && tmp->ib_noc != geni_se_dev->cur_ib_noc) + geni_se_dev->cur_ib_noc = tmp->ib_noc; + else if (!tmp && geni_se_dev->cur_ib_noc) + geni_se_dev->cur_ib_noc = 0; + + bus_bw_update_noc = geni_se_check_bus_bw_noc(geni_se_dev); + + geni_se_dev->pdata->usecase[1].vectors[1].ab = + geni_se_dev->cur_ab_noc; + geni_se_dev->pdata->usecase[1].vectors[1].ib = + geni_se_dev->cur_ib_noc; + + if (bus_bw_update_noc || bus_bw_update) + ret = msm_bus_scale_client_update_request + (geni_se_dev->bus_bw_noc, 1); + } mutex_unlock(&geni_se_dev->geni_dev_lock); return ret; } @@ -702,7 +796,8 @@ int se_geni_clks_off(struct se_geni_rsc *rsc) return -EINVAL; geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); - if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw)) + if (unlikely(!geni_se_dev || !(geni_se_dev->bus_bw || + geni_se_dev->bus_bw_noc))) return -ENODEV; clk_disable_unprepare(rsc->se_clk); @@ -713,6 +808,7 @@ int se_geni_clks_off(struct se_geni_rsc *rsc) if (ret) GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, "%s: Error %d during bus_bw_update\n", __func__, ret); + return ret; } EXPORT_SYMBOL(se_geni_clks_off); @@ -733,7 +829,9 @@ int se_geni_resources_off(struct se_geni_rsc *rsc) return -EINVAL; geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); - if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw)) + if (unlikely(!geni_se_dev || + !(geni_se_dev->bus_bw || + geni_se_dev->bus_bw_noc))) return -ENODEV; ret = se_geni_clks_off(rsc); @@ -753,10 +851,13 @@ static int geni_se_add_ab_ib(struct geni_se_device *geni_se_dev, { struct se_geni_rsc *tmp = NULL; struct list_head *ins_list_head; + struct list_head *ins_list_head_noc; bool bus_bw_update = false; + bool bus_bw_update_noc = false; int ret = 0; mutex_lock(&geni_se_dev->geni_dev_lock); + list_add(&rsc->ab_list, &geni_se_dev->ab_list_head); geni_se_dev->cur_ab += rsc->ab; @@ -772,14 +873,51 @@ static int geni_se_add_ab_ib(struct geni_se_device *geni_se_dev, geni_se_dev->cur_ib = rsc->ib; bus_bw_update = geni_se_check_bus_bw(geni_se_dev); - if (bus_bw_update) + + if (geni_se_dev->num_paths == 2) { + geni_se_dev->pdata->usecase[1].vectors[0].ab = + geni_se_dev->cur_ab; + geni_se_dev->pdata->usecase[1].vectors[0].ib = + geni_se_dev->cur_ib; + } + + if (bus_bw_update && geni_se_dev->num_paths != 2) { ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, geni_se_dev->cur_ab, geni_se_dev->cur_ib); - GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, - "%s: %s: cur_ab_ib(%lu:%lu) req_ab_ib(%lu:%lu) %d\n", - __func__, dev_name(rsc->ctrl_dev), geni_se_dev->cur_ab, - geni_se_dev->cur_ib, rsc->ab, rsc->ib, bus_bw_update); + GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, + "%s: %lu:%lu (%lu:%lu) %d\n", __func__, + geni_se_dev->cur_ab, geni_se_dev->cur_ib, + rsc->ab, rsc->ib, bus_bw_update); + } + + if (geni_se_dev->num_paths == 2) { + + list_add(&rsc->ab_list_noc, &geni_se_dev->ab_list_head_noc); + geni_se_dev->cur_ab_noc += rsc->ab_noc; + ins_list_head_noc = &geni_se_dev->ib_list_head_noc; + + list_for_each_entry(tmp, &geni_se_dev->ib_list_head_noc, + ib_list_noc) { + if (tmp->ib < rsc->ib) + break; + ins_list_head_noc = &tmp->ib_list_noc; + } + list_add(&rsc->ib_list_noc, ins_list_head_noc); + + if (ins_list_head_noc == &geni_se_dev->ib_list_head_noc) + geni_se_dev->cur_ib_noc = rsc->ib_noc; + + bus_bw_update_noc = geni_se_check_bus_bw_noc(geni_se_dev); + + geni_se_dev->pdata->usecase[1].vectors[1].ab = + geni_se_dev->cur_ab_noc; + geni_se_dev->pdata->usecase[1].vectors[1].ib = + geni_se_dev->cur_ib_noc; + if (bus_bw_update_noc || bus_bw_update) + ret = msm_bus_scale_client_update_request + (geni_se_dev->bus_bw_noc, 1); + } mutex_unlock(&geni_se_dev->geni_dev_lock); return ret; } @@ -890,21 +1028,42 @@ int geni_se_resources_init(struct se_geni_rsc *rsc, if (unlikely(!geni_se_dev)) return -EPROBE_DEFER; - if (unlikely(IS_ERR_OR_NULL(geni_se_dev->bus_bw))) { - geni_se_dev->bus_bw = msm_bus_scale_register( - geni_se_dev->bus_mas_id, - geni_se_dev->bus_slv_id, + if (geni_se_dev->num_paths == 2) { + if (unlikely(!(geni_se_dev->bus_bw_noc))) { + geni_se_dev->bus_bw_noc = + msm_bus_scale_register_client(geni_se_dev->pdata); + if (!(geni_se_dev->bus_bw_noc)) { + GENI_SE_ERR(geni_se_dev->log_ctx, + false, NULL, + "%s: Error creating bus client\n", __func__); + return -EFAULT; + } + } + + rsc->ab = ab; + rsc->ib = ab; + rsc->ab_noc = 0; + rsc->ib_noc = ib; + INIT_LIST_HEAD(&rsc->ab_list_noc); + INIT_LIST_HEAD(&rsc->ib_list_noc); + } else { + if (unlikely(IS_ERR_OR_NULL(geni_se_dev->bus_bw))) { + geni_se_dev->bus_bw = msm_bus_scale_register( + geni_se_dev->bus_mas_id, + geni_se_dev->bus_slv_id, (char *)dev_name(geni_se_dev->dev), - false); - if (IS_ERR_OR_NULL(geni_se_dev->bus_bw)) { - GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, + false); + if (IS_ERR_OR_NULL(geni_se_dev->bus_bw)) { + GENI_SE_ERR(geni_se_dev->log_ctx, + false, NULL, "%s: Error creating bus client\n", __func__); - return (int)PTR_ERR(geni_se_dev->bus_bw); + return (int)PTR_ERR(geni_se_dev->bus_bw); + } } + rsc->ab = ab; + rsc->ib = ib; } - rsc->ab = ab; - rsc->ib = ib; INIT_LIST_HEAD(&rsc->ab_list); INIT_LIST_HEAD(&rsc->ib_list); geni_se_iommu_map_and_attach(geni_se_dev); @@ -1435,6 +1594,87 @@ static const struct of_device_id geni_se_dt_match[] = { {} }; +static struct msm_bus_scale_pdata *ab_ib_register(struct platform_device *pdev, + struct geni_se_device *host) +{ + int rc = 0; + struct device *dev = &pdev->dev; + int i = 0, j, len; + bool mem_err = false; + const uint32_t *vec_arr = NULL; + struct msm_bus_scale_pdata *pdata = NULL; + struct msm_bus_paths *usecase = NULL; + + vec_arr = of_get_property(dev->of_node, + "qcom,msm-bus,vectors-bus-ids", &len); + if (vec_arr == NULL) { + pr_err("Error: Vector array not found\n"); + rc = 1; + goto out; + } + + if (len != host->num_paths * sizeof(uint32_t) * 2) { + pr_err("Error: Length-error on getting vectors\n"); + rc = 1; + goto out; + } + + + pdata = devm_kzalloc(dev, sizeof(struct msm_bus_scale_pdata), + GFP_KERNEL); + if (!pdata) { + mem_err = true; + goto out; + } + + pdata->name = (char *)dev_name(host->dev); + + pdata->num_usecases = 2; + + pdata->active_only = 0; + + usecase = devm_kzalloc(dev, (sizeof(struct msm_bus_paths) * + pdata->num_usecases), GFP_KERNEL); + if (!usecase) { + mem_err = true; + goto out; + } + + for (i = 0; i < pdata->num_usecases; i++) { + usecase[i].num_paths = host->num_paths; + usecase[i].vectors = devm_kzalloc(dev, host->num_paths * + sizeof(struct msm_bus_vectors), GFP_KERNEL); + if (!usecase[i].vectors) { + mem_err = true; + pr_err("Error: Mem alloc failure in vectors\n"); + goto out; + } + + for (j = 0; j < host->num_paths; j++) { + int index = (j * 2); + + usecase[i].vectors[j].src = + be32_to_cpu(vec_arr[index]); + usecase[i].vectors[j].dst = + be32_to_cpu(vec_arr[index + 1]); + usecase[i].vectors[j].ab = 0; + usecase[i].vectors[j].ib = 0; + } + } + + pdata->usecase = usecase; + + return pdata; +out: + if (mem_err) { + for ( ; i > 0; i--) + kfree(usecase[i-1].vectors); + kfree(usecase); + kfree(pdata); + } + return NULL; +} + static int geni_se_iommu_probe(struct device *dev) { struct geni_se_device *geni_se_dev; @@ -1495,28 +1735,57 @@ static int geni_se_probe(struct platform_device *pdev) } geni_se_dev->dev = dev; - ret = of_property_read_u32(dev->of_node, "qcom,bus-mas-id", - &geni_se_dev->bus_mas_id); - if (ret) { - dev_err(dev, "%s: Error missing bus master id\n", __func__); - devm_iounmap(dev, geni_se_dev->base); - devm_kfree(dev, geni_se_dev); + + ret = of_property_read_u32(dev->of_node, "qcom,msm-bus,num-paths", + &geni_se_dev->num_paths); + if (!ret) { + geni_se_dev->pdata = ab_ib_register(pdev, geni_se_dev); + if (geni_se_dev->pdata == NULL) { + dev_err(dev, + "%s: Error missing bus master and slave id\n", + __func__); + devm_iounmap(dev, geni_se_dev->base); + devm_kfree(dev, geni_se_dev); + } } - ret = of_property_read_u32(dev->of_node, "qcom,bus-slv-id", + + else { + geni_se_dev->num_paths = 1; + ret = of_property_read_u32(dev->of_node, "qcom,bus-mas-id", + &geni_se_dev->bus_mas_id); + if (ret) { + dev_err(dev, "%s: Error missing bus master id\n", + __func__); + devm_iounmap(dev, geni_se_dev->base); + devm_kfree(dev, geni_se_dev); + } + ret = of_property_read_u32(dev->of_node, "qcom,bus-slv-id", &geni_se_dev->bus_slv_id); - if (ret) { - dev_err(dev, "%s: Error missing bus slave id\n", __func__); - devm_iounmap(dev, geni_se_dev->base); - devm_kfree(dev, geni_se_dev); + if (ret) { + dev_err(dev, "%s: Error missing bus slave id\n", + __func__); + devm_iounmap(dev, geni_se_dev->base); + devm_kfree(dev, geni_se_dev); + } } geni_se_dev->iommu_s1_bypass = of_property_read_bool(dev->of_node, "qcom,iommu-s1-bypass"); geni_se_dev->bus_bw_set = default_bus_bw_set; - geni_se_dev->bus_bw_set_size = ARRAY_SIZE(default_bus_bw_set); + geni_se_dev->bus_bw_set_size = + ARRAY_SIZE(default_bus_bw_set); + if (geni_se_dev->num_paths == 2) { + geni_se_dev->bus_bw_set_noc = default_bus_bw_set; + geni_se_dev->bus_bw_set_size_noc = + ARRAY_SIZE(default_bus_bw_set); + } mutex_init(&geni_se_dev->iommu_lock); INIT_LIST_HEAD(&geni_se_dev->ab_list_head); INIT_LIST_HEAD(&geni_se_dev->ib_list_head); + if (geni_se_dev->num_paths == 2) { + INIT_LIST_HEAD(&geni_se_dev->ab_list_head_noc); + INIT_LIST_HEAD(&geni_se_dev->ib_list_head_noc); + } mutex_init(&geni_se_dev->geni_dev_lock); geni_se_dev->log_ctx = ipc_log_context_create(NUM_LOG_PAGES, dev_name(geni_se_dev->dev), 0); diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index a61f0014da82..9063cb41d07e 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -47,9 +47,16 @@ enum se_protocol_types { * @m_ahb_clk: Handle to the primary AHB clock. * @s_ahb_clk: Handle to the secondary AHB clock. * @ab_list: List Head of Average bus banwidth list. + * @ab_list_noc: List Head of Average DDR path bus + bandwidth list. * @ab: Average bus bandwidth request value. + * @ab_noc: Average DDR path bus bandwidth request value. * @ib_list: List Head of Instantaneous bus banwidth list. + * @ib_list_noc: List Head of Instantaneous DDR path bus + bandwidth list. * @ib: Instantaneous bus bandwidth request value. + * @ib_noc: Instantaneous DDR path bus bandwidth + request value. * @geni_pinctrl: Handle to the pinctrl configuration. * @geni_gpio_active: Handle to the default/active pinctrl state. * @geni_gpi_sleep: Handle to the sleep pinctrl state. @@ -61,9 +68,13 @@ struct se_geni_rsc { struct clk *m_ahb_clk; struct clk *s_ahb_clk; struct list_head ab_list; + struct list_head ab_list_noc; unsigned long ab; + unsigned long ab_noc; struct list_head ib_list; + struct list_head ib_list_noc; unsigned long ib; + unsigned long ib_noc; struct pinctrl *geni_pinctrl; struct pinctrl_state *geni_gpio_active; struct pinctrl_state *geni_gpio_sleep; -- GitLab From b5a1df4f4ab35e27fdea1775f46a3945368ef012 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 16 Jan 2019 15:15:44 +0530 Subject: [PATCH 0936/1286] ARM: dts: msm: Update stepwise and low limits thermal zones for TRINKET Update stepwise and low limits floor thermal_zone sensors for TRINKET based on latest TSENS floor plan recommendation. Update virtual sensor config as well based on new TSENS floor plan for TRINKET. Change-Id: Ie79dd2d6fa37ddd5aba64123b61b0542f61cc0a1 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-rumi.dtsi | 2 +- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 94 ++++++++++--------- drivers/thermal/qcom/qti_virtual_sensor.c | 13 ++- 3 files changed, 58 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi index 7e86aa4b7e9f..74e81c29e57e 100644 --- a/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-rumi.dtsi @@ -98,7 +98,7 @@ /delete-node/ camera-lowf; /delete-node/ video-lowf; /delete-node/ cpu-1-0-lowf; - /delete-node/ cpu-0-0-lowf; + /delete-node/ cpuss-2-lowf; /delete-node/ mdm-core-lowf; /delete-node/ display-lowf; /delete-node/ gpu-lowf; diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 44596816179f..170560b046d1 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -575,7 +575,7 @@ }; }; - octa-cpu-max-step { + hepta-cpu-max-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; @@ -588,87 +588,95 @@ }; }; - cpu-0-0-step { + cpuss-0-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 9>; + thermal-sensors = <&tsens0 6>; trips { - cpu0_config: cpu0-config { + cpu5_7_config: cpu-5-7-config { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; }; cooling-maps { - cpu0_cdev { - trip = <&cpu0_config>; + cpu5_cdev { + trip = <&cpu5_7_config>; cooling-device = - <&CPU0 THERMAL_MAX_LIMIT + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu7_cdev { + trip = <&cpu5_7_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; }; }; - cpu-0-1-step { + cpuss-1-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 10>; + thermal-sensors = <&tsens0 7>; trips { - cpu1_config: cpu1-config { + cpu4_6_config: cpu-4-6-config { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; }; cooling-maps { - cpu1_cdev { - trip = <&cpu1_config>; + cpu4_cdev { + trip = <&cpu4_6_config>; cooling-device = - <&CPU1 THERMAL_MAX_LIMIT + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu6_cdev { + trip = <&cpu4_6_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; }; }; - cpu-0-2-step { + cpuss-2-step { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 11>; + thermal-sensors = <&tsens0 8>; trips { - cpu2_config: cpu2-config { + silv_cpus_config: silv-cpus-config { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; }; cooling-maps { + cpu0_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu1_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; cpu2_cdev { - trip = <&cpu2_config>; + trip = <&silv_cpus_config>; cooling-device = <&CPU2 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - }; - }; - - cpu-0-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 12>; - trips { - cpu3_config: cpu3-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { cpu3_cdev { - trip = <&cpu3_config>; + trip = <&silv_cpus_config>; cooling-device = <&CPU3 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -680,7 +688,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 6>; + thermal-sensors = <&tsens0 9>; trips { cpu4_config: cpu4-config { temperature = <110000>; @@ -702,7 +710,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 7>; + thermal-sensors = <&tsens0 10>; trips { cpu5_config: cpu5-config { temperature = <110000>; @@ -724,7 +732,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 8>; + thermal-sensors = <&tsens0 11>; trips { cpu6_config: cpu6-config { temperature = <110000>; @@ -746,7 +754,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; + thermal-sensors = <&tsens0 12>; trips { cpu7_config: cpu7-config { temperature = <110000>; @@ -1076,7 +1084,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 5>; + thermal-sensors = <&tsens0 4>; tracks-low; trips { video_trip: video-trip { @@ -1153,7 +1161,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 6>; + thermal-sensors = <&tsens0 9>; tracks-low; trips { cpu4_lowf_trip: cpu4-lowf-trip { @@ -1226,11 +1234,11 @@ }; }; - cpu-0-0-lowf { + cpuss-2-lowf { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 9>; + thermal-sensors = <&tsens0 8>; tracks-low; trips { cpu0_lowf_trip: cpu0-lowf-trip { @@ -1461,7 +1469,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 5>; + thermal-sensors = <&tsens0 15>; tracks-low; trips { gpu_trip: gpu-trip { diff --git a/drivers/thermal/qcom/qti_virtual_sensor.c b/drivers/thermal/qcom/qti_virtual_sensor.c index 937e8aec3e4f..de3e2c87c014 100644 --- a/drivers/thermal/qcom/qti_virtual_sensor.c +++ b/drivers/thermal/qcom/qti_virtual_sensor.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -161,16 +161,15 @@ static const struct virtual_sensor_data qti_virtual_sensors[] = { .logic = VIRT_MAXIMUM, }, { - .virt_zone_name = "octa-cpu-max-step", - .num_sensors = 8, + .virt_zone_name = "hepta-cpu-max-step", + .num_sensors = 7, .sensor_names = {"cpu-1-0-usr", "cpu-1-1-usr", "cpu-1-2-usr", "cpu-1-3-usr", - "cpu-0-0-usr", - "cpu-0-1-usr", - "cpu-0-2-usr", - "cpu-0-3-usr"}, + "cpuss-0-usr", + "cpuss-1-usr", + "cpuss-2-usr"}, .logic = VIRT_MAXIMUM, }, }; -- GitLab From 64a0ea84717282652703047e043bf43f360a77a1 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 16 Jan 2019 15:35:55 +0530 Subject: [PATCH 0937/1286] ARM: dts: msm: Enable GPU thermal zone mitigation for TRINKET Enable high temperature GPU stepwise thermal zone mitigation configuration for TRINKET. Change-Id: I76c9398ae11d42d1f1da55a8e647f530942e7ef5 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 170560b046d1..686da40b1952 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -573,6 +573,13 @@ type = "passive"; }; }; + cooling-maps { + gpu_cdev { + trip = <&gpu_step_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; }; hepta-cpu-max-step { -- GitLab From a4161f9e967b2cea043d092558ee3f0ef65e8652 Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Wed, 16 Jan 2019 16:32:27 +0530 Subject: [PATCH 0938/1286] defconfig: trinket: Enable camera driver support for trinket Changes to add variables in perf defconfig to enable camera driver support for trinket. Change-Id: If398a464c86edf1eef9e4b2e2650c596ddb02f87 Signed-off-by: Abhishek Jain --- .../configs/vendor/trinket-perf_defconfig | 30 +++++++++++++++++-- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a06e1834ce21..8d7ea5eb354f 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -371,7 +371,33 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SPECTRA_CAMERA=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSMB_CAMERA=y +CONFIG_MSMB_CAMERA_DEBUG=y +CONFIG_MSM_CAMERA_SENSOR=y +CONFIG_MSM_CPP=y +CONFIG_MSM_CCI=y +CONFIG_MSM_CSI20_HEADER=y +CONFIG_MSM_CSI22_HEADER=y +CONFIG_MSM_CSI30_HEADER=y +CONFIG_MSM_CSI31_HEADER=y +CONFIG_MSM_CSIPHY=y +CONFIG_MSM_CSID=y +CONFIG_MSM_EEPROM=y +CONFIG_MSM_ISPIF=y +CONFIG_IMX134=y +CONFIG_IMX132=y +CONFIG_OV9724=y +CONFIG_OV5648=y +CONFIG_GC0339=y +CONFIG_OV8825=y +CONFIG_OV8865=y +CONFIG_s5k4e1=y +CONFIG_OV12830=y +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y +CONFIG_MSMB_JPEG=y +CONFIG_MSM_FD=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y @@ -451,8 +477,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y CONFIG_LEDS_QPNP_FLASH_V2=y CONFIG_LEDS_QPNP_HAPTICS=y CONFIG_LEDS_QTI_TRI_LED=y -- GitLab From 74fcf976ee52f131620aa9eb05a4c123762793a2 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 9 Jan 2019 11:45:20 +0530 Subject: [PATCH 0939/1286] power: smb5-lib: Fix wake lock acquisition Currently, pm_stay_awake and pm_relax are called directly from the alarm callback routines since we are in atomic context. However, pm_stay_awake/pm_relax are not ref counted which leaves a possibility of the wakelock being cleared by any other thread of this module. Fix this by explicitly voting to awake votable, to ensure pm_relax isn't called before the complete execution of the routine. Change-Id: I3b28315648261eacfa3247d8fcb76673d506629b Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/smb5-lib.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index 36a4c74f347a..bac6c41a219b 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -5795,6 +5795,12 @@ static void smblib_moisture_protection_work(struct work_struct *work) bool usb_plugged_in; u8 stat; + /* + * Hold awake votable to prevent pm_relax being called prior to + * completion of this work. + */ + vote(chg->awake_votable, MOISTURE_VOTER, true, 0); + /* * Disable 1% duty cycle on CC_ID pin and enable uUSB factory mode * detection to track any change on RID, as interrupts are disable. @@ -5859,7 +5865,7 @@ static void smblib_moisture_protection_work(struct work_struct *work) } out: - pm_relax(chg->dev); + vote(chg->awake_votable, MOISTURE_VOTER, false, 0); } static enum alarmtimer_restart moisture_protection_alarm_cb(struct alarm *alarm, -- GitLab From a6bde3f20d250bd72d4e002c9ea567dbd82d1faa Mon Sep 17 00:00:00 2001 From: "Jennifer L. Zenner" Date: Thu, 6 Dec 2018 16:39:21 -0500 Subject: [PATCH 0940/1286] msm: ipa3: Add support for IPA/GSI register dump/collection Add functionality to the IPA/GSI driver in support of a register dump/collection feature. Register's values are collected upon system crash. Change-Id: I6ccc5a801fd2cf9cd8e92ad4e2c9244a88fae393 CRs-Fixed: 2342813 Acked-by: Perry Randise Signed-off-by: Jennifer L. Zenner --- drivers/platform/msm/Kconfig | 28 + drivers/platform/msm/gsi/gsi.c | 3 +- drivers/platform/msm/ipa/ipa_v3/Makefile | 4 + .../msm/ipa/ipa_v3/dump/ipa_reg_dump.c | 1429 ++ .../msm/ipa/ipa_v3/dump/ipa_reg_dump.h | 1284 ++ .../msm/ipa/ipa_v3/dump/sm8150/gsi_hwio.h | 2313 +++ .../msm/ipa/ipa_v3/dump/sm8150/gsi_hwio_def.h | 517 + .../msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio.h | 16806 ++++++++++++++++ .../ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio_def.h | 29 + .../ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h | 472 + .../msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h | 10355 ++++++++++ .../msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h | 2817 +++ .../ipa/ipa_v3/dump/sm8150/ipa_pkt_cntxt.h | 190 + drivers/platform/msm/ipa/ipa_v3/ipa.c | 65 +- .../msm/ipa/ipa_v3/ipa_dt_replacement.c | 14 +- drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 16 + 16 files changed, 36339 insertions(+), 3 deletions(-) create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_pkt_cntxt.h diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig index 5fd32155da48..030115a384ca 100644 --- a/drivers/platform/msm/Kconfig +++ b/drivers/platform/msm/Kconfig @@ -212,4 +212,32 @@ config IPA_EMULATION help This option is used only when building the X86 version of the IPA/GSI driver. Never set this when building for ARM. + +config IPA3_REGDUMP + bool "Dump or collect IPA/GSI register values on Linux crash" + depends on IPA3 + help + This option is to be used when the saving of IPA/GSI + register state is desired upon system crash. + +choice + prompt "Platform whose registers are to be dumped/collected" + depends on IPA3_REGDUMP + +config IPA3_REGDUMP_SM8150 + bool "The sm8150 platform" + depends on IPA3_REGDUMP + depends on ARCH_SM8150 + help + The sm8150 platform's registers will be dumped/collected. + +endchoice + +config IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS + int "The number of extra endp registers for remaining pipes" + depends on IPA3_REGDUMP + default 0 + help + If the platform has extra endpoint registers for remaining + pipes, please express how many here. endmenu diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index ad6a69cb6c29..2e0b1228039e 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2503,6 +2503,7 @@ int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, mutex_unlock(&ctx->mlock); return GSI_STATUS_SUCCESS; } +EXPORT_SYMBOL(gsi_write_channel_scratch3_reg); static void __gsi_read_channel_scratch(unsigned long chan_hdl, union __packed gsi_channel_scratch * val) diff --git a/drivers/platform/msm/ipa/ipa_v3/Makefile b/drivers/platform/msm/ipa/ipa_v3/Makefile index 453b8a4e279b..2587e0cc9032 100644 --- a/drivers/platform/msm/ipa/ipa_v3/Makefile +++ b/drivers/platform/msm/ipa/ipa_v3/Makefile @@ -11,3 +11,7 @@ ipat-$(CONFIG_IPA_EMULATION) += ipa_dt_replacement.o obj-$(CONFIG_RMNET_IPA3) += rmnet_ipa.o ipa_qmi_service_v01.o ipa_qmi_service.o rmnet_ipa_fd_ioctl.o obj-$(CONFIG_IPA3_MHI_PROXY) += ipa_mhi_proxy.o + +ipat-$(CONFIG_IPA3_REGDUMP) += dump/ipa_reg_dump.o + +ccflags-$(CONFIG_IPA3_REGDUMP_SM8150) += -Idrivers/platform/msm/ipa/ipa_v3/dump/sm8150 diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c new file mode 100644 index 000000000000..aaedc8c6eedd --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c @@ -0,0 +1,1429 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipa_reg_dump.h" + +/* Total size required for test bus */ +#define IPA_MEM_OVERLAY_SIZE 0x66000 + +/* + * The following structure contains a hierarchy of structures that + * ultimately leads to a series of leafs. The leafs are structures + * containing detailed, bit level, register definitions. + */ +static struct regs_save_hierarchy_s ipa_reg_save; + +static unsigned int ipa_testbus_mem[IPA_MEM_OVERLAY_SIZE]; + +/* + * The following data structure contains a list of the registers + * (whose data are to be copied) and the locations (within + * ipa_reg_save above) into which the registers' values need to be + * copied. + */ +static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { + /* + * ===================================================================== + * IPA register definitions begin here... + * ===================================================================== + */ + + /* IPA General Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_STATE, + ipa.gen, + ipa_state), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_CONF, + ipa.gen, + ipa_gsi_conf), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_RX_ACTIVE, + ipa.gen, + ipa_state_rx_active), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_WRAPPER, + ipa.gen, + ipa_state_tx_wrapper), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0, + ipa.gen, + ipa_state_tx0), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1, + ipa.gen, + ipa_state_tx1), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_AGGR_ACTIVE, + ipa.gen, + ipa_state_aggr_active), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER, + ipa.gen, + ipa_state_dfetcher), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK, + ipa.gen, + ipa_state_fetcher_mask), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS, + ipa.gen, + ipa_state_gsi_aos), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_IF, + ipa.gen, + ipa_state_gsi_if), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_SKIP, + ipa.gen, + ipa_state_gsi_skip), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_TLV, + ipa.gen, + ipa_state_gsi_tlv), + GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER, + ipa.gen, + ipa_tag_timer), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_LSB, + ipa.gen, + ipa_dpl_timer_lsb), + GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_MSB, + ipa.gen, + ipa_dpl_timer_msb), + GEN_SRC_DST_ADDR_MAP(IPA_PROC_IPH_CFG, + ipa.gen, + ipa_proc_iph_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_ROUTE, + ipa.gen, + ipa_route), + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_1, + ipa.gen, + ipa_spare_reg_1), + GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_2, + ipa.gen, + ipa_spare_reg_2), + GEN_SRC_DST_ADDR_MAP(IPA_LOG, + ipa.gen, + ipa_log), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_CFG, + ipa.gen, + ipa_log_buf_status_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_ADDR, + ipa.gen, + ipa_log_buf_status_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_WRITE_PTR, + ipa.gen, + ipa_log_buf_status_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_RAM_PTR, + ipa.gen, + ipa_log_buf_status_ram_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_CFG, + ipa.gen, + ipa_log_buf_hw_cmd_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_ADDR, + ipa.gen, + ipa_log_buf_hw_cmd_addr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_WRITE_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_write_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR, + ipa.gen, + ipa_log_buf_hw_cmd_ram_ptr), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION, + ipa.gen, + ipa_comp_hw_version), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_EN, + ipa.gen, + ipa_filt_rout_hash_en), + GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_FLUSH, + ipa.gen, + ipa_filt_rout_hash_flush), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER, + ipa.gen, + ipa_state_fetcher), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv4_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_FILTER_INIT_VALUES, + ipa.gen, + ipa_ipv6_filter_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV4_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv4_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_IPV6_ROUTE_INIT_VALUES, + ipa.gen, + ipa_ipv6_route_init_values), + GEN_SRC_DST_ADDR_MAP(IPA_BCR, + ipa.gen, + ipa_bcr), + GEN_SRC_DST_ADDR_MAP(IPA_BAM_ACTIVATED_PORTS, + ipa.gen, + ipa_bam_activated_ports), + GEN_SRC_DST_ADDR_MAP(IPA_TX_COMMANDER_CMDQ_STATUS, + ipa.gen, + ipa_tx_commander_cmdq_status), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_EN, + ipa.gen, + ipa_log_buf_hw_snif_el_en), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL, + ipa.gen, + ipa_log_buf_hw_snif_el_wr_n_rd_sel), + GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX, + ipa.gen, + ipa_log_buf_hw_snif_el_cli_mux), + GEN_SRC_DST_ADDR_MAP(IPA_STATE_ACL, + ipa.gen, + ipa_state_acl), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_SYS_PKT_PROC_CNTXT_BASE_MSB, + ipa.gen, + ipa_sys_pkt_proc_cntxt_base_msb), + GEN_SRC_DST_ADDR_MAP(IPA_LOCAL_PKT_PROC_CNTXT_BASE, + ipa.gen, + ipa_local_pkt_proc_cntxt_base), + GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG, + ipa.gen, + ipa_rsrc_grp_cfg), + GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG, + ipa.gen, + ipa_comp_cfg), + + /* Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, + ipa.dbg, + ipa_debug_data), + GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS, + ipa.dbg, + ipa_step_mode_status), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_CMD, ipa.dbg, + ipa_rx_splt_cmdq_0_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_DATA_RD_0, ipa.dbg, + ipa_rx_splt_cmdq_0_data_rd_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_DATA_RD_1, ipa.dbg, + ipa_rx_splt_cmdq_0_data_rd_1), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_DATA_RD_2, ipa.dbg, + ipa_rx_splt_cmdq_0_data_rd_2), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_DATA_RD_3, ipa.dbg, + ipa_rx_splt_cmdq_0_data_rd_3), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_0_STATUS, ipa.dbg, + ipa_rx_splt_cmdq_0_status), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_CMD, ipa.dbg, + ipa_rx_splt_cmdq_1_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_DATA_RD_0, ipa.dbg, + ipa_rx_splt_cmdq_1_data_rd_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_DATA_RD_1, ipa.dbg, + ipa_rx_splt_cmdq_1_data_rd_1), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_DATA_RD_2, ipa.dbg, + ipa_rx_splt_cmdq_1_data_rd_2), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_DATA_RD_3, ipa.dbg, + ipa_rx_splt_cmdq_1_data_rd_3), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_1_STATUS, ipa.dbg, + ipa_rx_splt_cmdq_1_status), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_CMD, ipa.dbg, + ipa_rx_splt_cmdq_2_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_DATA_RD_0, ipa.dbg, + ipa_rx_splt_cmdq_2_data_rd_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_DATA_RD_1, ipa.dbg, + ipa_rx_splt_cmdq_2_data_rd_1), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_DATA_RD_2, ipa.dbg, + ipa_rx_splt_cmdq_2_data_rd_2), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_DATA_RD_3, ipa.dbg, + ipa_rx_splt_cmdq_2_data_rd_3), + GEN_SRC_DST_ADDR_MAP(IPA_RX_SPLT_CMDQ_2_STATUS, ipa.dbg, + ipa_rx_splt_cmdq_2_status), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD, + ipa.dbg, + ipa_rx_hps_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_rx_hps_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_min_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0, + ipa.dbg, + ipa_rx_hps_clients_max_depth_0), + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_CMD, + ipa.dbg, + ipa_hps_dps_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_hps_dps_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_CMD, + ipa.dbg, + ipa_dps_tx_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_dps_tx_cmdq_status_empty), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD, + ipa.dbg, + ipa_ackmngr_cmdq_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY, + ipa.dbg, + ipa_ackmngr_cmdq_status_empty), + + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_STTS_EE_n, + ipa_irq_stts_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_IRQ_EN_EE_n, + ipa_irq_en_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ADDR_EE_n, + ipa_fec_addr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_FEC_ATTR_EE_n, + ipa_fec_attr_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SNOC_FEC_EE_n, + ipa_snoc_fec_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_HOLB_DROP_IRQ_INFO_EE_n, + ipa_holb_drop_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_INFO_EE_n, + ipa_suspend_irq_info_ee_n), + IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_EN_EE_n, + ipa_suspend_irq_en_ee_n), + + /* Pipe Endp Registers */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG2_n, + ipa_endp_gsi_cfg2_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), + + /* Source Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n, + ipa_src_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, + ipa_src_rsrc_grp_23_rsrc_type_n), + + /* Destination Resource Group Config Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, + ipa_dst_rsrc_grp_01_rsrc_type_n), + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, + ipa_dst_rsrc_grp_23_rsrc_type_n), + + /* Source Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP + (IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n), + + /* Destination Resource Group Count Registers */ + IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP + (IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n), + + /* + * ===================================================================== + * GSI register definitions begin here... + * ===================================================================== + */ + + /* GSI General Registers */ + GEN_SRC_DST_ADDR_MAP(GSI_CFG, + gsi.gen, + gsi_cfg), + GEN_SRC_DST_ADDR_MAP(GSI_REE_CFG, + gsi.gen, + gsi_ree_cfg), + + /* GSI Debug Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_BUSY_REG, + gsi.debug, + ipa_gsi_top_gsi_debug_busy_reg), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_event_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_timer_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING, + gsi.debug, + ipa_gsi_top_gsi_debug_rd_wr_pending), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_from_sw), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_SW_STALL, + gsi.debug, + ipa_gsi_top_gsi_debug_sw_stall), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG, + gsi.debug, + ipa_gsi_top_gsi_debug_pc_for_debug), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID, + gsi.debug, + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id), + + /* GSI IRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ev_db), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_new_re), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_ch_empty), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_event_gen_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_timer_expired), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_write_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_read_eng_comp), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_uc_gp_int), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED, + gsi.debug.gsi_iram_ptrs, + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped), + + /* GSI SHRAM pointers Registers */ + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr), + GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR, + gsi.debug.gsi_shram_ptrs, + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr), + + /* + * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is + * because the following registers are not scaler, rather + * they are register arrays... + */ + + /* GSI General EE Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(GSI_MANAGER_EE_QOS_n, + gsi_manager_ee_qos_n), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_GSI_STATUS, + ee_n_gsi_status), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ, + ee_n_cntxt_type_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ_MSK, + ee_n_cntxt_type_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ, + ee_n_cntxt_src_gsi_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ, + ee_n_cntxt_src_ev_ch_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK, + ee_n_cntxt_src_gsi_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK, + ee_n_cntxt_src_ev_ch_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ, + ee_n_cntxt_src_ieob_irq), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ_MSK, + ee_n_cntxt_src_ieob_irq_msk), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GSI_IRQ_STTS, + ee_n_cntxt_gsi_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GLOB_IRQ_STTS, + ee_n_cntxt_glob_irq_stts), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_ERROR_LOG, + ee_n_error_log), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_0, + ee_n_cntxt_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SCRATCH_1, + ee_n_cntxt_scratch_1), + + /* GSI Channel Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_0, + ee_n_gsi_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_1, + ee_n_gsi_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_2, + ee_n_gsi_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_3, + ee_n_gsi_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_4, + ee_n_gsi_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_5, + ee_n_gsi_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_6, + ee_n_gsi_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_CNTXT_7, + ee_n_gsi_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_READ_PTR, + ee_n_gsi_ch_k_re_fetch_read_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR, + ee_n_gsi_ch_k_re_fetch_write_ptr), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_QOS, + ee_n_gsi_ch_k_qos), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_0, + ee_n_gsi_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_1, + ee_n_gsi_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_2, + ee_n_gsi_ch_k_scratch_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(EE_n_GSI_CH_k_SCRATCH_3, + ee_n_gsi_ch_k_scratch_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(GSI_DEBUG_EE_n_CH_k_VP_TABLE, + gsi_debug_ee_n_ch_k_vp_table), + + IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(GSI_DEBUG_QSB_LOG_LAST_MISC_IDn, + qsb_log_last_misc), + + /* GSI Channel Event Context Registers */ + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_0, + ee_n_ev_ch_k_cntxt_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_1, + ee_n_ev_ch_k_cntxt_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_2, + ee_n_ev_ch_k_cntxt_2), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_3, + ee_n_ev_ch_k_cntxt_3), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_4, + ee_n_ev_ch_k_cntxt_4), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_5, + ee_n_ev_ch_k_cntxt_5), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_6, + ee_n_ev_ch_k_cntxt_6), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_7, + ee_n_ev_ch_k_cntxt_7), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_8, + ee_n_ev_ch_k_cntxt_8), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_9, + ee_n_ev_ch_k_cntxt_9), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_10, + ee_n_ev_ch_k_cntxt_10), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_11, + ee_n_ev_ch_k_cntxt_11), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_12, + ee_n_ev_ch_k_cntxt_12), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_CNTXT_13, + ee_n_ev_ch_k_cntxt_13), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_0, + ee_n_ev_ch_k_scratch_0), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(EE_n_EV_CH_k_SCRATCH_1, + ee_n_ev_ch_k_scratch_1), + IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(GSI_DEBUG_EE_n_EV_k_VP_TABLE, + gsi_debug_ee_n_ev_k_vp_table), + +#if defined(CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS) && \ + CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS > 0 + /* Endp Registers for remaining pipes */ + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_n, + ipa_endp_init_ctrl_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CTRL_SCND_n, + ipa_endp_init_ctrl_scnd_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_CFG_n, + ipa_endp_init_cfg_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_NAT_n, + ipa_endp_init_nat_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_n, + ipa_endp_init_hdr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_EXT_n, + ipa_endp_init_hdr_ext_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_INIT_HDR_METADATA_MASK_n, + ipa_endp_init_hdr_metadata_mask_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HDR_METADATA_n, + ipa_endp_init_hdr_metadata_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_MODE_n, + ipa_endp_init_mode_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_AGGR_n, + ipa_endp_init_aggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_EN_n, + ipa_endp_init_hol_block_en_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_HOL_BLOCK_TIMER_n, + ipa_endp_init_hol_block_timer_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_DEAGGR_n, + ipa_endp_init_deaggr_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_STATUS_n, + ipa_endp_status_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_RSRC_GRP_n, + ipa_endp_init_rsrc_grp_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_INIT_SEQ_n, + ipa_endp_init_seq_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_TLV_n, + ipa_endp_gsi_cfg_tlv_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG_AOS_n, + ipa_endp_gsi_cfg_aos_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG1_n, + ipa_endp_gsi_cfg1_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(IPA_ENDP_GSI_CFG2_n, + ipa_endp_gsi_cfg2_n), + IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA + (IPA_ENDP_FILTER_ROUTER_HSH_CFG_n, + ipa_endp_filter_router_hsh_cfg_n), +#endif +}; + +/* IPA uC PER registers save Cfg array */ +static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = { + /* HWP registers */ + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_SYS_ADDR, + ipa.hwp, + ipa_uc_qmb_sys_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LOCAL_ADDR, + ipa.hwp, + ipa_uc_qmb_local_addr), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_LENGTH, + ipa.hwp, + ipa_uc_qmb_length), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_TRIGGER, + ipa.hwp, + ipa_uc_qmb_trigger), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_PENDING_TID, + ipa.hwp, + ipa_uc_qmb_pending_tid), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_rd_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK, + ipa.hwp, + ipa_uc_qmb_completed_wr_fifo_peek), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_MISC, + ipa.hwp, + ipa_uc_qmb_misc), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_STATUS, + ipa.hwp, + ipa_uc_qmb_status), + GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_BUS_ATTRIB, + ipa.hwp, + ipa_uc_qmb_bus_attrib), +}; + +static void ipa_hal_save_regs_save_ipa_testbus(void); +static void ipa_reg_save_gsi_fifo_status(void); +static void ipa_reg_save_rsrc_cnts(void); +static void ipa_hal_save_regs_ipa_cmdq(void); +static void ipa_hal_save_regs_rsrc_db(void); +static void ipa_reg_save_anomaly_check(void); + +/* + * FUNCTION: ipa_save_registers + * + * Saves all the IPA register values which are configured + * + * @return + * None + */ +void ipa_save_registers(void) +{ + u32 i = 0; + /* Fetch the number of registers configured to be saved */ + u32 num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + u32 num_uc_per_regs = ARRAY_SIZE(ipa_uc_regs_to_save_array); + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u ipa_rsrc_mngr_db_cfg; + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u + ipa_rsrc_mngr_db_rsrc_read; + + if (ipa3_ctx->do_register_collection_on_crash == false) + return; + + IPAERR("Commencing\n"); + + /* + * Remove the GSI FIFO and the endp registers for extra pipes for + * now. These would be saved later + */ + num_regs -= (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + memset(&ipa_rsrc_mngr_db_cfg, 0, sizeof(ipa_rsrc_mngr_db_cfg)); + memset(&ipa_rsrc_mngr_db_rsrc_read, 0, + sizeof(ipa_rsrc_mngr_db_rsrc_read)); + + /* Now save all the configured registers */ + for (i = 0; i < num_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[i].dst_addr) = + in_dword(ipa_regs_to_save_array[i].src_addr); + } + + IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE(); + + /* Now save the per endp registers for the remaining pipes */ + for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) { + /* Copy reg value to our data struct */ + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = + in_dword(ipa_regs_to_save_array[num_regs + i].src_addr); + } + + IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE(); + + num_regs += (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + /* Saving GSI FIFO Status registers */ + ipa_reg_save_gsi_fifo_status(); + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash == true) { + /* Save all the uC PER configured registers */ + for (i = 0; i < num_uc_per_regs; i++) { + /* Copy reg value to our data struct */ + *(ipa_uc_regs_to_save_array[i].dst_addr) = + in_dword(ipa_uc_regs_to_save_array[i].src_addr); + } + + /* Saving CMD Queue registers */ + ipa_hal_save_regs_ipa_cmdq(); + + /* Collecting resource DB information */ + ipa_hal_save_regs_rsrc_db(); + + /* Save IPA testbus */ + if (ipa3_ctx->do_testbus_collection_on_crash == true) + ipa_hal_save_regs_save_ipa_testbus(); + } + + /* GSI test bus and QSB log */ + for (i = 0; + i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); + i++) { + /* Write test bus selector */ + HWIO_GSI_TEST_BUS_SEL_OUT + (ipa_reg_save_gsi_ch_test_bus_selector_array[i]); + ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ + i].gsi_testbus_reg = + (u32)HWIO_GSI_TEST_BUS_REG_IN; + } + + ipa_reg_save_rsrc_cnts(); + + for (i = 0; i < HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_mcs_regs.mcs_reg[i].rf_reg = + IPA_READ_1xVECTOR_REG(GSI_DEBUG_SW_RF_n_READ, i); + + for (i = 0; i < HWIO_GSI_DEBUG_COUNTERn_MAXn + 1; i++) + ipa_reg_save.gsi.debug.gsi_cnt_regs.cnt[i].counter_value = + (u16)IPA_READ_1xVECTOR_REG(GSI_DEBUG_COUNTERn, i); + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7; i++) { + u32 phys_ch_idx = + ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_debug_ee_n_ch_k_vp_table.phy_ch; + u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.a7[ + i].gsi_debug_ee_n_ch_k_vp_table.valid) + continue; + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch4.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 2); + ipa_reg_save.gsi.ch_cntxt.a7[ + i].mcs_channel_scratch.scratch5.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1); + } + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) { + u32 phys_ch_idx = + ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_debug_ee_n_ch_k_vp_table.phy_ch; + u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.q6[ + i].gsi_debug_ee_n_ch_k_vp_table.valid) + continue; + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch4.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 2); + ipa_reg_save.gsi.ch_cntxt.q6[ + i].mcs_channel_scratch.scratch5.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1); + } + + for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) { + u32 phys_ch_idx = + ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_debug_ee_n_ch_k_vp_table.phy_ch; + u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM; + + if (!ipa_reg_save.gsi.ch_cntxt.uc[ + i].gsi_debug_ee_n_ch_k_vp_table.valid) + continue; + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch4.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 2); + ipa_reg_save.gsi.ch_cntxt.uc[ + i].mcs_channel_scratch.scratch5.shram = + IPA_READ_1xVECTOR_REG( + GSI_SHRAM_n, + n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1); + } + + /* + * On targets that support SSR, we generally want to disable + * the following reg save functionality as it may cause stalls + * in IPA after the SSR. + * + * To override this, set do_non_tn_collection_on_crash to + * true, via dtsi, and the collection will be done. + */ + if (ipa3_ctx->do_non_tn_collection_on_crash == true) { + /* Copy Pkt context directly from IPA_CTX_ID register space */ + memcpy((void *)ipa_reg_save.pkt_ctntx, + (void *)((u8 *) ipa3_ctx->reg_collection_base + + GEN_2xVECTOR_REG_OFST( + IPA_CTX_ID_m_CTX_NUM_n, 0, 0)), + sizeof(ipa_reg_save.pkt_ctntx)); + + ipa_rsrc_mngr_db_cfg.value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_CFG); + + ipa_rsrc_mngr_db_cfg.def.rsrc_type_sel = 0; + IPA_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + + for (i = 0; i < IPA_HW_PKT_CTNTX_MAX; i++) { + ipa_rsrc_mngr_db_cfg.def.rsrc_id_sel = i; + IPA_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + + ipa_rsrc_mngr_db_rsrc_read.value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_RSRC_READ); + + if (ipa_rsrc_mngr_db_rsrc_read.def.rsrc_occupied == + true) { + ipa_reg_save.pkt_ctntx_active[i] = true; + ipa_reg_save.pkt_cntxt_state[i] = + (enum ipa_hw_pkt_cntxt_state_e) + ipa_reg_save.pkt_ctntx[i].state; + } + } + } + + ipa_reg_save_anomaly_check(); + + IPAERR("Completed\n"); +} + +/* + * FUNCTION: ipa_reg_save_gsi_fifo_status + * + * This function saves the GSI FIFO Status registers for all endpoints + * + * @param + * + * @return + */ +static void ipa_reg_save_gsi_fifo_status(void) +{ + union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u gsi_fifo_status_ctrl; + u8 i; + + memset(&gsi_fifo_status_ctrl, 0, sizeof(gsi_fifo_status_ctrl)); + + for (i = 0; i < IPA_HW_PIPE_ID_MAX; i++) { + gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_en = 1; + gsi_fifo_status_ctrl.def.ipa_gsi_fifo_status_port_sel = i; + + IPA_WRITE_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL, + gsi_fifo_status_ctrl.value); + + ipa_reg_save.gsi_fifo_status[i].gsi_fifo_status_ctrl.value = + IPA_READ_SCALER_REG(IPA_GSI_FIFO_STATUS_CTRL); + ipa_reg_save.gsi_fifo_status[i].gsi_tlv_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_TLV_FIFO_STATUS); + ipa_reg_save.gsi_fifo_status[i].gsi_tlv_pub_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_TLV_PUB_FIFO_STATUS); + ipa_reg_save.gsi_fifo_status[i].gsi_aos_fifo_status.value = + IPA_READ_SCALER_REG(IPA_GSI_AOS_FIFO_STATUS); + } +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts + * + * This function saves the resource counts for all PCIE and DDR + * resource groups. + * + * @param + * @return + */ +static void ipa_reg_save_rsrc_cnts(void) +{ + union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u + src_0123_rsrc_cnt; + union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u + dst_0123_rsrc_cnt; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 2); + + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 3); + + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + src_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 4); + + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + src_0123_rsrc_cnt.def.src_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 0); + + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; + + dst_0123_rsrc_cnt.value = + IPA_READ_1xVECTOR_REG(IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, 1); + + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_0_cnt; + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + dst_0123_rsrc_cnt.def.dst_rsrc_grp_1_cnt; +} + +/* + * FUNCTION: ipa_reg_save_rsrc_cnts_test_bus + * + * This function saves the resource counts for all PCIE and DDR + * resource groups collected from test bus. + * + * @param + * + * @return + */ +void ipa_reg_save_rsrc_cnts_test_bus(void) +{ + int32_t rsrc_type = 0; + + ipa_reg_save.rsrc_cnts.pcie.resource_group = IPA_HW_PCIE_SRC_RSRP_GRP; + ipa_reg_save.rsrc_cnts.ddr.resource_group = IPA_HW_DDR_SRC_RSRP_GRP; + + rsrc_type = 0; + ipa_reg_save.rsrc_cnts.pcie.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.pkt_cntxt = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 1; + ipa_reg_save.rsrc_cnts.pcie.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.descriptor_list = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 2; + ipa_reg_save.rsrc_cnts.pcie.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.data_descriptor_buffer = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 3; + ipa_reg_save.rsrc_cnts.pcie.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.hps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 4; + ipa_reg_save.rsrc_cnts.pcie.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_SRC_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.src.reserved_acks = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_SRC_RSRP_GRP); + + rsrc_type = 5; + ipa_reg_save.rsrc_cnts.pcie.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.reserved_sectors = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); + + rsrc_type = 6; + ipa_reg_save.rsrc_cnts.pcie.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_PCIE_DEST_RSRP_GRP); + + ipa_reg_save.rsrc_cnts.ddr.dst.dps_dmars = + IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, + IPA_HW_DDR_DEST_RSRP_GRP); +} + +/* + * FUNCTION: ipa_hal_save_regs_ipa_cmdq + * + * This function saves the various IPA CMDQ registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_ipa_cmdq(void) +{ + int32_t i; + union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u rx_hps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u hps_dps_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u dps_tx_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u + prod_ackmngr_cmdq_cmd = { { 0 } }; + union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u ntf_tx_cmdq_cmd = { { 0 } }; + + /* Save RX_HPS CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS; i++) { + rx_hps_cmdq_cmd.def.rd_req = 0; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_COUNT); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_STATUS); + rx_hps_cmdq_cmd.def.rd_req = 1; + rx_hps_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_RX_HPS_CMDQ_CMD, + rx_hps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_0); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_1_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_1); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_2_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_2); + ipa_reg_save.ipa.dbg.ipa_rx_hps_cmdq_data_rd_3_arr[i].value = + IPA_READ_SCALER_REG(IPA_RX_HPS_CMDQ_DATA_RD_3); + } + + /* Save HPS_DPS CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + hps_dps_cmdq_cmd.def.rd_req = 0; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_COUNT); + + hps_dps_cmdq_cmd.def.rd_req = 1; + hps_dps_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_HPS_DPS_CMDQ_CMD, + hps_dps_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_hps_dps_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_HPS_DPS_CMDQ_DATA_RD_0); + } + + /* Save DPS_TX CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 0; + IPA_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_COUNT); + + dps_tx_cmdq_cmd.def.cmd_client = i; + dps_tx_cmdq_cmd.def.rd_req = 1; + IPA_WRITE_SCALER_REG(IPA_DPS_TX_CMDQ_CMD, + dps_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_dps_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_DPS_TX_CMDQ_DATA_RD_0); + } + + /* Save ACKMNGR CMDQ */ + for (i = 0; i < IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS; i++) { + ackmngr_cmdq_cmd.def.rd_req = 0; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_COUNT); + + ackmngr_cmdq_cmd.def.rd_req = 1; + ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_ACKMNGR_CMDQ_CMD, + ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ackmngr_cmdq_data_rd_arr[i].value = + IPA_READ_SCALER_REG(IPA_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save PROD ACKMNGR CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + prod_ackmngr_cmdq_cmd.def.rd_req = 0; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_status_arr[i].value + = IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_COUNT); + prod_ackmngr_cmdq_cmd.def.rd_req = 1; + prod_ackmngr_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_CMD, + prod_ackmngr_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_prod_ackmngr_cmdq_data_rd_arr[ + i].value = + IPA_READ_SCALER_REG(IPA_PROD_ACKMNGR_CMDQ_DATA_RD); + } + + /* Save NTF_TX CMDQ */ + for (i = 0; i < IPA_TESTBUS_SEL_EP_MAX + 1; i++) { + ntf_tx_cmdq_cmd.def.rd_req = 0; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_status_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_STATUS); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_count_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_COUNT); + ntf_tx_cmdq_cmd.def.rd_req = 1; + ntf_tx_cmdq_cmd.def.cmd_client = i; + IPA_WRITE_SCALER_REG(IPA_NTF_TX_CMDQ_CMD, + ntf_tx_cmdq_cmd.value); + ipa_reg_save.ipa.dbg.ipa_ntf_tx_cmdq_data_rd_0_arr[i].value = + IPA_READ_SCALER_REG(IPA_NTF_TX_CMDQ_DATA_RD_0); + } +} + +/* + * FUNCTION: ipa_hal_save_regs_save_ipa_testbus + * + * This function saves the IPA testbus + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_save_ipa_testbus(void) +{ + int32_t sel_internal, sel_external, sel_ep, sel_grp; + union ipa_hwio_def_ipa_debug_data_sel_u debug_data_sel = { { 0 } }; + union ipa_hwio_def_ipa_testbus_sel_u testbus_sel = { { 0 } }; + + if (ipa_reg_save.ipa.testbus == NULL) { + /* + * Test-bus structure not allocated - exit test-bus + * collection + */ + IPADBG("ipa_reg_save.ipa.testbus was not allocated\n"); + return; + } + + testbus_sel.def.pipe_select = 0xF; + testbus_sel.def.external_block_select = IPA_DEBUG_TESTBUS_DEF_EXTERNAL; + testbus_sel.def.internal_block_select = IPA_DEBUG_TESTBUS_DEF_INTERNAL; + + IPA_WRITE_SCALER_REG(IPA_TESTBUS_SEL, testbus_sel.value); + + /* Get Global test bus values */ + for (sel_external = 0; + sel_external <= IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + for (sel_internal = 0; + sel_internal <= IPA_TESTBUS_SEL_INTERNAL_MAX; + sel_internal++) { + debug_data_sel.def.pipe_select = 0; + debug_data_sel.def.external_block_select = sel_external; + debug_data_sel.def.internal_block_select = sel_internal; + IPA_WRITE_SCALER_REG(IPA_DEBUG_DATA_SEL, + debug_data_sel.value); + ipa_reg_save.ipa.testbus->global.global[sel_internal] + [sel_external].testbus_sel.value = + debug_data_sel.value; + ipa_reg_save.ipa.testbus->global.global[sel_internal] + [sel_external].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } + + /* Collect per EP test bus */ + for (sel_ep = 0; sel_ep <= IPA_TESTBUS_SEL_EP_MAX; sel_ep++) { + for (sel_external = 0; + sel_external <= IPA_TESTBUS_SEL_EXTERNAL_MAX; + sel_external++) { + for (sel_internal = 0; + sel_internal <= IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; + sel_internal++) { + debug_data_sel.def.pipe_select = sel_ep; + debug_data_sel.def.external_block_select = + sel_external; + debug_data_sel.def.internal_block_select = + sel_internal; + IPA_WRITE_SCALER_REG(IPA_DEBUG_DATA_SEL, + debug_data_sel.value); + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep + [sel_internal] + [sel_external].testbus_sel.value = + debug_data_sel.value; + ipa_reg_save.ipa.testbus->ep[sel_ep].entry_ep + [sel_internal] + [sel_external].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } + } + + /* Collect per EP RSRC count */ + for (sel_ep = 0; sel_ep < IPA_DEBUG_TESTBUS_RSRC_NUM_EP; sel_ep++) { + for (sel_grp = 0; + sel_grp < IPA_DEBUG_TESTBUS_RSRC_NUM_GRP; + sel_grp++) { + testbus_sel.def.pipe_select = sel_ep; + testbus_sel.def.external_block_select = + IPA_DEBUG_TESTBUS_DEF_EXTERNAL; + testbus_sel.def.internal_block_select = + IPA_DEBUG_TESTBUS_DEF_INTERNAL; + + debug_data_sel.def.pipe_select = sel_grp; + debug_data_sel.def.external_block_select = + IPA_DEBUG_TESTBUS_DEF_EXTERNAL; + debug_data_sel.def.internal_block_select = + IPA_DEBUG_TESTBUS_DEF_INTERNAL; + + IPA_WRITE_SCALER_REG(IPA_TESTBUS_SEL, + testbus_sel.value); + IPA_WRITE_SCALER_REG(IPA_DEBUG_DATA_SEL, + debug_data_sel.value); + ipa_reg_save.ipa.testbus->ep_rsrc[ + sel_ep].entry_ep[sel_grp].testbus_sel.value = + debug_data_sel.value; + ipa_reg_save.ipa.testbus->ep_rsrc[sel_ep].entry_ep[ + sel_grp].testbus_data.value = + IPA_READ_SCALER_REG(IPA_DEBUG_DATA); + } + } +} + +/* + * FUNCTION: ipa_reg_save_init + * + * This function initializes and memsets the register save struct. + * + * @param + * + * @return + */ +int ipa_reg_save_init(u8 value) +{ + u32 i, num_regs = ARRAY_SIZE(ipa_regs_to_save_array); + + if (ipa3_ctx->do_register_collection_on_crash == false) + return 0; + + memset(&ipa_reg_save, value, sizeof(ipa_reg_save)); + + ipa_reg_save.ipa.testbus = NULL; + + if (ipa3_ctx->do_testbus_collection_on_crash == true) { + ipa_reg_save.ipa.testbus = + (struct ipa_reg_save_ipa_testbus_s *) ipa_testbus_mem; + } + + /* setup access for register collection/dump on crash */ + IPADBG("Mapping 0x%x bytes starting at 0x%x\n", + ipa3_ctx->entire_ipa_block_size, + ipa3_ctx->ipa_wrapper_base); + + ipa3_ctx->reg_collection_base = + ioremap(ipa3_ctx->ipa_wrapper_base, + ipa3_ctx->entire_ipa_block_size); + + if (!ipa3_ctx->reg_collection_base) { + IPAERR(":register collection ioremap err\n"); + return -EFAULT; + } + + num_regs -= (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); + + for (i = 0; i < (CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS * + IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) + *(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0; + + return 0; +} + +/* + * FUNCTION: ipa_hal_save_regs_rsrc_db + * + * This function saves the various IPA RSRC_MNGR_DB registers + * + * @param + * + * @return + */ +static void ipa_hal_save_regs_rsrc_db(void) +{ + u32 rsrc_type = 0; + u32 rsrc_id = 0; + u32 rsrc_group = 0; + union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u + ipa_rsrc_mngr_db_cfg = { { 0 } }; + + ipa_rsrc_mngr_db_cfg.def.rsrc_grp_sel = rsrc_group; + + for (rsrc_type = 0; rsrc_type <= IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX; + rsrc_type++) { + for (rsrc_id = 0; rsrc_id <= IPA_RSCR_MNGR_DB_RSRC_ID_MAX; + rsrc_id++) { + ipa_rsrc_mngr_db_cfg.def.rsrc_id_sel = rsrc_id; + ipa_rsrc_mngr_db_cfg.def.rsrc_type_sel = rsrc_type; + IPA_WRITE_SCALER_REG(IPA_RSRC_MNGR_DB_CFG, + ipa_rsrc_mngr_db_cfg.value); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_rsrc_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_RSRC_READ); + ipa_reg_save.ipa.dbg.ipa_rsrc_mngr_db_list_read_arr + [rsrc_type][rsrc_id].value = + IPA_READ_SCALER_REG(IPA_RSRC_MNGR_DB_LIST_READ); + } + } +} + +/* + * FUNCTION: ipa_reg_save_anomaly_check + * + * Checks RX state and TX state upon crash dump collection and prints + * anomalies. + * + * TBD- Add more anomaly checks in the future. + * + * @return + */ +static void ipa_reg_save_anomaly_check(void) +{ + if ((ipa_reg_save.ipa.gen.ipa_state.rx_wait != 0) + || (ipa_reg_save.ipa.gen.ipa_state.rx_idle != 1)) { + IPADBG( + "RX ACTIVITY, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n", + ipa_reg_save.ipa.gen.ipa_state.rx_wait, + ipa_reg_save.ipa.gen.ipa_state.rx_idle, + ipa_reg_save.ipa.gen.ipa_state_rx_active.endpoints); + + if (ipa_reg_save.ipa.gen.ipa_state.tx_idle != 1) { + IPADBG( + "TX ACTIVITY, ipa_state.idle = %d, ipa_state_tx_wrapper.tx0_idle = %d, ipa_state_tx_wrapper.tx1_idle = %d\n", + ipa_reg_save.ipa.gen.ipa_state.tx_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx0_idle, + ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx1_idle); + + IPADBG( + "ipa_state_tx0.last_cmd_pipe = %d, ipa_state_tx1.last_cmd_pipe = %d\n", + ipa_reg_save.ipa.gen.ipa_state_tx0.last_cmd_pipe, + ipa_reg_save.ipa.gen.ipa_state_tx1.last_cmd_pipe); + } + } +} diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h new file mode 100644 index 000000000000..ca4af90b0877 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h @@ -0,0 +1,1284 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_REG_DUMP_H_) +#define _IPA_REG_DUMP_H_ + +#include +#include + +#include "ipa_i.h" + +#include "ipa_pkt_cntxt.h" +#include "ipa_hw_common_ex.h" + +/* + * The following macros are used to peek and poke register values and + * are required by some of the macros and include files that follow... + */ +#define my_in_dword(addr) \ + ({ u32 __v = readl_relaxed((addr)); __iormb(); __v; }) +#define in_dword(addr) \ + my_in_dword((u8 *) ipa3_ctx->reg_collection_base + \ + (u32)(addr)) + +#define my_in_dword_masked(addr, mask) \ + (my_in_dword(addr) & (mask)) +#define in_dword_masked(addr, mask) \ + my_in_dword_masked((u8 *) ipa3_ctx->reg_collection_base + \ + (u32)(addr), (mask)) + +#define my_out_dword(addr, val) \ + ({ __iowmb(); writel_relaxed((val), (addr)); }) +#define out_dword(addr, val) \ + my_out_dword((u8 *) ipa3_ctx->reg_collection_base + \ + (u32)(addr), (val)) + +#define IPA_0_IPA_WRAPPER_BASE 0 /* required by following includes */ + +#include "ipa_hwio.h" +#include "gsi_hwio.h" +#include "ipa_gcc_hwio.h" + +#include "ipa_hwio_def.h" +#include "gsi_hwio_def.h" +#include "ipa_gcc_hwio_def.h" + +#define IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS 0x6 +#define IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS 0x4 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_EP 7 +#define IPA_DEBUG_TESTBUS_RSRC_NUM_GRP 3 +#define IPA_TESTBUS_SEL_EP_MAX 0x1F +#define IPA_TESTBUS_SEL_EXTERNAL_MAX 0x40 +#define IPA_TESTBUS_SEL_INTERNAL_MAX 0xFF +#define IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX 0x40 +#define IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS 0x9 +#define IPA_RSCR_MNGR_DB_RSRC_ID_MAX 0x3F +#define IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX 0xA + +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS (0x0) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0 (0x1) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1 (0x2) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2 (0x3) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3 (0x4) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4 (0x5) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG (0x9) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0 (0xB) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1 (0xC) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2 (0xD) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3 (0xE) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0 (0x13) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1 (0x14) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2 (0x15) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3 (0x16) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4 (0x17) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5 (0x18) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0 (0x1B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1 (0x1C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0 (0x1F) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1 (0x20) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2 (0x21) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3 (0x22) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4 (0x23) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0 (0x27) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1 (0x28) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2 (0x29) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3 (0x2A) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0 (0x2B) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1 (0x2C) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2 (0x2D) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3 (0x2E) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0 (0x33) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1 (0x34) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2 (0x35) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3 (0x36) +#define HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR (0x3A) + +#define IPA_DEBUG_TESTBUS_DEF_EXTERNAL 50 +#define IPA_DEBUG_TESTBUS_DEF_INTERNAL 6 + +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 8 + +#define IPA_REG_SAVE_GSI_NUM_EE 3 + +#define IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS 22 + +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000 +#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT 13 + +#define IPA_REG_SAVE_HWP_GSI_EE 2 + +/* + * A structure used to map a source address to destination address... + */ +struct map_src_dst_addr_s { + u32 src_addr; /* register offset to copy value from */ + u32 *dst_addr; /* memory address to copy register value to */ +}; + +/* + * A macro to generate the names of scaler (ie. non-vector) registers + * that reside in the *hwio.h files (said files contain the manifest + * constants for the registers' offsets in the register memory map). + */ +#define GEN_SCALER_REG_OFST(reg_name) \ + (HWIO_ ## reg_name ## _ADDR) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via one dimension. + */ +#define GEN_1xVECTOR_REG_OFST(reg_name, row) \ + (HWIO_ ## reg_name ## _ADDR(row)) + +/* + * A macro to generate the names of vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate access to registers that are + * addressed via two dimensions. + */ +#define GEN_2xVECTOR_REG_OFST(reg_name, row, col) \ + (HWIO_ ## reg_name ## _ADDR(row, col)) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a scaler + * register.. + */ +#define IPA_READ_SCALER_REG(reg_name) \ + HWIO_ ## reg_name ## _IN + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a one + * dimensional vector register... + */ +#define IPA_READ_1xVECTOR_REG(reg_name, row) \ + HWIO_ ## reg_name ## _INI(row) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate read access from a two + * dimensional vector register... + */ +#define IPA_READ_2xVECTOR_REG(reg_name, row, col) \ + HWIO_ ## reg_name ## _INI2(row, col) + +/* + * A macro to generate the access to scaler registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a scaler + * register.. + */ +#define IPA_WRITE_SCALER_REG(reg_name, val) \ + HWIO_ ## reg_name ## _OUT(val) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a one + * dimensional vector register... + */ +#define IPA_WRITE_1xVECTOR_REG(reg_name, row, val) \ + HWIO_ ## reg_name ## _OUTI(row, val) + +/* + * A macro to generate the access to vector registers that reside in + * the *hwio.h files (said files contain the manifest constants for + * the registers' offsets in the register memory map). More + * specifically, this macro will generate write access to a two + * dimensional vector register... + */ +#define IPA_WRITE_2xVECTOR_REG(reg_name, row, col, val) \ + HWIO_ ## reg_name ## _OUTI2(row, col, val) + +/* + * Macro that helps generate a mapping between a register's address + * and where the register's value will get stored (ie. source and + * destination address mapping) upon dump... + */ +#define GEN_SRC_DST_ADDR_MAP(reg_name, sub_struct, field_name) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.sub_struct.field_name } + +/* + * Macro to get value of bits 18:13, used tp get rsrc cnts from + * IPA_DEBUG_DATA + */ +#define IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA(x) \ + ((x & IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK) >> \ + IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT) + +/* + * Macro to get rsrc cnt of specific rsrc type and rsrc grp from test + * bus collected data + */ +#define IPA_DEBUG_TESTBUS_GET_RSRC_TYPE_CNT(rsrc_type, rsrc_grp) \ + IPA_DEBUG_TESTBUS_DATA_GET_RSRC_CNT_BITS_FROM_DEBUG_DATA( \ + ipa_reg_save.ipa.testbus->ep_rsrc[rsrc_type].entry_ep \ + [rsrc_grp].testbus_data.value) + +/* + * Macro to define a particular register cfg entry for all 3 EE + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \ + { GEN_SCALER_REG_OFST(reg_name), \ + (u32 *)&ipa_reg_save.ipa.gsi_fifo_status[index].var_name } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(reg_name, var_name) \ + { 0, 0 } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[2].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[5].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[6].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[7].var_name } + +/* + * Macro to define a particular register cfg entry for all resource + * group register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[2].var_name } + +/* + * Macro to define a particular register cfg entry for all source + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[2].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[5].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[6].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[7].var_name } + +/* + * Macro to define a particular register cfg entry for all dest + * resource group count register + */ +#define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name } + +/* + * Macro to define a particular register cfg entry for GSI QSB debug + * registers + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0] }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1] }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2] }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] } + +/* + * IPA HW Platform Type + */ +enum ipa_hw_ee_e { + IPA_HW_A7_EE = 0, /* A7's execution environment */ + IPA_HW_Q6_EE = 1, /* Q6's execution environment */ + IPA_HW_HWP_EE = 3, /* HWP's execution environment */ + IPA_HW_EE_MAX, /* Max EE to support */ +}; + +/* + * General IPA register save data struct (ie. this is where register + * values, once read, get placed... + */ +struct ipa_gen_regs_s { + struct ipa_hwio_def_ipa_state_s + ipa_state; + struct ipa_hwio_def_ipa_gsi_conf_s + ipa_gsi_conf; + struct ipa_hwio_def_ipa_state_rx_active_s + ipa_state_rx_active; + struct ipa_hwio_def_ipa_state_tx_wrapper_s + ipa_state_tx_wrapper; + struct ipa_hwio_def_ipa_state_tx0_s + ipa_state_tx0; + struct ipa_hwio_def_ipa_state_tx1_s + ipa_state_tx1; + struct ipa_hwio_def_ipa_state_aggr_active_s + ipa_state_aggr_active; + struct ipa_hwio_def_ipa_state_dfetcher_s + ipa_state_dfetcher; + struct ipa_hwio_def_ipa_state_fetcher_mask_s + ipa_state_fetcher_mask; + struct ipa_hwio_def_ipa_state_gsi_aos_s + ipa_state_gsi_aos; + struct ipa_hwio_def_ipa_state_gsi_if_s + ipa_state_gsi_if; + struct ipa_hwio_def_ipa_state_gsi_skip_s + ipa_state_gsi_skip; + struct ipa_hwio_def_ipa_state_gsi_tlv_s + ipa_state_gsi_tlv; + struct ipa_hwio_def_ipa_tag_timer_s + ipa_tag_timer; + struct ipa_hwio_def_ipa_dpl_timer_lsb_s + ipa_dpl_timer_lsb; + struct ipa_hwio_def_ipa_dpl_timer_msb_s + ipa_dpl_timer_msb; + struct ipa_hwio_def_ipa_proc_iph_cfg_s + ipa_proc_iph_cfg; + struct ipa_hwio_def_ipa_route_s + ipa_route; + struct ipa_hwio_def_ipa_spare_reg_1_s + ipa_spare_reg_1; + struct ipa_hwio_def_ipa_spare_reg_2_s + ipa_spare_reg_2; + struct ipa_hwio_def_ipa_log_s + ipa_log; + struct ipa_hwio_def_ipa_log_buf_status_cfg_s + ipa_log_buf_status_cfg; + struct ipa_hwio_def_ipa_log_buf_status_addr_s + ipa_log_buf_status_addr; + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s + ipa_log_buf_status_write_ptr; + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s + ipa_log_buf_status_ram_ptr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s + ipa_log_buf_hw_cmd_cfg; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s + ipa_log_buf_hw_cmd_addr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s + ipa_log_buf_hw_cmd_write_ptr; + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s + ipa_log_buf_hw_cmd_ram_ptr; + struct ipa_hwio_def_ipa_comp_hw_version_s + ipa_comp_hw_version; + struct ipa_hwio_def_ipa_filt_rout_hash_en_s + ipa_filt_rout_hash_en; + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s + ipa_filt_rout_hash_flush; + struct ipa_hwio_def_ipa_state_fetcher_s + ipa_state_fetcher; + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s + ipa_ipv4_filter_init_values; + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s + ipa_ipv6_filter_init_values; + struct ipa_hwio_def_ipa_ipv4_route_init_values_s + ipa_ipv4_route_init_values; + struct ipa_hwio_def_ipa_ipv6_route_init_values_s + ipa_ipv6_route_init_values; + struct ipa_hwio_def_ipa_bcr_s + ipa_bcr; + struct ipa_hwio_def_ipa_bam_activated_ports_s + ipa_bam_activated_ports; + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s + ipa_tx_commander_cmdq_status; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s + ipa_log_buf_hw_snif_el_en; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + ipa_log_buf_hw_snif_el_wr_n_rd_sel; + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s + ipa_log_buf_hw_snif_el_cli_mux; + struct ipa_hwio_def_ipa_state_acl_s + ipa_state_acl; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s + ipa_sys_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s + ipa_sys_pkt_proc_cntxt_base_msb; + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s + ipa_local_pkt_proc_cntxt_base; + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s + ipa_rsrc_grp_cfg; + struct ipa_hwio_def_ipa_comp_cfg_s + ipa_comp_cfg; +}; + +/* + * General IPA register save data struct + */ +struct ipa_reg_save_gen_ee_s { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s + ipa_irq_stts_ee_n; + struct ipa_hwio_def_ipa_irq_en_ee_n_s + ipa_irq_en_ee_n; + struct ipa_hwio_def_ipa_fec_addr_ee_n_s + ipa_fec_addr_ee_n; + struct ipa_hwio_def_ipa_fec_attr_ee_n_s + ipa_fec_attr_ee_n; + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s + ipa_snoc_fec_ee_n; + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s + ipa_holb_drop_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s + ipa_suspend_irq_info_ee_n; + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s + ipa_suspend_irq_en_ee_n; +}; + +/* + * Pipe Endp IPA register save data struct + */ +struct ipa_reg_save_pipe_endp_s { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s + ipa_endp_init_ctrl_n; + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s + ipa_endp_init_ctrl_scnd_n; + struct ipa_hwio_def_ipa_endp_init_cfg_n_s + ipa_endp_init_cfg_n; + struct ipa_hwio_def_ipa_endp_init_nat_n_s + ipa_endp_init_nat_n; + struct ipa_hwio_def_ipa_endp_init_hdr_n_s + ipa_endp_init_hdr_n; + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s + ipa_endp_init_hdr_ext_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s + ipa_endp_init_hdr_metadata_mask_n; + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s + ipa_endp_init_hdr_metadata_n; + struct ipa_hwio_def_ipa_endp_init_mode_n_s + ipa_endp_init_mode_n; + struct ipa_hwio_def_ipa_endp_init_aggr_n_s + ipa_endp_init_aggr_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s + ipa_endp_init_hol_block_en_n; + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s + ipa_endp_init_hol_block_timer_n; + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s + ipa_endp_init_deaggr_n; + struct ipa_hwio_def_ipa_endp_status_n_s + ipa_endp_status_n; + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s + ipa_endp_init_rsrc_grp_n; + struct ipa_hwio_def_ipa_endp_init_seq_n_s + ipa_endp_init_seq_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s + ipa_endp_gsi_cfg_tlv_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s + ipa_endp_gsi_cfg_aos_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s + ipa_endp_gsi_cfg1_n; + struct ipa_hwio_def_ipa_endp_gsi_cfg2_n_s + ipa_endp_gsi_cfg2_n; + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s + ipa_endp_filter_router_hsh_cfg_n; +}; + +/* + * Pipe IPA register save data struct + */ +struct ipa_reg_save_pipe_s { + u8 active; + struct ipa_reg_save_pipe_endp_s endp; +}; + +/* + * HWP IPA register save data struct + */ +struct ipa_reg_save_hwp_s { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s + ipa_uc_qmb_sys_addr; + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s + ipa_uc_qmb_local_addr; + struct ipa_hwio_def_ipa_uc_qmb_length_s + ipa_uc_qmb_length; + struct ipa_hwio_def_ipa_uc_qmb_trigger_s + ipa_uc_qmb_trigger; + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s + ipa_uc_qmb_pending_tid; + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s + ipa_uc_qmb_completed_rd_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s + ipa_uc_qmb_completed_wr_fifo_peek; + struct ipa_hwio_def_ipa_uc_qmb_misc_s + ipa_uc_qmb_misc; + struct ipa_hwio_def_ipa_uc_qmb_status_s + ipa_uc_qmb_status; + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s + ipa_uc_qmb_bus_attrib; +}; + +/* + * IPA TESTBUS entry struct + */ +struct ipa_reg_save_ipa_testbus_entry_s { + union ipa_hwio_def_ipa_debug_data_sel_u testbus_sel; + union ipa_hwio_def_ipa_debug_data_u testbus_data; +}; + +/* IPA TESTBUS global struct */ +struct ipa_reg_save_ipa_testbus_global_s { + struct ipa_reg_save_ipa_testbus_entry_s + global[IPA_TESTBUS_SEL_INTERNAL_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX + 1] + [IPA_TESTBUS_SEL_EXTERNAL_MAX + 1]; +}; + +/* IPA TESTBUS per EP struct */ +struct ipa_reg_save_ipa_testbus_ep_rsrc_s { + struct ipa_reg_save_ipa_testbus_entry_s + entry_ep[IPA_DEBUG_TESTBUS_RSRC_NUM_GRP]; +}; + +/* IPA TESTBUS save data struct */ +struct ipa_reg_save_ipa_testbus_s { + struct ipa_reg_save_ipa_testbus_global_s global; + struct ipa_reg_save_ipa_testbus_ep_s + ep[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_reg_save_ipa_testbus_ep_rsrc_s + ep_rsrc[IPA_DEBUG_TESTBUS_RSRC_NUM_EP]; +}; + +/* + * Debug IPA register save data struct + */ +struct ipa_reg_save_dbg_s { + struct ipa_hwio_def_ipa_debug_data_s + ipa_debug_data; + struct ipa_hwio_def_ipa_step_mode_status_s + ipa_step_mode_status; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_cmd_s + ipa_rx_splt_cmdq_0_cmd; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_0_s + ipa_rx_splt_cmdq_0_data_rd_0; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_1_s + ipa_rx_splt_cmdq_0_data_rd_1; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_2_s + ipa_rx_splt_cmdq_0_data_rd_2; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_3_s + ipa_rx_splt_cmdq_0_data_rd_3; + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_status_s + ipa_rx_splt_cmdq_0_status; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_cmd_s + ipa_rx_splt_cmdq_1_cmd; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_0_s + ipa_rx_splt_cmdq_1_data_rd_0; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_1_s + ipa_rx_splt_cmdq_1_data_rd_1; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_2_s + ipa_rx_splt_cmdq_1_data_rd_2; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_3_s + ipa_rx_splt_cmdq_1_data_rd_3; + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_status_s + ipa_rx_splt_cmdq_1_status; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_cmd_s + ipa_rx_splt_cmdq_2_cmd; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_0_s + ipa_rx_splt_cmdq_2_data_rd_0; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_1_s + ipa_rx_splt_cmdq_2_data_rd_1; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_2_s + ipa_rx_splt_cmdq_2_data_rd_2; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_3_s + ipa_rx_splt_cmdq_2_data_rd_3; + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_status_s + ipa_rx_splt_cmdq_2_status; + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s + ipa_rx_hps_cmdq_cmd; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u + ipa_rx_hps_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u + ipa_rx_hps_cmdq_data_rd_1_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u + ipa_rx_hps_cmdq_data_rd_2_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u + ipa_rx_hps_cmdq_data_rd_3_arr[ + IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_count_u + ipa_rx_hps_cmdq_count_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_rx_hps_cmdq_status_u + ipa_rx_hps_cmdq_status_arr[IPA_DEBUG_CMDQ_HPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s + ipa_rx_hps_cmdq_status_empty; + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s + ipa_rx_hps_clients_min_depth_0; + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s + ipa_rx_hps_clients_max_depth_0; + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s + ipa_hps_dps_cmdq_cmd; + union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u + ipa_hps_dps_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_count_u + ipa_hps_dps_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_hps_dps_cmdq_status_u + ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s + ipa_hps_dps_cmdq_status_empty; + + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s + ipa_dps_tx_cmdq_cmd; + union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u + ipa_dps_tx_cmdq_data_rd_0_arr[ + IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_count_u + ipa_dps_tx_cmdq_count_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_dps_tx_cmdq_status_u + ipa_dps_tx_cmdq_status_arr[IPA_DEBUG_CMDQ_DPS_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s + ipa_dps_tx_cmdq_status_empty; + + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s + ipa_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u + ipa_ackmngr_cmdq_data_rd_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_count_u + ipa_ackmngr_cmdq_count_arr[IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + union ipa_hwio_def_ipa_ackmngr_cmdq_status_u + ipa_ackmngr_cmdq_status_arr[ + IPA_DEBUG_CMDQ_ACK_SELECT_NUM_GROUPS]; + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s + ipa_ackmngr_cmdq_status_empty; + + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s + ipa_prod_ackmngr_cmdq_cmd; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u + ipa_prod_ackmngr_cmdq_data_rd_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u + ipa_prod_ackmngr_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u + ipa_prod_ackmngr_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + ipa_prod_ackmngr_cmdq_status_empty; + + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s + ipa_ntf_tx_cmdq_cmd; + union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u + ipa_ntf_tx_cmdq_data_rd_0_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u + ipa_ntf_tx_cmdq_count_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u + ipa_ntf_tx_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1]; + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s + ipa_ntf_tx_cmdq_status_empty; + + union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u + ipa_rsrc_mngr_db_rsrc_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; + union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u + ipa_rsrc_mngr_db_list_read_arr[IPA_RSCR_MNGR_DB_RSRC_TYPE_MAX + + 1][IPA_RSCR_MNGR_DB_RSRC_ID_MAX + + 1]; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_src_rsrc_grp_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s + ipa_src_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s + ipa_src_rsrc_grp_23_rsrc_type_n; +}; + +/* Source Resource Group IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_grp_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s + ipa_dst_rsrc_grp_01_rsrc_type_n; + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s + ipa_dst_rsrc_grp_23_rsrc_type_n; +}; + +/* Source Resource Group Count IPA register save data struct */ +struct ipa_reg_save_src_rsrc_cnt_s { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_src_rsrc_grp_0123_rsrc_type_cnt_n; +}; + +/* Destination Resource Group Count IPA register save data struct */ +struct ipa_reg_save_dst_rsrc_cnt_s { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n; +}; + +/* GSI General register save data struct */ +struct ipa_reg_save_gsi_gen_s { + struct gsi_hwio_def_gsi_cfg_s + gsi_cfg; + struct gsi_hwio_def_gsi_ree_cfg_s + gsi_ree_cfg; +}; + +/* GSI General EE register save data struct */ +struct ipa_reg_save_gsi_gen_ee_s { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s + gsi_manager_ee_qos_n; + struct gsi_hwio_def_ee_n_gsi_status_s + ee_n_gsi_status; + struct gsi_hwio_def_ee_n_cntxt_type_irq_s + ee_n_cntxt_type_irq; + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s + ee_n_cntxt_type_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s + ee_n_cntxt_src_gsi_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s + ee_n_cntxt_src_ev_ch_irq; + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s + ee_n_cntxt_src_gsi_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s + ee_n_cntxt_src_ev_ch_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s + ee_n_cntxt_src_ieob_irq; + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s + ee_n_cntxt_src_ieob_irq_msk; + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s + ee_n_cntxt_gsi_irq_stts; + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s + ee_n_cntxt_glob_irq_stts; + struct gsi_hwio_def_ee_n_error_log_s + ee_n_error_log; + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s + ee_n_cntxt_scratch_0; + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s + ee_n_cntxt_scratch_1; +}; + +/* GSI QSB debug register save data struct */ +struct ipa_reg_save_gsi_qsb_debug_s { + struct + gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s + qsb_log_last_misc[GSI_HW_QSB_LOG_MISC_MAX]; +}; + +static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_ZEROS, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MCS_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_DB_ENG, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_EVE_5, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IC_4, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_MOQA_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TMR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_0, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_1, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_2, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_RD_WR_3, + HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR, +}; + +/* + * GSI QSB debug bus register save data struct + */ +struct ipa_reg_save_gsi_test_bus_s { + struct + gsi_hwio_def_gsi_test_bus_reg_s + test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; +}; + +/* GSI debug MCS registers save data struct */ +struct ipa_reg_save_gsi_mcs_regs_s { + struct + gsi_hwio_def_gsi_debug_sw_rf_n_read_s + mcs_reg[HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn + 1]; +}; + +/* GSI debug counters save data struct */ +struct ipa_reg_save_gsi_debug_cnt_s { + struct + gsi_hwio_def_gsi_debug_countern_s + cnt[HWIO_GSI_DEBUG_COUNTERn_MAXn + 1]; +}; + +/* GSI IRAM pointers (IEP) save data struct */ +struct ipa_reg_save_gsi_iram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s + ipa_gsi_top_gsi_iram_ptr_ch_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s + ipa_gsi_top_gsi_iram_ptr_ch_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s + ipa_gsi_top_gsi_iram_ptr_ev_db; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s + ipa_gsi_top_gsi_iram_ptr_new_re; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + ipa_gsi_top_gsi_iram_ptr_ch_dis_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s + ipa_gsi_top_gsi_iram_ptr_ch_empty; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + ipa_gsi_top_gsi_iram_ptr_event_gen_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + ipa_gsi_top_gsi_iram_ptr_timer_expired; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_write_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + ipa_gsi_top_gsi_iram_ptr_read_eng_comp; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + ipa_gsi_top_gsi_iram_ptr_uc_gp_int; + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + ipa_gsi_top_gsi_iram_ptr_int_mod_stopped; +}; + +/* GSI SHRAM pointers save data struct */ +struct ipa_reg_save_gsi_shram_ptr_regs_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr; + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr; +}; + +/* GSI debug register save data struct */ +struct ipa_reg_save_gsi_debug_s { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s + ipa_gsi_top_gsi_debug_busy_reg; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + ipa_gsi_top_gsi_debug_event_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + ipa_gsi_top_gsi_debug_timer_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + ipa_gsi_top_gsi_debug_rd_wr_pending; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s + ipa_gsi_top_gsi_debug_pc_from_sw; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s + ipa_gsi_top_gsi_debug_sw_stall; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + ipa_gsi_top_gsi_debug_pc_for_debug; + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + ipa_gsi_top_gsi_debug_qsb_log_err_trns_id; + struct ipa_reg_save_gsi_qsb_debug_s gsi_qsb_debug; + struct ipa_reg_save_gsi_test_bus_s gsi_test_bus; + struct ipa_reg_save_gsi_mcs_regs_s gsi_mcs_regs; + struct ipa_reg_save_gsi_debug_cnt_s gsi_cnt_regs; + struct ipa_reg_save_gsi_iram_ptr_regs_s gsi_iram_ptrs; + struct ipa_reg_save_gsi_shram_ptr_regs_s gsi_shram_ptrs; +}; + +/* GSI MCS channel scratch registers save data struct */ +struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s { + struct gsi_hwio_def_gsi_shram_n_s + scratch4; + struct gsi_hwio_def_gsi_shram_n_s + scratch5; +}; + +/* GSI Channel Context register save data struct */ +struct ipa_reg_save_gsi_ch_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s + ee_n_gsi_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s + ee_n_gsi_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s + ee_n_gsi_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s + ee_n_gsi_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s + ee_n_gsi_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s + ee_n_gsi_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s + ee_n_gsi_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s + ee_n_gsi_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s + ee_n_gsi_ch_k_re_fetch_read_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s + ee_n_gsi_ch_k_re_fetch_write_ptr; + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s + ee_n_gsi_ch_k_qos; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s + ee_n_gsi_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s + ee_n_gsi_ch_k_scratch_1; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s + ee_n_gsi_ch_k_scratch_2; + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s + ee_n_gsi_ch_k_scratch_3; + struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s + gsi_debug_ee_n_ch_k_vp_table; + struct ipa_reg_save_gsi_mcs_channel_scratch_regs_s mcs_channel_scratch; +}; + +/* GSI Event Context register save data struct */ +struct ipa_reg_save_gsi_evt_cntxt_per_ep_s { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s + ee_n_ev_ch_k_cntxt_0; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s + ee_n_ev_ch_k_cntxt_1; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s + ee_n_ev_ch_k_cntxt_2; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s + ee_n_ev_ch_k_cntxt_3; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s + ee_n_ev_ch_k_cntxt_4; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s + ee_n_ev_ch_k_cntxt_5; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s + ee_n_ev_ch_k_cntxt_6; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s + ee_n_ev_ch_k_cntxt_7; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s + ee_n_ev_ch_k_cntxt_8; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s + ee_n_ev_ch_k_cntxt_9; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s + ee_n_ev_ch_k_cntxt_10; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s + ee_n_ev_ch_k_cntxt_11; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s + ee_n_ev_ch_k_cntxt_12; + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s + ee_n_ev_ch_k_cntxt_13; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s + ee_n_ev_ch_k_scratch_0; + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s + ee_n_ev_ch_k_scratch_1; + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s + gsi_debug_ee_n_ev_k_vp_table; +}; + +/* GSI FIFO status register save data struct */ +struct ipa_reg_save_gsi_fifo_status_s { + union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u gsi_fifo_status_ctrl; + union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u gsi_tlv_fifo_status; + union ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_u + gsi_tlv_pub_fifo_status; + union ipa_hwio_def_ipa_gsi_aos_fifo_status_u gsi_aos_fifo_status; +}; + +/* GSI Channel Context register save top level data struct */ +struct ipa_reg_save_gsi_ch_cntxt_s { + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6]; + struct ipa_reg_save_gsi_ch_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC]; +}; + +/* GSI Event Context register save top level data struct */ +struct ipa_reg_save_gsi_evt_cntxt_s { + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6]; + struct ipa_reg_save_gsi_evt_cntxt_per_ep_s + uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC]; +}; + +/* Top level IPA register save data struct */ +struct ipa_regs_save_hierarchy_s { + struct ipa_gen_regs_s gen; + struct ipa_reg_save_gen_ee_s gen_ee[IPA_HW_EE_MAX]; + struct ipa_reg_save_hwp_s hwp; + struct ipa_reg_save_dbg_s dbg; + struct ipa_reg_save_ipa_testbus_s *testbus; + struct ipa_reg_save_pipe_s pipes[IPA_HW_PIPE_ID_MAX]; + struct ipa_reg_save_src_rsrc_grp_s + src_rsrc_grp[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_grp_s + dst_rsrc_grp[IPA_HW_DST_RSRP_TYPE_MAX]; + struct ipa_reg_save_src_rsrc_cnt_s + src_rsrc_cnt[IPA_HW_SRC_RSRP_TYPE_MAX]; + struct ipa_reg_save_dst_rsrc_cnt_s + dst_rsrc_cnt[IPA_HW_DST_RSRP_TYPE_MAX]; +}; + +/* Top level GSI register save data struct */ +struct gsi_regs_save_hierarchy_s { + struct ipa_reg_save_gsi_gen_s gen; + struct ipa_reg_save_gsi_gen_ee_s gen_ee[IPA_REG_SAVE_GSI_NUM_EE]; + struct ipa_reg_save_gsi_ch_cntxt_s ch_cntxt; + struct ipa_reg_save_gsi_evt_cntxt_s evt_cntxt; + struct ipa_reg_save_gsi_debug_s debug; +}; + +/* Source resources for a resource group */ +struct ipa_reg_save_src_rsrc_cnts_s { + u8 pkt_cntxt; + u8 descriptor_list; + u8 data_descriptor_buffer; + u8 hps_dmars; + u8 reserved_acks; +}; + +/* Destination resources for a resource group */ +struct ipa_reg_save_dst_rsrc_cnts_s { + u8 reserved_sectors; + u8 dps_dmars; +}; + +/* Resource count structure for a resource group */ +struct ipa_reg_save_rsrc_cnts_per_grp_s { + /* Resource group number */ + u8 resource_group; + /* Source resources for a resource group */ + struct ipa_reg_save_src_rsrc_cnts_s src; + /* Destination resources for a resource group */ + struct ipa_reg_save_dst_rsrc_cnts_s dst; +}; + +/* Top level resource count structure */ +struct ipa_reg_save_rsrc_cnts_s { + /* Resource count structure for PCIE group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s pcie; + /* Resource count structure for DDR group */ + struct ipa_reg_save_rsrc_cnts_per_grp_s ddr; +}; + +/* Top level IPA and GSI registers save data struct */ +struct regs_save_hierarchy_s { + struct ipa_regs_save_hierarchy_s ipa; + struct gsi_regs_save_hierarchy_s gsi; + bool pkt_ctntx_active[IPA_HW_PKT_CTNTX_MAX]; + union ipa_hwio_def_ipa_ctxh_ctrl_u pkt_ctntxt_lock; + enum ipa_hw_pkt_cntxt_state_e + pkt_cntxt_state[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_pkt_ctntx_s + pkt_ctntx[IPA_HW_PKT_CTNTX_MAX]; + struct ipa_reg_save_rsrc_cnts_s rsrc_cnts; + struct ipa_reg_save_gsi_fifo_status_s + gsi_fifo_status[IPA_HW_PIPE_ID_MAX]; +}; + +#endif /* #if !defined(_IPA_REG_DUMP_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio.h new file mode 100644 index 000000000000..b0565ba45635 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio.h @@ -0,0 +1,2313 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 and only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#if !defined(_GSI_HWIO_H_) +#define _GSI_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions. + * + * ***************************************************************************** + */ + +#define GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_GSI_CFG_ADDR (GSI_REG_BASE + 0x00000000) +#define HWIO_GSI_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_GSI_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_GSI_CFG_RMSK 0x3f +#define HWIO_GSI_CFG_ATTR 0x3 +#define HWIO_GSI_CFG_IN in_dword_masked(HWIO_GSI_CFG_ADDR, \ + HWIO_GSI_CFG_RMSK) +#define HWIO_GSI_CFG_INM(m) in_dword_masked(HWIO_GSI_CFG_ADDR, m) +#define HWIO_GSI_CFG_OUT(v) out_dword(HWIO_GSI_CFG_ADDR, v) +#define HWIO_GSI_CFG_OUTM(m, v) out_dword_masked_ns(HWIO_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_CFG_IN) +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR (GSI_REG_BASE + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_PHYS (GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OFFS (GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_GSI_ZEROS_ADDR (GSI_REG_BASE + 0x00000010) +#define HWIO_GSI_ZEROS_PHYS (GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_GSI_ZEROS_OFFS (GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR (GSI_REG_BASE + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR (GSI_REG_BASE + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_PHYS (GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OFFS (GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GSI_PERIPH_PENDING_ADDR (GSI_REG_BASE + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_GSI_MOQA_CFG_ADDR (GSI_REG_BASE + 0x00000030) +#define HWIO_GSI_MOQA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_GSI_REE_CFG_ADDR (GSI_REG_BASE + 0x00000038) +#define HWIO_GSI_REE_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_GSI_REE_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_GSI_REE_CFG_RMSK 0xff01 +#define HWIO_GSI_REE_CFG_ATTR 0x3 +#define HWIO_GSI_REE_CFG_IN in_dword_masked(HWIO_GSI_REE_CFG_ADDR, \ + HWIO_GSI_REE_CFG_RMSK) +#define HWIO_GSI_REE_CFG_INM(m) in_dword_masked(HWIO_GSI_REE_CFG_ADDR, m) +#define HWIO_GSI_REE_CFG_OUT(v) out_dword(HWIO_GSI_REE_CFG_ADDR, v) +#define HWIO_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_REE_CFG_IN) +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_GSI_SHRAM_WR_WRR_ADDR (GSI_REG_BASE + 0x00000050) +#define HWIO_GSI_SHRAM_WR_WRR_PHYS (GSI_REG_BASE_PHYS + 0x00000050) +#define HWIO_GSI_SHRAM_WR_WRR_OFFS (GSI_REG_BASE_OFFS + 0x00000050) +#define HWIO_GSI_SHRAM_RD_WRR_ADDR (GSI_REG_BASE + 0x00000058) +#define HWIO_GSI_SHRAM_RD_WRR_PHYS (GSI_REG_BASE_PHYS + 0x00000058) +#define HWIO_GSI_SHRAM_RD_WRR_OFFS (GSI_REG_BASE_OFFS + 0x00000058) +#define HWIO_GSI_CGC_CTRL_ADDR (GSI_REG_BASE + 0x00000060) +#define HWIO_GSI_CGC_CTRL_PHYS (GSI_REG_BASE_PHYS + 0x00000060) +#define HWIO_GSI_CGC_CTRL_OFFS (GSI_REG_BASE_OFFS + 0x00000060) +#define HWIO_GSI_MSI_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_GSI_EVENT_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_GSI_DATA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_GSI_TRE_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a4) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000bc) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c4) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000dc) +#define HWIO_IC_READ_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IC_WRITE_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR (GSI_REG_BASE + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR (GSI_REG_BASE + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f4) +#define HWIO_IC_INT_WEIGHT_REE_ADDR (GSI_REG_BASE + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_PHYS (GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_OFFS (GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR (GSI_REG_BASE + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_INT_ENG_ADDR (GSI_REG_BASE + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_CSR_ADDR (GSI_REG_BASE + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_PHYS (GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_OFFS (GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR (GSI_REG_BASE + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR (GSI_REG_BASE + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_DB_ENG_ADDR (GSI_REG_BASE + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR (GSI_REG_BASE + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_PHYS (GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OFFS (GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (GSI_REG_BASE + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_SDMA_ADDR (GSI_REG_BASE + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_PHYS (GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_OFFS (GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_GSI_SDMA_CFG_ADDR (GSI_REG_BASE + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000003c) +#define HWIO_GSI_SDMA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) (GSI_REG_BASE + 0x00000140 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) (GSI_REG_BASE + 0x00000144 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n) (GSI_REG_BASE + 0x00000300 + \ + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_RMSK 0x1f1f03 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_GSI_MANAGER_EE_QOS_n_INI(n) in_dword_masked( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + HWIO_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_GSI_MANAGER_EE_QOS_n_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + mask) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTI(n, val) out_dword( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + val) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + mask, \ + val, \ + HWIO_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0x1f0000 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0x1f00 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x00000250) +#define HWIO_GSI_IRAM_PTR_CH_CMD_ADDR (GSI_REG_BASE + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (GSI_REG_BASE + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_CH_DB_ADDR (GSI_REG_BASE + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_EV_DB_ADDR (GSI_REG_BASE + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_PHYS (GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_OFFS (GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_NEW_RE_ADDR (GSI_REG_BASE + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_PHYS (GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OFFS (GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (GSI_REG_BASE + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR (GSI_REG_BASE + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_PHYS (GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OFFS (GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (GSI_REG_BASE + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (GSI_REG_BASE + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (GSI_REG_BASE + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (GSI_REG_BASE + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (GSI_REG_BASE + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR (GSI_REG_BASE + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_PHYS (GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OFFS (GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR (GSI_REG_BASE + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) (GSI_REG_BASE + 0x00000450 + \ + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_ADDR(n) (GSI_REG_BASE + 0x00004000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00004000 + \ + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00004000 + \ + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_ADDR(n) (GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_MAXn 1023 +#define HWIO_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_GSI_SHRAM_n_INI(n) in_dword_masked(HWIO_GSI_SHRAM_n_ADDR( \ + n), \ + HWIO_GSI_SHRAM_n_RMSK) +#define HWIO_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_GSI_SHRAM_n_OUTI(n, val) out_dword(HWIO_GSI_SHRAM_n_ADDR( \ + n), val) +#define HWIO_GSI_SHRAM_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask, \ + val, \ + HWIO_GSI_SHRAM_n_INI(n)) +#define HWIO_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_SHRAM_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_ADDR (GSI_REG_BASE + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_SEL_OUT(v) out_dword(HWIO_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_GSI_TEST_BUS_SEL_IN) +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_GSI_TEST_BUS_REG_ADDR (GSI_REG_BASE + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + HWIO_GSI_TEST_BUS_REG_RMSK) +#define HWIO_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_BUSY_REG_ADDR (GSI_REG_BASE + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_GSI_DEBUG_EVENT_PENDING_ADDR (GSI_REG_BASE + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_GSI_DEBUG_TIMER_PENDING_ADDR (GSI_REG_BASE + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_ADDR (GSI_REG_BASE + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (GSI_REG_BASE + 0x00001200 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_ADDR(n) (GSI_REG_BASE + 0x00001240 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_COUNTERn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_GSI_DEBUG_PC_FROM_SW_ADDR (GSI_REG_BASE + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_PHYS (GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OFFS (GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_GSI_DEBUG_SW_STALL_ADDR (GSI_REG_BASE + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_PHYS (GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_OFFS (GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR (GSI_REG_BASE + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_PHYS (GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_OFFS (GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR (GSI_REG_BASE + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR (GSI_REG_BASE + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (GSI_REG_BASE + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (GSI_REG_BASE_PHYS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (GSI_REG_BASE_OFFS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR (GSI_REG_BASE + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_PHYS (GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_OFFS (GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR (GSI_REG_BASE + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_2_ADDR (GSI_REG_BASE + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_PHYS (GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_OFFS (GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (GSI_REG_BASE + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (GSI_REG_BASE + 0x00001080 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (GSI_REG_BASE + 0x00001100 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 16 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + mask) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 11 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k), \ + mask) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) (GSI_REG_BASE + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_UC_SRC_IRQ_ADDR (GSI_REG_BASE + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_PHYS (GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_OFFS (GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_MSK_ADDR (GSI_REG_BASE + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_PHYS (GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_OFFS (GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_CLR_ADDR (GSI_REG_BASE + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_GSI_ACC_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x0000050c + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ROUTINE_ADDR (GSI_REG_BASE + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_GSI_ACC_GO_ADDR (GSI_REG_BASE + 0x00000528) +#define HWIO_GSI_ACC_GO_PHYS (GSI_REG_BASE_PHYS + 0x00000528) +#define HWIO_GSI_ACC_GO_OFFS (GSI_REG_BASE_OFFS + 0x00000528) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_ADDR (GSI_REG_BASE + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_PHYS (GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_OFFS (GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR (GSI_REG_BASE + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR (GSI_REG_BASE + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_GSI_IC_2_UC_MCS_VLD_ADDR (GSI_REG_BASE + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_PC_ADDR (GSI_REG_BASE + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_PHYS (GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_OFFS (GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000540 + \ + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_VLD_ADDR (GSI_REG_BASE + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_ADDR (GSI_REG_BASE + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000560 + \ + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x0001c000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7dfff +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x0001c004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x0001c008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0001c00c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x0001c010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x0001c014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x0001c018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0001c01c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k) (GSI_REG_BASE + 0x0001c05c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_RMSK 0x70f +#define HWIO_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_QOS_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_EE_n_GSI_CH_k_QOS_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c070 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x0001d000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x0001d004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x0001d008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0001d00c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x0001d010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x0001d014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x0001d018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0001d01c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k) (GSI_REG_BASE + 0x0001d020 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k) (GSI_REG_BASE + 0x0001d024 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k) (GSI_REG_BASE + 0x0001d028 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k) (GSI_REG_BASE + 0x0001d02c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k) (GSI_REG_BASE + 0x0001d030 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k) (GSI_REG_BASE + 0x0001d034 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXk 11 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXk 11 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_STATUS_ADDR(n) (GSI_REG_BASE + 0x0001f000 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_STATUS_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_EE_n_GSI_STATUS_RMSK) +#define HWIO_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f008 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f010 + 0x4000 * \ + (n)) +#define HWIO_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f018 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n) (GSI_REG_BASE + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n) (GSI_REG_BASE + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n) (GSI_REG_BASE + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_ADDR(n) (GSI_REG_BASE + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n) (GSI_REG_BASE + 0x0001f048 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n) (GSI_REG_BASE + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (GSI_REG_BASE + 0x0001f088 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f094 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x1ffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK 0x1ffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f0b0 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0001f100 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x0001f108 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f110 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0001f118 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x0001f120 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f128 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_ADDR(n) (GSI_REG_BASE + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (GSI_REG_BASE + 0x0001f188 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (GSI_REG_BASE + 0x0001f18c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f18c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f18c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_ADDR(n) (GSI_REG_BASE + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_ADDR(n) (GSI_REG_BASE + 0x0001f200 + 0x4000 * \ + (n)) +#define HWIO_EE_n_ERROR_LOG_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_EE_n_ERROR_LOG_RMSK) +#define HWIO_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_ERROR_LOG_INI(n)) +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_EE_n_ERROR_LOG_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n) (GSI_REG_BASE + 0x0001f400 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_0_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n) (GSI_REG_BASE + 0x0001f404 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_1_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_GSI_MCS_CFG_ADDR (GSI_REG_BASE + 0x0000b000) +#define HWIO_GSI_MCS_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GSI_SP_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (GSI_REG_BASE + 0x0000c000 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c008 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c010 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x0000c01c + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio_def.h new file mode 100644 index 000000000000..0e7c02c684d1 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/gsi_hwio_def.h @@ -0,0 +1,517 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_GSI_HWIO_DEF_H_) +#define _GSI_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +struct gsi_hwio_def_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_cfg_u { + struct gsi_hwio_def_gsi_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 reserved0 : 7; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union gsi_hwio_def_gsi_ree_cfg_u { + struct gsi_hwio_def_gsi_ree_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union gsi_hwio_def_gsi_manager_ee_qos_n_u { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_shram_n_s { + u32 shram : 32; +}; +union gsi_hwio_def_gsi_shram_n_u { + struct gsi_hwio_def_gsi_shram_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union gsi_hwio_def_gsi_test_bus_sel_u { + struct gsi_hwio_def_gsi_test_bus_sel_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union gsi_hwio_def_gsi_test_bus_reg_u { + struct gsi_hwio_def_gsi_test_bus_reg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_gsi_debug_countern_u { + struct gsi_hwio_def_gsi_debug_countern_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s { + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; +union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union gsi_hwio_def_gsi_debug_sw_rf_n_read_u { + struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_u { + struct gsi_hwio_def_gsi_debug_ee_n_ch_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u { + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 reserved0 : 1; + u32 erindex : 5; + u32 reserved1 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 use_escape_buf_only : 1; + u32 reserved1 : 21; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_qos_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union gsi_hwio_def_ee_n_gsi_status_u { + struct gsi_hwio_def_ee_n_gsi_status_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 17; + u32 reserved0 : 15; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_s { + u32 error_log : 32; +}; +union gsi_hwio_def_ee_n_error_log_u { + struct gsi_hwio_def_ee_n_error_log_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union gsi_hwio_def_ee_n_error_log_clr_u { + struct gsi_hwio_def_ee_n_error_log_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_0_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_1_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio.h new file mode 100644 index 000000000000..c28da472b837 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio.h @@ -0,0 +1,16806 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_GCC_HWIO_H_) +#define _IPA_GCC_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +#define GCC_CLK_CTL_REG_REG_BASE (CLK_CTL_BASE + 0x00000000) +#define GCC_CLK_CTL_REG_REG_BASE_PHYS (CLK_CTL_BASE_PHYS + 0x00000000) +#define GCC_CLK_CTL_REG_REG_BASE_OFFS 0x00000000 +#define HWIO_GCC_GPLL0_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000000) +#define HWIO_GCC_GPLL0_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_GCC_GPLL0_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_GCC_GPLL0_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000004) +#define HWIO_GCC_GPLL0_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000004) +#define HWIO_GCC_GPLL0_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000004) +#define HWIO_GCC_GPLL0_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000008) +#define HWIO_GCC_GPLL0_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000008) +#define HWIO_GCC_GPLL0_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000008) +#define HWIO_GCC_GPLL0_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000014) +#define HWIO_GCC_GPLL0_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_GCC_GPLL0_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_GCC_GPLL0_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000020) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000020) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000020) +#define HWIO_GCC_GPLL0_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000030) +#define HWIO_GCC_GPLL0_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000030) +#define HWIO_GCC_GPLL0_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000030) +#define HWIO_GCC_GPLL0_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000034) +#define HWIO_GCC_GPLL0_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000034) +#define HWIO_GCC_GPLL0_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000034) +#define HWIO_GCC_GPLL0_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000038) +#define HWIO_GCC_GPLL0_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000038) +#define HWIO_GCC_GPLL0_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000038) +#define HWIO_GCC_GPLL0_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000003c) +#define HWIO_GCC_GPLL0_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000003c) +#define HWIO_GCC_GPLL0_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000003c) +#define HWIO_GCC_GPLL0_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000040) +#define HWIO_GCC_GPLL0_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000040) +#define HWIO_GCC_GPLL0_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000040) +#define HWIO_GCC_GPLL0_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000044) +#define HWIO_GCC_GPLL0_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000044) +#define HWIO_GCC_GPLL0_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000044) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000050) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000050) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000050) +#define HWIO_GCC_GPLL1_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001000) +#define HWIO_GCC_GPLL1_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001000) +#define HWIO_GCC_GPLL1_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001000) +#define HWIO_GCC_GPLL1_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001004) +#define HWIO_GCC_GPLL1_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001004) +#define HWIO_GCC_GPLL1_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001004) +#define HWIO_GCC_GPLL1_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001008) +#define HWIO_GCC_GPLL1_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001008) +#define HWIO_GCC_GPLL1_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001008) +#define HWIO_GCC_GPLL1_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001014) +#define HWIO_GCC_GPLL1_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001014) +#define HWIO_GCC_GPLL1_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001014) +#define HWIO_GCC_GPLL1_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001020) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001020) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001020) +#define HWIO_GCC_GPLL1_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001030) +#define HWIO_GCC_GPLL1_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001030) +#define HWIO_GCC_GPLL1_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001030) +#define HWIO_GCC_GPLL1_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001034) +#define HWIO_GCC_GPLL1_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001034) +#define HWIO_GCC_GPLL1_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001034) +#define HWIO_GCC_GPLL1_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001038) +#define HWIO_GCC_GPLL1_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001038) +#define HWIO_GCC_GPLL1_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001038) +#define HWIO_GCC_GPLL1_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000103c) +#define HWIO_GCC_GPLL1_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000103c) +#define HWIO_GCC_GPLL1_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000103c) +#define HWIO_GCC_GPLL1_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001040) +#define HWIO_GCC_GPLL1_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001040) +#define HWIO_GCC_GPLL1_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001040) +#define HWIO_GCC_GPLL1_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001044) +#define HWIO_GCC_GPLL1_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001044) +#define HWIO_GCC_GPLL1_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001044) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001050) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001050) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001050) +#define HWIO_GCC_GPLL2_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002000) +#define HWIO_GCC_GPLL2_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002000) +#define HWIO_GCC_GPLL2_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002000) +#define HWIO_GCC_GPLL2_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002004) +#define HWIO_GCC_GPLL2_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002004) +#define HWIO_GCC_GPLL2_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002004) +#define HWIO_GCC_GPLL2_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002008) +#define HWIO_GCC_GPLL2_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002008) +#define HWIO_GCC_GPLL2_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002008) +#define HWIO_GCC_GPLL2_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002014) +#define HWIO_GCC_GPLL2_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002014) +#define HWIO_GCC_GPLL2_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002014) +#define HWIO_GCC_GPLL2_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002020) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002020) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002020) +#define HWIO_GCC_GPLL2_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002030) +#define HWIO_GCC_GPLL2_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002030) +#define HWIO_GCC_GPLL2_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002030) +#define HWIO_GCC_GPLL2_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002034) +#define HWIO_GCC_GPLL2_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002034) +#define HWIO_GCC_GPLL2_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002034) +#define HWIO_GCC_GPLL2_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002038) +#define HWIO_GCC_GPLL2_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002038) +#define HWIO_GCC_GPLL2_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002038) +#define HWIO_GCC_GPLL2_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000203c) +#define HWIO_GCC_GPLL2_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000203c) +#define HWIO_GCC_GPLL2_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000203c) +#define HWIO_GCC_GPLL2_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002040) +#define HWIO_GCC_GPLL2_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002040) +#define HWIO_GCC_GPLL2_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002040) +#define HWIO_GCC_GPLL2_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002044) +#define HWIO_GCC_GPLL2_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002044) +#define HWIO_GCC_GPLL2_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002044) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002050) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002050) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002050) +#define HWIO_GCC_GPLL3_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003000) +#define HWIO_GCC_GPLL3_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003000) +#define HWIO_GCC_GPLL3_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003000) +#define HWIO_GCC_GPLL3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003004) +#define HWIO_GCC_GPLL3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003004) +#define HWIO_GCC_GPLL3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003004) +#define HWIO_GCC_GPLL3_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003008) +#define HWIO_GCC_GPLL3_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003008) +#define HWIO_GCC_GPLL3_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003008) +#define HWIO_GCC_GPLL3_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003014) +#define HWIO_GCC_GPLL3_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003014) +#define HWIO_GCC_GPLL3_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003014) +#define HWIO_GCC_GPLL3_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003020) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003020) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003020) +#define HWIO_GCC_GPLL3_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003030) +#define HWIO_GCC_GPLL3_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003030) +#define HWIO_GCC_GPLL3_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003030) +#define HWIO_GCC_GPLL3_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003034) +#define HWIO_GCC_GPLL3_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003034) +#define HWIO_GCC_GPLL3_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003034) +#define HWIO_GCC_GPLL3_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003038) +#define HWIO_GCC_GPLL3_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003038) +#define HWIO_GCC_GPLL3_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003038) +#define HWIO_GCC_GPLL3_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000303c) +#define HWIO_GCC_GPLL3_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000303c) +#define HWIO_GCC_GPLL3_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000303c) +#define HWIO_GCC_GPLL3_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003040) +#define HWIO_GCC_GPLL3_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003040) +#define HWIO_GCC_GPLL3_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003040) +#define HWIO_GCC_GPLL3_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003044) +#define HWIO_GCC_GPLL3_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003044) +#define HWIO_GCC_GPLL3_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003044) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003050) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003050) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003050) +#define HWIO_GCC_GPLL4_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076000) +#define HWIO_GCC_GPLL4_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076000) +#define HWIO_GCC_GPLL4_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076000) +#define HWIO_GCC_GPLL4_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076004) +#define HWIO_GCC_GPLL4_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076004) +#define HWIO_GCC_GPLL4_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076004) +#define HWIO_GCC_GPLL4_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076008) +#define HWIO_GCC_GPLL4_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076008) +#define HWIO_GCC_GPLL4_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076008) +#define HWIO_GCC_GPLL4_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076014) +#define HWIO_GCC_GPLL4_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076014) +#define HWIO_GCC_GPLL4_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076014) +#define HWIO_GCC_GPLL4_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076020) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076020) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076020) +#define HWIO_GCC_GPLL4_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076030) +#define HWIO_GCC_GPLL4_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076030) +#define HWIO_GCC_GPLL4_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076030) +#define HWIO_GCC_GPLL4_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076034) +#define HWIO_GCC_GPLL4_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076034) +#define HWIO_GCC_GPLL4_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076034) +#define HWIO_GCC_GPLL4_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076038) +#define HWIO_GCC_GPLL4_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076038) +#define HWIO_GCC_GPLL4_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076038) +#define HWIO_GCC_GPLL4_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007603c) +#define HWIO_GCC_GPLL4_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007603c) +#define HWIO_GCC_GPLL4_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007603c) +#define HWIO_GCC_GPLL4_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076040) +#define HWIO_GCC_GPLL4_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076040) +#define HWIO_GCC_GPLL4_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076040) +#define HWIO_GCC_GPLL4_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076044) +#define HWIO_GCC_GPLL4_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076044) +#define HWIO_GCC_GPLL4_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076044) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076050) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076050) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076050) +#define HWIO_GCC_GPLL5_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074000) +#define HWIO_GCC_GPLL5_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074000) +#define HWIO_GCC_GPLL5_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074000) +#define HWIO_GCC_GPLL5_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074004) +#define HWIO_GCC_GPLL5_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074004) +#define HWIO_GCC_GPLL5_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074004) +#define HWIO_GCC_GPLL5_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074008) +#define HWIO_GCC_GPLL5_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074008) +#define HWIO_GCC_GPLL5_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074008) +#define HWIO_GCC_GPLL5_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074014) +#define HWIO_GCC_GPLL5_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074014) +#define HWIO_GCC_GPLL5_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074014) +#define HWIO_GCC_GPLL5_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074020) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074020) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074020) +#define HWIO_GCC_GPLL5_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074030) +#define HWIO_GCC_GPLL5_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074030) +#define HWIO_GCC_GPLL5_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074030) +#define HWIO_GCC_GPLL5_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074034) +#define HWIO_GCC_GPLL5_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074034) +#define HWIO_GCC_GPLL5_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074034) +#define HWIO_GCC_GPLL5_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074038) +#define HWIO_GCC_GPLL5_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074038) +#define HWIO_GCC_GPLL5_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074038) +#define HWIO_GCC_GPLL5_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007403c) +#define HWIO_GCC_GPLL5_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007403c) +#define HWIO_GCC_GPLL5_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007403c) +#define HWIO_GCC_GPLL5_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074040) +#define HWIO_GCC_GPLL5_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074040) +#define HWIO_GCC_GPLL5_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074040) +#define HWIO_GCC_GPLL5_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074044) +#define HWIO_GCC_GPLL5_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074044) +#define HWIO_GCC_GPLL5_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074044) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074050) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074050) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074050) +#define HWIO_GCC_GPLL6_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013000) +#define HWIO_GCC_GPLL6_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013000) +#define HWIO_GCC_GPLL6_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013000) +#define HWIO_GCC_GPLL6_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013004) +#define HWIO_GCC_GPLL6_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013004) +#define HWIO_GCC_GPLL6_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013004) +#define HWIO_GCC_GPLL6_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013008) +#define HWIO_GCC_GPLL6_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013008) +#define HWIO_GCC_GPLL6_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013008) +#define HWIO_GCC_GPLL6_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013014) +#define HWIO_GCC_GPLL6_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013014) +#define HWIO_GCC_GPLL6_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013014) +#define HWIO_GCC_GPLL6_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013020) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013020) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013020) +#define HWIO_GCC_GPLL6_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013030) +#define HWIO_GCC_GPLL6_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013030) +#define HWIO_GCC_GPLL6_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013030) +#define HWIO_GCC_GPLL6_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013034) +#define HWIO_GCC_GPLL6_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013034) +#define HWIO_GCC_GPLL6_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013034) +#define HWIO_GCC_GPLL6_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013038) +#define HWIO_GCC_GPLL6_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013038) +#define HWIO_GCC_GPLL6_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013038) +#define HWIO_GCC_GPLL6_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001303c) +#define HWIO_GCC_GPLL6_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001303c) +#define HWIO_GCC_GPLL6_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001303c) +#define HWIO_GCC_GPLL6_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013040) +#define HWIO_GCC_GPLL6_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013040) +#define HWIO_GCC_GPLL6_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013040) +#define HWIO_GCC_GPLL6_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013044) +#define HWIO_GCC_GPLL6_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013044) +#define HWIO_GCC_GPLL6_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013044) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013050) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013050) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013050) +#define HWIO_GCC_GPLL7_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a000) +#define HWIO_GCC_GPLL7_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a000) +#define HWIO_GCC_GPLL7_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a000) +#define HWIO_GCC_GPLL7_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a004) +#define HWIO_GCC_GPLL7_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a004) +#define HWIO_GCC_GPLL7_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a004) +#define HWIO_GCC_GPLL7_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a030) +#define HWIO_GCC_GPLL7_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a030) +#define HWIO_GCC_GPLL7_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a030) +#define HWIO_GCC_GPLL7_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a038) +#define HWIO_GCC_GPLL7_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a038) +#define HWIO_GCC_GPLL7_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a038) +#define HWIO_GCC_GPLL7_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a03c) +#define HWIO_GCC_GPLL7_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a03c) +#define HWIO_GCC_GPLL7_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a03c) +#define HWIO_GCC_GPLL7_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a044) +#define HWIO_GCC_GPLL7_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a044) +#define HWIO_GCC_GPLL7_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a044) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a050) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a050) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a050) +#define HWIO_GCC_GPLL8_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b000) +#define HWIO_GCC_GPLL8_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b000) +#define HWIO_GCC_GPLL8_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b000) +#define HWIO_GCC_GPLL8_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b004) +#define HWIO_GCC_GPLL8_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b004) +#define HWIO_GCC_GPLL8_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b004) +#define HWIO_GCC_GPLL8_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b030) +#define HWIO_GCC_GPLL8_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b030) +#define HWIO_GCC_GPLL8_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b030) +#define HWIO_GCC_GPLL8_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b038) +#define HWIO_GCC_GPLL8_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b038) +#define HWIO_GCC_GPLL8_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b038) +#define HWIO_GCC_GPLL8_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b03c) +#define HWIO_GCC_GPLL8_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b03c) +#define HWIO_GCC_GPLL8_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b03c) +#define HWIO_GCC_GPLL8_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b044) +#define HWIO_GCC_GPLL8_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b044) +#define HWIO_GCC_GPLL8_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b044) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b050) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b050) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b050) +#define HWIO_GCC_GPLL9_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c000) +#define HWIO_GCC_GPLL9_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c000) +#define HWIO_GCC_GPLL9_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c000) +#define HWIO_GCC_GPLL9_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c004) +#define HWIO_GCC_GPLL9_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c004) +#define HWIO_GCC_GPLL9_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c004) +#define HWIO_GCC_GPLL9_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c030) +#define HWIO_GCC_GPLL9_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c030) +#define HWIO_GCC_GPLL9_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c030) +#define HWIO_GCC_GPLL9_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c038) +#define HWIO_GCC_GPLL9_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c038) +#define HWIO_GCC_GPLL9_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c038) +#define HWIO_GCC_GPLL9_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c03c) +#define HWIO_GCC_GPLL9_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c03c) +#define HWIO_GCC_GPLL9_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c03c) +#define HWIO_GCC_GPLL9_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c044) +#define HWIO_GCC_GPLL9_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c044) +#define HWIO_GCC_GPLL9_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c044) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c050) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c050) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c050) +#define HWIO_GCC_GPLL10_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d000) +#define HWIO_GCC_GPLL10_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d000) +#define HWIO_GCC_GPLL10_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d000) +#define HWIO_GCC_GPLL10_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d004) +#define HWIO_GCC_GPLL10_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d004) +#define HWIO_GCC_GPLL10_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d004) +#define HWIO_GCC_GPLL10_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d020) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001d020) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001d020) +#define HWIO_GCC_GPLL10_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d030) +#define HWIO_GCC_GPLL10_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d030) +#define HWIO_GCC_GPLL10_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d030) +#define HWIO_GCC_GPLL10_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d038) +#define HWIO_GCC_GPLL10_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d038) +#define HWIO_GCC_GPLL10_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d038) +#define HWIO_GCC_GPLL10_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d03c) +#define HWIO_GCC_GPLL10_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d03c) +#define HWIO_GCC_GPLL10_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d03c) +#define HWIO_GCC_GPLL10_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d044) +#define HWIO_GCC_GPLL10_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d044) +#define HWIO_GCC_GPLL10_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d044) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d050) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001d050) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001d050) +#define HWIO_GCC_SYSTEM_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004000) +#define HWIO_GCC_SYSTEM_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004000) +#define HWIO_GCC_SYSTEM_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004000) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004004) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004004) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004004) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004060) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004134) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004134) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004134) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000413c) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000413c) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000413c) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004140) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004140) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004140) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004144) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00004144) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00004144) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00004148) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004148) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004148) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004819c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004819c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004819c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004150) +#define HWIO_GCC_SYS_NOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004150) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004150) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041ac) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004280) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00004280) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00004280) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00004288) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004288) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004288) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000428c) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000428c) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000428c) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004290) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004290) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004290) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004294) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004294) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004294) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004298) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004298) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004298) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000042a4) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a4) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000042ac) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042ac) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004308) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004308) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004308) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000043dc) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043dc) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043dc) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000043e0) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e0) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000443c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000443c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000443c) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004510) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004510) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004510) +#define HWIO_GCC_CONFIG_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005000) +#define HWIO_GCC_CONFIG_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005000) +#define HWIO_GCC_CONFIG_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005000) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000500c) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000500c) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000500c) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005014) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005014) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005014) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005018) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005018) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005018) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000501c) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000501c) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000501c) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005020) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005020) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005020) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005024) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005024) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005024) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005028) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005028) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005028) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000502c) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000502c) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000502c) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010078) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005030) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005030) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005030) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005034) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005034) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005034) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005038) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005038) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005038) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000503c) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000503c) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000503c) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005040) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005040) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005040) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005044) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005044) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005044) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005048) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000504c) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000504c) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000504c) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005050) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005050) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005050) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00005054) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005054) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005054) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050b0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050b0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050b0) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000505c) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000505c) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000505c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051dc) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005188) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005188) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005188) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052cc) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052cc) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052cc) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000e000) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000e000) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000e000) +#define HWIO_GCC_IMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008000) +#define HWIO_GCC_IMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008000) +#define HWIO_GCC_IMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008000) +#define HWIO_GCC_IMEM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008004) +#define HWIO_GCC_IMEM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00008004) +#define HWIO_GCC_IMEM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00008004) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00008008) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00008008) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00008008) +#define HWIO_GCC_MMU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083000) +#define HWIO_GCC_MMU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083000) +#define HWIO_GCC_MMU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083000) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083004) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083004) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083004) +#define HWIO_GCC_MMU_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083008) +#define HWIO_GCC_MMU_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083008) +#define HWIO_GCC_MMU_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083008) +#define HWIO_GCC_MMU_TCU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008300c) +#define HWIO_GCC_MMU_TCU_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008300c) +#define HWIO_GCC_MMU_TCU_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008300c) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083068) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008313c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008313c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008313c) +#define HWIO_GCC_ANOC_TBU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00090000) +#define HWIO_GCC_ANOC_TBU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090000) +#define HWIO_GCC_ANOC_TBU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090000) +#define HWIO_GCC_ANOC_TBU_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009000c) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0009000c) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0009000c) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009002c) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0009002c) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0009002c) +#define HWIO_GCC_MMNOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009000) +#define HWIO_GCC_MMNOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009000) +#define HWIO_GCC_MMNOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009000) +#define HWIO_GCC_MMNOC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009004) +#define HWIO_GCC_MMNOC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009004) +#define HWIO_GCC_MMNOC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009004) +#define HWIO_GCC_MMNOC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009024) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009024) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009024) +#define HWIO_GCC_MMNOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009028) +#define HWIO_GCC_MMNOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009028) +#define HWIO_GCC_MMNOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009028) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000902c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000902c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000902c) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009030) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009030) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009030) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009034) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009090) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009090) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009090) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009164) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009164) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009164) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009168) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009168) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009168) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091c4) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009298) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009298) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009298) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000929c) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000929c) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000929c) +#define HWIO_GCC_MMSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b000) +#define HWIO_GCC_MMSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GCC_MMSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GCC_VIDEO_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b004) +#define HWIO_GCC_VIDEO_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b004) +#define HWIO_GCC_VIDEO_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b004) +#define HWIO_GCC_CAMERA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b008) +#define HWIO_GCC_CAMERA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b008) +#define HWIO_GCC_CAMERA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b008) +#define HWIO_GCC_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b00c) +#define HWIO_GCC_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b00c) +#define HWIO_GCC_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b00c) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000b014) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b014) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b014) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b01c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b01c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b01c) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b020) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b020) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b020) +#define HWIO_GCC_VIDEO_AXI0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXI1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXI1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b02c) +#define HWIO_GCC_VIDEO_AXIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b02c) +#define HWIO_GCC_VIDEO_AXIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b02c) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b034) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b034) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b034) +#define HWIO_GCC_DISP_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b038) +#define HWIO_GCC_DISP_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b038) +#define HWIO_GCC_DISP_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b038) +#define HWIO_GCC_DISP_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b03c) +#define HWIO_GCC_DISP_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b03c) +#define HWIO_GCC_DISP_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b03c) +#define HWIO_GCC_VIDEO_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b040) +#define HWIO_GCC_VIDEO_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b040) +#define HWIO_GCC_VIDEO_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b040) +#define HWIO_GCC_CAMERA_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b044) +#define HWIO_GCC_CAMERA_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b044) +#define HWIO_GCC_CAMERA_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b044) +#define HWIO_GCC_DISP_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b048) +#define HWIO_GCC_DISP_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b048) +#define HWIO_GCC_DISP_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b048) +#define HWIO_GCC_MMSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b04c) +#define HWIO_GCC_MMSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b04c) +#define HWIO_GCC_MMSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b04c) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b050) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b050) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b050) +#define HWIO_GCC_MMSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b054) +#define HWIO_GCC_MMSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b054) +#define HWIO_GCC_MMSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b054) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b070) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b070) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b070) +#define HWIO_GCC_PIMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a000) +#define HWIO_GCC_PIMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a000) +#define HWIO_GCC_PIMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a000) +#define HWIO_GCC_PIMEM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000a008) +#define HWIO_GCC_PIMEM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a008) +#define HWIO_GCC_PIMEM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a008) +#define HWIO_GCC_QDSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c000) +#define HWIO_GCC_QDSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c000) +#define HWIO_GCC_QDSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c000) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c004) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c00c) +#define HWIO_GCC_SOUTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c010) +#define HWIO_GCC_SOUTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c010) +#define HWIO_GCC_SOUTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c010) +#define HWIO_GCC_EAST_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c014) +#define HWIO_GCC_EAST_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c014) +#define HWIO_GCC_EAST_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c014) +#define HWIO_GCC_NORTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c018) +#define HWIO_GCC_NORTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c018) +#define HWIO_GCC_NORTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c018) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_STM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c020) +#define HWIO_GCC_QDSS_STM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c020) +#define HWIO_GCC_QDSS_STM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c020) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c024) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000c024) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000c024) +#define HWIO_GCC_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_DAP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c030) +#define HWIO_GCC_QDSS_DAP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c030) +#define HWIO_GCC_QDSS_DAP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c030) +#define HWIO_GCC_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c034) +#define HWIO_GCC_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c034) +#define HWIO_GCC_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c034) +#define HWIO_GCC_QDSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c038) +#define HWIO_GCC_QDSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c038) +#define HWIO_GCC_QDSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c038) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c094) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c040) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c040) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c040) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1c0) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c16c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c16c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c16c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2ec) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c298) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c298) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c298) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c418) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c3c4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c3c4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c3c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c544) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c4f0) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c4f0) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c4f0) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c61c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c61c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c61c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c688) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c634) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c634) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c634) +#define HWIO_GCC_USB30_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f04c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f04c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f04c) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f064) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f064) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f064) +#define HWIO_GCC_USB30_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010000) +#define HWIO_GCC_USB30_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010000) +#define HWIO_GCC_USB30_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010000) +#define HWIO_GCC_USB30_SEC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001000c) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001000c) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001000c) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010010) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010010) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010010) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010014) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010014) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010014) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010018) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010018) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010018) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001004c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001004c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001004c) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010064) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010064) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010064) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050000) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00050004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00050004) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00050008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00050008) +#define HWIO_GCC_USB3_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0005000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0005000c) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050010) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050014) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00012004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00012004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00012004) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a000) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006a004) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006a004) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006a004) +#define HWIO_GCC_SDCC2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014000) +#define HWIO_GCC_SDCC2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014000) +#define HWIO_GCC_SDCC2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014000) +#define HWIO_GCC_SDCC2_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014004) +#define HWIO_GCC_SDCC2_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014004) +#define HWIO_GCC_SDCC2_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014004) +#define HWIO_GCC_SDCC2_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014008) +#define HWIO_GCC_SDCC2_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014008) +#define HWIO_GCC_SDCC2_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014008) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001401c) +#define HWIO_GCC_SDCC2_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001401c) +#define HWIO_GCC_SDCC2_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001401c) +#define HWIO_GCC_SDCC4_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016000) +#define HWIO_GCC_SDCC4_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016000) +#define HWIO_GCC_SDCC4_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016000) +#define HWIO_GCC_SDCC4_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016004) +#define HWIO_GCC_SDCC4_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016004) +#define HWIO_GCC_SDCC4_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016004) +#define HWIO_GCC_SDCC4_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016008) +#define HWIO_GCC_SDCC4_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016008) +#define HWIO_GCC_SDCC4_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016008) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001601c) +#define HWIO_GCC_SDCC4_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001601c) +#define HWIO_GCC_SDCC4_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001601c) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017014) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017014) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017070) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018014) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018014) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018070) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018748) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018748) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018748) +#define HWIO_GCC_PDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033000) +#define HWIO_GCC_PDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033000) +#define HWIO_GCC_PDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033000) +#define HWIO_GCC_PDM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033004) +#define HWIO_GCC_PDM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033004) +#define HWIO_GCC_PDM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033004) +#define HWIO_GCC_PDM_XO4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033008) +#define HWIO_GCC_PDM_XO4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033008) +#define HWIO_GCC_PDM_XO4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033008) +#define HWIO_GCC_PDM2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003300c) +#define HWIO_GCC_PDM2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003300c) +#define HWIO_GCC_PDM2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003300c) +#define HWIO_GCC_PDM2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033010) +#define HWIO_GCC_PDM2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033010) +#define HWIO_GCC_PDM2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033010) +#define HWIO_GCC_PDM2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033014) +#define HWIO_GCC_PDM2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033014) +#define HWIO_GCC_PDM2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033014) +#define HWIO_GCC_PDM_XO4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033028) +#define HWIO_GCC_PDM_XO4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033028) +#define HWIO_GCC_PDM_XO4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033028) +#define HWIO_GCC_PRNG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034000) +#define HWIO_GCC_PRNG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034000) +#define HWIO_GCC_PRNG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034000) +#define HWIO_GCC_PRNG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034004) +#define HWIO_GCC_PRNG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00034004) +#define HWIO_GCC_PRNG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00034004) +#define HWIO_GCC_TSIF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036000) +#define HWIO_GCC_TSIF_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036000) +#define HWIO_GCC_TSIF_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036000) +#define HWIO_GCC_TSIF_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036004) +#define HWIO_GCC_TSIF_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036004) +#define HWIO_GCC_TSIF_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036004) +#define HWIO_GCC_TSIF_REF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036008) +#define HWIO_GCC_TSIF_REF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036008) +#define HWIO_GCC_TSIF_REF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036008) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003600c) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003600c) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003600c) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036018) +#define HWIO_GCC_TSIF_REF_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036018) +#define HWIO_GCC_TSIF_REF_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036018) +#define HWIO_GCC_TSIF_REF_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003601c) +#define HWIO_GCC_TSIF_REF_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003601c) +#define HWIO_GCC_TSIF_REF_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003601c) +#define HWIO_GCC_TSIF_REF_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036020) +#define HWIO_GCC_TSIF_REF_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036020) +#define HWIO_GCC_TSIF_REF_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036020) +#define HWIO_GCC_TCSR_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037000) +#define HWIO_GCC_TCSR_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037000) +#define HWIO_GCC_TCSR_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037000) +#define HWIO_GCC_TCSR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037004) +#define HWIO_GCC_TCSR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00037004) +#define HWIO_GCC_TCSR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00037004) +#define HWIO_GCC_BOOT_ROM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038000) +#define HWIO_GCC_BOOT_ROM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00038000) +#define HWIO_GCC_BOOT_ROM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00038000) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00038004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00038004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00038004) +#define HWIO_GCC_TLMM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a000) +#define HWIO_GCC_TLMM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a000) +#define HWIO_GCC_TLMM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a000) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a004) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a004) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a004) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a008) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a008) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a008) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a010) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a010) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a010) +#define HWIO_GCC_TLMM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a014) +#define HWIO_GCC_TLMM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a014) +#define HWIO_GCC_TLMM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a014) +#define HWIO_GCC_AOSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c000) +#define HWIO_GCC_AOSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003c000) +#define HWIO_GCC_AOSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003c000) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003c004) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003c004) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003c004) +#define HWIO_GCC_AOSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c008) +#define HWIO_GCC_AOSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003c008) +#define HWIO_GCC_AOSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003c008) +#define HWIO_GCC_SEC_CTRL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003d014) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d014) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d014) +#define HWIO_GCC_ACC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d018) +#define HWIO_GCC_ACC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d018) +#define HWIO_GCC_ACC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d018) +#define HWIO_GCC_ACC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d01c) +#define HWIO_GCC_ACC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d01c) +#define HWIO_GCC_ACC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d01c) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d034) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d034) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d034) +#define HWIO_GCC_SPDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040000) +#define HWIO_GCC_SPDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040000) +#define HWIO_GCC_SPDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040000) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040004) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040008) +#define HWIO_GCC_SPDM_FF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004000c) +#define HWIO_GCC_SPDM_FF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004000c) +#define HWIO_GCC_SPDM_FF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004000c) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040010) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040014) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040018) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004001c) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004001c) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004001c) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040020) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00040020) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00040020) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040024) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040024) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040024) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040028) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040028) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040028) +#define HWIO_GCC_CE1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041000) +#define HWIO_GCC_CE1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041000) +#define HWIO_GCC_CE1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041000) +#define HWIO_GCC_CE1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041004) +#define HWIO_GCC_CE1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041004) +#define HWIO_GCC_CE1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041004) +#define HWIO_GCC_CE1_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041008) +#define HWIO_GCC_CE1_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041008) +#define HWIO_GCC_CE1_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041008) +#define HWIO_GCC_CE1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004100c) +#define HWIO_GCC_CE1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004100c) +#define HWIO_GCC_CE1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004100c) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041068) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041068) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041068) +#define HWIO_GCC_CE1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041010) +#define HWIO_GCC_CE1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041010) +#define HWIO_GCC_CE1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041010) +#define HWIO_GCC_CE1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041014) +#define HWIO_GCC_CE1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041014) +#define HWIO_GCC_CE1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041014) +#define HWIO_GCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043000) +#define HWIO_GCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043000) +#define HWIO_GCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043000) +#define HWIO_GCC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043004) +#define HWIO_GCC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043004) +#define HWIO_GCC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043004) +#define HWIO_GCC_XO_DIV4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043008) +#define HWIO_GCC_XO_DIV4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043008) +#define HWIO_GCC_XO_DIV4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043008) +#define HWIO_GCC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004300c) +#define HWIO_GCC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004300c) +#define HWIO_GCC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004300c) +#define HWIO_GCC_XO_DIV4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043010) +#define HWIO_GCC_XO_DIV4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043010) +#define HWIO_GCC_XO_DIV4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043010) +#define HWIO_GCC_SLEEP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00043018) +#define HWIO_GCC_SLEEP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043018) +#define HWIO_GCC_SLEEP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043018) +#define HWIO_GCC_XO_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004302c) +#define HWIO_GCC_XO_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004302c) +#define HWIO_GCC_XO_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004302c) +#define HWIO_GCC_XO_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043030) +#define HWIO_GCC_XO_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043030) +#define HWIO_GCC_XO_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043030) +#define HWIO_GCC_DDRSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044000) +#define HWIO_GCC_DDRSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044000) +#define HWIO_GCC_DDRSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044000) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000092a4) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000092a4) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000092a4) +#define HWIO_GCC_DDRSS_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045158) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00045158) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00045158) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a154) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008a154) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008a154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071154) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d04c) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d04c) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d04c) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004400c) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004400c) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004400c) +#define HWIO_GCC_DDRSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044010) +#define HWIO_GCC_DDRSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044010) +#define HWIO_GCC_DDRSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044010) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044014) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044018) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044018) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044018) +#define HWIO_GCC_MEMNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004401c) +#define HWIO_GCC_MEMNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004401c) +#define HWIO_GCC_MEMNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004401c) +#define HWIO_GCC_DDRSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044020) +#define HWIO_GCC_DDRSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044020) +#define HWIO_GCC_DDRSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044020) +#define HWIO_GCC_DDRSS_DRE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044024) +#define HWIO_GCC_DDRSS_DRE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044024) +#define HWIO_GCC_DDRSS_DRE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044024) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044080) +#define HWIO_GCC_MEMNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004402c) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441ac) +#define HWIO_GCC_SHRM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044154) +#define HWIO_GCC_SHRM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044154) +#define HWIO_GCC_SHRM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044154) +#define HWIO_GCC_SHRM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044158) +#define HWIO_GCC_SHRM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044158) +#define HWIO_GCC_SHRM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044158) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044280) +#define HWIO_GCC_DCNOC_CFG_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044284) +#define HWIO_GCC_DCNOC_CFG_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044284) +#define HWIO_GCC_DCNOC_CFG_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044284) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044288) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00044288) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00044288) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004428c) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004428c) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004428c) +#define HWIO_GCC_SHRM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044290) +#define HWIO_GCC_SHRM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044290) +#define HWIO_GCC_SHRM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044290) +#define HWIO_GCC_DNOC_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044294) +#define HWIO_GCC_DNOC_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044294) +#define HWIO_GCC_DNOC_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044294) +#define HWIO_GCC_DDR_I_HCLK_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044298) +#define HWIO_GCC_DDR_I_HCLK_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044298) +#define HWIO_GCC_DDR_I_HCLK_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044298) +#define HWIO_GCC_DDRMC_CH0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a0) +#define HWIO_GCC_DDRMC_CH1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000442a0) +#define HWIO_GCC_DDRMC_CH1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000442a0) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442fc) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443d0) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d0) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d0) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004442c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004442c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004442c) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044500) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044500) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044500) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047000) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047000) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047000) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047004) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00047004) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00047004) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00047008) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047008) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047008) +#define HWIO_GCC_LPASS_SWAY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004700c) +#define HWIO_GCC_LPASS_SWAY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004700c) +#define HWIO_GCC_LPASS_SWAY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004700c) +#define HWIO_GCC_LPASS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047010) +#define HWIO_GCC_LPASS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047010) +#define HWIO_GCC_LPASS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047010) +#define HWIO_GCC_LPASS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047014) +#define HWIO_GCC_LPASS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047014) +#define HWIO_GCC_LPASS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047014) +#define HWIO_GCC_TURING_TBU0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004500c) +#define HWIO_GCC_TURING_TBU1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004500c) +#define HWIO_GCC_TURING_TBU1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004500c) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045010) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045010) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045010) +#define HWIO_GCC_TURING_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045014) +#define HWIO_GCC_TURING_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045014) +#define HWIO_GCC_TURING_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045014) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045018) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045018) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045018) +#define HWIO_GCC_TURING_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004501c) +#define HWIO_GCC_TURING_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004501c) +#define HWIO_GCC_TURING_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004501c) +#define HWIO_GCC_TURING_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045020) +#define HWIO_GCC_TURING_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045020) +#define HWIO_GCC_TURING_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045020) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004507c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004507c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004507c) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045150) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045150) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045150) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045154) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00045154) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00045154) +#define HWIO_GCC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048000) +#define HWIO_GCC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048000) +#define HWIO_GCC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048000) +#define HWIO_GCC_CPUSS_GNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048004) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048008) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048008) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048008) +#define HWIO_GCC_CPUSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00048010) +#define HWIO_GCC_CPUSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048010) +#define HWIO_GCC_CPUSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048010) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004802c) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004802c) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004802c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048088) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048088) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048088) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048034) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048034) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048034) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048160) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048160) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048160) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048178) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048178) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048178) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004818c) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004818c) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004818c) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048190) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048190) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048190) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048194) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048194) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048194) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048198) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048198) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048198) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004900c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004900c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004900c) +#define HWIO_GCC_APB2JTAG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004c000) +#define HWIO_GCC_APB2JTAG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004c000) +#define HWIO_GCC_APB2JTAG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004c000) +#define HWIO_GCC_RBCPR_CX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_MX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f010) +#define HWIO_GCC_DEBUG_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062004) +#define HWIO_GCC_DEBUG_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062004) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062004) +#define HWIO_GCC_DEBUG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062008) +#define HWIO_GCC_DEBUG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062008) +#define HWIO_GCC_DEBUG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062008) +#define HWIO_GCC_GP1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064000) +#define HWIO_GCC_GP1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064000) +#define HWIO_GCC_GP1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064000) +#define HWIO_GCC_GP1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064004) +#define HWIO_GCC_GP1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00064004) +#define HWIO_GCC_GP1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00064004) +#define HWIO_GCC_GP1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064008) +#define HWIO_GCC_GP1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00064008) +#define HWIO_GCC_GP1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00064008) +#define HWIO_GCC_GP1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006400c) +#define HWIO_GCC_GP1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006400c) +#define HWIO_GCC_GP1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006400c) +#define HWIO_GCC_GP1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064010) +#define HWIO_GCC_GP1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064010) +#define HWIO_GCC_GP1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064010) +#define HWIO_GCC_GP1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064014) +#define HWIO_GCC_GP1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064014) +#define HWIO_GCC_GP1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064014) +#define HWIO_GCC_GP2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065000) +#define HWIO_GCC_GP2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065000) +#define HWIO_GCC_GP2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065000) +#define HWIO_GCC_GP2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065004) +#define HWIO_GCC_GP2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00065004) +#define HWIO_GCC_GP2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00065004) +#define HWIO_GCC_GP2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065008) +#define HWIO_GCC_GP2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00065008) +#define HWIO_GCC_GP2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00065008) +#define HWIO_GCC_GP2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006500c) +#define HWIO_GCC_GP2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006500c) +#define HWIO_GCC_GP2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006500c) +#define HWIO_GCC_GP2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065010) +#define HWIO_GCC_GP2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065010) +#define HWIO_GCC_GP2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065010) +#define HWIO_GCC_GP2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065014) +#define HWIO_GCC_GP2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065014) +#define HWIO_GCC_GP2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065014) +#define HWIO_GCC_GP3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066000) +#define HWIO_GCC_GP3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066000) +#define HWIO_GCC_GP3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066000) +#define HWIO_GCC_GP3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066004) +#define HWIO_GCC_GP3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00066004) +#define HWIO_GCC_GP3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00066004) +#define HWIO_GCC_GP3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066008) +#define HWIO_GCC_GP3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00066008) +#define HWIO_GCC_GP3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00066008) +#define HWIO_GCC_GP3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006600c) +#define HWIO_GCC_GP3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006600c) +#define HWIO_GCC_GP3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006600c) +#define HWIO_GCC_GP3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066010) +#define HWIO_GCC_GP3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066010) +#define HWIO_GCC_GP3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066010) +#define HWIO_GCC_GP3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066014) +#define HWIO_GCC_GP3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066014) +#define HWIO_GCC_GP3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066014) +#define HWIO_GCC_PCIE_0_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b000) +#define HWIO_GCC_PCIE_0_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b000) +#define HWIO_GCC_PCIE_0_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b000) +#define HWIO_GCC_PCIE_0_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b004) +#define HWIO_GCC_PCIE_0_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b004) +#define HWIO_GCC_PCIE_0_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b004) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b018) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006b018) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006b018) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b03c) +#define HWIO_GCC_PCIE_0_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b03c) +#define HWIO_GCC_PCIE_0_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b03c) +#define HWIO_GCC_PCIE_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d000) +#define HWIO_GCC_PCIE_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d000) +#define HWIO_GCC_PCIE_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d000) +#define HWIO_GCC_PCIE_1_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d004) +#define HWIO_GCC_PCIE_1_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d004) +#define HWIO_GCC_PCIE_1_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d004) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d018) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008d018) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008d018) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d03c) +#define HWIO_GCC_PCIE_1_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d03c) +#define HWIO_GCC_PCIE_1_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d03c) +#define HWIO_GCC_PCIE_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f018) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006f018) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006f018) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f02c) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f02c) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f02c) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f030) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f030) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f030) +#define HWIO_GCC_UFS_CARD_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075000) +#define HWIO_GCC_UFS_CARD_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075000) +#define HWIO_GCC_UFS_CARD_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075000) +#define HWIO_GCC_UFS_CARD_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075018) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075018) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075018) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007501c) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007501c) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007501c) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075030) +#define HWIO_GCC_UFS_CARD_AXI_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075030) +#define HWIO_GCC_UFS_CARD_AXI_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075030) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007504c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007504c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007504c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075058) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075058) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075058) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075064) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075064) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075064) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007507c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007507c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007507c) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075098) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075098) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075098) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000750ac) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750ac) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750ac) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b4) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b4) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b4) +#define HWIO_GCC_UFS_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077000) +#define HWIO_GCC_UFS_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077000) +#define HWIO_GCC_UFS_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077000) +#define HWIO_GCC_UFS_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077004) +#define HWIO_GCC_UFS_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077004) +#define HWIO_GCC_UFS_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077004) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077018) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077018) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077018) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007701c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007701c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007701c) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077030) +#define HWIO_GCC_UFS_PHY_AXI_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077030) +#define HWIO_GCC_UFS_PHY_AXI_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077030) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007704c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007704c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007704c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077058) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077058) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077058) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00077064) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077064) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077064) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007707c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007707c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007707c) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077098) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077098) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077098) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770ac) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770ac) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770ac) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b4) +#define HWIO_GCC_SSC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063000) +#define HWIO_GCC_SSC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063000) +#define HWIO_GCC_SSC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063000) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00063004) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063004) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063004) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00063008) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063008) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063008) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00063010) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063010) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063010) +#define HWIO_GCC_SSC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063014) +#define HWIO_GCC_SSC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063014) +#define HWIO_GCC_SSC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063014) +#define HWIO_GCC_VS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a000) +#define HWIO_GCC_VS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a000) +#define HWIO_GCC_VS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a000) +#define HWIO_GCC_VDDCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a004) +#define HWIO_GCC_VDDCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a004) +#define HWIO_GCC_VDDCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a004) +#define HWIO_GCC_VDDMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a008) +#define HWIO_GCC_VDDMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a008) +#define HWIO_GCC_VDDMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a008) +#define HWIO_GCC_VDDA_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a00c) +#define HWIO_GCC_VDDA_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a00c) +#define HWIO_GCC_VDDA_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a00c) +#define HWIO_GCC_VS_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a010) +#define HWIO_GCC_VS_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a010) +#define HWIO_GCC_VS_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a010) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a014) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a014) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a014) +#define HWIO_GCC_VSENSOR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a01c) +#define HWIO_GCC_VSENSOR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a01c) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a01c) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a034) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a034) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a034) +#define HWIO_GCC_MSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a048) +#define HWIO_GCC_MSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a048) +#define HWIO_GCC_MSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a048) +#define HWIO_GCC_GPU_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a04c) +#define HWIO_GCC_GPU_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a04c) +#define HWIO_GCC_GPU_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a04c) +#define HWIO_GCC_APC_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a050) +#define HWIO_GCC_APC_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a050) +#define HWIO_GCC_APC_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a050) +#define HWIO_GCC_VDDMMCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a054) +#define HWIO_GCC_VDDMMCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a054) +#define HWIO_GCC_VDDMMCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a054) +#define HWIO_GCC_WCSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a058) +#define HWIO_GCC_WCSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a058) +#define HWIO_GCC_WCSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a058) +#define HWIO_GCC_VDDMMMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a05c) +#define HWIO_GCC_VDDMMMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a05c) +#define HWIO_GCC_VDDMMMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a05c) +#define HWIO_GCC_AGGRE_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008200c) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008200c) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008200c) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082010) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082038) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082038) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082038) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001007c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001007c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001007c) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000750c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750c0) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d148) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d148) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d148) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082094) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082040) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082040) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082040) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821c0) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008216c) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008216c) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008216c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822ec) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822ec) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822ec) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082434) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082434) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082434) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008250c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008250c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008250c) +#define HWIO_GCC_DCC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084000) +#define HWIO_GCC_DCC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084000) +#define HWIO_GCC_DCC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084000) +#define HWIO_GCC_DCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084004) +#define HWIO_GCC_DCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00084004) +#define HWIO_GCC_DCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00084004) +#define HWIO_GCC_IPA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089000) +#define HWIO_GCC_IPA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089000) +#define HWIO_GCC_IPA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089000) +#define HWIO_GCC_IPA_BCR_RMSK 0x1 +#define HWIO_GCC_IPA_BCR_ATTR 0x3 +#define HWIO_GCC_IPA_BCR_IN in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, \ + HWIO_GCC_IPA_BCR_RMSK) +#define HWIO_GCC_IPA_BCR_INM(m) in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, m) +#define HWIO_GCC_IPA_BCR_OUT(v) out_dword(HWIO_GCC_IPA_BCR_ADDR, v) +#define HWIO_GCC_IPA_BCR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GCC_IPA_BCR_ADDR, \ + m, \ + v, \ + HWIO_GCC_IPA_BCR_IN) +#define HWIO_GCC_IPA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IPA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089004) +#define HWIO_GCC_IPA_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089004) +#define HWIO_GCC_IPA_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089004) +#define HWIO_GCC_IPA_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089008) +#define HWIO_GCC_IPA_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089008) +#define HWIO_GCC_IPA_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089008) +#define HWIO_GCC_IPA_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008900c) +#define HWIO_GCC_IPA_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089010) +#define HWIO_GCC_IPA_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089010) +#define HWIO_GCC_IPA_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089010) +#define HWIO_GCC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089014) +#define HWIO_GCC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089014) +#define HWIO_GCC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089014) +#define HWIO_GCC_IPA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089018) +#define HWIO_GCC_IPA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089018) +#define HWIO_GCC_IPA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089018) +#define HWIO_GCC_IPA_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008901c) +#define HWIO_GCC_IPA_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008901c) +#define HWIO_GCC_IPA_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008901c) +#define HWIO_GCC_IPA_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089020) +#define HWIO_GCC_IPA_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089020) +#define HWIO_GCC_IPA_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089020) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008907c) +#define HWIO_GCC_IPA_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089150) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00089150) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00089150) +#define HWIO_GCC_IPA_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089154) +#define HWIO_GCC_IPA_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089154) +#define HWIO_GCC_IPA_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089154) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a000) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a004) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a004) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a004) +#define HWIO_GCC_MSS_AXIS2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a008) +#define HWIO_GCC_MSS_AXIS2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a008) +#define HWIO_GCC_MSS_AXIS2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a008) +#define HWIO_GCC_MSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a00c) +#define HWIO_GCC_MSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a00c) +#define HWIO_GCC_MSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a00c) +#define HWIO_GCC_MSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a010) +#define HWIO_GCC_MSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a010) +#define HWIO_GCC_MSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a010) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a014) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a070) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a144) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a144) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a144) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a14c) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a14c) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a14c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a150) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a150) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a150) +#define HWIO_GCC_GLM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b000) +#define HWIO_GCC_GLM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b000) +#define HWIO_GCC_GLM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b000) +#define HWIO_GCC_GLM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b004) +#define HWIO_GCC_GLM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b004) +#define HWIO_GCC_GLM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b004) +#define HWIO_GCC_GLM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b008) +#define HWIO_GCC_GLM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b008) +#define HWIO_GCC_GLM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b008) +#define HWIO_GCC_GLM_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b00c) +#define HWIO_GCC_GLM_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b00c) +#define HWIO_GCC_GLM_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b00c) +#define HWIO_GCC_GLM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b010) +#define HWIO_GCC_GLM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b010) +#define HWIO_GCC_GLM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b010) +#define HWIO_GCC_GLM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b014) +#define HWIO_GCC_GLM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b014) +#define HWIO_GCC_GLM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b014) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00088004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00088004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00088004) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011000) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011000) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011000) +#define HWIO_GCC_WCSS_AXI_M_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011004) +#define HWIO_GCC_WCSS_AXI_M_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011004) +#define HWIO_GCC_WCSS_AXI_M_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011004) +#define HWIO_GCC_WCSS_ECAHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011008) +#define HWIO_GCC_WCSS_ECAHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011008) +#define HWIO_GCC_WCSS_ECAHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011008) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001100c) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001100c) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001100c) +#define HWIO_GCC_WCSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011010) +#define HWIO_GCC_WCSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011010) +#define HWIO_GCC_WCSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011010) +#define HWIO_GCC_WCSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011014) +#define HWIO_GCC_WCSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011014) +#define HWIO_GCC_WCSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011014) +#define HWIO_GCC_GPU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071000) +#define HWIO_GCC_GPU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071000) +#define HWIO_GCC_GPU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071000) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071004) +#define HWIO_GCC_GPU_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071008) +#define HWIO_GCC_GPU_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071008) +#define HWIO_GCC_GPU_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071008) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071010) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00071010) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00071010) +#define HWIO_GCC_GPU_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071014) +#define HWIO_GCC_GPU_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071014) +#define HWIO_GCC_GPU_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071014) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00071018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00071018) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071074) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071148) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007114c) +#define HWIO_GCC_GPU_TRIG_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071150) +#define HWIO_GCC_GPU_TRIG_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071150) +#define HWIO_GCC_GPU_TRIG_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071150) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00072000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00072000) +#define HWIO_GCC_SP_SCR_NIU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072004) +#define HWIO_GCC_SP_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072008) +#define HWIO_GCC_SP_SCSR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007200c) +#define HWIO_GCC_SP_SCSR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007200c) +#define HWIO_GCC_SP_SCSR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007200c) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072010) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072010) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072010) +#define HWIO_GCC_SP_GPKT_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072014) +#define HWIO_GCC_SP_GPKT_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072014) +#define HWIO_GCC_SP_GPKT_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072014) +#define HWIO_GCC_SP_RSSC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072018) +#define HWIO_GCC_SP_RSSC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072018) +#define HWIO_GCC_SP_RSSC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072018) +#define HWIO_GCC_SP_ARI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007201c) +#define HWIO_GCC_SP_ARI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007201c) +#define HWIO_GCC_SP_ARI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007201c) +#define HWIO_GCC_SP_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072020) +#define HWIO_GCC_SP_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072020) +#define HWIO_GCC_SP_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072020) +#define HWIO_GCC_SP_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072024) +#define HWIO_GCC_SP_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072024) +#define HWIO_GCC_SP_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072024) +#define HWIO_GCC_NAV_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015000) +#define HWIO_GCC_NAV_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015000) +#define HWIO_GCC_NAV_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015000) +#define HWIO_GCC_NAV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015004) +#define HWIO_GCC_NAV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00015004) +#define HWIO_GCC_NAV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00015004) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00007004) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00007004) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00007004) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00024004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00024004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00024004) +#define HWIO_GCC_QSPI_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024008) +#define HWIO_GCC_QSPI_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024008) +#define HWIO_GCC_QSPI_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024008) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004b000) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b000) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b000) +#define HWIO_GCC_QSPI_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b00c) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b00c) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b00c) +#define HWIO_GCC_NPU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d000) +#define HWIO_GCC_NPU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d000) +#define HWIO_GCC_NPU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d000) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d004) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d004) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d004) +#define HWIO_GCC_NPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d008) +#define HWIO_GCC_NPU_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d008) +#define HWIO_GCC_NPU_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d008) +#define HWIO_GCC_NPU_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d00c) +#define HWIO_GCC_NPU_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d00c) +#define HWIO_GCC_NPU_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d00c) +#define HWIO_GCC_NPU_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d010) +#define HWIO_GCC_NPU_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d010) +#define HWIO_GCC_NPU_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d010) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d06c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d06c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d06c) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d140) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0004d140) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0004d140) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d144) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d144) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d144) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e070) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e748) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e748) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e748) +#define HWIO_GCC_RBCPR_MMCX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d010) +#define HWIO_GCC_EMAC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006000) +#define HWIO_GCC_EMAC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006000) +#define HWIO_GCC_EMAC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006000) +#define HWIO_GCC_EMAC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006004) +#define HWIO_GCC_EMAC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006004) +#define HWIO_GCC_EMAC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006004) +#define HWIO_GCC_EMAC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000600c) +#define HWIO_GCC_EMAC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000600c) +#define HWIO_GCC_EMAC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000600c) +#define HWIO_GCC_EMAC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006010) +#define HWIO_GCC_EMAC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006010) +#define HWIO_GCC_EMAC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006010) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006014) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006014) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006014) +#define HWIO_GCC_EMAC_RGMII_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000602c) +#define HWIO_GCC_EMAC_RGMII_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000602c) +#define HWIO_GCC_EMAC_RGMII_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000602c) +#define HWIO_GCC_EMAC_PTP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000603c) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000603c) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000603c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000f9c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000f9c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000f9c) +#define HWIO_GCC_TZ_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b000) +#define HWIO_GCC_TZ_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b000) +#define HWIO_GCC_TZ_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b000) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b004) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b004) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b004) +#define HWIO_GCC_TZ_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b008) +#define HWIO_GCC_TZ_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b008) +#define HWIO_GCC_TZ_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b008) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b00c) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003b00c) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003b00c) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b010) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b010) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b010) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b014) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b014) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b014) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b01c) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b01c) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b01c) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b020) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b020) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b020) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b024) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b024) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b024) +#define HWIO_GCC_MSS_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e000) +#define HWIO_GCC_MSS_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e000) +#define HWIO_GCC_MSS_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e000) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e004) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e004) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e004) +#define HWIO_GCC_MSS_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e008) +#define HWIO_GCC_MSS_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e008) +#define HWIO_GCC_MSS_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e008) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e00c) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003e00c) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003e00c) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e010) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e010) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e010) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e014) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e014) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e014) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e01c) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e01c) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e01c) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e020) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003e020) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003e020) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e024) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e024) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e024) +#define HWIO_GCC_SP_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f000) +#define HWIO_GCC_SP_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f000) +#define HWIO_GCC_SP_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f000) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f004) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f004) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f004) +#define HWIO_GCC_SP_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f008) +#define HWIO_GCC_SP_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f008) +#define HWIO_GCC_SP_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f008) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003f00c) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f010) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f014) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f014) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f014) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f01c) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f020) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f020) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f020) +#define HWIO_GCC_SP_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f024) +#define HWIO_GCC_SP_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f024) +#define HWIO_GCC_SP_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f024) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b0) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b0) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b0) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f05c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f05c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f05c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001005c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001005c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001005c) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b028) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b028) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d028) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075040) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075044) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075044) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075044) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075050) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075054) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075054) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075054) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b8) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000750bc) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750bc) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750bc) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077040) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077044) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077044) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077044) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077050) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077054) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077054) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077054) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b8) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770bc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770bc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770bc) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a148) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a148) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a148) +#define HWIO_GCC_ACC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e030) +#define HWIO_GCC_ACC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e030) +#define HWIO_GCC_ACC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e030) +#define HWIO_GCC_CPUSS_AHB_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048024) +#define HWIO_GCC_CPUSS_AHB_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048024) +#define HWIO_GCC_CPUSS_AHB_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048024) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054000) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00054000) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00054000) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054018) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054018) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054018) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00051000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00051000) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051018) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051018) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051018) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00052000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00052000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00052000) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052018) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052018) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052018) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00053000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00053000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00053000) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053018) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053018) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053018) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00055000) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055000) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055000) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055018) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055018) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055018) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00056000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00056000) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056018) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056018) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056018) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00057000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00057000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00057000) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057018) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057018) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057018) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005a000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0005a000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0005a000) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a018) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a018) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a018) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005b000) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b000) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b000) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b018) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b018) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b018) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00069000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00069000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00069000) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069018) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069018) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069018) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00035000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00035000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00035000) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035018) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035018) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035018) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006c014) +#define HWIO_GCC_PCIE_0_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c020) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0006c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c028) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_COM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f010) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008e014) +#define HWIO_GCC_PCIE_1_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e020) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008e000) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e000) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e000) +#define HWIO_GCC_SSC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063020) +#define HWIO_GCC_SSC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063020) +#define HWIO_GCC_SSC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063020) +#define HWIO_GCC_DEBUG_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062000) +#define HWIO_GCC_DEBUG_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062000) +#define HWIO_GCC_DEBUG_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062000) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006200c) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006200c) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006200c) +#define HWIO_GCC_PLL_RESET_N_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062018) +#define HWIO_GCC_PLL_RESET_N_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062018) +#define HWIO_GCC_PLL_RESET_N_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062018) +#define HWIO_GCC_PLL_STATUS_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006201c) +#define HWIO_GCC_PLL_STATUS_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006201c) +#define HWIO_GCC_PLL_STATUS_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006201c) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062020) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062020) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062020) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00062030) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062030) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062030) +#define HWIO_GCC_PLLTEST_PAD_CFG_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062034) +#define HWIO_GCC_PLLTEST_PAD_CFG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062034) +#define HWIO_GCC_PLLTEST_PAD_CFG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062034) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006203c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006203c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006203c) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00078040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00078040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00078040) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00067000) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067000) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067000) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00067020) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067020) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067020) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00068000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00068000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00068000) +#define HWIO_GCC_VTT_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007300c) +#define HWIO_GCC_VTT_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007300c) +#define HWIO_GCC_VTT_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007300c) +#define HWIO_GCC_VREF_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073010) +#define HWIO_GCC_VREF_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00073010) +#define HWIO_GCC_VREF_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00073010) +#define HWIO_GCC_PVC_DATA_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073014) +#define HWIO_GCC_PVC_DATA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073014) +#define HWIO_GCC_PVC_DATA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073014) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00078030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00078030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00078030) +#define HWIO_GCC_WCSS_PD_CLK_DIS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011104) +#define HWIO_GCC_SPARE0_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d000) +#define HWIO_GCC_SPARE0_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006d000) +#define HWIO_GCC_SPARE0_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006d000) +#define HWIO_GCC_SPARE1_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e000) +#define HWIO_GCC_SPARE1_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006e000) +#define HWIO_GCC_SPARE1_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006e000) +#define HWIO_GCC_SPARE2_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081000) +#define HWIO_GCC_SPARE2_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00081000) +#define HWIO_GCC_SPARE2_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00081000) +#define HWIO_GCC_SPARE3_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042000) +#define HWIO_GCC_SPARE3_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00042000) +#define HWIO_GCC_SPARE3_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00042000) +#define HWIO_GCC_SPARE4_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039000) +#define HWIO_GCC_SPARE4_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00039000) +#define HWIO_GCC_SPARE4_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00039000) +#define HWIO_GCC_SPARE5_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032000) +#define HWIO_GCC_SPARE5_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00032000) +#define HWIO_GCC_SPARE5_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00032000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007f000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007f000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007f000) +#define HWIO_GCC_TSIF_0_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036024) +#define HWIO_GCC_TSIF_0_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036024) +#define HWIO_GCC_TSIF_0_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036024) +#define HWIO_GCC_TSIF_1_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036028) +#define HWIO_GCC_TSIF_1_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036028) +#define HWIO_GCC_TSIF_1_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036028) +#define HWIO_GCC_NPU_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d110) +#define HWIO_GCC_NPU_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d110) +#define HWIO_GCC_NPU_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d110) +#define HWIO_GCC_GPU_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071028) +#define HWIO_GCC_GPU_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071028) +#define HWIO_GCC_GPU_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071028) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007b068) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c068) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d068) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e068) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c000) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c000) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c000) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c004) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c004) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c004) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c008) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c008) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c008) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c028) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c028) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c028) +#define HWIO_GCC_PCIE_0_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_0_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_0_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c02c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c02c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c02c) +#define HWIO_GCC_GPU_IREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c010) +#define HWIO_GCC_GPU_IREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c010) +#define HWIO_GCC_GPU_IREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c010) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c014) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c014) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c014) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c018) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c018) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c018) +#define HWIO_GCC_RX3_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c01c) +#define HWIO_GCC_RX3_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c01c) +#define HWIO_GCC_RX3_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c01c) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c020) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c020) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c020) +#define HWIO_GCC_CLKREF_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c024) +#define HWIO_GCC_CLKREF_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c024) +#define HWIO_GCC_CLKREF_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c024) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009160) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009160) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009160) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009464) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009464) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009464) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009474) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009474) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009474) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008267c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008267c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008267c) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082680) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082680) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082680) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082690) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082690) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082690) +#define HWIO_GCC_MSS_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a024) +#define HWIO_GCC_MSS_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a024) +#define HWIO_GCC_MSS_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a024) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00086000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00086000) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086010) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008601c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008601c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008601c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086024) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086024) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086024) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086028) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008603c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008604c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086058) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086058) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086058) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086060) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086060) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086060) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086064) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00086068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00086068) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00087000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00087000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00087000) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087010) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087024) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087024) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087024) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00087028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087028) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087058) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087058) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087058) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087060) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087060) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087060) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00087064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087064) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00087068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00087068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00087068) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019068) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051024) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00051024) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00051024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00035024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00052024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00053024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00054024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00054024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00056024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00056024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005a024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00069024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069024) +#define HWIO_GCC_JBIST_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080000) +#define HWIO_GCC_JBIST_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080000) +#define HWIO_GCC_JBIST_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080000) +#define HWIO_GCC_JBIST_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080004) +#define HWIO_GCC_JBIST_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080004) +#define HWIO_GCC_JBIST_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080004) +#define HWIO_GCC_JBIST_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008000c) +#define HWIO_GCC_JBIST_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008000c) +#define HWIO_GCC_JBIST_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008000c) +#define HWIO_GCC_JBIST_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080010) +#define HWIO_GCC_JBIST_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080010) +#define HWIO_GCC_JBIST_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080010) +#define HWIO_GCC_JBIST_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080014) +#define HWIO_GCC_JBIST_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080014) +#define HWIO_GCC_JBIST_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080014) +#define HWIO_GCC_JBIST_MEAS_DONE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080018) +#define HWIO_GCC_JBIST_MEAS_DONE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080018) +#define HWIO_GCC_JBIST_MEAS_DONE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080018) +#define HWIO_GCC_GLOBAL_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f000) +#define HWIO_GCC_GLOBAL_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008f000) +#define HWIO_GCC_GLOBAL_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008f000) +#define HWIO_GCC_CAM_CC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006100) +#define HWIO_GCC_CAM_CC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006100) +#define HWIO_GCC_CAM_CC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006100) +#define HWIO_GCC_WCSS_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011100) +#define HWIO_GCC_WCSS_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011100) +#define HWIO_GCC_WCSS_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000104) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000104) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000104) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000010c) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000010c) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000010c) +#define HWIO_GCC_PLL0_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000114) +#define HWIO_GCC_PLL0_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000114) +#define HWIO_GCC_PLL0_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000114) +#define HWIO_GCC_PLL1_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001114) +#define HWIO_GCC_PLL1_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001114) +#define HWIO_GCC_PLL1_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001114) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009103c) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092040) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b040) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c040) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095040) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095040) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095040) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096040) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044530) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044530) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044530) +#define HWIO_GCC_EMAC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006040) +#define HWIO_GCC_EMAC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006040) +#define HWIO_GCC_EMAC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006040) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio_def.h new file mode 100644 index 000000000000..11987afcded5 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_gcc_hwio_def.h @@ -0,0 +1,29 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_GCC_HWIO_DEF_H_) +#define _IPA_GCC_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +struct ipa_gcc_hwio_def_gcc_ipa_bcr_s { + u32 blk_ares : 1; + u32 reserved0 : 31; +}; +union ipa_gcc_hwio_def_gcc_ipa_bcr_u { + struct ipa_gcc_hwio_def_gcc_ipa_bcr_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h new file mode 100644 index 000000000000..5a84940b1cda --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h @@ -0,0 +1,472 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HW_COMMON_EX_H_) +#define _IPA_HW_COMMON_EX_H_ + +/* VLVL defs are available for 854 */ +#define FEATURE_VLVL_DEFS true + +/* IPAv4 version flag for Sdx24 */ +#define FEATURE_IPA_HW_VERSION_4_0 true + +/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */ +#define IPA_HW_BAM_IRQ_NUM 440 + +/* Q6 IRQ number for IPA. Fetched from IPCatalog */ +#define IPA_HW_IRQ_NUM 441 + +/* Total number of different interrupts that can be enabled */ +#define IPA_HW_IRQ_CNT_TOTAL 23 + +/* IPAv4 BCR value */ +#define IPA_HW_BCR_REG_VAL 0x00000039 + +/* IPAv4 spare reg value */ +#define IPA_HW_SPARE_1_REG_VAL 0xC0000005 + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false) + +/* GSI MHI related definitions */ +#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0 +#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1 + +#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1 +#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11 + +/* IPA ZIP WA related Macros */ +#define IPA_HW_DCMP_SRC_PIPE 0x8 +#define IPA_HW_DCMP_DEST_PIPE 0x4 +#define IPA_HW_ACK_MNGR_MASK 0x1D +#define IPA_HW_DCMP_SRC_GRP 0x5 + +/* IPA Clock resource name */ +#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc" + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* HPS Sequences */ +#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7 +#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9 + +/* DPS Sequences */ +#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2 + +/* Src RSRC GRP config */ +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x05050404 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0A0A0A0A +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0C0C0C0C +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x0E0E0E0E + +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x00000101 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x00000808 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x00000808 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x00000E0E + +/* Dest RSRC GRP config */ +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x04040404 +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02 + +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020303 +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02000201 + + +#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x00020703 +#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x00020703 + +#define IPA_HW_RSRP_GRP_0 0x0 +#define IPA_HW_RSRP_GRP_1 0x1 +#define IPA_HW_RSRP_GRP_2 0x2 +#define IPA_HW_RSRP_GRP_3 0x3 + +#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0 +#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0 + +#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 +#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 + +#define IPA_HW_SRC_RSRP_TYPE_MAX 0x4 +#define IPA_HW_DST_RSRP_TYPE_MAX 0x3 + +#define GSI_HW_QSB_LOG_MISC_MAX 0x4 + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* Is IPA decompression feature enabled */ +#define IPA_HW_IS_DECOMPRESSION_ENABLED (1) + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_HW_IS_STEP_MODE_ALLOWED (true) + +/* + * HW specific clock vote freq values in KHz + * (BIMC/SNOC/PCNOC/IPA/Q6 CPU) + */ +enum ipa_hw_clk_freq_e { + /* BIMC */ + IPA_HW_CLK_FREQ_BIMC_PEAK = 518400, + IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200, + IPA_HW_CLK_FREQ_BIMC_NOM = 404200, + IPA_HW_CLK_FREQ_BIMC_SVS = 100000, + + /* PCNOC */ + IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330, + IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000, + IPA_HW_CLK_FREQ_PCNOC_NOM = 100000, + IPA_HW_CLK_FREQ_PCNOC_SVS = 50000, + + /*IPA_HW_CLK_SNOC*/ + IPA_HW_CLK_FREQ_SNOC_PEAK = 200000, + IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000, + IPA_HW_CLK_FREQ_SNOC_NOM = 150000, + IPA_HW_CLK_FREQ_SNOC_SVS = 85000, + IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000, + + /* IPA */ + IPA_HW_CLK_FREQ_IPA_PEAK = 500000, + IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 440000, + IPA_HW_CLK_FREQ_IPA_NOM = 440000, + IPA_HW_CLK_FREQ_IPA_SVS = 250000, + IPA_HW_CLK_FREQ_IPA_SVS_2 = 120000, + + /* Q6 CPU */ + IPA_HW_CLK_FREQ_Q6_PEAK = 729600, + IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600, + IPA_HW_CLK_FREQ_Q6_NOM = 729600, + IPA_HW_CLK_FREQ_Q6_SVS = 729600, +}; + +/* Pipe ID of all the IPA pipes */ +enum ipa_hw_pipe_id_e { + IPA_HW_PIPE_ID_0, + IPA_HW_PIPE_ID_1, + IPA_HW_PIPE_ID_2, + IPA_HW_PIPE_ID_3, + IPA_HW_PIPE_ID_4, + IPA_HW_PIPE_ID_5, + IPA_HW_PIPE_ID_6, + IPA_HW_PIPE_ID_7, + IPA_HW_PIPE_ID_8, + IPA_HW_PIPE_ID_9, + IPA_HW_PIPE_ID_10, + IPA_HW_PIPE_ID_11, + IPA_HW_PIPE_ID_12, + IPA_HW_PIPE_ID_13, + IPA_HW_PIPE_ID_14, + IPA_HW_PIPE_ID_15, + IPA_HW_PIPE_ID_16, + IPA_HW_PIPE_ID_17, + IPA_HW_PIPE_ID_18, + IPA_HW_PIPE_ID_19, + IPA_HW_PIPE_ID_20, + IPA_HW_PIPE_ID_21, + IPA_HW_PIPE_ID_22, + IPA_HW_PIPE_ID_MAX +}; + +/* Pipe ID's of System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_id_e { + /* Pipes used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_3, + IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4, + IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_13, + IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_14, + + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6, + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_16, + /* Test Simulator Pipes */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_12, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_10, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_2, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_11, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_5, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_18, + IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_19, + IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX, +}; + +enum ipa_hw_q6_pipe_ch_id_e { + /* Channels used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0, + IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1, + IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 3, + IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 4, + + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_CH_ID = 2, + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_CH_ID = 5, + /* Test Simulator Channels */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 6, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 8, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 9, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 10, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 11, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 12, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 13, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 14, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 15, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 16, +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_e { + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE = 1, + /* DL Pipe Q6->IPA */ + IPA_HW_Q6_DL_CONSUMER_PIPE = 2, + /* CTL Pipe Q6->IPA */ + IPA_HW_Q6_CTL_CONSUMER_PIPE = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE = 4, + /* LWA DL(Wifi to Q6) */ + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE = 5, + /* Diag status pipe IPA->Q6 */ + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 7, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 8, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 9, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 10, + /* SIM B2B PROD Pipe */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 11, + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 12, + /* End FEATURE_IPA_TEST_PER_SIM */ + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 13, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 14, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 15, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 16, + IPA_HW_Q6_PIPE_TOTAL +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */ + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1, + /* DL Pipe Q6->IPA */ + //IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2, + /* CTL Pipe Q6->IPA */ + //IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + //IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4, + /* LWA DL(Wifi to Q6) */ + //IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5, + /* Diag status pipe IPA->Q6 */ + //IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6, + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_1_GSI_EV = 5, + IPA_HW_Q6_SIM_2_GSI_EV = 6, + IPA_HW_Q6_SIM_3_GSI_EV = 7, + IPA_HW_Q6_SIM_4_GSI_EV = 8, + + IPA_HW_Q6_PIPE_GSI_EV_TOTAL +}; + +/* + * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN + * register and read IRQ_STTS register + */ +enum ipa_hw_irq_e { + IPA_HW_IRQ_GSI_HWP = (1 << 25), + IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24), + IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23), + IPA_HW_IRQ_DCMP_ERR = (1 << 22), + IPA_HW_IRQ_HWP_ERR = (1 << 21), + IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20), + IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19), + IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18), + IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17), + IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16), + IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15), + IPA_HW_IRQ_TX_SUSPEND = (1 << 14), + IPA_HW_IRQ_PROC_ERR = (1 << 13), + IPA_HW_IRQ_STEP_MODE = (1 << 12), + IPA_HW_IRQ_TX_ERR = (1 << 11), + IPA_HW_IRQ_DEAGGR_ERR = (1 << 10), + IPA_HW_IRQ_RX_ERR = (1 << 9), + IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8), + IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7), + IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6), + IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5), + IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4), + IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3), + IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2), + IPA_HW_IRQ_EOT_COAL = (1 << 1), + IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0), + IPA_HW_IRQ_NONE = 0, + IPA_HW_IRQ_ALL = 0xFFFFFFFF +}; + +/* + * All the IRQ sources supported by the IPA HW. Use this enum to set + * IRQ_SRCS register + */ +enum ipa_hw_irq_srcs_e { + IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0), + IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1), + IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2), + IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3), + IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4), + IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5), + IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6), + IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7), + IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8), + IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9), + IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10), + IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11), + IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12), + IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13), + IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14), + IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15), + IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16), + IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17), + IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18), + IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19), + IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20), + IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21), + IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22), + IPA_HW_IRQ_SRCS_NONE = 0, + IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF, +}; + +/* + * Total number of channel contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 14 + +/* + * Total number of channel contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 6 + +/* + * Total number of channel contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 2 + +/* + * Total number of event ring contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 12 + +/* + * Total number of event ring contexts that need to be saved for Q6 + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 4 + +/* + * Total number of event ring contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 1 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are not saved by default (only if ipa_cfg.gen.full_reg_trace = + * true) There is no extra endpoints in Stingray + */ +#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are always saved + */ +#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES 23 + +/* + * Macro to set the active flag for all active pipe indexed register + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE() \ + do { \ + ipa_reg_save.ipa.pipes[0].active = true; \ + ipa_reg_save.ipa.pipes[1].active = true; \ + ipa_reg_save.ipa.pipes[2].active = true; \ + ipa_reg_save.ipa.pipes[3].active = true; \ + ipa_reg_save.ipa.pipes[4].active = true; \ + ipa_reg_save.ipa.pipes[5].active = true; \ + ipa_reg_save.ipa.pipes[6].active = true; \ + ipa_reg_save.ipa.pipes[7].active = true; \ + ipa_reg_save.ipa.pipes[8].active = true; \ + ipa_reg_save.ipa.pipes[9].active = true; \ + ipa_reg_save.ipa.pipes[10].active = true; \ + ipa_reg_save.ipa.pipes[11].active = true; \ + ipa_reg_save.ipa.pipes[12].active = true; \ + ipa_reg_save.ipa.pipes[13].active = true; \ + ipa_reg_save.ipa.pipes[14].active = true; \ + ipa_reg_save.ipa.pipes[15].active = true; \ + ipa_reg_save.ipa.pipes[16].active = true; \ + ipa_reg_save.ipa.pipes[17].active = true; \ + ipa_reg_save.ipa.pipes[18].active = true; \ + ipa_reg_save.ipa.pipes[19].active = true; \ + ipa_reg_save.ipa.pipes[20].active = true; \ + ipa_reg_save.ipa.pipes[21].active = true; \ + ipa_reg_save.ipa.pipes[22].active = true; \ + } while (0) + +/* + * Macro to define a particular register cfg entry for the remaining + * pipe indexed register. In Stingray case we don't have extra + * endpoints so it is intentially empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \ + { 0, 0 } + +/* + * Macro to set the active flag for all active pipe indexed register + * In Stingray case we don't have extra endpoints so it is intentially + * empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \ + do { \ + } while (0) + +#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h new file mode 100644 index 000000000000..0affad19d1f1 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h @@ -0,0 +1,10355 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HWIO_H_) +#define _IPA_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +#define IPA_GSI_TOP_GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_IPA_GSI_TOP_GSI_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK 0xff01 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK 0x1f1f03 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0x1f0000 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_MAXn 1023 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL \ + 0x33 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL \ + 0x34 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL \ + 0x35 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL \ + 0x36 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK \ + 0x1000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK \ + 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK \ + 0xf8000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK \ + 0x7c00000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK \ + 0x200000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK \ + 0x1fffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 16 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001600 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 11 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7dfff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK \ + 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c054 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c058 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK 0x70f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL \ + 0x0 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c060 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c064 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c068 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c06c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c070 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d02c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d02c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d048 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d04c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d04c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d04c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e000 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e004 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e100 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e104 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f000 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f008 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f010 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK \ + 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK \ + 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x1ffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK \ + 0x1ffff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR( \ + n), \ + mask) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK \ + 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f200 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c02c + 0x1000 * (n)) +#define IPA_CFG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00040000) +#define IPA_CFG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00040000) +#define IPA_CFG_REG_BASE_OFFS 0x00040000 +#define HWIO_IPA_COMP_HW_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_COMP_HW_VERSION_ATTR 0x1 +#define HWIO_IPA_COMP_HW_VERSION_IN in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + HWIO_IPA_COMP_HW_VERSION_RMSK) +#define HWIO_IPA_COMP_HW_VERSION_INM(m) in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + m) +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_COMP_HW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_COMP_HW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_COMP_HW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_COMP_HW_VERSION_STEP_SHFT 0x0 +#define HWIO_IPA_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000034) +#define HWIO_IPA_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_ENABLED_PIPES_ADDR (IPA_CFG_REG_BASE + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_COMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000003c) +#define HWIO_IPA_COMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_RMSK 0x1fffff +#define HWIO_IPA_COMP_CFG_ATTR 0x3 +#define HWIO_IPA_COMP_CFG_IN in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, \ + HWIO_IPA_COMP_CFG_RMSK) +#define HWIO_IPA_COMP_CFG_INM(m) in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, m) +#define HWIO_IPA_COMP_CFG_OUT(v) out_dword(HWIO_IPA_COMP_CFG_ADDR, v) +#define HWIO_IPA_COMP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_COMP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_COMP_CFG_IN) +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0x1e0000 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 0x11 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 0x10 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 0xf +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x4000 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xe +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x2000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT \ + 0xd +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 0xc +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 0xb +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 0xa +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 0x9 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 0x8 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 0x7 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 0x6 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 0x5 +#define HWIO_IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK 0x10 +#define HWIO_IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 0x3 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 0x1 +#define HWIO_IPA_COMP_CFG_ENABLE_BMSK 0x1 +#define HWIO_IPA_COMP_CFG_ENABLE_SHFT 0x0 +#define HWIO_IPA_COMP_SW_RESET_ADDR (IPA_CFG_REG_BASE + 0x00000040) +#define HWIO_IPA_COMP_SW_RESET_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_COMP_SW_RESET_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_CLKON_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000044) +#define HWIO_IPA_CLKON_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_CLKON_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_ROUTE_ADDR (IPA_CFG_REG_BASE + 0x00000048) +#define HWIO_IPA_ROUTE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_ROUTE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_ROUTE_RMSK 0x13fffff +#define HWIO_IPA_ROUTE_ATTR 0x3 +#define HWIO_IPA_ROUTE_IN in_dword_masked(HWIO_IPA_ROUTE_ADDR, \ + HWIO_IPA_ROUTE_RMSK) +#define HWIO_IPA_ROUTE_INM(m) in_dword_masked(HWIO_IPA_ROUTE_ADDR, m) +#define HWIO_IPA_ROUTE_OUT(v) out_dword(HWIO_IPA_ROUTE_ADDR, v) +#define HWIO_IPA_ROUTE_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_ROUTE_ADDR, \ + m, \ + v, \ + HWIO_IPA_ROUTE_IN) +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x1000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x18 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0x3e0000 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x11 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x1ff80 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x7 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x40 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x6 +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0x3e +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_BMSK 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_SHFT 0x0 +#define HWIO_IPA_FILTER_ADDR (IPA_CFG_REG_BASE + 0x0000004c) +#define HWIO_IPA_FILTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_FILTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_MASTER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_SHARED_MEM_SIZE_ADDR (IPA_CFG_REG_BASE + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_NAT_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000058) +#define HWIO_IPA_NAT_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_NAT_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_NAT_TIMER_RESET_ADDR (IPA_CFG_REG_BASE + 0x0000005c) +#define HWIO_IPA_NAT_TIMER_RESET_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_NAT_TIMER_RESET_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_TAG_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000060) +#define HWIO_IPA_TAG_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_TAG_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_TAG_TIMER_RMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_ATTR 0x3 +#define HWIO_IPA_TAG_TIMER_IN in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, \ + HWIO_IPA_TAG_TIMER_RMSK) +#define HWIO_IPA_TAG_TIMER_INM(m) in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, \ + m) +#define HWIO_IPA_TAG_TIMER_OUT(v) out_dword(HWIO_IPA_TAG_TIMER_ADDR, v) +#define HWIO_IPA_TAG_TIMER_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_TAG_TIMER_ADDR, \ + m, \ + v, \ + HWIO_IPA_TAG_TIMER_IN) +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_BMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_SHFT 0x0 +#define HWIO_IPA_FRAG_RULES_CLR_ADDR (IPA_CFG_REG_BASE + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_RMSK 0xff0fff +#define HWIO_IPA_PROC_IPH_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IN in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + HWIO_IPA_PROC_IPH_CFG_RMSK) +#define HWIO_IPA_PROC_IPH_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m) +#define HWIO_IPA_PROC_IPH_CFG_OUT(v) out_dword(HWIO_IPA_PROC_IPH_CFG_ADDR, \ + v) +#define HWIO_IPA_PROC_IPH_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROC_IPH_CFG_IN) +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_BMSK \ + 0xff0000 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_SHFT 0x10 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_BMSK 0x800 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_SHFT 0xb +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_BMSK 0x400 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_SHFT 0xa +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_BMSK 0x200 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_SHFT 0x9 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_BMSK \ + 0x100 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_SHFT 0x8 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_BMSK 0x80 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_SHFT 0x7 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_BMSK 0x40 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_SHFT 0x6 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_BMSK 0x10 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_SHFT 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_TIME_CNT_CLK_SRC_BMSK 0x8 +#define HWIO_IPA_PROC_IPH_CFG_IPH_TIME_CNT_CLK_SRC_SHFT 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_BMSK 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_SHFT 0x2 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_BMSK 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_SHFT 0x0 +#define HWIO_IPA_QSB_MAX_WRITES_ADDR (IPA_CFG_REG_BASE + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_ADDR (IPA_CFG_REG_BASE + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x00000080) +#define HWIO_IPA_QSB_READ_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_DPL_TIMER_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_LSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + HWIO_IPA_DPL_TIMER_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_LSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_LSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_LSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_LSB_IN) +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_SHFT 0x0 +#define HWIO_IPA_DPL_TIMER_MSB_ADDR (IPA_CFG_REG_BASE + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_RMSK 0x8000ffff +#define HWIO_IPA_DPL_TIMER_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_MSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + HWIO_IPA_DPL_TIMER_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_MSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_MSB_IN) +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_BMSK 0x80000000 +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_SHFT 0x1f +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_BMSK 0xffff +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_SHFT 0x0 +#define HWIO_IPA_STATE_TX_WRAPPER_ADDR (IPA_CFG_REG_BASE + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_RMSK 0x3ff +#define HWIO_IPA_STATE_TX_WRAPPER_ATTR 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_IN in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + HWIO_IPA_STATE_TX_WRAPPER_RMSK) +#define HWIO_IPA_STATE_TX_WRAPPER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + m) +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_BMSK 0x100 +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_SHFT 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_EXPIRY_BMSK 0x80 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_EXPIRY_SHFT 0x7 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_TX1_ADDR (IPA_CFG_REG_BASE + 0x00000094) +#define HWIO_IPA_STATE_TX1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_STATE_TX1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_STATE_TX1_RMSK 0xfffffff +#define HWIO_IPA_STATE_TX1_ATTR 0x1 +#define HWIO_IPA_STATE_TX1_IN in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + HWIO_IPA_STATE_TX1_RMSK) +#define HWIO_IPA_STATE_TX1_INM(m) in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + m) +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_BMSK 0xf800000 +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_SHFT 0x17 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_BMSK 0x100000 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_SHFT 0x14 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_BMSK 0x20000 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_SHFT 0x11 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_TX1_PF_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX1_PF_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX1_AR_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX1_AR_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX1_PA_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TX1_PA_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX1_NEXT_ARBIT_TYPE_BMSK 0xc +#define HWIO_IPA_STATE_TX1_NEXT_ARBIT_TYPE_SHFT 0x2 +#define HWIO_IPA_STATE_TX1_LAST_ARBIT_TYPE_BMSK 0x3 +#define HWIO_IPA_STATE_TX1_LAST_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_ADDR (IPA_CFG_REG_BASE + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_RMSK 0x7ffffff +#define HWIO_IPA_STATE_FETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + HWIO_IPA_STATE_FETCHER_RMSK) +#define HWIO_IPA_STATE_FETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_BMSK \ + 0x4000000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_SHFT 0x1a +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_BMSK 0x3f80000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_REP_STATE_IDLE_BMSK 0x7f000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_REP_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_BMSK 0xfe0 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_MASK_ADDR (IPA_CFG_REG_BASE + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_RMSK 0xfffffff +#define HWIO_IPA_STATE_FETCHER_MASK_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_ADDR, \ + HWIO_IPA_STATE_FETCHER_MASK_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_STEP_MODE_BMSK 0xf000000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_STEP_MODE_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_ARB_LOCK_BMSK 0xf00000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_ARB_LOCK_SHFT 0x14 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_BMSK \ + 0xf0000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_SHFT \ + 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_BMSK \ + 0xf000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_SHFT \ + 0xc +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_CONTEXT_BMSK \ + 0xf00 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_CONTEXT_SHFT \ + 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_IMM_EXEC_BMSK 0xf0 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_IMM_EXEC_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_DMAR_USES_QUEUE_BMSK 0xf +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_DMAR_USES_QUEUE_SHFT 0x0 +#define HWIO_IPA_STATE_DFETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_RMSK 0x3f3f3 +#define HWIO_IPA_STATE_DFETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + HWIO_IPA_STATE_DFETCHER_RMSK) +#define HWIO_IPA_STATE_DFETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_BMSK 0x3f000 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_BMSK 0x3f0 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_ACL_ADDR (IPA_CFG_REG_BASE + 0x000000a4) +#define HWIO_IPA_STATE_ACL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_RMSK 0xffffff +#define HWIO_IPA_STATE_ACL_ATTR 0x1 +#define HWIO_IPA_STATE_ACL_IN in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + HWIO_IPA_STATE_ACL_RMSK) +#define HWIO_IPA_STATE_ACL_INM(m) in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + m) +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_SHFT 0x15 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_BMSK 0x80000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_SHFT 0x13 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_ACTIVE_BMSK 0x20000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_ACTIVE_SHFT 0x11 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_BMSK 0x8000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_SHFT 0xf +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_BMSK 0x2000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_SHFT 0xd +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_BMSK 0x1000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_SHFT 0xc +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_BMSK 0x800 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_SHFT 0xb +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_BMSK 0x400 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_SHFT 0xa +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_BMSK 0x200 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_SHFT 0x9 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_BMSK 0x100 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_SHFT 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_BMSK 0x80 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_SHFT 0x7 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_BMSK 0x20 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_SHFT 0x5 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_BMSK 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_SHFT 0x3 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_BMSK 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_SHFT 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_BMSK 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_TLV_ADDR (IPA_CFG_REG_BASE + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_RMSK 0x3ff +#define HWIO_IPA_STATE_GSI_TLV_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_TLV_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + HWIO_IPA_STATE_GSI_TLV_RMSK) +#define HWIO_IPA_STATE_GSI_TLV_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_BMSK 0x3ff +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_AOS_ADDR (IPA_CFG_REG_BASE + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_RMSK 0x7fffff +#define HWIO_IPA_STATE_GSI_AOS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + HWIO_IPA_STATE_GSI_AOS_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_BMSK 0x7fffff +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_IF_ADDR (IPA_CFG_REG_BASE + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_RMSK 0xf +#define HWIO_IPA_STATE_GSI_IF_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + HWIO_IPA_STATE_GSI_IF_RMSK) +#define HWIO_IPA_STATE_GSI_IF_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_BMSK 0xc +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_SHFT 0x2 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_BMSK 0x3 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_SKIP_ADDR (IPA_CFG_REG_BASE + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_RMSK 0x3ffffff +#define HWIO_IPA_STATE_GSI_SKIP_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_SKIP_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + HWIO_IPA_STATE_GSI_SKIP_RMSK) +#define HWIO_IPA_STATE_GSI_SKIP_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_BMSK 0x3ffffff +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_SHFT 0x0 +#define HWIO_IPA_STATE_ADDR (IPA_CFG_REG_BASE + 0x000000a8) +#define HWIO_IPA_STATE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_STATE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_STATE_RMSK 0xf3fdfff7 +#define HWIO_IPA_STATE_ATTR 0x1 +#define HWIO_IPA_STATE_IN in_dword_masked(HWIO_IPA_STATE_ADDR, \ + HWIO_IPA_STATE_RMSK) +#define HWIO_IPA_STATE_INM(m) in_dword_masked(HWIO_IPA_STATE_ADDR, m) +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_BMSK 0x20000000 +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_SHFT 0x1d +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_2_EMPTY_BMSK 0x2000000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_2_EMPTY_SHFT 0x19 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_1_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_1_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_0_EMPTY_BMSK 0x800000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_0_EMPTY_SHFT 0x17 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_BMSK 0x400000 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_SHFT 0x16 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_BMSK 0x2000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_SHFT 0xd +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_BMSK 0x800 +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_SHFT 0xb +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_AGGR_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_AGGR_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TX_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RX_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RX_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RX_WAIT_BMSK 0x1 +#define HWIO_IPA_STATE_RX_WAIT_SHFT 0x0 +#define HWIO_IPA_STATE_RX_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_RMSK 0x3ff +#define HWIO_IPA_STATE_RX_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_RX_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + HWIO_IPA_STATE_RX_ACTIVE_RMSK) +#define HWIO_IPA_STATE_RX_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_BMSK 0x3ff +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_STATE_TX0_ADDR (IPA_CFG_REG_BASE + 0x000000b0) +#define HWIO_IPA_STATE_TX0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_RMSK 0xfffffff +#define HWIO_IPA_STATE_TX0_ATTR 0x1 +#define HWIO_IPA_STATE_TX0_IN in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + HWIO_IPA_STATE_TX0_RMSK) +#define HWIO_IPA_STATE_TX0_INM(m) in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + m) +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_BMSK 0xf800000 +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_SHFT 0x17 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_BMSK 0x100000 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_SHFT 0x14 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_BMSK 0x20000 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_SHFT 0x11 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_TX0_PF_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX0_PF_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX0_AR_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX0_AR_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX0_PA_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TX0_PA_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_BMSK 0xc +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_SHFT 0x2 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_BMSK 0x3 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_AGGR_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_RMSK 0x7fffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + HWIO_IPA_STATE_AGGR_ACTIVE_RMSK) +#define HWIO_IPA_STATE_AGGR_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_YELLOW_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000118) +#define HWIO_IPA_RED_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000124) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RED_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000138) +#define HWIO_IPA_RED_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000144) +#define HWIO_IPA_FILT_ROUT_HASH_EN_ADDR (IPA_CFG_REG_BASE + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_EN_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IN in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + HWIO_IPA_FILT_ROUT_HASH_EN_RMSK) +#define HWIO_IPA_FILT_ROUT_HASH_EN_INM(m) in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_FILT_ROUT_HASH_EN_IN) +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_SHFT 0x0 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR (IPA_CFG_REG_BASE + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IN in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_RMSK) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_INM(m) in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + m) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + m, \ + v, \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_IN) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_SHFT 0x0 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR (IPA_CFG_REG_BASE + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR (IPA_CFG_REG_BASE + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR (IPA_CFG_REG_BASE + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b8) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c8) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001cc) +#define HWIO_IPA_BCR_ADDR (IPA_CFG_REG_BASE + 0x000001d0) +#define HWIO_IPA_BCR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d0) +#define HWIO_IPA_BCR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d0) +#define HWIO_IPA_BCR_RMSK 0x3ff +#define HWIO_IPA_BCR_ATTR 0x3 +#define HWIO_IPA_BCR_IN in_dword_masked(HWIO_IPA_BCR_ADDR, \ + HWIO_IPA_BCR_RMSK) +#define HWIO_IPA_BCR_INM(m) in_dword_masked(HWIO_IPA_BCR_ADDR, m) +#define HWIO_IPA_BCR_OUT(v) out_dword(HWIO_IPA_BCR_ADDR, v) +#define HWIO_IPA_BCR_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_BCR_ADDR, \ + m, \ + v, \ + HWIO_IPA_BCR_IN) +#define HWIO_IPA_BCR_BCR_ROUTER_PREFETCH_EN_BMSK 0x200 +#define HWIO_IPA_BCR_BCR_ROUTER_PREFETCH_EN_SHFT 0x9 +#define HWIO_IPA_BCR_BCR_FILTER_PREFETCH_EN_BMSK 0x100 +#define HWIO_IPA_BCR_BCR_FILTER_PREFETCH_EN_SHFT 0x8 +#define HWIO_IPA_BCR_BCR_NOTIF_PRIORITY_OVER_ZLT_BMSK 0x80 +#define HWIO_IPA_BCR_BCR_NOTIF_PRIORITY_OVER_ZLT_SHFT 0x7 +#define HWIO_IPA_BCR_BCR_ENABLE_FILTER_DATA_CACHE_BMSK 0x40 +#define HWIO_IPA_BCR_BCR_ENABLE_FILTER_DATA_CACHE_SHFT 0x6 +#define HWIO_IPA_BCR_BCR_DUAL_TX_BMSK 0x20 +#define HWIO_IPA_BCR_BCR_DUAL_TX_SHFT 0x5 +#define HWIO_IPA_BCR_BCR_HOLB_DROP_L2_IRQ_BMSK 0x10 +#define HWIO_IPA_BCR_BCR_HOLB_DROP_L2_IRQ_SHFT 0x4 +#define HWIO_IPA_BCR_BCR_SUSPEND_L2_IRQ_BMSK 0x8 +#define HWIO_IPA_BCR_BCR_SUSPEND_L2_IRQ_SHFT 0x3 +#define HWIO_IPA_BCR_BCR_TX_SUSPEND_IRQ_ONLY_ASSERT_ONCE_PER_PKT_BMSK 0x4 +#define HWIO_IPA_BCR_BCR_TX_SUSPEND_IRQ_ONLY_ASSERT_ONCE_PER_PKT_SHFT 0x2 +#define HWIO_IPA_BCR_BCR_TX_NOT_USING_BRESP_BMSK 0x2 +#define HWIO_IPA_BCR_BCR_TX_NOT_USING_BRESP_SHFT 0x1 +#define HWIO_IPA_BCR_BCR_CMDQ_L_LACK_ONE_ENTRY_BMSK 0x1 +#define HWIO_IPA_BCR_BCR_CMDQ_L_LACK_ONE_ENTRY_SHFT 0x0 +#define HWIO_IPA_MVS_ADDR (IPA_CFG_REG_BASE + 0x000001d4) +#define HWIO_IPA_MVS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d4) +#define HWIO_IPA_MVS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d4) +#define HWIO_IPA_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d8) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR (IPA_CFG_REG_BASE + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK 0x7fffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ATTR 0x1 +#define HWIO_IPA_BAM_ACTIVATED_PORTS_IN in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_INM(m) in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + m) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0xfffffff8 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_BMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_SHFT 0x0 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK 0x1ffff +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0x1fff8 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_AGGR_FORCE_CLOSE_ADDR (IPA_CFG_REG_BASE + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001ec) +#define HWIO_IPA_COUNTER_CFG_ADDR (IPA_CFG_REG_BASE + 0x000001f0) +#define HWIO_IPA_COUNTER_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001f0) +#define HWIO_IPA_COUNTER_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001f0) +#define HWIO_IPA_SCND_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001f4) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_ADDR (IPA_CFG_REG_BASE + 0x000001f8) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001f8) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001f8) +#define HWIO_IPA_TX_CFG_ADDR (IPA_CFG_REG_BASE + 0x000001fc) +#define HWIO_IPA_TX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001fc) +#define HWIO_IPA_TX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001fc) +#define HWIO_IPA_RAM_INTLV_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_FLAVOR_0_ADDR (IPA_CFG_REG_BASE + 0x00000210) +#define HWIO_IPA_FLAVOR_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000210) +#define HWIO_IPA_FLAVOR_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000210) +#define HWIO_IPA_FLAVOR_1_ADDR (IPA_CFG_REG_BASE + 0x00000214) +#define HWIO_IPA_FLAVOR_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_FLAVOR_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_FLAVOR_2_ADDR (IPA_CFG_REG_BASE + 0x00000218) +#define HWIO_IPA_FLAVOR_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_FLAVOR_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_FLAVOR_3_ADDR (IPA_CFG_REG_BASE + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_IDLE_INDICATION_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000220) +#define HWIO_IPA_IDLE_INDICATION_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000220) +#define HWIO_IPA_IDLE_INDICATION_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000220) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000033c) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000344) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_ADDR (IPA_CFG_REG_BASE + \ + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000348) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000400 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000404 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000500 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000504 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_RSRC_GRP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_RMSK 0x311f131 +#define HWIO_IPA_RSRC_GRP_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + HWIO_IPA_RSRC_GRP_CFG_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_GRP_CFG_OUT(v) out_dword(HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_GRP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_GRP_CFG_IN) +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3000000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 0x18 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 0x14 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0x1f000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 0xc +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 0x8 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x30 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0x0 +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_ADDR (IPA_CFG_REG_BASE + \ + 0x000005a4) +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000005a4) +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000005a4) +#define HWIO_IPA_PIPELINE_DISABLE_ADDR (IPA_CFG_REG_BASE + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a8) +#define HWIO_IPA_AXI_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005ac) +#define HWIO_IPA_AXI_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005ac) +#define HWIO_IPA_AXI_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005ac) +#define HWIO_STAT_QUOTA_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000700 + \ + 0x4 * (n)) +#define HWIO_STAT_QUOTA_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000708 + \ + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_FILTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000720) +#define HWIO_STAT_FILTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000720) +#define HWIO_STAT_FILTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000720) +#define HWIO_STAT_FILTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000724) +#define HWIO_STAT_FILTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_STAT_FILTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_STAT_ROUTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000728) +#define HWIO_STAT_ROUTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_STAT_ROUTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_STAT_ROUTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x0000072c) +#define HWIO_STAT_ROUTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_STAT_ROUTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_STAT_FILTER_IPV4_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000730) +#define HWIO_STAT_FILTER_IPV4_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000730) +#define HWIO_STAT_FILTER_IPV4_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000730) +#define HWIO_STAT_FILTER_IPV6_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000734) +#define HWIO_STAT_FILTER_IPV6_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000734) +#define HWIO_STAT_FILTER_IPV6_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000734) +#define HWIO_STAT_ROUTER_IPV4_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000738) +#define HWIO_STAT_ROUTER_IPV4_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000738) +#define HWIO_STAT_ROUTER_IPV4_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000738) +#define HWIO_STAT_ROUTER_IPV6_START_ID_ADDR (IPA_CFG_REG_BASE + 0x0000073c) +#define HWIO_STAT_ROUTER_IPV6_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000073c) +#define HWIO_STAT_ROUTER_IPV6_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000073c) +#define HWIO_STAT_FILTER_IPV4_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000740) +#define HWIO_STAT_FILTER_IPV4_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000740) +#define HWIO_STAT_FILTER_IPV4_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000740) +#define HWIO_STAT_FILTER_IPV6_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000744) +#define HWIO_STAT_FILTER_IPV6_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000744) +#define HWIO_STAT_FILTER_IPV6_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000744) +#define HWIO_STAT_ROUTER_IPV4_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000748) +#define HWIO_STAT_ROUTER_IPV4_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000748) +#define HWIO_STAT_ROUTER_IPV4_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000748) +#define HWIO_STAT_ROUTER_IPV6_END_ID_ADDR (IPA_CFG_REG_BASE + 0x0000074c) +#define HWIO_STAT_ROUTER_IPV6_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000074c) +#define HWIO_STAT_ROUTER_IPV6_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000074c) +#define HWIO_STAT_DROP_CNT_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000750 + \ + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000758 + \ + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000800 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000808 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_RMSK 0x17f +#define HWIO_IPA_ENDP_INIT_CFG_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CFG_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000080c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_NAT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_NAT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_NAT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000810 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_RMSK 0x1fffffff +#define HWIO_IPA_ENDP_INIT_HDR_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK 0x3fff +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK \ + 0x3f0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000818 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK \ + 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000820 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_RMSK 0x7ffff1f7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_MODE_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_MODE_n_RMSK) +#define HWIO_IPA_ENDP_INIT_MODE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_MODE_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_BMSK 0x40000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0x1f0 +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000824 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_RMSK 0x17fffff +#define HWIO_IPA_ENDP_INIT_AGGR_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_AGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_AGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_AGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK \ + 0x1000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x400000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x16 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x15 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x1f8000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0xf +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x7c00 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x3e0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000830 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK 0xffff7fff +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xffff0000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3f00 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000083c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_RMSK 0xffff +#define HWIO_IPA_ENDP_INIT_SEQ_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_SEQ_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_SEQ_n_RMSK) +#define HWIO_IPA_ENDP_INIT_SEQ_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_SEQ_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_BMSK 0xf000 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_BMSK 0xf00 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0xf0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0xf +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 +#define HWIO_IPA_ENDP_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000840 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_RMSK 0x33f +#define HWIO_IPA_ENDP_STATUS_n_MAXn 22 +#define HWIO_IPA_ENDP_STATUS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_STATUS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + HWIO_IPA_ENDP_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_STATUS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_STATUS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_STATUS_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_STATUS_n_INI(n)) +#define HWIO_IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK 0x100 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_WEIGHTS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000844 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_WEIGHTS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000844 + 0x70 * (n)) +#define HWIO_IPA_ENDP_WEIGHTS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000844 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000085c + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK 0x7f007f +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_MAXn 31 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n)) +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK \ + 0x400000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT \ + 0x16 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK \ + 0x200000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT \ + 0x15 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK \ + 0x100000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT \ + 0x14 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK \ + 0x80000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT \ + 0x13 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x40000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x12 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x20000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x11 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK \ + 0x10000 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK \ + 0x40 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT \ + 0x6 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK \ + 0x20 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT \ + 0x5 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK \ + 0x8 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT \ + 0x3 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT \ + 0x0 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000860 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_SNIFFER_QMB_SEL_ADDR (IPA_CFG_REG_BASE + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001800) +#define IPA_DEBUG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00042000) +#define IPA_DEBUG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00042000) +#define IPA_DEBUG_REG_BASE_OFFS 0x00042000 +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000074) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000088) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK 0x3f73 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUT(v) out_dword( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_BMSK 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK 0x3f3 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK 0x7f7f3f3 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_BMSK 0x7f00000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_SHFT 0x14 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_BMSK 0x7f000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_BRESP_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000138) +#define HWIO_IPA_BRESP_DB_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_DEBUG_DATA_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_RMSK 0x11fffff +#define HWIO_IPA_DEBUG_DATA_SEL_ATTR 0x3 +#define HWIO_IPA_DEBUG_DATA_SEL_IN in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + HWIO_IPA_DEBUG_DATA_SEL_RMSK) +#define HWIO_IPA_DEBUG_DATA_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + m) +#define HWIO_IPA_DEBUG_DATA_SEL_OUT(v) out_dword( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + v) +#define HWIO_IPA_DEBUG_DATA_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_DEBUG_DATA_SEL_IN) +#define HWIO_IPA_DEBUG_DATA_SEL_UC_DAP_EN_BMSK 0x1000000 +#define HWIO_IPA_DEBUG_DATA_SEL_UC_DAP_EN_SHFT 0x18 +#define HWIO_IPA_DEBUG_DATA_SEL_PIPE_SELECT_BMSK 0x1f0000 +#define HWIO_IPA_DEBUG_DATA_SEL_PIPE_SELECT_SHFT 0x10 +#define HWIO_IPA_DEBUG_DATA_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff00 +#define HWIO_IPA_DEBUG_DATA_SEL_INTERNAL_BLOCK_SELECT_SHFT 0x8 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x0 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_DEBUGBUS_FVAL \ + 0x0 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX_DEBUGBUS_FVAL \ + 0x1 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_FRAG_DEBUGBUS_FVAL \ + 0x2 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_UCP_DEBUGBUS_FVAL \ + 0x3 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_ROUTER_DEBUGBUS_FVAL \ + 0x5 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_DCMP_DEBUGBUS_FVAL \ + 0xb +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_D_DCPH_DEBUGBUS_FVAL \ + 0xd +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_GSI_TEST_BUS_OUT_FVAL \ + 0xe +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DEADBEAF_FVAL 0xf +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_MISC_DEBUGBUS_FVAL \ + 0x10 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_DEBUGBUS_0_FVAL \ + 0x12 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_DEBUGBUS_1_FVAL \ + 0x13 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_AGGR_DEBUGBUS_FVAL \ + 0x16 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_H_DCPH_DEBUGBUS_FVAL \ + 0x17 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_CMDQ_L_TESTBUS_FVAL \ + 0x1b +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_DEBUGBUS_FVAL \ + 0x1e +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_RSRC_DEBUGBUS_FVAL \ + 0x32 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_ACKMNGR_DEBUGBUS_FVAL \ + 0x33 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_SEQ_DEBUGBUS_FVAL \ + 0x34 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_SEQ_DEBUGBUS_FVAL \ + 0x35 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_FTCH_DEBUGBUS_FVAL \ + 0x36 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_FTCH_DEBUGBUS_FVAL \ + 0x37 +#define HWIO_IPA_DEBUG_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_RMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_ATTR 0x1 +#define HWIO_IPA_DEBUG_DATA_IN in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, \ + HWIO_IPA_DEBUG_DATA_RMSK) +#define HWIO_IPA_DEBUG_DATA_INM(m) in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_ADDR, \ + m) +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_BMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_SHFT 0x0 +#define HWIO_IPA_TESTBUS_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_RMSK 0x1fffff1 +#define HWIO_IPA_TESTBUS_SEL_ATTR 0x3 +#define HWIO_IPA_TESTBUS_SEL_IN in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, \ + HWIO_IPA_TESTBUS_SEL_RMSK) +#define HWIO_IPA_TESTBUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m) +#define HWIO_IPA_TESTBUS_SEL_OUT(v) out_dword(HWIO_IPA_TESTBUS_SEL_ADDR, v) +#define HWIO_IPA_TESTBUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_TESTBUS_SEL_IN) +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_BMSK 0x1f00000 +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_SHFT 0x14 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff000 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_SHFT 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_TESTBUS_FVAL 0x0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX_TESTBUS_FVAL 0x1 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FRAG_TESTBUS_FVAL \ + 0x2 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_UCP_TESTBUS_FVAL \ + 0x3 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ENQUEUER_TESTBUS_FVAL \ + 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ROUTER_TESTBUS_FVAL \ + 0x5 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_PKT_PARSER_TESTBUS_FVAL \ + 0x6 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FILTER_NAT_TESTBUS_FVAL \ + 0x7 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_AHB2AHB_TESTBUS_FVAL \ + 0x9 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MAXI2AXI_TESTBUS_FVAL \ + 0xa +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DCMP_TESTBUS_FVAL \ + 0xb +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DISPATCHER_TESTBUS_FVAL \ + 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_D_DCPH_TESTBUS_FVAL \ + 0xd +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_GSI_TEST_BUS_OUT_FVAL \ + 0xe +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DEADBEAF_FVAL 0xf +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MISC_TESTBUS_FVAL \ + 0x10 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_TESTBUS_0_FVAL \ + 0x12 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_TESTBUS_1_FVAL \ + 0x13 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_UC_ACKQ_TESTBUS_FVAL \ + 0x14 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_ACKQ_TESTBUS_FVAL \ + 0x15 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_AGGR_TESTBUS_FVAL 0x16 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RX_HPS_CMDQ_TESTBUS_FVAL \ + 0x17 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_DPS_CMDQ_TESTBUS_FVAL \ + 0x18 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_TX_CMDQ_TESTBUS_FVAL \ + 0x19 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_CMDQ_L_TESTBUS_FVAL \ + 0x1b +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_TESTBUS_FVAL \ + 0x1e +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACK_MNGR_CMDQ_TESTBUS_FVAL \ + 0x1f +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RSRC_TESTBUS_FVAL 0x32 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACKMNGR_TESTBUS_FVAL \ + 0x33 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_SEQ_TESTBUS_FVAL \ + 0x34 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_SEQ_TESTBUS_FVAL \ + 0x35 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FTCH_TESTBUS_FVAL \ + 0x36 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_FTCH_TESTBUS_FVAL \ + 0x37 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_D_DCPH_2_TESTBUS_FVAL \ + 0x38 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_NTF_TX_CMDQ_TESTBUS_FVAL \ + 0x39 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_PROD_ACK_MNGR_DEBUGBUS_FVAL \ + 0x3b +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_BMSK 0x1 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_STATUS_IN in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + HWIO_IPA_STEP_MODE_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + m) +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_GO_ADDR (IPA_DEBUG_REG_BASE + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_HW_EVENTS_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x0000021c) +#define HWIO_IPA_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_LOG_RMSK 0x3ff1f2 +#define HWIO_IPA_LOG_ATTR 0x3 +#define HWIO_IPA_LOG_IN in_dword_masked(HWIO_IPA_LOG_ADDR, \ + HWIO_IPA_LOG_RMSK) +#define HWIO_IPA_LOG_INM(m) in_dword_masked(HWIO_IPA_LOG_ADDR, m) +#define HWIO_IPA_LOG_OUT(v) out_dword(HWIO_IPA_LOG_ADDR, v) +#define HWIO_IPA_LOG_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_LOG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_IN) +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_LOG_LOG_PIPE_BMSK 0x1f0 +#define HWIO_IPA_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_LOG_LOG_EN_SHFT 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK 0x3ffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_BMSK 0x20000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_SHFT 0x11 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK 0xbfff3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_BMSK \ + 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_BMSK 0x3fff0000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_BMSK 0x3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000254) +#define HWIO_IPA_RX_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_UC_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000027c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000280) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000280) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000280) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_0_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_0_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000284) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000284) +#define HWIO_IPA_RX_SPLT_CMDQ_0_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000284) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000288) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000288) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000288) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000028c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000028c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000028c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000290) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000290) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000290) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000294) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000294) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000294) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000298) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000298) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000298) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000029c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000029c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000029c) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002a0) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002a0) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002a0) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002a4) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002a4) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002a4) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_0_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002a8) +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002a8) +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002a8) +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_0_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000002ac) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002ac) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002ac) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_1_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x000002b0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002b0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002b0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002b4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002b4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002b4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002b8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002b8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002b8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002bc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002bc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002bc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002c0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002c0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002c0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002c4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002c4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002c4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002c8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002c8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002c8) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002cc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002cc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002cc) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002d0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002d0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002d0) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_1_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002d4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002d4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002d4) +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_1_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000002d8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002d8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002d8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_2_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x000002dc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002dc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002dc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002e0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002e0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002e0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002e4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002e4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002e4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002e8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002e8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002e8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002ec) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002ec) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002ec) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002f0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002f0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002f0) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002f4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002f4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002f4) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002f8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002f8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002f8) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000002fc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002fc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002fc) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_2_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000300) +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000300) +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000300) +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_ADDR, \ + HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_2_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK 0x7 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK 0x2f +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_BMSK 0x20 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_SHFT 0x5 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_BMSK 0xc +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_RX_HPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003bc) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK 0xf0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK 0xf0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK 0x7f +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x7c +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK 0x1f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x1f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK 0x9f +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x1c +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK 0xff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_DPS_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_BMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_BMSK 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK 0x7ffffff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x3ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x3ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK 0x3f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUT(v) out_dword( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + v) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_BMSK 0x20 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_SHFT 0x5 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_BMSK \ + 0x1f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK 0xc007ffff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FSM_STATE_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FSM_STATE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_EMPTY_BMSK 0x40000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_EMPTY_SHFT 0x12 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_WR_ADDR_BMSK 0x3fe00 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_WR_ADDR_SHFT 0x9 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RD_ADDR_BMSK 0x1ff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RD_ADDR_SHFT 0x0 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RMSK 0xc007ffff +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_FSM_STATE_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_FSM_STATE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_EMPTY_PUB_BMSK 0x40000 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_EMPTY_PUB_SHFT 0x12 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_WR_ADDR_BMSK 0x3fe00 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_WR_ADDR_SHFT 0x9 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RD_ADDR_PUB_BMSK 0x1ff +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RD_ADDR_PUB_SHFT 0x0 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK 0xe01fffff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FSM_STATE_BMSK 0xe0000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FSM_STATE_SHFT 0x1d +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_EMPTY_BMSK 0x100000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_EMPTY_SHFT 0x14 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_WR_ADDR_BMSK 0xffc00 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_WR_ADDR_SHFT 0xa +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RD_ADDR_BMSK 0x3ff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RD_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000540) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000584) +#define HWIO_IPA_HPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000590) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000598) +#define HWIO_IPA_DPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a4) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_IN) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_NTF_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000624) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK 0x7ffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK \ + 0x4000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000750) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000778) +#define HWIO_IPA_SPARE_REG_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_1_IN in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, \ + HWIO_IPA_SPARE_REG_1_RMSK) +#define HWIO_IPA_SPARE_REG_1_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_1_OUT(v) out_dword(HWIO_IPA_SPARE_REG_1_ADDR, v) +#define HWIO_IPA_SPARE_REG_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_1_IN) +#define HWIO_IPA_SPARE_REG_1_GENERAL_CONFIG_BMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_1_GENERAL_CONFIG_SHFT 0x0 +#define HWIO_IPA_SPARE_REG_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_2_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_2_IN in_dword_masked(HWIO_IPA_SPARE_REG_2_ADDR, \ + HWIO_IPA_SPARE_REG_2_RMSK) +#define HWIO_IPA_SPARE_REG_2_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_2_OUT(v) out_dword(HWIO_IPA_SPARE_REG_2_ADDR, v) +#define HWIO_IPA_SPARE_REG_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_2_IN) +#define HWIO_IPA_SPARE_REG_2_GENERAL_CONFIG_BMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_2_GENERAL_CONFIG_SHFT 0x0 +#define HWIO_IPA_GSI_CONF_ADDR (IPA_DEBUG_REG_BASE + 0x00000790) +#define HWIO_IPA_GSI_CONF_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000790) +#define HWIO_IPA_GSI_CONF_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000790) +#define HWIO_IPA_GSI_CONF_RMSK 0x1 +#define HWIO_IPA_GSI_CONF_ATTR 0x3 +#define HWIO_IPA_GSI_CONF_IN in_dword_masked(HWIO_IPA_GSI_CONF_ADDR, \ + HWIO_IPA_GSI_CONF_RMSK) +#define HWIO_IPA_GSI_CONF_INM(m) in_dword_masked(HWIO_IPA_GSI_CONF_ADDR, m) +#define HWIO_IPA_GSI_CONF_OUT(v) out_dword(HWIO_IPA_GSI_CONF_ADDR, v) +#define HWIO_IPA_GSI_CONF_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_CONF_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_CONF_IN) +#define HWIO_IPA_GSI_CONF_IPA_GSI_SELECT_BMSK 0x1 +#define HWIO_IPA_GSI_CONF_IPA_GSI_SELECT_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_RMSK 0x11f0f +#define HWIO_IPA_ENDP_GSI_CFG1_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG1_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG1_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG1_n_CHID_BMSK 0x1f00 +#define HWIO_IPA_ENDP_GSI_CFG1_n_CHID_SHFT 0x8 +#define HWIO_IPA_ENDP_GSI_CFG1_n_EE_BMSK 0xf +#define HWIO_IPA_ENDP_GSI_CFG1_n_EE_SHFT 0x0 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000920) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK 0x1ff01ff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_SIZE_BMSK 0x1ff0000 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_START_ADDR_BMSK 0x1ff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_START_ADDR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK 0x1ff03ff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_SIZE_BMSK 0x1ff0000 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_START_ADDR_BMSK 0x3ff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_START_ADDR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_RMSK 0x8000ffff +#define HWIO_IPA_ENDP_GSI_CFG2_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG2_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG2_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG2_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG2_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_INIT_ENDP_BMSK 0x80000000 +#define HWIO_IPA_ENDP_GSI_CFG2_n_INIT_ENDP_SHFT 0x1f +#define HWIO_IPA_ENDP_GSI_CFG2_n_PUBLISH_THRESHOLD_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG2_n_PUBLISH_THRESHOLD_SHFT 0x0 +#define HWIO_IPA_CTXH_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000afc) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m, n) (IPA_DEBUG_REG_BASE + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_PHYS(m, n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OFFS(m, n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define IPA_EE_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00043000) +#define IPA_EE_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00043000) +#define IPA_EE_REG_BASE_OFFS 0x00043000 +#define HWIO_IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000008 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_RMSK 0x3fffffd +#define HWIO_IPA_IRQ_STTS_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), \ + HWIO_IPA_IRQ_STTS_EE_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_BMSK 0x2000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_SHFT 0x19 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_BMSK 0x1000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_SHFT 0x18 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_BMSK 0x800000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_SHFT 0x17 +#define HWIO_IPA_IRQ_STTS_EE_n_DCMP_IRQ_BMSK 0x400000 +#define HWIO_IPA_IRQ_STTS_EE_n_DCMP_IRQ_SHFT 0x16 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_BMSK 0x200000 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_SHFT 0x15 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_BMSK 0x100000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_SHFT 0x14 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_BMSK 0x80000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_SHFT 0x13 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_BMSK 0x40000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_SHFT 0x12 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_BMSK 0x20000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_SHFT 0x11 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_BMSK 0x10000 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_SHFT 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_BMSK 0x8000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_SHFT 0xf +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_BMSK 0x4000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_SHFT 0xe +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_BMSK 0x2000 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_SHFT 0xd +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_BMSK 0x1000 +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_SHFT 0xc +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_BMSK 0x800 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_SHFT 0xb +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_BMSK 0x400 +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_SHFT 0xa +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_BMSK 0x200 +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_SHFT 0x9 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_BMSK 0x100 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_SHFT 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_BMSK 0x80 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_SHFT 0x7 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_BMSK 0x40 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_SHFT 0x6 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_BMSK 0x20 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_SHFT 0x5 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_BMSK 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_SHFT 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_BMSK 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_SHFT 0x3 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_BMSK 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_SHFT 0x2 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_BMSK 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_SHFT 0x0 +#define HWIO_IPA_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_RMSK 0x3fffffd +#define HWIO_IPA_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_IRQ_EN_EE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_BMSK 0x2000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_SHFT 0x19 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_BMSK 0x1000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_SHFT 0x18 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_BMSK 0x800000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_SHFT 0x17 +#define HWIO_IPA_IRQ_EN_EE_n_DCMP_IRQ_EN_BMSK 0x400000 +#define HWIO_IPA_IRQ_EN_EE_n_DCMP_IRQ_EN_SHFT 0x16 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_BMSK 0x200000 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_SHFT 0x15 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_BMSK 0x100000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_SHFT 0x14 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_BMSK 0x80000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_SHFT 0x13 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_BMSK 0x40000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_SHFT 0x12 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_BMSK 0x20000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_SHFT 0x11 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_BMSK 0x10000 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_SHFT 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_BMSK 0x8000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_SHFT 0xf +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_BMSK 0x4000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_SHFT 0xe +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_BMSK 0x2000 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_SHFT 0xd +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_BMSK 0x1000 +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_SHFT 0xc +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_BMSK 0x800 +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_SHFT 0xb +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_BMSK 0x400 +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_SHFT 0xa +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_BMSK 0x200 +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_SHFT 0x9 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_BMSK 0x100 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_SHFT 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_BMSK 0x80 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_SHFT 0x7 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_SHFT 0x2 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_SHFT 0x0 +#define HWIO_IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000018 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_RMSK 0x8000f1ff +#define HWIO_IPA_SNOC_FEC_EE_n_MAXn 3 +#define HWIO_IPA_SNOC_FEC_EE_n_ATTR 0x1 +#define HWIO_IPA_SNOC_FEC_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + HWIO_IPA_SNOC_FEC_EE_n_RMSK) +#define HWIO_IPA_SNOC_FEC_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_BMSK 0x80000000 +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_SHFT 0x1f +#define HWIO_IPA_SNOC_FEC_EE_n_TID_BMSK 0xf000 +#define HWIO_IPA_SNOC_FEC_EE_n_TID_SHFT 0xc +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_BMSK 0x100 +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_SHFT 0x8 +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_BMSK 0xff +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_SHFT 0x0 +#define HWIO_IPA_IRQ_EE_UC_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000020 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ADDR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_ADDR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_SHFT 0x0 +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000024 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000028 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ATTR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_ATTR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ATTR_EE_n_MISC2_BMSK 0xffffe000 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC2_SHFT 0xd +#define HWIO_IPA_FEC_ATTR_EE_n_PIPE_NUM_BMSK 0x1f00 +#define HWIO_IPA_FEC_ATTR_EE_n_PIPE_NUM_SHFT 0x8 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC1_BMSK 0xc0 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC1_SHFT 0x6 +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_SHFT 0x0 +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK 0x7fffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR (IPA_EE_REG_BASE + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR (IPA_EE_REG_BASE + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR (IPA_EE_REG_BASE + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK 0x1ffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_IN) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR (IPA_EE_REG_BASE + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_BMSK 0xffff0000 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_ADDR (IPA_EE_REG_BASE + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_ADDR (IPA_EE_REG_BASE + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c4) +#define HWIO_IPA_SECURED_PIPES_ADDR (IPA_EE_REG_BASE + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_PHYS (IPA_EE_REG_BASE_PHYS + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_OFFS (IPA_EE_REG_BASE_OFFS + 0x000010d0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_ADDR (IPA_EE_REG_BASE + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010d4) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR (IPA_EE_REG_BASE + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR (IPA_EE_REG_BASE + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001204) +#define HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00002048 + \ + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR (IPA_EE_REG_BASE + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00002058) +#define HWIO_IPA_UCP_RESUME_ADDR (IPA_EE_REG_BASE + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a0) +#define HWIO_IPA_PROC_UCP_CFG_ADDR (IPA_EE_REG_BASE + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR (IPA_EE_REG_BASE + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR (IPA_EE_REG_BASE + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR (IPA_EE_REG_BASE + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030b0) +#define IPA_UC_IPA_UC_PER_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00070000) +#define IPA_UC_IPA_UC_PER_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x00070000) +#define IPA_UC_IPA_UC_PER_REG_BASE_OFFS 0x00070000 +#define HWIO_IPA_UC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_UC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_UC_CONTROL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000004) +#define HWIO_IPA_UC_CONTROL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000004) +#define HWIO_IPA_UC_CONTROL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000004) +#define HWIO_IPA_UC_BASE_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000000c) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_UC_PEND_IRQ_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_UC_TRACE_BUFFER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000018) +#define HWIO_IPA_UC_PC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000001c) +#define HWIO_IPA_UC_PC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_UC_PC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK 0x1ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_IN) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_BMSK 0x1ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LENGTH_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_RMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LENGTH_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + HWIO_IPA_UC_QMB_LENGTH_RMSK) +#define HWIO_IPA_UC_QMB_LENGTH_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LENGTH_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LENGTH_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LENGTH_IN) +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_BMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_RMSK 0x31 +#define HWIO_IPA_UC_QMB_TRIGGER_ATTR 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + HWIO_IPA_UC_QMB_TRIGGER_RMSK) +#define HWIO_IPA_UC_QMB_TRIGGER_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_TRIGGER_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_TRIGGER_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_TRIGGER_IN) +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_BMSK 0x30 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_SHFT 0x4 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_POSTED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_POSTED_FVAL 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_COMPLETE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_COMPLETE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_BMSK 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_READ_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_WRITE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_RMSK 0x11113f +#define HWIO_IPA_UC_QMB_PENDING_TID_ATTR 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + HWIO_IPA_UC_QMB_PENDING_TID_RMSK) +#define HWIO_IPA_UC_QMB_PENDING_TID_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_SHFT 0x14 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_SHFT 0x10 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_SHFT 0xc +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_BMSK 0x100 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_SHFT 0x8 +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_MISC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_RMSK 0xf11333ff +#define HWIO_IPA_UC_QMB_MISC_ATTR 0x3 +#define HWIO_IPA_UC_QMB_MISC_IN in_dword_masked(HWIO_IPA_UC_QMB_MISC_ADDR, \ + HWIO_IPA_UC_QMB_MISC_RMSK) +#define HWIO_IPA_UC_QMB_MISC_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_MISC_OUT(v) out_dword(HWIO_IPA_UC_QMB_MISC_ADDR, v) +#define HWIO_IPA_UC_QMB_MISC_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_MISC_IN) +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_SHFT 0x1f +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_SHFT 0x1e +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_BMSK 0x20000000 +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_SHFT 0x1d +#define HWIO_IPA_UC_QMB_MISC_SWAP_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_MISC_SWAP_SHFT 0x1c +#define HWIO_IPA_UC_QMB_MISC_OOOWR_BMSK 0x1000000 +#define HWIO_IPA_UC_QMB_MISC_OOOWR_SHFT 0x18 +#define HWIO_IPA_UC_QMB_MISC_OOORD_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_MISC_OOORD_SHFT 0x14 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_BMSK 0x30000 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_BMSK 0x3000 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_SHFT 0xc +#define HWIO_IPA_UC_QMB_MISC_USER_BMSK 0x3ff +#define HWIO_IPA_UC_QMB_MISC_USER_SHFT 0x0 +#define HWIO_IPA_UC_QMB_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_RMSK 0x1fff1fff +#define HWIO_IPA_UC_QMB_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_STATUS_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + HWIO_IPA_UC_QMB_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_SHFT 0x1c +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_BMSK 0xf000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_SHFT 0x18 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_BMSK 0xf00000 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_SHFT 0x14 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_BMSK 0xf0000 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_SHFT 0xc +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_BMSK 0xf00 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_SHFT 0x8 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_BMSK 0xf0 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_SHFT 0x4 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_BMSK 0xf +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL \ + 0x6 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_HWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_UC_SWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_UC_VUIC_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_EVENTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000600) +#define HWIO_IPA_UC_EVENTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_UC_EVENTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000710) +#define HWIO_IPA_UC_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_UC_PC_RESTORE_WR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_RD_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_UC_SPARE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00001ffc) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h new file mode 100644 index 000000000000..6c7eceb32573 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h @@ -0,0 +1,2817 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HWIO_DEF_H_) +#define _IPA_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ + +struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 reserved0 : 7; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s { + u32 shram : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s { + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s { + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s { + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s { + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 reserved0 : 1; + u32 erindex : 5; + u32 reserved1 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 use_escape_buf_only : 1; + u32 reserved1 : 21; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 17; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s { + u32 error_log : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_hw_version_s { + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; +union ipa_hwio_def_ipa_comp_hw_version_u { + struct ipa_hwio_def_ipa_comp_hw_version_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_cfg_s { + u32 enable : 1; + u32 gsi_snoc_bypass_dis : 1; + u32 gen_qmb_0_snoc_bypass_dis : 1; + u32 gen_qmb_1_snoc_bypass_dis : 1; + u32 ipa_dcmp_fast_clk_en : 1; + u32 ipa_qmb_select_by_address_cons_en : 1; + u32 ipa_qmb_select_by_address_prod_en : 1; + u32 gsi_multi_inorder_rd_dis : 1; + u32 gsi_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_multi_inorder_rd_dis : 1; + u32 gen_qmb_1_multi_inorder_rd_dis : 1; + u32 gen_qmb_0_multi_inorder_wr_dis : 1; + u32 gen_qmb_1_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_multi_axi_masters_dis : 1; + u32 ipa_qmb_select_by_address_global_en : 1; + u32 ipa_atomic_fetcher_arb_lock_dis : 4; + u32 reserved0 : 11; +}; +union ipa_hwio_def_ipa_comp_cfg_u { + struct ipa_hwio_def_ipa_comp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_route_s { + u32 route_dis : 1; + u32 route_def_pipe : 5; + u32 route_def_hdr_table : 1; + u32 route_def_hdr_ofst : 10; + u32 route_frag_def_pipe : 5; + u32 reserved0 : 2; + u32 route_def_retain_hdr : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_route_u { + struct ipa_hwio_def_ipa_route_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_tag_timer_s { + u32 tag_timer : 24; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_tag_timer_u { + struct ipa_hwio_def_ipa_tag_timer_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_proc_iph_cfg_s { + u32 iph_threshold : 2; + u32 iph_pipelining_disable : 1; + u32 iph_time_cnt_clk_src : 1; + u32 status_from_iph_frst_always : 1; + u32 iph_nat_blind_invalidate_tport_offset_disable : 1; + u32 pipestage_overlap_disable : 1; + u32 ftch_dcph_overlap_enable : 1; + u32 iph_pkt_parser_protocol_stop_enable : 1; + u32 iph_pkt_parser_protocol_stop_hop : 1; + u32 iph_pkt_parser_protocol_stop_dest : 1; + u32 iph_pkt_parser_ihl_to_2nd_frag_en : 1; + u32 reserved0 : 4; + u32 iph_pkt_parser_protocol_stop_value : 8; + u32 reserved1 : 8; +}; +union ipa_hwio_def_ipa_proc_iph_cfg_u { + struct ipa_hwio_def_ipa_proc_iph_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_lsb_s { + u32 tod_lsb : 32; +}; +union ipa_hwio_def_ipa_dpl_timer_lsb_u { + struct ipa_hwio_def_ipa_dpl_timer_lsb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_msb_s { + u32 tod_msb : 16; + u32 reserved0 : 15; + u32 timer_en : 1; +}; +union ipa_hwio_def_ipa_dpl_timer_msb_u { + struct ipa_hwio_def_ipa_dpl_timer_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx_wrapper_s { + u32 tx0_idle : 1; + u32 tx1_idle : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_empty : 1; + u32 ipa_prod_bresp_toggle_idle : 1; + u32 ipa_mbim_pkt_fms_idle : 1; + u32 mbim_expiry : 1; + u32 trnseq_force_valid : 1; + u32 pkt_drop_cnt_idle : 1; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_tx_wrapper_u { + struct ipa_hwio_def_ipa_state_tx_wrapper_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx1_s { + u32 last_arbit_type : 2; + u32 next_arbit_type : 2; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_tx1_u { + struct ipa_hwio_def_ipa_state_tx1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_s { + u32 ipa_hps_ftch_state_idle : 1; + u32 ipa_hps_ftch_alloc_state_idle : 1; + u32 ipa_hps_ftch_pkt_state_idle : 1; + u32 ipa_hps_ftch_imm_state_idle : 1; + u32 ipa_hps_ftch_cmplt_state_idle : 1; + u32 ipa_hps_dmar_state_idle : 7; + u32 ipa_hps_dmar_rep_state_idle : 7; + u32 ipa_hps_dmar_slot_state_idle : 7; + u32 ipa_hps_imm_cmd_exec_state_idle : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_state_fetcher_u { + struct ipa_hwio_def_ipa_state_fetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_mask_s { + u32 mask_queue_dmar_uses_queue : 4; + u32 mask_queue_imm_exec : 4; + u32 mask_queue_no_resources_context : 4; + u32 mask_queue_no_resources_hps_dmar : 4; + u32 mask_queue_no_resources_ack_entry : 4; + u32 mask_queue_arb_lock : 4; + u32 mask_queue_step_mode : 4; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_fetcher_mask_u { + struct ipa_hwio_def_ipa_state_fetcher_mask_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_dfetcher_s { + u32 ipa_dps_ftch_pkt_state_idle : 1; + u32 ipa_dps_ftch_cmplt_state_idle : 1; + u32 reserved0 : 2; + u32 ipa_dps_dmar_state_idle : 6; + u32 reserved1 : 2; + u32 ipa_dps_dmar_slot_state_idle : 6; + u32 reserved2 : 14; +}; +union ipa_hwio_def_ipa_state_dfetcher_u { + struct ipa_hwio_def_ipa_state_dfetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_acl_s { + u32 ipa_hps_h_dcph_empty : 1; + u32 ipa_hps_h_dcph_active : 1; + u32 ipa_hps_pkt_parser_empty : 1; + u32 ipa_hps_pkt_parser_active : 1; + u32 ipa_hps_filter_nat_empty : 1; + u32 ipa_hps_filter_nat_active : 1; + u32 ipa_hps_router_empty : 1; + u32 ipa_hps_router_active : 1; + u32 ipa_hps_hdri_empty : 1; + u32 ipa_hps_hdri_active : 1; + u32 ipa_hps_ucp_empty : 1; + u32 ipa_hps_ucp_active : 1; + u32 ipa_hps_enqueuer_empty : 1; + u32 ipa_hps_enqueuer_active : 1; + u32 ipa_dps_d_dcph_empty : 1; + u32 ipa_dps_d_dcph_active : 1; + u32 ipa_dps_dcmp_empty : 1; + u32 ipa_dps_dcmp_active : 1; + u32 ipa_dps_dispatcher_empty : 1; + u32 ipa_dps_dispatcher_active : 1; + u32 ipa_dps_d_dcph_2_empty : 1; + u32 ipa_dps_d_dcph_2_active : 1; + u32 ipa_hps_sequencer_idle : 1; + u32 ipa_dps_sequencer_idle : 1; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_state_acl_u { + struct ipa_hwio_def_ipa_state_acl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_tlv_s { + u32 ipa_gsi_toggle_fsm_idle : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_gsi_tlv_u { + struct ipa_hwio_def_ipa_state_gsi_tlv_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_aos_s { + u32 ipa_gsi_aos_fsm_idle : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_state_gsi_aos_u { + struct ipa_hwio_def_ipa_state_gsi_aos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_if_s { + u32 ipa_gsi_prod_fsm_tx_0 : 2; + u32 ipa_gsi_prod_fsm_tx_1 : 2; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_state_gsi_if_u { + struct ipa_hwio_def_ipa_state_gsi_if_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_skip_s { + u32 ipa_gsi_skip_fsm : 26; + u32 reserved0 : 6; +}; +union ipa_hwio_def_ipa_state_gsi_skip_u { + struct ipa_hwio_def_ipa_state_gsi_skip_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_s { + u32 rx_wait : 1; + u32 rx_idle : 1; + u32 tx_idle : 1; + u32 reserved0 : 1; + u32 bam_gsi_idle : 1; + u32 ipa_status_sniffer_idle : 1; + u32 ipa_noc_idle : 1; + u32 aggr_idle : 1; + u32 mbim_aggr_idle : 1; + u32 ipa_rsrc_mngr_db_empty : 1; + u32 ipa_rsrc_state_idle : 1; + u32 ipa_ackmngr_db_empty : 1; + u32 ipa_ackmngr_state_idle : 1; + u32 ipa_tx_ackq_full : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_idle : 1; + u32 reserved1 : 1; + u32 ipa_ntf_tx_empty : 1; + u32 ipa_tx_ackq_empty : 1; + u32 ipa_uc_ackq_empty : 1; + u32 ipa_rx_ackq_empty : 1; + u32 ipa_tx_commander_cmdq_empty : 1; + u32 ipa_rx_splt_cmdq_0_empty : 1; + u32 ipa_rx_splt_cmdq_1_empty : 1; + u32 ipa_rx_splt_cmdq_2_empty : 1; + u32 reserved2 : 2; + u32 ipa_rx_hps_empty : 1; + u32 ipa_hps_dps_empty : 1; + u32 ipa_dps_tx_empty : 1; + u32 ipa_uc_rx_hnd_cmdq_empty : 1; +}; +union ipa_hwio_def_ipa_state_u { + struct ipa_hwio_def_ipa_state_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_rx_active_s { + u32 endpoints : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_rx_active_u { + struct ipa_hwio_def_ipa_state_rx_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx0_s { + u32 last_arbit_type : 2; + u32 next_arbit_type : 2; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_tx0_u { + struct ipa_hwio_def_ipa_state_tx0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_aggr_active_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_state_aggr_active_u { + struct ipa_hwio_def_ipa_state_aggr_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_en_s { + u32 ipv6_router_hash_en : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_en : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_en : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_en : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_en_u { + struct ipa_hwio_def_ipa_filt_rout_hash_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_flush_s { + u32 ipv6_router_hash_flush : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_flush : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_flush : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_flush : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_flush_u { + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_filter_init_values_s { + u32 ip_v4_filter_init_hashed_addr : 16; + u32 ip_v4_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_filter_init_values_s { + u32 ip_v6_filter_init_hashed_addr : 16; + u32 ip_v6_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_route_init_values_s { + u32 ip_v4_route_init_hashed_addr : 16; + u32 ip_v4_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_route_init_values_u { + struct ipa_hwio_def_ipa_ipv4_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_route_init_values_s { + u32 ip_v6_route_init_hashed_addr : 16; + u32 ip_v6_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_route_init_values_u { + struct ipa_hwio_def_ipa_ipv6_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_bcr_s { + u32 bcr_cmdq_l_lack_one_entry : 1; + u32 bcr_tx_not_using_bresp : 1; + u32 bcr_tx_suspend_irq_only_assert_once_per_pkt : 1; + u32 bcr_suspend_l2_irq : 1; + u32 bcr_holb_drop_l2_irq : 1; + u32 bcr_dual_tx : 1; + u32 bcr_enable_filter_data_cache : 1; + u32 bcr_notif_priority_over_zlt : 1; + u32 bcr_filter_prefetch_en : 1; + u32 bcr_router_prefetch_en : 1; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_bcr_u { + struct ipa_hwio_def_ipa_bcr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_bam_activated_ports_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_bam_activated_ports_u { + struct ipa_hwio_def_ipa_bam_activated_ports_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 29; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 14; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s { + u32 src_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s { + u32 src_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 src_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s { + u32 dst_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s { + u32 dst_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 dst_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_grp_cfg_s { + u32 src_grp_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_special_index : 2; + u32 reserved1 : 2; + u32 dst_pipe_special_valid : 1; + u32 reserved2 : 3; + u32 dst_pipe_special_index : 5; + u32 reserved3 : 3; + u32 dst_grp_special_valid : 1; + u32 reserved4 : 3; + u32 dst_grp_special_index : 2; + u32 reserved5 : 6; +}; +union ipa_hwio_def_ipa_rsrc_grp_cfg_u { + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_n_s { + u32 endp_suspend : 1; + u32 endp_delay : 1; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s { + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_cfg_n_s { + u32 frag_offload_en : 1; + u32 cs_offload_en : 2; + u32 cs_metadata_hdr_offset : 4; + u32 reserved0 : 1; + u32 gen_qmb_master_sel : 1; + u32 reserved1 : 23; +}; +union ipa_hwio_def_ipa_endp_init_cfg_n_u { + struct ipa_hwio_def_ipa_endp_init_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_nat_n_s { + u32 nat_en : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_nat_n_u { + struct ipa_hwio_def_ipa_endp_init_nat_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_n_s { + u32 hdr_len : 6; + u32 hdr_ofst_metadata_valid : 1; + u32 hdr_ofst_metadata : 6; + u32 hdr_additional_const_len : 6; + u32 hdr_ofst_pkt_size_valid : 1; + u32 hdr_ofst_pkt_size : 6; + u32 hdr_a5_mux : 1; + u32 hdr_len_inc_deagg_hdr : 1; + u32 hdr_metadata_reg_valid : 1; + u32 reserved0 : 3; +}; +union ipa_hwio_def_ipa_endp_init_hdr_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s { + u32 hdr_endianness : 1; + u32 hdr_total_len_or_pad_valid : 1; + u32 hdr_total_len_or_pad : 1; + u32 hdr_payload_len_inc_padding : 1; + u32 hdr_total_len_or_pad_offset : 6; + u32 hdr_pad_to_alignment : 4; + u32 reserved0 : 18; +}; +union ipa_hwio_def_ipa_endp_init_hdr_ext_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s { + u32 metadata_mask : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s { + u32 metadata : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_mode_n_s { + u32 mode : 3; + u32 reserved0 : 1; + u32 dest_pipe_index : 5; + u32 reserved1 : 3; + u32 byte_threshold : 16; + u32 pipe_replicate_en : 1; + u32 pad_en : 1; + u32 hdr_ftch_disable : 1; + u32 reserved2 : 1; +}; +union ipa_hwio_def_ipa_endp_init_mode_n_u { + struct ipa_hwio_def_ipa_endp_init_mode_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_aggr_n_s { + u32 aggr_en : 2; + u32 aggr_type : 3; + u32 aggr_byte_limit : 5; + u32 aggr_time_limit : 5; + u32 aggr_pkt_limit : 6; + u32 aggr_sw_eof_active : 1; + u32 aggr_force_close : 1; + u32 reserved0 : 1; + u32 aggr_hard_byte_limit_enable : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_init_aggr_n_u { + struct ipa_hwio_def_ipa_endp_init_aggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s { + u32 en : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_en_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s { + u32 timer : 32; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_timer_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_deaggr_n_s { + u32 deaggr_hdr_len : 6; + u32 syspipe_err_detection : 1; + u32 packet_offset_valid : 1; + u32 packet_offset_location : 6; + u32 ignore_min_pkt_err : 1; + u32 reserved0 : 1; + u32 max_packet_len : 16; +}; +union ipa_hwio_def_ipa_endp_init_deaggr_n_u { + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s { + u32 rsrc_grp : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_rsrc_grp_n_u { + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_seq_n_s { + u32 hps_seq_type : 4; + u32 dps_seq_type : 4; + u32 hps_rep_seq_type : 4; + u32 dps_rep_seq_type : 4; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_endp_init_seq_n_u { + struct ipa_hwio_def_ipa_endp_init_seq_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_status_n_s { + u32 status_en : 1; + u32 status_endp : 5; + u32 reserved0 : 2; + u32 status_location : 1; + u32 status_pkt_suppress : 1; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_endp_status_n_u { + struct ipa_hwio_def_ipa_endp_status_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s { + u32 filter_hash_msk_src_id : 1; + u32 filter_hash_msk_src_ip_add : 1; + u32 filter_hash_msk_dst_ip_add : 1; + u32 filter_hash_msk_src_port : 1; + u32 filter_hash_msk_dst_port : 1; + u32 filter_hash_msk_protocol : 1; + u32 filter_hash_msk_metadata : 1; + u32 reserved0 : 9; + u32 router_hash_msk_src_id : 1; + u32 router_hash_msk_src_ip_add : 1; + u32 router_hash_msk_dst_ip_add : 1; + u32 router_hash_msk_src_port : 1; + u32 router_hash_msk_dst_port : 1; + u32 router_hash_msk_protocol : 1; + u32 router_hash_msk_metadata : 1; + u32 reserved1 : 9; +}; +union ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_u { + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s { + u32 rsrc_grp_sel : 2; + u32 reserved0 : 2; + u32 rsrc_type_sel : 3; + u32 reserved1 : 1; + u32 rsrc_id_sel : 6; + u32 reserved2 : 18; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s { + u32 rsrc_occupied : 1; + u32 rsrc_next_valid : 1; + u32 reserved0 : 2; + u32 rsrc_next_index : 6; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s { + u32 rsrc_list_valid : 1; + u32 rsrc_list_hold : 1; + u32 reserved0 : 2; + u32 rsrc_list_head_rsrc : 6; + u32 reserved1 : 2; + u32 rsrc_list_head_cnt : 7; + u32 reserved2 : 1; + u32 rsrc_list_entry_cnt : 7; + u32 reserved3 : 5; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_debug_data_sel_s { + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 pipe_select : 5; + u32 reserved0 : 3; + u32 uc_dap_en : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_debug_data_sel_u { + struct ipa_hwio_def_ipa_debug_data_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_debug_data_s { + u32 debug_data : 32; +}; +union ipa_hwio_def_ipa_debug_data_u { + struct ipa_hwio_def_ipa_debug_data_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_testbus_sel_s { + u32 testbus_en : 1; + u32 reserved0 : 3; + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 pipe_select : 5; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_testbus_sel_u { + struct ipa_hwio_def_ipa_testbus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_step_mode_status_s { + u32 hw_en : 32; +}; +union ipa_hwio_def_ipa_step_mode_status_u { + struct ipa_hwio_def_ipa_step_mode_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_s { + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 5; + u32 reserved2 : 3; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved3 : 10; +}; +union ipa_hwio_def_ipa_log_u { + struct ipa_hwio_def_ipa_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 skip_ddr_dma : 1; + u32 reserved0 : 14; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s { + u32 read_ptr : 14; + u32 reserved0 : 2; + u32 write_ptr : 14; + u32 reserved1 : 1; + u32 skip_ddr_wrap_happened : 1; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_cmd_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_0_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_0_status_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_0_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_cmd_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_1_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_1_status_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_1_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_cmd_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_2_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_2_status_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_2_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_tx_commander_cmdq_status_u { + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 2; + u32 reserved0 : 1; + u32 rd_req : 1; + u32 reserved1 : 26; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s { + u32 cmdq_empty : 4; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_count_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s { + u32 client_0_min_depth : 4; + u32 reserved0 : 4; + u32 client_1_min_depth : 4; + u32 reserved1 : 4; + u32 client_2_min_depth : 4; + u32 reserved2 : 4; + u32 client_3_min_depth : 4; + u32 reserved3 : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s { + u32 client_0_max_depth : 4; + u32 reserved0 : 4; + u32 client_1_max_depth : 4; + u32 reserved1 : 4; + u32 client_2_max_depth : 4; + u32 reserved2 : 4; + u32 client_3_max_depth : 4; + u32 reserved3 : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 5; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s { + u32 fifo_count : 5; + u32 reserved0 : 27; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_count_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 3; + u32 reserved0 : 2; + u32 rd_req : 1; + u32 reserved1 : 24; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s { + u32 cmdq_empty : 8; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_en_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s { + u32 all_cli_mux_concat : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s { + u32 src_group_sel : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s { + u32 ipa_gsi_fifo_status_port_sel : 5; + u32 ipa_gsi_fifo_status_en : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u { + struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s { + u32 rd_addr : 9; + u32 wr_addr : 9; + u32 empty : 1; + u32 reserved0 : 11; + u32 fsm_state : 2; +}; +union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_s { + u32 rd_addr_pub : 9; + u32 wr_addr : 9; + u32 empty_pub : 1; + u32 reserved0 : 11; + u32 fsm_state : 2; +}; +union ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s { + u32 rd_addr : 10; + u32 wr_addr : 10; + u32 empty : 1; + u32 reserved0 : 8; + u32 fsm_state : 3; +}; +union ipa_hwio_def_ipa_gsi_aos_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_1_s { + u32 general_config : 32; +}; +union ipa_hwio_def_ipa_spare_reg_1_u { + struct ipa_hwio_def_ipa_spare_reg_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_2_s { + u32 general_config : 32; +}; +union ipa_hwio_def_ipa_spare_reg_2_u { + struct ipa_hwio_def_ipa_spare_reg_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_conf_s { + u32 ipa_gsi_select : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_conf_u { + struct ipa_hwio_def_ipa_gsi_conf_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s { + u32 ee : 4; + u32 reserved0 : 4; + u32 chid : 5; + u32 reserved1 : 3; + u32 endp_en : 1; + u32 reserved2 : 15; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg1_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s { + u32 tlv_fifo_start_addr : 9; + u32 reserved0 : 7; + u32 tlv_fifo_size : 9; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s { + u32 aos_fifo_start_addr : 10; + u32 reserved0 : 6; + u32 aos_fifo_size : 9; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg2_n_s { + u32 publish_threshold : 16; + u32 reserved0 : 15; + u32 init_endp : 1; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg2_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ctxh_ctrl_s { + u32 ctxh_lock_id : 4; + u32 reserved0 : 27; + u32 ctxh_lock : 1; +}; +union ipa_hwio_def_ipa_ctxh_ctrl_u { + struct ipa_hwio_def_ipa_ctxh_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_stts_ee_n_s { + u32 bad_snoc_access_irq : 1; + u32 reserved0 : 1; + u32 uc_irq_0 : 1; + u32 uc_irq_1 : 1; + u32 uc_irq_2 : 1; + u32 uc_irq_3 : 1; + u32 uc_in_q_not_empty_irq : 1; + u32 uc_rx_cmd_q_not_full_irq : 1; + u32 proc_to_uc_ack_q_not_empty_irq : 1; + u32 rx_err_irq : 1; + u32 deaggr_err_irq : 1; + u32 tx_err_irq : 1; + u32 step_mode_irq : 1; + u32 proc_err_irq : 1; + u32 tx_suspend_irq : 1; + u32 tx_holb_drop_irq : 1; + u32 bam_gsi_idle_irq : 1; + u32 pipe_yellow_marker_below_irq : 1; + u32 pipe_red_marker_below_irq : 1; + u32 pipe_yellow_marker_above_irq : 1; + u32 pipe_red_marker_above_irq : 1; + u32 ucp_irq : 1; + u32 dcmp_irq : 1; + u32 gsi_ee_irq : 1; + u32 gsi_ipa_if_tlv_rcvd_irq : 1; + u32 gsi_uc_irq : 1; + u32 reserved1 : 6; +}; +union ipa_hwio_def_ipa_irq_stts_ee_n_u { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_en_ee_n_s { + u32 bad_snoc_access_irq_en : 1; + u32 reserved0 : 1; + u32 uc_irq_0_irq_en : 1; + u32 uc_irq_1_irq_en : 1; + u32 uc_irq_2_irq_en : 1; + u32 uc_irq_3_irq_en : 1; + u32 uc_in_q_not_empty_irq_en : 1; + u32 uc_rx_cmd_q_not_full_irq_en : 1; + u32 proc_to_uc_ack_q_not_empty_irq_en : 1; + u32 rx_err_irq_en : 1; + u32 deaggr_err_irq_en : 1; + u32 tx_err_irq_en : 1; + u32 step_mode_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 tx_suspend_irq_en : 1; + u32 tx_holb_drop_irq_en : 1; + u32 bam_gsi_idle_irq_en : 1; + u32 pipe_yellow_marker_below_irq_en : 1; + u32 pipe_red_marker_below_irq_en : 1; + u32 pipe_yellow_marker_above_irq_en : 1; + u32 pipe_red_marker_above_irq_en : 1; + u32 ucp_irq_en : 1; + u32 dcmp_irq_en : 1; + u32 gsi_ee_irq_en : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_en : 1; + u32 gsi_uc_irq_en : 1; + u32 reserved1 : 6; +}; +union ipa_hwio_def_ipa_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_snoc_fec_ee_n_s { + u32 client : 8; + u32 qmb_index : 1; + u32 reserved0 : 3; + u32 tid : 4; + u32 reserved1 : 15; + u32 read_not_write : 1; +}; +union ipa_hwio_def_ipa_snoc_fec_ee_n_u { + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_addr_ee_n_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_fec_addr_ee_n_u { + struct ipa_hwio_def_ipa_fec_addr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_attr_ee_n_s { + u32 opcode : 6; + u32 misc1 : 2; + u32 pipe_num : 5; + u32 misc2 : 19; +}; +union ipa_hwio_def_ipa_fec_attr_ee_n_u { + struct ipa_hwio_def_ipa_fec_attr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_suspend_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_suspend_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_log_buf_status_cfg_u { + struct ipa_hwio_def_ipa_log_buf_status_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s { + u32 read_ptr : 16; + u32 write_ptr : 16; +}; +union ipa_hwio_def_ipa_log_buf_status_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s { + u32 addr_msb : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_local_addr_s { + u32 addr : 17; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_uc_qmb_local_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_length_s { + u32 length : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_uc_qmb_length_u { + struct ipa_hwio_def_ipa_uc_qmb_length_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_trigger_s { + u32 direction : 1; + u32 reserved0 : 3; + u32 posting : 2; + u32 reserved1 : 26; +}; +union ipa_hwio_def_ipa_uc_qmb_trigger_u { + struct ipa_hwio_def_ipa_uc_qmb_trigger_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error_bus : 1; + u32 reserved1 : 3; + u32 error_max_os : 1; + u32 reserved2 : 3; + u32 error_max_comp : 1; + u32 reserved3 : 3; + u32 error_security : 1; + u32 reserved4 : 11; +}; +union ipa_hwio_def_ipa_uc_qmb_pending_tid_u { + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_misc_s { + u32 user : 10; + u32 reserved0 : 2; + u32 rd_priority : 2; + u32 reserved1 : 2; + u32 wr_priority : 2; + u32 reserved2 : 2; + u32 ooord : 1; + u32 reserved3 : 3; + u32 ooowr : 1; + u32 reserved4 : 3; + u32 swap : 1; + u32 irq_coal : 1; + u32 posted_stall : 1; + u32 qmb_hready_bcr : 1; +}; +union ipa_hwio_def_ipa_uc_qmb_misc_u { + struct ipa_hwio_def_ipa_uc_qmb_misc_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_status_s { + u32 max_outstanding_rd : 4; + u32 outstanding_rd_cnt : 4; + u32 completed_rd_cnt : 4; + u32 completed_rd_fifo_full : 1; + u32 reserved0 : 3; + u32 max_outstanding_wr : 4; + u32 outstanding_wr_cnt : 4; + u32 completed_wr_cnt : 4; + u32 completed_wr_fifo_full : 1; + u32 reserved1 : 3; +}; +union ipa_hwio_def_ipa_uc_qmb_status_u { + struct ipa_hwio_def_ipa_uc_qmb_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s { + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_bus_attrib_u { + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_pkt_cntxt.h b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_pkt_cntxt.h new file mode 100644 index 000000000000..eaf77af446a2 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_pkt_cntxt.h @@ -0,0 +1,190 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_PKT_CNTXT_H_) +#define _IPA_PKT_CNTXT_H_ + +#define IPA_HW_PKT_CTNTX_MAX 0x10 +#define IPA_HW_NUM_SAVE_PKT_CTNTX 0x8 +#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00 +#define IPA_HW_PKT_CTNTX_SIZE (sizeof(ipa_pkt_ctntx_opcode_state_s) + \ + sizeof(ipa_pkt_ctntx_u)) + +/* + * Packet Context States + */ +enum ipa_hw_pkt_cntxt_state_e { + IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP, + IPA_HW_PKT_CNTXT_STATE_H_DCPH, + IPA_HW_PKT_CNTXT_STATE_PKT_PARSER, + IPA_HW_PKT_CNTXT_STATE_FILTER_NAT, + IPA_HW_PKT_CNTXT_STATE_ROUTER, + IPA_HW_PKT_CNTXT_STATE_HDRI, + IPA_HW_PKT_CNTXT_STATE_UCP, + IPA_HW_PKT_CNTXT_STATE_ENQUEUER, + IPA_HW_PKT_CNTXT_STATE_DFETCHER, + IPA_HW_PKT_CNTXT_STATE_D_DCPH, + IPA_HW_PKT_CNTXT_STATE_DISPATCHER, + IPA_HW_PKT_CNTXT_STATE_TX, + IPA_HW_PKT_CNTXT_STATE_TX_ZLT, + IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_DCMP, +}; + +/* + * Packet Context fields as received from VI/Design + */ +struct ipa_pkt_ctntx_s { + u64 opcode : 8; + u64 state : 5; + u64 not_used_1 : 2; + u64 tx_pkt_dma_done : 1; + u64 exc_deagg : 1; + u64 exc_pkt_version : 1; + u64 exc_pkt_len : 1; + u64 exc_threshold : 1; + u64 exc_sw : 1; + u64 exc_nat : 1; + u64 exc_frag_miss : 1; + u64 filter_bypass : 1; + u64 router_bypass : 1; + u64 nat_bypass : 1; + u64 hdri_bypass : 1; + u64 dcph_bypass : 1; + u64 security_credentials_select : 1; + u64 pkt_2nd_pass : 1; + u64 xlat_bypass : 1; + u64 dcph_valid : 1; + u64 ucp_on : 1; + u64 replication : 1; + u64 src_status_en : 1; + u64 dest_status_en : 1; + u64 frag_status_en : 1; + u64 eot_dest : 1; + u64 eot_notif : 1; + u64 prev_eot_dest : 1; + u64 src_hdr_len : 8; + u64 tx_valid_sectors : 8; + u64 rx_flags : 8; + u64 rx_packet_length : 16; + u64 revised_packet_length : 16; + u64 frag_en : 1; + u64 frag_bypass : 1; + u64 frag_process : 1; + u64 notif_pipe : 5; + u64 src_id : 8; + u64 tx_pkt_transferred : 1; + u64 src_pipe : 5; + u64 dest_pipe : 5; + u64 frag_pipe : 5; + u64 ihl_offset : 8; + u64 protocol : 8; + u64 tos : 8; + u64 id : 16; + u64 v6_reserved : 4; + u64 ff : 1; + u64 mf : 1; + u64 pkt_israg : 1; + u64 tx_holb_timer_overflow : 1; + u64 tx_holb_timer_running : 1; + u64 trnseq_0 : 3; + u64 trnseq_1 : 3; + u64 trnseq_2 : 3; + u64 trnseq_3 : 3; + u64 trnseq_4 : 3; + u64 trnseq_ex_length : 8; + u64 trnseq_4_length : 8; + u64 trnseq_4_offset : 8; + u64 dps_tx_pop_cnt : 2; + u64 dps_tx_push_cnt : 2; + u64 vol_ic_dcph_cfg : 1; + u64 vol_ic_tag_stts : 1; + u64 vol_ic_pxkt_init_e : 1; + u64 vol_ic_pkt_init : 1; + u64 tx_holb_counter : 32; + u64 trnseq_0_length : 8; + u64 trnseq_0_offset : 8; + u64 trnseq_1_length : 8; + u64 trnseq_1_offset : 8; + u64 trnseq_2_length : 8; + u64 trnseq_2_offset : 8; + u64 trnseq_3_length : 8; + u64 trnseq_3_offset : 8; + u64 dmar_valid_length : 16; + u64 dcph_valid_length : 16; + u64 frag_hdr_offset : 9; + u64 ip_payload_offset : 9; + u64 frag_rule : 4; + u64 frag_table : 1; + u64 frag_hit : 1; + u64 data_cmdq_ptr : 8; + u64 filter_result : 6; + u64 router_result : 6; + u64 nat_result : 6; + u64 hdri_result : 6; + u64 dcph_result : 6; + u64 dcph_result_valid : 1; + u32 not_used_2 : 4; + u64 tx_pkt_suspended : 1; + u64 tx_pkt_dropped : 1; + u32 not_used_3 : 3; + u64 metadata_valid : 1; + u64 metadata_type : 4; + u64 ul_cs_start_diff : 9; + u64 cs_disable_trlr_vld_bit : 1; + u64 cs_required : 1; + u64 dest_hdr_len : 8; + u64 fr_l : 1; + u64 fl_h : 1; + u64 fr_g : 1; + u64 fr_ret : 1; + u64 fr_rule_id : 10; + u64 rt_l : 1; + u64 rt_h : 1; + u64 rtng_tbl_index : 5; + u64 rt_match : 1; + u64 rt_rule_id : 10; + u64 nat_tbl_index : 13; + u64 nat_type : 2; + u64 hdr_l : 1; + u64 header_offset : 10; + u64 not_used_4 : 1; + u64 filter_result_valid : 1; + u64 router_result_valid : 1; + u64 nat_result_valid : 1; + u64 hdri_result_valid : 1; + u64 not_used_5 : 1; + u64 stream_id : 8; + u64 not_used_6 : 6; + u64 dcph_context_index : 2; + u64 dcph_cfg_size : 16; + u64 dcph_cfg_count : 32; + u64 tag_info : 48; + u64 ucp_cmd_id : 16; + u64 metadata : 32; + u64 ucp_cmd_params : 32; + u64 nat_ip_address : 32; + u64 nat_ip_cs_diff : 16; + u64 frag_dest_pipe : 5; + u64 frag_nat_type : 2; + u64 fragr_ret : 1; + u64 frag_protocol : 8; + u64 src_ip_address : 32; + u64 dest_ip_address : 32; + u64 not_used_7 : 37; + u64 frag_hdr_l : 1; + u64 frag_header_offset : 10; + u64 frag_id : 16; +} __packed; + +#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index cbe406470451..58306d7c05c3 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -4489,8 +4489,10 @@ static int ipa3_panic_notifier(struct notifier_block *this, if (res) IPAERR("uC panic handler failed %d\n", res); - if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) != 0) + if (atomic_read(&ipa3_ctx->ipa3_active_clients.cnt) != 0) { ipahal_print_all_regs(false); + ipa_save_registers(); + } return NOTIFY_DONE; } @@ -5339,6 +5341,13 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, ipa3_ctx->mhi_evid_limits[1] = resource_p->mhi_evid_limits[1]; ipa3_ctx->uc_mailbox17_chk = 0; ipa3_ctx->uc_mailbox17_mismatch = 0; + ipa3_ctx->entire_ipa_block_size = resource_p->entire_ipa_block_size; + ipa3_ctx->do_register_collection_on_crash = + resource_p->do_register_collection_on_crash; + ipa3_ctx->do_testbus_collection_on_crash = + resource_p->do_testbus_collection_on_crash; + ipa3_ctx->do_non_tn_collection_on_crash = + resource_p->do_non_tn_collection_on_crash; WARN(ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_NORMAL, "Non NORMAL IPA HW mode, is this emulation platform ?"); @@ -5456,6 +5465,14 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, ipa3_ctx->mmio, resource_p->ipa_mem_size); + /* + * Setup access for register collection/dump on crash + */ + if (ipa_reg_save_init(0xFF) != 0) { + result = -EFAULT; + goto fail_gsi_map; + } + /* * Since we now know where the transport's registers live, * let's set up access to them. This is done since subseqent @@ -5796,6 +5813,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, fail_ipahal_init: gsi_unmap_base(); fail_gsi_map: + if (ipa3_ctx->reg_collection_base) + iounmap(ipa3_ctx->reg_collection_base); iounmap(ipa3_ctx->mmio); fail_remap: ipa3_disable_clks(); @@ -6264,6 +6283,50 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->emulator_intcntrlr_mem_size); } + result = of_property_read_u32(pdev->dev.of_node, + "qcom,entire-ipa-block-size", + &ipa_drv_res->entire_ipa_block_size); + if (result || ipa_drv_res->entire_ipa_block_size == 0) + ipa_drv_res->entire_ipa_block_size = 0x100000; + + IPADBG(": entire_ipa_block_size = %d\n", + ipa_drv_res->entire_ipa_block_size); + + /* + * We'll read register-collection-on-crash here, but log it + * later below because its value may change based on other + * subsequent dtsi reads...... + */ + ipa_drv_res->do_register_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,register-collection-on-crash"); + /* + * We'll read testbus-collection-on-crash here... + */ + ipa_drv_res->do_testbus_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,testbus-collection-on-crash"); + IPADBG(": doing testbus collection on crash = %s\n", + ipa_drv_res->do_testbus_collection_on_crash ? "True":"False"); + + if (ipa_drv_res->do_testbus_collection_on_crash) + ipa_drv_res->do_register_collection_on_crash = true; + + /* + * We'll read non-tn-collection-on-crash here... + */ + ipa_drv_res->do_non_tn_collection_on_crash = + of_property_read_bool(pdev->dev.of_node, + "qcom,non-tn-collection-on-crash"); + IPADBG(": doing non-tn collection on crash = %s\n", + ipa_drv_res->do_non_tn_collection_on_crash ? "True":"False"); + + if (ipa_drv_res->do_non_tn_collection_on_crash) + ipa_drv_res->do_register_collection_on_crash = true; + + IPADBG(": doing register collection on crash = %s\n", + ipa_drv_res->do_register_collection_on_crash ? "True":"False"); + return 0; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c index b581f75a64f0..8ad07f9a741b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -86,6 +86,9 @@ static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_5[] = { {"qcom,use-rg10-limitation-mitigation", false}, {"qcom,do-not-use-ch-gsi-20", false}, {"qcom,use-ipa-pm", true}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, }; static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_0[] = { @@ -99,6 +102,9 @@ static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_0[] = { {"qcom,use-rg10-limitation-mitigation", false}, {"qcom,do-not-use-ch-gsi-20", false}, {"qcom,use-ipa-pm", false}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, }; static struct dtsi_replacement_bool ipa3_plat_drv_bool_3_5_1[] = { @@ -112,6 +118,9 @@ static struct dtsi_replacement_bool ipa3_plat_drv_bool_3_5_1[] = { {"qcom,use-rg10-limitation-mitigation", false}, {"qcom,do-not-use-ch-gsi-20", false}, {"qcom,use-ipa-pm", false}, + {"qcom,register-collection-on-crash", true}, + {"qcom,testbus-collection-on-crash", true}, + {"qcom,non-tn-collection-on-crash", true}, }; static struct dtsi_replacement_bool_table @@ -132,6 +141,7 @@ static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_5[] = { {"qcom,ee", 0}, {"qcom,msm-bus,num-cases", 5}, {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, }; static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_0[] = { @@ -141,6 +151,7 @@ static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_0[] = { {"qcom,lan-rx-ring-size", 192}, {"qcom,ee", 0}, {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, }; static struct dtsi_replacement_u32 ipa3_plat_drv_u32_3_5_1[] = { @@ -150,6 +161,7 @@ static struct dtsi_replacement_u32 ipa3_plat_drv_u32_3_5_1[] = { {"qcom,lan-rx-ring-size", 192}, {"qcom,ee", 0}, {"emulator-bar0-offset", 0x01C00000}, + {"qcom,entire-ipa-block-size", 0x00100000}, }; static struct dtsi_replacement_u32_table ipa3_plat_drv_u32_table[] = { diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index 643719c2fd4c..dd6c5e989bbc 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1688,6 +1688,11 @@ struct ipa3_context { bool use_ipa_pm; bool vlan_mode_iface[IPA_VLAN_IF_MAX]; bool wdi_over_pcie; + u32 entire_ipa_block_size; + bool do_register_collection_on_crash; + bool do_testbus_collection_on_crash; + bool do_non_tn_collection_on_crash; + void __iomem *reg_collection_base; struct ipa3_wdi2_ctx wdi2_ctx; struct mbox_client mbox_client; struct mbox_chan *mbox; @@ -1734,6 +1739,10 @@ struct ipa3_plat_drv_res { bool use_ipa_pm; struct ipa_pm_init_params pm_init; bool wdi_over_pcie; + u32 entire_ipa_block_size; + bool do_register_collection_on_crash; + bool do_testbus_collection_on_crash; + bool do_non_tn_collection_on_crash; }; /** @@ -2733,4 +2742,11 @@ int ipa3_get_transport_info( unsigned long *size_ptr); irq_handler_t ipa3_get_isr(void); void ipa_pc_qmp_enable(void); +#if defined(CONFIG_IPA3_REGDUMP) +int ipa_reg_save_init(uint8_t value); +void ipa_save_registers(void); +#else +static inline int ipa_reg_save_init(uint8_t value) { return 0; } +static inline void ipa_save_registers(void) {}; +#endif #endif /* _IPA3_I_H_ */ -- GitLab From be4428e63ffb68bf49f92e2beb326d5f5de8b6f2 Mon Sep 17 00:00:00 2001 From: "Jennifer L. Zenner" Date: Thu, 6 Dec 2018 16:38:55 -0500 Subject: [PATCH 0941/1286] dt-bindings: msm: Document "register collection" in qcom-ipa node Add documentation for "register collection" attributes in the qcom-ipa node. Change-Id: I472ade3f80dda77bdb46cb22bb71598087679f6b CRs-Fixed: 2342813 Acked-by: Perry Randise Signed-off-by: Jennifer L. Zenner --- Documentation/devicetree/bindings/platform/msm/ipa.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/platform/msm/ipa.txt b/Documentation/devicetree/bindings/platform/msm/ipa.txt index d80ed990accd..e52a65da1425 100644 --- a/Documentation/devicetree/bindings/platform/msm/ipa.txt +++ b/Documentation/devicetree/bindings/platform/msm/ipa.txt @@ -94,6 +94,16 @@ memory allocation over a PCIe bridge over pcie bus or not. - qcom,ipa-wdi2_over_gsi: Boolean context flag to indicate WDI2 offload over GSI supported or not. +- qcom,register-collection-on-crash: Boolean that controls IPA/GSI register + collection upon system crash (i.e. SSR). +- qcom,testbus-collection-on-crash: Boolean that controls testbus register + collection upon system crash. +- qcom,non-tn-collection-on-crash: Boolean to control a certain subset of IPA/GSI + register collection relative to an SSR. Accessing + these registers can cause stalling, hence this + control. +- qcom,entire-ipa-block-size: Complete size of the ipa block in which all + registers, collected upon crash, reside. IPA pipe sub nodes (A2 static pipes configurations): -- GitLab From 68e5ec33fd276d2f59a285c5e41785bbf6d037dd Mon Sep 17 00:00:00 2001 From: "Jennifer L. Zenner" Date: Tue, 18 Dec 2018 15:23:11 -0500 Subject: [PATCH 0942/1286] ARM: dts: msm: add ipa nodes for sm8150_sdxprairie target Add devicetree nodes for IPA driver. The nodes will allow for the turning on or off of IPA/GSI register collection upon system crash. Change-Id: I32e424769c87e0ca829f93b47177a682a1024103 CRs-Fixed: 2342813 Acked-by: Perry Randise Signed-off-by: Jennifer L. Zenner --- arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index a3d625c8406f..ac243fba7bef 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -103,6 +103,10 @@ &soc { ipa_hw: qcom,ipa@1e00000 { qcom,platform-type = <2>; /* APQ platform */ + qcom,entire-ipa-block-size = <0x100000>; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; }; }; -- GitLab From 79f0f790a7c0b4356586c465a9b0645338efda4c Mon Sep 17 00:00:00 2001 From: "Jennifer L. Zenner" Date: Thu, 6 Dec 2018 16:39:10 -0500 Subject: [PATCH 0943/1286] msm: ipa: Enable crash dump register collection for sm8150_sdx55 Functionality added to the IPA/GSI drivers in support of a register dump/collection feature. Register's values are collected upon system crash. Change-Id: I806dfbdd908391af537cab6461bdff6c6ccb3176 CRs-Fixed: 2342813 Acked-by: Perry Randise Signed-off-by: Jennifer L. Zenner --- arch/arm64/configs/vendor/sm8150-perf_defconfig | 1 + arch/arm64/configs/vendor/sm8150_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index b319f9402654..d0673727c24a 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -512,6 +512,7 @@ CONFIG_IPA3_MHI_PROXY=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m CONFIG_SEEMP_CORE=y +CONFIG_IPA3_REGDUMP=y CONFIG_QCOM_MDSS_PLL=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_MSM_CLK_AOP_QMP=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index 4c79f1412236..612eec624896 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -535,6 +535,7 @@ CONFIG_IPA3_MHI_PROXY=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m CONFIG_SEEMP_CORE=y +CONFIG_IPA3_REGDUMP=y CONFIG_QCOM_MDSS_PLL=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_MSM_CLK_AOP_QMP=y -- GitLab From 2b77d87c35a4c39ccec5b23635aadbb777082041 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 17 Dec 2018 13:20:00 +0530 Subject: [PATCH 0944/1286] ARM: dts: msm: Add IDP and QRD support for ADC on trinket Add support for bat_therm, to ensure correct scaling function is selected, for bat_therm on PMI632 on trinket QRD. Add rf_patherm_1 channel for trinket IDP alone. Change-Id: If0c08a17f8e8ed97c39a99626092b797d9c3c362 Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 41 ++++++++++++++++++- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 15 +++++++ arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 14 ------- arch/arm64/boot/dts/qcom/trinket.dtsi | 18 +------- 4 files changed, 56 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 9561076739c3..8e2a69fb8db5 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ #include - +#include #include "trinket-thermal-overlay.dtsi" #include "trinket-sde-display.dtsi" @@ -28,6 +28,45 @@ }; }; +&pm6125_vadc { + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>, + <&pm6125_vadc ADC_GPIO4_PU2>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + &sdhc_1 { vdd-supply = <&pm6125_l24>; qcom,vdd-voltage-level = <2950000 2950000>; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index ec41e7be9591..1fcabcc4085a 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ #include +#include &qupv3_se1_i2c { status = "ok"; @@ -173,6 +174,20 @@ status = "ok"; }; +&pmi632_vadc { + bat_therm { + qcom,lut-index = <0>; + }; + + bat_therm_30k { + qcom,lut-index = <0>; + }; + + bat_therm_400k { + qcom,lut-index = <0>; + }; +}; + &usb0 { extcon = <&pmi632_charger>; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 44596816179f..6f86f13f50dd 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -130,20 +130,6 @@ }; }; - rf-pa1-therm-adc { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - conn-therm-adc { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f6ab706410d6..4903ea0a4943 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2358,15 +2358,6 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; - - rf_pa1_therm { - reg = ; - label = "rf_pa1_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - }; &pm6125_gpios { @@ -2413,8 +2404,7 @@ &pm6125_adc_tm { io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, <&pm6125_vadc ADC_AMUX_THM2_PU2>, - <&pm6125_vadc ADC_XO_THERM_PU2>, - <&pm6125_vadc ADC_GPIO4_PU2>; + <&pm6125_vadc ADC_XO_THERM_PU2>; /* Channel nodes */ rf_pa0_therm { @@ -2434,12 +2424,6 @@ qcom,ratiometric; qcom,hw-settle-time = <200>; }; - - rf_pa1_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; }; &pmi632_vadc { -- GitLab From 2406a4cd8333c09360456fcd32a39499f4c74f7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 15 Jan 2019 01:00:19 +0530 Subject: [PATCH 0945/1286] clk: qcom: gcc: Add halt_reg for pcie_0_pipe_clk Halt register is required to allow the clk_set_flag API to set the memory flags for this branch register. Change-Id: I717f2f1b79f7f03abca4b994d7b2f6dd859a7ff2 Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-sdmmagpie.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-sdmmagpie.c b/drivers/clk/qcom/gcc-sdmmagpie.c index ac9a20b899a9..591d76fb0186 100644 --- a/drivers/clk/qcom/gcc-sdmmagpie.c +++ b/drivers/clk/qcom/gcc-sdmmagpie.c @@ -1820,6 +1820,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { }; static struct clk_branch gcc_pcie_0_pipe_clk = { + .halt_reg = 0x6b020, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x5200c, -- GitLab From cc4100ae567d0ae5a9026fa5cb7ca3eff2e7d87d Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Wed, 16 Jan 2019 14:09:35 -0800 Subject: [PATCH 0946/1286] msm: ipa: Set hard byte limit for coalescing pipe only Change the set_aggr_limit to only set the hard byte limit for coalescing pipe instead for every pipe in devices with IPA HW version > 4.5 (support coalescing). Remove the warn on for the hard byte limit in the 4.5 construct_aggr function. Change-Id: I6e7b5cc7a58d09898060ba7fe94a88a8a51aa628 Signed-off-by: Michael Adisumarta --- drivers/platform/msm/ipa/ipa_v3/ipa_dp.c | 19 ++++++++++--------- .../msm/ipa/ipa_v3/ipahal/ipahal_reg.c | 8 +------- 2 files changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c index a93f6ff0e1e7..e5f2aee00cac 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -3247,25 +3247,26 @@ static void ipa3_set_aggr_limit(struct ipa_sys_connect_params *in, u32 *aggr_byte_limit = &in->ipa_ep_cfg.aggr.aggr_byte_limit; u32 adjusted_sz = ipa_adjust_ra_buff_base_sz(*aggr_byte_limit); - IPAERR("get close-by %u\n", adjusted_sz); - IPAERR("set rx_buff_sz %lu\n", (unsigned long int) + IPADBG("get close-by %u\n", adjusted_sz); + IPADBG("set rx_buff_sz %lu\n", (unsigned long int) IPA_GENERIC_RX_BUFF_SZ(adjusted_sz)); /* disable ipa_status */ sys->ep->status.status_en = false; sys->rx_buff_sz = IPA_GENERIC_RX_BUFF_SZ(adjusted_sz); - if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_5) { - *aggr_byte_limit = sys->rx_buff_sz < *aggr_byte_limit ? - IPA_ADJUST_AGGR_BYTE_LIMIT(sys->rx_buff_sz) : - IPA_ADJUST_AGGR_BYTE_LIMIT(*aggr_byte_limit); - } else { + if (in->client == IPA_CLIENT_APPS_WAN_COAL_CONS) { *aggr_byte_limit = sys->rx_buff_sz < *aggr_byte_limit ? IPA_ADJUST_AGGR_BYTE_HARD_LIMIT(sys->rx_buff_sz) : IPA_ADJUST_AGGR_BYTE_HARD_LIMIT(*aggr_byte_limit); in->ipa_ep_cfg.aggr.aggr_hard_byte_limit_en = 1; + } else { + *aggr_byte_limit = sys->rx_buff_sz < *aggr_byte_limit ? + IPA_ADJUST_AGGR_BYTE_LIMIT(sys->rx_buff_sz) : + IPA_ADJUST_AGGR_BYTE_LIMIT(*aggr_byte_limit); } - IPAERR("set aggr_limit %lu\n", (unsigned long int) *aggr_byte_limit); + + IPADBG("set aggr_limit %lu\n", (unsigned long int) *aggr_byte_limit); } static int ipa3_assign_policy(struct ipa_sys_connect_params *in, diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c index 13c112807f12..ff33340f960d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1797,12 +1797,6 @@ static void ipareg_construct_endp_init_aggr_n_v4_5(enum ipahal_reg_name reg, IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT_V4_5, IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK_V4_5); - /* At IPAv3 hard_byte_limit is not supported */ - if (ep_aggr->aggr_hard_byte_limit_en) { - IPAHAL_ERR("hard byte limit aggr is not supported\n"); - WARN_ON(1); - } - ep_aggr->aggr_hard_byte_limit_en = 0; IPA_SETFIELD_IN_REG(*val, ep_aggr->aggr_hard_byte_limit_en, IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT_V4_5, IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK_V4_5); -- GitLab From ac65cb8e405e6bde6f22823d579e3dd0ea7b6b8a Mon Sep 17 00:00:00 2001 From: Subash Abhinov Kasiviswanathan Date: Sun, 13 Jan 2019 15:58:29 -0700 Subject: [PATCH 0947/1286] net: ipv6: Generate all random IID for addresses on RAWIP devices This reverts commit 557a3b4d19fc ("net: ipv6: Generate random IID for addresses on RAWIP devices") and commit 8601ea9279dd ("ipv6: Do not generate random IID only for RAWIP devices"). This scheme allows for generation of a new IID each time the interface state is toggled rather than it persisting for the lifetime of the device. CRs-Fixed: 2379253 Change-Id: I5c524ae18c374e3afcc26b4ba93a292d51839ed1 Signed-off-by: Subash Abhinov Kasiviswanathan --- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 6 +----- net/ipv6/addrconf.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c index f054733b5ef9..c0393d6a474e 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -298,10 +298,6 @@ void rmnet_vnd_setup(struct net_device *rmnet_dev) rmnet_dev->needs_free_netdev = true; rmnet_dev->ethtool_ops = &rmnet_ethtool_ops; - - /* This perm addr will be used as interface identifier by IPv6 */ - rmnet_dev->addr_assign_type = NET_ADDR_RANDOM; - eth_random_addr(rmnet_dev->perm_addr); } /* Exposed API */ diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index 35e7644d74cd..cccbf6ee838d 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -2216,8 +2216,17 @@ static int ipv6_generate_eui64(u8 *eui, struct net_device *dev) return addrconf_ifid_ieee1394(eui, dev); case ARPHRD_TUNNEL6: case ARPHRD_IP6GRE: - case ARPHRD_RAWIP: return addrconf_ifid_ip6tnl(eui, dev); + case ARPHRD_RAWIP: { + struct in6_addr lladdr; + + if (ipv6_get_lladdr(dev, &lladdr, IFA_F_TENTATIVE)) + get_random_bytes(eui, 8); + else + memcpy(eui, lladdr.s6_addr + 8, 8); + + return 0; + } } return -1; } -- GitLab From 41d7cd868f4b322434bfa895360f60a2e103cffe Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 16 Jan 2019 15:46:15 -0800 Subject: [PATCH 0948/1286] ARM: dts: msm: Allow tx fifo resize for sec usb core on SM8150 This allows to increase fifo size for the functions require bursting in super speed mode for high data rate. Change-Id: I463a11c99b8e6e91fe250d6ce6d3e31b5e168197 Signed-off-by: Hemant Kumar --- arch/arm64/boot/dts/qcom/sm8150-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi index 69dc14ede189..210ead532d21 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi @@ -421,6 +421,7 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; usb-core-id = <1>; + tx-fifo-resize; maximum-speed = "super-speed"; dr_mode = "otg"; }; -- GitLab From e56edded018968d6361230931b7c0010c3738e9d Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Wed, 5 Dec 2018 14:46:21 -0800 Subject: [PATCH 0949/1286] ARM: dts: msm: enable UFS HS-G4 related attributes for sm8150 UFS 3.0 devices support HS-G4 bus speed modes and these devices need additional voltage supply to be enabled. In addition, this change adds new bus bandwidth votes for HS-G4. Change-Id: I12baec5fcad014a5e58dc5ead4fc5d39730e438c Signed-off-by: Subhash Jadavani --- arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 +++++++++----- 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi index 2a37653bd41c..3a071348ef9e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi @@ -302,8 +302,10 @@ vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; vcc-voltage-level = <2950000 2960000>; + vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; vccq2-max-microamp = <750000>; qcom,vddp-ref-clk-supply = <&pm8150_l9>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index 467f8ef56689..421f5353f836 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -277,8 +277,10 @@ vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; vcc-voltage-level = <2950000 2960000>; + vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; vccq2-max-microamp = <750000>; qcom,vddp-ref-clk-supply = <&pm8150_l9>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi index 1447fcc9741f..b0c640ca2ebe 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi @@ -241,8 +241,10 @@ vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; vcc-voltage-level = <2950000 2960000>; + vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; vccq2-max-microamp = <750000>; qcom,vddp-ref-clk-supply = <&pm8150_l9>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 112282eb7747..5cdb4cf5897e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2313,7 +2313,7 @@ <0 0>; qcom,msm-bus,name = "ufshc_mem"; - qcom,msm-bus,num-cases = <22>; + qcom,msm-bus,num-cases = <26>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* @@ -2338,12 +2338,15 @@ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */ <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ + <123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */ <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ /* As UFS working in HS G3 RB L2 mode, aggregated @@ -2353,15 +2356,16 @@ * bindwidth (IB) needs to be given a proper value too. */ <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ + <123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", - "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", - "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "MAX"; /* PM QoS */ -- GitLab From c8ecc8772acdb26f9e2d9596fd677aa1311aa89c Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Wed, 5 Dec 2018 16:41:04 -0800 Subject: [PATCH 0950/1286] scsi: ufs: add UFS HS-G4 support New generation (3.0) UFS devices are capable of running at HS-G4 (High Speed Gear 4) which is 2x faster than previous generation UFS devices. This change adds all required support to make our host controller work with these faster devices. Change-Id: I3efc6ce6ab1e90bca78348518a1f50d8d5be971e Signed-off-by: Bao D. Nguyen Signed-off-by: Subhash Jadavani --- .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 + drivers/phy/qualcomm/phy-qcom-ufs-i.h | 3 +- drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 4 +- .../phy/qualcomm/phy-qcom-ufs-qmp-v3-660.c | 2 +- drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c | 4 +- drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c | 47 ++++++++--- drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h | 59 ++++++++++++-- .../phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c | 2 +- drivers/phy/qualcomm/phy-qcom-ufs.c | 5 +- drivers/scsi/ufs/ufs-debugfs.c | 4 +- drivers/scsi/ufs/ufs-qcom.c | 10 ++- drivers/scsi/ufs/ufs-qcom.h | 4 +- drivers/scsi/ufs/ufshcd-pltfrm.c | 9 +++ drivers/scsi/ufs/ufshcd.c | 78 ++++++++++++++++++- drivers/scsi/ufs/ufshcd.h | 3 + drivers/scsi/ufs/unipro.h | 17 ++++ include/linux/phy/phy-qcom-ufs.h | 2 +- 17 files changed, 224 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 6e4855673d15..df5d605f4228 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -76,6 +76,7 @@ Optional properties: Defaults to 26 MHz if not specified. - extcon: phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details). - non-removable : defines if the connected ufs device is not removable +- force-g4 : forces UFS Host PHY to be initialized in HS-G4 Note: If above properties are not defined it can be assumed that the supply @@ -108,6 +109,7 @@ Example: rpm-level = <3>; spm-level = <5>; dev-ref-clk-freq = <0>; /* reference clock freq: 19.2 MHz */ + force-g4; }; ==== MSM UFS platform driver properties ===== diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-i.h b/drivers/phy/qualcomm/phy-qcom-ufs-i.h index cb07bc114a2d..2208fd35cd32 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-i.h +++ b/drivers/phy/qualcomm/phy-qcom-ufs-i.h @@ -159,7 +159,8 @@ struct ufs_qcom_phy { * @dbg_register_dump: pointer to a function that dumps phy registers for debug. */ struct ufs_qcom_phy_specific_ops { - int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B); + int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B, + bool is_g4); void (*start_serdes)(struct ufs_qcom_phy *phy); int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy); void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val); diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c index 6cf7b467fe8d..2ea9b4f4ebd0 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2015, 2018, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,7 +18,7 @@ static int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) + bool is_rate_B, bool is_g4) { int err; int tbl_size_A, tbl_size_B; diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3-660.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3-660.c index 12507a0af0f0..5fd23f105977 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3-660.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3-660.c @@ -18,7 +18,7 @@ static int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) + bool is_rate_B, bool is_g4) { int err; int tbl_size_A, tbl_size_B; diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c index d35dc7d18c90..fdf4c9d0e7a2 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2016, 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,7 +18,7 @@ static int ufs_qcom_phy_qmp_v3_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) + bool is_rate_B, bool is_g4) { /* * Writing PHY calibration in this order: diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c index 78eab289efb8..2e538ce52d2c 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.c @@ -15,9 +15,14 @@ #define UFS_PHY_NAME "ufs_phy_qmp_v4" +#define check_v1(major, minor, step) \ + ((major == 0x4) && (minor == 0x000) && (step == 0x0000)) +#define check_v2(major, minor, step) \ + ((major == 0x4) && (minor == 0x001) && (step == 0x0000)) + static int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) + bool is_rate_B, bool is_g4) { u8 major = ufs_qcom_phy->host_ctrl_rev_major; u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; @@ -30,29 +35,53 @@ int ufs_qcom_phy_qmp_v4_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, /* * Writing PHY calibration in this order: * 1. Write Rate-A calibration first (1-lane mode). + * Apply G3 or G4 specific settings (v2 may have additional + * settings). * 2. Write 2nd lane configuration if needed. + * Apply G3 or G4 specific settings (v2 may have additional + * settings). * 3. Write Rate-B calibration overrides */ ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A, ARRAY_SIZE(phy_cal_table_rate_A)); - if ((major == 0x4) && (minor == 0x001) && (step == 0x0000)) - ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_v2, - ARRAY_SIZE(phy_cal_table_rate_A_v2)); + if (!is_g4) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g3, + ARRAY_SIZE(phy_cal_table_rate_A_g3)); + else + ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g4, + ARRAY_SIZE(phy_cal_table_rate_A_g4)); + + if (check_v2(major, minor, step)) { + if (!is_g4) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_rate_A_v2_g3, + ARRAY_SIZE(phy_cal_table_rate_A_v2_g3)); + else + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_rate_A_v2_g4, + ARRAY_SIZE(phy_cal_table_rate_A_v2_g4)); + } if (ufs_qcom_phy->lanes_per_direction == 2) { ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_2nd_lane, ARRAY_SIZE(phy_cal_table_2nd_lane)); - if ((major == 0x4) && (minor == 0x001) && (step == 0x0000)) - ufs_qcom_phy_write_tbl(ufs_qcom_phy, - phy_cal_table_2nd_lane_v2, - ARRAY_SIZE(phy_cal_table_2nd_lane_v2)); + if (check_v2(major, minor, step)) { + if (!is_g4) + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_2nd_lane_v2_g3, + ARRAY_SIZE(phy_cal_table_2nd_lane_v2_g3)); + else + ufs_qcom_phy_write_tbl(ufs_qcom_phy, + phy_cal_table_2nd_lane_v2_g4, + ARRAY_SIZE(phy_cal_table_2nd_lane_v2_g4)); + } } if (is_rate_B) ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B, ARRAY_SIZE(phy_cal_table_rate_B)); - if ((major == 0x4) && (minor == 0x000) && (step == 0x0000)) { + if (check_v1(major, minor, step)) { writel_relaxed(0x01, ufs_qcom_phy->mmio + QSERDES_RX0_AC_JTAG_ENABLE); writel_relaxed(0x01, ufs_qcom_phy->mmio + diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h index 24cd78889aad..17b8a4badc5b 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h @@ -77,6 +77,7 @@ #define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74) #define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xB4) #define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x150) +#define UFS_PHY_BIST_FIXED_PAT_CTRL PHY_OFF(0x60) /* UFS PHY TX registers */ #define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0xD8) @@ -126,6 +127,7 @@ #define QSERDES_RX0_RX_MODE_10_HIGH2 RX_OFF(0, 0x1A0) #define QSERDES_RX0_RX_MODE_10_HIGH3 RX_OFF(0, 0x1A4) #define QSERDES_RX0_RX_MODE_10_HIGH4 RX_OFF(0, 0x1A8) +#define QSERDES_RX0_DCC_CTRL1 RX_OFF(0, 0x1BC) #define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68) #define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08) #define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14) @@ -163,6 +165,7 @@ #define QSERDES_RX1_RX_MODE_10_HIGH2 RX_OFF(1, 0x1A0) #define QSERDES_RX1_RX_MODE_10_HIGH3 RX_OFF(1, 0x1A4) #define QSERDES_RX1_RX_MODE_10_HIGH4 RX_OFF(1, 0x1A8) +#define QSERDES_RX1_DCC_CTRL1 RX_OFF(1, 0x1BC) #define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68) #define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08) #define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14) @@ -223,6 +226,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x1B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), @@ -246,12 +251,15 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g3[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xD8), @@ -263,7 +271,23 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), }; -static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2[] = { +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x81), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6D), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_BIST_FIXED_PAT_CTRL, 0x0A), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g3[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x35), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E), @@ -273,6 +297,13 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C), }; +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_v2_g4[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x75), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x6C), +}; + static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), @@ -289,6 +320,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x1B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04), @@ -313,11 +346,9 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), }; -static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2[] = { +static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g3[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x35), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E), @@ -327,6 +358,24 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C), }; +static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_v2_g4[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x75), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x81), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x6D), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C), +}; + static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06), }; diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c b/drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c index e62a422b31b4..99af623377ad 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qrbtc-sdm845.c @@ -18,7 +18,7 @@ static int ufs_qcom_phy_qrbtc_sdm845_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) + bool is_rate_B, bool is_g4) { int err; int tbl_size_A, tbl_size_B; diff --git a/drivers/phy/qualcomm/phy-qcom-ufs.c b/drivers/phy/qualcomm/phy-qcom-ufs.c index acf632a527ca..6028f6ec4891 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs.c @@ -639,7 +639,8 @@ void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, } EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version); -int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) +int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B, + bool is_g4) { struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); int ret = 0; @@ -650,7 +651,7 @@ int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B) ret = -ENOTSUPP; } else { ret = ufs_qcom_phy->phy_spec_ops-> - calibrate_phy(ufs_qcom_phy, is_rate_B); + calibrate_phy(ufs_qcom_phy, is_rate_B, is_g4); if (ret) dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n", __func__, ret); diff --git a/drivers/scsi/ufs/ufs-debugfs.c b/drivers/scsi/ufs/ufs-debugfs.c index 59f2f4ab1dc4..656e3becdcb4 100644 --- a/drivers/scsi/ufs/ufs-debugfs.c +++ b/drivers/scsi/ufs/ufs-debugfs.c @@ -1083,8 +1083,8 @@ static int ufsdbg_power_mode_show(struct seq_file *file, void *data) static bool ufsdbg_power_mode_validate(struct ufs_pa_layer_attr *pwr_mode) { - if (pwr_mode->gear_rx < UFS_HS_G1 || pwr_mode->gear_rx > UFS_HS_G3 || - pwr_mode->gear_tx < UFS_HS_G1 || pwr_mode->gear_tx > UFS_HS_G3 || + if (pwr_mode->gear_rx < UFS_HS_G1 || pwr_mode->gear_rx > UFS_HS_G4 || + pwr_mode->gear_tx < UFS_HS_G1 || pwr_mode->gear_tx > UFS_HS_G4 || pwr_mode->lane_rx < 1 || pwr_mode->lane_rx > 2 || pwr_mode->lane_tx < 1 || pwr_mode->lane_tx > 2 || (pwr_mode->pwr_rx != FAST_MODE && diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 837046fb74a5..349a993dc419 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -273,12 +273,15 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B) ? true : false; + if (hba->reinit_g4_rate_A) + is_rate_B = false; + /* Assert PHY reset and apply PHY calibration values */ ufs_qcom_assert_reset(hba); /* provide 1ms delay to let the reset pulse propagate */ usleep_range(1000, 1100); - ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B); + ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B, hba->reinit_g4_rate_A); if (ret) { dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n", @@ -1405,7 +1408,10 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM; ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS; ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS; - ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; + if (hba->reinit_g4_rate_A) + ufs_qcom_cap.hs_rate = PA_HS_MODE_A; + else + ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; ufs_qcom_cap.desired_working_mode = UFS_QCOM_LIMIT_DESIRED_MODE; diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h index f3f60c2a4dbb..5b71e40461e1 100644 --- a/drivers/scsi/ufs/ufs-qcom.h +++ b/drivers/scsi/ufs/ufs-qcom.h @@ -40,8 +40,8 @@ #define UFS_QCOM_LIMIT_NUM_LANES_RX 2 #define UFS_QCOM_LIMIT_NUM_LANES_TX 2 -#define UFS_QCOM_LIMIT_HSGEAR_RX UFS_HS_G3 -#define UFS_QCOM_LIMIT_HSGEAR_TX UFS_HS_G3 +#define UFS_QCOM_LIMIT_HSGEAR_RX UFS_HS_G4 +#define UFS_QCOM_LIMIT_HSGEAR_TX UFS_HS_G4 #define UFS_QCOM_LIMIT_PWMGEAR_RX UFS_PWM_G4 #define UFS_QCOM_LIMIT_PWMGEAR_TX UFS_PWM_G4 #define UFS_QCOM_LIMIT_RX_PWR_PWM SLOW_MODE diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c index 887ea4927f99..074c9066de4c 100644 --- a/drivers/scsi/ufs/ufshcd-pltfrm.c +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c @@ -340,6 +340,14 @@ static void ufshcd_parse_cmd_timeout(struct ufs_hba *hba) hba->scsi_cmd_timeout = 0; } +static void ufshcd_parse_force_g4_flag(struct ufs_hba *hba) +{ + if (device_property_read_bool(hba->dev, "force-g4")) + hba->force_g4 = true; + else + hba->force_g4 = false; +} + static void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba) { struct device *dev = hba->dev; @@ -495,6 +503,7 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, ufshcd_parse_pm_levels(hba); ufshcd_parse_gear_limits(hba); ufshcd_parse_cmd_timeout(hba); + ufshcd_parse_force_g4_flag(hba); err = ufshcd_parse_extcon_info(hba); if (err) goto dealloc_host; diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index fa15ebd825c1..60fad9bb8ec0 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -403,7 +403,6 @@ static struct ufs_dev_fix ufs_fixups[] = { /* UFS cards deviations table */ UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM), - UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ), UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_FASTAUTO), UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, @@ -5488,6 +5487,17 @@ int ufshcd_change_power_mode(struct ufs_hba *hba, ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), pwr_mode->hs_rate); + if (pwr_mode->gear_tx == UFS_HS_G4) { + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSADAPTINITIAL), + PA_PEERRXHSADAPTINITIAL_Default); + /* INITIAL ADAPT */ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), + PA_INITIAL_ADAPT); + } else { + /* NO ADAPT */ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_NO_ADAPT); + } + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), DL_FC0ProtectionTimeOutVal_Default); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), @@ -8611,6 +8621,34 @@ static int ufs_read_device_desc_data(struct ufs_hba *hba) return 0; } +/** + * ufshcd_is_g4_supported - check if device supports HS-G4 + * @hba: per-adapter instance + * + * Returns True if device supports HS-G4, False otherwise. + */ +static bool ufshcd_is_g4_supported(struct ufs_hba *hba) +{ + int ret; + u32 tx_hsgear = 0; + + /* check device capability */ + ret = ufshcd_dme_peer_get(hba, + UIC_ARG_MIB_SEL(TX_HSGEAR_CAPABILITY, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), + &tx_hsgear); + if (ret) { + dev_err(hba->dev, "%s: Failed getting peer TX_HSGEAR_CAPABILITY. err = %d\n", + __func__, ret); + return false; + } + + if (tx_hsgear == UFS_HS_G4) + return true; + else + return false; +} + /** * ufshcd_probe_hba - probe hba to detect device and initialize * @hba: per-adapter instance @@ -8623,6 +8661,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) int ret; ktime_t start = ktime_get(); +reinit: ret = ufshcd_link_startup(hba); if (ret) goto out; @@ -8662,6 +8701,40 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) goto out; } + /* + * Note: Some UFS 3.0 devices may still advertise UFS specification + * version as 2.1. So let's also read the TX_HSGEAR_CAPABILITY from + * device to know if device support HS-G4 or not. + */ + if ((card.wspecversion >= 0x300 || ufshcd_is_g4_supported(hba)) && + !hba->reinit_g4_rate_A) { + unsigned long flags; + int err; + + hba->reinit_g4_rate_A = true; + + err = ufshcd_vops_full_reset(hba); + if (err) + dev_warn(hba->dev, "%s: full reset returned %d\n", + __func__, err); + + err = ufshcd_reset_device(hba); + if (err) + dev_warn(hba->dev, "%s: device reset failed. err %d\n", + __func__, err); + + /* Reset the host controller */ + spin_lock_irqsave(hba->host->host_lock, flags); + ufshcd_hba_stop(hba, false); + spin_unlock_irqrestore(hba->host->host_lock, flags); + + err = ufshcd_hba_enable(hba); + if (err) + goto out; + + goto reinit; + } + ufs_fixup_device_setup(hba, &card); ufshcd_tune_unipro_params(hba); @@ -10870,6 +10943,9 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) dev_warn(hba->dev, "%s: device reset failed. err %d\n", __func__, err); + if (hba->force_g4) + hba->reinit_g4_rate_A = true; + /* Host controller enable */ err = ufshcd_hba_enable(hba); if (err) { diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index e0e3d7b94f35..b1e7b49958a3 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -1039,6 +1039,9 @@ struct ufs_hba { int latency_hist_enabled; struct io_latency_state io_lat_s; + + bool reinit_g4_rate_A; + bool force_g4; }; static inline void ufshcd_mark_shutdown_ongoing(struct ufs_hba *hba) diff --git a/drivers/scsi/ufs/unipro.h b/drivers/scsi/ufs/unipro.h index 8a8421dd8467..4472a3d4968b 100644 --- a/drivers/scsi/ufs/unipro.h +++ b/drivers/scsi/ufs/unipro.h @@ -16,6 +16,7 @@ * M-TX Configuration Attributes */ #define TX_HIBERN8TIME_CAPABILITY 0x000F +#define TX_HSGEAR_CAPABILITY 0x0002 #define TX_MODE 0x0021 #define TX_HSRATE_SERIES 0x0022 #define TX_HSGEAR 0x0023 @@ -36,6 +37,7 @@ #define TX_LCC_SEQUENCER 0x0032 #define TX_MIN_ACTIVATETIME 0x0033 #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 +#define TX_HS_ADAPT_LENGTH 0x003A #define TX_REFCLKFREQ 0x00EB #define TX_CFGCLKFREQVAL 0x00EC #define CFGEXTRATTR 0x00F0 @@ -55,6 +57,7 @@ #define RX_TERMINATION_FORCE_ENABLE 0x0089 #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F #define RX_HIBERN8TIME_CAPABILITY 0x0092 +#define RX_HS_ADAPT_INITIAL_CAPABILITY 0x009F #define RX_REFCLKFREQ 0x00EB #define RX_CFGCLKFREQVAL 0x00EC #define CFGWIDEINLN 0x00F0 @@ -152,6 +155,19 @@ #define PA_SLEEPNOCONFIGTIME 0x15A2 #define PA_STALLNOCONFIGTIME 0x15A3 #define PA_SAVECONFIGTIME 0x15A4 +#define PA_PEERRXHSADAPTINITIAL 0x15D3 +#define PA_TXHSADAPTTYPE 0x15D4 + +/* + * Default value of PA_PEERRXHSADAPTINITIAL. + * TODO: This may need to be tuned if required. + */ +#define PA_PEERRXHSADAPTINITIAL_Default 0x91 + +/* Adpat type for PA_TXHSADAPTTYPE attribute */ +#define PA_REFRESH_ADAPT 0x00 +#define PA_INITIAL_ADAPT 0x01 +#define PA_NO_ADAPT 0x03 #define PA_TACTIVATE_TIME_UNIT_US 10 #define PA_HIBERN8_TIME_UNIT_US 100 @@ -206,6 +222,7 @@ enum ufs_hs_gear_tag { UFS_HS_G1, /* HS Gear 1 (default for reset) */ UFS_HS_G2, /* HS Gear 2 */ UFS_HS_G3, /* HS Gear 3 */ + UFS_HS_G4, /* HS Gear 4 */ }; enum ufs_unipro_ver { diff --git a/include/linux/phy/phy-qcom-ufs.h b/include/linux/phy/phy-qcom-ufs.h index 05d9a598cd61..91203f7fb27d 100644 --- a/include/linux/phy/phy-qcom-ufs.h +++ b/include/linux/phy/phy-qcom-ufs.h @@ -34,7 +34,7 @@ void ufs_qcom_phy_disable_dev_ref_clk(struct phy *phy); int ufs_qcom_phy_start_serdes(struct phy *phy); int ufs_qcom_phy_set_tx_lane_enable(struct phy *phy, u32 tx_lanes); int ufs_qcom_phy_ctrl_rx_linecfg(struct phy *generic_phy, bool ctrl); -int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B); +int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B, bool is_g4); int ufs_qcom_phy_is_pcs_ready(struct phy *phy); void ufs_qcom_phy_save_controller_version(struct phy *phy, u8 major, u16 minor, u16 step); -- GitLab From 1766175ab6513136d1082f16187ef7b8771e6299 Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Thu, 13 Dec 2018 14:52:15 -0800 Subject: [PATCH 0951/1286] scsi: ufs: add support for low voltage VCC support UFS3.0 devices are capable of running at lower level (2.5v) of VCC rail. If both host and device supports 2.5v level then we do runtime switch of UFS VCC voltage level. Change-Id: Ifa7f73f6afdfc382fa018c7403a2da79d08df845 Signed-off-by: Subhash Jadavani --- .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 3 ++ drivers/scsi/ufs/ufs.h | 2 + drivers/scsi/ufs/ufshcd-pltfrm.c | 3 ++ drivers/scsi/ufs/ufshcd.c | 48 +++++++++++++++++++ 4 files changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index df5d605f4228..101322abd919 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -25,6 +25,8 @@ Optional properties: - vcc-supply : phandle to VCC supply regulator node - vcc-voltage-level : specifies voltage levels for VCC supply. Should be specified in pairs (min, max), units uV. +- vcc-low-voltage-sup : If specified, treats min voltage from vcc-voltage-level as + low voltage level different from max voltage. - vccq-supply : phandle to VCCQ supply regulator node - vccq2-supply : phandle to VCCQ2 supply regulator node - vccq2-voltage-level : specifies voltage levels for VCCQ2 supply. @@ -93,6 +95,7 @@ Example: vdd-hba-fixed-regulator; vcc-supply = <&xxx_reg1>; vcc-supply-1p8; + vcc-low-voltage-sup; vccq-supply = <&xxx_reg2>; vccq2-supply = <&xxx_reg3>; vcc-max-microamp = 500000; diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h index 02840d6e739b..00df8861aeac 100644 --- a/drivers/scsi/ufs/ufs.h +++ b/drivers/scsi/ufs/ufs.h @@ -480,6 +480,8 @@ struct ufs_vreg { bool unused; int min_uV; int max_uV; + bool low_voltage_sup; + bool low_voltage_active; int min_uA; int max_uA; }; diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c index 074c9066de4c..dedcd7f28725 100644 --- a/drivers/scsi/ufs/ufshcd-pltfrm.c +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c @@ -197,6 +197,9 @@ static int ufshcd_populate_vreg(struct device *dev, const char *name, vreg->min_uV = be32_to_cpup(&prop[0]); vreg->max_uV = be32_to_cpup(&prop[1]); } + + if (of_property_read_bool(np, "vcc-low-voltage-sup")) + vreg->low_voltage_sup = true; } } else if (!strcmp(name, "vccq")) { vreg->min_uV = UFS_VREG_VCCQ_MIN_UV; diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 60fad9bb8ec0..850f45360755 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -469,6 +469,13 @@ static int ufshcd_devfreq_target(struct device *dev, static int ufshcd_devfreq_get_dev_status(struct device *dev, struct devfreq_dev_status *stat); static void __ufshcd_shutdown_clkscaling(struct ufs_hba *hba); +static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, + enum ufs_dev_pwr_mode pwr_mode); +static int ufshcd_config_vreg(struct device *dev, + struct ufs_vreg *vreg, bool on); +static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg); +static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg); +static bool ufshcd_is_g4_supported(struct ufs_hba *hba); #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) static struct devfreq_simple_ondemand_data ufshcd_ondemand_data = { @@ -8101,6 +8108,41 @@ static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) __func__, icc_level, ret); } +static int ufshcd_set_low_vcc_level(struct ufs_hba *hba, + struct ufs_dev_desc *dev_desc) +{ + int ret; + struct ufs_vreg *vreg = hba->vreg_info.vcc; + + /* Check if device supports the low voltage VCC feature */ + if (dev_desc->wspecversion < 0x300 && !ufshcd_is_g4_supported(hba)) + return 0; + + /* + * Check if host has support for low VCC voltage? + * In addition, also check if we have already set the low VCC level + * or not? + */ + if (!vreg->low_voltage_sup || vreg->low_voltage_active) + return 0; + + /* Put the device in sleep before lowering VCC level */ + ret = ufshcd_set_dev_pwr_mode(hba, UFS_SLEEP_PWR_MODE); + + /* Switch off VCC before switching it ON at 2.5v */ + ret = ufshcd_disable_vreg(hba->dev, vreg); + /* add ~2ms delay before renabling VCC at lower voltage */ + usleep_range(2000, 2100); + /* Now turn back VCC ON at low voltage */ + vreg->low_voltage_active = true; + ret = ufshcd_enable_vreg(hba->dev, vreg); + + /* Bring the device in active now */ + ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); + + return ret; +} + /** * ufshcd_scsi_add_wlus - Adds required W-LUs * @hba: per-adapter instance @@ -8794,6 +8836,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) if (ufshcd_scsi_add_wlus(hba)) goto out; + /* lower VCC voltage level */ + ufshcd_set_low_vcc_level(hba, &card); + /* Initialize devfreq after UFS device is detected */ if (ufshcd_is_clkscaling_supported(hba)) { memcpy(&hba->clk_scaling.saved_pwr_info.info, @@ -9351,6 +9396,9 @@ static int ufshcd_config_vreg(struct device *dev, goto out; min_uV = on ? vreg->min_uV : 0; + if (vreg->low_voltage_sup && !vreg->low_voltage_active) + min_uV = vreg->max_uV; + ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); if (ret) { dev_err(dev, "%s: %s set voltage failed, err=%d\n", -- GitLab From 9428bb77dd720a0e2da41c7052a9c7cecc58ae8e Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Thu, 13 Dec 2018 14:55:41 -0800 Subject: [PATCH 0952/1286] ARM: dts: msm: enable low voltage VCC support for UFS on sm8150 UFS3.0 devices support the low voltage VCC and this change enables same on host side. Change-Id: Ia2e07ab8ab918f64c52851e53e6686de92e037ad Signed-off-by: Subhash Jadavani --- arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi index 3a071348ef9e..84c11b5540db 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi @@ -301,7 +301,8 @@ vdd-hba-supply = <&ufs_phy_gdsc>; vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index 421f5353f836..ae56d903b41a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -276,7 +276,8 @@ vdd-hba-supply = <&ufs_phy_gdsc>; vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi index b0c640ca2ebe..442b8a0332cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi @@ -240,7 +240,8 @@ vdd-hba-supply = <&ufs_phy_gdsc>; vdd-hba-fixed-regulator; vcc-supply = <&pm8150_l10>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; vccq-supply = <&pm8150_l9>; vccq2-supply = <&pm8150_s4>; vcc-max-microamp = <750000>; -- GitLab From cec3669ba8862e19a8f5ccd83bb3ea981ac391e4 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Wed, 16 Jan 2019 10:54:57 +0530 Subject: [PATCH 0953/1286] ARM: dts: msm: Enable APC CL CPR for QCS405 Enable APC closed-loop CPR with the required margins. Change-Id: I3ecb78c663be2cd403ead9bd3c4f4bad6e56743f Signed-off-by: Anirudh Ghayal --- arch/arm64/boot/dts/qcom/qcs405-regulator.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405-regulator.dtsi b/arch/arm64/boot/dts/qcom/qcs405-regulator.dtsi index ba20df42027c..b49317e19c96 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-regulator.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -361,5 +361,8 @@ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-quotient-adjustment = + <0 (-20) 0>; + qcom,cpr-enable; }; }; -- GitLab From a0734f209d6efd694b7c199740f4de1e11fc26c4 Mon Sep 17 00:00:00 2001 From: Tingwei Zhang Date: Tue, 8 Jan 2019 18:10:05 +0800 Subject: [PATCH 0954/1286] arm64: hw_breakpoint: don't clear debug registers in halt mode Don't clear debug registers when halting debug mode is enabled. This avoids wiping out break point from external debugger. Change-Id: I891b0938e8b901231f70ae02c2c2c0cc1d3f5296 Signed-off-by: Tingwei Zhang --- arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/kernel/hw_breakpoint.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index a44cf5225429..790d02358f70 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -31,6 +31,7 @@ /* MDSCR_EL1 enabling bits */ #define DBG_MDSCR_KDE (1 << 13) +#define DBG_MDSCR_HDE (1 << 14) #define DBG_MDSCR_MDE (1 << 15) #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 749f81779420..54e9f6cfe2a3 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -934,6 +934,17 @@ void hw_breakpoint_thread_switch(struct task_struct *next) !next_debug_info->wps_disabled); } +/* + * Check if halted debug mode is enabled. + */ +static u32 hde_enabled(void) +{ + u32 mdscr; + + asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); + return (mdscr & DBG_MDSCR_HDE); +} + /* * CPU initialisation. */ @@ -941,6 +952,14 @@ static int hw_breakpoint_reset(unsigned int cpu) { int i; struct perf_event **slots; + + /* + * When halting debug mode is enabled, break point could be already + * set be external debugger. Don't reset debug registers here to + * reserve break point from external debugger. + */ + if (hde_enabled()) + return 0; /* * When a CPU goes through cold-boot, it does not have any installed * slot, so it is safe to share the same function for restoring and -- GitLab From f3f25337eeaba85b1272a94b7b8dd29e6fc60541 Mon Sep 17 00:00:00 2001 From: Tanya Dixit Date: Mon, 14 Jan 2019 20:55:19 +0530 Subject: [PATCH 0955/1286] ARM: dts: msm: Add audio support for external codec Add audio dtsi files in base dt files for trinket tasha variant. Change-Id: I9e9f46c37ab31cbc46200258780e71050f636e9f Signed-off-by: Tanya Dixit --- arch/arm64/boot/dts/qcom/trinket-audio.dtsi | 9 +++++ .../trinket-external-codec-idp-overlay.dts | 2 ++ .../dts/qcom/trinket-external-codec-idp.dts | 2 ++ .../trinket-tasha-codec-audio-overlay.dtsi | 1 - .../boot/dts/qcom/trinket-tasha-codec.dtsi | 36 +++++++++---------- arch/arm64/boot/dts/qcom/trinket-wcd.dtsi | 4 +-- 6 files changed, 31 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-audio.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio.dtsi index cd4808674fa6..1cce93e729f7 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio.dtsi @@ -138,3 +138,12 @@ fsa4480-i2c-handle = <&fsa4480>; }; }; + +&slim_aud { + status = "disabled"; + dai_slim: msm_dai_slim { + status = "disabled"; + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts index c8fe133cb177..2a366244cfcc 100644 --- a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts @@ -16,6 +16,8 @@ #include #include "trinket-idp.dtsi" +#include "trinket-tasha-codec-audio-overlay.dtsi" +#include "trinket-tasha-codec.dtsi" / { model = "Ext Audio Codec IDP"; diff --git a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts index 97e8a31ea423..c18f4502ca92 100644 --- a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts +++ b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp.dts @@ -14,6 +14,8 @@ #include "trinket.dtsi" #include "trinket-idp.dtsi" +#include "trinket-tasha-codec-audio-overlay.dtsi" +#include "trinket-tasha-codec.dtsi" / { model = "Qualcomm Technologies, Inc. Trinket Ext Audio Codec IDP"; diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi index d60aee9206f7..8e85ba88f1b1 100644 --- a/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ #include "trinket-audio-overlay.dtsi" -#include "trinket-wcd.dtsi" &bolero { status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi index d16b579d03e7..73f3c2ee6ce5 100644 --- a/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi @@ -10,27 +10,23 @@ * GNU General Public License for more details. */ -#include "trinket-tasha-codec-audio-overlay.dtsi" - -&pm6125_div_clk { - status = "okay"; -}; +#include +#include "trinket-wcd.dtsi" &sm6150_snd { qcom,model = "trinket-tashalite-snd-card"; qcom,tasha_codec = <1>; asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, - <&pcm_noirq>, <&cpe3>; + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-cpe-lsm", - "msm-compr-dsp", "msm-pcm-dsp-noirq", - "msm-cpe-lsm.3"; + "msm-pcm-routing", + "msm-compr-dsp", "msm-pcm-dsp-noirq"; asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, @@ -66,6 +62,16 @@ "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16400", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -108,17 +114,7 @@ "SpkrLeft", "SpkrRight"; }; -&soc { - wsa_spkr_en2: wsa_spkr_en2_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_2_sd_n_active>; - pinctrl-1 = <&spkr_2_sd_n_sleep>; - }; -}; - &slim_aud { - status = "okay"; tasha_codec { swr3: swr_master { compatible = "qcom,swr-mstr"; diff --git a/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi b/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi index d8813c29304a..1c6b200e1c7c 100644 --- a/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-wcd.dtsi @@ -12,14 +12,14 @@ &slim_aud { tasha_codec { - wsa_spkr_sd1: msm_cdc_pinctrll { + wsa_spk_wcd_sd1: msm_cdc_pinctrll { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&tasha_spkr_1_sd_n_active>; pinctrl-1 = <&tasha_spkr_1_sd_n_sleep>; }; - wsa_spkr_sd2: msm_cdc_pinctrlr { + wsa_spk_wcd_sd2: msm_cdc_pinctrlr { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&tasha_spkr_2_sd_n_active>; -- GitLab From 4661b7b1946d501dfe331d2fcddd613a9d957fc5 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Thu, 22 Nov 2018 12:17:45 +0530 Subject: [PATCH 0956/1286] power: smb1390-psy: Add module parameter to control logging To control SMB1390 logging, add a module parameter debug_mask. Change-Id: I229a10a69f7efa8841c821ba9286b4ed681db1c1 Signed-off-by: Umang Agrawal --- .../power/supply/qcom/smb1390-charger-psy.c | 89 +++++++++++++++---- 1 file changed, 71 insertions(+), 18 deletions(-) diff --git a/drivers/power/supply/qcom/smb1390-charger-psy.c b/drivers/power/supply/qcom/smb1390-charger-psy.c index d9e765415a00..7d987629433d 100644 --- a/drivers/power/supply/qcom/smb1390-charger-psy.c +++ b/drivers/power/supply/qcom/smb1390-charger-psy.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,6 +12,7 @@ #define pr_fmt(fmt) "SMB1390: %s: " fmt, __func__ +#include #include #include #include @@ -91,6 +92,16 @@ #define SRC_VOTER "SRC_VOTER" #define SWITCHER_TOGGLE_VOTER "SWITCHER_TOGGLE_VOTER" +#define smb1390_dbg(chip, reason, fmt, ...) \ + do { \ + if (chip->debug_mask & (reason)) \ + pr_info("SMB1390: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + pr_debug("SMB1390: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + } while (0) + enum { SWITCHER_OFF_WINDOW_IRQ = 0, SWITCHER_OFF_FAULT_IRQ, @@ -108,6 +119,14 @@ enum { SMB_PIN_EN, }; +enum print_reason { + PR_INTERRUPT = BIT(0), + PR_REGISTER = BIT(1), + PR_INFO = BIT(2), + PR_EXT_DEPENDENCY = BIT(3), + PR_MISC = BIT(4), +}; + struct smb1390_iio { struct iio_channel *die_temp_chan; }; @@ -117,6 +136,7 @@ struct smb1390 { struct regmap *regmap; struct notifier_block nb; struct wakeup_source *cp_ws; + struct dentry *dfs_root; /* work structs */ struct work_struct status_change_work; @@ -147,6 +167,7 @@ struct smb1390 { bool switcher_enabled; int die_temp; bool suspended; + u32 debug_mask; }; struct smb_irq { @@ -173,7 +194,8 @@ static int smb1390_masked_write(struct smb1390 *chip, int reg, int mask, { int rc; - pr_debug("Writing 0x%02x to 0x%04x with mask 0x%02x\n", val, reg, mask); + smb1390_dbg(chip, PR_REGISTER, "Writing 0x%02x to 0x%04x with mask 0x%02x\n", + val, reg, mask); rc = regmap_update_bits(chip->regmap, reg, mask, val); if (rc < 0) pr_err("Couldn't write 0x%02x to 0x%04x with mask 0x%02x\n", @@ -187,7 +209,7 @@ static bool is_psy_voter_available(struct smb1390 *chip) if (!chip->batt_psy) { chip->batt_psy = power_supply_get_by_name("battery"); if (!chip->batt_psy) { - pr_debug("Couldn't find battery psy\n"); + smb1390_dbg(chip, PR_EXT_DEPENDENCY, "Couldn't find battery psy\n"); return false; } } @@ -195,7 +217,7 @@ static bool is_psy_voter_available(struct smb1390 *chip) if (!chip->usb_psy) { chip->usb_psy = power_supply_get_by_name("usb"); if (!chip->usb_psy) { - pr_debug("Couldn't find usb psy\n"); + smb1390_dbg(chip, PR_EXT_DEPENDENCY, "Couldn't find usb psy\n"); return false; } } @@ -203,7 +225,7 @@ static bool is_psy_voter_available(struct smb1390 *chip) if (!chip->dc_psy) { chip->dc_psy = power_supply_get_by_name("dc"); if (!chip->dc_psy) { - pr_debug("Couldn't find dc psy\n"); + smb1390_dbg(chip, PR_EXT_DEPENDENCY, "Couldn't find dc psy\n"); return false; } } @@ -211,7 +233,7 @@ static bool is_psy_voter_available(struct smb1390 *chip) if (!chip->fcc_votable) { chip->fcc_votable = find_votable("FCC"); if (!chip->fcc_votable) { - pr_debug("Couldn't find FCC votable\n"); + smb1390_dbg(chip, PR_EXT_DEPENDENCY, "Couldn't find FCC votable\n"); return false; } } @@ -219,13 +241,13 @@ static bool is_psy_voter_available(struct smb1390 *chip) if (!chip->fv_votable) { chip->fv_votable = find_votable("FV"); if (!chip->fv_votable) { - pr_debug("Couldn't find FV votable\n"); + smb1390_dbg(chip, PR_EXT_DEPENDENCY, "Couldn't find FV votable\n"); return false; } } if (!chip->disable_votable) { - pr_debug("Couldn't find CP DISABLE votable\n"); + smb1390_dbg(chip, PR_MISC, "Couldn't find CP DISABLE votable\n"); return false; } @@ -261,7 +283,8 @@ static int smb1390_get_cp_en_status(struct smb1390 *chip, int id, bool *enable) *enable = !!(status & EN_PIN_OUT2_BIT); break; default: - pr_debug("cp_en status %d is not supported", id); + smb1390_dbg(chip, PR_MISC, "cp_en status %d is not supported", + id); rc = -EINVAL; break; } @@ -277,7 +300,8 @@ static irqreturn_t default_irq_handler(int irq, void *data) for (i = 0; i < NUM_IRQS; ++i) { if (irq == chip->irqs[i]) { - pr_debug("%s IRQ triggered\n", smb_irqs[i].name); + smb1390_dbg(chip, PR_INTERRUPT, "%s IRQ triggered\n", + smb_irqs[i].name); chip->irq_status |= 1 << i; } } @@ -478,10 +502,11 @@ static int smb1390_ilim_vote_cb(struct votable *votable, void *data, /* ILIM less than 1A is not accurate; disable charging */ if (ilim_uA < 1000000) { - pr_debug("ILIM %duA is too low to allow charging\n", ilim_uA); + smb1390_dbg(chip, PR_INFO, "ILIM %duA is too low to allow charging\n", + ilim_uA); vote(chip->disable_votable, ILIM_VOTER, true, 0); } else { - pr_debug("ILIM set to %duA\n", ilim_uA); + smb1390_dbg(chip, PR_INFO, "ILIM set to %duA\n", ilim_uA); vote(chip->disable_votable, ILIM_VOTER, false, 0); } @@ -628,7 +653,7 @@ static void smb1390_taper_work(struct work_struct *work) if (get_effective_result(chip->fv_votable) > chip->taper_entry_fv) { - pr_debug("Float voltage increased. Exiting taper\n"); + smb1390_dbg(chip, PR_INFO, "Float voltage increased. Exiting taper\n"); goto out; } else { chip->taper_entry_fv = @@ -638,7 +663,8 @@ static void smb1390_taper_work(struct work_struct *work) if (pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER) { fcc_uA = get_effective_result(chip->fcc_votable) - 100000; - pr_debug("taper work reducing FCC to %duA\n", fcc_uA); + smb1390_dbg(chip, PR_INFO, "taper work reducing FCC to %duA\n", + fcc_uA); vote(chip->fcc_votable, CP_VOTER, true, fcc_uA); if (fcc_uA < 2000000) { @@ -647,13 +673,13 @@ static void smb1390_taper_work(struct work_struct *work) goto out; } } else { - pr_debug("In fast charging. Wait for next taper\n"); + smb1390_dbg(chip, PR_INFO, "In fast charging. Wait for next taper\n"); } msleep(500); } out: - pr_debug("taper work exit\n"); + smb1390_dbg(chip, PR_INFO, "taper work exit\n"); vote(chip->fcc_votable, CP_VOTER, false, 0); chip->taper_work_running = false; } @@ -740,7 +766,7 @@ static int smb1390_get_prop(struct power_supply *psy, + 500000; break; default: - pr_debug("charge pump power supply get prop %d not supported\n", + smb1390_dbg(chip, PR_MISC, "charge pump power supply get prop %d not supported\n", prop); return -EINVAL; } @@ -767,7 +793,7 @@ static int smb1390_set_prop(struct power_supply *psy, chip->irq_status = val->intval; break; default: - pr_debug("charge pump power supply set prop %d not supported\n", + smb1390_dbg(chip, PR_MISC, "charge pump power supply set prop %d not supported\n", prop); return -EINVAL; } @@ -976,6 +1002,31 @@ static int smb1390_request_interrupts(struct smb1390 *chip) return rc; } +#ifdef CONFIG_DEBUG_FS +static void smb1390_create_debugfs(struct smb1390 *chip) +{ + struct dentry *entry; + + chip->dfs_root = debugfs_create_dir("smb1390_charger_psy", NULL); + if (IS_ERR_OR_NULL(chip->dfs_root)) { + pr_err("Failed to create debugfs directory, rc=%ld\n", + (long)chip->dfs_root); + return; + } + + entry = debugfs_create_u32("debug_mask", 0600, chip->dfs_root, + &chip->debug_mask); + if (IS_ERR_OR_NULL(entry)) { + pr_err("Failed to create debug_mask, rc=%ld\n", (long)entry); + debugfs_remove_recursive(chip->dfs_root); + } +} +#else +static void smb1390_create_debugfs(struct smb1390 *chip) +{ +} +#endif + static int smb1390_probe(struct platform_device *pdev) { struct smb1390 *chip; @@ -1041,6 +1092,8 @@ static int smb1390_probe(struct platform_device *pdev) goto out_notifier; } + smb1390_create_debugfs(chip); + pr_info("smb1390 probed successfully"); return 0; -- GitLab From 3511974da2d4adf5727f7bc09c3bcb525c8f905f Mon Sep 17 00:00:00 2001 From: Laurent Dufour Date: Mon, 14 Jan 2019 18:35:39 +0100 Subject: [PATCH 0957/1286] mm: flush TLB once pages are copied when SPF is on Vinayak Menon reported that the following scenario results in threads A and B of process 1 blocking on pthread_mutex_lock forever after few iterations. CPU 1 CPU 2 CPU 3 Process 1, Process 1, Process 1, Thread A Thread B Thread C while (1) { while (1) { while(1) { pthread_mutex_lock(l) pthread_mutex_lock(l) fork pthread_mutex_unlock(l) pthread_mutex_unlock(l) } } } When from thread C, copy_one_pte write-protects the parent pte (of lock l), stale tlb entries can exist with write permissions on one of the CPUs at least. This can create a problem if one of the threads A or B hits the write fault. Though dup_mmap calls flush_tlb_mm after copy_page_range, since speculative page fault does not take mmap_sem it can proceed further fixing a fault soon after CPU 3 does ptep_set_wrprotect. But the CPU with stale tlb entry can still modify old_page even after it is copied to new_page by wp_page_copy, thus causing a corruption. Change-Id: Id9cb10d745f96fadec693ffad61c7d999d15bd81 Patch-mainline: linux-mm @ Wed, 16 Jan 2019 14:31:21 Reported-by: Vinayak Menon Signed-off-by: Laurent Dufour [vinmenon@codeaurora.org: fix the addr passed to flush_tlb_range] Signed-off-by: Charan Teja Reddy --- mm/memory.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index fe6f22065be8..9ff21b7bc363 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -1087,6 +1087,7 @@ static int copy_pte_range(struct mm_struct *dst_mm, struct mm_struct *src_mm, spinlock_t *src_ptl, *dst_ptl; int progress = 0; int rss[NR_MM_COUNTERS]; + unsigned long orig_addr = addr; swp_entry_t entry = (swp_entry_t){0}; again: @@ -1125,6 +1126,15 @@ static int copy_pte_range(struct mm_struct *dst_mm, struct mm_struct *src_mm, } while (dst_pte++, src_pte++, addr += PAGE_SIZE, addr != end); arch_leave_lazy_mmu_mode(); + + /* + * Prevent the page fault handler to copy the page while stale tlb entry + * are still not flushed. + */ + if (IS_ENABLED(CONFIG_SPECULATIVE_PAGE_FAULT) && + is_cow_mapping(vma->vm_flags)) + flush_tlb_range(vma, orig_addr, end); + spin_unlock(src_ptl); pte_unmap(orig_src_pte); add_mm_rss_vec(dst_mm, rss); -- GitLab From c73c439f8ea94ef2daae30859aec397cc750d0d0 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Tue, 8 Jan 2019 15:04:53 +0530 Subject: [PATCH 0958/1286] ARM: dts: msm: Pass eud as extcon device for USB on Trinket Eud device sends extcon notifications to perform USB spoof attach and detach. Hence pass the eud device as extcon for USB on Trinket. Change-Id: I6c5d959eecb4cf941214c078f376ac3bfe441185 Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 2 +- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 9561076739c3..7733bc1ed806 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -93,7 +93,7 @@ }; &usb0 { - extcon = <&pmi632_charger>; + extcon = <&pmi632_charger>, <&eud>; }; &pmi632_gpios { diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index ec41e7be9591..702b70168158 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -174,5 +174,5 @@ }; &usb0 { - extcon = <&pmi632_charger>; + extcon = <&pmi632_charger>, <&eud>; }; -- GitLab From 4f98a302cd6064449dc12b17b4ea9beafb9bda52 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Tue, 15 Jan 2019 15:54:30 +0530 Subject: [PATCH 0959/1286] power: qpnp-qg: Add support for DC charging path Add support for DC charger status. Update SOC scaling and QG status based on input presence (USB & DC). Change-Id: I168c376883dab2c7a8f524060764d2f52f22bd35 Signed-off-by: Anirudh Ghayal --- drivers/power/supply/qcom/qg-core.h | 4 ++- drivers/power/supply/qcom/qg-soc.c | 14 ++++----- drivers/power/supply/qcom/qg-util.c | 30 ++++++++++++++++++- drivers/power/supply/qcom/qg-util.h | 4 ++- drivers/power/supply/qcom/qpnp-qg.c | 45 +++++++++++++++++------------ 5 files changed, 69 insertions(+), 28 deletions(-) diff --git a/drivers/power/supply/qcom/qg-core.h b/drivers/power/supply/qcom/qg-core.h index 9feaed6f7fd8..893282144b67 100644 --- a/drivers/power/supply/qcom/qg-core.h +++ b/drivers/power/supply/qcom/qg-core.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -106,6 +106,7 @@ struct qpnp_qg { struct qg_user_data udata; struct power_supply *batt_psy; struct power_supply *usb_psy; + struct power_supply *dc_psy; struct power_supply *parallel_psy; struct qg_esr_data esr_data[QG_MAX_ESR_COUNT]; @@ -120,6 +121,7 @@ struct qpnp_qg { bool charge_done; bool parallel_enabled; bool usb_present; + bool dc_present; bool charge_full; bool force_soc; int charge_status; diff --git a/drivers/power/supply/qcom/qg-soc.c b/drivers/power/supply/qcom/qg-soc.c index a4da904d42fc..c76e2ffea4fa 100644 --- a/drivers/power/supply/qcom/qg-soc.c +++ b/drivers/power/supply/qcom/qg-soc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -134,8 +134,8 @@ static bool is_scaling_required(struct qpnp_qg *chip) return false; - if (chip->catch_up_soc > chip->msoc && !is_usb_present(chip)) - /* USB is not present and SOC has increased */ + if (chip->catch_up_soc > chip->msoc && !is_input_present(chip)) + /* input is not present and SOC has increased */ return false; return true; @@ -169,11 +169,11 @@ static bool maint_soc_timeout(struct qpnp_qg *chip) static void update_msoc(struct qpnp_qg *chip) { int rc = 0, sdam_soc, batt_temp = 0, batt_soc_32bit = 0; - bool usb_present = is_usb_present(chip); + bool input_present = is_input_present(chip); if (chip->catch_up_soc > chip->msoc) { /* SOC increased */ - if (usb_present) /* Increment if USB is present */ + if (input_present) /* Increment if input is present */ chip->msoc += chip->dt.delta_soc; } else if (chip->catch_up_soc < chip->msoc) { /* SOC dropped */ @@ -213,14 +213,14 @@ static void update_msoc(struct qpnp_qg *chip) QG_SOC_FULL); cap_learning_update(chip->cl, batt_temp, batt_soc_32bit, chip->charge_status, chip->charge_done, - usb_present, false); + input_present, false); } } cycle_count_update(chip->counter, DIV_ROUND_CLOSEST(chip->msoc * 255, 100), chip->charge_status, chip->charge_done, - usb_present); + input_present); qg_dbg(chip, QG_DEBUG_SOC, "SOC scale: Update maint_soc=%d msoc=%d catch_up_soc=%d delta_soc=%d\n", diff --git a/drivers/power/supply/qcom/qg-util.c b/drivers/power/supply/qcom/qg-util.c index bd998c9652a5..9a41314f8ed6 100644 --- a/drivers/power/supply/qcom/qg-util.c +++ b/drivers/power/supply/qcom/qg-util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -275,6 +275,18 @@ static bool is_usb_available(struct qpnp_qg *chip) return true; } +static bool is_dc_available(struct qpnp_qg *chip) +{ + if (chip->dc_psy) + return true; + + chip->dc_psy = power_supply_get_by_name("dc"); + if (!chip->dc_psy) + return false; + + return true; +} + bool is_usb_present(struct qpnp_qg *chip) { union power_supply_propval pval = {0, }; @@ -286,6 +298,22 @@ bool is_usb_present(struct qpnp_qg *chip) return pval.intval ? true : false; } +bool is_dc_present(struct qpnp_qg *chip) +{ + union power_supply_propval pval = {0, }; + + if (is_dc_available(chip)) + power_supply_get_property(chip->dc_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + + return pval.intval ? true : false; +} + +bool is_input_present(struct qpnp_qg *chip) +{ + return is_usb_present(chip) || is_dc_present(chip); +} + static bool is_parallel_available(struct qpnp_qg *chip) { if (chip->parallel_psy) diff --git a/drivers/power/supply/qcom/qg-util.h b/drivers/power/supply/qcom/qg-util.h index 307b2ae54546..b342040cd4a2 100644 --- a/drivers/power/supply/qcom/qg-util.h +++ b/drivers/power/supply/qcom/qg-util.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,6 +22,8 @@ int get_sample_interval(struct qpnp_qg *chip, u32 *sample_interval); int get_fifo_done_time(struct qpnp_qg *chip, bool rt, int *time_ms); int get_rtc_time(unsigned long *rtc_time); bool is_usb_present(struct qpnp_qg *chip); +bool is_dc_present(struct qpnp_qg *chip); +bool is_input_present(struct qpnp_qg *chip); bool is_parallel_enabled(struct qpnp_qg *chip); int qg_write_monotonic_soc(struct qpnp_qg *chip, int msoc); int qg_get_battery_temp(struct qpnp_qg *chip, int *batt_temp); diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c index d6951895f989..97ec786177b8 100644 --- a/drivers/power/supply/qcom/qpnp-qg.c +++ b/drivers/power/supply/qcom/qpnp-qg.c @@ -1979,14 +1979,14 @@ static int qg_charge_full_update(struct qpnp_qg *chip) } else if ((!chip->charge_done || chip->msoc <= recharge_soc) && chip->charge_full) { - bool usb_present = is_usb_present(chip); + bool input_present = is_input_present(chip); /* * force a recharge only if SOC <= recharge SOC and * we have not started charging. */ if ((chip->wa_flags & QG_RECHARGE_SOC_WA) && - usb_present && chip->msoc <= recharge_soc && + input_present && chip->msoc <= recharge_soc && chip->charge_status != POWER_SUPPLY_STATUS_CHARGING) { /* Force recharge */ prop.intval = 0; @@ -2004,10 +2004,10 @@ static int qg_charge_full_update(struct qpnp_qg *chip) /* * If SOC has indeed dropped below recharge-SOC or - * the USB is removed, if linearize-soc is set scale + * the input is removed, if linearize-soc is set scale * msoc from 100% for better UX. */ - if (chip->msoc < recharge_soc || !usb_present) { + if (chip->msoc < recharge_soc || !input_present) { if (chip->dt.linearize_soc) { get_rtc_time(&chip->last_maint_soc_update_time); chip->maint_soc = FULL_SOC; @@ -2018,9 +2018,9 @@ static int qg_charge_full_update(struct qpnp_qg *chip) chip->msoc, recharge_soc); } else { /* continue with charge_full state */ - qg_dbg(chip, QG_DEBUG_STATUS, "msoc=%d recharge_soc=%d charge_full=%d usb_present=%d\n", + qg_dbg(chip, QG_DEBUG_STATUS, "msoc=%d recharge_soc=%d charge_full=%d input_present=%d\n", chip->msoc, recharge_soc, - chip->charge_full, usb_present); + chip->charge_full, input_present); } } out: @@ -2058,18 +2058,21 @@ static int qg_parallel_status_update(struct qpnp_qg *chip) return 0; } -static int qg_usb_status_update(struct qpnp_qg *chip) +static int qg_input_status_update(struct qpnp_qg *chip) { bool usb_present = is_usb_present(chip); + bool dc_present = is_dc_present(chip); - if (chip->usb_present != usb_present) { + if ((chip->usb_present != usb_present) || + (chip->dc_present != dc_present)) { qg_dbg(chip, QG_DEBUG_STATUS, - "USB status changed Present=%d\n", - usb_present); + "Input status changed usb_present=%d dc_present=%d\n", + usb_present, dc_present); qg_scale_soc(chip, false); } chip->usb_present = usb_present; + chip->dc_present = dc_present; return 0; } @@ -2183,6 +2186,7 @@ static void qg_status_change_work(struct work_struct *work) struct qpnp_qg, qg_status_change_work); union power_supply_propval prop = {0, }; int rc = 0, batt_temp = 0, batt_soc_32b = 0; + bool input_present = false; if (!is_batt_available(chip)) { pr_debug("batt-psy not available\n"); @@ -2221,14 +2225,17 @@ static void qg_status_change_work(struct work_struct *work) if (rc < 0) pr_err("Failed to update parallel-status, rc=%d\n", rc); - rc = qg_usb_status_update(chip); + rc = qg_input_status_update(chip); if (rc < 0) - pr_err("Failed to update usb status, rc=%d\n", rc); + pr_err("Failed to update input status, rc=%d\n", rc); + + /* get input status */ + input_present = is_input_present(chip); cycle_count_update(chip->counter, DIV_ROUND_CLOSEST(chip->msoc * 255, 100), chip->charge_status, chip->charge_done, - chip->usb_present); + input_present); if (!chip->dt.cl_disable) { rc = qg_get_battery_temp(chip, &batt_temp); @@ -2240,14 +2247,14 @@ static void qg_status_change_work(struct work_struct *work) QG_SOC_FULL); cap_learning_update(chip->cl, batt_temp, batt_soc_32b, chip->charge_status, chip->charge_done, - chip->usb_present, false); + input_present, false); } } rc = qg_charge_full_update(chip); if (rc < 0) pr_err("Failed in charge_full_update, rc=%d\n", rc); - ttf_update(chip->ttf, chip->usb_present); + ttf_update(chip->ttf, input_present); out: pm_relax(chip->dev); } @@ -2266,7 +2273,8 @@ static int qg_notifier_cb(struct notifier_block *nb, if ((strcmp(psy->desc->name, "battery") == 0) || (strcmp(psy->desc->name, "parallel") == 0) - || (strcmp(psy->desc->name, "usb") == 0)) { + || (strcmp(psy->desc->name, "usb") == 0) + || (strcmp(psy->desc->name, "dc") == 0)) { /* * We cannot vote for awake votable here as that takes * a mutex lock and this is executed in an atomic context. @@ -4040,8 +4048,9 @@ static int qpnp_qg_remove(struct platform_device *pdev) static void qpnp_qg_shutdown(struct platform_device *pdev) { struct qpnp_qg *chip = platform_get_drvdata(pdev); + bool input_present = is_input_present(chip); - if (!is_usb_present(chip) || !chip->profile_loaded) + if (!input_present || !chip->profile_loaded) return; /* * Charging status doesn't matter when the device shuts down and we @@ -4050,7 +4059,7 @@ static void qpnp_qg_shutdown(struct platform_device *pdev) cycle_count_update(chip->counter, DIV_ROUND_CLOSEST(chip->msoc * 255, 100), POWER_SUPPLY_STATUS_NOT_CHARGING, - true, chip->usb_present); + true, input_present); } static const struct of_device_id match_table[] = { -- GitLab From 804422fce81092a2062ca5b02215100f95099db1 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Mon, 14 Jan 2019 20:11:56 +0530 Subject: [PATCH 0960/1286] ARM: dts: sa4155p: Add support for new soc id Add new msm-id to support a variant sa4155p. Change-Id: Ib90818c5b4feb47f33b4242c941ade7a145eba7d Signed-off-by: Venkata Rao Kakani --- arch/arm64/boot/dts/qcom/sa6155p-adp-air-overlay.dts | 4 ++-- arch/arm64/boot/dts/qcom/sa6155p-adp-star-overlay.dts | 4 ++-- arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts | 2 +- arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts | 2 +- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155p-adp-air-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-adp-air-overlay.dts index ad4f3e5d0d6c..6d79a17a7a15 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-adp-air-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-adp-air-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; - qcom,msm-id = <377 0x0>; + qcom,msm-id = <377 0x0>, <380 0>; qcom,board-id = <0x03000019 0>; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-adp-star-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-adp-star-overlay.dts index c892af7c15c3..4e52cf4c0f45 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-adp-star-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-adp-star-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; - qcom,msm-id = <377 0x0>; + qcom,msm-id = <377 0x0>, <380 0>; qcom,board-id = <25 0>; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts index db177128ce81..40b2766bafc1 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; - qcom,msm-id = <377 0x0>; + qcom,msm-id = <377 0x0>, <380 0>; qcom,board-id = <0x03010019 0>; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts index e57b835aba88..9207b500a0f3 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts @@ -21,6 +21,6 @@ / { model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; - qcom,msm-id = <377 0x0>; + qcom,msm-id = <377 0x0>, <380 0>; qcom,board-id = <0x010019 0>; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 73faf37deb00..3ce74a06c637 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,7 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SA6155P"; qcom,msm-name = "SA6155P"; - qcom,msm-id = <377 0>; + qcom,msm-id = <377 0>, <380 0>; aliases { pci-domain0 = &pcie0; /* PCIe0 domain */ -- GitLab From f668e01ee5de69dfba51f7eec6793a637dbf90df Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Thu, 17 Jan 2019 14:51:12 +0530 Subject: [PATCH 0961/1286] ARM: dts: msm: Add memshare for trinket Memshare driver allocates and share the memory with the modem clients for their use. The device tree information for memshare driver on trinket are added to specify client details. Change-Id: I129365487f54f0d3f0af0eda110f1e8e8e4140f0 Signed-off-by: Manoj Prabhu B --- arch/arm64/boot/dts/qcom/trinket.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f6ab706410d6..375c34cdbf54 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -662,6 +662,33 @@ #interrupt-cells = <2>; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, -- GitLab From ad388fed3d6108b4cb8841eb126b2d5f8dece824 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 16 Jan 2019 13:47:05 +0530 Subject: [PATCH 0962/1286] ARM: dts: msm: Add support IPA core clock vote for TRINKET Added changes to support IPA core clock vote using RPM. Change-Id: I36a5e5fd27ec2a9c90bfe22f326bf0af24ca80df Signed-off-by: Ashok Vuyyuru --- arch/arm64/boot/dts/qcom/trinket.dtsi | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index d509f98982f0..dfd721669520 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2054,36 +2054,32 @@ qcom,arm-smmu; qcom,smmu-fast-map; qcom,use-ipa-pm; - qcom,bandwidth-vote-for-ipa; + clocks = <&clock_rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core_clk"; qcom,msm-bus,name = "ipa"; qcom,msm-bus,num-cases = <5>; - qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = /* No vote */ , , , - , /* SVS2 */ , , , - , /* SVS */ , , , - , /* NOMINAL */ , , , - , /* TURBO */ , , - , - ; + ; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,throughput-threshold = <310 600 1000>; @@ -2106,7 +2102,7 @@ ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; iommus = <&apps_smmu 0x00E0 0x0>; - qcom,iova-mapping = <0x20000000 0x40000000>; + qcom,iova-mapping = <0x10000000 0x30000000>; /* modem tables in IMEM */ qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; }; -- GitLab From 2541c9927c6af1244f2a0ea5ba53f47ab50270c5 Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Thu, 17 Jan 2019 15:09:27 +0530 Subject: [PATCH 0963/1286] ARM: dts: msm: Change glink intent size for diag on trinket Modify glink intent request size for the diag channels from 1k to 16k for trinket. Change-Id: I0d9b14ffaf7b25b4addabbb32fc1684ca8aace46 Signed-off-by: Manoj Prabhu B --- arch/arm64/boot/dts/qcom/trinket.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index f6ab706410d6..26dfbf791cc4 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1647,6 +1647,21 @@ qcom,glink-channels = "g_glink_audio_data"; qcom,intents = <0x1000 2>; }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; }; }; -- GitLab From d657d13315c715bbe7334d4c7319ff9736c0e5c5 Mon Sep 17 00:00:00 2001 From: Hardik Arya Date: Thu, 10 Jan 2019 15:49:30 +0530 Subject: [PATCH 0964/1286] diag: Synchronize socket read_work_fn and close Currently there is a possibility of NULL pointer dereference because of synchronization is missing in socket read_work_fn and close. The patch adds mutex protection to fix this issue. Change-Id: I82f9907dd233e8cb5811cc380e4813b6541a5420 Signed-off-by: Hardik Arya --- drivers/char/diag/diagfwd_socket.c | 52 ++++++++++++++---------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/drivers/char/diag/diagfwd_socket.c b/drivers/char/diag/diagfwd_socket.c index 6423eae07a05..6e02b0805fa2 100644 --- a/drivers/char/diag/diagfwd_socket.c +++ b/drivers/char/diag/diagfwd_socket.c @@ -576,10 +576,16 @@ static void socket_read_work_fn(struct work_struct *work) struct diag_socket_info, read_work); - if (!info || !info->hdl) + if (!info) return; + mutex_lock(&info->socket_info_mutex); + if (!info->hdl || !info->hdl->sk) { + mutex_unlock(&info->socket_info_mutex); + return; + } err = sock_error(info->hdl->sk); + mutex_unlock(&info->socket_info_mutex); if (unlikely(err == -ENETRESET)) { socket_close_channel(info); if (info->port_type == PORT_TYPE_SERVER) @@ -721,28 +727,24 @@ static int diag_socket_read(void *ctxt, unsigned char *buf, int buf_len) read_msg.msg_name = &src_addr; read_msg.msg_namelen = sizeof(src_addr); - if (info->port_type != PORT_TYPE_SERVER) { - mutex_lock(&info->socket_info_mutex); - if (!info->hdl) { - DIAG_LOG(DIAG_DEBUG_PERIPHERALS, - "%s closing read thread\n", - info->name); - mutex_unlock(&info->socket_info_mutex); - goto fail; - } + mutex_lock(&info->socket_info_mutex); + if (!info->hdl) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s closing read thread\n", + info->name); + mutex_unlock(&info->socket_info_mutex); + goto fail; } err = kernel_sock_ioctl(info->hdl, TIOCINQ, (unsigned long)&pkt_len); if (err || pkt_len < 0) { - if (info->port_type != PORT_TYPE_SERVER) - mutex_unlock(&info->socket_info_mutex); + mutex_unlock(&info->socket_info_mutex); break; } if (pkt_len > bytes_remaining) { buf_full = 1; - if (info->port_type != PORT_TYPE_SERVER) - mutex_unlock(&info->socket_info_mutex); + mutex_unlock(&info->socket_info_mutex); break; } @@ -752,8 +754,7 @@ static int diag_socket_read(void *ctxt, unsigned char *buf, int buf_len) read_len = kernel_recvmsg(info->hdl, &read_msg, &iov, 1, pkt_len, MSG_DONTWAIT); - if (info->port_type != PORT_TYPE_SERVER) - mutex_unlock(&info->socket_info_mutex); + mutex_unlock(&info->socket_info_mutex); if (unlikely(read_len == -ENETRESET)) { mutex_lock(channel_mutex); diagfwd_channel_read_done(info->fwd_ctxt, buf, 0); @@ -861,16 +862,13 @@ static int diag_socket_write(void *ctxt, unsigned char *buf, int len) write_msg.msg_name = &info->remote_addr; write_msg.msg_namelen = sizeof(info->remote_addr); write_msg.msg_flags |= MSG_DONTWAIT; - if (info->port_type != PORT_TYPE_SERVER) { - mutex_lock(&info->socket_info_mutex); - if (!info->hdl) { - mutex_unlock(&info->socket_info_mutex); - return -ENODEV; - } + mutex_lock(&info->socket_info_mutex); + if (!info->hdl) { + mutex_unlock(&info->socket_info_mutex); + return -ENODEV; } write_len = kernel_sendmsg(info->hdl, &write_msg, &iov, 1, len); - if (info->port_type != PORT_TYPE_SERVER) - mutex_unlock(&info->socket_info_mutex); + mutex_unlock(&info->socket_info_mutex); if (write_len < 0) { err = write_len; /* @@ -968,8 +966,7 @@ static void __diag_socket_init(struct diag_socket_info *info) break; } - if (info->port_type == PORT_TYPE_CLIENT) - mutex_init(&info->socket_info_mutex); + mutex_init(&info->socket_info_mutex); info->svc_id = DIAG_SVC_ID; info->ins_id = ins_base + ins_offset; info->inited = 1; @@ -1127,8 +1124,7 @@ static void __diag_socket_exit(struct diag_socket_info *info) if (info->hdl) sock_release(info->hdl); info->hdl = NULL; - if (info->port_type == PORT_TYPE_CLIENT) - mutex_destroy(&info->socket_info_mutex); + mutex_destroy(&info->socket_info_mutex); if (info->wq) destroy_workqueue(info->wq); } -- GitLab From d56fad20b4577a73ccab15c6eef23e670553d53c Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 11 Dec 2018 15:49:15 +0530 Subject: [PATCH 0965/1286] ARM: dts: msm: Add ADC support for sm6150-pm6125-interposer-trinket Add VADC and ADC_TM nodes and user thermal zones for thermistors for sm6150-pm6125-interposer-trinket. Change-Id: I9caf5bf129ab582e07e6fd7a0d76c15814afc909 Signed-off-by: Jishnu Prakash --- .../sm6150-pm6125-interposer-trinket.dtsi | 278 ++++++++++++++++++ 1 file changed, 278 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi b/arch/arm64/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi index 63eab5ccff6a..f4b7508aa8ac 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ #include +#include &spmi_bus { /delete-node/ qcom,pm6150@0; @@ -441,3 +442,280 @@ /delete-property/ clocks; clocks = <&clock_rpmh RPMH_CXO_CLK>; }; + +&pm6125_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + + rf_pa0_therm { + reg = ; + label = "rf_pa0_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&spmi_bus { + qcom,pm6125@0 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, + <&pm6125_vadc ADC_GPIO3_PU2>; + + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>; + + /* Channel nodes */ + rf_pa0_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + status = "disabled"; + }; + + bat_therm { + qcom,lut-index = <1>; + }; + + bat_therm_30k { + qcom,lut-index = <1>; + }; + + bat_therm_400k { + qcom,lut-index = <1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; +}; + +&pmi632_adc_tm { + io-channels = <&pmi632_vadc ADC_GPIO1_PU2>, + <&pmi632_vadc ADC_VBAT_SNS>, + <&pmi632_vadc ADC_GPIO2_PU2>; + + /* Channel nodes */ + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + vbat_sns { + reg = ; + qcom,kernel-client; + qcom,scale-type = <0>; + qcom,prescaling = <3>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + + /delete-node/ sdm-therm; + /delete-node/ conn-therm; + /delete-node/ xo-therm; + /delete-node/ emmc_ufs-therm; + /delete-node/ rf_pa0_therm-therm; + /delete-node/ camera_flash-therm; + /delete-node/ quiet-therm; + + rf-pa0-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + emmc-ufs-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO1_PU2>; + }; + + camera-ftherm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO3_PU2>; + }; + +}; -- GitLab From e60d0ebebfbc02fc4ff718d743d030794528acad Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Wed, 12 Dec 2018 18:53:51 +0530 Subject: [PATCH 0966/1286] defconfig: enable synaptics_tcm driver for SM6150 interposer Enable synaptics_tcm Touch driver for SM6150 interposer trinket. Change-Id: If96ba3eb400b042ce776b65d2dd8297aa7b2a331 Signed-off-by: Vevek Venkatesan --- arch/arm64/configs/vendor/sdmsteppe_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 33e76a3f0e38..22973b22ce89 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -327,6 +327,15 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y -- GitLab From f023ee6b21372667a34200086368cf2c12f43f0d Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Thu, 17 Jan 2019 18:38:03 +0530 Subject: [PATCH 0967/1286] defconfig: enable synaptics_tcm driver for trinket target Enable synaptics_tcm Touch driver for trinket target. Change-Id: I75c3dc277e243e3438b2d4cf84388dc98868852e Signed-off-by: Vevek Venkatesan --- arch/arm64/configs/vendor/trinket-perf_defconfig | 15 +++++++++------ arch/arm64/configs/vendor/trinket_defconfig | 15 +++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a06e1834ce21..0e606f15ac5d 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -302,12 +302,15 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 3b5a024acb50..7dd6d7d170b5 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -314,12 +314,15 @@ CONFIG_TOUCHSCREEN_HIMAX_I2C=y CONFIG_TOUCHSCREEN_HIMAX_INCELL=y CONFIG_TOUCHSCREEN_HIMAX_IC_HX83112=y CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH=y +CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y -- GitLab From 638dcccf15e817ce30d2bcc7138c443ba613ea52 Mon Sep 17 00:00:00 2001 From: Mohamed Sunfeer Date: Thu, 17 Jan 2019 19:08:23 +0530 Subject: [PATCH 0968/1286] qcs405_defconfig: Enable the smcinvoke driver Enable the Smcinvoke driver for qcs40x target. Change-Id: Ie8df3debd46797e6803ae830d57914188cba0ad5 Signed-off-by: Mohamed Sunfeer --- arch/arm/configs/vendor/qcs405-perf_defconfig | 1 + arch/arm/configs/vendor/qcs405_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 4cbd9b6d8d24..7dd2e15d10f3 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -327,6 +327,7 @@ CONFIG_QCOM_GLINK=y CONFIG_QCOM_GLINK_PKT=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_MSM_CDSP_LOADER=y +CONFIG_QCOM_SMCINVOKE=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_QCOM_BIMC_BWMON=y diff --git a/arch/arm/configs/vendor/qcs405_defconfig b/arch/arm/configs/vendor/qcs405_defconfig index 640035fca2b7..91e6b950ead1 100644 --- a/arch/arm/configs/vendor/qcs405_defconfig +++ b/arch/arm/configs/vendor/qcs405_defconfig @@ -464,6 +464,7 @@ CONFIG_QCOM_GLINK_PKT=y # CONFIG_MSM_JTAGV8 is not set CONFIG_QTI_RPM_STATS_LOG=y CONFIG_MSM_CDSP_LOADER=y +CONFIG_QCOM_SMCINVOKE=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y CONFIG_QCOM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y -- GitLab From 5be81a84ae2004cd1f4bfd8c47961988fb792c3a Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Thu, 10 Jan 2019 14:14:30 +0530 Subject: [PATCH 0969/1286] ARM: dts: msm: add touch support in DT for trinket IDP Add Synaptics touch support DT node for trinket IDP platform. Change-Id: Ia45d05da83fb7ef7556b46231304ac60bf0c841e Signed-off-by: Vevek Venkatesan --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 29 +++++++ arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 75 +++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 8e2a69fb8db5..1e8c681be2a3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -238,3 +238,32 @@ qcom,platform-reset-gpio = <&tlmm 90 0>; qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; + +&qupv3_se2_i2c { + status = "okay"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + vdd-supply = <&pm6125_l9>; + avdd-supply = <&pm6125_l21>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,bus-reg-name = "vdd"; + synaptics,pwr-reg-name = "avdd"; + synaptics,irq-gpio = <&tlmm 88 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 87 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 2c820213aafa..693a63a7a497 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -1346,6 +1346,81 @@ output-high; /* active low reset */ }; }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio88", "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; -- GitLab From 963c17c2b801128977edbe4389cabbf43e7842e8 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Thu, 17 Jan 2019 16:30:29 +0530 Subject: [PATCH 0970/1286] ARM: dts: msm: Add GPU speed bin support for Trinket Trinket supports multiple GPU speed bins. This change adds support for all supported GPU speed bins. Specific speed bin will be used based on efuse value. Change-Id: I120920ecdd8cf1e030ceed8fd8b1b9d2fae4410c Signed-off-by: Deepak Kumar --- arch/arm64/boot/dts/qcom/trinket-gpu.dtsi | 326 +++++++++++++++++----- 1 file changed, 255 insertions(+), 71 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi b/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi index d01fd1fcc313..8ac0dd959f15 100644 --- a/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-gpu.dtsi @@ -51,8 +51,10 @@ status = "ok"; reg = <0x5900000 0x90000>, - <0x5961000 0x800>; - reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; + <0x5961000 0x800>, + <0x1b40000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", + "qfprom_memory"; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; @@ -124,6 +126,8 @@ /* Context aware jump target power level */ qcom,ca-target-pwrlevel = <5>; + qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>; + /* GPU Mempools */ qcom,gpu-mempools { #address-cells = <1>; @@ -156,84 +160,264 @@ }; }; - /* Power levels */ - qcom,gpu-pwrlevels { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,gpu-pwrlevels"; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <980000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <11>; - }; - - /* TURBO */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <900000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <9>; - qcom,bus-max = <11>; + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <5>; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <980000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <820000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; }; - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <820000000>; - qcom,bus-freq = <10>; - qcom,bus-min = <9>; - qcom,bus-max = <11>; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <205>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <5>; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <980000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <820000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; }; - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <745000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <10>; + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <198>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <5>; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <950000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <820000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; }; - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <600000000>; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; - - /* SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <465000000>; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <8>; - }; - - /* LOW SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <320000000>; - qcom,bus-freq = <4>; - qcom,bus-min = <3>; - qcom,bus-max = <5>; - }; - - /* XO */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <0>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; }; }; -- GitLab From deed01599aa88c23e47dbf96082e5f26a9067bf8 Mon Sep 17 00:00:00 2001 From: Jitendra Sharma Date: Mon, 19 Mar 2018 14:57:46 +0530 Subject: [PATCH 0971/1286] soc: qcom: pil: Add PDR minidump support This change adds support to collect PD dumps along with minidump on subsystem SSR event. Change-Id: Idf1454bb4f66ae274b73612f4bc7f3d1d5cc895e Signed-off-by: Jitendra Sharma Signed-off-by: Isaac J. Manjarres --- .../devicetree/bindings/pil/subsys-pil-tz.txt | 7 + drivers/soc/qcom/peripheral-loader.c | 349 +++++++++++++++--- drivers/soc/qcom/peripheral-loader.h | 5 +- 3 files changed, 308 insertions(+), 53 deletions(-) diff --git a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt b/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt index 3606df280e7b..1a9ea1ecf07f 100644 --- a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt +++ b/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt @@ -72,6 +72,13 @@ Optional properties: to AOP through qmp mailbox driver. - qcom,mas-crypto: phandle to the bus master of crypto core. +- qcom,minidump-id: ID that is used to index into the global minidump table of + contents to access a subsystem's minidump table of + contents. +- qcom,aux-minidump-ids: List of IDs that index into the global minidump table + of contents to access the table of contents for + additional minidump entries that should be collected + along with the subsystem's minidump. Example: qcom,venus@fdce0000 { diff --git a/drivers/soc/qcom/peripheral-loader.c b/drivers/soc/qcom/peripheral-loader.c index 80700db833be..594a9891f199 100644 --- a/drivers/soc/qcom/peripheral-loader.c +++ b/drivers/soc/qcom/peripheral-loader.c @@ -146,60 +146,247 @@ struct pil_priv { size_t region_size; }; +/** + * struct aux_minidumpinfo - State maintained for each aux minidump entry dumped + * during SSR + * @region_info_aux: region that contains an array of descriptors, where + * each one describes the base address and size of a segment that should be + * dumped during SSR minidump + * @seg_cnt: the number of such regions + */ +struct aux_minidump_info { + struct md_ss_region __iomem *region_info_aux; + unsigned int seg_cnt; +}; + +/** + * map_minidump_regions() - map the region containing the segment descriptors + * for an entry in the global minidump table + * @toc: the subsystem table of contents + * @num_segs: the number of segment descriptors in the region defined by the + * subsystem table of contents + * + * Maps the region containing num_segs segment descriptor into the kernel's + * address space. + */ +static struct md_ss_region __iomem *map_minidump_regions(struct md_ss_toc *toc, + int num_segs) +{ + u64 region_ptr = (u64)toc->md_ss_smem_regions_baseptr; + void __iomem *segtable_base = ioremap((unsigned long)region_ptr, + num_segs * + sizeof(struct md_ss_region)); + struct md_ss_region __iomem *region_info = (struct md_ss_region __iomem + *)segtable_base; + if (!region_info) + return NULL; + + pr_debug("Minidump : Segments in minidump 0x%x\n", num_segs); + + return region_info; +} + +/** + * map_aux_minidump_regions() - map the region containing the segment + * descriptors for a set of entries in the global minidump table + * @desc: descriptor from pil_desc_init() + * @aux_mdump_data: contains an array of pointers to segment descriptor regions + * per auxiliary minidump ID + * @total_aux_segs: value that is incremented to capture the total number of + * segments that are needed to dump all auxiliary regions + * + * Maps the regions of segment descriptors for a set of auxiliary minidump IDs. + */ +static int map_aux_minidump_regions(struct pil_desc *desc, + struct aux_minidump_info *aux_mdump_data, + int *total_aux_segs) +{ + unsigned int i; + struct md_ss_toc *toc; + + for (i = 0; i < desc->num_aux_minidump_ids; i++) { + toc = desc->aux_minidump[i]; + if (toc && (toc->md_ss_toc_init == true) && + (toc->md_ss_enable_status == MD_SS_ENABLED) && + (toc->md_ss_smem_regions_baseptr) && + (toc->encryption_status == MD_SS_ENCR_DONE)) { + aux_mdump_data[i].seg_cnt = toc->ss_region_count; + aux_mdump_data[i].region_info_aux = + map_minidump_regions(desc->aux_minidump[i], + aux_mdump_data[i].seg_cnt); + if (!aux_mdump_data[i].region_info_aux) + return -ENOMEM; + *total_aux_segs += aux_mdump_data[i].seg_cnt; + } + } + + return 0; +} + +/** + * unmap_aux_minidump_regions() - unmap the regions containing the segment + * descriptors for a set of entries in the global minidump table + * @aux_mdump: contains an array of pointers to segment descriptor regions + * per auxiliary minidump ID + * @num_aux_md_ids: the number of auxiliary minidump IDs + * + * Unmaps the regions of segment descriptors for a set of auxiliary minidump + * IDs. + */ +static void unmap_aux_minidump_regions(struct aux_minidump_info *aux_mdump, + int num_aux_md_ids) +{ + unsigned int i = 0; + + while (i < num_aux_md_ids && aux_mdump[i].region_info_aux) { + iounmap(aux_mdump[i].region_info_aux); + i++; + } +} + +/** + * prepare_minidump_segments() - Fills in the necessary information for the + * ramdump driver to dump a region of memory, described by a segment. + * @rd_segs: segments that will be filled in for ramdump collection + * @region_info: the start of the region that contains the segment descriptors + * @num_segs: the number of segment descriptors in region_info + * @ss_valid_seg_cnt: the number of valid segments for this ramdump. Will be + * decremented if a segment is found to be invalid. + * + * Fills in the necessary information in the ramdump_segment structures to + * describe regions that should be dumped by the ramdump driver. + */ +static unsigned int prepare_minidump_segments(struct ramdump_segment *rd_segs, + struct md_ss_region __iomem *region_info, + int num_segs, int *ss_valid_seg_cnt) +{ + void __iomem *offset; + unsigned int i; + unsigned int val_segs = 0; + + + for (i = 0; i < num_segs; i++) { + memcpy(&offset, ®ion_info, sizeof(region_info)); + offset = offset + sizeof(region_info->name) + + sizeof(region_info->seq_num); + if (__raw_readl(offset) == MD_REGION_VALID) { + memcpy(&rd_segs->name, ®ion_info, + sizeof(region_info)); + offset = offset + + sizeof(region_info->md_valid); + rd_segs->address = __raw_readl(offset); + offset = offset + + sizeof(region_info->region_base_address); + rd_segs->size = __raw_readl(offset); + pr_debug("Minidump : Dumping segment %s with address 0x%lx and size 0x%x\n", + rd_segs->name, rd_segs->address, + (unsigned int)rd_segs->size); + rd_segs++; + val_segs++; + } else { + *ss_valid_seg_cnt--; + } + + region_info++; + } + + return val_segs; +} + +/** + * prepare_aux_minidump_segments() - Fills in the necessary information for the + * ramdump driver to dump a region of memory, described by a segment. This is + * done for a set of auxiliary minidump IDs. + * @rd_segs: segments that will be filled in for ramdump collection + * @aux_mdump: contains an array of pointers to segment descriptor regions per + * auxiliary minidump ID + * @ss_valid_seg_cnt: the number of valid segments for this ramdump. Will be + * decremented if a segment is found to be invalid. + * @num_aux_md_ids: the number of auxiliary minidump IDs + * + * Fills in the necessary information in the ramdump_segment structures to + * describe the regions that should be dumped by the ramdump driver for a set + * of auxiliary minidump IDs. + */ +static void prepare_aux_minidump_segments(struct ramdump_segment *rd_segs, + struct aux_minidump_info *aux_mdump, + int *ss_valid_seg_cnt, + int num_aux_md_ids) +{ + unsigned int i; + struct ramdump_segment *s = rd_segs; + unsigned int next_offset = 0; + + for (i = 0; i < num_aux_md_ids; i++) { + s = &rd_segs[next_offset]; + next_offset = prepare_minidump_segments(s, + aux_mdump[i].region_info_aux, + aux_mdump[i].seg_cnt, + ss_valid_seg_cnt); + } +} + static int pil_do_minidump(struct pil_desc *desc, void *ramdump_dev) { - struct md_ss_region __iomem *region_info; - struct ramdump_segment *ramdump_segs, *s; + struct md_ss_region __iomem *region_info_ss; + struct ramdump_segment *ramdump_segs; struct pil_priv *priv = desc->priv; - void __iomem *subsys_segtable_base; - u64 ss_region_ptr = 0; - void __iomem *offset; - int ss_mdump_seg_cnt; + int ss_mdump_seg_cnt_ss = 0, total_segs; + int total_aux_segs = 0; int ss_valid_seg_cnt; - int ret, i; + int ret; + struct aux_minidump_info *aux_minidump_data = NULL; + unsigned int next_offset; - ss_region_ptr = desc->minidump->md_ss_smem_regions_baseptr; if (!ramdump_dev) return -ENODEV; - ss_mdump_seg_cnt = desc->minidump->ss_region_count; - subsys_segtable_base = - ioremap((unsigned long)ss_region_ptr, - ss_mdump_seg_cnt * sizeof(struct md_ss_region)); - region_info = (struct md_ss_region __iomem *)subsys_segtable_base; - if (!region_info) + + ss_mdump_seg_cnt_ss = desc->minidump_ss->ss_region_count; + region_info_ss = map_minidump_regions(desc->minidump_ss, + ss_mdump_seg_cnt_ss); + if (!region_info_ss) return -EINVAL; - pr_debug("Segments in minidump 0x%x\n", ss_mdump_seg_cnt); - ramdump_segs = kcalloc(ss_mdump_seg_cnt, + + if (desc->num_aux_minidump_ids > 0) { + aux_minidump_data = kcalloc(desc->num_aux_minidump_ids, + sizeof(*aux_minidump_data), + GFP_KERNEL); + if (!aux_minidump_data) { + ret = -ENOMEM; + goto setup_fail; + } + + if (map_aux_minidump_regions(desc, aux_minidump_data, + &total_aux_segs) < 0) { + ret = -ENOMEM; + goto mapping_fail; + } + } + + total_segs = ss_mdump_seg_cnt_ss + total_aux_segs; + ramdump_segs = kcalloc(total_segs, sizeof(*ramdump_segs), GFP_KERNEL); - if (!ramdump_segs) - return -ENOMEM; + if (!ramdump_segs) { + ret = -ENOMEM; + goto mapping_fail; + } if (desc->subsys_vmid > 0) ret = pil_assign_mem_to_linux(desc, priv->region_start, (priv->region_end - priv->region_start)); - s = ramdump_segs; - ss_valid_seg_cnt = ss_mdump_seg_cnt; - for (i = 0; i < ss_mdump_seg_cnt; i++) { - memcpy(&offset, ®ion_info, sizeof(region_info)); - offset = offset + sizeof(region_info->name) + - sizeof(region_info->seq_num); - if (__raw_readl(offset) == MD_REGION_VALID) { - memcpy(&s->name, ®ion_info, sizeof(region_info)); - offset = offset + sizeof(region_info->md_valid); - s->address = __raw_readl(offset); - offset = offset + - sizeof(region_info->region_base_address); - s->size = __raw_readl(offset); - pr_debug("Minidump : Dumping segment %s with address 0x%lx and size 0x%x\n", - s->name, s->address, (unsigned int)s->size); - } else - ss_valid_seg_cnt--; - s++; - region_info++; - } + ss_valid_seg_cnt = total_segs; + next_offset = prepare_minidump_segments(ramdump_segs, region_info_ss, + ss_mdump_seg_cnt_ss, + &ss_valid_seg_cnt); + + if (desc->num_aux_minidump_ids > 0) + prepare_aux_minidump_segments(&ramdump_segs[next_offset], + aux_minidump_data, + &ss_valid_seg_cnt, + desc->num_aux_minidump_ids); + ret = do_minidump(ramdump_dev, ramdump_segs, ss_valid_seg_cnt); - kfree(ramdump_segs); if (ret) pil_err(desc, "%s: Minidump collection failed for subsys %s rc:%d\n", __func__, desc->name, ret); @@ -207,6 +394,14 @@ static int pil_do_minidump(struct pil_desc *desc, void *ramdump_dev) if (desc->subsys_vmid > 0) ret = pil_assign_mem_to_subsys(desc, priv->region_start, (priv->region_end - priv->region_start)); + + kfree(ramdump_segs); +mapping_fail: + unmap_aux_minidump_regions(aux_minidump_data, + desc->num_aux_minidump_ids); + kfree(aux_minidump_data); +setup_fail: + iounmap(region_info_ss); return ret; } @@ -226,28 +421,28 @@ int pil_do_ramdump(struct pil_desc *desc, struct pil_seg *seg; int count = 0, ret; - if (desc->minidump) { + if (desc->minidump_ss) { pr_debug("Minidump : md_ss_toc->md_ss_toc_init is 0x%x\n", - (unsigned int)desc->minidump->md_ss_toc_init); + (unsigned int)desc->minidump_ss->md_ss_toc_init); pr_debug("Minidump : md_ss_toc->md_ss_enable_status is 0x%x\n", - (unsigned int)desc->minidump->md_ss_enable_status); + (unsigned int)desc->minidump_ss->md_ss_enable_status); pr_debug("Minidump : md_ss_toc->encryption_status is 0x%x\n", - (unsigned int)desc->minidump->encryption_status); + (unsigned int)desc->minidump_ss->encryption_status); pr_debug("Minidump : md_ss_toc->ss_region_count is 0x%x\n", - (unsigned int)desc->minidump->ss_region_count); + (unsigned int)desc->minidump_ss->ss_region_count); pr_debug("Minidump : md_ss_toc->md_ss_smem_regions_baseptr is 0x%x\n", (unsigned int) - desc->minidump->md_ss_smem_regions_baseptr); + desc->minidump_ss->md_ss_smem_regions_baseptr); /** * Collect minidump if SS ToC is valid and segment table * is initialized in memory and encryption status is set. */ - if ((desc->minidump->md_ss_smem_regions_baseptr != 0) && - (desc->minidump->md_ss_toc_init == true) && - (desc->minidump->md_ss_enable_status == + if ((desc->minidump_ss->md_ss_smem_regions_baseptr != 0) && + (desc->minidump_ss->md_ss_toc_init == true) && + (desc->minidump_ss->md_ss_enable_status == MD_SS_ENABLED)) { - if (desc->minidump->encryption_status == - MD_SS_ENCR_DONE) { + if (desc->minidump_ss->encryption_status == + MD_SS_ENCR_DONE) { pr_debug("Dumping Minidump for %s\n", desc->name); return pil_do_minidump(desc, minidump_dev); @@ -1232,6 +1427,50 @@ bool is_timeout_disabled(void) { return disable_timeouts; } + +static int collect_aux_minidump_ids(struct pil_desc *desc) +{ + u32 id; + const __be32 *p; + struct property *prop; + unsigned int i = 0; + void *aux_toc_addr; + struct device_node *node = desc->dev->of_node; + int num_ids = of_property_count_u32_elems(node, + "qcom,aux-minidump-ids"); + + if (num_ids > 0) { + desc->num_aux_minidump_ids = num_ids; + desc->aux_minidump_ids = kmalloc_array(num_ids, + sizeof(*desc->aux_minidump_ids), + GFP_KERNEL); + if (!desc->aux_minidump_ids) + return -ENOMEM; + + desc->aux_minidump = kmalloc_array(num_ids, + sizeof(*desc->aux_minidump), + GFP_KERNEL); + if (!desc->aux_minidump) { + kfree(desc->aux_minidump_ids); + desc->aux_minidump_ids = NULL; + return -ENOMEM; + } + + of_property_for_each_u32(node, "qcom,aux-minidump-ids", prop, + p, id) { + desc->aux_minidump_ids[i] = id; + aux_toc_addr = &g_md_toc->md_ss_toc[id]; + pr_debug("Minidump: aux_toc_addr is %pa and id: %d\n", + &aux_toc_addr, id); + memcpy(&desc->aux_minidump[i], &aux_toc_addr, + sizeof(aux_toc_addr)); + i++; + } + } + + return 0; +} + /** * pil_desc_init() - Initialize a pil descriptor * @desc: descriptor to initialize @@ -1277,10 +1516,14 @@ int pil_desc_init(struct pil_desc *desc) else { if (g_md_toc && g_md_toc->md_toc_init == true) { ss_toc_addr = &g_md_toc->md_ss_toc[desc->minidump_id]; - pr_debug("Minidump : ss_toc_addr is %pa and desc->minidump_id is %d\n", + pr_debug("Minidump : ss_toc_addr for ss is %pa and desc->minidump_id is %d\n", &ss_toc_addr, desc->minidump_id); - memcpy(&desc->minidump, &ss_toc_addr, + memcpy(&desc->minidump_ss, &ss_toc_addr, sizeof(ss_toc_addr)); + + if (collect_aux_minidump_ids(desc) < 0) + pr_err("Failed to get aux %s minidump ids\n", + desc->name); } } @@ -1324,6 +1567,8 @@ int pil_desc_init(struct pil_desc *desc) err_parse_dt: ida_simple_remove(&pil_ida, priv->id); err: + kfree(desc->aux_minidump); + kfree(desc->aux_minidump_ids); kfree(priv); return ret; } diff --git a/drivers/soc/qcom/peripheral-loader.h b/drivers/soc/qcom/peripheral-loader.h index b99f0431199a..6abe985cca29 100644 --- a/drivers/soc/qcom/peripheral-loader.h +++ b/drivers/soc/qcom/peripheral-loader.h @@ -64,8 +64,11 @@ struct pil_desc { bool signal_aop; struct mbox_client cl; struct mbox_chan *mbox; - struct md_ss_toc *minidump; + struct md_ss_toc *minidump_ss; + struct md_ss_toc **aux_minidump; int minidump_id; + int *aux_minidump_ids; + int num_aux_minidump_ids; }; /** -- GitLab From c3c226e81b7a352cb0a359aee46b76a64475b3fa Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Mon, 14 Jan 2019 15:47:55 -0800 Subject: [PATCH 0972/1286] ARM: dts: msm: Add WLAN PD auxilary minidump ID for MSS on SM8150 Add the auxilary minidump ID for the WLAN PD, so that the dumps for the PD can be collected during modem SSR. Change-Id: I06d38af6c604c1bcd1936425f0436ed9f0a39f36 Signed-off-by: Isaac J. Manjarres --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 112282eb7747..7cfc2fefe290 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1660,6 +1660,7 @@ qcom,proxy-timeout-ms = <10000>; qcom,sysmon-id = <0>; qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; qcom,ssctl-instance-id = <0x12>; qcom,pas-id = <4>; qcom,smem-id = <421>; -- GitLab From 3cda0e1d74c1bcbf6728ffb4ffdcff6f7485a52e Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Wed, 28 Nov 2018 11:05:44 -0800 Subject: [PATCH 0973/1286] msm: ipa: IPA IMP handle vote unvote in 5G SSR Honor the clock devote request while we have already devoted for the clock while handling MDM SSR. Change-Id: I6b6156e6359cb2749d5e2f8fa15adc0cec81b5fa Signed-off-by: Michael Adisumarta --- drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c index 3b8681aec3e0..c1ab441657e2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi_proxy.c @@ -623,6 +623,17 @@ struct ipa_mhi_clk_vote_resp_msg_v01 resp->resp.error = IPA_QMI_ERR_INTERNAL_V01; mutex_lock(&imp_ctx->mutex); + + /* + * returning success for clock unvote request - since it could + * be 5G modem SSR scenario where clocks are already OFF. + */ + if (!vote && imp_ctx->state == IMP_INVALID) { + IMP_DBG("Unvote in Invalid state, no op for clock unvote\n"); + mutex_unlock(&imp_ctx->mutex); + return 0; + } + if (imp_ctx->state != IMP_STARTED) { IMP_ERR("unexpected vote when in state %d\n", imp_ctx->state); mutex_unlock(&imp_ctx->mutex); -- GitLab From 26c2d1923f292abf0fb84140934f40fed24cd47c Mon Sep 17 00:00:00 2001 From: jiad Date: Thu, 17 Jan 2019 07:17:30 +0800 Subject: [PATCH 0974/1286] cnss2: Add daemon_support dts option for QCA6390 ENABLE_DAEMON_SUPPORT is by default enabled. For platforms where cnss_daemon is not needed, number of qmi clients will be 2 and WLAN FW will then wait for cnss_daemon to be connected and CNSS2 will timeout waiting for FW ready. Thus add a dts option to enable daemon_support. Change-Id: I20745a1cd6143a3f826ac6b19ddd602d21164ef2 Signed-off-by: Jia Ding --- Documentation/devicetree/bindings/cnss/cnss-wlan.txt | 4 +++- drivers/net/wireless/cnss2/main.c | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt index 751e498597e1..9d6351baa651 100644 --- a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt +++ b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt @@ -60,7 +60,9 @@ Optional properties: WLAN_EN pin is a gpio or fixed regulator. - qcom,mhi: phandle to indicate the device which needs MHI support. - qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip - specifications, should be drived depending on products + specifications, should be drived depending on products. + - cnss-daemon-support: Boolean property to decide whether cnss_daemon + userspace QMI client is supported. Example: diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c index 6f0fa4c9d491..3b48c6298f27 100644 --- a/drivers/net/wireless/cnss2/main.c +++ b/drivers/net/wireless/cnss2/main.c @@ -38,7 +38,6 @@ #define FW_ASSERT_TIMEOUT 5000 #define CNSS_EVENT_PENDING 2989 -#define CNSS_QUIRKS_DEFAULT BIT(ENABLE_DAEMON_SUPPORT) #ifdef CONFIG_CNSS_EMULATION #define CNSS_MHI_TIMEOUT_DEFAULT 90000 #else @@ -1608,7 +1607,10 @@ static void cnss_misc_deinit(struct cnss_plat_data *plat_priv) static void cnss_init_control_params(struct cnss_plat_data *plat_priv) { - plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT; + if (of_property_read_bool(plat_priv->plat_dev->dev.of_node, + "cnss-daemon-support")) + plat_priv->ctrl_params.quirks |= BIT(ENABLE_DAEMON_SUPPORT); + plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT; plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT; -- GitLab From f0ca633c49b3f6f1765533a20a69eed659e2f2b9 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Mon, 14 Jan 2019 12:30:22 -0800 Subject: [PATCH 0975/1286] power: qpnp-fg-gen4: Support configuring ESR calibration during discharging Add support to configure ESR calibration or measurements done only during discharging. This configuration works mutually exclusive to ESR fast calibration with the required parameters specified by the user. Change-Id: Id9f65e373b988af6dc60b12c932d1efaa81af42c Signed-off-by: Subbaraman Narayanamurthy --- .../power/supply/qcom/qpnp-fg-gen4.txt | 8 + drivers/power/supply/qcom/qpnp-fg-gen4.c | 170 ++++++++++++------ 2 files changed, 119 insertions(+), 59 deletions(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt index d293cf250b5d..c696341648a1 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt @@ -154,6 +154,14 @@ First Level Node - FG Gen4 device This factor will be used when ESR correction delta is applied after the calculation. Default value is 2. +- qcom,fg-esr-calib-dischg: + Usage: optional + Value type: + Definition: Enables ESR calibration only during discharging. This + should be specified only when ESR fast calibration is not + required. Also, ESR discharging timers should be specified + for the proper functionality. + - qcom,fg-esr-pulse-thresh-ma Usage: optional Value type: diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index d784adaa9499..0f3899e3a139 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -104,6 +104,7 @@ #define VBATT_LOW_OFFSET 1 #define SYS_CONFIG_WORD 60 #define SYS_CONFIG_OFFSET 0 +#define SYS_CONFIG2_OFFSET 1 #define PROFILE_LOAD_WORD 65 #define PROFILE_LOAD_OFFSET 0 #define RSLOW_COEFF_DISCHG_WORD 78 @@ -193,6 +194,7 @@ struct fg_dt_props { bool rapid_soc_dec_en; bool five_pin_battery; bool multi_profile_load; + bool esr_calib_dischg; int cutoff_volt_mv; int empty_volt_mv; int cutoff_curr_ma; @@ -3989,6 +3991,104 @@ static int fg_alg_init(struct fg_gen4_chip *chip) return 0; } +static int fg_gen4_esr_calib_config(struct fg_gen4_chip *chip) +{ + struct fg_dev *fg = &chip->fg; + u8 buf[2], val, mask; + int rc; + + if (chip->esr_fast_calib) { + rc = fg_gen4_esr_fast_calib_config(chip, true); + if (rc < 0) + return rc; + } else { + if (chip->dt.esr_timer_chg_slow[TIMER_RETRY] >= 0 && + chip->dt.esr_timer_chg_slow[TIMER_MAX] >= 0) { + rc = fg_set_esr_timer(fg, + chip->dt.esr_timer_chg_slow[TIMER_RETRY], + chip->dt.esr_timer_chg_slow[TIMER_MAX], true, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in setting ESR charge timer, rc=%d\n", + rc); + return rc; + } + } + + if (chip->dt.esr_timer_dischg_slow[TIMER_RETRY] >= 0 && + chip->dt.esr_timer_dischg_slow[TIMER_MAX] >= 0) { + rc = fg_set_esr_timer(fg, + chip->dt.esr_timer_dischg_slow[TIMER_RETRY], + chip->dt.esr_timer_dischg_slow[TIMER_MAX], + false, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in setting ESR discharge timer, rc=%d\n", + rc); + return rc; + } + } + + if (chip->dt.esr_calib_dischg) { + /* Allow ESR calibration only during discharging */ + val = BIT(6) | BIT(7); + mask = BIT(1) | BIT(6) | BIT(7); + rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, + SYS_CONFIG_OFFSET, mask, val, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing SYS_CONFIG_WORD, rc=%d\n", + rc); + return rc; + } + + /* Disable ESR charging timer */ + val = 0; + mask = BIT(0); + rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, + SYS_CONFIG2_OFFSET, mask, val, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing SYS_CONFIG2_OFFSET, rc=%d\n", + rc); + return rc; + } + } else { + /* + * Disable ESR discharging timer and ESR pulsing during + * discharging when ESR fast calibration is disabled. + */ + val = 0; + mask = BIT(6) | BIT(7); + rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, + SYS_CONFIG_OFFSET, mask, val, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing SYS_CONFIG_WORD, rc=%d\n", + rc); + return rc; + } + } + } + + /* + * Delta ESR interrupt threshold should be configured as specified if + * ESR fast calibration is disabled. Else, set it to max (4000 mOhms). + */ + fg_encode(fg->sp, FG_SRAM_DELTA_ESR_THR, + chip->esr_fast_calib ? 4000000 : chip->dt.delta_esr_thr_uohms, + buf); + rc = fg_sram_write(fg, + fg->sp[FG_SRAM_DELTA_ESR_THR].addr_word, + fg->sp[FG_SRAM_DELTA_ESR_THR].addr_byte, buf, + fg->sp[FG_SRAM_DELTA_ESR_THR].len, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing DELTA_ESR_THR, rc=%d\n", rc); + return rc; + } + + return rc; +} + #define BATT_TEMP_HYST_MASK GENMASK(3, 0) #define BATT_TEMP_DELTA_MASK GENMASK(7, 4) #define BATT_TEMP_DELTA_SHIFT 4 @@ -4234,66 +4334,9 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) } } - if (chip->esr_fast_calib) { - rc = fg_gen4_esr_fast_calib_config(chip, true); - if (rc < 0) - return rc; - } else { - if (chip->dt.esr_timer_chg_slow[TIMER_RETRY] >= 0 && - chip->dt.esr_timer_chg_slow[TIMER_MAX] >= 0) { - rc = fg_set_esr_timer(fg, - chip->dt.esr_timer_chg_slow[TIMER_RETRY], - chip->dt.esr_timer_chg_slow[TIMER_MAX], true, - FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in setting ESR charge timer, rc=%d\n", - rc); - return rc; - } - } - - if (chip->dt.esr_timer_dischg_slow[TIMER_RETRY] >= 0 && - chip->dt.esr_timer_dischg_slow[TIMER_MAX] >= 0) { - rc = fg_set_esr_timer(fg, - chip->dt.esr_timer_dischg_slow[TIMER_RETRY], - chip->dt.esr_timer_dischg_slow[TIMER_MAX], - false, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in setting ESR discharge timer, rc=%d\n", - rc); - return rc; - } - } - - /* - * Disable ESR discharging timer and ESR pulsing during - * discharging when ESR fast calibration is disabled. - */ - val = 0; - mask = BIT(6) | BIT(7); - rc = fg_sram_masked_write(fg, SYS_CONFIG_WORD, - SYS_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in writing SYS_CONFIG_WORD, rc=%d\n", rc); - return rc; - } - } - - /* - * Delta ESR interrupt threshold should be configured as specified if - * ESR fast calibration is disabled. Else, set it to max (4000 mOhms). - */ - fg_encode(fg->sp, FG_SRAM_DELTA_ESR_THR, - chip->esr_fast_calib ? 4000000 : chip->dt.delta_esr_thr_uohms, - buf); - rc = fg_sram_write(fg, - fg->sp[FG_SRAM_DELTA_ESR_THR].addr_word, - fg->sp[FG_SRAM_DELTA_ESR_THR].addr_byte, buf, - fg->sp[FG_SRAM_DELTA_ESR_THR].len, FG_IMA_DEFAULT); - if (rc < 0) { - pr_err("Error in writing DELTA_ESR_THR, rc=%d\n", rc); + rc = fg_gen4_esr_calib_config(chip); + if (rc < 0) return rc; - } rc = restore_cycle_count(chip->counter); if (rc < 0) { @@ -4440,6 +4483,15 @@ static int fg_parse_esr_cal_params(struct fg_dev *fg) struct device_node *node = fg->dev->of_node; int rc, i, temp; + if (chip->dt.esr_timer_dischg_slow[TIMER_RETRY] >= 0 && + chip->dt.esr_timer_dischg_slow[TIMER_MAX] >= 0) { + /* ESR calibration only during discharging */ + chip->dt.esr_calib_dischg = of_property_read_bool(node, + "qcom,fg-esr-calib-dischg"); + if (chip->dt.esr_calib_dischg) + return 0; + } + if (!of_find_property(node, "qcom,fg-esr-cal-soc-thresh", NULL) || !of_find_property(node, "qcom,fg-esr-cal-temp-thresh", NULL)) return 0; -- GitLab From 07c841b60c7985fb9cb0b404a6e6315800a786e6 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Thu, 17 Jan 2019 18:12:21 -0500 Subject: [PATCH 0976/1286] msm: ipa: Add IPA producer and consumer clients for AQC Add IPA client enums for AQC producer and consumer pipes. CRs-Fixed: 2304918 Change-Id: Icf1f8105ab8177f7cbc282d11b9fab331baffb97 Signed-off-by: Jinesh K. Jayakumar --- drivers/platform/msm/ipa/ipa_api.c | 4 +++- include/uapi/linux/msm_ipa.h | 7 ++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c index 1fe75ffbd174..7558248ad6a0 100644 --- a/drivers/platform/msm/ipa/ipa_api.c +++ b/drivers/platform/msm/ipa/ipa_api.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -208,6 +208,8 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = { __stringify(IPA_CLIENT_WIGIG_CONS3), __stringify(RESERVERD_PROD_94), __stringify(IPA_CLIENT_WIGIG_CONS4), + __stringify(IPA_CLIENT_AQC_ETHERNET_PROD), + __stringify(IPA_CLIENT_AQC_ETHERNET_CONS), }; /** diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h index 314389e8ee69..d45c33adc3ee 100644 --- a/include/uapi/linux/msm_ipa.h +++ b/include/uapi/linux/msm_ipa.h @@ -336,9 +336,12 @@ enum ipa_client_type { IPA_CLIENT_WIGIG3_CONS = 93, /* RESERVERD PROD = 94, */ IPA_CLIENT_WIGIG4_CONS = 95, + + IPA_CLIENT_AQC_ETHERNET_PROD = 96, + IPA_CLIENT_AQC_ETHERNET_CONS = 97, }; -#define IPA_CLIENT_MAX (IPA_CLIENT_WIGIG4_CONS + 1) +#define IPA_CLIENT_MAX (IPA_CLIENT_AQC_ETHERNET_CONS + 1) #define IPA_CLIENT_WLAN2_PROD IPA_CLIENT_A5_WLAN_AMPDU_PROD #define IPA_CLIENT_Q6_DL_NLO_DATA_PROD IPA_CLIENT_Q6_DL_NLO_DATA_PROD @@ -352,6 +355,8 @@ enum ipa_client_type { #define IPA_CLIENT_WIGIG2_CONS IPA_CLIENT_WIGIG2_CONS #define IPA_CLIENT_WIGIG3_CONS IPA_CLIENT_WIGIG3_CONS #define IPA_CLIENT_WIGIG4_CONS IPA_CLIENT_WIGIG4_CONS +#define IPA_CLIENT_AQC_ETHERNET_PROD IPA_CLIENT_AQC_ETHERNET_PROD +#define IPA_CLIENT_AQC_ETHERNET_CONS IPA_CLIENT_AQC_ETHERNET_CONS #define IPA_CLIENT_IS_APPS_CONS(client) \ ((client) == IPA_CLIENT_APPS_LAN_CONS || \ -- GitLab From 94f26feed9ebd8dd27876aa48713ce727a60a811 Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Mon, 14 Jan 2019 12:35:41 -0800 Subject: [PATCH 0977/1286] power: smb5-lib: Don't turn off the parallel charger on soft JEITA Earlier, as part of a reverse boost workaround, the SMB1390/SMB1355 parallel charger is turned off on soft JEITA condition. While it is happening, even with overall FCC reduced, the charging current now all through main charger increases, which may cause big jump in the main die temp on some platforms, leading to ICL reduction to handle thermal conditions. Update the SW by not explicitly turning off parallel charger in this case. Change-Id: Ibbae6da3399339747934c58395a84a4fd64f0750 Signed-off-by: Harry Yang --- drivers/power/supply/qcom/smb5-lib.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index bac6c41a219b..9cfc3f0c4e4e 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -3974,17 +3974,9 @@ static int smblib_soft_jeita_arb_wa(struct smb_charger *chg) if (!chg->jeita_arb_flag && !soft_jeita) return 0; - if (!chg->cp_disable_votable) - chg->cp_disable_votable = find_votable("CP_DISABLE"); - /* Entering soft JEITA from normal state */ if (!chg->jeita_arb_flag && soft_jeita) { vote(chg->chg_disable_votable, JEITA_ARB_VOTER, true, 0); - /* Disable parallel charging */ - if (chg->pl_disable_votable) - vote(chg->pl_disable_votable, JEITA_ARB_VOTER, true, 0); - if (chg->cp_disable_votable) - vote(chg->cp_disable_votable, JEITA_ARB_VOTER, true, 0); rc = smblib_charge_inhibit_en(chg, true); if (rc < 0) @@ -4030,12 +4022,6 @@ static int smblib_soft_jeita_arb_wa(struct smb_charger *chg) vote(chg->fcc_votable, JEITA_ARB_VOTER, false, 0); vote(chg->fv_votable, JEITA_ARB_VOTER, false, 0); - if (chg->pl_disable_votable) - vote(chg->pl_disable_votable, JEITA_ARB_VOTER, false, - 0); - if (chg->cp_disable_votable) - vote(chg->cp_disable_votable, JEITA_ARB_VOTER, false, - 0); vote(chg->chg_disable_votable, JEITA_ARB_VOTER, false, 0); chg->jeita_arb_flag = false; } -- GitLab From 8439d0748f0a7a440ad2689a696e58e2ad02c974 Mon Sep 17 00:00:00 2001 From: Vadim Solomin Date: Fri, 11 Jan 2019 00:30:24 +0300 Subject: [PATCH 0978/1286] atlantic-forwarding driver v1.0.16 Signed-off-by: Vadim Solomin commit 78002ddb8d6c323953ce663d1d548ef9ef09580f Author: Vadim Solomin Date: Thu Jan 10 14:50:27 2019 +0300 Version 1.0.16 Signed-off-by: Vadim Solomin commit e2a13e1fb19c91cbb7659255c5d2c2b7ac04bd55 Author: Vadim Solomin Date: Thu Jan 10 13:25:46 2019 +0300 Fix MSI-X vectors being disabled on cpu unplug (AQ032) Use pci_alloc_irq_vectors() instead of pci_alloc_irq_vectors_affinity() and set affinity hints manually. Signed-off-by: Vadim Solomin commit 13f7de5ed684dcc09c4c7e4d526e313b5afc89e6 Author: Vadim Solomin Date: Thu Jan 10 09:17:18 2019 +0300 Implement catchall ethtool filter (AQ034) Signed-off-by: Vadim Solomin commit b7bef15ddf23988845c3b135cf5bf6f408450b6a Author: Vadim Solomin Date: Wed Jan 9 06:21:33 2019 +0300 Introduce the config options for forwarding API (AQ033) Signed-off-by: Vadim Solomin commit f39d8180de8249aa0c5c3fb630eff9a576a48ab0 Author: Vadim Solomin Date: Wed Jan 9 05:53:57 2019 +0300 Workaround LRO interrupts issue (ATLDRV-667) Signed-off-by: Vadim Solomin CRs-Fixed: 2309519 Change-Id: Ib250e3c66e1a095024269913c47283535283772b Git-commit: 5b7bb561633dfec8a9a52cbb35c202f40c474cf4 Git-repo: https://github.com/aquantia/linux-4.14-atlantic-forwarding Signed-off-by: Jinesh K. Jayakumar --- drivers/net/ethernet/aquantia/Kconfig | 2 + .../ethernet/aquantia/atlantic-fwd/Kconfig | 44 ++++++ .../ethernet/aquantia/atlantic-fwd/Makefile | 3 +- .../aquantia/atlantic-fwd/atl_common.h | 31 +++- .../aquantia/atlantic-fwd/atl_compat.c | 79 +--------- .../aquantia/atlantic-fwd/atl_compat.h | 51 ++----- .../aquantia/atlantic-fwd/atl_ethtool.c | 141 +++++++++++++----- .../ethernet/aquantia/atlantic-fwd/atl_hw.c | 19 ++- .../ethernet/aquantia/atlantic-fwd/atl_main.c | 4 + .../ethernet/aquantia/atlantic-fwd/atl_regs.h | 2 + .../ethernet/aquantia/atlantic-fwd/atl_ring.c | 64 ++++++-- .../ethernet/aquantia/atlantic-fwd/atl_ring.h | 4 +- 12 files changed, 275 insertions(+), 169 deletions(-) create mode 100644 drivers/net/ethernet/aquantia/atlantic-fwd/Kconfig diff --git a/drivers/net/ethernet/aquantia/Kconfig b/drivers/net/ethernet/aquantia/Kconfig index 7bcedcfa9327..2ba545dea662 100644 --- a/drivers/net/ethernet/aquantia/Kconfig +++ b/drivers/net/ethernet/aquantia/Kconfig @@ -27,6 +27,8 @@ config AQFWD ---help--- This enables the support for forwarding driver for the aQuantia AQtion(tm) Ethernet card. +source "drivers/net/ethernet/aquantia/atlantic-fwd/Kconfig" + config AQFWD_QCOM bool "QTI MSM/MDM target support" depends on AQFWD diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/Kconfig b/drivers/net/ethernet/aquantia/atlantic-fwd/Kconfig new file mode 100644 index 000000000000..4a60625404de --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/Kconfig @@ -0,0 +1,44 @@ +# +# Aquantia atlantic-forwarding driver config +# + +if AQFWD + +config ATLFWD_FWD + bool "Enable forwarding-engine API" + default n + ---help--- + + Say Y to enable the forwarding-engine API + +config ATLFWD_FWD_RXBUF + int + prompt "Rx buffer space for forwarding engine's rings" if ATLFWD_FWD + range 0 320 + default 160 if ATLFWD_FWD + default 0 + ---help--- + + Amount of Rx buffer to reserve for the forwarding-engine + rings. This sets the default value of the fwd_rx_buf_reserve + module option. + + Value in kiB, 0 to 320, defaults to 160 if forwarding-engine + API enabled, 0 otherwise. + +config ATLFWD_FWD_TXBUF + int + prompt "Tx buffer space for forwarding engine's rings" if ATLFWD_FWD + range 0 160 + default 80 if ATLFWD_FWD + default 0 + ---help--- + + Amount of Tx buffer to reserve for the forwarding-engine + rings. This sets the default value of the fwd_tx_buf_reserve + module option. + + Value in kiB, 0 to 320, defaults to 80 if forwarding-engine + API enabled, 0 otherwise. + +endif diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/Makefile b/drivers/net/ethernet/aquantia/atlantic-fwd/Makefile index db1aa6e9d9ef..c25bf1f95327 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/Makefile +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/Makefile @@ -35,10 +35,11 @@ atlantic-fwd-objs := atl_fw.o \ atl_ring.o \ atl_ethtool.o \ atl_trace.o \ - atl_fwd.o \ atl_compat.o \ atl_hwmon.o +atlantic-fwd-$(CONFIG_ATLFWD_FWD) += atl_fwd.o + atlantic-fwd-$(CONFIG_OF) += atl_of.o atlantic-fwd-$(CONFIG_AQFWD_QCOM) += atl_qcom.o diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_common.h b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_common.h index f60358c7a6af..925aca668482 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_common.h +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_common.h @@ -18,7 +18,7 @@ #include #include -#define ATL_VERSION "1.0.15" +#define ATL_VERSION "1.0.16" struct atl_nic; @@ -92,6 +92,8 @@ enum { ATL_RXF_ETYPE_MAX = ATL_ETYPE_FLT_NUM, ATL_RXF_NTUPLE_BASE = ATL_RXF_ETYPE_BASE + ATL_RXF_ETYPE_MAX, ATL_RXF_NTUPLE_MAX = ATL_NTUPLE_FLT_NUM, + ATL_RXF_FLEX_BASE = ATL_RXF_NTUPLE_BASE + ATL_RXF_NTUPLE_MAX, + ATL_RXF_FLEX_MAX = 1, }; enum atl_rxf_common_cmd { @@ -173,6 +175,19 @@ struct atl_rxf_etype { int count; }; +enum atl_flex_cmd { + ATL_FLEX_EN = ATL_RXF_EN, + ATL_FLEX_RXQ = BIT(30), + ATL_FLEX_RXQ_SHIFT = 20, + ATL_FLEX_RXQ_MASK = ATL_RXF_RXQ_MSK << ATL_FLEX_RXQ_SHIFT, + ATL_FLEX_ACT_SHIFT = ATL_RXF_ACT_SHIFT, +}; + +struct atl_rxf_flex { + uint32_t cmd[ATL_RXF_FLEX_MAX]; + int count; +}; + struct atl_queue_vec; #define ATL_NUM_FWD_RINGS ATL_MAX_QUEUES @@ -217,11 +232,14 @@ struct atl_nic { spinlock_t stats_lock; struct work_struct work; +#ifdef CONFIG_ATLFWD_FWD struct atl_fwd fwd; +#endif struct atl_rxf_ntuple rxf_ntuple; struct atl_rxf_vlan rxf_vlan; struct atl_rxf_etype rxf_etype; + struct atl_rxf_flex rxf_flex; }; /* Flags only modified with RTNL lock held */ @@ -318,6 +336,17 @@ extern unsigned atl_min_intr_delay; #define atl_module_param(_name, _type, _mode) \ module_param_named(_name, atl_ ## _name, _type, _mode) +static inline void atl_intr_enable_non_ring(struct atl_nic *nic) +{ + struct atl_hw *hw = &nic->hw; + uint32_t mask = hw->intr_mask; + +#ifdef CONFIG_ATLFWD_FWD + mask |= (uint32_t)(nic->fwd.msi_map); +#endif + atl_intr_enable(hw, mask); +} + netdev_tx_t atl_start_xmit(struct sk_buff *skb, struct net_device *ndev); int atl_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid); int atl_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid); diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.c index 62a56aab8a31..25db52ea89c0 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.c @@ -15,7 +15,8 @@ #include #include -#ifdef ATL_COMPAT_PCI_IRQ_VECTOR +#ifdef ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS + /* From commit aff171641d181ea573380efc3f559c9de4741fc5 */ int atl_compat_pci_irq_vector(struct pci_dev *dev, unsigned int nr) { @@ -45,83 +46,11 @@ int atl_compat_pci_irq_vector(struct pci_dev *dev, unsigned int nr) return dev->irq + nr; } -#endif - -#ifdef ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY - -void atl_compat_set_affinity(int vector, struct atl_queue_vec *qvec) -{ - cpumask_t *cpumask = qvec ? &qvec->affinity_hint : NULL; - - irq_set_affinity_hint(vector, cpumask); -} - -void atl_compat_calc_affinities(struct atl_nic *nic) -{ - struct pci_dev *pdev = nic->hw.pdev; - int i; - unsigned int cpu; - - get_online_cpus(); - cpu = cpumask_first(cpu_online_mask); - - for (i = 0; i < nic->nvecs; i++) { - cpumask_t *cpumask = &nic->qvecs[i].affinity_hint; - int vector; - - /* If some cpus went offline since allocating - * vectors, leave the remaining vectors' affininty - * unset. - */ - if (cpu >= nr_cpumask_bits) - break; - - cpumask_clear(cpumask); - cpumask_set_cpu(cpu, cpumask); - cpu = cpumask_next(cpu, cpu_online_mask); - vector = pci_irq_vector(pdev, i + ATL_NUM_NON_RING_IRQS); - } - put_online_cpus(); -} - -/* from commit 6f9a22bc5775d231ab8fbe2c2f3c88e45e3e7c28 */ -static int irq_calc_affinity_vectors(int minvec, int maxvec, - const struct irq_affinity *affd) +int atl_compat_pci_alloc_irq_vectors(struct pci_dev *dev, + unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { - int resv = affd->pre_vectors + affd->post_vectors; - int vecs = maxvec - resv; - int cpus; - - if (resv > minvec) - return 0; - - /* Stabilize the cpumasks */ - get_online_cpus(); - cpus = cpumask_weight(cpu_online_mask); - put_online_cpus(); - - return min(cpus, vecs) + resv; -} - -/* based on commit 402723ad5c625ee052432698ae5e56b02d38d4ec */ -int atl_compat_pci_alloc_irq_vectors_affinity(struct pci_dev *dev, - unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, - const struct irq_affinity *affd) -{ - static const struct irq_affinity msi_default_affd; int vecs = -ENOSPC; - if (flags & PCI_IRQ_AFFINITY) { - if (!affd) - affd = &msi_default_affd; - } else { - if (WARN_ON(affd)) - affd = NULL; - } - - if (affd) - max_vecs = irq_calc_affinity_vectors(min_vecs, max_vecs, affd); - if (flags & PCI_IRQ_MSIX) { struct msix_entry *entries; int i; diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.h b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.h index 0ec20a3e45ff..92c406d6a6cd 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.h +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_compat.h @@ -17,8 +17,6 @@ #include #include -struct atl_queue_vec; - #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) /* introduced in commit 686fef928bba6be13cabe639f154af7d72b63120 */ @@ -48,25 +46,6 @@ static inline void timer_setup(struct timer_list *timer, #define ETHTOOL_LINK_MODE_2500baseT_Full_BIT 47 #define ETHTOOL_LINK_MODE_5000baseT_Full_BIT 48 -/* from commit 20e407e195b29a4f5a18d713a61f54a75f992bd5 */ -struct irq_affinity { - int pre_vectors; - int post_vectors; -}; - -#define ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY -struct atl_nic; -int atl_compat_pci_alloc_irq_vectors_affinity(struct pci_dev *dev, - unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, - const struct irq_affinity *affd); -static inline int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, - unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, - const struct irq_affinity *affd) -{ - return atl_compat_pci_alloc_irq_vectors_affinity(dev, min_vecs, - max_vecs, flags, affd); -} - #else /* 4.10.0 */ #define ATL_HAVE_MINMAX_MTU @@ -83,7 +62,16 @@ pci_request_mem_regions(struct pci_dev *pdev, const char *name) pci_select_bars(pdev, IORESOURCE_MEM), name); } -#define ATL_COMPAT_PCI_IRQ_VECTOR +#define ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS +int atl_compat_pci_alloc_irq_vectors(struct pci_dev *dev, + unsigned int min_vecs, unsigned int max_vecs, unsigned int flags); +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, + unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) +{ + return atl_compat_pci_alloc_irq_vectors(dev, min_vecs, + max_vecs, flags); +} + int atl_compat_pci_irq_vector(struct pci_dev *dev, unsigned int nr); static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) { @@ -96,19 +84,10 @@ static inline void pci_free_irq_vectors(struct pci_dev *dev) pci_disable_msi(dev); } -static inline int -pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, - unsigned int max_vecs, unsigned int flags) -{ - return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, - NULL); -} - /* from commit 4fe0d154880bb6eb833cbe84fa6f385f400f0b9c */ #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ -#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ #endif /* 4.8.0 */ @@ -164,14 +143,4 @@ static inline void page_ref_inc(struct page *page) #endif /* 4.6.0 */ -#ifdef ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY -void atl_compat_set_affinity(int vector, struct atl_queue_vec *qvec); -void atl_compat_calc_affinities(struct atl_nic *nic); -#else /* ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY */ -static inline void atl_compat_set_affinity(int vector, struct atl_queue_vec *qvec) -{} -static inline void atl_compat_calc_affinities(struct atl_nic *nic) -{} -#endif /* ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY */ - #endif diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ethtool.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ethtool.c index 624a6e30eab9..cb86c0a43343 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ethtool.c @@ -908,7 +908,7 @@ static int atl_set_coalesce(struct net_device *ndev, struct atl_rxf_flt_desc { int base; - int count; + int max; uint32_t rxq_bit; int rxq_shift; size_t cmd_offt; @@ -928,7 +928,7 @@ for (_desc = atl_rxf_descs; \ _desc++) #define atl_for_each_rxf_idx(_desc, _idx) \ - for (_idx = 0; _idx < _desc->count; _idx++) + for (_idx = 0; _idx < _desc->max; _idx++) static inline int atl_rxf_idx(const struct atl_rxf_flt_desc *desc, struct ethtool_rx_flow_spec *fsp) @@ -1091,31 +1091,19 @@ static int atl_rxf_get_ntuple(const struct atl_rxf_flt_desc *desc, return 0; } -static int atl_get_rxf_locs(struct atl_nic *nic, struct ethtool_rxnfc *rxnfc, - uint32_t *rule_locs) +static int atl_rxf_get_flex(const struct atl_rxf_flt_desc *desc, + struct atl_nic *nic, struct ethtool_rx_flow_spec *fsp) { - struct atl_rxf_ntuple *ntuple = &nic->rxf_ntuple; - struct atl_rxf_vlan *vlan = &nic->rxf_vlan; - struct atl_rxf_etype *etype = &nic->rxf_etype; - int count = ntuple->count + vlan->count + etype->count; - int i; - - if (rxnfc->rule_cnt < count) - return -EMSGSIZE; - - for (i = 0; i < ATL_RXF_VLAN_MAX; i++) - if (vlan->cmd[i] & ATL_RXF_EN) - *rule_locs++ = i + ATL_RXF_VLAN_BASE; + struct atl_rxf_flex *flex = &nic->rxf_flex; + int idx = atl_rxf_idx(desc, fsp); + uint32_t cmd = flex->cmd[idx]; - for (i = 0; i < ATL_RXF_ETYPE_MAX; i++) - if (etype->cmd[i] & ATL_RXF_EN) - *rule_locs++ = i + ATL_RXF_ETYPE_BASE; + if (!(cmd & ATL_RXF_EN)) + return -EINVAL; - for (i = 0; i < ATL_RXF_NTUPLE_MAX; i++) - if (ntuple->cmd[i] & ATL_RXF_EN) - *rule_locs++ = i + ATL_RXF_NTUPLE_BASE; + fsp->flow_type = ETHER_FLOW; + fsp->ring_cookie = atl_ring_cookie(desc, cmd); - rxnfc->rule_cnt = count; return 0; } @@ -1141,6 +1129,22 @@ static int atl_check_mask(uint8_t *mask, int len, uint32_t *cmd, uint32_t flag) return 0; } +static int atl_rxf_check_ring(struct atl_nic *nic, uint32_t ring) +{ + if (ring > ATL_RXF_RING_ANY) + return -EINVAL; + + if (ring < nic->nvecs || ring == ATL_RXF_RING_ANY) + return 0; + +#ifdef CONFIG_ATLFWD_FWD + if (test_bit(ring, &nic->fwd.ring_map[ATL_FWDIR_RX])) + return 0; +#endif + + return -EINVAL; +} + static int atl_rxf_set_ring(const struct atl_rxf_flt_desc *desc, struct atl_nic *nic, struct ethtool_rx_flow_spec *fsp, uint32_t *cmd) { @@ -1151,9 +1155,7 @@ static int atl_rxf_set_ring(const struct atl_rxf_flt_desc *desc, return 0; ring = ethtool_get_flow_spec_ring(ring_cookie); - if (ring > ATL_RXF_RING_ANY || - (ring >= nic->nvecs && ring != ATL_RXF_RING_ANY && - !test_bit(ring, &nic->fwd.ring_map[ATL_FWDIR_RX]))) { + if (atl_rxf_check_ring(nic, ring)) { atl_nic_err("Invalid Rx filter queue %d\n", ring); return -EINVAL; } @@ -1577,6 +1579,24 @@ static int atl_rxf_set_ntuple(const struct atl_rxf_flt_desc *desc, return !present; } +static int atl_rxf_set_flex(const struct atl_rxf_flt_desc *desc, + struct atl_nic *nic, struct ethtool_rx_flow_spec *fsp) +{ + struct atl_rxf_flex *flex = &nic->rxf_flex; + int idx = atl_rxf_idx(desc, fsp); + int ret; + uint32_t cmd = ATL_RXF_EN; + int present = !!(flex->cmd[idx] & ATL_RXF_EN);; + + ret = atl_rxf_set_ring(desc, nic, fsp, &cmd); + if (ret) + return ret; + + flex->cmd[idx] = cmd; + + return !present; +} + static void atl_rxf_update_vlan(struct atl_nic *nic, int idx) { atl_write(&nic->hw, ATL_RX_VLAN_FLT(idx), nic->rxf_vlan.cmd[idx]); @@ -1587,10 +1607,15 @@ static void atl_rxf_update_etype(struct atl_nic *nic, int idx) atl_write(&nic->hw, ATL_RX_ETYPE_FLT(idx), nic->rxf_etype.cmd[idx]); } +static void atl_rxf_update_flex(struct atl_nic *nic, int idx) +{ + atl_write(&nic->hw, ATL_RX_FLEX_FLT_CTRL(idx), nic->rxf_flex.cmd[idx]); +} + static const struct atl_rxf_flt_desc atl_rxf_descs[] = { { .base = ATL_RXF_VLAN_BASE, - .count = ATL_RXF_VLAN_MAX, + .max = ATL_RXF_VLAN_MAX, .rxq_bit = ATL_VLAN_RXQ, .rxq_shift = ATL_VLAN_RXQ_SHIFT, .cmd_offt = offsetof(struct atl_nic, rxf_vlan.cmd), @@ -1602,7 +1627,7 @@ static const struct atl_rxf_flt_desc atl_rxf_descs[] = { }, { .base = ATL_RXF_ETYPE_BASE, - .count = ATL_RXF_ETYPE_MAX, + .max = ATL_RXF_ETYPE_MAX, .rxq_bit = ATL_ETYPE_RXQ, .rxq_shift = ATL_ETYPE_RXQ_SHIFT, .cmd_offt = offsetof(struct atl_nic, rxf_etype.cmd), @@ -1613,7 +1638,7 @@ static const struct atl_rxf_flt_desc atl_rxf_descs[] = { }, { .base = ATL_RXF_NTUPLE_BASE, - .count = ATL_RXF_NTUPLE_MAX, + .max = ATL_RXF_NTUPLE_MAX, .rxq_bit = ATL_NTC_RXQ, .rxq_shift = ATL_NTC_RXQ_SHIFT, .cmd_offt = offsetof(struct atl_nic, rxf_ntuple.cmd), @@ -1622,6 +1647,17 @@ static const struct atl_rxf_flt_desc atl_rxf_descs[] = { .set_rxf = atl_rxf_set_ntuple, .update_rxf = atl_update_ntuple_flt, }, + { + .base = ATL_RXF_FLEX_BASE, + .max = ATL_RXF_FLEX_MAX, + .rxq_bit = ATL_FLEX_RXQ, + .rxq_shift = ATL_FLEX_RXQ_SHIFT, + .cmd_offt = offsetof(struct atl_nic, rxf_flex.cmd), + .count_offt = offsetof(struct atl_nic, rxf_flex.count), + .get_rxf = atl_rxf_get_flex, + .set_rxf = atl_rxf_set_flex, + .update_rxf = atl_rxf_update_flex, + }, }; static uint32_t *atl_rxf_cmd(const struct atl_rxf_flt_desc *desc, @@ -1652,7 +1688,7 @@ static const struct atl_rxf_flt_desc *atl_rxf_desc(struct atl_nic *nic, if (loc < desc->base) return NULL; - if (loc < desc->base + desc->count) + if (loc < desc->base + desc->max) return desc; } @@ -1787,6 +1823,46 @@ static int atl_set_rxf(struct atl_nic *nic, return 0; } +static void atl_get_rxf_count(struct atl_nic *nic, struct ethtool_rxnfc *rxnfc) +{ + int count = 0, max = 0; + const struct atl_rxf_flt_desc *desc; + + atl_for_each_rxf_desc(desc) { + count += *atl_rxf_count(desc, nic); + max += desc->max; + } + + rxnfc->rule_cnt = count; + rxnfc->data = max | RX_CLS_LOC_SPECIAL; +} + +static int atl_get_rxf_locs(struct atl_nic *nic, struct ethtool_rxnfc *rxnfc, + uint32_t *rule_locs) +{ + int count = 0; + int i; + const struct atl_rxf_flt_desc *desc; + + atl_for_each_rxf_desc(desc) + count += *atl_rxf_count(desc, nic); + + if (rxnfc->rule_cnt < count) + return -EMSGSIZE; + + atl_for_each_rxf_desc(desc) { + uint32_t *cmd = atl_rxf_cmd(desc, nic); + + atl_for_each_rxf_idx(desc, i) + if (cmd[i] & ATL_RXF_EN) + *rule_locs++ = i + desc->base; + + } + + rxnfc->rule_cnt = count; + return 0; +} + static int atl_get_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *rxnfc, uint32_t *rule_locs) { @@ -1801,10 +1877,7 @@ static int atl_get_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *rxnfc, return 0; case ETHTOOL_GRXCLSRLCNT: - rxnfc->rule_cnt = nic->rxf_ntuple.count + nic->rxf_vlan.count + - nic->rxf_etype.count; - rxnfc->data = (ATL_RXF_VLAN_MAX + ATL_RXF_ETYPE_MAX + - ATL_RXF_NTUPLE_MAX) | RX_CLS_LOC_SPECIAL; + atl_get_rxf_count(nic, rxnfc); return 0; case ETHTOOL_GRXCLSRULE: diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_hw.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_hw.c index 1afd7b738a3d..8582d75d491f 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_hw.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_hw.c @@ -421,7 +421,20 @@ void atl_set_rss_tbl(struct atl_hw *hw) } } -unsigned int atl_fwd_rx_buf_reserve = 0, atl_fwd_tx_buf_reserve = 0; +unsigned int atl_fwd_rx_buf_reserve = +#ifdef CONFIG_ATLFWD_FWD_RXBUF + CONFIG_ATLFWD_FWD_RXBUF; +#else + 0; +#endif + +unsigned int atl_fwd_tx_buf_reserve = +#ifdef CONFIG_ATLFWD_FWD_TXBUF + CONFIG_ATLFWD_FWD_TXBUF; +#else + 0; +#endif + module_param_named(fwd_tx_buf_reserve, atl_fwd_tx_buf_reserve, uint, 0444); module_param_named(fwd_rx_buf_reserve, atl_fwd_rx_buf_reserve, uint, 0444); @@ -519,14 +532,14 @@ void atl_start_hw_global(struct atl_nic *nic) atl_write(hw, ATL_INTR_GEN_INTR_MAP4, BIT(7) | (0 << 0)); atl_write(hw, ATL_TX_INTR_CTRL, BIT(4)); - atl_write(hw, ATL_RX_INTR_CTRL, 2 << 4 | BIT(3)); + atl_write(hw, ATL_RX_INTR_CTRL, BIT(3)); /* Reset Rx/Tx on unexpected PERST# */ atl_write_bit(hw, 0x1000, 29, 0); atl_write(hw, 0x448, 3); /* Enable non-ring interrupts */ - atl_intr_enable(hw, hw->intr_mask | (uint32_t)(nic->fwd.msi_map)); + atl_intr_enable_non_ring(nic); } #define atl_vlan_flt_val(vid) ((uint32_t)(vid) | 1 << 16 | 1 << 31) diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_main.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_main.c index bcd6e1f81b4b..16cd696bf662 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_main.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_main.c @@ -455,7 +455,11 @@ static void atl_remove(struct pci_dev *pdev) /* atl_hw_reset(&nic->hw); */ atl_free_link_intr(nic); unregister_netdev(nic->ndev); + +#ifdef CONFIG_ATLFWD_FWD atl_fwd_release_rings(nic); +#endif + atl_clear_datapath(nic); iounmap(nic->hw.regs); disable_needed = test_and_clear_bit(ATL_ST_ENABLED, &nic->state); diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_regs.h b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_regs.h index aefb5d5a873d..367f7247f947 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_regs.h +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_regs.h @@ -102,6 +102,8 @@ enum mcp_scratchpad { #define ATL_NTUPLE_SPORT(idx) ATL_REG_STRIDE(0x5400, 4, idx) #define ATL_NTUPLE_DPORT(idx) ATL_REG_STRIDE(0x5420, 4, idx) #define ATL_NTUPLE_FLT_NUM 8 +#define ATL_RX_FLEX_FLT_CTRL(idx) ATL_REG_STRIDE(0x5460, 0x20, idx) +#define ATL_FLEX_FLT_NUM 2 #define ATL_RX_RSS_CTRL 0x54c0 #define ATL_RX_RSS_KEY_ADDR 0x54d0 #define ATL_RX_RSS_KEY_WR_DATA 0x54d4 diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c index 2496fe0b05ad..7810d90cd96a 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "atl_trace.h" @@ -844,6 +845,13 @@ static struct sk_buff *atl_process_rx_frag(struct atl_desc_ring *ring, struct atl_pgref *headref = &rxbuf->head, *dataref = &rxbuf->data; struct device *dev = ring->qvec->dev; + if (unlikely(wb->rdm_err)) { + if (skb && skb != (void *)-1l) + dev_kfree_skb_any(skb); + + skb = (void *)-1l; + } + if (!skb) { /* First buffer of a packet */ skb = atl_init_skb(ring, rxbuf, wb); @@ -1070,17 +1078,16 @@ static int atl_config_interrupts(struct atl_nic *nic) struct atl_hw *hw = &nic->hw; unsigned int flags; int ret; - struct irq_affinity iaff = { - .pre_vectors = ATL_NUM_NON_RING_IRQS, - .post_vectors = 0, - }; if (enable_msi) { - flags = PCI_IRQ_MSIX | PCI_IRQ_MSI | PCI_IRQ_AFFINITY; - ret = pci_alloc_irq_vectors_affinity(hw->pdev, + int nvecs; + + nvecs = min_t(int, nic->requested_nvecs, num_present_cpus()); + flags = PCI_IRQ_MSIX | PCI_IRQ_MSI; + ret = pci_alloc_irq_vectors(hw->pdev, ATL_NUM_NON_RING_IRQS + 1, - ATL_NUM_NON_RING_IRQS + nic->requested_nvecs, - flags, &iaff); + ATL_NUM_NON_RING_IRQS + nvecs, + flags); /* pci_alloc_irq_vectors() never allocates less * than min_vectors @@ -1147,6 +1154,34 @@ void atl_clear_datapath(struct atl_nic *nic) nic->qvecs = NULL; } +static void atl_calc_affinities(struct atl_nic *nic) +{ + struct pci_dev *pdev = nic->hw.pdev; + int i; + unsigned int cpu; + + get_online_cpus(); + cpu = cpumask_first(cpu_online_mask); + + for (i = 0; i < nic->nvecs; i++) { + cpumask_t *cpumask = &nic->qvecs[i].affinity_hint; + int vector; + + /* If more vectors got allocated (based on + * cpu_present_mask) than cpus currently online, + * spread the remaining vectors among online cpus. + */ + if (cpu >= nr_cpumask_bits) + cpu = cpumask_first(cpu_online_mask); + + cpumask_clear(cpumask); + cpumask_set_cpu(cpu, cpumask); + cpu = cpumask_next(cpu, cpu_online_mask); + vector = pci_irq_vector(pdev, i + ATL_NUM_NON_RING_IRQS); + } + put_online_cpus(); +} + int atl_setup_datapath(struct atl_nic *nic) { int nvecs, i, ret; @@ -1183,7 +1218,7 @@ int atl_setup_datapath(struct atl_nic *nic) netif_napi_add(nic->ndev, &qvec->napi, atl_poll, 64); } - atl_compat_calc_affinities(nic); + atl_calc_affinities(nic); nic->max_mtu = atl_rx_linear ? ATL_MAX_RX_LINEAR_MTU : ATL_MAX_MTU; @@ -1304,6 +1339,13 @@ static int atl_alloc_ring(struct atl_desc_ring *ring, size_t buf_size, return ret; } +static void atl_set_affinity(int vector, struct atl_queue_vec *qvec) +{ + cpumask_t *cpumask = qvec ? &qvec->affinity_hint : NULL; + + irq_set_affinity_hint(vector, cpumask); +} + static int atl_alloc_qvec_intr(struct atl_queue_vec *qvec) { struct atl_nic *nic = qvec->nic; @@ -1323,7 +1365,7 @@ static int atl_alloc_qvec_intr(struct atl_queue_vec *qvec) return ret; } - atl_compat_set_affinity(vector, qvec); + atl_set_affinity(vector, qvec); return 0; } @@ -1335,7 +1377,7 @@ static void atl_free_qvec_intr(struct atl_queue_vec *qvec) if (!(qvec->nic->flags & ATL_FL_MULTIPLE_VECTORS)) return; - atl_compat_set_affinity(vector, NULL); + atl_set_affinity(vector, NULL); free_irq(vector, &qvec->napi); } diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.h b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.h index bc433db0c6d1..b19e46d13498 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.h +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.h @@ -123,7 +123,7 @@ struct atl_desc_ring { struct atl_ring_stats stats; }; -struct atl_queue_vec { +struct ____cacheline_aligned atl_queue_vec { struct atl_desc_ring tx; struct atl_desc_ring rx; struct device *dev; /* pdev->dev for DMA */ @@ -131,9 +131,7 @@ struct atl_queue_vec { struct atl_nic *nic; unsigned idx; char name[IFNAMSIZ + 10]; -#ifdef ATL_COMPAT_PCI_ALLOC_IRQ_VECTORS_AFFINITY cpumask_t affinity_hint; -#endif }; #define atl_for_each_qvec(nic, qvec) \ -- GitLab From 3c20c4faf69c6bde00be47a054d27bde86f19c83 Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Tue, 8 Jan 2019 18:52:40 -0800 Subject: [PATCH 0979/1286] power-supply: Add VOLTAGE_VPH power supply property Add VOLTAGE_VPH power supply property to expose VPH voltage to user space. Change-Id: I16eb6efe3eef5b173b0f1a66dc21ab6c4c5cb968 Signed-off-by: Harry Yang --- drivers/power/supply/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 5a3e4dc9c66f..9c1d306f67a8 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -391,6 +391,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(qc_opti_disable), POWER_SUPPLY_ATTR(cc_soc), POWER_SUPPLY_ATTR(batt_age_level), + POWER_SUPPLY_ATTR(voltage_vph), /* Charge pump properties */ POWER_SUPPLY_ATTR(cp_status1), POWER_SUPPLY_ATTR(cp_status2), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index b9da4620a61e..402196b35ba2 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -322,6 +322,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_QC_OPTI_DISABLE, POWER_SUPPLY_PROP_CC_SOC, POWER_SUPPLY_PROP_BATT_AGE_LEVEL, + POWER_SUPPLY_PROP_VOLTAGE_VPH, /* Charge pump properties */ POWER_SUPPLY_PROP_CP_STATUS1, POWER_SUPPLY_PROP_CP_STATUS2, -- GitLab From eb677206b36df4ae15c21584577a352689cb8ace Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Thu, 17 Jan 2019 17:06:59 -0800 Subject: [PATCH 0980/1286] msm: ipa: keep proxy clock on if uC loading fails Remove clk unvote if uC loading fails so device does not enter power collapse as uC is needed to restore the registers brought down by power collapse. Change-Id: I569b3138b89191cbdb5a01a2a09090e514f65cc2 Signed-off-by: Michael Adisumarta --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index cbe406470451..5470e4ed3ec8 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -5069,7 +5069,6 @@ static void ipa3_load_ipa_fw(struct work_struct *work) if (result) { IPAERR("IPA uC loading process has failed result=%d\n", result); - ipa3_proxy_clk_unvote(); return; } IPADBG("IPA uC PIL loading succeeded\n"); -- GitLab From d9165e6350584e4b60ce43b12b3bba2aabcbe9da Mon Sep 17 00:00:00 2001 From: Shaoqing Liu Date: Mon, 14 Jan 2019 15:34:13 +0800 Subject: [PATCH 0981/1286] coresight: tpdm: memset tc_dataset in reset_store Memset tc_dataset in reset_store since all resource need be restored as initial value in reset_store. Change-Id: I4b075dd3877d55c5e2e202a0f7c804b703092a53 Signed-off-by: Shaoqing Liu --- drivers/hwtracing/coresight/coresight-tpdm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 81daa9dcbcd4..3aa81bc6afe7 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -924,6 +924,9 @@ static ssize_t reset_store(struct device *dev, if (drvdata->bc != NULL) memset(drvdata->bc, 0, sizeof(struct bc_dataset)); + if (drvdata->tc != NULL) + memset(drvdata->tc, 0, sizeof(struct tc_dataset)); + if (drvdata->dsb != NULL) memset(drvdata->dsb, 0, sizeof(struct dsb_dataset)); -- GitLab From cfca7b85a9475b7bf8be22a56a5993a4abf374e3 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Thu, 17 Jan 2019 21:46:16 -0500 Subject: [PATCH 0982/1286] net: aquantia: support for 32-bit ARM target Add support to build the Aquantia forwarding driver for 32-bit ARM target. CRs-Fixed: 2309519 Change-Id: I4e0596a23fe96f81db12260b210d5cfd6e56b205 Signed-off-by: Jinesh K. Jayakumar --- drivers/net/ethernet/aquantia/Kconfig | 2 +- drivers/net/ethernet/aquantia/atlantic-fwd/atl_fwd.c | 4 ++-- drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/aquantia/Kconfig b/drivers/net/ethernet/aquantia/Kconfig index 2ba545dea662..ad7b1370aaf4 100644 --- a/drivers/net/ethernet/aquantia/Kconfig +++ b/drivers/net/ethernet/aquantia/Kconfig @@ -23,7 +23,7 @@ config AQTION config AQFWD tristate "aQuantia Forwarding driver" - depends on PCI && (X86_64 || ARM64) + depends on PCI && (X86_64 || ARM64 || ARM) ---help--- This enables the support for forwarding driver for the aQuantia AQtion(tm) Ethernet card. diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_fwd.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_fwd.c index d6cdfb335646..5b320366bc3d 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_fwd.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_fwd.c @@ -193,7 +193,7 @@ static void atl_fwd_init_ring(struct atl_fwd_ring *fwd_ring) int lxo_bit = !!(flags & ATL_FWR_LXO); atl_write(hw, ATL_RING_BASE_LSW(ring), ring->daddr); - atl_write(hw, ATL_RING_BASE_MSW(ring), ring->daddr >> 32); + atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->daddr >> 32); if (dir_tx) { atl_write(hw, ATL_TX_RING_THRESH(ring), @@ -511,7 +511,7 @@ int atl_fwd_request_event(struct atl_fwd_event *evt) atl_write(hw, ATL_TX_RING_HEAD_WB_LSW(hwring), evt->tx_head_wrb); atl_write(hw, ATL_TX_RING_HEAD_WB_MSW(hwring), - evt->tx_head_wrb >> 32); + (u64)evt->tx_head_wrb >> 32); return 0; } diff --git a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c index 7810d90cd96a..90cc11e2fd0a 100644 --- a/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c +++ b/drivers/net/ethernet/aquantia/atlantic-fwd/atl_ring.c @@ -1492,7 +1492,7 @@ static void atl_start_rx_ring(struct atl_desc_ring *ring) unsigned int rx_ctl; atl_write(hw, ATL_RING_BASE_LSW(ring), ring->hw.daddr); - atl_write(hw, ATL_RING_BASE_MSW(ring), ring->hw.daddr >> 32); + atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->hw.daddr >> 32); atl_write(hw, ATL_RX_RING_TAIL(ring), ring->tail); atl_write(hw, ATL_RX_RING_BUF_SIZE(ring), @@ -1515,7 +1515,7 @@ static void atl_start_tx_ring(struct atl_desc_ring *ring) struct atl_hw *hw = &nic->hw; atl_write(hw, ATL_RING_BASE_LSW(ring), ring->hw.daddr); - atl_write(hw, ATL_RING_BASE_MSW(ring), ring->hw.daddr >> 32); + atl_write(hw, ATL_RING_BASE_MSW(ring), (u64)ring->hw.daddr >> 32); /* Enable TSO on all active Tx rings */ atl_write(hw, ATL_TX_LSO_CTRL, BIT(nic->nvecs) - 1); -- GitLab From b6263b4b1d20d3c1789c0942f3de4f478b665025 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 9 Jan 2019 22:20:34 -0500 Subject: [PATCH 0983/1286] msm: ipa: IPA EP mapping for AQC ethernet on IPA v4.5 Add IPA 4.5 endpoint configuration for AQC ethernet client. CRs-Fixed: 2304918 Change-Id: I8932b1b4d8b84fbf8e2717b50faea7ae190435ce Signed-off-by: Jinesh K. Jayakumar --- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 2ae3d0825c0f..c4442f14e293 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -2247,6 +2247,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP, QMB_MASTER_SELECT_DDR, { 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } }, + [IPA_4_5][IPA_CLIENT_AQC_ETHERNET_PROD] = { + true, IPA_v4_5_GROUP_UL_DL_SRC, + true, + IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP, + QMB_MASTER_SELECT_DDR, + { 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } }, /* Only for test purpose */ [IPA_4_5][IPA_CLIENT_TEST_PROD] = { true, IPA_v4_5_GROUP_UL_DL_SRC, @@ -2363,6 +2369,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 18, 4, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } }, + [IPA_4_5][IPA_CLIENT_AQC_ETHERNET_CONS] = { + true, IPA_v4_5_GROUP_UL_DL_DST, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 23, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } }, /* Only for test purpose */ /* MBIM aggregation test pipes should have the same QMB as USB_CONS */ [IPA_4_5][IPA_CLIENT_TEST_CONS] = { -- GitLab From 382be32fdcc0ee697b8f13737c3428d65af2384d Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 18 Jan 2019 10:15:45 +0530 Subject: [PATCH 0984/1286] msm: kgsl: Enable efuse read capabilities for A610 GPU A610 GPU has multiple speed bins, for loading a specific speed bin enable speed bin read capability for A610 GPU. Change-Id: I2af316a0ad4211bb8a85bb45fe9ba92bab83c840 Signed-off-by: Deepak Kumar --- drivers/gpu/msm/adreno_a6xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 60d7e50c97c1..9eb144438733 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -2857,6 +2857,7 @@ static const struct { } a6xx_efuse_funcs[] = { { adreno_is_a615_family, a6xx_efuse_speed_bin }, { adreno_is_a612, a6xx_efuse_speed_bin }, + { adreno_is_a610, a6xx_efuse_speed_bin }, }; static void a6xx_check_features(struct adreno_device *adreno_dev) -- GitLab From 4a8150b3ad30a55e55cb514dcbf84bae92870d7b Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Wed, 9 Jan 2019 15:32:29 +0530 Subject: [PATCH 0985/1286] scsi: ufs: Update setting ufs debug error state Do not set ufs debug error state for the command which is retried with -EAGAIN. This is not a fatal error and QMVS tool should not fail validation based on such error. Change-Id: Iaf8e1e81a14bee4c37269ee3f096979ce344dfa4 Signed-off-by: Sayali Lokhande --- drivers/scsi/ufs/ufshcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 0424a41bf886..105f606fb272 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -4001,7 +4001,7 @@ static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, ufshcd_outstanding_req_clear(hba, lrbp->task_tag); } - if (err) + if (err && err != -EAGAIN) ufsdbg_set_err_state(hba); return err; -- GitLab From 2e73b610edef864f202763e7141caab13a8133b4 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Thu, 17 Jan 2019 12:26:17 -0800 Subject: [PATCH 0986/1286] ARM: dts: msm: Enable bus suspend functionality on sdxprairie Set snps,bus-suspend-enable on sdxprairie to enable USB bus suspend functionality. Change-Id: I9caaccd0e6123d573ce0508cf4cc28ce73840374 Signed-off-by: Mayank Rana --- arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index 77ccb8fe15d5..22a83f7c4c72 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -87,6 +87,7 @@ snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; snps,usb3-u1u2-disable; + snps,bus-suspend-enable; usb-core-id = <0>; tx-fifo-resize; maximum-speed = "super-speed-plus"; -- GitLab From 98ecf6163807b97416dfe8dfe98fb378acab2347 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Wed, 16 Jan 2019 17:50:37 +0530 Subject: [PATCH 0987/1286] mmc: core: Make host->card as NULL when card is removed Make host->card as NULL when card is removed otherwise we do see some kernel crashes in async contexts, where host->card is referred (as dangling pointer). Change-Id: Ifff6c7dffa674459add8b1e179f3ff7a8ddc7071 Signed-off-by: Ritesh Harjani --- drivers/mmc/core/bus.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index c4b8c0650595..b0986b6aa31b 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -275,12 +275,15 @@ EXPORT_SYMBOL(mmc_unregister_driver); static void mmc_release_card(struct device *dev) { struct mmc_card *card = mmc_dev_to_card(dev); + struct mmc_host *host = card->host; sdio_free_common_cis(card); kfree(card->info); kfree(card); + if (host) + host->card = NULL; } /* -- GitLab From 92424849c537f7815d4a33c274fff59eb181c7a6 Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Fri, 18 Jan 2019 11:50:12 +0530 Subject: [PATCH 0988/1286] defconfig: msm: Enable memshare driver on trinket Enable memshare driver compilation necessary for allocation of memory for the clients requesting. Change-Id: I12ce0e37012c058bac2d9d8623576fc8214e138b Signed-off-by: Manoj Prabhu B --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 8d7ea5eb354f..a095f3517c52 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -569,6 +569,7 @@ CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y CONFIG_MSM_PM=y CONFIG_QCOM_FSA4480_I2C=y +CONFIG_MEM_SHARE_QMI_SERVICE=y CONFIG_MSM_PERFORMANCE=y CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 3b5a024acb50..8e7d6a81d8a6 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -597,6 +597,7 @@ CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_AVTIMER=y CONFIG_MSM_PM=y CONFIG_QCOM_FSA4480_I2C=y +CONFIG_MEM_SHARE_QMI_SERVICE=y CONFIG_MSM_PERFORMANCE=y CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y -- GitLab From cf8cd96ade85e2a8aebf9d927311d952f5981715 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Fri, 18 Jan 2019 12:00:55 +0530 Subject: [PATCH 0989/1286] defconfig: sdmsteppe: Disable CONFIG_FILE_TABLE_DEBUG This disables CONFIG_FILE_TABLE_DEBUG as not required any more. Change-Id: I5f690becbf7ce83f9aa404196152590e99e57d19 Signed-off-by: Ritesh Harjani --- arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 1 - arch/arm64/configs/vendor/sdmsteppe_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index 5f8c46bb719c..8f649ef48ea4 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -676,7 +676,6 @@ CONFIG_SDCARD_FS=y # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_FILE_TABLE_DEBUG=y CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_MODULE_LOAD_INFO=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 33e76a3f0e38..61a9e24abdcc 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -681,7 +681,6 @@ CONFIG_SDCARD_FS=y # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_FILE_TABLE_DEBUG=y CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_MODULE_LOAD_INFO=y -- GitLab From 534b13a8f2f5bc8aa18375ffcb7c3db8c20f627b Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 16 Jan 2019 12:57:39 +0530 Subject: [PATCH 0990/1286] power: smb5: Fix HVDCP detection configuration for non-PD design Update HVDCP configuration logic to keep HVDCP detection always enabled for non-PD design. Change-Id: Ic9aa3d31b916421546b44842b4171464f41e41f8 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/smb5-lib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index bac6c41a219b..6b155a0cfcc7 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -911,7 +911,7 @@ void smblib_hvdcp_detect_enable(struct smb_charger *chg, bool enable) int rc; u8 mask; - if (chg->hvdcp_disable) + if (chg->hvdcp_disable || chg->pd_not_supported) return; mask = HVDCP_AUTH_ALG_EN_CFG_BIT | HVDCP_EN_BIT; -- GitLab From 5ced67527ea7319a916ed9d806ac6326221f7abf Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Wed, 16 Jan 2019 17:29:58 +0530 Subject: [PATCH 0991/1286] power: smb5: Fix PD capability configuration Currently, PD capability support can be configured either using DT property or by default initialization based on PMIC subtype. However, the DT property value for PD support overrides the default initialization, rendering the default configuration ineffective. Fix this by taking a logical OR between the two control methods. Change-Id: I5d47f80e3b20471ec94a8ea5bddaafee10935952 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/qpnp-smb5.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index 516ac724fbde..eb6801fc30d4 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -407,8 +407,8 @@ static int smb5_parse_dt(struct smb5 *chip) chg->sw_jeita_enabled = of_property_read_bool(node, "qcom,sw-jeita-enable"); - chg->pd_not_supported = of_property_read_bool(node, - "qcom,usb-pd-disable"); + chg->pd_not_supported = chg->pd_not_supported || + of_property_read_bool(node, "qcom,usb-pd-disable"); chg->lpd_disabled = of_property_read_bool(node, "qcom,lpd-disable"); -- GitLab From b51650bf06bb7518210d123cd420cdb0593d2151 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Wed, 26 Dec 2018 16:43:40 +0800 Subject: [PATCH 0992/1286] defconfig: sa8155: enable QMI for CNSS2 CNSS2 platform driver uses QMI framework to communicate with WLAN firmware. It sends and receives boot handshake messages to WLAN firmware, which includes hardware and software capabilities and configurations. It also sends WLAN on/off control message to firmware over QMI channel. CRs-Fixed: 2381673 Change-Id: Ic070cf142c7601f4d458be161833f4e9a34c5c63 Signed-off-by: Yu Wang --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 1 + arch/arm64/configs/vendor/sa8155_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index 883418632e09..e10986375679 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -297,6 +297,7 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y CONFIG_CNSS2=y CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index 8cabd1895149..fd8bcfd93fdc 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -308,6 +308,7 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y CONFIG_CNSS2=y CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set -- GitLab From 4e883cede356df7280d3808435125d9a1d82b7b8 Mon Sep 17 00:00:00 2001 From: GranthaliDhandar Date: Wed, 16 Jan 2019 16:34:29 +0530 Subject: [PATCH 0993/1286] dts: qcom: Add gpu-pwrlevel to support frequency 650MHz,500MHz and 350MHz Add gpu-pwrlevel to support frequency 650MHZ,500MHz and 350MHz on SM6150. Change-Id: Idc9d8fe959c1b2207b5c982b7d965d4f3d716479 Signed-off-by: Granthali Dhandar --- arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi | 140 ++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi b/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi index ab68610afa19..b80d84a2f3aa 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -450,6 +450,144 @@ qcom,bus-max = <0>; }; }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <2>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-6 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; }; }; -- GitLab From d2c66f992c3ec8401d6003203c1eb36c31d0e122 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Tue, 15 Jan 2019 16:32:20 +0800 Subject: [PATCH 0994/1286] defconfig: sa8155: enable CNSS_GENL There are multiple wlan drivers for sa8155, enable CNSS_GENL to support communicating with userspace utilities, such as cnss_diag. CRs-Fixed: 2381682 Change-Id: I6a15e177a2a2114797259135858249a1afeac72a Signed-off-by: Yu Wang --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 1 + arch/arm64/configs/vendor/sa8155_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index e10986375679..1e84758c900f 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -298,6 +298,7 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS2=y CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y +CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index fd8bcfd93fdc..ac5b78b6e571 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -309,6 +309,7 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS2=y CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y +CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set -- GitLab From 3cdf17ded16a4c9a7653e88e515180f745270a7a Mon Sep 17 00:00:00 2001 From: Animesh Kishore Date: Fri, 18 Jan 2019 15:24:22 +0530 Subject: [PATCH 0995/1286] defconfig: qcs405: Enable xlog logging Enable xlog dumps in memory. Change-Id: Ia47af7dc52bcd9ae6d1ebb4a3089037eeb26524c Signed-off-by: Animesh Kishore --- arch/arm64/configs/vendor/qcs405-perf_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index 11fe84787ecf..ec7bd588a581 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -337,6 +337,7 @@ CONFIG_FB_MSM_MDSS_HDMI_PANEL=y CONFIG_FB_MSM_MDSS_SPI_PANEL=y CONFIG_FB_MSM_MDSS_RGB_PANEL=y CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y +CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_SOUND=y CONFIG_SND=y -- GitLab From fd568f7f9a7c69b8c1ff46aad1b88c46ce9c4861 Mon Sep 17 00:00:00 2001 From: Mangesh Kunchamwar Date: Fri, 18 Jan 2019 14:58:35 +0530 Subject: [PATCH 0996/1286] ARM: dts: msm: GPIO for lineout booster in QCS405 Add GPIO node for lineout booster in QCS405. Change-Id: Id4c2ac612331517ea2e6d1f68bfcf8896143ca0a Signed-off-by: Mangesh Kunchamwar --- .../dts/qcom/qcs405-amic-audio-overlay.dtsi | 2 ++ .../boot/dts/qcom/qcs405-audio-overlay.dtsi | 2 ++ .../dts/qcom/qcs405-csra1-audio-overlay.dtsi | 2 ++ .../dts/qcom/qcs405-csra6-audio-overlay.dtsi | 2 ++ .../dts/qcom/qcs405-csra8-audio-overlay.dtsi | 2 ++ arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi | 29 +++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs405-tasha.dtsi | 14 ++++++++- .../dts/qcom/qcs405-tdm-audio-overlay.dtsi | 2 ++ .../dts/qcom/qcs405-wsa-audio-overlay.dtsi | 2 ++ 9 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi index e7ae31f13006..c1f4529d3610 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi @@ -27,6 +27,8 @@ asoc-codec = <&stub_codec>, <&bolero>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; qcom,audio-routing = + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi index b7f681e9a043..26dc6e4804ff 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-audio-overlay.dtsi @@ -66,6 +66,8 @@ qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi index 2707d5b4b995..a068858fb59d 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi @@ -70,6 +70,8 @@ qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi index c1df3ff51001..0b4bf441ef1c 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi @@ -73,6 +73,8 @@ qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi index 2ddd66b5d879..20e1a9ea3a56 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi @@ -74,6 +74,8 @@ qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi index 6a120e3ad285..2e9cbcc650df 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi @@ -2198,6 +2198,35 @@ }; }; }; + + lineout_booster_ctrl { + lineout_booster_sleep: lineout_booster_sleep { + mux { + pins = "gpio113"; + function = "gpio"; + }; + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + lineout_booster_active:lineout_booster_active { + mux { + pins = "gpio113"; + function = "gpio"; + }; + config { + pins = "gpio113"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + emac { emac_mdc: emac_mdc { mux { diff --git a/arch/arm64/boot/dts/qcom/qcs405-tasha.dtsi b/arch/arm64/boot/dts/qcom/qcs405-tasha.dtsi index f6c621546f11..e67fcee902b3 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-tasha.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-tasha.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -42,6 +42,14 @@ pinctrl-0 = <&cdc_reset_active>; pinctrl-1 = <&cdc_reset_sleep>; }; + + lineout_booster_gpio: msm_cdc_pinctrl@113 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,lo-booster-gpio = <&tlmm 113 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&lineout_booster_active>; + pinctrl-1 = <&lineout_booster_sleep>; + }; }; &slim_aud { @@ -96,3 +104,7 @@ "cdc-vdd-rx-h"; }; }; + +&qcs405_snd { + qcom,lineout-booster-gpio = <&lineout_booster_gpio>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi index 1d30aa2a049c..dda3f81e6672 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi @@ -46,6 +46,8 @@ qcom,tdm-vdd-micb-current = <13000>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", diff --git a/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi index b6a6314022a1..1284c6ac4a50 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi @@ -88,6 +88,8 @@ qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; qcom,audio-routing = "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", "AMIC3", "MIC BIAS3", "AMIC4", "MIC BIAS4", "MIC BIAS3", "Analog Mic3", -- GitLab From 0c4581315d8c828951b6fca09a68a41ca58ac423 Mon Sep 17 00:00:00 2001 From: Kedi Xu Date: Fri, 18 Jan 2019 19:18:18 +0800 Subject: [PATCH 0997/1286] HID:correct mag axis config for External viewer External viewer mag axis is different from ACCEL and Gyro, we need change it to Android coordinate system. Change-Id: I90b8427b3cbd176f5daea30e5ff01991ca146ae3 Signed-off-by: Kedi Xu --- drivers/hid/hid-qvr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hid/hid-qvr.c b/drivers/hid/hid-qvr.c index 00ce28967422..16e91f46b8c0 100644 --- a/drivers/hid/hid-qvr.c +++ b/drivers/hid/hid-qvr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -123,8 +123,8 @@ int qvr_send_package_wrap(u8 *message, int msize, struct hid_device *hid) data->gx = -imuData.gx0; data->gy = imuData.gy0; data->gz = -imuData.gz0; - data->mx = -imuData.mx0; - data->my = imuData.my0; + data->mx = -imuData.my0; + data->my = -imuData.mx0; data->mz = -imuData.mz0; trace_qvr_recv_sensor("gyro", data->gts, data->gx, data->gy, data->gz); -- GitLab From 71debd624f8ecc44e15dcaa24354baea9818e35e Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 17 Dec 2018 13:33:59 +0530 Subject: [PATCH 0998/1286] ARM: dts: msm: Add IDP and QRD support for sm6150-interposer-trinket Add support for bat_therm, to ensure correct scaling function is selected, for bat_therm on PMI632 for trinket interposer qrd platform with sm6150 soc. Add rf_patherm_1 channel for trinket interposer IDP platform alone. Change-Id: Idac2ec6d5ca4f54c1fa3ccac261c5be4f57b25b4 Signed-off-by: Jishnu Prakash --- .../qcom/sm6150-interposer-trinket-idp.dtsi | 42 ++++++++++++++++++- .../qcom/sm6150-interposer-trinket-qrd.dtsi | 13 ++++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi index 318cf5ae8f3c..3c66e63dc021 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,6 +14,7 @@ #include #include #include "sm6150-sde-display.dtsi" +#include &pm6125_gpios { key_vol_up { @@ -27,6 +28,45 @@ }; }; +&pm6125_vadc { + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>, + <&pm6125_vadc ADC_GPIO4_PU2>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + &soc { gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi index 518b58557622..25541325a9d1 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -167,3 +167,16 @@ }; }; +&pmi632_vadc { + bat_therm { + qcom,lut-index = <0>; + }; + + bat_therm_30k { + qcom,lut-index = <0>; + }; + + bat_therm_400k { + qcom,lut-index = <0>; + }; +}; -- GitLab From cb31bb4dc51cbb94ff1df0acf6415cf2abeca2a8 Mon Sep 17 00:00:00 2001 From: Yong Ding Date: Thu, 29 Nov 2018 17:39:34 +0800 Subject: [PATCH 0999/1286] soc: qcom: hab: add a dummy hypervisor With such a dummy hypervisor, HAB driver can still be compiled when no real hypervisor relevant files are available. Moreover, it supports the connection creation between two local processes over HAB socket pair and the message transaction over such connection. Change-Id: Ic9102ac3ce067ae8981b185c23bfadef3b4a020c Signed-off-by: Yong Ding --- drivers/soc/qcom/hab/Makefile | 4 + drivers/soc/qcom/hab/hab_comm.c | 270 ++++++++++++++++++++++++++++++++ drivers/soc/qcom/hab/hyp_stub.c | 25 +++ 3 files changed, 299 insertions(+) create mode 100644 drivers/soc/qcom/hab/hab_comm.c create mode 100644 drivers/soc/qcom/hab/hyp_stub.c diff --git a/drivers/soc/qcom/hab/Makefile b/drivers/soc/qcom/hab/Makefile index 09f144724bed..235d303ba494 100644 --- a/drivers/soc/qcom/hab/Makefile +++ b/drivers/soc/qcom/hab/Makefile @@ -26,6 +26,10 @@ ifdef CONFIG_QTI_GVM_QUIN msm_hab_hyp-objs = \ qvm_comm.o \ hab_qvm.o +else +msm_hab_hyp-objs = \ + hab_comm.o \ + hyp_stub.o endif endif diff --git a/drivers/soc/qcom/hab/hab_comm.c b/drivers/soc/qcom/hab/hab_comm.c new file mode 100644 index 000000000000..689254f96e71 --- /dev/null +++ b/drivers/soc/qcom/hab/hab_comm.c @@ -0,0 +1,270 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include "hab.h" + +struct loopback_msg { + struct list_head node; + int payload_size; + struct hab_header header; + char payload[]; +}; + +struct lb_thread_struct { + int stop; /* set by creator */ + int bexited; /* set by thread */ + void *data; /* thread private data */ +}; + +struct loopback_dev { + spinlock_t io_lock; + struct list_head msg_list; + int msg_cnt; + struct task_struct *kthread; /* creator's thread handle */ + struct lb_thread_struct thread_data; /* thread private data */ + wait_queue_head_t thread_queue; + struct loopback_msg *current_msg; +}; + +static int lb_thread_queue_empty(struct loopback_dev *dev) +{ + int ret; + + spin_lock_bh(&dev->io_lock); + ret = list_empty(&dev->msg_list); + spin_unlock_bh(&dev->io_lock); + return ret; +} + + +int lb_kthread(void *d) +{ + struct lb_thread_struct *p = (struct lb_thread_struct *)d; + struct physical_channel *pchan = (struct physical_channel *)p->data; + struct loopback_dev *dev = pchan->hyp_data; + int ret = 0; + + while (!p->stop) { + schedule(); + ret = wait_event_interruptible(dev->thread_queue, + !lb_thread_queue_empty(dev) || + p->stop); + + spin_lock_bh(&dev->io_lock); + + while (!list_empty(&dev->msg_list)) { + struct loopback_msg *msg = NULL; + + msg = list_first_entry(&dev->msg_list, + struct loopback_msg, node); + dev->current_msg = msg; + list_del(&msg->node); + dev->msg_cnt--; + + ret = hab_msg_recv(pchan, &msg->header); + if (ret) { + pr_err("failed %d msg handling sz %d header %d %d %d, %d %X %d, total %d\n", + ret, msg->payload_size, + HAB_HEADER_GET_ID(msg->header), + HAB_HEADER_GET_TYPE(msg->header), + HAB_HEADER_GET_SIZE(msg->header), + msg->header.session_id, + msg->header.signature, + msg->header.sequence, dev->msg_cnt); + } + + kfree(msg); + dev->current_msg = NULL; + } + + spin_unlock_bh(&dev->io_lock); + } + p->bexited = 1; + pr_debug("exit kthread\n"); + return 0; +} + +int physical_channel_send(struct physical_channel *pchan, + struct hab_header *header, + void *payload) +{ + int size = HAB_HEADER_GET_SIZE(*header); /* payload size */ + struct timeval tv; + struct loopback_msg *msg = NULL; + struct loopback_dev *dev = pchan->hyp_data; + + msg = kmalloc(size + sizeof(*msg), GFP_KERNEL); + if (!msg) + return -ENOMEM; + + memcpy(&msg->header, header, sizeof(*header)); + msg->payload_size = size; /* payload size could be zero */ + + if (size && payload) { + if (HAB_HEADER_GET_TYPE(*header) == HAB_PAYLOAD_TYPE_PROFILE) { + struct habmm_xing_vm_stat *pstat = + (struct habmm_xing_vm_stat *)payload; + + do_gettimeofday(&tv); + pstat->tx_sec = tv.tv_sec; + pstat->tx_usec = tv.tv_usec; + } + + memcpy(msg->payload, payload, size); + } + + spin_lock_bh(&dev->io_lock); + list_add_tail(&msg->node, &dev->msg_list); + dev->msg_cnt++; + spin_unlock_bh(&dev->io_lock); + + wake_up_interruptible(&dev->thread_queue); + return 0; +} + +/* loopback read is only used during open */ +int physical_channel_read(struct physical_channel *pchan, + void *payload, + size_t read_size) +{ + struct loopback_dev *dev = pchan->hyp_data; + struct loopback_msg *msg = dev->current_msg; + + if (read_size) { + if (read_size != msg->payload_size) { + pr_err("read size mismatch requested %zd, received %d\n", + read_size, msg->payload_size); + memcpy(payload, msg->payload, min(((int)read_size), + msg->payload_size)); + } else { + memcpy(payload, msg->payload, read_size); + } + } else { + read_size = 0; + } + return read_size; +} + +/* pchan is directly added into the hab_device */ +int loopback_pchan_create(struct hab_device *dev, char *pchan_name) +{ + int result; + struct physical_channel *pchan = NULL; + struct loopback_dev *lb_dev = NULL; + + pchan = hab_pchan_alloc(dev, LOOPBACK_DOM); + if (!pchan) { + result = -ENOMEM; + goto err; + } + + pchan->closed = 0; + strlcpy(pchan->name, pchan_name, sizeof(pchan->name)); + + lb_dev = kzalloc(sizeof(*lb_dev), GFP_KERNEL); + if (!lb_dev) { + result = -ENOMEM; + goto err; + } + + spin_lock_init(&lb_dev->io_lock); + INIT_LIST_HEAD(&lb_dev->msg_list); + + init_waitqueue_head(&lb_dev->thread_queue); + + lb_dev->thread_data.data = pchan; + lb_dev->kthread = kthread_run(lb_kthread, &lb_dev->thread_data, + pchan->name); + if (IS_ERR(lb_dev->kthread)) { + result = PTR_ERR(lb_dev->kthread); + pr_err("failed to create kthread for %s, ret %d\n", + pchan->name, result); + goto err; + } + + pchan->hyp_data = lb_dev; + + return 0; +err: + kfree(lb_dev); + kfree(pchan); + + return result; +} + +void physical_channel_rx_dispatch(unsigned long data) +{ +} + +int habhyp_commdev_alloc(void **commdev, int is_be, char *name, + int vmid_remote, struct hab_device *mmid_device) +{ + struct physical_channel *pchan; + + int ret = loopback_pchan_create(mmid_device, name); + + if (ret) { + pr_err("failed to create %s pchan in mmid device %s, ret %d, pchan cnt %d\n", + name, mmid_device->name, ret, mmid_device->pchan_cnt); + *commdev = NULL; + } else { + pr_debug("loopback physical channel on %s return %d, loopback mode(%d), total pchan %d\n", + name, ret, hab_driver.b_loopback, + mmid_device->pchan_cnt); + pchan = hab_pchan_find_domid(mmid_device, + HABCFG_VMID_DONT_CARE); + *commdev = pchan; + hab_pchan_put(pchan); + + pr_debug("pchan %s vchans %d refcnt %d\n", + pchan->name, pchan->vcnt, get_refcnt(pchan->refcount)); + } + + return ret; +} + +int habhyp_commdev_dealloc(void *commdev) +{ + struct physical_channel *pchan = commdev; + struct loopback_dev *dev = pchan->hyp_data; + struct loopback_msg *msg, *tmp; + int ret; + + spin_lock_bh(&dev->io_lock); + if (!list_empty(&dev->msg_list) || dev->msg_cnt) { + pr_err("pchan %s msg leak cnt %d\n", pchan->name, dev->msg_cnt); + + list_for_each_entry_safe(msg, tmp, &dev->msg_list, node) { + list_del(&msg->node); + dev->msg_cnt--; + kfree(msg); + } + pr_debug("pchan %s msg cnt %d now\n", + pchan->name, dev->msg_cnt); + } + spin_unlock_bh(&dev->io_lock); + + dev->thread_data.stop = 1; + ret = kthread_stop(dev->kthread); + while (!dev->thread_data.bexited) + schedule(); + dev->kthread = NULL; + + /* hyp_data is freed in pchan */ + if (get_refcnt(pchan->refcount) > 1) { + pr_warn("potential leak pchan %s vchans %d refcnt %d\n", + pchan->name, pchan->vcnt, get_refcnt(pchan->refcount)); + } + hab_pchan_put((struct physical_channel *)commdev); + + return 0; +} diff --git a/drivers/soc/qcom/hab/hyp_stub.c b/drivers/soc/qcom/hab/hyp_stub.c new file mode 100644 index 000000000000..c25bbe3ae1b8 --- /dev/null +++ b/drivers/soc/qcom/hab/hyp_stub.c @@ -0,0 +1,25 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include "hab.h" + +int hab_hypervisor_register(void) +{ + hab_driver.b_loopback = 1; + + return 0; +} + +void hab_hypervisor_unregister(void) +{ + hab_hypervisor_unregister_common(); +} -- GitLab From 27ad4651dc9d768a299728ccc54fe3ab888e0c93 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Thu, 3 Jan 2019 14:43:12 -0500 Subject: [PATCH 1000/1286] msm: npu: Show FW status register value if polling timed out When polling for FW status timed out, print out status register value to help check current FW state. Change-Id: I12ab8602ddf3ff298b962693b684822ad7a80987 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index a75e1ab608d2..6c28733d093f 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -421,8 +421,8 @@ static int wait_for_status_ready(struct npu_device *npu_dev, msleep(NPU_FW_TIMEOUT_POLL_INTERVAL_MS); wait_cnt += NPU_FW_TIMEOUT_POLL_INTERVAL_MS; if (wait_cnt >= max_wait_ms) { - pr_err("timeout wait for status %x in %s\n", - status_bits, __func__); + pr_err("timeout wait for status %x[%x] in reg %x\n", + status_bits, ctrl_sts, status_reg); return -EPERM; } } -- GitLab From 0358bf07bd2d678f1db463523a5e4ff35968c084 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Tue, 8 Jan 2019 20:03:46 -0500 Subject: [PATCH 1001/1286] msm: npu: Trace active network count This change is to add debug code to trace active network count in driver and fw. Change-Id: Ie65375df08ba57a28be2f4c1cb32951807d860a8 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_mgr.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index 6c28733d093f..f30555922ebe 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -543,6 +543,8 @@ static struct npu_network *alloc_network(struct npu_host_ctx *ctx, } ctx->network_num++; + pr_debug("%s:Active network num %d\n", __func__, ctx->network_num); + return network; } @@ -613,6 +615,8 @@ static void free_network(struct npu_host_ctx *ctx, struct npu_client *client, kfree(network->stats_buf); memset(network, 0, sizeof(struct npu_network)); ctx->network_num--; + pr_debug("%s:Active network num %d\n", __func__, + ctx->network_num); } else { pr_warn("network %d:%d is in use\n", network->id, atomic_read(&network->ref_cnt)); @@ -769,6 +773,13 @@ static void app_msg_proc(struct npu_host_ctx *host_ctx, uint32_t *msg) load_rsp_pkt->header.status, load_rsp_pkt->header.trans_id); + /* + * The upper 8 bits in flags is the current active + * network count in fw + */ + pr_debug("Current active network count in FW is %d\n", + load_rsp_pkt->header.flags >> 24); + /* * the upper 16 bits in returned network_hdl is * the network ID @@ -806,6 +817,13 @@ static void app_msg_proc(struct npu_host_ctx *host_ctx, uint32_t *msg) unload_rsp_pkt->header.status, unload_rsp_pkt->header.trans_id); + /* + * The upper 8 bits in flags is the current active + * network count in fw + */ + pr_debug("Current active network count in FW is %d\n", + unload_rsp_pkt->header.flags >> 24); + network = get_network_by_hdl(host_ctx, NULL, unload_rsp_pkt->network_hdl); if (!network) { -- GitLab From f92c0ea0b686fac21ae2ec20f203a808d32a9bd0 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 18 Jan 2019 20:00:17 +0530 Subject: [PATCH 1002/1286] ARM: dts: msm: add gpio_key device for VOL_UP button for trinket Add pinctrl configurations for volume up button which utilize PM6125 GPIO 5. Add gpio_key devices for this button on trinket IDP and QRD targets. Change-Id: Iebe1555b37d4ab751eb8335840b104628624637d Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 33 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 33 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index bad09668f380..eb84c0ce1630 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ #include +#include #include #include "trinket-thermal-overlay.dtsi" #include "trinket-sde-display.dtsi" @@ -163,6 +164,38 @@ }; }; +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + &tlmm { smb_int_default: smb_int_default { mux { diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 72ca664fca9c..51b4af6cfac3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -12,6 +12,7 @@ */ #include #include +#include &qupv3_se1_i2c { status = "ok"; @@ -117,6 +118,38 @@ }; }; +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + &tlmm { smb_int_default: smb_int_default { mux { -- GitLab From 2bc9d1d073cf02e3a336eae02a0b080f38051213 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Thu, 17 Jan 2019 17:49:59 -0800 Subject: [PATCH 1003/1286] cnss2: Collect device RAM dump during WLAN driver unload There is a chance that firmware crashes while WLAN driver is unloading. Collect device RAM dump for this case only in debug builds in order to debug the issue. For other builds, ignore it since device is going to be shutdown completely. Change-Id: I16cab04744b376d3104f07255b4421d60ac22d20 Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/main.c | 5 +++++ drivers/net/wireless/cnss2/pci.c | 23 ++++++++++++++++++----- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c index 6f0fa4c9d491..4b3457efca9c 100644 --- a/drivers/net/wireless/cnss2/main.c +++ b/drivers/net/wireless/cnss2/main.c @@ -985,6 +985,11 @@ void cnss_schedule_recovery(struct device *dev, cnss_bus_update_status(plat_priv, CNSS_FW_DOWN); + if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state)) { + cnss_pr_dbg("Driver unload is in progress, ignore schedule recovery\n"); + return; + } + if (in_interrupt() || irqs_disabled()) gfp = GFP_ATOMIC; diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index fdaab03336a9..a1d735bd5a68 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -373,6 +373,18 @@ int cnss_pci_update_status(struct cnss_pci_data *pci_priv, return 0; } +#ifdef CONFIG_CNSS2_DEBUG +static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) +{ + cnss_pci_collect_dump_info(pci_priv, false); + CNSS_ASSERT(0); +} +#else +static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) +{ +} +#endif + static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv) { int ret = 0; @@ -531,6 +543,12 @@ static int cnss_qca6290_shutdown(struct cnss_pci_data *pci_priv) cnss_pci_set_monitor_wake_intr(pci_priv, false); cnss_pci_set_auto_suspended(pci_priv, 0); + if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) && + test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) { + del_timer(&pci_priv->dev_rddm_timer); + cnss_pci_collect_dump(pci_priv); + } + cnss_pci_stop_mhi(pci_priv); ret = cnss_suspend_pci_link(pci_priv); @@ -2069,11 +2087,6 @@ static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl, void *priv, cnss_pr_dbg("MHI status cb is called with reason %s(%d)\n", cnss_mhi_notify_status_to_str(reason), reason); - if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state)) { - cnss_pr_dbg("Driver unload is in progress, ignore device error\n"); - return; - } - switch (reason) { case MHI_CB_IDLE: return; -- GitLab From ff742b52d44051aba8a005440cabdcc7e666a8e9 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 29 Nov 2018 16:52:23 -0800 Subject: [PATCH 1004/1286] ARM: dts: msm: add initial devicetree node for PCIe for sdxprairie Add initial devicetree node to enable PCIe on sdxprairie. Change-Id: I719eddd93e6ec84259a55f1b60e9b2d235c0e812 Signed-off-by: Tony Truong --- arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi | 229 ++++++++++++++++++ .../boot/dts/qcom/sdxprairie-pinctrl.dtsi | 41 ++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 5 + 3 files changed, 275 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi new file mode 100644 index 000000000000..4e00c29a679f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pcie.dtsi @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_a", "int_b", "int_c", "int_d", + "int_global_int"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 141 0 + 0 0 0 1 &intc 0 142 0 + 0 0 0 2 &intc 0 143 0 + 0 0 0 3 &intc 0 144 0 + 0 0 0 4 &intc 0 140 0>; + + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xce 0x0 + 0x1028 0x0b 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x18 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x04 0x0 + 0x10b0 0x0d 0x0 + 0x10b4 0x0a 0x0 + 0x10b8 0x1a 0x0 + 0x10bc 0xc3 0x0 + 0x10c4 0xd0 0x0 + 0x10d4 0x05 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x32 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x05 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x11a0 0x03 0x0 + 0x11ac 0xca 0x0 + 0x11b0 0x1e 0x0 + 0x11b4 0xd8 0x0 + 0x11b8 0x20 0x0 + 0x11bc 0x22 0x0 + 0x106c 0x0a 0x0 + 0x1070 0x10 0x0 + 0x0258 0x16 0x0 + 0x0a58 0x16 0x0 + 0x161c 0xc1 0x0 + 0x1690 0x00 0x0 + 0x13e4 0x02 0x0 + 0x1708 0x02 0x0 + 0x16a0 0x14 0x0 + 0x13d8 0x01 0x0 + 0x16fc 0x01 0x0 + 0x13dc 0x00 0x0 + 0x1700 0x00 0x0 + 0x13e0 0x16 0x0 + 0x16f0 0x13 0x0 + 0x16f4 0x13 0x0 + 0x0b78 0x83 0x0 + 0x0b60 0xe2 0x0 + 0x0b64 0x04 0x0 + 0x0b70 0xff 0x0 + 0x0378 0x83 0x0 + 0x0360 0xe2 0x0 + 0x0364 0x04 0x0 + 0x0370 0xff 0x0 + 0x0088 0x05 0x0 + 0x008c 0x06 0x0 + 0x034c 0x14 0x0 + 0x0350 0xbf 0x0 + 0x03f8 0x0f 0x0 + 0x0888 0x05 0x0 + 0x088c 0x06 0x0 + 0x0b4c 0x14 0x0 + 0x0b50 0xbf 0x0 + 0x0bf8 0x0f 0x0 + 0x1060 0x28 0x0 + 0x0368 0x00 0x0 + 0x0b68 0x00 0x0 + 0x0424 0x10 0x0 + 0x0c24 0x10 0x0 + 0x043c 0x10 0x0 + 0x0c3c 0x10 0x0 + 0x0310 0x00 0x0 + 0x0310 0x00 0x0 + 0x00e4 0x25 0x0 + 0x08e4 0x25 0x0 + 0x000c 0x20 0x0 + 0x080c 0x20 0x0 + 0x0b70 0x3f 0x0 + 0x0b74 0x00 0x0 + 0x0370 0x3f 0x0 + 0x0374 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1.8-supply = <&pmxprairie_l1>; + vreg-0.9-supply = <&pmxprairie_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0.9-voltage-level = <872000 872000 47900>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x40000000>; + + qcom,pcie-phy-ver = <0x1000>; + qcom,use-19p2mhz-aux-clk; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,smmu-sid-base = <0x0200>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_AUX_CLK>, + <&clock_gcc GCC_PCIE_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_PCIE_SLEEP_CLK>, + <&clock_gcc GCC_PCIE_RCHNG_PHY_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_0_sleep_clk", "pcie_phy_refgen_clk"; + + max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>; + + resets = <&clock_gcc GCC_PCIE_BCR>, + <&clock_gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index 7eaa9917b569..a3ec2a0e06ea 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -1288,5 +1288,46 @@ }; }; }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 9b76b40de941..b0b69d11c6da 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -30,6 +30,10 @@ qcom,msm-id = <357 0x10000>, <368 0x10000>; interrupt-parent = <&pdc>; + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -919,6 +923,7 @@ #include "sdxprairie-usb.dtsi" #include "sdxprairie-blsp.dtsi" #include "sdxprairie-audio.dtsi" +#include "sdxprairie-pcie.dtsi" &gdsc_usb30 { status = "ok"; -- GitLab From 92fe8412b765700cb34d52695347e9c0f62307f7 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 17 Jan 2019 17:51:14 -0800 Subject: [PATCH 1005/1286] usb: gadget: f_cdev: Fix memory leak in creating debugfs dir Driver creates two instances dun and nmea and saves debugfs dir handle into a global variable i.e. debugfs.debugfs_root. As a result debugfs_root gets overwritten when second instance gets created. Fix this issue by saving debugfs dir handle to cdev instance. Change-Id: Id4295f021582a0ba677e37755b8bf27656fbcb6f Signed-off-by: Hemant Kumar --- drivers/usb/gadget/function/f_cdev.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/usb/gadget/function/f_cdev.c b/drivers/usb/gadget/function/f_cdev.c index 05bcccec552c..008ba9e168b9 100644 --- a/drivers/usb/gadget/function/f_cdev.c +++ b/drivers/usb/gadget/function/f_cdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, 2013-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2011, 2013-2019, The Linux Foundation. All rights reserved. * Linux Foundation chooses to take subject only to the GPLv2 license terms, * and distributes only under these terms. * @@ -136,6 +136,8 @@ struct f_cdev { unsigned long nbytes_to_port_bridge; unsigned long nbytes_from_port_bridge; + struct dentry *debugfs_root; + /* To test remote wakeup using debugfs */ u8 debugfs_rw_enable; }; @@ -147,12 +149,6 @@ struct f_cdev_opts { u8 port_num; }; -struct usb_cser_debugfs { - struct dentry *debugfs_root; -}; - -static struct usb_cser_debugfs debugfs; - static int major, minors; struct class *fcdev_classp; static DEFINE_IDA(chardev_ida); @@ -165,7 +161,7 @@ static int usb_cser_connect(struct f_cdev *port); static void usb_cser_disconnect(struct f_cdev *port); static struct f_cdev *f_cdev_alloc(char *func_name, int portno); static void usb_cser_free_req(struct usb_ep *ep, struct usb_request *req); -static void usb_cser_debugfs_exit(void); +static void usb_cser_debugfs_exit(struct f_cdev *port); static struct usb_interface_descriptor cser_interface_desc = { .bLength = USB_DT_INTERFACE_SIZE, @@ -883,9 +879,9 @@ static void cser_free_inst(struct usb_function_instance *fi) if (opts->port) { device_destroy(fcdev_classp, MKDEV(major, opts->port->minor)); cdev_del(&opts->port->fcdev_cdev); + usb_cser_debugfs_exit(opts->port); } usb_cser_chardev_deinit(); - usb_cser_debugfs_exit(); kfree(opts->func_name); kfree(opts->port); kfree(opts); @@ -1703,17 +1699,17 @@ static const struct file_operations cser_rem_wakeup_fops = { static void usb_cser_debugfs_init(struct f_cdev *port) { - debugfs.debugfs_root = debugfs_create_dir(port->name, NULL); - if (IS_ERR(debugfs.debugfs_root)) + port->debugfs_root = debugfs_create_dir(port->name, NULL); + if (IS_ERR(port->debugfs_root)) return; debugfs_create_file("remote_wakeup", 0600, - debugfs.debugfs_root, port, &cser_rem_wakeup_fops); + port->debugfs_root, port, &cser_rem_wakeup_fops); } -static void usb_cser_debugfs_exit(void) +static void usb_cser_debugfs_exit(struct f_cdev *port) { - debugfs_remove_recursive(debugfs.debugfs_root); + debugfs_remove_recursive(port->debugfs_root); } static struct f_cdev *f_cdev_alloc(char *func_name, int portno) -- GitLab From 828842bd8f589bb2ce15c5c07ee274d200081510 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 18 Jan 2019 13:44:25 -0800 Subject: [PATCH 1006/1286] usb: gadget: f_cdev: Increase number of char device instance In case DUN and NMEA instances are created on another gadget instance, increase total number of char device instance from 2 to 4. Change-Id: Id0dad281095662465f8543edfc033c40834430a0 Signed-off-by: Hemant Kumar --- drivers/usb/gadget/function/f_cdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/f_cdev.c b/drivers/usb/gadget/function/f_cdev.c index 008ba9e168b9..8befe7bd54a8 100644 --- a/drivers/usb/gadget/function/f_cdev.c +++ b/drivers/usb/gadget/function/f_cdev.c @@ -49,7 +49,7 @@ #define DEVICE_NAME "at_usb" #define MODULE_NAME "msm_usb_bridge" -#define NUM_INSTANCE 2 +#define NUM_INSTANCE 4 #define MAX_CDEV_INST_NAME 15 #define MAX_CDEV_FUNC_NAME 5 -- GitLab From 9217418cf299488e834a02207ed8daf62a19fedc Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Fri, 11 Jan 2019 12:13:35 -0500 Subject: [PATCH 1007/1286] msm: npu: Retry fw loading if it doesn't boot up properly If fw doesn't boot up properly, retry couple times to avoid fw loading failure. Change-Id: I1078bacbcef7a7be883a1161cdd9f61fa23a168c Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_mgr.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index f30555922ebe..e1564ca4bfb7 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -74,7 +74,8 @@ int fw_init(struct npu_device *npu_dev) { uint32_t reg_val; struct npu_host_ctx *host_ctx = &npu_dev->host_ctx; - int ret = 0; + int ret = 0, retry_cnt = 3; + bool need_retry; mutex_lock(&host_ctx->lock); if (host_ctx->fw_state == FW_ENABLED) { @@ -83,6 +84,8 @@ int fw_init(struct npu_device *npu_dev) return 0; } +retry: + need_retry = false; npu_notify_aop(npu_dev, true); if (npu_enable_core_power(npu_dev)) { @@ -139,14 +142,19 @@ int fw_init(struct npu_device *npu_dev) REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val); /* Initialize the host side IPC */ - npu_host_ipc_pre_init(npu_dev); + ret = npu_host_ipc_pre_init(npu_dev); + if (ret) { + pr_err("npu_host_ipc_pre_init failed %d\n", ret); + goto enable_post_clk_fail; + } /* Keep reading ctrl status until NPU is ready */ pr_debug("waiting for status ready from fw\n"); if (wait_for_status_ready(npu_dev, REG_NPU_FW_CTRL_STATUS, - FW_CTRL_STATUS_MAIN_THREAD_READY_BIT)) { + FW_CTRL_STATUS_MAIN_THREAD_READY_VAL)) { ret = -EPERM; + need_retry = true; goto wait_fw_ready_fail; } @@ -183,7 +191,13 @@ int fw_init(struct npu_device *npu_dev) enable_sys_cache_fail: npu_disable_core_power(npu_dev); enable_pw_fail: + npu_notify_aop(npu_dev, false); host_ctx->fw_state = FW_DISABLED; + if (need_retry && (retry_cnt > 0)) { + retry_cnt--; + pr_warn("retry fw init %d\n", retry_cnt); + goto retry; + } mutex_unlock(&host_ctx->lock); return ret; } -- GitLab From 28ced7270cbced1b43f6a01fda52568389d9e21a Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Sat, 12 Jan 2019 21:13:12 -0500 Subject: [PATCH 1008/1286] msm: npu: Add a sysfs node to load/unload fw This change is to add a sysfs node to allow user to load/unload firmware by accessing it. Change-Id: I5115534aec9fcd15e9657dc691a6a493149390d7 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_dev.c | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/media/platform/msm/npu/npu_dev.c b/drivers/media/platform/msm/npu/npu_dev.c index f1314d729aba..744c4d6b4104 100644 --- a/drivers/media/platform/msm/npu/npu_dev.c +++ b/drivers/media/platform/msm/npu/npu_dev.c @@ -68,6 +68,12 @@ static ssize_t npu_show_perf_mode_override(struct device *dev, static ssize_t npu_store_perf_mode_override(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); +static ssize_t npu_show_fw_state(struct device *dev, + struct device_attribute *attr, + char *buf); +static ssize_t npu_store_fw_state(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); static void npu_suspend_devbw(struct npu_device *npu_dev); static void npu_resume_devbw(struct npu_device *npu_dev); static bool npu_is_post_clock(const char *clk_name); @@ -166,11 +172,13 @@ static DEVICE_ATTR(caps, 0444, npu_show_capabilities, NULL); static DEVICE_ATTR(pwr, 0644, npu_show_pwr_state, npu_store_pwr_state); static DEVICE_ATTR(perf_mode_override, 0644, npu_show_perf_mode_override, npu_store_perf_mode_override); +static DEVICE_ATTR(fw_state, 0644, npu_show_fw_state, npu_store_fw_state); static struct attribute *npu_fs_attrs[] = { &dev_attr_caps.attr, &dev_attr_pwr.attr, &dev_attr_perf_mode_override.attr, + &dev_attr_fw_state.attr, NULL }; @@ -307,6 +315,47 @@ static ssize_t npu_store_perf_mode_override(struct device *dev, return count; } +/* ------------------------------------------------------------------------- + * SysFS - firmware state + * ------------------------------------------------------------------------- + */ +static ssize_t npu_show_fw_state(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct npu_device *npu_dev = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%s\n", + (npu_dev->host_ctx.fw_state == FW_ENABLED) ? + "on" : "off"); +} + +static ssize_t npu_store_fw_state(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct npu_device *npu_dev = dev_get_drvdata(dev); + bool enable = false; + int rc; + + if (strtobool(buf, &enable) < 0) + return -EINVAL; + + if (enable) { + pr_debug("%s: fw init\n", __func__); + rc = fw_init(npu_dev); + if (rc) { + pr_err("fw init failed\n"); + return rc; + } + } else { + pr_debug("%s: fw deinit\n", __func__); + fw_deinit(npu_dev, false, true); + } + + return count; +} + /* ------------------------------------------------------------------------- * Power Related * ------------------------------------------------------------------------- -- GitLab From d151c07f6d2377368def7494f9c423ba31372f44 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Mon, 14 Jan 2019 14:59:21 -0500 Subject: [PATCH 1009/1286] msm: npu: Support delayed unloading NPU fw In order to reduce the latency caused by loading NPU fw during switching networks, support delayed unloading fw after network is unloaded. Change-Id: Ibb92ed7f55829ac82158792d8630cd5a187de07f Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_dev.c | 43 +++++++++++++++ .../media/platform/msm/npu/npu_hw_access.c | 21 +------- .../media/platform/msm/npu/npu_hw_access.h | 6 +-- drivers/media/platform/msm/npu/npu_mgr.c | 52 +++++++++++++++++-- drivers/media/platform/msm/npu/npu_mgr.h | 5 +- 5 files changed, 97 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_dev.c b/drivers/media/platform/msm/npu/npu_dev.c index 744c4d6b4104..427a9872fef4 100644 --- a/drivers/media/platform/msm/npu/npu_dev.c +++ b/drivers/media/platform/msm/npu/npu_dev.c @@ -68,6 +68,12 @@ static ssize_t npu_show_perf_mode_override(struct device *dev, static ssize_t npu_store_perf_mode_override(struct device *dev, struct device_attribute *attr, const char *buf, size_t count); +static ssize_t npu_show_fw_unload_delay_ms(struct device *dev, + struct device_attribute *attr, + char *buf); +static ssize_t npu_store_fw_unload_delay_ms(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); static ssize_t npu_show_fw_state(struct device *dev, struct device_attribute *attr, char *buf); @@ -172,6 +178,8 @@ static DEVICE_ATTR(caps, 0444, npu_show_capabilities, NULL); static DEVICE_ATTR(pwr, 0644, npu_show_pwr_state, npu_store_pwr_state); static DEVICE_ATTR(perf_mode_override, 0644, npu_show_perf_mode_override, npu_store_perf_mode_override); +static DEVICE_ATTR(fw_unload_delay_ms, 0644, + npu_show_fw_unload_delay_ms, npu_store_fw_unload_delay_ms); static DEVICE_ATTR(fw_state, 0644, npu_show_fw_state, npu_store_fw_state); static struct attribute *npu_fs_attrs[] = { @@ -179,6 +187,7 @@ static struct attribute *npu_fs_attrs[] = { &dev_attr_pwr.attr, &dev_attr_perf_mode_override.attr, &dev_attr_fw_state.attr, + &dev_attr_fw_unload_delay_ms.attr, NULL }; @@ -315,6 +324,40 @@ static ssize_t npu_store_perf_mode_override(struct device *dev, return count; } +/* ------------------------------------------------------------------------- + * SysFS - Delayed FW unload + * ------------------------------------------------------------------------- + */ +static ssize_t npu_show_fw_unload_delay_ms(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct npu_device *npu_dev = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%d\n", + npu_dev->host_ctx.fw_unload_delay_ms); +} + +static ssize_t npu_store_fw_unload_delay_ms(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct npu_device *npu_dev = dev_get_drvdata(dev); + uint32_t val; + int rc; + + rc = kstrtou32(buf, 10, &val); + if (rc) { + pr_err("Invalid input for fw unload delay setting\n"); + return -EINVAL; + } + + npu_dev->host_ctx.fw_unload_delay_ms = val; + pr_debug("setting fw_unload_delay_ms to %d\n", val); + + return count; +} + /* ------------------------------------------------------------------------- * SysFS - firmware state * ------------------------------------------------------------------------- diff --git a/drivers/media/platform/msm/npu/npu_hw_access.c b/drivers/media/platform/msm/npu/npu_hw_access.c index c7773d52e743..a5b2ea77f85a 100644 --- a/drivers/media/platform/msm/npu/npu_hw_access.c +++ b/drivers/media/platform/msm/npu/npu_hw_access.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -378,25 +378,6 @@ void npu_mem_unmap(struct npu_client *client, int buf_hdl, uint64_t addr) npu_free_npu_ion_buffer(client, buf_hdl); } -/* ------------------------------------------------------------------------- - * Functions - Work Queue - * ------------------------------------------------------------------------- - */ -void npu_destroy_wq(struct workqueue_struct *wq) -{ - destroy_workqueue(wq); -} - -struct workqueue_struct *npu_create_wq(struct npu_host_ctx *host_ctx, - const char *name, wq_hdlr_fn hdlr, struct work_struct *irq_work) -{ - struct workqueue_struct *wq = create_workqueue(name); - - INIT_WORK(irq_work, hdlr); - - return wq; -} - /* ------------------------------------------------------------------------- * Functions - Features * ------------------------------------------------------------------------- diff --git a/drivers/media/platform/msm/npu/npu_hw_access.h b/drivers/media/platform/msm/npu/npu_hw_access.h index c9ad0720b1a3..61457e1ca21c 100644 --- a/drivers/media/platform/msm/npu/npu_hw_access.h +++ b/drivers/media/platform/msm/npu/npu_hw_access.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -78,10 +78,6 @@ void npu_interrupt_ack(struct npu_device *npu_dev, uint32_t intr_num); int32_t npu_interrupt_raise_m0(struct npu_device *npu_dev); int32_t npu_interrupt_raise_dsp(struct npu_device *npu_dev); -struct workqueue_struct *npu_create_wq(struct npu_host_ctx *host_ctx, - const char *name, wq_hdlr_fn hdlr, struct work_struct *irq_work); -void npu_destroy_wq(struct workqueue_struct *wq); - uint8_t npu_hw_clk_gating_enabled(void); uint8_t npu_hw_log_enabled(void); diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index e1564ca4bfb7..afa4ae7b0092 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -40,6 +40,7 @@ * ------------------------------------------------------------------------- */ static void host_irq_wq(struct work_struct *work); +static void fw_deinit_wq(struct work_struct *work); static void turn_off_fw_logging(struct npu_device *npu_dev); static int wait_for_status_ready(struct npu_device *npu_dev, uint32_t status_reg, uint32_t status_bits); @@ -65,6 +66,9 @@ static int npu_send_misc_cmd(struct npu_device *npu_dev, uint32_t q_idx, static int npu_queue_event(struct npu_client *client, struct npu_kevent *evt); static int npu_notify_dsp(struct npu_device *npu_dev, bool pwr_up); static int npu_notify_aop(struct npu_device *npu_dev, bool on); +static void npu_destroy_wq(struct npu_host_ctx *host_ctx); +static struct workqueue_struct *npu_create_wq(struct npu_host_ctx *host_ctx, + const char *name); /* ------------------------------------------------------------------------- * Function Definitions - Init / Deinit @@ -298,8 +302,7 @@ int npu_host_init(struct npu_device *npu_dev) mutex_init(&host_ctx->lock); atomic_set(&host_ctx->ipc_trans_id, 1); - host_ctx->wq = npu_create_wq(host_ctx, "irq_hdl", host_irq_wq, - &host_ctx->irq_work); + host_ctx->wq = npu_create_wq(host_ctx, "npu_wq"); if (!host_ctx->wq) sts = -EPERM; @@ -310,7 +313,7 @@ void npu_host_deinit(struct npu_device *npu_dev) { struct npu_host_ctx *host_ctx = &npu_dev->host_ctx; - npu_destroy_wq(host_ctx->wq); + npu_destroy_wq(host_ctx); mutex_destroy(&host_ctx->lock); } @@ -397,6 +400,40 @@ static void host_irq_wq(struct work_struct *work) host_session_msg_hdlr(npu_dev); } +static void fw_deinit_wq(struct work_struct *work) +{ + struct npu_host_ctx *host_ctx; + struct npu_device *npu_dev; + + pr_debug("%s: deinit fw\n", __func__); + host_ctx = container_of(work, struct npu_host_ctx, fw_deinit_work.work); + npu_dev = container_of(host_ctx, struct npu_device, host_ctx); + + if (atomic_read(&host_ctx->fw_deinit_work_cnt) == 0) + return; + + do { + fw_deinit(npu_dev, false, true); + } while (!atomic_dec_and_test(&host_ctx->fw_deinit_work_cnt)); +} + +static void npu_destroy_wq(struct npu_host_ctx *host_ctx) +{ + flush_delayed_work(&host_ctx->fw_deinit_work); + destroy_workqueue(host_ctx->wq); +} + +static struct workqueue_struct *npu_create_wq(struct npu_host_ctx *host_ctx, + const char *name) +{ + struct workqueue_struct *wq = create_workqueue(name); + + INIT_WORK(&host_ctx->irq_work, host_irq_wq); + INIT_DELAYED_WORK(&host_ctx->fw_deinit_work, fw_deinit_wq); + + return wq; +} + static void turn_off_fw_logging(struct npu_device *npu_dev) { struct ipc_cmd_log_state_pkt log_packet; @@ -1433,7 +1470,14 @@ int32_t npu_host_unload_network(struct npu_client *client, if (ret) pr_err("network unload failed to set power level\n"); mutex_unlock(&host_ctx->lock); - fw_deinit(npu_dev, false, true); + if (host_ctx->fw_unload_delay_ms) { + flush_delayed_work(&host_ctx->fw_deinit_work); + atomic_inc(&host_ctx->fw_deinit_work_cnt); + queue_delayed_work(host_ctx->wq, &host_ctx->fw_deinit_work, + msecs_to_jiffies(host_ctx->fw_unload_delay_ms)); + } else { + fw_deinit(npu_dev, false, true); + } return ret; } diff --git a/drivers/media/platform/msm/npu/npu_mgr.h b/drivers/media/platform/msm/npu/npu_mgr.h index 56de0c144374..03439ebbd98f 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.h +++ b/drivers/media/platform/msm/npu/npu_mgr.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -78,6 +78,8 @@ struct npu_host_ctx { int32_t fw_ref_cnt; int32_t power_vote_num; struct work_struct irq_work; + struct delayed_work fw_deinit_work; + atomic_t fw_deinit_work_cnt; struct workqueue_struct *wq; struct completion loopback_done; struct completion fw_deinit_done; @@ -86,6 +88,7 @@ struct npu_host_ctx { bool sys_cache_disable; uint32_t fw_dbg_mode; uint32_t exec_flags_override; + uint32_t fw_unload_delay_ms; atomic_t ipc_trans_id; atomic_t network_exeute_cnt; -- GitLab From 51b27d27ed62a5a002f9d4d7f9d5f0a8cf5e359b Mon Sep 17 00:00:00 2001 From: Conner Huff Date: Thu, 17 Jan 2019 13:48:53 -0800 Subject: [PATCH 1010/1286] drivers: rmnet: Add option for wq context packets Timer in perf module requires that packets be passed to gro cells instead of regular GRO path since wq context has no access to napi struct. This change allows for clients of rmnet to designate what context packets they are delivering to rmnet are coming from. Change-Id: I24e1430d85494e5e04405fc3be901f68214022d5 Signed-off-by: Conner Huff --- .../ethernet/qualcomm/rmnet/rmnet_handlers.c | 61 ++++++++++++++++++- .../ethernet/qualcomm/rmnet/rmnet_handlers.h | 10 ++- 2 files changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c index a76423c8d654..07e57262f4be 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -86,11 +86,15 @@ void rmnet_set_skb_proto(struct sk_buff *skb) EXPORT_SYMBOL(rmnet_set_skb_proto); /* Shs hook handler */ - int (*rmnet_shs_skb_entry)(struct sk_buff *skb, struct rmnet_port *port) __rcu __read_mostly; EXPORT_SYMBOL(rmnet_shs_skb_entry); +/* Shs hook handler for work queue*/ +int (*rmnet_shs_skb_entry_wq)(struct sk_buff *skb, + struct rmnet_port *port) __rcu __read_mostly; +EXPORT_SYMBOL(rmnet_shs_skb_entry_wq); + /* Generic handler */ void @@ -133,6 +137,59 @@ rmnet_deliver_skb(struct sk_buff *skb, struct rmnet_port *port) } EXPORT_SYMBOL(rmnet_deliver_skb); +/* Important to note, port cannot be used here if it has gone stale */ +void +rmnet_deliver_skb_wq(struct sk_buff *skb, struct rmnet_port *port, + enum rmnet_packet_context ctx) +{ + int (*rmnet_shs_stamp)(struct sk_buff *skb, struct rmnet_port *port); + struct rmnet_priv *priv = netdev_priv(skb->dev); + + trace_rmnet_low(RMNET_MODULE, RMNET_DLVR_SKB, 0xDEF, 0xDEF, + 0xDEF, 0xDEF, (void *)skb, NULL); + skb_reset_transport_header(skb); + skb_reset_network_header(skb); + rmnet_vnd_rx_fixup(skb->dev, skb->len); + + skb->pkt_type = PACKET_HOST; + skb_set_mac_header(skb, 0); + + /* packets coming from work queue context due to packet flush timer + * must go through the special workqueue path in SHS driver + */ + rmnet_shs_stamp = (!ctx) ? rcu_dereference(rmnet_shs_skb_entry) : + rcu_dereference(rmnet_shs_skb_entry_wq); + if (rmnet_shs_stamp) { + rmnet_shs_stamp(skb, port); + return; + } + + if (ctx == RMNET_NET_RX_CTX) { + if (port->data_format & RMNET_INGRESS_FORMAT_DL_MARKER) { + if (!rmnet_check_skb_can_gro(skb) && + port->dl_marker_flush >= 0) { + struct napi_struct *napi = + get_current_napi_context(); + napi_gro_receive(napi, skb); + port->dl_marker_flush++; + } else { + netif_receive_skb(skb); + } + } else { + if (!rmnet_check_skb_can_gro(skb)) + gro_cells_receive(&priv->gro_cells, skb); + else + netif_receive_skb(skb); + } + } else { + if ((port->data_format & RMNET_INGRESS_FORMAT_DL_MARKER) && + port->dl_marker_flush >= 0) + port->dl_marker_flush++; + gro_cells_receive(&priv->gro_cells, skb); + } +} +EXPORT_SYMBOL(rmnet_deliver_skb_wq); + /* MAP handler */ static void diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.h b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.h index a6299eac3476..9bb7b8dcd192 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.h +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.h @@ -1,4 +1,5 @@ -/* Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved. +/* Copyright (c) 2013, 2016-2017, 2019 + * The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,8 +19,15 @@ #include "rmnet_config.h" +enum rmnet_packet_context { + RMNET_NET_RX_CTX, + RMNET_WQ_CTX, +}; + void rmnet_egress_handler(struct sk_buff *skb); void rmnet_deliver_skb(struct sk_buff *skb, struct rmnet_port *port); +void rmnet_deliver_skb_wq(struct sk_buff *skb, struct rmnet_port *port, + enum rmnet_packet_context ctx); void rmnet_set_skb_proto(struct sk_buff *skb); rx_handler_result_t _rmnet_map_ingress_handler(struct sk_buff *skb, struct rmnet_port *port); -- GitLab From 3641c7e3cafb0c8ec3fdabc41186269436f1e034 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Thu, 17 Jan 2019 18:12:30 -0800 Subject: [PATCH 1011/1286] cnss2: Suspend/resume PCIe link and MHI even without WLAN driver Even WLAN host driver is not present, still suspend/resume PCIe and MHI during runtime PM feature so that it can be tested properly. Change-Id: I9306a2503f47a106abbc1c93f43b6021a1b82f92 Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index a1d735bd5a68..da611a6b2cf9 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -1138,6 +1138,8 @@ static int cnss_pci_runtime_suspend(struct device *dev) if (driver_ops && driver_ops->runtime_ops && driver_ops->runtime_ops->runtime_suspend) ret = driver_ops->runtime_ops->runtime_suspend(pci_dev); + else + ret = cnss_auto_suspend(dev); cnss_pr_info("Runtime suspend status: %d\n", ret); @@ -1165,6 +1167,8 @@ static int cnss_pci_runtime_resume(struct device *dev) if (driver_ops && driver_ops->runtime_ops && driver_ops->runtime_ops->runtime_resume) ret = driver_ops->runtime_ops->runtime_resume(pci_dev); + else + ret = cnss_auto_resume(dev); cnss_pr_info("Runtime resume status: %d\n", ret); -- GitLab From 2859df60e266c19b511665aea8c09bcfe7ae02ae Mon Sep 17 00:00:00 2001 From: Samyukta Mogily Date: Mon, 7 Jan 2019 17:05:55 +0530 Subject: [PATCH 1012/1286] msm: camera: dtsi: Adding camera dtsi for trinket mtp,cdp and qrd Adding camera dtsi with required csid, csiphy, cci, vfe, cpp nodes, which enables camera on trinket. Change-Id: Iedb2546c462abf2dcffc9424b53c867dcebd5243 Signed-off-by: Samyukta Mogily --- .../bindings/media/video/msm-csi-phy.txt | 41 + .../bindings/media/video/msm-csid.txt | 52 ++ .../bindings/media/video/msm-eeprom.txt | 199 +++++ .../dts/qcom/trinket-camera-sensor-idp.dtsi | 230 ++++++ arch/arm64/boot/dts/qcom/trinket-camera.dtsi | 768 ++++++++++++++++++ .../boot/dts/qcom/trinket-idp-overlay.dts | 1 + arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 2 + arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 226 ++++++ arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 9 files changed, 1520 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/video/msm-csi-phy.txt create mode 100644 Documentation/devicetree/bindings/media/video/msm-csid.txt create mode 100644 Documentation/devicetree/bindings/media/video/msm-eeprom.txt create mode 100644 arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/trinket-camera.dtsi diff --git a/Documentation/devicetree/bindings/media/video/msm-csi-phy.txt b/Documentation/devicetree/bindings/media/video/msm-csi-phy.txt new file mode 100644 index 000000000000..24a3443113e5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/video/msm-csi-phy.txt @@ -0,0 +1,41 @@ +* Qualcomm Technologies, Inc. MSM CSI Phy + +Required properties: +- cell-index: csi phy hardware core index +- compatible : + - "qcom,csiphy" + - "qcom,csiphy-v2.0" + - "qcom,csiphy-v2.2" + - "qcom,csiphy-v3.0" + - "qcom,csiphy-v3.1" + - "qcom,csiphy-v3.1.1" + - "qcom,csiphy-v3.2" + - "qcom,csiphy-v3.4.2" + - "qcom,csiphy-v3.5" + - "qcom,csiphy-v5.0" + - "qcom,csiphy-v5.01" + - "qcom,csiphy-v10.00" +- reg : offset and length of the register set for the device + for the csiphy operating in compatible mode. +- reg-names : should specify relevant names to each reg property defined. +- interrupts : should contain the csiphy interrupt. +- interrupt-names : should specify relevant names to each interrupts + property defined. +- clock-names: name of the clocks required for the device +- qcom,clock-rates: clock rate in Hz + - 0 if appropriate clock is required but doesn't have to apply the rate + +Example: + + qcom,csiphy@fda0ac00 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0xfda0ac00 0x200>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + clock-names = "camss_top_ahb_clk", + "ispif_ahb_clk", "csiphy_timer_src_clk", + "csiphy_timer_clk"; + qcom,clock-rates = <0 0 200000000 0>; + }; diff --git a/Documentation/devicetree/bindings/media/video/msm-csid.txt b/Documentation/devicetree/bindings/media/video/msm-csid.txt new file mode 100644 index 000000000000..340d98688b76 --- /dev/null +++ b/Documentation/devicetree/bindings/media/video/msm-csid.txt @@ -0,0 +1,52 @@ +* Qualcomm Technologies, Inc. MSM CSID + +Required properties: +- cell-index: csid hardware core index +- compatible : + - "qcom,csid" + - "qcom,csid-v2.0" + - "qcom,csid-v2.2" + - "qcom,csid-v3.0" + - "qcom,csid-v3.1" + - "qcom,csid-v3.2" + - "qcom,csid-v3.5" + - "qcom,csid-v4.0" + - "qcom,csid-v3.4.2" + - "qcom,csid-v3.5.1" + - "qcom,csid-v3.4.3" + - "qcom,csid-v5.0" +- reg : offset and length of the register set for the device + for the csid operating in compatible mode. +- reg-names : should specify relevant names to each reg property defined. +- interrupts : should contain the csid interrupt. +- interrupt-names : should specify relevant names to each interrupts + property defined. +- qcom,csi-vdd-voltage : should specify voltage level + for mipi csi in uV. +- qcom,mipi-csi-vdd-supply : should contain regulator to be used for + this csid core +- clock-names: name of the clocks required for the device +- qcom,clock-rates: clock rate in Hz + - 0 if appropriate clock is required but doesn't have to apply the rate + +Optional properties: +- qcom,cam-vreg-name : name of the voltage regulators required for the device. +- gdscr-supply : should contain regulator used for csid clocks. +- mmagic-supply : should contain mmagic regulator used for mmagic clocks. + +Example: + + qcom,csid@fda08000 { + cell-index = <0>; + compatible = "qcom,csid-v2.0", "qcom,csid"; + reg = <0xfda08000 0x200>; + reg-names = "csid"; + interrupts = <0 51 0>; + interrupt-names = "csiphy"; + qcom,csi-vdd-voltage = <1800000>; + qcom,mipi-csi-vdd-supply = <&pm8941_l12>; + clock-names = "camss_top_ahb_clk", "ispif_ahb_clk", + "csi_ahb_clk", "csi_src_clk", "csi_clk", + "csi_phy_clk", "csi_pix_clk", "csi_rdi_clk"; + qcom,clock-rates = <0 0 0 200000000 0 0 0 0>; + }; diff --git a/Documentation/devicetree/bindings/media/video/msm-eeprom.txt b/Documentation/devicetree/bindings/media/video/msm-eeprom.txt new file mode 100644 index 000000000000..d5bfba5672fa --- /dev/null +++ b/Documentation/devicetree/bindings/media/video/msm-eeprom.txt @@ -0,0 +1,199 @@ +* Qualcomm Technologies, Inc. MSM EEPROM + +EEPROM is a one time programmed(OTP) device that stores the calibration data +use for camera sensor. It may either be integrated in the sensor module or in +the sensor itself. As a result, the power, clock and GPIOs may be the same as +the camera sensor. The following describes the page block map, power supply, +clock, GPIO and power on sequence properties of the EEPROM device. + +Required properties if probe happens from camera daemon: +- cell-index: eeprom hardware core index +- compatible : + - "qcom,eeprom" +- reg : offset of eeprom device registers. +- qcom,cci-master : should specify the cci core index that eeprom use. +- cam_vio-supply : should contain regulator to be used for the IO vdd. +- qcom,cam-vreg-name : should specify the regulator name to be used for + this eeprom. +- qcom,cam-vreg-type : should specify the regulator type to be used for + this eeprom. +- qcom,cam-vreg-min-voltage : should specify minimum voltage level + for eeprom in uV. +- qcom,cam-vreg-max-voltage : should specify maximum voltage level + for eeprom in uV. +- qcom,cam-vreg-op-mode : should specify current level for eeprom in uA. +- qcom,gpio-no-mux : should specify the gpio mux type. +- gpios : should specify the gpios to be used for the eeprom. +- qcom,gpio-reset : should specify the reset gpio index. +- qcom,gpio-standby : should specify the standby gpio index. +- qcom,gpio-req-tbl-num : should specify the gpio table index. +- qcom,gpio-req-tbl-flags : should specify the gpio functions. +- qcom,gpio-req-tbl-label : should specify the gpio labels. +- qcom,cam-power-seq-type : should specify the power on sequence types. +- qcom,cam-power-seq-val : should specify the power on sequence values. +- qcom,cam-power-seq-cfg-val : should specify the power on sequence config + values. +- qcom,cam-power-seq-delay : should specify the power on sequence delay + time in ms. + +Optional properties: +- cam_vdig-supply : should contain regulator to be used for the digital vdd. + + + +Example: + + eeprom0: qcom,eeprom@60 { + cell-index = <0>; + reg = <0x60 0x0>; + compatible = "qcom,eeprom"; + qcom,cci-master = <0>; + cam_vdig-supply = <&pm8226_l5>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio"; + qcom,cam-vreg-type = <0 1>; + qcom,cam-vreg-min-voltage = <1200000 0>; + qcom,cam-vreg-max-voltage = <1200000 0>; + qcom,cam-vreg-op-mode = <200000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,cam-power-seq-type = "sensor_vreg", + "sensor_vreg", "sensor_clk", + "sensor_gpio", "sensor_gpio"; + qcom,cam-power-seq-val = "cam_vdig", + "cam_vio", "sensor_cam_mclk", + "sensor_gpio_reset", + "sensor_gpio_standby"; + qcom,cam-power-seq-cfg-val = <1 1 24000000 1 1>; + qcom,cam-power-seq-delay = <1 1 5 5 10>; + }; + + + +Required properties if eeprom probe is kernel probe: +- cell-index: eeprom hardware core index +- compatible : + - "qcom,eeprom" +- reg : offset of eeprom device registers. +- qcom,eeprom-name : should specify relevant names of the eeprom module + library. +- qcom,slave-addr : should specify the slave address of the eeprom. +- qcom,cci-master : should specify the cci core index that eeprom use. +- qcom,num-blocks : should specify the total block number that eeprom contains, + every block should contains page poll and mem. +- qcom,page%d : number %d page size, start address, address type, data, + data type, delay in ms. size 0 stand for non-paged. + - address type : 1 byte, 2 word. + - data type : 1 byte, 2 word. +- qcom,poll%d : number %d poll size, poll reg address, address type, data, + data type, delay in ms. size 0 stand for not used. + - address type : 1 byte, 2 word. + - data type : 1 byte, 2 word. +- qcom,mem%d : number %d memory size, start address, address type, data, + data type, delay in ms. size 0 stand for not used. + - address type : 1 byte, 2 word. + - data type : 1 byte, 2 word. +- cam_vio-supply : should contain regulator to be used for the IO vdd. +- qcom,cam-vreg-name : should specify the regulator name to be used for + this eeprom. +- qcom,cam-vreg-type : should specify the regulator type to be used for + this eeprom. +- qcom,cam-vreg-min-voltage : should specify minimum voltage level + for eeprom in uV. +- qcom,cam-vreg-max-voltage : should specify maximum voltage level + for eeprom in uV. +- qcom,cam-vreg-op-mode : should specify current level for eeprom in uA. +- pinctrl-names : should specify the pin control groups followed by + the definition of each group +- qcom,gpio-no-mux : should specify the gpio mux type. +- gpios : should specify the gpios to be used for the eeprom. +- qcom,gpio-reset : should specify the reset gpio index. +- qcom,gpio-standby : should specify the standby gpio index. +- qcom,gpio-req-tbl-num : should specify the gpio table index. +- qcom,gpio-req-tbl-flags : should specify the gpio functions. +- qcom,gpio-req-tbl-label : should specify the gpio labels. +- qcom,cam-power-seq-type : should specify the power on sequence types. +- qcom,cam-power-seq-val : should specify the power on sequence values. +- qcom,cam-power-seq-cfg-val : should specify the power on sequence config + values. +- qcom,cam-power-seq-delay : should specify the power on sequence delay + time in ms. + +Optional properties: +- qcom,pageen%d : number %d page enable reg size, start address, address type, + data, data type, delay in ms. size 0 stand for not used. +- cam_vdig-supply : should contain regulator to be used for the digital vdd. +- qcom,saddr%d : property should specify the slave address for block (%d). +- qcom,i2c-freq-mode : property should specify the I2C speed mode. + +Optional properties -EEPROM Camera Multimodule +- qcom,cmm-data-support - Camera MultiModule data capability flag. +- qcom,cmm-data-compressed - Camera MultiModule data compression flag. +- qcom,cmm-data-offset - Camera MultiModule data start offset. +- qcom,cmm-data-size - Camera MultiModule data size. + + + +Example: + + eeprom0: qcom,eeprom@60 { + cell-index = <0>; + reg = <0x60 0x0>; + qcom,eeprom-name = "msm_eeprom"; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0x60>; + qcom,cci-master = <0>; + qcom,num-blocks = <2>; + qcom,page0 = <1 0x0100 2 0x01 1 1>; + qcom,poll0 = <0 0x0 2 0 1 1>; + qcom,mem0 = <0 0x0 2 0 1 0>; + qcom,page1 = <1 0x0200 2 0x8 1 1>; + qcom,pageen1 = <1 0x0202 2 0x01 1 10>; + qcom,poll1 = <0 0x0 2 0 1 1>; + qcom,mem1 = <32 0x3000 2 0 1 0>; + qcom,saddr1 = <0x62>; + + qcom,cmm-data-support; + qcom,cmm-data-compressed; + qcom,cmm-data-offset = <0>; + qcom,cmm-data-size = <0>; + + cam_vdig-supply = <&pm8226_l5>; + cam_vio-supply = <&pm8226_lvs1>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio"; + qcom,cam-vreg-type = <0 1>; + qcom,cam-vreg-min-voltage = <1200000 0>; + qcom,cam-vreg-max-voltage = <1200000 0>; + qcom,cam-vreg-op-mode = <200000 0>; + qcom,gpio-no-mux = <0>; + gpios = <&msmgpio 26 0>, + <&msmgpio 37 0>, + <&msmgpio 36 0>; + qcom,gpio-reset = <1>; + qcom,gpio-standby = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET1", + "CAM_STANDBY"; + qcom,cam-power-seq-type = "sensor_vreg", + "sensor_vreg", "sensor_clk", + "sensor_gpio", "sensor_gpio"; + qcom,cam-power-seq-val = "cam_vdig", + "cam_vio", "sensor_cam_mclk", + "sensor_gpio_reset", + "sensor_gpio_standby"; + qcom,cam-power-seq-cfg-val = <1 1 24000000 1 1>; + qcom,cam-power-seq-delay = <1 1 5 5 10>; + }; + + diff --git a/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..9bea872b05e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>; + qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>; + qcom,switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator0>; + qcom,eeprom-src = <&eeprom0>; + qcom,led-flash-src = <&led_flash0>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 35 0>, + <&tlmm 45 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-camera.dtsi b/arch/arm64/boot/dts/qcom/trinket-camera.dtsi new file mode 100644 index 000000000000..59156b2b61c0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-camera.dtsi @@ -0,0 +1,768 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@5c00000 { + compatible = "qcom,msm-cam"; + reg = <0x5c00000 0x4000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 150000000 320000000 320000000>; + qcom,gpu-limit = <700000000>; + }; + + qcom,csiphy@1628000 { + cell-index = <0>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x1628000 0x1000>, + <0x5C00120 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 72 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID0_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY0_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 268800000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csiphy@1629000 { + cell-index = <1>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x1629000 0x1000>, + <0x5c00124 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 73 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID1_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY1_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 268800000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csiphy@162a000 { + cell-index = <2>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x162a000 0x1000>, + <0x5c00128 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 74 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID2_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY2_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 268800000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csid@5c30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30000 0x400>; + reg-names = "csid"; + interrupts = <0 208 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <925000 0>; + qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID0_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30400 0x400>; + reg-names = "csid"; + interrupts = <0 209 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <925000 0>; + qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID1_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30800 0x400>; + reg-names = "csid"; + interrupts = <0 210 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <925000 0>; + qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID2_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30c00 0x400>; + reg-names = "csid"; + interrupts = <0 211 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <925000 0>; + qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI3_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI3RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI3PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID3_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x420 0x0000>, + <&apps_smmu 0x421 0x0002>, + <&apps_smmu 0x423 0x0002>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x0000>; + label = "cpp"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x0001>; + label = "jpeg_enc0"; + }; + + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x821 0x0001>; + label = "jpeg_dma"; + }; + }; + + qcom,cpp@5c04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0x5c04000 0x100>, + <0x5c80000 0x3000>, + <0x5c18000 0x3000>, + <0x014560bc 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 206 0>; + interrupt-names = "cpp"; + camss-vdd-supply = <&camss_top_gdsc>; + vdd-supply = <&camss_cpp_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks =<&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CPP_CLK>, + <&clock_gcc GCC_CAMSS_CPP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_AXI_CLK>, + <&clock_gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_VBIF_AHB_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 256000000 256000000 0 0 0 0>; + qcom,min-clock-rate = <256000000>; + qcom,bus-master = <1>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + /*qcom,cpp-cx-ipeak = <&cx_ipeak_lm 7>;*/ + resets = <&clock_gcc GCC_CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <120000000 256000000 384000000 + 480000000 533000000 576000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@5c31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0x5c31000 0xc00>, + <0x5c00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 212 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&camss_top_gdsc>; + vfe0-vdd-supply = <&camss_vfe0_gdsc>; + vfe1-vdd-supply = <&camss_vfe1_gdsc>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI3_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI1RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI2RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI3RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI3PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE1_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "vfe0_clk_src", + "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", + "vfe1_clk_src", + "camss_vfe_vfe1_clk", + "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@5c10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0x5c10000 0x4000>, + <0x5c40000 0x3000>, + <0x5C00000 0x40000>; + reg-names = "vfe", "vfe_vbif", "msm-cam"; + interrupts = <0 214 0>, + <0 258 0>; + interrupt-names = "vfe", "dual-vfe-irq"; + vdd-supply = <&camss_vfe0_gdsc>; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "vdd", "camss-vdd"; + clocks = <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_STREAM_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE0_CLK>; + clock-names = "mmss_throttle_camss_axi_clk", "camss_ahb_clk", + "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 403200000 0 0 0 0 0 0 + 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 576000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + /* qcom,vfe-cx-ipeak = <&cx_ipeak_lm 7>;*/ + }; + + vfe1: qcom,vfe1@5c14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0x5c14000 0x4000>, + <0x5c40000 0x3000>, + <0x5C00000 0x40000>; + reg-names = "vfe", "vfe_vbif", "dual-vfe-irq"; + interrupts = <0 215 0>, + <0 258 0>; + interrupt-names = "vfe", "dual-vfe-irq"; + vdd-supply = <&camss_vfe1_gdsc>; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "vdd", "camss-vdd"; + clocks = <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE1_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_STREAM_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "mmss_throttle_camss_axi_clk", "camss_ahb_clk", + "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 403200000 0 0 0 0 0 0 + 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 576000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + /* qcom,vfe-cx-ipeak = <&cx_ipeak_lm 7>;*/ + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@5c0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0x5c0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 207 0>; + interrupt-names = "cci"; + status = "ok"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CCI_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CCI_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CCI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 19200000 0 0>, + <0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 37 0>, + <&tlmm 38 0>, + <&tlmm 39 0>, + <&tlmm 40 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@5c1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0x05c1c000 0x4000>, + <0x5c60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 216 0>; + interrupt-names = "jpeg"; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "camss-vdd"; + clock-names = "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,vbif-qos-setting = <0x550 0x1111>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1200000 1200000>; + status = "ok"; + }; + + qcom,jpeg@5ca0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0x5ca0000 0x4000>, + <0x5c60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 217 0>; + interrupt-names = "jpeg"; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "camss-vdd"; + clock-names = "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,vbif-qos-setting = <0x550 0x1111>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1200000 1200000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts index fcde40c18b76..fe4e03b4dd51 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts @@ -14,6 +14,7 @@ /plugin/; #include +#include #include "trinket-idp.dtsi" #include "trinket-audio-overlay.dtsi" diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index bad09668f380..b037c8ef488e 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -14,6 +14,8 @@ #include #include "trinket-thermal-overlay.dtsi" #include "trinket-sde-display.dtsi" +#include +#include "trinket-camera-sensor-idp.dtsi" &qupv3_se1_i2c { status = "ok"; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 693a63a7a497..a694c85691d1 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -1421,6 +1421,232 @@ }; }; }; + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio37", "gpio38"; + function = "cci_i2c"; + }; + + config { + pins = "gpio37", "gpio38"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio37", "gpio38"; + function = "cci_i2c"; + }; + + config { + pins = "gpio37", "gpio38"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio35"; + function = "cam_mclk"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio35"; + function = "cam_mclk"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio36"; + function = "cam_mclk"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio36"; + function = "cam_mclk"; + }; + + config { + pins = "gpio36"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 8fd8175ce749..19d4b20e2e59 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2374,6 +2374,7 @@ #include "trinket-regulator.dtsi" #include "trinket-gdsc.dtsi" #include "trinket-usb.dtsi" +#include "trinket-camera.dtsi" #include "msm-arm-smmu-trinket.dtsi" #include "trinket-qupv3.dtsi" #include "trinket-coresight.dtsi" -- GitLab From 0cf3b54de30b3902a2a9bd279db4f05487a6d3c5 Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Sun, 20 Jan 2019 16:50:37 +0530 Subject: [PATCH 1013/1286] ARM: dts: msm: Update swrm base address for wsa master Update swrm io base address for wsa macro soundwire master. Change-Id: I488006a8e1af3de726fc675db6233f2bd3cba64d Signed-off-by: Aditya Bavanari --- arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi index 8dce48a95559..9dd9b78f0d0d 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -97,7 +97,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,swr_master_id = <1>; - swrm-io-base = <0xa4900000 0x0>; + swrm-io-base = <0x0a490000 0x0>; interrupts = <0 79 0>; interrupt-names = "swr_master_irq"; qcom,swr-num-ports = <8>; -- GitLab From 9eb7d36fe64a340c729785ec5a2e2f23c803f7f9 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Sat, 19 Jan 2019 16:54:04 +0530 Subject: [PATCH 1014/1286] ARM: dts: msm: Update the resource-id for CX/MX/LDO9 for trinket RPM expects the CX/MX rails resource-ids as '0' instead of '3' and '9' for LDO9. Fix it. Change-Id: Iac88fbc737a2e2deb0f6c67f7314d882a1de96ff Signed-off-by: Kiran Gunda --- arch/arm64/boot/dts/qcom/pm6125-rpm-regulator.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125-rpm-regulator.dtsi b/arch/arm64/boot/dts/qcom/pm6125-rpm-regulator.dtsi index b83c16dea76a..1a248dd55aff 100644 --- a/arch/arm64/boot/dts/qcom/pm6125-rpm-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125-rpm-regulator.dtsi @@ -32,7 +32,7 @@ rpm-regulator-smpa3 { compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "rwcx"; - qcom,resource-id = <3>; + qcom,resource-id = <0>; qcom,regulator-type = <1>; qcom,hpm-min-load = <100000>; status = "disabled"; @@ -49,7 +49,7 @@ rpm-regulator-smpa5 { compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "rwmx"; - qcom,resource-id = <5>; + qcom,resource-id = <0>; qcom,regulator-type = <1>; qcom,hpm-min-load = <100000>; status = "disabled"; @@ -225,8 +225,8 @@ rpm-regulator-ldoa9 { compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "rwlm"; - qcom,resource-id = <0>; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; qcom,regulator-type = <0>; qcom,hpm-min-load = <10000>; status = "disabled"; -- GitLab From dbd5b63ab636c589e0a39dea203ebe6805920645 Mon Sep 17 00:00:00 2001 From: Preeti Nagar Date: Fri, 18 Jan 2019 16:01:29 +0530 Subject: [PATCH 1015/1286] Adding KBUILD_AFLAGS for RTIC DTS For DTS content compilation in RTIC, adding KBUILD_AFLAGS variable for passing target related flag info. Change-Id: Ie94ca9fa6428fc39532511978ea0c98fa38343b0 Signed-off-by: Preeti Nagar --- arch/arm64/boot/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile index 96df135300fe..abc6b0524b89 100644 --- a/arch/arm64/boot/Makefile +++ b/arch/arm64/boot/Makefile @@ -36,7 +36,7 @@ endif rtic_mp.dtb: vmlinux FORCE $(RTIC_MPGEN) --objcopy="${OBJCOPY}" --objdump="${OBJDUMP}" \ --binpath="" --vmlinux="vmlinux" --config=${KCONFIG_CONFIG} \ - --cc="${CC}" --dts=rtic_mp.dts && \ + --cc="${CC} ${KBUILD_AFLAGS}" --dts=rtic_mp.dts && \ $(DTC) -O dtb -o rtic_mp.dtb -b 0 $(DTC_FLAGS) rtic_mp.dts $(obj)/Image: vmlinux FORCE -- GitLab From 56fbcb9b7e9c07d8b85cabf3aa7b393c74fec3ff Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Fri, 18 Jan 2019 14:25:01 +0530 Subject: [PATCH 1016/1286] phy: ufs: Update phy settings for sdmmagpie This change updates UFS PHY settings for sdmmagpie as per latest PHY recommendations for 10nm. Change-Id: Iefd906d00494a43b92be4a5ceae13a655eb56122 Signed-off-by: Sayali Lokhande --- drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h index 38bd30be340f..0d0778e4fc7f 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -58,7 +58,9 @@ #define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08) #define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C) #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x2C) +#define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x30) #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x34) +#define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x38) #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x130) #define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134) #define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x138) @@ -257,7 +259,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), @@ -265,17 +267,19 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x07), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00, 0x59), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6E), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0x9A), /* 8 us */ }; @@ -286,7 +290,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_INTERFACE_MODE, 0x40), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x5B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04), @@ -294,7 +298,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER, 0x04), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x81), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), -- GitLab From 58a75d5339b4e9b3e3f3c29d635921be6e8376cc Mon Sep 17 00:00:00 2001 From: Srikanth Uyyala Date: Mon, 24 Dec 2018 16:04:27 +0530 Subject: [PATCH 1017/1286] msm-camera: add support for cx_ipeak camera drivers need to vote when moving to turbo clock and unvote when moving out of turbo. cx_ipeak driver then makes sure to limit the current drawn from cx based on this vote. This dirver provides common utility functions to track vote and unvote. Change-Id: I34d860003518924ab3233d8de24ccdb11f513f7e Signed-off-by: Srikanth Uyyala --- .../platform/msm/camera_v2/common/Makefile | 2 +- .../msm/camera_v2/common/msm_cam_cx_ipeak.c | 89 +++++++++++++++++++ .../msm/camera_v2/common/msm_cam_cx_ipeak.h | 24 +++++ 3 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.c create mode 100644 drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.h diff --git a/drivers/media/platform/msm/camera_v2/common/Makefile b/drivers/media/platform/msm/camera_v2/common/Makefile index 74fe58f430e0..e3765fc4c524 100644 --- a/drivers/media/platform/msm/camera_v2/common/Makefile +++ b/drivers/media/platform/msm/camera_v2/common/Makefile @@ -1,3 +1,3 @@ ccflags-y += -Idrivers/media/platform/msm/camera_v2/ ccflags-y += -Idrivers/misc/ -obj-$(CONFIG_MSMB_CAMERA) += msm_camera_io_util.o cam_smmu_api.o cam_hw_ops.o cam_soc_api.o msm_camera_tz_util.o +obj-$(CONFIG_MSMB_CAMERA) += msm_camera_io_util.o cam_smmu_api.o cam_hw_ops.o cam_soc_api.o msm_camera_tz_util.o msm_cam_cx_ipeak.o diff --git a/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.c b/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.c new file mode 100644 index 000000000000..d9cea15eb666 --- /dev/null +++ b/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.c @@ -0,0 +1,89 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "msm_cam_cx_ipeak.h" + +static struct cx_ipeak_client *cam_cx_ipeak; +static int cx_default_ipeak_mask; +static int cx_current_ipeak_mask; +static int cam_cx_client_cnt; + +int cam_cx_ipeak_register_cx_ipeak(struct cx_ipeak_client *p_cam_cx_ipeak, + int *cam_cx_ipeak_bit) +{ + int rc = 0; + + *cam_cx_ipeak_bit = 1 << cam_cx_client_cnt++; + cx_default_ipeak_mask |= *cam_cx_ipeak_bit; + + if (cam_cx_ipeak) + goto exit; + + cam_cx_ipeak = p_cam_cx_ipeak; + + if (!cam_cx_ipeak) + rc = -EINVAL; + +exit: + pr_debug("%s: client_cnt %d client mask = %x default_mask = %x\n", + __func__, cam_cx_client_cnt, *cam_cx_ipeak_bit, + cx_default_ipeak_mask); + return rc; +} + +int cam_cx_ipeak_update_vote_cx_ipeak(int cam_cx_ipeak_bit) +{ + int32_t soc_cx_ipeak_bit = cam_cx_ipeak_bit; + int ret = 0; + + pr_debug("%s: E: current_mask = %x default_mask = %x new bit = %x\n", + __func__, cx_current_ipeak_mask, + cx_default_ipeak_mask, soc_cx_ipeak_bit); + + cx_current_ipeak_mask |= soc_cx_ipeak_bit; + pr_debug("%s: current_mask = %x\n", __func__, cx_current_ipeak_mask); + + if (cx_current_ipeak_mask == cx_default_ipeak_mask) { + if (cam_cx_ipeak) { + ret = cx_ipeak_update(cam_cx_ipeak, true); + if (ret) + goto exit; + pr_debug("%s: X: All client VOTE\n", __func__); + } + } +exit: + return ret; +} + +int cam_cx_ipeak_unvote_cx_ipeak(int cam_cx_ipeak_bit) +{ + int32_t soc_cx_ipeak_bit = cam_cx_ipeak_bit; + + pr_debug("%s: current_mask = %x soc_cx_ipeak_bit = %x\n", __func__, + cx_current_ipeak_mask, soc_cx_ipeak_bit); + if (cx_current_ipeak_mask == cx_default_ipeak_mask) { + if (cam_cx_ipeak) + cx_ipeak_update(cam_cx_ipeak, false); + pr_debug("%s: One client requested UNVOTE\n", __func__); + } + cx_current_ipeak_mask &= (~soc_cx_ipeak_bit); + pr_debug("%s:X:updated cx_current_ipeak_mask = %x\n", __func__, + cx_current_ipeak_mask); + + return 0; +} diff --git a/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.h b/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.h new file mode 100644 index 000000000000..b60b896eb060 --- /dev/null +++ b/drivers/media/platform/msm/camera_v2/common/msm_cam_cx_ipeak.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MSM_CAM_CX_IPEAK_H_ +#define _MSM_CAM_CX_IPEAK_H_ + +#include + +int cam_cx_ipeak_register_cx_ipeak(struct cx_ipeak_client *p_cam_cx_ipeak, + int *cam_cx_ipeak_bit); + +int cam_cx_ipeak_update_vote_cx_ipeak(int cam_cx_ipeak_bit); +int cam_cx_ipeak_unvote_cx_ipeak(int cam_cx_ipeak_bit); + +#endif /* _CAM_CX_IPEAK_H_ */ -- GitLab From d6458232962764fe4bece1f2258ffebe83937f47 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 17 Jan 2019 18:17:37 +0530 Subject: [PATCH 1018/1286] soc: qcom: socinfo: Add soc information for SA4155P Add socinfo support for SA4155P SoC and update the bindings for the same. Change-Id: Id27dbd6e32d0bd203276e9a7b2dfb9384609ff7c Signed-off-by: Venkata Rao Kakani --- drivers/soc/qcom/socinfo.c | 9 ++++++++- include/soc/qcom/socinfo.h | 6 +++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index a607852a2f6e..e4b1702b049c 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -363,6 +363,9 @@ static struct msm_soc_info cpu_of_id[] = { /* sa6155P ID */ [377] = {MSM_CPU_SA6155P, "SA6155P"}, + /* sa4155P ID */ + [380] = {MSM_CPU_SA4155P, "SA4155P"}, + /* sa6155 ID */ [384] = {MSM_CPU_SA6155, "SA6155"}, @@ -1277,6 +1280,10 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 377; strlcpy(dummy_socinfo.build_id, "sa6155p - ", sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_sa4155p()) { + dummy_socinfo.id = 380; + strlcpy(dummy_socinfo.build_id, "sa4155p - ", + sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_sa6155()) { dummy_socinfo.id = 384; strlcpy(dummy_socinfo.build_id, "sa6155 - ", diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index be1c2f990a0f..e26f8f874035 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -81,6 +81,8 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdmmagpie") #define early_machine_is_sa6155p() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sa6155p") +#define early_machine_is_sa4155p() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sa4155p") #define early_machine_is_sa6155() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sa6155") #define early_machine_is_trinket() \ @@ -115,6 +117,7 @@ #define early_machine_is_sdxprairie() 0 #define early_machine_is_sdmmagpie() 0 #define early_machine_is_sa6155p() 0 +#define early_machine_is_sa4155p() 0 #define early_machine_is_sa6155() 0 #define early_machine_is_trinket() 0 #endif @@ -149,6 +152,7 @@ enum msm_cpu { SDX_CPU_SDXPRAIRIE, MSM_CPU_SDMMAGPIE, MSM_CPU_SA6155P, + MSM_CPU_SA4155P, MSM_CPU_SA6155, MSM_CPU_TRINKET, }; -- GitLab From d5dc9b889bae7e425c968c37ac347b9e02dfbcbd Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Wed, 16 Jan 2019 18:52:30 -0800 Subject: [PATCH 1019/1286] msm: IPA: debug QMI encode issue This debug code is to help check if we have issue on QMI encode. Change-Id: I76faa953a15b56fd6b911032ac6244d35e737c07 Signed-off-by: Bojun Pan --- .../platform/msm/ipa/ipa_v3/ipa_qmi_service.c | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c index 7538527ad1c9..35a7d876e8d5 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -77,6 +77,8 @@ static void ipa3_handle_indication_req(struct qmi_handle *qmi_handle, memset(&resp, 0, sizeof(struct ipa_indication_reg_resp_msg_v01)); resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_INDICATION_REGISTER_RESP_V01, QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01, @@ -162,6 +164,8 @@ static void ipa3_handle_install_filter_rule_req(struct qmi_handle *qmi_handle, rule_req->filter_spec_ex_list[i].rule_id; } + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_INSTALL_FILTER_RULE_RESP_V01, QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01, @@ -187,6 +191,8 @@ static void ipa3_handle_filter_installed_notify_req( IPAWANDBG("Received filter_install_notify Request\n"); resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01, QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01, @@ -216,6 +222,9 @@ static void handle_ipa_config_req(struct qmi_handle *qmi_handle, IPAERR("ipa3_mhi_handle_ipa_config_req failed %d\n", rc); resp.resp.result = IPA_QMI_RESULT_FAILURE_V01; } + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_CONFIG_RESP_V01, QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01, @@ -251,6 +260,8 @@ static void ipa3_handle_modem_init_cmplt_req(struct qmi_handle *qmi_handle, memset(&resp, 0, sizeof(resp)); resp.resp.result = IPA_QMI_RESULT_SUCCESS_V01; + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp.resp.result, resp.resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01, QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01, @@ -270,14 +281,21 @@ static void ipa3_handle_mhi_alloc_channel_req(struct qmi_handle *qmi_handle, const void *decoded_msg) { struct ipa_mhi_alloc_channel_req_msg_v01 *ch_alloc_req; - struct ipa_mhi_alloc_channel_resp_msg_v01 *resp; + struct ipa_mhi_alloc_channel_resp_msg_v01 *resp = NULL; int rc; IPAWANDBG("Received QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01\n"); ch_alloc_req = (struct ipa_mhi_alloc_channel_req_msg_v01 *)decoded_msg; resp = imp_handle_allocate_channel_req(ch_alloc_req); + if (!resp) { + IPAWANERR("imp handle allocate channel req fails"); + return; + } + IPAWANDBG("qmi_snd_rsp: result %d, err %d, arr_vald: %d, arr_len %d\n", + resp->resp.result, resp->resp.error, resp->alloc_resp_arr_valid, + resp->alloc_resp_arr_len); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01, IPA_MHI_ALLOC_CHANNEL_RESP_MSG_V01_MAX_MSG_LEN, @@ -296,14 +314,21 @@ static void ipa3_handle_mhi_vote_req(struct qmi_handle *qmi_handle, const void *decoded_msg) { struct ipa_mhi_clk_vote_req_msg_v01 *vote_req; - struct ipa_mhi_clk_vote_resp_msg_v01 *resp; + struct ipa_mhi_clk_vote_resp_msg_v01 *resp = NULL; int rc; vote_req = (struct ipa_mhi_clk_vote_req_msg_v01 *)decoded_msg; IPAWANDBG("Received QMI_IPA_MHI_CLK_VOTE_REQ_V01(%d)\n", vote_req->mhi_vote); resp = imp_handle_vote_req(vote_req->mhi_vote); + if (!resp) { + IPAWANERR("imp handle allocate channel req fails"); + return; + } IPAWANDBG("start sending QMI_IPA_MHI_CLK_VOTE_RESP_V01\n"); + + IPAWANDBG("qmi_snd_rsp: result %d, err %d\n", + resp->resp.result, resp->resp.error); rc = qmi_send_response(qmi_handle, sq, txn, QMI_IPA_MHI_CLK_VOTE_RESP_V01, IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN, -- GitLab From 9fc310f45e8af52453d3a9ba4325a54879257cb1 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 18 Jan 2019 11:58:26 +0530 Subject: [PATCH 1020/1286] ARM: dts: msm: Update QUSB PHY BIAS_CTRL2 parameter on sdmmagpie Currently QUSB phy PLL_BIAS_CONTROL_2 register value is overriding in driver to 0x28. For better USB compliance results update QUSB PHY BIAS_2 value to 0x22 as per HPG for both device and host modes. Change-Id: I85d6350ae68877ab347ba0acda287ba33805422f Signed-off-by: Chandana Kishori Chiluveru --- arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi index 29a88ecc7b81..367be23a8c81 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -143,7 +143,6 @@ vdd-supply = <&pm6150_l4>; vdda18-supply = <&pm6150_l11>; vdda33-supply = <&pm6150_l17>; - qcom,override-bias-ctrl2; qcom,vdd-voltage-level = <0 880000 880000>; qcom,qusb-phy-reg-offset = <0x240 /* QUSB2PHY_PORT_TUNE1 */ @@ -166,7 +165,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ @@ -187,7 +186,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ -- GitLab From 100bf42258859bcc51778515ef0bb7881881f379 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Mon, 21 Jan 2019 19:36:29 +0530 Subject: [PATCH 1021/1286] ARM: dts: msm: remove regulator voting for ANoC TBU on trinket Remove the regulator voting for ANoC TBU as it is not power collapsible. Moreover the GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS is not defined on trinket. Change-Id: Ief10a9d94b5be9a74ce2646bc4210413698f04f2 Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index b4c49dc1146c..5dfdfb6eeecd 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -150,8 +150,6 @@ <0xc782200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - qcom,regulator-names = "vdd"; - vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; -- GitLab From debafb6e09a49b8ec60c43eb01fb368dfeed6860 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 21 Jan 2019 13:28:11 -0800 Subject: [PATCH 1022/1286] ARM: dts: rearrange PCIe interrupts for sm8150 Move global_int to the beginning of PCIe interrupt-map because PCI framework expects PCIe legacy interrupts to start at index 1. Update PCIe interrupt-map for sm8150 based on this requirement. Change-Id: I3148aaca15e127d2e191b11da7d4bbb4dfedce76 Signed-off-by: Tony Truong --- arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index e1753d4cf23d..d99c48c6adb6 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -36,15 +36,15 @@ <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; interrupt-parent = <&pcie0>; interrupts = <0 1 2 3 4>; - interrupt-names = "int_a", "int_b", "int_c", "int_d", - "int_global_int"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 149 0 - 0 0 0 1 &intc 0 150 0 - 0 0 0 2 &intc 0 151 0 - 0 0 0 3 &intc 0 152 0 - 0 0 0 4 &intc 0 140 0>; + interrupt-map = < 0 0 0 0 &intc 0 140 0 + 0 0 0 1 &intc 0 149 0 + 0 0 0 2 &intc 0 150 0 + 0 0 0 3 &intc 0 151 0 + 0 0 0 4 &intc 0 152 0>; qcom,phy-sequence = <0x0840 0x03 0x0 0x0094 0x08 0x0 @@ -303,15 +303,15 @@ <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; interrupt-parent = <&pcie1>; interrupts = <0 1 2 3 4>; - interrupt-names = "int_a", "int_b", "int_c", "int_d", - "int_global_int"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 434 0 - 0 0 0 1 &intc 0 435 0 - 0 0 0 2 &intc 0 438 0 - 0 0 0 3 &intc 0 439 0 - 0 0 0 4 &intc 0 306 0>; + interrupt-map = <0 0 0 0 &intc 0 306 0 + 0 0 0 1 &intc 0 434 0 + 0 0 0 2 &intc 0 435 0 + 0 0 0 3 &intc 0 438 0 + 0 0 0 4 &intc 0 439 0>; qcom,phy-sequence = <0x0a40 0x03 0x0 0x0010 0x00 0x0 -- GitLab From f710e2e4ee802e786c0bf02b12316fc222c44069 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 15 Jan 2019 17:34:28 -0700 Subject: [PATCH 1023/1286] ARM: dts: msm: Remove QFE sensor for modem1 in sdx50 QFE sensor is not supported for modem1 in sdx50. Remove the thermal zone mapping to this sensor. Change-Id: I6c8b701d04204f4f2d2c258d3ff3443795910853 Signed-off-by: Ram Chandrasekar --- arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi index 39895bfee544..e791d1d32ff2 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -409,20 +409,6 @@ }; }; - modem1-qfe-pa-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 102>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - modem1-qfe-wtr-usr { polling-delay-passive = <0>; polling-delay = <0>; -- GitLab From 9109f814ffd0f5eb38009b4021f3b6a1a3c00d1d Mon Sep 17 00:00:00 2001 From: Karthikeyan Mani Date: Wed, 16 Jan 2019 12:07:07 -0800 Subject: [PATCH 1024/1286] drivers: soc: qcom: notify drivers registering first time Send usbc mode at register function so that all drivers registering first time will get the notification of current usb connection type, if any. Change-Id: Ifac7af1ff546a17bc6f382246ae0aeec5194ca9f Signed-off-by: Karthikeyan Mani --- drivers/soc/qcom/fsa4480-i2c.c | 86 ++++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 34 deletions(-) diff --git a/drivers/soc/qcom/fsa4480-i2c.c b/drivers/soc/qcom/fsa4480-i2c.c index 38ce57378870..639dc66e3bf9 100644 --- a/drivers/soc/qcom/fsa4480-i2c.c +++ b/drivers/soc/qcom/fsa4480-i2c.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,6 +15,7 @@ #include #include #include +#include #include #define FSA4480_I2C_NAME "fsa4480-driver" @@ -41,6 +42,7 @@ struct fsa4480_priv { atomic_t usbc_mode; struct work_struct usbc_analog_work; struct blocking_notifier_head fsa4480_notifier; + struct mutex notification_lock; }; struct fsa4480_reg_val { @@ -132,6 +134,51 @@ static int fsa4480_usbc_event_changed(struct notifier_block *nb, return ret; } +static int fsa4480_usbc_analog_setup_switches(struct fsa4480_priv *fsa_priv) +{ + int rc = 0; + union power_supply_propval mode; + struct device *dev; + + if (!fsa_priv) + return -EINVAL; + dev = fsa_priv->dev; + if (!dev) + return -EINVAL; + + mutex_lock(&fsa_priv->notification_lock); + /* get latest mode again within locked context */ + rc = power_supply_get_property(fsa_priv->usb_psy, + POWER_SUPPLY_PROP_TYPEC_MODE, &mode); + if (rc) { + dev_err(dev, "%s: Unable to read USB TYPEC_MODE: %d\n", + __func__, rc); + goto done; + } + dev_dbg(dev, "%s: setting GPIOs active = %d\n", + __func__, mode.intval != POWER_SUPPLY_TYPEC_NONE); + + if (mode.intval != POWER_SUPPLY_TYPEC_NONE) { + /* activate switches */ + fsa4480_usbc_update_settings(fsa_priv, 0x00, 0x9F); + + /* notify call chain on event */ + blocking_notifier_call_chain(&fsa_priv->fsa4480_notifier, + POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER, NULL); + } else { + /* notify call chain on event */ + blocking_notifier_call_chain(&fsa_priv->fsa4480_notifier, + POWER_SUPPLY_TYPEC_NONE, NULL); + + /* deactivate switches */ + fsa4480_usbc_update_settings(fsa_priv, 0x18, 0x98); + } + +done: + mutex_unlock(&fsa_priv->notification_lock); + return rc; +} + /* * fsa4480_reg_notifier - register notifier block with fsa driver * @@ -165,9 +212,7 @@ int fsa4480_reg_notifier(struct notifier_block *nb, */ dev_dbg(fsa_priv->dev, "%s: verify if USB adapter is already inserted\n", __func__); - rc = fsa4480_usbc_event_changed(&fsa_priv->psy_nb, - PSY_EVENT_PROP_CHANGED, - fsa_priv->usb_psy); + rc = fsa4480_usbc_analog_setup_switches(fsa_priv); return rc; } @@ -194,7 +239,6 @@ int fsa4480_unreg_notifier(struct notifier_block *nb, if (!fsa_priv) return -EINVAL; - atomic_set(&(fsa_priv->usbc_mode), 0); fsa4480_usbc_update_settings(fsa_priv, 0x18, 0x98); return blocking_notifier_chain_unregister (&fsa_priv->fsa4480_notifier, nb); @@ -266,33 +310,6 @@ int fsa4480_switch_event(struct device_node *node, } EXPORT_SYMBOL(fsa4480_switch_event); -static int fsa4480_usbc_analog_setup_switches - (struct fsa4480_priv *fsa_priv, bool active) -{ - int rc = 0; - - dev_dbg(fsa_priv->dev, "%s: setting GPIOs active = %d\n", - __func__, active); - - if (active) { - /* activate switches */ - fsa4480_usbc_update_settings(fsa_priv, 0x00, 0x9F); - - /* notify call chain on event */ - blocking_notifier_call_chain(&fsa_priv->fsa4480_notifier, - POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER, NULL); - } else { - /* notify call chain on event */ - blocking_notifier_call_chain(&fsa_priv->fsa4480_notifier, - POWER_SUPPLY_TYPEC_NONE, NULL); - - /* deactivate switches */ - fsa4480_usbc_update_settings(fsa_priv, 0x18, 0x98); - } - - return rc; -} - static void fsa4480_usbc_analog_work_fn(struct work_struct *work) { struct fsa4480_priv *fsa_priv = @@ -302,8 +319,7 @@ static void fsa4480_usbc_analog_work_fn(struct work_struct *work) pr_err("%s: fsa container invalid\n", __func__); return; } - fsa4480_usbc_analog_setup_switches(fsa_priv, - atomic_read(&(fsa_priv->usbc_mode)) != POWER_SUPPLY_TYPEC_NONE); + fsa4480_usbc_analog_setup_switches(fsa_priv); pm_relax(fsa_priv->dev); } @@ -361,6 +377,7 @@ static int fsa4480_probe(struct i2c_client *i2c, goto err_supply; } + mutex_init(&fsa_priv->notification_lock); i2c_set_clientdata(i2c, fsa_priv); INIT_WORK(&fsa_priv->usbc_analog_work, @@ -394,6 +411,7 @@ static int fsa4480_remove(struct i2c_client *i2c) /* deregister from PMI */ power_supply_unreg_notifier(&fsa_priv->psy_nb); power_supply_put(fsa_priv->usb_psy); + mutex_destroy(&fsa_priv->notification_lock); dev_set_drvdata(&i2c->dev, NULL); return 0; -- GitLab From 3094361f3f19330a58a265224dd61c1f05affea8 Mon Sep 17 00:00:00 2001 From: jiad Date: Fri, 4 Jan 2019 13:28:47 +0800 Subject: [PATCH 1025/1286] ARM: dts: msm: Support CNSS WLAN device for sdxprairie Support CNSS WLAN device for sdxprairie. Change-Id: I1c5fbc1ea5d21f0bc06f0502b123161f5867e871 Signed-off-by: jiad --- .../boot/dts/qcom/sdxprairie-pinctrl.dtsi | 31 ++++- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 109 ++++++++++++++++++ 2 files changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index a3ec2a0e06ea..e77298218622 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1329,5 +1329,34 @@ }; }; }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index b0b69d11c6da..18cd1b08adb5 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -912,6 +912,115 @@ < 576000 MHZ_TO_MBPS(1017, 4) >, < 1497600 MHZ_TO_MBPS(1804, 4)>; }; + + qcom,cnss-qca6390@a0000000 { + compatible = "qcom,cnss-qca6390"; + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 52 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x400000>; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + + mhi_devices { + }; + }; }; #include "sdxprairie-pm.dtsi" -- GitLab From 1dc3c3b8588564e4fce5b29ea35503b2d738d1cd Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Mon, 21 Jan 2019 14:39:02 +0530 Subject: [PATCH 1026/1286] usb: qusb: Remove the PHY_HOST_MODE check from set_suspend The PHY_HOST_MODE check in the set_suspend call to distinguish between low power mode exit and bus suspend exit is redundant as the cable_connected flag distinguishes the same. Change-Id: I9a422ee5cb24553217a03bf6d1eb0750a6793836 Signed-off-by: Sriharsha Allenki --- drivers/usb/phy/phy-msm-qusb-v2.c | 8 +++----- drivers/usb/phy/phy-msm-qusb.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c index 40777edba7a3..8af48e009067 100644 --- a/drivers/usb/phy/phy-msm-qusb-v2.c +++ b/drivers/usb/phy/phy-msm-qusb-v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -580,8 +580,7 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) if (suspend) { /* Bus suspend case */ - if (qphy->cable_connected || - (qphy->phy.flags & PHY_HOST_MODE)) { + if (qphy->cable_connected) { /* Disable all interrupts */ writel_relaxed(0x00, qphy->base + qphy->phy_reg[INTR_CTRL]); @@ -632,8 +631,7 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) qphy->suspended = true; } else { /* Bus resume case */ - if (qphy->cable_connected || - (qphy->phy.flags & PHY_HOST_MODE)) { + if (qphy->cable_connected) { qusb_phy_enable_clocks(qphy, true); /* Clear all interrupts on resume */ writel_relaxed(0x00, diff --git a/drivers/usb/phy/phy-msm-qusb.c b/drivers/usb/phy/phy-msm-qusb.c index 256c0e419cff..5e733c482887 100644 --- a/drivers/usb/phy/phy-msm-qusb.c +++ b/drivers/usb/phy/phy-msm-qusb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -634,8 +634,7 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) if (suspend) { /* Bus suspend case */ - if (qphy->cable_connected || - (qphy->phy.flags & PHY_HOST_MODE)) { + if (qphy->cable_connected) { /* Clear all interrupts */ writel_relaxed(0x00, qphy->base + QUSB2PHY_PORT_INTR_CTRL); @@ -715,8 +714,7 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) qphy->suspended = true; } else { /* Bus suspend case */ - if (qphy->cable_connected || - (qphy->phy.flags & PHY_HOST_MODE)) { + if (qphy->cable_connected) { qusb_phy_enable_clocks(qphy, true); /* Clear all interrupts on resume */ writel_relaxed(0x00, -- GitLab From bf613d98555c095bbdea603778ced5734920cc1a Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 22 Jan 2019 00:18:32 +0530 Subject: [PATCH 1027/1286] ARM: dts: msm: Change eMMC lower bus speed mode for trinket Change eMMC lower bus speed mode from HS50 to DDR52. Change-Id: I1209bc863e7eb6601db68c0bba8377d03d6471ed Signed-off-by: Ram Prakash Gupta --- arch/arm64/boot/dts/qcom/trinket.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 8fd8175ce749..fb93f97abff2 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2047,6 +2047,8 @@ qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; -- GitLab From e5e33ae29a0d38a4c62da914536f4fbbfa428a48 Mon Sep 17 00:00:00 2001 From: Aggarwal Shubham Date: Tue, 22 Jan 2019 12:21:12 +0530 Subject: [PATCH 1028/1286] defconfig: qcs403: Cleanup of data configs for memory improvement This is for optimizing ram usage for qcs403. Removing unused configs based on discussion with data team. Change-Id: I0de34d6f98b895d4f858b52f56573e2ce811a14e Signed-off-by: Aggarwal Shubham --- arch/arm/configs/vendor/qcs405-perf_defconfig | 55 +++++-------------- 1 file changed, 15 insertions(+), 40 deletions(-) diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 7dd2e15d10f3..1b209ccbc9d5 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -60,8 +60,6 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y @@ -69,49 +67,32 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_IPV6_SIT is not set CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y +# CONFIG_ANDROID_PARANOID_NETWORK is not set CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y +# CONFIG_NF_CONNTRACK_PROCFS is not set CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=y +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_U32=y CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_LOG_IPV4=y CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_NAT=y @@ -125,7 +106,7 @@ CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_NF_DUP_IPV6=y +CONFIG_NF_LOG_IPV6=y CONFIG_IP6_NF_IPTABLES=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y @@ -136,14 +117,7 @@ CONFIG_BRIDGE_EBT_BROUTE=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y @@ -384,4 +358,5 @@ CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_TWOFISH=y +CONFIG_LIBCRC32C=y CONFIG_XZ_DEC=y -- GitLab From 092a3b2560093541a9bf9069d041d583d12f5317 Mon Sep 17 00:00:00 2001 From: Praneeth Paladugu Date: Mon, 29 Jan 2018 16:15:18 -0800 Subject: [PATCH 1029/1286] msm: vidc: Add support for buffer tags and sub-frame info 1) Clients send input_tag and output_tag through buffer reserved fields. Driver needs to pass them to FW and when FW returns them back, send them to client. 2) Convey sub-frame information to client from FW. Change-Id: Ia92bca933d18a7795ba17eea9178a4c5de49157b Signed-off-by: Praneeth Paladugu Signed-off-by: Umesh Pandey Signed-off-by: Praveen Chavan --- .../platform/msm/vidc/hfi_packetization.c | 7 +- .../platform/msm/vidc/hfi_response_handler.c | 27 +++- drivers/media/platform/msm/vidc/msm_vidc.c | 19 ++- .../media/platform/msm/vidc/msm_vidc_common.c | 125 +++++++++++++++++- .../media/platform/msm/vidc/msm_vidc_common.h | 7 +- .../platform/msm/vidc/msm_vidc_internal.h | 12 +- .../media/platform/msm/vidc/vidc_hfi_api.h | 11 +- .../media/platform/msm/vidc/vidc_hfi_helper.h | 10 +- include/uapi/linux/videodev2.h | 1 + 9 files changed, 203 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.c b/drivers/media/platform/msm/vidc/hfi_packetization.c index a5bbcd0102d9..6d779eb53bcb 100644 --- a/drivers/media/platform/msm/vidc/hfi_packetization.c +++ b/drivers/media/platform/msm/vidc/hfi_packetization.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -828,7 +828,7 @@ int create_pkt_cmd_session_etb_decoder( pkt->offset = input_frame->offset; pkt->alloc_len = input_frame->alloc_len; pkt->filled_len = input_frame->filled_len; - pkt->input_tag = input_frame->clnt_data; + pkt->input_tag = input_frame->input_tag; pkt->packet_buffer = (u32)input_frame->device_addr; trace_msm_v4l2_vidc_buffer_event_start("ETB", @@ -863,7 +863,7 @@ int create_pkt_cmd_session_etb_encoder( pkt->offset = input_frame->offset; pkt->alloc_len = input_frame->alloc_len; pkt->filled_len = input_frame->filled_len; - pkt->input_tag = input_frame->clnt_data; + pkt->input_tag = input_frame->input_tag; pkt->packet_buffer = (u32)input_frame->device_addr; pkt->extra_data_buffer = (u32)input_frame->extradata_addr; @@ -899,6 +899,7 @@ int create_pkt_cmd_session_ftb(struct hfi_cmd_session_fill_buffer_packet *pkt, return -EINVAL; pkt->packet_buffer = (u32)output_frame->device_addr; + pkt->output_tag = output_frame->output_tag; pkt->extra_data_buffer = (u32)output_frame->extradata_addr; pkt->alloc_len = output_frame->alloc_len; pkt->filled_len = output_frame->filled_len; diff --git a/drivers/media/platform/msm/vidc/hfi_response_handler.c b/drivers/media/platform/msm/vidc/hfi_response_handler.c index b6bdce92f7ca..0fb18d28c547 100644 --- a/drivers/media/platform/msm/vidc/hfi_response_handler.c +++ b/drivers/media/platform/msm/vidc/hfi_response_handler.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -116,6 +116,7 @@ static int hfi_process_sess_evt_seq_changed(u32 device_id, struct hfi_pic_struct *pic_struct; struct hfi_buffer_requirements *buf_req; struct hfi_index_extradata_input_crop_payload *crop_info; + struct hfi_dpb_counts *dpb_counts; u32 entropy_mode = 0; u8 *data_ptr; int prop_id; @@ -216,6 +217,23 @@ static int hfi_process_sess_evt_seq_changed(u32 device_id, data_ptr += sizeof(struct hfi_pic_struct); break; + case HFI_PROPERTY_PARAM_VDEC_DPB_COUNTS: + data_ptr = data_ptr + sizeof(u32); + dpb_counts = (struct hfi_dpb_counts *) data_ptr; + event_notify.max_dpb_count = + dpb_counts->max_dpb_count; + event_notify.max_ref_count = + dpb_counts->max_ref_count; + event_notify.max_dec_buffering = + dpb_counts->max_dec_buffering; + dprintk(VIDC_DBG, + "DPB Counts: dpb %d ref %d buff %d\n", + dpb_counts->max_dpb_count, + dpb_counts->max_ref_count, + dpb_counts->max_dec_buffering); + data_ptr += + sizeof(struct hfi_pic_struct); + break; case HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE: data_ptr = data_ptr + sizeof(u32); colour_info = @@ -313,6 +331,7 @@ static int hfi_process_evt_release_buffer_ref(u32 device_id, event_notify.hal_event_type = HAL_EVENT_RELEASE_BUFFER_REFERENCE; event_notify.packet_buffer = data->packet_buffer; event_notify.extra_data_buffer = data->extra_data_buffer; + event_notify.output_tag = data->output_tag; info->response_type = HAL_SESSION_EVENT_CHANGE; info->response.event = event_notify; @@ -1400,7 +1419,7 @@ static int hfi_process_session_etb_done(u32 device_id, data_done.session_id = (void *)(uintptr_t)pkt->session_id; data_done.status = hfi_map_err_status(pkt->error_type); data_done.size = sizeof(struct msm_vidc_cb_data_done); - data_done.clnt_data = pkt->input_tag; + data_done.input_done.input_tag = pkt->input_tag; data_done.input_done.recon_stats.buffer_index = pkt->ubwc_cr_stats.frame_index; memcpy(&data_done.input_done.recon_stats.ubwc_stats_info, @@ -1532,7 +1551,9 @@ static int hfi_process_session_ftb_done( data_done.output_done.frame_height = pkt->frame_height; data_done.output_done.start_x_coord = pkt->start_x_coord; data_done.output_done.start_y_coord = pkt->start_y_coord; - data_done.output_done.input_tag1 = pkt->input_tag; + data_done.output_done.input_tag = pkt->input_tag; + data_done.output_done.input_tag1 = pkt->input_tag2; + data_done.output_done.output_tag = pkt->output_tag; data_done.output_done.picture_type = pkt->picture_type; data_done.output_done.packet_buffer1 = pkt->packet_buffer; data_done.output_done.extra_data_buffer = diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c index 438d1df63465..1097ea8ed63e 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc.c +++ b/drivers/media/platform/msm/vidc/msm_vidc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -505,6 +505,7 @@ int msm_vidc_qbuf(void *instance, struct v4l2_buffer *b) struct msm_vidc_inst *inst = instance; int rc = 0, i = 0; struct buf_queue *q = NULL; + struct vidc_tag_data tag_data; u32 cr = 0; if (!inst || !inst->core || !b || !valid_v4l2_buffer(b, inst)) { @@ -531,6 +532,12 @@ int msm_vidc_qbuf(void *instance, struct v4l2_buffer *b) b->m.planes[0].reserved[3], b->m.planes[0].reserved[4]); } + tag_data.index = b->index; + tag_data.type = b->type; + tag_data.input_tag = b->m.planes[0].reserved[5]; + tag_data.output_tag = b->m.planes[0].reserved[6]; + msm_comm_store_tags(inst, &tag_data); + q = msm_comm_get_vb2q(inst, b->type); if (!q) { dprintk(VIDC_ERR, @@ -553,6 +560,7 @@ int msm_vidc_dqbuf(void *instance, struct v4l2_buffer *b) struct msm_vidc_inst *inst = instance; int rc = 0, i = 0; struct buf_queue *q = NULL; + struct vidc_tag_data tag_data; if (!inst || !b || !valid_v4l2_buffer(b, inst)) { dprintk(VIDC_ERR, "%s: invalid params, inst %pK\n", @@ -589,6 +597,13 @@ int msm_vidc_dqbuf(void *instance, struct v4l2_buffer *b) &b->m.planes[0].reserved[4]); } + tag_data.index = b->index; + tag_data.type = b->type; + + msm_comm_fetch_tags(inst, &tag_data); + b->m.planes[0].reserved[5] = tag_data.input_tag; + b->m.planes[0].reserved[6] = tag_data.output_tag; + return rc; } EXPORT_SYMBOL(msm_vidc_dqbuf); @@ -1856,6 +1871,7 @@ void *msm_vidc_open(int core_id, int session_type) INIT_MSM_VIDC_LIST(&inst->scratchbufs); INIT_MSM_VIDC_LIST(&inst->freqs); INIT_MSM_VIDC_LIST(&inst->input_crs); + INIT_MSM_VIDC_LIST(&inst->buffer_tags); INIT_MSM_VIDC_LIST(&inst->persistbufs); INIT_MSM_VIDC_LIST(&inst->pending_getpropq); INIT_MSM_VIDC_LIST(&inst->outputbufs); @@ -1981,6 +1997,7 @@ void *msm_vidc_open(int core_id, int session_type) DEINIT_MSM_VIDC_LIST(&inst->eosbufs); DEINIT_MSM_VIDC_LIST(&inst->freqs); DEINIT_MSM_VIDC_LIST(&inst->input_crs); + DEINIT_MSM_VIDC_LIST(&inst->buffer_tags); DEINIT_MSM_VIDC_LIST(&inst->etb_data); DEINIT_MSM_VIDC_LIST(&inst->fbd_data); diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c index a2754c4f6712..3af514d39bfa 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1605,7 +1605,7 @@ static void handle_session_init_done(enum hal_command_response cmd, void *data) } static void msm_vidc_queue_rbr_event(struct msm_vidc_inst *inst, - int fd, u32 offset) + int fd, u32 offset, u32 output_tag) { struct v4l2_event buf_event = {0}; u32 *ptr; @@ -1614,6 +1614,7 @@ static void msm_vidc_queue_rbr_event(struct msm_vidc_inst *inst, ptr = (u32 *)buf_event.u.data; ptr[0] = fd; ptr[1] = offset; + ptr[2] = output_tag; v4l2_event_queue_fh(&inst->event_handler, &buf_event); } @@ -1669,6 +1670,7 @@ static void handle_event_change(enum hal_command_response cmd, void *data) "%s: data_addr %x, extradata_addr %x not found\n", __func__, planes[0], planes[1]); } else { + mbuf->output_tag = event_notify->output_tag; handle_release_buffer_reference(inst, mbuf); kref_put_mbuf(mbuf); } @@ -1730,6 +1732,9 @@ static void handle_event_change(enum hal_command_response cmd, void *data) ptr[10] = msm_comm_get_v4l2_level( inst->fmts[OUTPUT_PORT].fourcc, event_notify->level); + ptr[11] = event_notify->max_dpb_count; + ptr[12] = event_notify->max_ref_count; + ptr[13] = event_notify->max_dec_buffering; dprintk(VIDC_DBG, "Event payload: height = %u width = %u profile = %u level = %u\n", @@ -2474,6 +2479,7 @@ static void handle_ebd(enum hal_command_response cmd, void *data) struct vb2_buffer *vb; struct msm_vidc_inst *inst; struct vidc_hal_ebd *empty_buf_done; + struct vidc_tag_data tag_data; u32 planes[VIDEO_MAX_PLANES] = {0}; u32 extra_idx = 0; @@ -2534,6 +2540,13 @@ static void handle_ebd(enum hal_command_response cmd, void *data) if (extra_idx && extra_idx < VIDEO_MAX_PLANES) vb->planes[extra_idx].bytesused = vb->planes[extra_idx].length; + tag_data.index = vb->index; + tag_data.input_tag = empty_buf_done->input_tag; + tag_data.output_tag = empty_buf_done->output_tag; + tag_data.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + + msm_comm_store_tags(inst, &tag_data); + update_recon_stats(inst, &empty_buf_done->recon_stats); msm_vidc_clear_freq_entry(inst, mbuf->smem[0].device_addr); /* @@ -2603,6 +2616,7 @@ static void handle_fbd(enum hal_command_response cmd, void *data) struct msm_vidc_inst *inst; struct vb2_buffer *vb; struct vidc_hal_fbd *fill_buf_done; + struct vidc_tag_data tag_data; enum hal_buffer buffer_type; u64 time_usec = 0; u32 planes[VIDEO_MAX_PLANES] = {0}; @@ -2670,6 +2684,13 @@ static void handle_fbd(enum hal_command_response cmd, void *data) fill_buf_done->mark_data, fill_buf_done->mark_target); } + tag_data.index = vb->index; + tag_data.input_tag = fill_buf_done->input_tag; + tag_data.output_tag = fill_buf_done->output_tag; + tag_data.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + + msm_comm_store_tags(inst, &tag_data); + extra_idx = EXTRADATA_IDX(inst->bufq[CAPTURE_PORT].num_planes); if (extra_idx && extra_idx < VIDEO_MAX_PLANES) vb->planes[extra_idx].bytesused = vb->planes[extra_idx].length; @@ -2685,6 +2706,8 @@ static void handle_fbd(enum hal_command_response cmd, void *data) mbuf->vvb.flags |= V4L2_BUF_FLAG_KEYFRAME; if (fill_buf_done->flags1 & HAL_BUFFERFLAG_DATACORRUPT) mbuf->vvb.flags |= V4L2_BUF_FLAG_DATA_CORRUPT; + if (fill_buf_done->flags1 & HAL_BUFFERFLAG_ENDOFSUBFRAME) + mbuf->vvb.flags |= V4L2_QCOM_BUF_END_OF_SUBFRAME; switch (fill_buf_done->picture_type) { case HAL_PICTURE_P: mbuf->vvb.flags |= V4L2_BUF_FLAG_PFRAME; @@ -4062,7 +4085,6 @@ int msm_vidc_send_pending_eos_buffers(struct msm_vidc_inst *inst) list_for_each_entry_safe(binfo, temp, &inst->eosbufs.list, list) { data.alloc_len = binfo->smem.size; data.device_addr = binfo->smem.device_addr; - data.clnt_data = data.device_addr; data.buffer_type = HAL_BUFFER_INPUT; data.filled_len = 0; data.offset = 0; @@ -4181,6 +4203,7 @@ static void populate_frame_data(struct vidc_frame_data *data, int extra_idx; struct vb2_buffer *vb; struct vb2_v4l2_buffer *vbuf; + struct vidc_tag_data tag_data; if (!inst || !mbuf || !data) { dprintk(VIDC_ERR, "%s: invalid params %pK %pK %pK\n", @@ -4198,7 +4221,6 @@ static void populate_frame_data(struct vidc_frame_data *data, data->device_addr = mbuf->smem[0].device_addr; data->timestamp = time_usec; data->flags = 0; - data->clnt_data = data->device_addr; if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { data->buffer_type = HAL_BUFFER_INPUT; @@ -4220,6 +4242,14 @@ static void populate_frame_data(struct vidc_frame_data *data, data->buffer_type = msm_comm_get_hal_output_buffer(inst); } + tag_data.index = vb->index; + tag_data.type = vb->type; + + msm_comm_fetch_tags(inst, &tag_data); + data->input_tag = tag_data.input_tag; + data->output_tag = tag_data.output_tag; + + extra_idx = EXTRADATA_IDX(vb->num_planes); if (extra_idx && extra_idx < VIDEO_MAX_PLANES) { data->extradata_addr = mbuf->smem[extra_idx].device_addr; @@ -6667,7 +6697,8 @@ void handle_release_buffer_reference(struct msm_vidc_inst *inst, /* send RBR event to client */ msm_vidc_queue_rbr_event(inst, mbuf->vvb.vb2_buf.planes[0].m.fd, - mbuf->vvb.vb2_buf.planes[0].data_offset); + mbuf->vvb.vb2_buf.planes[0].data_offset, + mbuf->output_tag); /* clear RBR_PENDING flag */ mbuf->flags &= ~MSM_VIDC_FLAG_RBR_PENDING; @@ -6807,6 +6838,90 @@ bool kref_get_mbuf(struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf) return ret; } +void msm_comm_free_buffer_tags(struct msm_vidc_inst *inst) +{ + struct vidc_tag_data *temp, *next; + + if (!inst) { + dprintk(VIDC_ERR, "%s: invalid params %pK\n", + __func__, inst); + return; + } + + mutex_lock(&inst->buffer_tags.lock); + list_for_each_entry_safe(temp, next, &inst->buffer_tags.list, list) { + list_del(&temp->list); + kfree(temp); + } + INIT_LIST_HEAD(&inst->buffer_tags.list); + mutex_unlock(&inst->buffer_tags.lock); +} + +void msm_comm_store_tags(struct msm_vidc_inst *inst, + struct vidc_tag_data *tag_data) +{ + + struct vidc_tag_data *temp, *next; + struct vidc_tag_data *pdata = NULL; + bool found = false; + + if (!inst || !tag_data) { + dprintk(VIDC_ERR, "%s: invalid params %pK %pK\n", + __func__, inst, tag_data); + return; + } + + + mutex_lock(&inst->buffer_tags.lock); + list_for_each_entry_safe(temp, next, &inst->buffer_tags.list, list) { + if (temp->index == tag_data->index && + temp->type == tag_data->type) { + temp->input_tag = tag_data->input_tag; + temp->output_tag = tag_data->output_tag; + found = true; + break; + } + } + + if (!found) { + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dprintk(VIDC_WARN, "%s: malloc failure.\n", __func__); + goto exit; + } + pdata->input_tag = tag_data->input_tag; + pdata->output_tag = tag_data->output_tag; + pdata->index = tag_data->index; + pdata->type = tag_data->type; + list_add_tail(&pdata->list, &inst->buffer_tags.list); + } + +exit: + mutex_unlock(&inst->buffer_tags.lock); +} + +void msm_comm_fetch_tags(struct msm_vidc_inst *inst, + struct vidc_tag_data *tag_data) +{ + struct vidc_tag_data *temp, *next; + + if (!inst || !tag_data) { + dprintk(VIDC_ERR, "%s: invalid params %pK %pK\n", + __func__, inst, tag_data); + return; + } + mutex_lock(&inst->buffer_tags.lock); + list_for_each_entry_safe(temp, next, &inst->buffer_tags.list, list) { + if (temp->index == tag_data->index && + temp->type == tag_data->type) { + tag_data->input_tag = temp->input_tag; + tag_data->output_tag = temp->output_tag; + break; + } + } + mutex_unlock(&inst->buffer_tags.lock); +} + void msm_comm_store_mark_data(struct msm_vidc_list *data_list, u32 index, u32 mark_data, u32 mark_target) { diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.h b/drivers/media/platform/msm/vidc/msm_vidc_common.h index 954bb65d0668..5f0e28db5119 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_common.h +++ b/drivers/media/platform/msm/vidc/msm_vidc_common.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -232,6 +232,11 @@ bool msm_comm_compare_device_plane(struct msm_vidc_buffer *mbuf, u32 type, u32 *planes, u32 i); bool msm_comm_compare_device_planes(struct msm_vidc_buffer *mbuf, u32 type, u32 *planes); +void msm_comm_store_tags(struct msm_vidc_inst *inst, + struct vidc_tag_data *tag_data); +void msm_comm_fetch_tags(struct msm_vidc_inst *inst, + struct vidc_tag_data *tag_data); +void msm_comm_free_buffer_tags(struct msm_vidc_inst *inst); int msm_comm_qbuf_cache_operations(struct msm_vidc_inst *inst, struct msm_vidc_buffer *mbuf); int msm_comm_dqbuf_cache_operations(struct msm_vidc_inst *inst, diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h index 4705a2701723..323ed15b2536 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h +++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -158,6 +158,14 @@ struct vidc_input_cr_data { u32 input_cr; }; +struct vidc_tag_data { + struct list_head list; + u32 index; + u32 type; + u32 input_tag; + u32 output_tag; +}; + struct recon_buf { struct list_head list; u32 buffer_index; @@ -431,6 +439,7 @@ struct msm_vidc_inst { struct buf_queue bufq[MAX_PORT_NUM]; struct msm_vidc_list freqs; struct msm_vidc_list input_crs; + struct msm_vidc_list buffer_tags; struct msm_vidc_list scratchbufs; struct msm_vidc_list persistbufs; struct msm_vidc_list pending_getpropq; @@ -517,6 +526,7 @@ struct msm_vidc_buffer { struct msm_smem smem[VIDEO_MAX_PLANES]; struct vb2_v4l2_buffer vvb; enum msm_vidc_flags flags; + u32 output_tag; }; struct msm_vidc_cvp_buffer { diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_api.h b/drivers/media/platform/msm/vidc/vidc_hfi_api.h index 16dc29d34f99..d1074f065aff 100644 --- a/drivers/media/platform/msm/vidc/vidc_hfi_api.h +++ b/drivers/media/platform/msm/vidc/vidc_hfi_api.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -972,6 +972,8 @@ struct vidc_frame_data { u32 filled_len; u32 mark_target; u32 mark_data; + u32 input_tag; + u32 output_tag; u32 clnt_data; u32 extradata_size; }; @@ -1168,6 +1170,8 @@ struct vidc_hal_ebd { u32 mark_data; u32 stats; u32 offset; + u32 input_tag; + u32 output_tag; u32 alloc_len; u32 filled_len; enum hal_picture picture_type; @@ -1194,6 +1198,7 @@ struct vidc_hal_fbd { u32 start_y_coord; u32 input_tag; u32 input_tag1; + u32 output_tag; enum hal_picture picture_type; u32 packet_buffer1; u32 extra_data_buffer; @@ -1313,12 +1318,16 @@ struct msm_vidc_cb_event { u32 hal_event_type; u32 packet_buffer; u32 extra_data_buffer; + u32 output_tag; u32 pic_struct; u32 colour_space; u32 profile; u32 level; u32 entropy_mode; u32 capture_buf_count; + u32 max_dpb_count; + u32 max_ref_count; + u32 max_dec_buffering; struct hal_index_extradata_input_crop_payload crop_data; }; diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h index 3e8d8b4e1d99..a7c796d1dcec 100644 --- a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h +++ b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -265,6 +265,8 @@ struct hfi_buffer_info { (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x009) #define HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE \ (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x00A) +#define HFI_PROPERTY_PARAM_VDEC_DPB_COUNTS \ + (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x00B) #define HFI_PROPERTY_CONFIG_VDEC_COMMON_START \ @@ -577,6 +579,12 @@ struct hfi_profile_level { u32 level; }; +struct hfi_dpb_counts { + u32 max_dpb_count; + u32 max_ref_count; + u32 max_dec_buffering; +}; + struct hfi_profile_level_supported { u32 profile_count; struct hfi_profile_level rg_profile_level[1]; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 6ae8a4bb1003..81fab0467b63 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1060,6 +1060,7 @@ struct v4l2_buffer { /* mem2mem encoder/decoder */ #define V4L2_BUF_FLAG_LAST 0x00100000 /* Vendor extensions */ +#define V4L2_QCOM_BUF_END_OF_SUBFRAME 0x00000080 #define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x00020000 #define V4L2_BUF_FLAG_DATA_CORRUPT 0x00400000 #define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x01000000 -- GitLab From 2ea1e2ac10623234d791939ac3f5371245fdaabc Mon Sep 17 00:00:00 2001 From: Praneeth Paladugu Date: Tue, 13 Mar 2018 12:42:38 -0700 Subject: [PATCH 1030/1286] msm: vidc: Fix buffer tag issue for encoder For encoder, copy the FW returned tags to vidc layer. Vidc layer sends them back to client. CRs-Fixed: 2197700 Change-Id: Ibac274d256cdb69c5819589cc1d3edf1a0cf363c Signed-off-by: Praneeth Paladugu Signed-off-by: Praveen Chavan --- drivers/media/platform/msm/vidc/hfi_response_handler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/msm/vidc/hfi_response_handler.c b/drivers/media/platform/msm/vidc/hfi_response_handler.c index 0fb18d28c547..08c8ac4eb1a4 100644 --- a/drivers/media/platform/msm/vidc/hfi_response_handler.c +++ b/drivers/media/platform/msm/vidc/hfi_response_handler.c @@ -1504,6 +1504,8 @@ static int hfi_process_session_ftb_done( data_done.output_done.timestamp_hi = pkt->time_stamp_hi; data_done.output_done.timestamp_lo = pkt->time_stamp_lo; data_done.output_done.flags1 = pkt->flags; + data_done.output_done.input_tag = pkt->input_tag; + data_done.output_done.output_tag = pkt->output_tag; data_done.output_done.mark_target = pkt->mark_target; data_done.output_done.mark_data = pkt->mark_data; data_done.output_done.stats = pkt->stats; -- GitLab From 7d4b509344860027cde14f4b042157f1542fc08e Mon Sep 17 00:00:00 2001 From: Konstantin Dorfman Date: Tue, 15 Jan 2019 14:04:38 +0200 Subject: [PATCH 1031/1286] soc: qcom: spcom: fix poll() for channel connected Userspace loads SP application and immediately polls for link up on spcom channel matching the application loaded. There is a race between rpmsg device arrived and channel state becomes connected, so poll() called on channel returns 1(link up) to spcomlib. This change fixes link up logic: instead of checking the channel completion state, need to check that rpmsg device arrived for the channel. Change-Id: I1920a9a55d6ab0cf886996b27e32515df465cc9b Signed-off-by: Konstantin Dorfman --- drivers/soc/qcom/spcom.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/spcom.c b/drivers/soc/qcom/spcom.c index 71e9ef198983..31608b66411e 100644 --- a/drivers/soc/qcom/spcom.c +++ b/drivers/soc/qcom/spcom.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1611,7 +1611,8 @@ static unsigned int spcom_device_poll(struct file *filp, pr_debug("ch [%s] poll CH_CONNECT signaled.\n", name); } mutex_lock(&ch->lock); - done = completion_done(&ch->connect); + done = (ch->rpdev != NULL); + pr_debug("ch [%s] reported done=%d\n", name, done); mutex_unlock(&ch->lock); break; default: -- GitLab From 9898510f7271ea02739381f132317b4b7d5cc181 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 16 Jan 2019 12:01:02 +0530 Subject: [PATCH 1032/1286] usb: gadget: f_fs: Fix NULL pointer issues in ffs driver commit e4ed11d670ed ("usb: gadget: f_fs: Support multi-instance IPC logging") moved the ipc_log context create from functionfs_init to ffs_data_new, ffs_data_new() function will be called from the userspace to mount the ffs function. In case of mount happening multiple times from the userspace on same device node. ipc_log context destroyed from the second mount failure path and causing crashes by using freed ipc_log context for ffs_log(). Hence fix this issue by adding proper check in ffs_data_new() before mounting the device node so that driver can fail the second time mount happens from userspace on same device node. Change-Id: Icb80c69222cd2b15aba612e2624756afd8dde803 Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/function/f_fs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 988f132283a5..ad24bc1a341a 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -1811,10 +1811,18 @@ static void ffs_data_closed(struct ffs_data *ffs) static struct ffs_data *ffs_data_new(const char *dev_name) { char ipcname[24] = "usb_ffs_"; + struct ffs_dev *ffs_dev; struct ffs_data *ffs = kzalloc(sizeof *ffs, GFP_KERNEL); if (unlikely(!ffs)) return NULL; + ffs_dev = _ffs_find_dev(dev_name); + if (ffs_dev && ffs_dev->mounted) { + pr_info("%s(): %s Already mounted\n", __func__, dev_name); + kfree(ffs); + return ERR_PTR(-EBUSY); + } + ENTER(); ffs->io_completion_wq = alloc_ordered_workqueue("%s", 0, dev_name); -- GitLab From d0465385cc935a7b37f3df86fbf1176d6b42125c Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Tue, 22 Jan 2019 14:07:27 +0530 Subject: [PATCH 1033/1286] ARM: dts: msm: Correct the HS PHY interrupt number on Trinket There are two interrupts on Trinket that triggers on HS PHY linestate changes, one by the Qscratch and other by the HS PHY. Use the interrupt which is sourced by PHY rather than the Qscratch so that it can be triggered when core in in low power mode. So, update the interrupt number accordingly. Change-Id: I9218ca2ccdc9fa099d398e1255b28773e983b3bf Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index 6b0aa0f29976..7f0848ebb405 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -26,7 +26,7 @@ #size-cells = <1>; ranges; - interrupts = <0 302 0>, <0 422 0>, <0 254 0>; + interrupts = <0 302 0>, <0 422 0>, <0 260 0>; interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; USB3_GDSC-supply = <&usb30_prim_gdsc>; -- GitLab From 363ba5efcf01f9e118e2aa6d8782526686304f67 Mon Sep 17 00:00:00 2001 From: Srinivasarao P Date: Tue, 8 Jan 2019 13:52:13 +0530 Subject: [PATCH 1034/1286] iommu/iommu-debug: fix buffer overflows in debugfs read functions The kernel buffer 'ubuf' can overflow while copying data to user space in debugfs read functions. Fix it by limiting the length of data to be copied to userspace. Change-Id: Ibb3d8c4fb637ddc0e63677ec2dff14a4cf8c0c73 Signed-off-by: Srinivasarao P --- drivers/iommu/iommu-debug.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/iommu-debug.c b/drivers/iommu/iommu-debug.c index f008234a3930..90c0befee18f 100644 --- a/drivers/iommu/iommu-debug.c +++ b/drivers/iommu/iommu-debug.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1438,6 +1438,7 @@ static ssize_t iommu_debug_dma_attach_read(struct file *file, char __user *ubuf, struct iommu_debug_device *ddev = file->private_data; struct device *dev = ddev->dev; char c[2]; + size_t buflen = sizeof(c); if (*offset) return 0; @@ -1448,13 +1449,14 @@ static ssize_t iommu_debug_dma_attach_read(struct file *file, char __user *ubuf, c[0] = dev->archdata.mapping->domain ? '1' : '0'; c[1] = '\n'; - if (copy_to_user(ubuf, &c, 2)) { + buflen = min(count, buflen); + if (copy_to_user(ubuf, &c, buflen)) { pr_err("copy_to_user failed\n"); return -EFAULT; } *offset = 1; /* non-zero means we're done */ - return 2; + return buflen; } static const struct file_operations iommu_debug_dma_attach_fops = { @@ -1482,7 +1484,7 @@ static ssize_t iommu_debug_test_virt_addr_read(struct file *file, else snprintf(buf, buf_len, "0x%pK\n", test_virt_addr); - buflen = strlen(buf); + buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { pr_err("Couldn't copy_to_user\n"); retval = -EFAULT; @@ -1513,19 +1515,21 @@ static ssize_t iommu_debug_attach_read(struct file *file, char __user *ubuf, { struct iommu_debug_device *ddev = file->private_data; char c[2]; + size_t buflen = sizeof(c); if (*offset) return 0; c[0] = ddev->domain ? '1' : '0'; c[1] = '\n'; - if (copy_to_user(ubuf, &c, 2)) { + buflen = min(count, buflen); + if (copy_to_user(ubuf, &c, buflen)) { pr_err("copy_to_user failed\n"); return -EFAULT; } *offset = 1; /* non-zero means we're done */ - return 2; + return buflen; } static const struct file_operations iommu_debug_attach_fops = { @@ -1603,7 +1607,7 @@ static ssize_t iommu_debug_pte_read(struct file *file, char __user *ubuf, else snprintf(buf, sizeof(buf), "pte=%016llx\n", pte); - buflen = strlen(buf); + buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { pr_err("Couldn't copy_to_user\n"); retval = -EFAULT; @@ -1672,7 +1676,7 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, snprintf(buf, 100, "%pa\n", &phys); } - buflen = strlen(buf); + buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { pr_err("Couldn't copy_to_user\n"); retval = -EFAULT; @@ -1725,7 +1729,7 @@ static ssize_t iommu_debug_dma_atos_read(struct file *file, char __user *ubuf, else snprintf(buf, sizeof(buf), "%pa\n", &phys); - buflen = strlen(buf); + buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { pr_err("Couldn't copy_to_user\n"); retval = -EFAULT; @@ -1958,7 +1962,7 @@ static ssize_t iommu_debug_dma_map_read(struct file *file, char __user *ubuf, iova = ddev->iova; snprintf(buf, sizeof(buf), "%pa\n", &iova); - buflen = strlen(buf); + buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { pr_err("Couldn't copy_to_user\n"); retval = -EFAULT; -- GitLab From 916bfbf639b9e979da5d7410d7222b632c00e454 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Mon, 14 Jan 2019 15:15:55 +0530 Subject: [PATCH 1035/1286] power: qpnp-qg: Report averaged VBAT Report the last FIFO's VBAT for usecases which need an averaged VBAT instead of instantaneous. Change-Id: Idf4ca48a06c012ed52ea06b187ee12ab8cfe12d3 Signed-off-by: Anirudh Ghayal --- drivers/power/supply/qcom/qg-reg.h | 2 ++ drivers/power/supply/qcom/qg-util.c | 17 +++++++++++++++++ drivers/power/supply/qcom/qg-util.h | 1 + drivers/power/supply/qcom/qpnp-qg.c | 4 ++++ 4 files changed, 24 insertions(+) diff --git a/drivers/power/supply/qcom/qg-reg.h b/drivers/power/supply/qcom/qg-reg.h index fd8e1b96242b..95276251ddd8 100644 --- a/drivers/power/supply/qcom/qg-reg.h +++ b/drivers/power/supply/qcom/qg-reg.h @@ -96,6 +96,8 @@ #define QG_POST_ESR_V_DATA0_REG 0x7C #define QG_POST_ESR_I_DATA0_REG 0x7E +#define QG_S2_NORMAL_AVG_V_DATA0_REG 0x80 + #define QG_V_ACCUM_DATA0_RT_REG 0x88 #define QG_I_ACCUM_DATA0_RT_REG 0x8B #define QG_ACCUM_CNT_RT_REG 0x8E diff --git a/drivers/power/supply/qcom/qg-util.c b/drivers/power/supply/qcom/qg-util.c index 9a41314f8ed6..2154b318d86b 100644 --- a/drivers/power/supply/qcom/qg-util.c +++ b/drivers/power/supply/qcom/qg-util.c @@ -427,3 +427,20 @@ int qg_get_battery_voltage(struct qpnp_qg *chip, int *vbat_uv) return rc; } + +int qg_get_vbat_avg(struct qpnp_qg *chip, int *vbat_uv) +{ + int rc = 0; + u64 last_vbat = 0; + + rc = qg_read(chip, chip->qg_base + QG_S2_NORMAL_AVG_V_DATA0_REG, + (u8 *)&last_vbat, 2); + if (rc < 0) { + pr_err("Failed to read S2_NORMAL_AVG_V reg, rc=%d\n", rc); + return rc; + } + + *vbat_uv = V_RAW_TO_UV(last_vbat); + + return 0; +} diff --git a/drivers/power/supply/qcom/qg-util.h b/drivers/power/supply/qcom/qg-util.h index b342040cd4a2..2ada4781fa26 100644 --- a/drivers/power/supply/qcom/qg-util.h +++ b/drivers/power/supply/qcom/qg-util.h @@ -29,6 +29,7 @@ int qg_write_monotonic_soc(struct qpnp_qg *chip, int msoc); int qg_get_battery_temp(struct qpnp_qg *chip, int *batt_temp); int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua); int qg_get_battery_voltage(struct qpnp_qg *chip, int *vbat_uv); +int qg_get_vbat_avg(struct qpnp_qg *chip, int *vbat_uv); s64 qg_iraw_to_ua(struct qpnp_qg *chip, int iraw); #endif diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c index 97ec786177b8..08c3c364811b 100644 --- a/drivers/power/supply/qcom/qpnp-qg.c +++ b/drivers/power/supply/qcom/qpnp-qg.c @@ -1872,6 +1872,9 @@ static int qg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CC_SOC: rc = qg_get_cc_soc(chip, &pval->intval); break; + case POWER_SUPPLY_PROP_VOLTAGE_AVG: + rc = qg_get_vbat_avg(chip, &pval->intval); + break; default: pr_debug("Unsupported property %d\n", psp); break; @@ -1925,6 +1928,7 @@ static enum power_supply_property qg_psy_props[] = { POWER_SUPPLY_PROP_SOH, POWER_SUPPLY_PROP_FG_RESET, POWER_SUPPLY_PROP_CC_SOC, + POWER_SUPPLY_PROP_VOLTAGE_AVG, }; static const struct power_supply_desc qg_psy_desc = { -- GitLab From 6b9bcb078d17113ff29bb853ecddd9b763f105b0 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Wed, 26 Dec 2018 16:07:55 +0530 Subject: [PATCH 1036/1286] defconfig: Enable SCC and SLPI pinctrl driver for SM6150 Enable the sensor clock controller driver so that kernel clients can manage sensor clocks. Enable SLPI PIN controller driver for SSC QuP GPIOs on SM6150 platform. Signed-off-by: Rahul Sharma Change-Id: I0edfefb6077cf7f8ee466213246060a7f063a2d4 --- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 2 ++ arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index fa6b8c6faa79..dbd5b5501014 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -352,6 +352,7 @@ CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_SM6150=y +CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y @@ -529,6 +530,7 @@ CONFIG_MSM_VIDEOCC_SM6150=y CONFIG_MSM_DEBUGCC_SM6150=y CONFIG_MSM_CAMCC_SM6150=y CONFIG_MSM_DISPCC_SM6150=y +CONFIG_MSM_SCC_SM6150=y CONFIG_MSM_CAMCC_SDMMAGPIE=y CONFIG_MSM_DISPCC_SDMMAGPIE=y CONFIG_MSM_GCC_SDMMAGPIE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index 8f649ef48ea4..bec7f78e9d93 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -366,6 +366,7 @@ CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_SM6150=y +CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y @@ -551,6 +552,7 @@ CONFIG_MSM_VIDEOCC_SM6150=y CONFIG_MSM_DEBUGCC_SM6150=y CONFIG_MSM_CAMCC_SM6150=y CONFIG_MSM_DISPCC_SM6150=y +CONFIG_MSM_SCC_SM6150=y CONFIG_MSM_CAMCC_SDMMAGPIE=y CONFIG_MSM_DISPCC_SDMMAGPIE=y CONFIG_MSM_GCC_SDMMAGPIE=y -- GitLab From bcefdf3cdf127c7973a0b2152ea606877617337c Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Tue, 22 Jan 2019 16:41:35 +0530 Subject: [PATCH 1037/1286] defconfig: enable MDSS DSI PLL for TRINKET Add changes to enable MDSS DSI PLL for TRINKET target. Change-Id: Ib85c8ef5180e701b8536f59f46dad1046d3cc1ba Signed-off-by: Tharun Raj Soma --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 13fba4a12fe7..a494111ccb6a 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -506,6 +506,7 @@ CONFIG_RMNET_IPA3=y CONFIG_RNDIS_IPA=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m +CONFIG_QCOM_MDSS_PLL=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_CLOCK_CPU_OSM=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 2060e06ead9e..a6f31e4b4d80 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -528,6 +528,7 @@ CONFIG_RMNET_IPA3=y CONFIG_RNDIS_IPA=y CONFIG_IPA_UT=y CONFIG_MSM_11AD=m +CONFIG_QCOM_MDSS_PLL=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_SPMI_PMIC_CLKDIV=y CONFIG_CLOCK_CPU_OSM=y -- GitLab From 437e269f212cc7d1a927d280b605b4abf7b93006 Mon Sep 17 00:00:00 2001 From: Arun Kumar Neelakantam Date: Tue, 22 Jan 2019 16:48:57 +0530 Subject: [PATCH 1038/1286] soc: qcom: qmi_interface: Fix race between net_reset and release qmi client calling qmi_handle_release while handling net_reset cause NULL pointer access. Synchronize the net_reset handling with qmi_handle_release to avoid memory leak and invalid pointer access. CRs-Fixed: 2383987 Change-Id: I8179f96e5dfabe945b1a37f83530bc3b05ed746a Signed-off-by: Arun Kumar Neelakantam --- drivers/soc/qcom/qmi_interface.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index d940cca0a3dc..c6800ebd0434 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -459,17 +459,18 @@ static void qmi_handle_net_reset(struct qmi_handle *qmi) if (IS_ERR(sock)) return; - mutex_lock(&qmi->sock_lock); - sock_release(qmi->sock); - qmi->sock = NULL; - mutex_unlock(&qmi->sock_lock); - qmi_recv_del_server(qmi, -1, -1); if (qmi->ops.net_reset) qmi->ops.net_reset(qmi); mutex_lock(&qmi->sock_lock); + /* Already qmi_handle_release() started */ + if (!qmi->sock) { + sock_release(sock); + return; + } + sock_release(qmi->sock); qmi->sock = sock; qmi->sq = sq; mutex_unlock(&qmi->sock_lock); @@ -695,23 +696,24 @@ EXPORT_SYMBOL(qmi_handle_init); */ void qmi_handle_release(struct qmi_handle *qmi) { - struct socket *sock = qmi->sock; + struct socket *sock; struct qmi_service *svc, *tmp; struct qmi_txn *txn; int txn_id; + mutex_lock(&qmi->sock_lock); + sock = qmi->sock; write_lock_bh(&sock->sk->sk_callback_lock); sock->sk->sk_user_data = NULL; write_unlock_bh(&sock->sk->sk_callback_lock); - cancel_work_sync(&qmi->work); - - qmi_recv_del_server(qmi, -1, -1); - - mutex_lock(&qmi->sock_lock); sock_release(sock); qmi->sock = NULL; mutex_unlock(&qmi->sock_lock); + cancel_work_sync(&qmi->work); + + qmi_recv_del_server(qmi, -1, -1); + destroy_workqueue(qmi->wq); mutex_lock(&qmi->txn_lock); -- GitLab From bb2bcd921b2e9356adb421aea6014e1d7c8d27fe Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Tue, 22 Jan 2019 18:23:52 +0530 Subject: [PATCH 1039/1286] ARM: dts: msm: Fix SMB1355 interrupt configuration Update the gpio number of SMB1355 interrupt configuration for trinket target. Change-Id: I9eff2623389e0a04b1d06fb852c31b4c0d9dce3b Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 2 +- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 3a0bc4a9a75a..5bfefed8f4fe 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -216,7 +216,7 @@ pinctrl-names = "default"; pinctrl-0 = <&smb_int_default>; interrupt-parent = <&tlmm>; - interrupts = <62 IRQ_TYPE_LEVEL_LOW>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 51b4af6cfac3..bb8a1f131f0c 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -168,7 +168,7 @@ pinctrl-names = "default"; pinctrl-0 = <&smb_int_default>; interrupt-parent = <&tlmm>; - interrupts = <62 IRQ_TYPE_LEVEL_LOW>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; status = "ok"; }; -- GitLab From b0f59ea68fe6d27d157ac2ebd1f849300c7be514 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Tue, 22 Jan 2019 19:00:32 +0530 Subject: [PATCH 1040/1286] ARM: dts: msm: enable display in command mode on TRINKET Add support to enable display in command mode on TRINKET. Change-Id: I9d322dca546b188a4e7bffba9fa200336083ba65 Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts index fe4e03b4dd51..4fef9da0c768 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-idp-overlay.dts @@ -25,6 +25,6 @@ qcom,board-id = <34 0>; }; -&dsi_td4330_truly_vid_display { +&dsi_td4330_truly_cmd_display { qcom,dsi-display-active; }; -- GitLab From caa945c199a943514fd98a221a57bde4564e9deb Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Tue, 22 Jan 2019 16:01:36 +0200 Subject: [PATCH 1041/1286] wil6210: prevent access to RGF_CAF_ICR in Talyn Due to access control RGF_CAF_ICR cannot be accessed by host. Such an access will cause device AHB logger to halt and it will not capture future AHB fault if there is any. Change-Id: I9c9eddb4c059241ad7404f971c2eda6c75e01658 Signed-off-by: Maya Erez --- drivers/net/wireless/ath/wil6210/main.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 5c307fe5088a..f419f24611e3 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -1571,11 +1571,6 @@ static void wil_pre_fw_config(struct wil6210_priv *wil) if (wil->hw_version < HW_VER_TALYN_MB) { wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0); wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0); - } else { - wil_s(wil, - RGF_CAF_ICR_TALYN_MB + offsetof(struct RGF_ICR, ICR), 0); - wil_w(wil, RGF_CAF_ICR_TALYN_MB + - offsetof(struct RGF_ICR, IMV), ~0); } /* clear PAL_UNIT_ICR (potential D0->D3 leftover) * In Talyn-MB host cannot access this register due to -- GitLab From 9afc33e39e1f0e0ad7eaa032447eaa9682cf7fc3 Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Tue, 22 Jan 2019 16:17:58 +0200 Subject: [PATCH 1042/1286] wil6210: prevent ioctl access while in reset or suspend Accessing some of the memory of the device while the device is resetting or suspending may cause unexpected error as the HW is still not in a stable state. Prevent this access to guarantee successful read/write memory operations. Change-Id: Idbf046e21726ec8d074161f75643f34137d6ec24 Signed-off-by: Ahmad Masri Signed-off-by: Maya Erez --- drivers/net/wireless/ath/wil6210/ioctl.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/ioctl.c b/drivers/net/wireless/ath/wil6210/ioctl.c index b7df8512167c..d68cab72072f 100644 --- a/drivers/net/wireless/ath/wil6210/ioctl.c +++ b/drivers/net/wireless/ath/wil6210/ioctl.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2014,2017 Qualcomm Atheros, Inc. + * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -70,6 +71,7 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data) struct wil_memio io; void __iomem *a; bool need_copy = false; + int rc; if (copy_from_user(&io, data, sizeof(io))) return -EFAULT; @@ -83,6 +85,11 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data) io.op); return -EINVAL; } + + rc = wil_mem_access_lock(wil); + if (rc) + return rc; + /* operation */ switch (io.op & wil_mmio_op_mask) { case wil_mmio_read: @@ -97,9 +104,12 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data) #endif default: wil_err(wil, "Unsupported operation, op = 0x%08x\n", io.op); + wil_mem_access_unlock(wil); return -EINVAL; } + wil_mem_access_unlock(wil); + if (need_copy) { wil_dbg_ioctl(wil, "IO done: addr(0x%08x) val(0x%08x) op(0x%08x)\n", @@ -141,6 +151,12 @@ static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data) if (!block) return -ENOMEM; + rc = wil_mem_access_lock(wil); + if (rc) { + kfree(block); + return rc; + } + /* operation */ switch (io.op & wil_mmio_op_mask) { case wil_mmio_read: @@ -148,14 +164,14 @@ static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data) wil_hex_dump_ioctl("Read ", block, io.size); if (copy_to_user(io.block, block, io.size)) { rc = -EFAULT; - goto out_free; + goto out_unlock; } break; #if defined(CONFIG_WIL6210_WRITE_IOCTL) case wil_mmio_write: if (copy_from_user(block, io.block, io.size)) { rc = -EFAULT; - goto out_free; + goto out_unlock; } wil_memcpy_toio_32(a, block, io.size); wmb(); /* make sure write propagated to HW */ @@ -168,7 +184,8 @@ static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data) break; } -out_free: +out_unlock: + wil_mem_access_unlock(wil); kfree(block); return rc; } -- GitLab From 3dae7bb7a81d0a6efe779f5b77214668d90f6f65 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Tue, 22 Jan 2019 21:27:56 +0530 Subject: [PATCH 1043/1286] ARM: dts: msm: enable DFPS, ESD and ULPS for td4330 truly panel on TRINKET Add support for DFPS, ESD and ULPS for td4330 truly panel on TRINKET. With this change power optimization can be achieved during idle screen scenarios. Change-Id: Ie2883b7e7bfa67d8bd9b70edd000f1c3f8ca9598 Signed-off-by: Tharun Raj Soma --- .../boot/dts/qcom/trinket-sde-display.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi index 1ca88a6df603..537e78fc5d4a 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi @@ -149,6 +149,14 @@ &dsi_td4330_truly_cmd { qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = @@ -167,6 +175,18 @@ &dsi_td4330_truly_video { qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-min-refresh-rate = <48>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = -- GitLab From c4ac6998e1502d9887197f9c8d81d2843d6f79a0 Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Tue, 22 Jan 2019 11:19:33 -0700 Subject: [PATCH 1044/1286] soc: qcom: wda: Fix wda cleanup Fixed an issue that incorrect wda data pointer is passed to the cleanup function in back-to-back SSR scenarios. The cleanup would not be done propperty and could lead to invalid memory access later. CRs-fixed: 2384118 Change-Id: Ie50a419d0c9a5a1a906931e1a7123b29a086a9e4 Acked-by: Weiyi Chen Signed-off-by: Sean Tranchetti --- drivers/soc/qcom/qmi_rmnet.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qmi_rmnet.c b/drivers/soc/qcom/qmi_rmnet.c index bede9fcf49b1..b04796e9f710 100644 --- a/drivers/soc/qcom/qmi_rmnet.c +++ b/drivers/soc/qcom/qmi_rmnet.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -559,7 +559,7 @@ void qmi_rmnet_qmi_exit(void *qmi_pt, void *port) data = qmi->wda_pending; if (data) { - wda_qmi_client_exit(qmi->wda_client); + wda_qmi_client_exit(data); qmi->wda_client = NULL; qmi->wda_pending = NULL; } -- GitLab From 162b08093bdf8001a968cc8de74fd1d6f11a9332 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Tue, 22 Oct 2013 23:19:18 -0700 Subject: [PATCH 1045/1286] ARM: hw_breakpoint: don't clear bkpts during halting mode debug Skip clearing breakpoints and enabling monitor mode when halting debug mode is enabled. This avoids wiping out user configured breakpoints as part of halting mode debug. Change-Id: I0dcd1b7dc048f3d795b0c7c31ba6b90d7b6e9eeb Signed-off-by: Pratik Patel Signed-off-by: Jeevan Shriram --- arch/arm/kernel/hw_breakpoint.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index af2a7f1e3103..4268998b535d 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -226,6 +226,18 @@ static int get_num_brps(void) return core_has_mismatch_brps() ? brps - 1 : brps; } +/* Determine if halting mode is enabled */ +static int halting_mode_enabled(void) +{ + u32 dscr; + + ARM_DBG_READ(c0, c1, 0, dscr); + WARN_ONCE(dscr & ARM_DSCR_HDBGEN, + "halting debug mode enabled. Unable to access hardware resources.\n"); + + return !!(dscr & ARM_DSCR_HDBGEN); +} + /* * In order to access the breakpoint/watchpoint control registers, * we must be running in debug monitor mode. Unfortunately, we can @@ -930,6 +942,17 @@ static void reset_ctrl_regs(unsigned int cpu) int i, raw_num_brps, err = 0; u32 val; + /* + * Bail out without clearing the breakpoint registers if halting + * debug mode or monitor debug mode is enabled. Checking for monitor + * debug mode here ensures we don't clear the breakpoint registers + * across power collapse if save and restore code has already + * preserved the debug register values or they weren't lost and + * monitor mode was already enabled earlier. + */ + if (halting_mode_enabled() || monitor_mode_enabled()) + return; + /* * v7 debug contains save and restore registers so that debug state * can be maintained across low-power modes without leaving the debug -- GitLab From 3693d049bda4e3f0ccb66d2e8dbdc4b548730089 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Tue, 22 Jan 2019 10:19:30 -0500 Subject: [PATCH 1046/1286] msm: npu: Increase maximum patch number for v2 commands Increase the maximum patch number for v2 commands to support MIMO mode. Change-Id: Id36b23a8b08e9cffe957cc0bee7ef3e496d68007 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_common.h | 3 ++- drivers/media/platform/msm/npu/npu_dev.c | 8 ++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_common.h b/drivers/media/platform/msm/npu/npu_common.h index 494ab01d7590..4b839d34b2a5 100644 --- a/drivers/media/platform/msm/npu/npu_common.h +++ b/drivers/media/platform/msm/npu/npu_common.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -49,6 +49,7 @@ #define NPU_MAX_DT_NAME_LEN 21 #define NPU_MAX_PWRLEVELS 8 #define NPU_MAX_STATS_BUF_SIZE 16384 +#define NPU_MAX_PATCH_NUM 160 enum npu_power_level { NPU_PWRLEVEL_MINSVS = 0, diff --git a/drivers/media/platform/msm/npu/npu_dev.c b/drivers/media/platform/msm/npu/npu_dev.c index 427a9872fef4..3ed39bfe3f6f 100644 --- a/drivers/media/platform/msm/npu/npu_dev.c +++ b/drivers/media/platform/msm/npu/npu_dev.c @@ -1342,9 +1342,9 @@ static int npu_load_network_v2(struct npu_client *client, return -EFAULT; } - if (req.patch_info_num > MSM_NPU_MAX_PATCH_LAYER_NUM) { + if (req.patch_info_num > NPU_MAX_PATCH_NUM) { pr_err("Invalid patch info num %d[max:%d]\n", - req.patch_info_num, MSM_NPU_MAX_PATCH_LAYER_NUM); + req.patch_info_num, NPU_MAX_PATCH_NUM); return -EINVAL; } @@ -1467,9 +1467,9 @@ static int npu_exec_network_v2(struct npu_client *client, return -EFAULT; } - if (req.patch_buf_info_num > MSM_NPU_MAX_PATCH_LAYER_NUM) { + if (req.patch_buf_info_num > NPU_MAX_PATCH_NUM) { pr_err("Invalid patch buf info num %d[max:%d]\n", - req.patch_buf_info_num, MSM_NPU_MAX_PATCH_LAYER_NUM); + req.patch_buf_info_num, NPU_MAX_PATCH_NUM); return -EINVAL; } -- GitLab From 92fefd881cd5762cc3ee86388871eb0dfeea72aa Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Tue, 8 Jan 2019 19:14:26 -0800 Subject: [PATCH 1047/1286] power: qpnp-smb5: Add VOLTAGE_VPH property Add VOLTAGE_VPH property in SMB5 driver to export vph voltage to user space. Change-Id: I1a6ce4f37b3a55401baadd819c232d8296e62fb2 Signed-off-by: Harry Yang --- drivers/power/supply/qcom/qpnp-smb5.c | 6 +++++- drivers/power/supply/qcom/smb5-lib.c | 25 ++++++++++++++++++++----- drivers/power/supply/qcom/smb5-lib.h | 4 +++- 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index 516ac724fbde..63200249f23a 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -642,6 +642,7 @@ static enum power_supply_property smb5_usb_props[] = { POWER_SUPPLY_PROP_MOISTURE_DETECTED, POWER_SUPPLY_PROP_HVDCP_OPTI_ALLOWED, POWER_SUPPLY_PROP_QC_OPTI_DISABLE, + POWER_SUPPLY_PROP_VOLTAGE_VPH, }; static int smb5_usb_get_prop(struct power_supply *psy, @@ -797,6 +798,9 @@ static int smb5_usb_get_prop(struct power_supply *psy, if (chg->hw_connector_mitigation) val->intval |= POWER_SUPPLY_QC_CTM_DISABLE; break; + case POWER_SUPPLY_PROP_VOLTAGE_VPH: + rc = smblib_get_prop_vph_voltage_now(chg, val); + break; default: pr_err("get prop %d is not supported in usb\n", psp); rc = -EINVAL; diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index bac6c41a219b..4000ed4a7869 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -3034,6 +3034,23 @@ int smblib_get_prop_usb_voltage_now(struct smb_charger *chg, return smblib_read_usbin_voltage_chan(chg, val); } +int smblib_get_prop_vph_voltage_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + if (!chg->iio.vph_v_chan) + return -ENODATA; + + rc = iio_read_channel_processed(chg->iio.vph_v_chan, &val->intval); + if (rc < 0) { + smblib_err(chg, "Couldn't read vph channel rc=%d\n", rc); + return rc; + } + + return 0; +} + bool smblib_rsbux_low(struct smb_charger *chg, int r_thr) { int r_sbu1, r_sbu2; @@ -5323,14 +5340,12 @@ irqreturn_t dc_plugin_irq_handler(int irq, void *data) int rc, wireless_vout = 0; int sec_charger; - rc = iio_read_channel_processed(chg->iio.vph_v_chan, - &wireless_vout); + rc = smblib_get_prop_vph_voltage_now(chg, &pval); if (rc < 0) return IRQ_HANDLED; - wireless_vout *= 2; - wireless_vout /= 100000; - wireless_vout *= 100000; + /* 2*VPH, with a granularity of 100mV */ + wireless_vout = ((pval.intval * 2) / 100000) * 100000; rc = smblib_is_input_present(chg, &input_present); if (rc < 0) diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h index 27bae2895c07..386aca3eb879 100644 --- a/drivers/power/supply/qcom/smb5-lib.h +++ b/drivers/power/supply/qcom/smb5-lib.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -666,6 +666,8 @@ int smblib_get_prop_charger_temp(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_die_health(struct smb_charger *chg); int smblib_get_prop_connector_health(struct smb_charger *chg); +int smblib_get_prop_vph_voltage_now(struct smb_charger *chg, + union power_supply_propval *val); int smblib_set_prop_pd_current_max(struct smb_charger *chg, const union power_supply_propval *val); int smblib_set_prop_sdp_current_max(struct smb_charger *chg, -- GitLab From a8aa70cd79208e36c6ab4de18ea80035282fd7ba Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Tue, 22 Jan 2019 14:24:20 -0700 Subject: [PATCH 1048/1286] ARM: dts: msm: enable PSCI for sdxprairie Enable PSCI firmwware support for CPU for sdxprairie. Change-Id: Ia1168b00c6d486db48596db7d194be726f5618bb Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index b0b69d11c6da..d755b7da104d 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -117,9 +117,15 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + soc: soc { }; }; -- GitLab From 666ccc011b84a0c4df201f2b4f50526701577b8e Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Tue, 22 Jan 2019 14:26:22 -0800 Subject: [PATCH 1049/1286] msm: ipa: revert gsi check for erindex Gsi_alloc_channel should complete successfully even if erindex is invalid since for some channels even ring is not needed. Change-Id: I41c20bb76daf701f261f8c956523b702b4b4c09f Signed-off-by: Michael Adisumarta --- drivers/platform/msm/gsi/gsi.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index 3c862f3f510e..b37859e6d025 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -2377,17 +2377,20 @@ int gsi_alloc_channel(struct gsi_chan_props *props, unsigned long dev_hdl, } erindex = props->evt_ring_hdl != ~0 ? props->evt_ring_hdl : GSI_NO_EVT_ERINDEX; - if (erindex == GSI_NO_EVT_ERINDEX || erindex >= GSI_EVT_RING_MAX) { + if (erindex != GSI_NO_EVT_ERINDEX && erindex >= GSI_EVT_RING_MAX) { GSIERR("invalid erindex %u\n", erindex); devm_kfree(gsi_ctx->dev, user_data); return -GSI_STATUS_INVALID_PARAMS; } - ctx->evtr = &gsi_ctx->evtr[erindex]; - atomic_inc(&ctx->evtr->chan_ref_cnt); - if (props->prot != GSI_CHAN_PROT_GCI && - ctx->evtr->props.exclusive && - atomic_read(&ctx->evtr->chan_ref_cnt) == 1) - ctx->evtr->chan = ctx; + + if (erindex < GSI_EVT_RING_MAX) { + ctx->evtr = &gsi_ctx->evtr[erindex]; + atomic_inc(&ctx->evtr->chan_ref_cnt); + if (props->prot != GSI_CHAN_PROT_GCI && + ctx->evtr->props.exclusive && + atomic_read(&ctx->evtr->chan_ref_cnt) == 1) + ctx->evtr->chan = ctx; + } gsi_program_chan_ctx(props, gsi_ctx->per.ee, erindex); -- GitLab From 0d6958dac9109621d7e2185044d05ce555c1ff19 Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Wed, 16 Jan 2019 16:57:02 +0800 Subject: [PATCH 1050/1286] ARM: dts: msm: add touch support in DT for trinket QRD Add Synaptics touch support DT node for trinket QRD platform. Change-Id: I8e748eca402beec6ccceb4dcf8972f818cca09eb Signed-off-by: Fei Mao --- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 51b4af6cfac3..0c42ec42bfb0 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -52,6 +52,35 @@ 2000000 1500000 1000000 500000>; }; +&qupv3_se2_i2c { + status = "okay"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + vdd-supply = <&pm6125_l9>; + avdd-supply = <&pm6125_l21>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,bus-reg-name = "vdd"; + synaptics,pwr-reg-name = "avdd"; + synaptics,irq-gpio = <&tlmm 88 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 87 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; +}; + &sdhc_1 { vdd-supply = <&pm6125_l24>; qcom,vdd-voltage-level = <2950000 2950000>; -- GitLab From 0635add40c6d67e306deea2cf8b98d340b7fe143 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Mon, 14 Jan 2019 17:17:01 -0800 Subject: [PATCH 1051/1286] power: qpnp-fg-gen4: Add CHARGE_NOW property Add POWER_SUPPLY_PROP_CHARGE_NOW property to expose the initial capacity when the capacity learning has begun. CRs-Fixed: 2382855 Change-Id: Ic9cf0251f8bef2f05a6f0b0d5cfe31414d3da2b8 Signed-off-by: Subbaraman Narayanamurthy --- drivers/power/supply/qcom/qpnp-fg-gen4.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index 0f3899e3a139..ca6b528ade12 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -3522,6 +3522,9 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CHARGE_NOW_RAW: rc = fg_gen4_get_charge_raw(chip, &pval->intval); break; + case POWER_SUPPLY_PROP_CHARGE_NOW: + pval->intval = chip->cl->init_cap_uah; + break; case POWER_SUPPLY_PROP_CHARGE_FULL: rc = fg_gen4_get_learned_capacity(chip, &temp); if (!rc) @@ -3715,6 +3718,7 @@ static enum power_supply_property fg_psy_props[] = { POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, POWER_SUPPLY_PROP_CHARGE_NOW_RAW, + POWER_SUPPLY_PROP_CHARGE_NOW, POWER_SUPPLY_PROP_CHARGE_FULL, POWER_SUPPLY_PROP_CHARGE_COUNTER, POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, -- GitLab From 425616e8edacbc279e12a1a58a1b601f309af7eb Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 17 Jan 2019 19:23:24 -0800 Subject: [PATCH 1052/1286] power: qpnp-fg-gen4: Add CC_SOC property Add CC_SOC property to expose coulomb counter value in centi percentage so that charger driver can make use of it for certain workarounds. Change-Id: Ic427c65f4602220088e97c811de1cfb32dfff8f9 Signed-off-by: Subbaraman Narayanamurthy --- drivers/power/supply/qcom/qpnp-fg-gen4.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index ca6b528ade12..a1a2287b53f9 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -3476,7 +3476,7 @@ static int fg_psy_get_property(struct power_supply *psy, { struct fg_gen4_chip *chip = power_supply_get_drvdata(psy); struct fg_dev *fg = &chip->fg; - int rc = 0; + int rc = 0, val; int64_t temp; switch (psp) { @@ -3486,6 +3486,15 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CAPACITY_RAW: rc = fg_get_msoc_raw(fg, &pval->intval); break; + case POWER_SUPPLY_PROP_CC_SOC: + rc = fg_get_sram_prop(&chip->fg, FG_SRAM_CC_SOC, &val); + if (rc < 0) { + pr_err("Error in getting CC_SOC, rc=%d\n", rc); + return rc; + } + /* Show it in centi-percentage */ + pval->intval = div_s64((int64_t)val * 10000, CC_SOC_30BIT); + break; case POWER_SUPPLY_PROP_VOLTAGE_NOW: if (fg->battery_missing) pval->intval = 3700000; @@ -3706,6 +3715,7 @@ static int fg_property_is_writeable(struct power_supply *psy, static enum power_supply_property fg_psy_props[] = { POWER_SUPPLY_PROP_CAPACITY, POWER_SUPPLY_PROP_CAPACITY_RAW, + POWER_SUPPLY_PROP_CC_SOC, POWER_SUPPLY_PROP_TEMP, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_VOLTAGE_OCV, -- GitLab From eff5986ce316a995165bcb0cfcad89d89716988e Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 17 Jan 2019 19:35:42 -0800 Subject: [PATCH 1053/1286] power: qpnp-fg-gen4: add support to show high resolution of MSOC Currently CAPACITY_RAW property shows the monotonic SOC read from FG_BATT_SOC peripheral which is in the scale of 0-255. For showing a higher resolution of monotonic SOC to the user, obtain it from FG SRAM which is in the scale of 0-65535 and show it in centi-percentage when "qcom,soc-hi-res" property is specified. When the charger is removed, show CAPACITY_RAW simply as CAPACITY multiplied by 100. Change-Id: I01b81be1d0ad9020bb6f5d33afe1401dde289a12 Signed-off-by: Subbaraman Narayanamurthy --- .../power/supply/qcom/qpnp-fg-gen4.txt | 7 ++++ drivers/power/supply/qcom/qpnp-fg-gen4.c | 33 ++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt index c696341648a1..9bc43dc97f89 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt @@ -419,6 +419,13 @@ First Level Node - FG Gen4 device multiple battery profiles to be specified for a battery for proper functionality. +- qcom,soc-hi-res + Usage: optional + Value type: + Definition: A boolean property that when specified shows high + resolution of monotonic SOC under CAPACITY_RAW property + during charging in the scale of 0-10000. + ========================================================== Second Level Nodes - Peripherals managed by FG Gen4 driver ========================================================== diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index a1a2287b53f9..9cee5ed7c478 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -195,6 +195,7 @@ struct fg_dt_props { bool five_pin_battery; bool multi_profile_load; bool esr_calib_dischg; + bool soc_hi_res; int cutoff_volt_mv; int empty_volt_mv; int cutoff_curr_ma; @@ -829,6 +830,35 @@ static int fg_gen4_get_prop_capacity(struct fg_dev *fg, int *val) return 0; } +static int fg_gen4_get_prop_capacity_raw(struct fg_gen4_chip *chip, int *val) +{ + struct fg_dev *fg = &chip->fg; + int rc; + + if (!chip->dt.soc_hi_res) { + rc = fg_get_msoc_raw(fg, val); + return rc; + } + + if (!is_input_present(fg)) { + rc = fg_gen4_get_prop_capacity(fg, val); + if (!rc) + *val = *val * 100; + return rc; + } + + rc = fg_get_sram_prop(&chip->fg, FG_SRAM_MONOTONIC_SOC, val); + if (rc < 0) { + pr_err("Error in getting MONOTONIC_SOC, rc=%d\n", rc); + return rc; + } + + /* Show it in centi-percentage */ + *val = (*val * 10000) / 0xFFFF; + + return 0; +} + static inline void get_esr_meas_current(int curr_ma, u8 *val) { switch (curr_ma) { @@ -3484,7 +3514,7 @@ static int fg_psy_get_property(struct power_supply *psy, rc = fg_gen4_get_prop_capacity(fg, &pval->intval); break; case POWER_SUPPLY_PROP_CAPACITY_RAW: - rc = fg_get_msoc_raw(fg, &pval->intval); + rc = fg_gen4_get_prop_capacity_raw(chip, &pval->intval); break; case POWER_SUPPLY_PROP_CC_SOC: rc = fg_get_sram_prop(&chip->fg, FG_SRAM_CC_SOC, &val); @@ -4859,6 +4889,7 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) "qcom,five-pin-battery"); chip->dt.multi_profile_load = of_property_read_bool(node, "qcom,multi-profile-load"); + chip->dt.soc_hi_res = of_property_read_bool(node, "qcom,soc-hi-res"); return 0; } -- GitLab From 7c0592dbc7531fab1a15b3ef1f121309d69c195c Mon Sep 17 00:00:00 2001 From: Shaoqing Liu Date: Wed, 2 Jan 2019 15:31:29 +0800 Subject: [PATCH 1054/1286] ARM: dts: msm: Add coresight components for sdxprairie Add coresight components for sdxprairie. Change-Id: I8a0373cb72815dc9a472989619b23e4c2adfab69 Signed-off-by: Shaoqing Liu --- .../boot/dts/qcom/sdxprairie-coresight.dtsi | 1173 +++++++++++++++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 1 + 2 files changed, 1174 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi new file mode 100644 index 000000000000..5723a018814a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-coresight.dtsi @@ -0,0 +1,1173 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator_qdss>; + }; + }; + + port@1 { + reg = <1>; + replicator_qdss_out_tpiu: endpoint { + remote-endpoint= + <&tpiu_in_replicator_qdss>; + }; + }; + + port@2 { + reg = <0>; + replicator_qdss_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint= + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + }; + + replicator_swao: replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + + }; + }; + + tmc_etf: tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-csr = <&swao_csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint= + <&funnel_swao_out_tmc_etf>; + }; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_swao: funnel@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_swao>; + }; + }; + + port@1 { + reg = <6>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint = + <&tpda_swao_out_funnel_swao>; + }; + }; + port@2 { + reg = <7>; + funnel_swao_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_funnel_swao>; + }; + }; + }; + }; + + funnel_qdss_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qdss-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qdss_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qdss_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qdss_qatb_in_tpda_qdss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_qdss_out_funnel_qdss_qatb>; + }; + }; + }; + }; + + tpda_qdss: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-qdss"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <14 32>; + qcom,cmb-elem-size = <0 64>, + <12 32>, + <13 32>, + <14 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_out_funnel_qdss_qatb: endpoint { + remote-endpoint = + <&funnel_qdss_qatb_in_tpda_qdss>; + }; + + }; + + port@1 { + reg = <0>; + tpda_qdss_in_funnel_ddr_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr_qatb_out_tpda_qdss>; + }; + }; + + port@2 { + reg = <12>; + tpda_qdss_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda_qdss>; + }; + }; + + port@3 { + reg = <13>; + tpda_qdss_in_tpdm_dcc: endpoint { + slave-mode; + emote-endpoint = + <&tpdm_dcc_out_tpda_qdss>; + }; + }; + + port@4 { + reg = <14>; + tpda_qdss_in_tpdm_top: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_top_out_tpda_qdss>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>, + <0x7820f0 0x4>; + reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + swao_csr: csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qdss_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qdss_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <0>; + funnel_in1_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_in1>; + }; + }; + port@2 { + reg = <2>; + funnel_in1_in_funnel_modem_dl: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_dl_out_funnel_in1>; + }; + }; + }; + }; + + funnel_modem_dl: funnel@6804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem-dl"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_dl_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem_dl>; + }; + }; + port@1 { + reg = <0>; + funnel_modem_dl_in_tpda_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_out_funnel_modem_dl>; + }; + }; + port@2 { + reg = <1>; + funnel_modem_dl_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_modem_dl>; + }; + }; + }; + }; + + + funnel_ddr_qatb: funnel@69e2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x69e2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_qatb_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_funnel_ddr_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_ddr_qatb_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_qatb>; + }; + }; + }; + }; + + tpda_swao: tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + }; + + port@1 { + reg = <0>; + tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao0_out_tpda_swao>; + }; + }; + port@2 { + reg = <1>; + tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + }; + }; + }; + + tpda_modem: tpda@6803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_tpda_modem>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_in_tpdm_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@6800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_0_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_0>; + }; + }; + }; + + tpdm_swao0: tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_swao0_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao0>; + }; + }; + }; + + tpdm_swao1: tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + + tpdm_ddr: tpdm@69e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x069e0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_ddr_out_funnel_ddr_qatb: endpoint { + remote-endpoint = + <&funnel_ddr_qatb_in_tpdm_ddr>; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_vsense>; + }; + }; + }; + + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_dcc_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_dcc>; + }; + }; + }; + + + tpdm_top: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-top"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_top_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_top>; + }; + }; + }; + + etm0: etm@7002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b956>; + + reg = <0x7002000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_etm0>; + }; + }; + }; + + cti0_ddr0: cti@69e1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@69e4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@69e5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_ddr1: cti@69e6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e6000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@7003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7003000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti0_swao:cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao:cti@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b05000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_swao:cti@6b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b06000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao:cti@6b07000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b07000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + + dummy_tpiu: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpiu"; + + qcom,dummy-sink; + port { + tpiu_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tpiu>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_modem_etm0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index b0b69d11c6da..fb1dbfa40c1f 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -924,6 +924,7 @@ #include "sdxprairie-blsp.dtsi" #include "sdxprairie-audio.dtsi" #include "sdxprairie-pcie.dtsi" +#include "sdxprairie-coresight.dtsi" &gdsc_usb30 { status = "ok"; -- GitLab From c003a4b5e7337ee7bf22de5f07517dade6b11abc Mon Sep 17 00:00:00 2001 From: Sahil Chandna Date: Tue, 13 Nov 2018 16:43:19 +0530 Subject: [PATCH 1055/1286] ARM: dts: msm: Enable weighted capacity learning for 8150 platforms Enable weighted capacity learning for SM8150 MTP/QRD. This helps to learn capacity from any starting battery SOC and whenever battery SOC changes by at least 10 % during charging. Change-Id: I83d63068ff7357a25173b24be6a54b55de16daa5 Signed-off-by: Sahil Chandna --- arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index 467f8ef56689..1c8bdeca95db 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -306,6 +306,7 @@ qcom,hold-soc-while-full; qcom,linearize-soc; qcom,five-pin-battery; + qcom,cl-wt-enable; /* ESR fast calibration */ qcom,fg-esr-timer-chg-fast = <0 7>; qcom,fg-esr-timer-dischg-fast = <0 7>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi index 1447fcc9741f..78e540a0b1c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -50,6 +50,7 @@ qcom,hold-soc-while-full; qcom,linearize-soc; qcom,five-pin-battery; + qcom,cl-wt-enable; /* ESR fast calibration */ qcom,fg-esr-timer-chg-fast = <0 7>; qcom,fg-esr-timer-dischg-fast = <0 7>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi index c899349086c9..6e57ff0b5c07 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and or modify * it under the terms of the GNU General Public License version 2 and @@ -48,6 +48,7 @@ qcom,battery-data = <&fusion_qrd_batterydata>; qcom,hold-soc-while-full; qcom,linearize-soc; + qcom,cl-wt-enable; /* ESR fast calibration */ qcom,fg-esr-timer-chg-fast = <0 7>; qcom,fg-esr-timer-dischg-fast = <0 7>; -- GitLab From c4c67bbe4dbedfc3a1cb3215524b32803a5dee5c Mon Sep 17 00:00:00 2001 From: Shaoqing Liu Date: Fri, 18 Jan 2019 15:14:03 +0800 Subject: [PATCH 1056/1286] defconfig: sdxprairie: Enable coresight components Enable coresight components in config. Change-Id: Ice5491a69a34cf41cd0c25517dbd1d3590153bca Signed-off-by: Shaoqing Liu --- .../arm/configs/vendor/sdxprairie-perf_defconfig | 13 +++++++++++++ arch/arm/configs/vendor/sdxprairie_defconfig | 16 ++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 84123b0cbd01..db545d3002c0 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -382,6 +382,19 @@ CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y CONFIG_IPC_LOGGING=y # CONFIG_FTRACE is not set +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index a3c39935112c..73a39d2ffece 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -355,7 +355,6 @@ CONFIG_IIO=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y CONFIG_ANDROID=y -CONFIG_STM=y CONFIG_MSM_TZ_LOG=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y @@ -392,8 +391,21 @@ CONFIG_IPC_LOGGING=y CONFIG_QCOM_RTB=y # CONFIG_FTRACE is not set CONFIG_PANIC_ON_DATA_CORRUPTION=y -# CONFIG_STRICT_DEVMEM is not set CONFIG_DEBUG_USER=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y -- GitLab From f00c64217f32eaaaebb229faa0f0e9a29063ba25 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 9 Jan 2019 11:14:33 +0530 Subject: [PATCH 1057/1286] usb: XHCI: Bailout command abort operation upon XHCI remove As part of Command timeout handling command abort operation is performed. This requires to poll for command ring status for 5 second and a re-try for another 3 second. In case of XHCI removal this can cause watch dog timeout because polling is done with spin lock held. Fix this issue by adding xhci state check in xhci_handshake() API which bails out the polling upon XHCI removal. Change-Id: I2d4c4654cb8909a3a71002870f1f5946d60f7d8f Signed-off-by: Hemant Kumar Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/host/xhci-hub.c | 2 +- drivers/usb/host/xhci-ring.c | 2 +- drivers/usb/host/xhci.c | 22 +++++++++++++--------- drivers/usb/host/xhci.h | 3 ++- 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index a67137948740..0548981f445b 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -1856,7 +1856,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) /* poll for U0 link state complete, both USB2 and USB3 */ for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { - sret = xhci_handshake(port_array[port_index], PORT_PLC, + sret = xhci_handshake(xhci, port_array[port_index], PORT_PLC, PORT_PLC, 10 * 1000); if (sret) { xhci_warn(xhci, "port %d resume PLC timeout\n", diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 3f4337efb332..38097f0b6925 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -367,7 +367,7 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) * In the future we should distinguish between -ENODEV and -ETIMEDOUT * and try to recover a -ETIMEDOUT with a host controller reset. */ - ret = xhci_handshake(&xhci->op_regs->cmd_ring, + ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring, CMD_RING_RUNNING, 0, 5 * 1000 * 1000); if (ret < 0) { xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index e867a0a38a20..a849b5e8d250 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -76,7 +76,8 @@ static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring) * handshake done). There are two failure modes: "usec" have passed (major * hardware flakeout), or the register reads as all-ones (hardware removed). */ -int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) +int xhci_handshake(struct xhci_hcd *xhci, + void __iomem *ptr, u32 mask, u32 done, int usec) { u32 result; @@ -84,6 +85,9 @@ int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) result = readl(ptr); if (result == ~(u32)0) /* card removed */ return -ENODEV; + /* host removed. Bail out */ + if (xhci->xhc_state & XHCI_STATE_REMOVING) + return -ENODEV; result &= mask; if (result == done) return 0; @@ -126,7 +130,7 @@ int xhci_halt(struct xhci_hcd *xhci) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); xhci_quiesce(xhci); - ret = xhci_handshake(&xhci->op_regs->status, + ret = xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); if (ret) { xhci_warn(xhci, "Host halt failed, %d\n", ret); @@ -161,7 +165,7 @@ int xhci_start(struct xhci_hcd *xhci) * Wait for the HCHalted Status bit to be 0 to indicate the host is * running. */ - ret = xhci_handshake(&xhci->op_regs->status, + ret = xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, 0, XHCI_MAX_HALT_USEC); if (ret == -ETIMEDOUT) xhci_err(xhci, "Host took too long to start, " @@ -216,7 +220,7 @@ int xhci_reset(struct xhci_hcd *xhci) if (xhci->quirks & XHCI_INTEL_HOST) udelay(1000); - ret = xhci_handshake(&xhci->op_regs->command, + ret = xhci_handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 10 * 1000 * 1000); if (ret) return ret; @@ -230,7 +234,7 @@ int xhci_reset(struct xhci_hcd *xhci) * xHCI cannot write to any doorbells or operational registers other * than status until the "Controller Not Ready" flag is cleared. */ - ret = xhci_handshake(&xhci->op_regs->status, + ret = xhci_handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 10 * 1000 * 1000); for (i = 0; i < 2; i++) { @@ -960,7 +964,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) /* Some chips from Fresco Logic need an extraordinary delay */ delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; - if (xhci_handshake(&xhci->op_regs->status, + if (xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, STS_HALT, delay)) { xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); spin_unlock_irq(&xhci->lock); @@ -975,7 +979,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) command = readl(&xhci->op_regs->command); command |= CMD_CSS; writel(command, &xhci->op_regs->command); - if (xhci_handshake(&xhci->op_regs->status, + if (xhci_handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10 * 1000)) { xhci_warn(xhci, "WARN: xHC save state timeout\n"); spin_unlock_irq(&xhci->lock); @@ -1050,7 +1054,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) * restore so setting the timeout to 100ms. Xhci specification * doesn't mention any timeout value. */ - if (xhci_handshake(&xhci->op_regs->status, + if (xhci_handshake(xhci, &xhci->op_regs->status, STS_RESTORE, 0, 100 * 1000)) { xhci_warn(xhci, "WARN: xHC restore state timeout\n"); spin_unlock_irq(&xhci->lock); @@ -1121,7 +1125,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) command = readl(&xhci->op_regs->command); command |= CMD_RUN; writel(command, &xhci->op_regs->command); - xhci_handshake(&xhci->op_regs->status, STS_HALT, + xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, 0, 250 * 1000); /* step 5: walk topology and initialize portsc, diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index d7107386ea0f..1ecd419beab6 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -2023,7 +2023,8 @@ int xhci_sec_event_ring_cleanup(struct usb_hcd *hcd, unsigned int intr_num); /* xHCI host controller glue */ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); -int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); +int xhci_handshake(struct xhci_hcd *xhci, + void __iomem *ptr, u32 mask, u32 done, int usec); void xhci_quiesce(struct xhci_hcd *xhci); int xhci_halt(struct xhci_hcd *xhci); int xhci_start(struct xhci_hcd *xhci); -- GitLab From 8dbac5527f3ff5e921b96b5eb38182ba442b12b7 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Mon, 12 Mar 2018 12:38:06 -0700 Subject: [PATCH 1058/1286] usb: xhci: Reduce command abort handshake timeout Once command completion times out (5 sec), command abort operation is currently perfomed with local irq disabled and spinlock held for 5 sec timeout. In case xHC becomes unresponsive for some reason this results into watchdog bark. Hence reduce timeout value from 5 sec to 1 sec to initiate recovery faster. Change-Id: I1383721ce1d25bc40fb0e7620135fafcba6d5640 Signed-off-by: Hemant Kumar Signed-off-by: Jack Pham Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/host/xhci-ring.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 38097f0b6925..815a590faf9c 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -362,13 +362,13 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) &xhci->op_regs->cmd_ring); /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the - * completion of the Command Abort operation. If CRR is not negated in 5 - * seconds then driver handles it as if host died (-ENODEV). + * completion of the Command Abort operation. If CRR is not negated in a + * timely manner then driver handles it as if host died (-ENODEV). * In the future we should distinguish between -ENODEV and -ETIMEDOUT * and try to recover a -ETIMEDOUT with a host controller reset. */ ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring, - CMD_RING_RUNNING, 0, 5 * 1000 * 1000); + CMD_RING_RUNNING, 0, 1000 * 1000); if (ret < 0) { xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); xhci_halt(xhci); -- GitLab From d05b3b8a33fdbb1bd8fe479c65998e762acb4496 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 17 May 2018 13:04:17 -0700 Subject: [PATCH 1059/1286] fs/proc: re-factor proc_pid_cmdline_read() a bit This is a pure refactoring of the function, preparing for some further cleanups. The thing was pretty illegible, and the core functionality still is, but now the core loop is a bit more isolated from the thing that goes on around it. This was "inspired" by the confluence of kworker workqueue name cleanups by Tejun, currently scheduled for 4.18, and commit 7f7ccc2ccc2e ("proc: do not access cmdline nor environ from file-backed areas"). Change-Id: Ia50851c44fce78de4eb4e6f7b2ef5b91cdda74c1 Signed-off-by: Linus Torvalds Git-commit: e4b4e441323b7988a344f88d7ee3f8fcb17db048 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Prateek Sood --- fs/proc/base.c | 64 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 25 deletions(-) diff --git a/fs/proc/base.c b/fs/proc/base.c index cf4ff3e81bf5..64501ad7b1f3 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -208,11 +208,9 @@ static int proc_root_link(struct dentry *dentry, struct path *path) return result; } -static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, - size_t _count, loff_t *pos) +static ssize_t get_mm_cmdline(struct mm_struct *mm, char __user *buf, + size_t _count, loff_t *pos) { - struct task_struct *tsk; - struct mm_struct *mm; char *page; unsigned long count = _count; unsigned long arg_start, arg_end, env_start, env_end; @@ -221,26 +219,13 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, char c; ssize_t rv; - BUG_ON(*pos < 0); - - tsk = get_proc_task(file_inode(file)); - if (!tsk) - return -ESRCH; - mm = get_task_mm(tsk); - put_task_struct(tsk); - if (!mm) - return 0; /* Check if process spawned far enough to have cmdline. */ - if (!mm->env_end) { - rv = 0; - goto out_mmput; - } + if (!mm->env_end) + return 0; page = (char *)__get_free_page(GFP_KERNEL); - if (!page) { - rv = -ENOMEM; - goto out_mmput; - } + if (!page) + return -ENOMEM; down_read(&mm->mmap_sem); arg_start = mm->arg_start; @@ -368,13 +353,42 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, out_free_page: free_page((unsigned long)page); -out_mmput: - mmput(mm); - if (rv > 0) - *pos += rv; return rv; } +static ssize_t get_task_cmdline(struct task_struct *tsk, char __user *buf, + size_t count, loff_t *pos) +{ + struct mm_struct *mm; + ssize_t ret; + + mm = get_task_mm(tsk); + if (!mm) + return 0; + + ret = get_mm_cmdline(mm, buf, count, pos); + mmput(mm); + return ret; +} + +static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + struct task_struct *tsk; + ssize_t ret; + + BUG_ON(*pos < 0); + + tsk = get_proc_task(file_inode(file)); + if (!tsk) + return -ESRCH; + ret = get_task_cmdline(tsk, buf, count, pos); + put_task_struct(tsk); + if (ret > 0) + *pos += ret; + return ret; +} + static const struct file_operations proc_pid_cmdline_ops = { .read = proc_pid_cmdline_read, .llseek = generic_file_llseek, -- GitLab From acc3265772b44f1525baa30d49da568fdf774d1c Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Wed, 23 Jan 2019 12:14:11 +0530 Subject: [PATCH 1060/1286] ARM: dts: msm: enable partial update for td4330 truly panel on TRINKET Add support for partial update for td4330 truly panel on TRINKET. With this change power optimization can be achieved during partial update scenarios. Change-Id: I3e1bfef0a3ba24e70c8966d25ad1e5a36ee81ae2 Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi index 537e78fc5d4a..d7e7beabde25 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi @@ -168,6 +168,8 @@ qcom,display-topology = <1 0 1>; qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <16 16 8 2 16 16>; }; }; }; -- GitLab From 300bc40c97a8b66e498294ecdc8fa52fff035690 Mon Sep 17 00:00:00 2001 From: Kai Liu Date: Wed, 23 Jan 2019 08:57:01 +0800 Subject: [PATCH 1061/1286] cnss2: Fix implicit conversion compile warning Add type cast enum wlfw_driver_mode_enum_v01 for cnss_driver_mode to fix implicit conversion compile warning Change-Id: I16938f84ef6989f0adb81f25a3b3a068ad764c28 Signed-off-by: Kai Liu --- drivers/net/wireless/cnss2/qmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/cnss2/qmi.c b/drivers/net/wireless/cnss2/qmi.c index f93d59f71882..0bc3530801bb 100644 --- a/drivers/net/wireless/cnss2/qmi.c +++ b/drivers/net/wireless/cnss2/qmi.c @@ -660,7 +660,7 @@ int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv, return -ENOMEM; } - req->mode = mode; + req->mode = (enum wlfw_driver_mode_enum_v01)mode; req->hw_debug_valid = 1; req->hw_debug = 0; -- GitLab From 8572cf8343a7c498fb035c413b75fcb2fb9c6174 Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Fri, 18 Jan 2019 14:40:48 +0530 Subject: [PATCH 1062/1286] ARM: dts: msm: Update in master id for crypto devices for trinket Update in master id for qcedev and qcrypto device node to enable HW crypto CE operations. Change-Id: Iafe674797a338261de52487e72b8c1d9e0b6fe32 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 19d4b20e2e59..c54951ccc816 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1903,8 +1903,8 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; + <55 512 0 0>, + <55 512 393600 393600>; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x01A6 0x0011>, @@ -1927,8 +1927,8 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; + <55 512 0 0>, + <55 512 393600 393600>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; -- GitLab From 94671952295f0d50729d26b5005f5862302a0779 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 14 Dec 2018 11:10:41 +0800 Subject: [PATCH 1063/1286] ARM: dts: msm: Add td4330 panel video mode support for QRD Add the dtsi nodes to enable td4330 panel on trinket QRD platform. Change-Id: Ie19efea9a525abdbfc9bc4fd819ac1f1aa7b0d8d Signed-off-by: Lei Chen --- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 51b4af6cfac3..f848d8807de0 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include "trinket-sde-display.dtsi" +#include &qupv3_se1_i2c { status = "ok"; @@ -224,3 +226,32 @@ &usb0 { extcon = <&pmi632_charger>, <&eud>; }; + +&dsi_td4330_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + pwms = <&pm6125_pwm 0 0>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 89 0>; + qcom,platform-reset-gpio = <&tlmm 90 0>; +}; + +&dsi_td4330_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + pwms = <&pm6125_pwm 0 0>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 90 0>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm6125_pwm { + status = "ok"; +}; -- GitLab From 3c3f5489c348c688544783261d7f5ca254bb2156 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 10 Aug 2018 13:53:52 -0700 Subject: [PATCH 1064/1286] msm: ep_pcie: update pcie parameters PCIe EP global interrupt may or may not be wake-up capable as per design. Remove error condition in case interrupt is not wake-up capable. Update pcie parameters. Change-Id: If67bac204f3f126b3e23c379340985ce870ee6c4 Signed-off-by: Tony Truong Signed-off-by: Rama Krishna Phani A --- .../devicetree/bindings/pci/msm_ep_pcie.txt | 18 ++++---- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 4 +- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 44 +++++++++---------- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt index faf56c2cdb3d..3e265a1ea80d 100644 --- a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt @@ -33,10 +33,10 @@ Optional Properties: - qcom,-voltage-level: specifies voltage levels for supply. Should be specified in pairs (max, min, optimal), units uV. - clock-names: list of names of clock inputs. - Should be "pcie_0_pipe_clk", - "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", - "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", - "pcie_0_ldo"; + Should be "pcie_pipe_clk", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_ldo"; - max-clock-frequency-hz: list of the maximum operating frequencies stored in the same order of clock names; - resets: reset specifier pair consists of phandle for the reset controller @@ -105,17 +105,17 @@ Example: qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>; qcom,vreg-0.9-voltage-level = <950000 950000 24000>; - clock-names = "pcie_0_pipe_clk", - "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", - "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", - "pcie_0_ldo"; + clock-names = "pcie_pipe_clk", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_ldo"; max-clock-frequency-hz = <62500000>, <1000000>, <0>, <0>, <0>, <0>; resets = <&clock_gcc GCC_PCIE_BCR>, <&clock_gcc GCC_PCIE_PHY_BCR>; - reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; + reset-names = "pcie_core_reset", "pcie_phy_reset"; qcom,msm-bus,name = "pcie-ep"; qcom,msm-bus,num-cases = <2>; diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index 36d49e4eb4d3..9a5877e583c5 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -154,7 +154,7 @@ #define MAX_IATU_ENTRY_NUM 2 #define EP_PCIE_LOG_PAGES 50 -#define EP_PCIE_MAX_VREG 2 +#define EP_PCIE_MAX_VREG 3 #define EP_PCIE_MAX_CLK 7 #define EP_PCIE_MAX_PIPE_CLK 1 #define EP_PCIE_MAX_RESET 2 diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index a676f4e8b32f..3a9e16816ac3 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -52,6 +52,7 @@ struct ep_pcie_dev_t ep_pcie_dev = {0}; static struct ep_pcie_vreg_info_t ep_pcie_vreg_info[EP_PCIE_MAX_VREG] = { {NULL, "vreg-1.8", 1800000, 1800000, 14000, true}, {NULL, "vreg-0.9", 1000000, 1000000, 40000, true}, + {NULL, "vreg-cx", 0, 0, 0, false} }; static struct ep_pcie_gpio_info_t ep_pcie_gpio_info[EP_PCIE_MAX_GPIO] = { @@ -63,24 +64,24 @@ static struct ep_pcie_gpio_info_t ep_pcie_gpio_info[EP_PCIE_MAX_GPIO] = { static struct ep_pcie_clk_info_t ep_pcie_clk_info[EP_PCIE_MAX_CLK] = { - {NULL, "pcie_0_cfg_ahb_clk", 0, true}, - {NULL, "pcie_0_mstr_axi_clk", 0, true}, - {NULL, "pcie_0_slv_axi_clk", 0, true}, - {NULL, "pcie_0_aux_clk", 1000000, true}, - {NULL, "pcie_0_ldo", 0, true}, - {NULL, "pcie_0_sleep_clk", 0, false}, - {NULL, "pcie_0_slv_q2a_axi_clk", 0, false}, + {NULL, "pcie_cfg_ahb_clk", 0, true}, + {NULL, "pcie_mstr_axi_clk", 0, true}, + {NULL, "pcie_slv_axi_clk", 0, true}, + {NULL, "pcie_aux_clk", 1000000, true}, + {NULL, "pcie_ldo", 0, true}, + {NULL, "pcie_sleep_clk", 0, false}, + {NULL, "pcie_slv_q2a_axi_clk", 0, false}, }; static struct ep_pcie_clk_info_t ep_pcie_pipe_clk_info[EP_PCIE_MAX_PIPE_CLK] = { - {NULL, "pcie_0_pipe_clk", 62500000, true}, + {NULL, "pcie_pipe_clk", 62500000, true}, }; static struct ep_pcie_reset_info_t ep_pcie_reset_info[EP_PCIE_MAX_RESET] = { - {NULL, "pcie_0_core_reset", false}, - {NULL, "pcie_0_phy_reset", false}, + {NULL, "pcie_core_reset", false}, + {NULL, "pcie_phy_reset", false}, }; static const struct ep_pcie_res_info_t ep_pcie_res_info[EP_PCIE_MAX_RES] = { @@ -1280,15 +1281,6 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) goto clk_fail; } - /* enable pipe clock */ - ret = ep_pcie_pipe_clk_init(dev); - if (ret) { - EP_PCIE_ERR(dev, - "PCIe V%d: failed to enable pipe clock\n", - dev->rev); - goto pipe_clk_fail; - } - dev->power_on = true; } @@ -1381,7 +1373,16 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) /* init PCIe PHY */ ep_pcie_phy_init(dev); - EP_PCIE_DBG(dev, "PCIe V%d: waiting for phy ready\n", dev->rev); + /* enable pipe clock */ + ret = ep_pcie_pipe_clk_init(dev); + if (ret) { + EP_PCIE_ERR(dev, + "PCIe V%d: failed to enable pipe clock\n", + dev->rev); + goto pipe_clk_fail; + } + + EP_PCIE_DBG(dev, "PCIe V%d: waiting for phy ready...\n", dev->rev); retries = 0; do { if (ep_pcie_phy_is_ready(dev)) @@ -1966,7 +1967,6 @@ int32_t ep_pcie_irq_init(struct ep_pcie_dev_t *dev) EP_PCIE_ERR(dev, "PCIe V%d: Unable to enable wake for Global interrupt\n", dev->rev); - return ret; } EP_PCIE_DBG(dev, -- GitLab From ef81ba295eabfccd9d7f40888fed5313cba20201 Mon Sep 17 00:00:00 2001 From: Manikanta Kanamarlapudi Date: Sun, 20 Jan 2019 23:39:23 +0530 Subject: [PATCH 1065/1286] ARM: dts: msm: Update correct irq for venus in trinket Correct irq for venus in trinket. CRs-Fixed: 2384061 Change-Id: I003ba896f0cad8c2482b2f5ec44cb4593030c57d Signed-off-by: Manikanta Kanamarlapudi --- arch/arm64/boot/dts/qcom/trinket-vidc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-vidc.dtsi b/arch/arm64/boot/dts/qcom/trinket-vidc.dtsi index 11e3b52613a1..7b159b3f80e4 100644 --- a/arch/arm64/boot/dts/qcom/trinket-vidc.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-vidc.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,7 +19,7 @@ compatible = "qcom,msm-vidc", "qcom,trinket-vidc"; status = "ok"; reg = <0x5a00000 0x200000>; - interrupts = ; + interrupts = ; /* Supply */ venus-supply = <&venus_gdsc>; -- GitLab From 9314110ad4bc90b6ab1df04be966e824b60aff53 Mon Sep 17 00:00:00 2001 From: Mohammed Javid Date: Wed, 9 Jan 2019 23:14:43 +0530 Subject: [PATCH 1066/1286] ipa: Fix to MHI channel state update Make a change to use the right channel state size when updating the state info to avoid overwriting other fields in the MHI context. Change-Id: Ic0483dedaacfd3d74452f561b4e25953a1e24fb0 Acked-by: Chaitanya Pratapa Signed-off-by: Mohammed Javid --- drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c index bc55db746dd7..29f0c87fdb91 100644 --- a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +++ b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, 2017-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2015, 2017-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1607,7 +1607,7 @@ int ipa_mhi_connect_pipe(struct ipa_mhi_connect_params *in, u32 *clnt_hdl) res = ipa_mhi_read_write_host(IPA_MHI_DMA_TO_HOST, &channel->state, channel->channel_context_addr + offsetof(struct ipa_mhi_ch_ctx, chstate), - sizeof(channel->state)); + sizeof(((struct ipa_mhi_ch_ctx *)0)->chstate)); if (res) { IPA_MHI_ERR("ipa_mhi_read_write_host failed\n"); return res; -- GitLab From be8cc119dd5a9359b37211d23525d3aeb72d07df Mon Sep 17 00:00:00 2001 From: Shubhashree Dhar Date: Mon, 21 Jan 2019 11:33:44 +0530 Subject: [PATCH 1067/1286] ARM: dts: msm: update reg bus id and enable rotator for TRINKET target Update reg bus id and enable rotator for trinket target. Change-Id: I2093a13b8f220d621e7b81aad1a4b3aec2507e91 Signed-off-by: Shubhashree Dhar --- arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi index 3569a84cdaeb..f7eb8c89e73c 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -236,18 +236,19 @@ qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; + <1 700 0 0>, + <1 700 0 76800>, + <1 700 0 150000>, + <1 700 0 300000>; }; }; mdss_rotator: qcom,mdss_rotator@5e00000 { compatible = "qcom,sde_rotator"; - reg = <0x5e00000 0xac000>; - reg-names = "mdp_phys"; - status = "disabled"; + reg = <0x5e00000 0xac000>, + <0x5eb0000 0x2008>; + reg-names = "mdp_phys", + "rot_vbif_phys"; #list-cells = <1>; @@ -295,8 +296,8 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>; + <1 700 0 0>, + <1 700 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { -- GitLab From 6654725c2a636430bb330561234f83d9d1587c48 Mon Sep 17 00:00:00 2001 From: Tanya Dixit Date: Wed, 23 Jan 2019 19:09:02 +0530 Subject: [PATCH 1068/1286] ARM: dts: msm: USB Type C changes for trinket Add support for USB Type C variant on trinket. Change-Id: Id0fdcf8984986014e8150d4977d1c60ac019b8a4 Signed-off-by: Tanya Dixit --- .../boot/dts/qcom/trinket-usbc-idp-overlay.dts | 1 + arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts | 1 + arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi | 17 +++++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts index 6fc501c8e333..4746bff9fdf2 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts @@ -16,6 +16,7 @@ #include #include "trinket-idp.dtsi" +#include "trinket-usbc-idp.dtsi" / { model = "USBC Audio IDP"; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts index 8f1fc5827f06..22adfd297b2f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dts @@ -14,6 +14,7 @@ #include "trinket.dtsi" #include "trinket-idp.dtsi" +#include "trinket-usbc-idp.dtsi" / { model = "Qualcomm Technologies, Inc. Trinket USBC Audio IDP"; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi new file mode 100644 index 000000000000..574908e27456 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi @@ -0,0 +1,17 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "trinket-audio-overlay.dtsi" + +&sm6150_snd { + qcom,msm-mbhc-usbc-audio-supported = <1>; +}; -- GitLab From c4d2facb04065d13a6d8ac1df273862a0922647d Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Thu, 17 Jan 2019 08:54:57 +0530 Subject: [PATCH 1069/1286] coresight: tgu: Fix issue which is unable to enable/disbale tgu pm_runtime_get_sync can return positive. Correct the check of it. And remove the extra spin_unlock in enable_tgu which will cause issue when disable tgu. Change-Id: Ic8b46d1da7cbfe06b3e58e34bd1e62cea31ac8bf Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tgu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tgu.c b/drivers/hwtracing/coresight/coresight-tgu.c index e919f475a02e..607bc60f4b0e 100644 --- a/drivers/hwtracing/coresight/coresight-tgu.c +++ b/drivers/hwtracing/coresight/coresight-tgu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -123,8 +123,10 @@ static ssize_t enable_tgu(struct device *dev, /* Enable clock */ ret = pm_runtime_get_sync(drvdata->dev); - if (ret) + if (ret < 0) { + pm_runtime_put(drvdata->dev); return ret; + } spin_lock(&drvdata->spinlock); /* Unlock the TGU LAR */ @@ -176,7 +178,6 @@ static ssize_t enable_tgu(struct device *dev, /* Disable TGU to program the triggers */ tgu_writel(drvdata, 0, TGU_CONTROL); TGU_LOCK(drvdata); - spin_unlock(&drvdata->spinlock); pm_runtime_put(drvdata->dev); dev_dbg(dev, "Coresight-TGU disabled\n"); @@ -202,8 +203,10 @@ static ssize_t reset_tgu(struct device *dev, if (!drvdata->enable) { /* Enable clock */ ret = pm_runtime_get_sync(drvdata->dev); - if (ret) + if (ret < 0) { + pm_runtime_put(drvdata->dev); return ret; + } } spin_lock(&drvdata->spinlock); -- GitLab From 17a75e26a8f3389c73fd942898bbe0e1efb1102b Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 23 Jan 2019 21:53:15 +0530 Subject: [PATCH 1070/1286] ARM: dts: msm: Correct thermistor names on PM6125 for trinket Correct names of emmc_therm and camera_flash_therm on PM6125 for trinket. Change-Id: I0cf5b8c157ea8ed0f17bda8230838688ffd39fe7 Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/trinket.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 71e9099dd0fc..a870c53b19c1 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -158,14 +158,14 @@ }; }; - emmc-ufs-therm-adc { + camera-ftherm-adc { polling-delay-passive = <0>; polling-delay = <5000>; thermal-governor = "user_space"; thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO1_PU2>; }; - camera-ftherm-adc { + emmc-ufs-therm-adc { polling-delay-passive = <0>; polling-delay = <5000>; thermal-governor = "user_space"; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 644c0e5756c0..08d5eb3b8ba4 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2405,13 +2405,13 @@ io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, <&pm6125_vadc ADC_GPIO3_PU2>; - emmc_ufs_therm { + camera_flash_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - camera_flash_therm { + emmc_ufs_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; -- GitLab From 5c8665cc3fc2a5554a848d8cdaa7773de8951e25 Mon Sep 17 00:00:00 2001 From: Tanya Dixit Date: Wed, 23 Jan 2019 20:11:16 +0530 Subject: [PATCH 1071/1286] ARM: dts: msm: Remove vote for L15 in trinket No need to vote for L15 for micbias as it is connected to Vph. Change-Id: I4b55b5c231848a751887c52370be35fe7f8b6648 Signed-off-by: Tanya Dixit --- arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi index 9dd9b78f0d0d..0ba63ab04d33 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -170,17 +170,12 @@ qcom,cdc-vdd-buck-voltage = <1800000 1800000>; qcom,cdc-vdd-buck-current = <650000>; - cdc-vdd-mic-bias-supply = <&L15A>; - qcom,cdc-vdd-mic-bias-voltage = <3104000 3104000>; - qcom,cdc-vdd-mic-bias-current = <25000>; - qcom,cdc-micbias1-mv = <1800>; qcom,cdc-micbias2-mv = <1800>; qcom,cdc-micbias3-mv = <1800>; qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx", - "cdc-vddpx-1", - "cdc-vdd-mic-bias"; + "cdc-vddpx-1"; qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; }; }; -- GitLab From 5d1d6b1f341e2f7d4a6b2b2555f47cb152939164 Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Mon, 5 Nov 2018 10:23:27 -0700 Subject: [PATCH 1072/1286] net: qualcomm: rmnet: Add QMAPv5 header definitions Adds definitions for new QMAPv5 checksum offload and coalescing headers, as well as changing the main QMAP header definition to support these additional headers. Change-Id: I62fdf6d8d35e8788b089156703fdf3a1d6367e5b Acked-by: Ryan Chapman Signed-off-by: Sean Tranchetti --- .../net/ethernet/qualcomm/rmnet/rmnet_map.h | 64 ++++++++++++++++++- include/uapi/linux/if_link.h | 3 + 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h index 3e8ae2df216d..710fa87be50e 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,6 +12,8 @@ #ifndef _RMNET_MAP_H_ #define _RMNET_MAP_H_ + +#include #include "rmnet_config.h" struct rmnet_map_control_command { @@ -42,14 +44,72 @@ enum rmnet_map_commands { RMNET_MAP_COMMAND_ENUM_LENGTH }; +enum rmnet_map_v5_header_type { + RMNET_MAP_HEADER_TYPE_UNKNOWN, + RMNET_MAP_HEADER_TYPE_COALESCING = 0x1, + RMNET_MAP_HEADER_TYPE_CSUM_OFFLOAD = 0x2, + RMNET_MAP_HEADER_TYPE_ENUM_LENGTH +}; + +enum rmnet_map_v5_close_type { + RMNET_MAP_COAL_CLOSE_NON_COAL, + RMNET_MAP_COAL_CLOSE_IP_MISS, + RMNET_MAP_COAL_CLOSE_TRANS_MISS, + RMNET_MAP_COAL_CLOSE_HW, + RMNET_MAP_COAL_CLOSE_COAL, +}; + +enum rmnet_map_v5_close_value { + RMNET_MAP_COAL_CLOSE_HW_NL, + RMNET_MAP_COAL_CLOSE_HW_PKT, + RMNET_MAP_COAL_CLOSE_HW_BYTE, + RMNET_MAP_COAL_CLOSE_HW_TIME, + RMNET_MAP_COAL_CLOSE_HW_EVICT, +}; + +/* Main QMAP header */ struct rmnet_map_header { u8 pad_len:6; - u8 reserved_bit:1; + u8 next_hdr:1; u8 cd_bit:1; u8 mux_id; __be16 pkt_len; } __aligned(1); +/* QMAP v5 headers */ +struct rmnet_map_v5_csum_header { + u8 next_hdr:1; + u8 header_type:7; + u8 hw_reserved:7; + u8 csum_valid_required:1; + __be16 reserved; +} __aligned(1); + +struct rmnet_map_v5_nl_pair { + __be16 pkt_len; + u8 csum_error_bitmap; + u8 num_packets; +} __aligned(1); + +/* NLO: Number-length object */ +#define RMNET_MAP_V5_MAX_NLOS (6) +#define RMNET_MAP_V5_MAX_PACKETS (48) + +struct rmnet_map_v5_coal_header { + u8 next_hdr:1; + u8 header_type:7; + u8 reserved1:4; + u8 num_nlos:3; + u8 csum_valid:1; + u8 close_type:4; + u8 close_value:4; + u8 reserved2:4; + u8 virtual_channel_id:4; + + struct rmnet_map_v5_nl_pair nl_pairs[RMNET_MAP_V5_MAX_NLOS]; +} __aligned(1); + +/* QMAP v4 headers */ struct rmnet_map_dl_csum_trailer { u8 reserved1; u8 valid:1; diff --git a/include/uapi/linux/if_link.h b/include/uapi/linux/if_link.h index 304e641d8314..aa2b90d1a58c 100644 --- a/include/uapi/linux/if_link.h +++ b/include/uapi/linux/if_link.h @@ -934,6 +934,9 @@ enum { #define RMNET_FLAGS_INGRESS_MAP_COMMANDS (1U << 1) #define RMNET_FLAGS_INGRESS_MAP_CKSUMV4 (1U << 2) #define RMNET_FLAGS_EGRESS_MAP_CKSUMV4 (1U << 3) +#define RMNET_FLAGS_INGRESS_COALESCE (1U << 4) +#define RMNET_FLAGS_INGRESS_MAP_CKSUMV5 (1U << 5) +#define RMNET_FLAGS_EGRESS_MAP_CKSUMV5 (1U << 6) enum { IFLA_RMNET_UNSPEC, -- GitLab From ac04ce05710f7c2e22d18b1e31f06bb677ceaa38 Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Mon, 5 Nov 2018 12:03:43 -0700 Subject: [PATCH 1073/1286] net: qualcomm: rmnet: Add support for QMAPv5 checksum offload Hardware can now perform full checksum validation for IP packets. As such, we can simply mark all incoming SKBs as CHECKSUM_UNNECESSARY if they pass validation in the new QMAPv5 format. Outgoing SKBs will now have a new checksum offload header added as well to request offload from the lower level drivers. Change-Id: I39636e83de6a96c4c06d48b885bef037817e9379 Signed-off-by: Sean Tranchetti --- .../ethernet/qualcomm/rmnet/rmnet_handlers.c | 25 +++- .../net/ethernet/qualcomm/rmnet/rmnet_map.h | 20 +++- .../ethernet/qualcomm/rmnet/rmnet_map_data.c | 109 +++++++++++++++++- 3 files changed, 141 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c index 07e57262f4be..995510402ba7 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_handlers.c @@ -227,8 +227,15 @@ __rmnet_map_ingress_handler(struct sk_buff *skb, skb->dev = ep->egress_dev; - /* Subtract MAP header */ - pskb_pull(skb, sizeof(struct rmnet_map_header)); + /* Handle QMAPv5 packet */ + if (qmap->next_hdr) { + if (rmnet_map_process_next_hdr_packet(skb)) + goto free_skb; + } else { + /* We only have the main QMAP header to worry about */ + pskb_pull(skb, sizeof(*qmap)); + } + rmnet_set_skb_proto(skb); if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) { @@ -299,17 +306,23 @@ static int rmnet_map_egress_handler(struct sk_buff *skb, struct rmnet_port *port, u8 mux_id, struct net_device *orig_dev) { - int required_headroom, additional_header_len; + int required_headroom, additional_header_len, csum_type; struct rmnet_map_header *map_header; additional_header_len = 0; required_headroom = sizeof(struct rmnet_map_header); + csum_type = 0; if (port->data_format & RMNET_FLAGS_EGRESS_MAP_CKSUMV4) { additional_header_len = sizeof(struct rmnet_map_ul_csum_header); - required_headroom += additional_header_len; + csum_type = RMNET_FLAGS_EGRESS_MAP_CKSUMV4; + } else if (port->data_format & RMNET_FLAGS_EGRESS_MAP_CKSUMV5) { + additional_header_len = sizeof(struct rmnet_map_v5_csum_header); + csum_type = RMNET_FLAGS_EGRESS_MAP_CKSUMV5; } + required_headroom += additional_header_len; + if (skb_headroom(skb) < required_headroom) { if (pskb_expand_head(skb, required_headroom, 0, GFP_ATOMIC)) return -ENOMEM; @@ -318,8 +331,8 @@ static int rmnet_map_egress_handler(struct sk_buff *skb, if (port->data_format & RMNET_INGRESS_FORMAT_PS) qmi_rmnet_work_maybe_restart(port); - if (port->data_format & RMNET_FLAGS_EGRESS_MAP_CKSUMV4) - rmnet_map_checksum_uplink_packet(skb, orig_dev); + if (csum_type) + rmnet_map_checksum_uplink_packet(skb, orig_dev, csum_type); map_header = rmnet_map_add_map_header(skb, additional_header_len, 0); if (!map_header) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h index 710fa87be50e..3f1e78aad9b0 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map.h @@ -222,6 +222,22 @@ rmnet_map_get_cmd_start(struct sk_buff *skb) return (struct rmnet_map_control_command *)data; } +static inline u8 rmnet_map_get_next_hdr_type(struct sk_buff *skb) +{ + unsigned char *data = rmnet_map_data_ptr(skb); + + data += sizeof(struct rmnet_map_header); + return ((struct rmnet_map_v5_coal_header *)data)->header_type; +} + +static inline bool rmnet_map_get_csum_valid(struct sk_buff *skb) +{ + unsigned char *data = rmnet_map_data_ptr(skb); + + data += sizeof(struct rmnet_map_header); + return ((struct rmnet_map_v5_csum_header *)data)->csum_valid_required; +} + struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, struct rmnet_port *port); struct rmnet_map_header *rmnet_map_add_map_header(struct sk_buff *skb, @@ -229,7 +245,9 @@ struct rmnet_map_header *rmnet_map_add_map_header(struct sk_buff *skb, void rmnet_map_command(struct sk_buff *skb, struct rmnet_port *port); int rmnet_map_checksum_downlink_packet(struct sk_buff *skb, u16 len); void rmnet_map_checksum_uplink_packet(struct sk_buff *skb, - struct net_device *orig_dev); + struct net_device *orig_dev, + int csum_type); +int rmnet_map_process_next_hdr_packet(struct sk_buff *skb); int rmnet_map_tx_agg_skip(struct sk_buff *skb, int offset); void rmnet_map_tx_aggregate(struct sk_buff *skb, struct rmnet_port *port); void rmnet_map_tx_aggregate_init(struct rmnet_port *port); diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c index 1229a542571f..6149b34b9005 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_data.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -277,6 +277,7 @@ struct rmnet_map_header *rmnet_map_add_map_header(struct sk_buff *skb, int hdrlen, int pad) { struct rmnet_map_header *map_header; + struct rmnet_port *port = rmnet_get_port(skb->dev); u32 padding, map_datalen; u8 *padbytes; @@ -285,6 +286,10 @@ struct rmnet_map_header *rmnet_map_add_map_header(struct sk_buff *skb, skb_push(skb, sizeof(struct rmnet_map_header)); memset(map_header, 0, sizeof(struct rmnet_map_header)); + /* Set next_hdr bit for csum offload packets */ + if (port->data_format & RMNET_FLAGS_EGRESS_MAP_CKSUMV5) + map_header->next_hdr = 1; + if (pad == RMNET_MAP_NO_PAD_BYTES) { map_header->pkt_len = htons(map_datalen); return map_header; @@ -330,6 +335,8 @@ struct sk_buff *rmnet_map_deaggregate(struct sk_buff *skb, if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV4) packet_len += sizeof(struct rmnet_map_dl_csum_trailer); + else if (port->data_format & RMNET_FLAGS_INGRESS_MAP_CKSUMV5) + packet_len += sizeof(struct rmnet_map_v5_csum_header); if (((int)skb->len - (int)packet_len) < 0) return NULL; @@ -408,11 +415,8 @@ int rmnet_map_checksum_downlink_packet(struct sk_buff *skb, u16 len) } EXPORT_SYMBOL(rmnet_map_checksum_downlink_packet); -/* Generates UL checksum meta info header for IPv4 and IPv6 over TCP and UDP - * packets that are supported for UL checksum offload. - */ -void rmnet_map_checksum_uplink_packet(struct sk_buff *skb, - struct net_device *orig_dev) +void rmnet_map_v4_checksum_uplink_packet(struct sk_buff *skb, + struct net_device *orig_dev) { struct rmnet_priv *priv = netdev_priv(orig_dev); struct rmnet_map_ul_csum_header *ul_header; @@ -456,6 +460,99 @@ void rmnet_map_checksum_uplink_packet(struct sk_buff *skb, priv->stats.csum_sw++; } +void rmnet_map_v5_checksum_uplink_packet(struct sk_buff *skb, + struct net_device *orig_dev) +{ + struct rmnet_priv *priv = netdev_priv(orig_dev); + struct rmnet_map_v5_csum_header *ul_header; + + ul_header = (struct rmnet_map_v5_csum_header *) + skb_push(skb, sizeof(*ul_header)); + memset(ul_header, 0, sizeof(*ul_header)); + ul_header->header_type = RMNET_MAP_HEADER_TYPE_CSUM_OFFLOAD; + + if (skb->ip_summed == CHECKSUM_PARTIAL) { + void *iph = (char *)ul_header + sizeof(*ul_header); + void *trans; + __sum16 *check; + u8 proto; + + if (skb->protocol == htons(ETH_P_IP)) { + u16 ip_len = ((struct iphdr *)iph)->ihl * 4; + + proto = ((struct iphdr *)iph)->protocol; + trans = iph + ip_len; + } else if (skb->protocol == htons(ETH_P_IPV6)) { + u16 ip_len = sizeof(struct ipv6hdr); + + proto = ((struct ipv6hdr *)iph)->nexthdr; + trans = iph + ip_len; + } else { + priv->stats.csum_err_invalid_ip_version++; + goto sw_csum; + } + + check = rmnet_map_get_csum_field(proto, trans); + if (check) { + *check = 0; + skb->ip_summed = CHECKSUM_NONE; + /* Ask for checksum offloading */ + ul_header->csum_valid_required = 1; + priv->stats.csum_hw++; + return; + } + } + +sw_csum: + priv->stats.csum_sw++; +} + +/* Generates UL checksum meta info header for IPv4 and IPv6 over TCP and UDP + * packets that are supported for UL checksum offload. + */ +void rmnet_map_checksum_uplink_packet(struct sk_buff *skb, + struct net_device *orig_dev, + int csum_type) +{ + switch (csum_type) { + case RMNET_FLAGS_EGRESS_MAP_CKSUMV4: + rmnet_map_v4_checksum_uplink_packet(skb, orig_dev); + break; + case RMNET_FLAGS_EGRESS_MAP_CKSUMV5: + rmnet_map_v5_checksum_uplink_packet(skb, orig_dev); + break; + default: + break; + } +} + +/* Process a QMAPv5 packet header */ +int rmnet_map_process_next_hdr_packet(struct sk_buff *skb) +{ + struct rmnet_priv *priv = netdev_priv(skb->dev); + int rc = 0; + + switch (rmnet_map_get_next_hdr_type(skb)) { + case RMNET_MAP_HEADER_TYPE_CSUM_OFFLOAD: + if (rmnet_map_get_csum_valid(skb)) { + priv->stats.csum_ok++; + skb->ip_summed = CHECKSUM_UNNECESSARY; + } else { + priv->stats.csum_valid_unset++; + } + + pskb_pull(skb, + (sizeof(struct rmnet_map_header) + + sizeof(struct rmnet_map_v5_csum_header))); + break; + default: + rc = -EINVAL; + break; + } + + return rc; +} + long rmnet_agg_time_limit __read_mostly = 1000000L; long rmnet_agg_bypass_time __read_mostly = 10000000L; -- GitLab From 14712bd0847f4d0016725cb174eaff166235dfe2 Mon Sep 17 00:00:00 2001 From: Josh Kirsch Date: Wed, 2 Jan 2019 18:13:49 -0800 Subject: [PATCH 1074/1286] ARM: dts: msm: DT fixes for sdxprairie Fix codec GPIO lines for sdxprairie so codec will boot up properly. Add correct child association for apr service. Fix for setting the correct clk frequency so codec will run properly. Change-Id: I23b98b48d536d04eefaf15985a77d2db8a82f4d4 Signed-off-by: Josh Kirsch --- .../boot/dts/qcom/sdxprairie-audio-overlay.dtsi | 17 ++++++++++------- .../arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 5 +++++ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-audio-overlay.dtsi index c58118d864f4..f4d43970d8b2 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -43,6 +43,7 @@ qcom,msm-mbhc-gnd-swh = <1>; qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,cdc-ext-clk-rate = <19200000>; qcom,tavil-mclk-clk-freq = <9600000>; asoc-codec = <&stub_codec>; @@ -62,24 +63,26 @@ interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&tlmm>; - qcom,gpio-connect = <&tlmm 90 0>; + qcom,gpio-connect = <&tlmm 96 0>; pinctrl-names = "default"; pinctrl-0 = <&wcd_intr_default>; }; clock_audio_up: audio_ext_clk_up { compatible = "qcom,audio-ref-clk"; - qcom,audio-ref-clk-gpio = <&tlmm 62 0>; - qcom,codec-mclk-clk-freq = <9600000>; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,use-pinctrl = <1>; pinctrl-names = "sleep", "active"; pinctrl-0 = <&i2s_mclk_sleep>; pinctrl-1 = <&i2s_mclk_active>; #clock-cells = <1>; }; - wcd_rst_gpio: msm_cdc_pinctrl@86 { + wcd_rst_gpio: msm_cdc_pinctrl@92 { compatible = "qcom,msm-cdc-pinctrl"; - qcom,cdc-rst-n-gpio = <&tlmm 86 0>; + qcom,cdc-rst-n-gpio = <&tlmm 92 0>; pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&cdc_reset_active>; pinctrl-1 = <&cdc_reset_sleep>; @@ -99,7 +102,7 @@ qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; clock-names = "wcd_clk"; - clocks = <&clock_audio_up AUDIO_LPASS_MCLK_1>; + clocks = <&clock_audio_up 0>; cdc-vdd-buck-supply = <&pmxprairie_l6>; qcom,cdc-vdd-buck-voltage = <1800000 1800000>; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index e77298218622..dcb1b0c538f4 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -376,12 +376,12 @@ wcd9xxx_intr { wcd_intr_default: wcd_intr_default{ mux { - pins = "gpio78"; + pins = "gpio96"; function = "gpio"; }; config { - pins = "gpio78"; + pins = "gpio96"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* pull down */ input-enable; @@ -392,11 +392,11 @@ cdc_reset_ctrl { cdc_reset_sleep: cdc_reset_sleep { mux { - pins = "gpio79"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio79"; + pins = "gpio92"; drive-strength = <2>; bias-disable; output-low; @@ -405,11 +405,11 @@ cdc_reset_active:cdc_reset_active { mux { - pins = "gpio79"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio79"; + pins = "gpio92"; drive-strength = <8>; bias-pull-down; output-high; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 18cd1b08adb5..476afd8cff21 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -630,6 +630,11 @@ 0x2000 3 0x4400 2>; }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; }; }; -- GitLab From c8886658ec9aad7ab51be30fb3da4510ec3b7910 Mon Sep 17 00:00:00 2001 From: jiad Date: Tue, 15 Jan 2019 08:04:02 +0800 Subject: [PATCH 1075/1286] ARM: dts: msm: add CMA pool for QCA6390 on sdxprairie QCA6390 device needs more than 10MB contiguous memory. Thus add CMA pool for QCA6390 device. Change-Id: I72725a3f31ccc036c6bf5be3dae5b3af0a118fa0 Signed-off-by: Jia Ding --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 18cd1b08adb5..34e9df96625e 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -106,7 +106,13 @@ compatible = "shared-dma-pool"; reusable; size = <0x400000>; - }; + }; + + cnss_wlan_mem: cnss_wlan_region@0 { + compatible = "shared-dma-pool"; + reusable; + size = <0x1400000>; + }; }; cpus { @@ -1145,3 +1151,11 @@ }; }; }; + +&pcie0_rp { + cnss: qcom,qca6390@0 { + reg = <0 0 0 0 0>; + + memory-region = <&cnss_wlan_mem>; + }; +}; -- GitLab From a337e14e9e0532404479b8368c0b1a69bc5ddd9d Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 16 Jan 2019 16:13:28 -0800 Subject: [PATCH 1076/1286] power: qpnp-qnovo5: Support configuring external FET control As per the hardware recommendation, external FET should be controlled through a GPIO upon charger removal. Add support for this by allowing GPIO to be configured upon charger removal. Change-Id: Ib171cfb5dfae10a8aa5d67067b9a77740d77eb83 Signed-off-by: Subbaraman Narayanamurthy --- .../power/supply/qcom/qpnp-qnovo5.txt | 15 +++++++ drivers/power/supply/qcom/qpnp-qnovo5.c | 40 ++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt index f27cb33a7335..323e943d2063 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qnovo5.txt @@ -30,6 +30,18 @@ Properties: Definition: Specifies the interrupt name for Qnovo5. There is only one interrupt named as "ptrain-done". +- pinctrl-N: + Usage: optional + Value type: + Definition: Specifies the pinctrl configuration that needs to be applied + when the charger is removed for controlling external FET. + +- pinctrl-names: + Usage: optional + Value type: + Definition: Specifies the names for pinctrl configurations defined above. + Allowed names are "q_state1" and "q_state2". + Example: qcom,qpnp-qnovo@b000 { @@ -37,4 +49,7 @@ qcom,qpnp-qnovo@b000 { reg = <0xb000 0x100>; interrupts = <0x2 0xb0 0x0 IRQ_TYPE_NONE>; interrupt-names = "ptrain-done"; + pinctrl-names = "q_state1", "q_state2"; + pinctrl-0 = <&qnovo_fet_ctrl_state1>; + pinctrl-1 = <&qnovo_fet_ctrl_state2>; }; diff --git a/drivers/power/supply/qcom/qpnp-qnovo5.c b/drivers/power/supply/qcom/qpnp-qnovo5.c index 6250ee8a8c36..d4d3b8d0a388 100644 --- a/drivers/power/supply/qcom/qpnp-qnovo5.c +++ b/drivers/power/supply/qcom/qpnp-qnovo5.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -115,6 +115,9 @@ struct qnovo { struct class qnovo_class; struct power_supply *batt_psy; struct power_supply *usb_psy; + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_state1; + struct pinctrl_state *pinctrl_state2; struct notifier_block nb; struct votable *disable_votable; struct votable *pt_dis_votable; @@ -304,6 +307,30 @@ static int qnovo5_parse_dt(struct qnovo *chip) return rc; } + chip->pinctrl = devm_pinctrl_get(chip->dev); + if (IS_ERR(chip->pinctrl)) { + pr_err("Couldn't get pinctrl rc=%d\n", PTR_ERR(chip->pinctrl)); + chip->pinctrl = NULL; + } + + if (chip->pinctrl) { + chip->pinctrl_state1 = pinctrl_lookup_state(chip->pinctrl, + "q_state1"); + if (IS_ERR(chip->pinctrl_state1)) { + rc = PTR_ERR(chip->pinctrl_state1); + pr_err("Couldn't get pinctrl state1 rc=%d\n", rc); + return rc; + } + + chip->pinctrl_state2 = pinctrl_lookup_state(chip->pinctrl, + "q_state2"); + if (IS_ERR(chip->pinctrl_state2)) { + rc = PTR_ERR(chip->pinctrl_state2); + pr_err("Couldn't get pinctrl state2 rc=%d\n", rc); + return rc; + } + } + return 0; } @@ -1120,6 +1147,17 @@ static void status_change_work(struct work_struct *work) cancel_delayed_work_sync(&chip->usb_debounce_work); vote(chip->awake_votable, USB_READY_VOTER, false, 0); vote(chip->chg_ready_votable, USB_READY_VOTER, false, 0); + if (chip->pinctrl) { + rc = pinctrl_select_state(chip->pinctrl, + chip->pinctrl_state1); + if (rc < 0) + pr_err("Couldn't select state 1 rc=%d\n", rc); + + rc = pinctrl_select_state(chip->pinctrl, + chip->pinctrl_state2); + if (rc < 0) + pr_err("Couldn't select state 2 rc=%d\n", rc); + } } else if (!chip->usb_present && usb_present) { /* insertion */ chip->usb_present = 1; -- GitLab From 3923503d8f52953843c0d3bb2c8ba234f4843b5b Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 16 Jan 2019 16:17:16 -0800 Subject: [PATCH 1077/1286] ARM: dts: msm: Specify pinctrl configuration for qnovo on pm8150b External FET for Qnovo peripheral on PM8150B is controlled via GPIO8. Add the required configuration for it so that it can be configured properly upon charger removal. Change-Id: I6bf88c9c0ab3a8a39c0606b7ccfde0fa586cef52 Signed-off-by: Subbaraman Narayanamurthy --- .../boot/dts/qcom/sm8150-pmic-overlay.dtsi | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi index 43cebaaba219..87f66eaad8c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -88,6 +88,12 @@ }; }; +&pm8150b_qnovo { + pinctrl-names = "q_state1", "q_state2"; + pinctrl-0 = <&qnovo_fet_ctrl_state1>; + pinctrl-1 = <&qnovo_fet_ctrl_state2>; +}; + &pm8150b_gpios { smb_stat { smb_stat_default: smb_stat_default { @@ -99,6 +105,26 @@ power-source = <0>; }; }; + + qnovo_fet_ctrl { + qnovo_fet_ctrl_state1: qnovo_fet_ctrl_state1 { + pins = "gpio8"; + function = "normal"; + input-enable; + output-disable; + bias-disable; + power-source = <0>; + }; + + qnovo_fet_ctrl_state2: qnovo_fet_ctrl_state2 { + pins = "gpio8"; + function = "normal"; + input-enable; + output-disable; + bias-pull-down; + power-source = <0>; + }; + }; }; &usb0 { -- GitLab From 8aaf6a09d3d1870dc980ec9672d02c4f45da19cc Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Tue, 22 Jan 2019 15:26:49 -0800 Subject: [PATCH 1078/1286] msm: IPA: fix the QMI response mismatch between Q6 and AP There is a mismatch between the internal structure of ipa_qmi_response_type_v01 and QMI structure qmi_response_type_v01 which is causing this encode issue. Change-Id: I145ce7ccb20a37fd32f6a9180bfb9f675a4330fa Signed-off-by: Bojun Pan --- include/uapi/linux/ipa_qmi_service_v01.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/uapi/linux/ipa_qmi_service_v01.h b/include/uapi/linux/ipa_qmi_service_v01.h index 8747cbd64ad8..159799bb4f7d 100644 --- a/include/uapi/linux/ipa_qmi_service_v01.h +++ b/include/uapi/linux/ipa_qmi_service_v01.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -92,8 +92,8 @@ enum ipa_qmi_error_type_v01 { }; struct ipa_qmi_response_type_v01 { - enum ipa_qmi_result_type_v01 result; - enum ipa_qmi_error_type_v01 error; + uint16_t result; + uint16_t error; }; enum ipa_platform_type_enum_v01 { -- GitLab From fe0e3ff456e49826f8bf3458bf7b362a4f2c4d5b Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Wed, 23 Jan 2019 12:57:18 -0800 Subject: [PATCH 1079/1286] ARM: dts: msm: Enable Service Locator config for sdxprairie Enable Service locator and notifier configurations for sdxprairie target for service notifications. Change-Id: Ic88fb476c755a661f28a58a5b799db2b96f0e51c Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 84123b0cbd01..bf7d5ec584d5 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -338,6 +338,8 @@ CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index a3c39935112c..476287647b10 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -329,6 +329,8 @@ CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y -- GitLab From 9761de0bb3325a898c39e6948cada628d82868b1 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 22 Jan 2019 11:58:55 -0700 Subject: [PATCH 1080/1286] drivers: thermal: qmi-sensor: Add support for new qmi sensor Add support for new qmi sensor pa_2. Now this sensor will be recognized by the driver and can be registered as a thermal zone. Change-Id: I75eed4496824ea65c9b1a483b321cfb003168fbc Signed-off-by: Ram Chandrasekar --- .../bindings/thermal/qti-qmi-sensor.txt | 21 ++++++++++--------- drivers/thermal/qcom/qmi_sensors.c | 4 +++- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt b/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt index adb382b97d8e..12cf0276805d 100644 --- a/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt +++ b/Documentation/devicetree/bindings/thermal/qti-qmi-sensor.txt @@ -33,16 +33,17 @@ Subsystem properties: are the only acceptable sensor names, 1. pa 2. pa1 - 3. qfe_pa0 - 4. qfe_wtr0 - 5. modem_tsens - 6. qfe_mmw0 - 7. qfe_mmw1 - 8. qfe_mmw2 - 9. qfe_mmw3 - 10. xo_therm - 11. qfe_pa_mdm - 12. qfe_pa_wtr + 3. pa2 + 4. qfe_pa0 + 5. qfe_wtr0 + 6. modem_tsens + 7. qfe_mmw0 + 8. qfe_mmw1 + 9. qfe_mmw2 + 10. qfe_mmw3 + 11. xo_therm + 12. qfe_pa_mdm + 13. qfe_pa_wtr Example: diff --git a/drivers/thermal/qcom/qmi_sensors.c b/drivers/thermal/qcom/qmi_sensors.c index 4feb3cb9f1fe..dbd2eb4bfd69 100644 --- a/drivers/thermal/qcom/qmi_sensors.c +++ b/drivers/thermal/qcom/qmi_sensors.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -40,6 +40,7 @@ enum qmi_ts_sensor { QMI_TS_PA, QMI_TS_PA_1, + QMI_TS_PA_2, QMI_TS_QFE_PA_0, QMI_TS_QFE_WTR_0, QMI_TS_MODEM_MODEM, @@ -83,6 +84,7 @@ static atomic_t in_suspend; static char sensor_clients[QMI_TS_MAX_NR][QMI_CLIENT_NAME_LENGTH] = { {"pa"}, {"pa_1"}, + {"pa_2"}, {"qfe_pa0"}, {"qfe_wtr0"}, {"modem_tsens"}, -- GitLab From 6cce2a0ae75dd50af675e398780c122eb7f3694e Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 21 Jan 2019 15:22:38 -0700 Subject: [PATCH 1081/1286] ARM: dts: msm: Add support for new sensor in sdx50 Add a new thermal zone to map the pa_2 sensor from modem1 in sdx50. Change-Id: If8e1e797e5e2b0ec71221056e8f942aa99f464ff Signed-off-by: Ram Chandrasekar --- arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi | 33 +++++++++++++++------ 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi index e791d1d32ff2..93b4591b5f17 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -338,6 +338,7 @@ qcom,instance-id = <100>; qcom,qmi-sensor-names = "pa", "pa_1", + "pa_2", "qfe_pa0", "qfe_wtr0", "modem_tsens", @@ -413,7 +414,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 103>; + thermal-sensors = <&qmi_sensor 104>; trips { active-config0 { temperature = <125000>; @@ -427,7 +428,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 104>; + thermal-sensors = <&qmi_sensor 105>; trips { active-config0 { temperature = <125000>; @@ -441,7 +442,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 105>; + thermal-sensors = <&qmi_sensor 106>; trips { active-config0 { temperature = <125000>; @@ -455,7 +456,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 106>; + thermal-sensors = <&qmi_sensor 107>; trips { active-config0 { temperature = <125000>; @@ -469,7 +470,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 107>; + thermal-sensors = <&qmi_sensor 108>; trips { active-config0 { temperature = <125000>; @@ -483,7 +484,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 108>; + thermal-sensors = <&qmi_sensor 109>; trips { active-config0 { temperature = <125000>; @@ -497,7 +498,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 109>; + thermal-sensors = <&qmi_sensor 110>; trips { active-config0 { temperature = <125000>; @@ -511,7 +512,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 110>; + thermal-sensors = <&qmi_sensor 111>; trips { active-config0 { temperature = <125000>; @@ -525,7 +526,21 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 111>; + thermal-sensors = <&qmi_sensor 112>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 102>; trips { active-config0 { temperature = <125000>; -- GitLab From 86251e9d7d87b8b457be09d9b88a06be8f9754c3 Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 23 Jan 2019 23:16:07 -0500 Subject: [PATCH 1082/1286] ARM: dts: msm: Add support for Aquantia ethernet adapter Add initial devicetree node for enabling Aquantia AQC107 PCIe ethernet adapter. CRs-Fixed: 2309519 Change-Id: I5b3d2615f311bfca89c6ad2d2e607eff130c97d2 Signed-off-by: Jinesh K. Jayakumar --- arch/arm64/boot/dts/qcom/sdxprairie-aqc.dtsi | 26 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 1 + 2 files changed, 27 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-aqc.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-aqc.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-aqc.dtsi new file mode 100644 index 000000000000..0e9495a09563 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-aqc.dtsi @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie0_rp { + aqc_x4: aquantia,aqc107@pcie0_rp { + reg = <0 0 0 0 0>; + + compatible = "aquantia,aqc-107"; + + qcom,smmu; + qcom,smmu-iova-base = /bits/ 64 <0x0>; + qcom,smmu-iova-size = /bits/ 64 <0x80000000>; + + qcom,smmu-attr-s1-bypass; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index e92274f75b22..d1a3f79bc777 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -1034,6 +1034,7 @@ #include "sdxprairie-audio.dtsi" #include "sdxprairie-pcie.dtsi" #include "sdxprairie-coresight.dtsi" +#include "sdxprairie-aqc.dtsi" &gdsc_usb30 { status = "ok"; -- GitLab From 5b1e33be39a4cc64a4b07235bc57647b80af940e Mon Sep 17 00:00:00 2001 From: "Jinesh K. Jayakumar" Date: Wed, 23 Jan 2019 23:38:47 -0500 Subject: [PATCH 1083/1286] defconfig: sdxprairie: Enable Aquantia forwarding driver Enable Aquantia forwarding driver for sdxprairie target. CRs-Fixed: 2309519 Change-Id: I4fad092b644617885970cc2b3f975d61865e82c3 Signed-off-by: Jinesh K. Jayakumar --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index db545d3002c0..6486bf087dd1 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -185,6 +185,8 @@ CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_NETDEVICES=y CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM=y # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_FARADAY is not set diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 73a39d2ffece..78b334736af1 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -173,6 +173,8 @@ CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_NETDEVICES=y CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM=y # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_FARADAY is not set -- GitLab From 127872185447114b8b9c861b45e59765ddde1d04 Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Thu, 17 Jan 2019 15:24:30 +0530 Subject: [PATCH 1084/1286] memshare: Enable info logs to help in debug alloc failure Presently debug logs to help analyze errors related to QMI requests for memory size query, allocation and free are not enough. Enabling few logs to add debuggability and modify debug logs to dev_* calls. Change-Id: I1c48681782a41dd83b87ec7ccfd237cf8c74494a Signed-off-by: Manoj Prabhu B --- drivers/soc/qcom/memshare/msm_memshare.c | 195 +++++++++++++---------- 1 file changed, 109 insertions(+), 86 deletions(-) diff --git a/drivers/soc/qcom/memshare/msm_memshare.c b/drivers/soc/qcom/memshare/msm_memshare.c index 7cd685039584..4a86eead0a0a 100644 --- a/drivers/soc/qcom/memshare/msm_memshare.c +++ b/drivers/soc/qcom/memshare/msm_memshare.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -81,7 +81,7 @@ static int mem_share_configure_ramdump(int client) clnt = "DIAG"; break; default: - pr_err("memshare: no memshare clients registered\n"); + dev_err(memsh_child->dev, "memshare: no memshare clients registered\n"); return -EINVAL; } @@ -92,12 +92,13 @@ static int mem_share_configure_ramdump(int client) create_ramdump_device(client_name, memshare_dev[client]); } else { - pr_err("memshare:%s: invalid memshare device\n", __func__); + dev_err(memsh_child->dev, + "memshare: invalid memshare device for creating ramdump device\n"); return -ENODEV; } if (IS_ERR_OR_NULL(memshare_ramdump_dev[client])) { - pr_err("memshare: %s: Unable to create memshare ramdump device\n", - __func__); + dev_err(memsh_child->dev, + "memshare: unable to create memshare ramdump device\n"); memshare_ramdump_dev[client] = NULL; return -ENOMEM; } @@ -118,7 +119,9 @@ static int check_client(int client_id, int proc, int request) } } if ((found == DHMS_MEM_CLIENT_INVALID) && !request) { - pr_debug("memshare: No registered client, adding a new client\n"); + dev_dbg(memsh_child->dev, + "memshare: No registered client for the client_id: %d, adding a new client\n", + client_id); /* Add a new client */ for (i = 0; i < MAX_CLIENTS; i++) { if (memblock[i].client_id == DHMS_MEM_CLIENT_INVALID) { @@ -131,8 +134,9 @@ static int check_client(int client_id, int proc, int request) if (!memblock[i].file_created) { rc = mem_share_configure_ramdump(i); if (rc) - pr_err("memshare: %s, Cannot create ramdump for client: %d\n", - __func__, client_id); + dev_err(memsh_child->dev, + "memshare_check_client: cannot create ramdump for client with id: %d\n", + client_id); else memblock[i].file_created = 1; } @@ -228,12 +232,14 @@ static int mem_share_do_ramdump(void) client_name = "DIAG"; break; default: - pr_err("memshare: no memshare clients registered\n"); + dev_err(memsh_child->dev, + "memshare: no memshare clients registered for client_id: %d\n", + i); return -EINVAL; } if (!memblock[i].allotted) { - pr_err("memshare:%s memblock is not allotted\n", + dev_err(memsh_child->dev, "memshare: %s: memblock is not allotted\n", client_name); continue; } @@ -241,8 +247,9 @@ static int mem_share_do_ramdump(void) if (memblock[i].hyp_mapping && memblock[i].peripheral == DHMS_MEM_PROC_MPSS_V01) { - pr_debug("memshare: hypervisor unmapping for client id: %d\n", - memblock[i].client_id); + dev_dbg(memsh_child->dev, + "memshare: %s: hypervisor unmapping for client before elf dump\n", + client_name); if (memblock[i].alloc_request) continue; ret = hyp_assign_phys( @@ -258,8 +265,9 @@ static int mem_share_do_ramdump(void) * earlier but during unmap * it lead to failure. */ - pr_err("memshare: %s, failed to map the region to APPS\n", - __func__); + dev_err(memsh_child->dev, + "memshare: %s: failed to map the memory region to APPS\n", + client_name); } else { memblock[i].hyp_mapping = 0; } @@ -274,14 +282,16 @@ static int mem_share_do_ramdump(void) ramdump_segments_tmp[0].size = memblock[i].size; ramdump_segments_tmp[0].address = memblock[i].phy_addr; - pr_debug("memshare: %s:%s client:id: %d:size = %d\n", - __func__, client_name, i, memblock[i].size); + dev_dbg(memsh_child->dev, "memshare: %s: Begin elf dump for size = %d\n", + client_name, memblock[i].size); ret = do_elf_ramdump(memshare_ramdump_dev[i], ramdump_segments_tmp, 1); kfree(ramdump_segments_tmp); if (ret < 0) { - pr_err("memshare: Unable to dump: %d\n", ret); + dev_err(memsh_child->dev, + "memshare: %s: Unable to elf dump with failure: %d\n", + client_name, ret); return ret; } } @@ -320,23 +330,22 @@ static int modem_notifier_cb(struct notifier_block *this, unsigned long code, } if (notifdata->enable_ramdump && ramdump_event) { - pr_debug("memshare: %s, Ramdump collection is enabled\n", - __func__); + dev_info(memsh_child->dev, "memshare: Ramdump collection is enabled\n"); ret = mem_share_do_ramdump(); if (ret) - pr_err("memshare: Ramdump collection failed\n"); + dev_err(memsh_child->dev, "memshare: Ramdump collection failed\n"); ramdump_event = 0; } break; case SUBSYS_AFTER_POWERUP: - pr_debug("memshare: Modem has booted up\n"); + dev_dbg(memsh_child->dev, "memshare: Modem has booted up\n"); for (i = 0; i < MAX_CLIENTS; i++) { size = memblock[i].size; if (memblock[i].free_memory > 0 && bootup_request >= 2) { memblock[i].free_memory -= 1; - pr_debug("memshare: free_memory count: %d for client id: %d\n", + dev_dbg(memsh_child->dev, "memshare: free_memory count: %d for client id: %d\n", memblock[i].free_memory, memblock[i].client_id); } @@ -348,7 +357,8 @@ static int modem_notifier_cb(struct notifier_block *this, unsigned long code, !memblock[i].client_request && memblock[i].allotted && !memblock[i].alloc_request) { - pr_debug("memshare: hypervisor unmapping for client id: %d\n", + dev_info(memsh_child->dev, + "memshare: hypervisor unmapping for allocated memory with client id: %d\n", memblock[i].client_id); if (memblock[i].hyp_mapping) { ret = hyp_assign_phys( @@ -365,8 +375,9 @@ static int modem_notifier_cb(struct notifier_block *this, unsigned long code, * earlier but during unmap * it lead to failure. */ - pr_err("memshare: %s, failed to unmap the region\n", - __func__); + dev_err(memsh_child->dev, + "memshare: failed to hypervisor unmap the memory region for client id: %d\n", + memblock[i].client_id); } else { memblock[i].hyp_mapping = 0; } @@ -409,7 +420,8 @@ static void shared_hyp_mapping(int client_id) int dest_perms[1] = {PERM_READ|PERM_WRITE}; if (client_id == DHMS_MEM_CLIENT_INVALID) { - pr_err("memshare: %s, Invalid Client\n", __func__); + dev_err(memsh_child->dev, + "memshare: hypervisor mapping failure for invalid client\n"); return; } @@ -419,7 +431,7 @@ static void shared_hyp_mapping(int client_id) dest_perms, 1); if (ret != 0) { - pr_err("memshare: hyp_assign_phys failed size=%u err=%d\n", + dev_err(memsh_child->dev, "memshare: hyp_assign_phys failed size=%u err=%d\n", memblock[client_id].size, ret); return; } @@ -437,8 +449,9 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, mutex_lock(&memsh_drv->mem_share); alloc_req = (struct mem_alloc_generic_req_msg_v01 *)decoded_msg; - pr_debug("memshare: alloc request client id: %d proc _id: %d\n", - alloc_req->client_id, alloc_req->proc_id); + dev_info(memsh_child->dev, + "memshare_alloc: memory alloc request received for client id: %d, proc_id: %d, request size: %d\n", + alloc_req->client_id, alloc_req->proc_id, alloc_req->num_bytes); alloc_resp = kzalloc(sizeof(*alloc_resp), GFP_KERNEL); if (!alloc_resp) { @@ -451,9 +464,9 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, CHECK); if (client_id >= MAX_CLIENTS) { - pr_err("memshare: %s client not found, requested client: %d, proc_id: %d\n", - __func__, alloc_req->client_id, - alloc_req->proc_id); + dev_err(memsh_child->dev, + "memshare_alloc: client not found, requested client: %d, proc_id: %d\n", + alloc_req->client_id, alloc_req->proc_id); kfree(alloc_resp); alloc_resp = NULL; mutex_unlock(&memsh_drv->mem_share); @@ -468,8 +481,9 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, rc = memshare_alloc(memsh_drv->dev, size, &memblock[client_id]); if (rc) { - pr_err("memshare: %s,Unable to allocate memory for requested client\n", - __func__); + dev_err(memsh_child->dev, + "memshare_alloc: unable to allocate memory of size: %d for requested client\n", + size); resp = 1; } if (!resp) { @@ -479,9 +493,9 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, memblock[client_id].peripheral = alloc_req->proc_id; } } - pr_debug("memshare: In %s, free memory count for client id: %d = %d", - __func__, memblock[client_id].client_id, - memblock[client_id].free_memory); + dev_dbg(memsh_child->dev, + "memshare_alloc: free memory count for client id: %d = %d\n", + memblock[client_id].client_id, memblock[client_id].free_memory); memblock[client_id].sequence_id = alloc_req->sequence_id; memblock[client_id].alloc_request = 1; @@ -495,17 +509,20 @@ static void handle_alloc_generic_req(struct qmi_handle *handle, memblock[client_id].allotted) shared_hyp_mapping(client_id); mutex_unlock(&memsh_drv->mem_share); - pr_debug("memshare: alloc_resp.num_bytes :%d, alloc_resp.resp.result :%lx\n", - alloc_resp->dhms_mem_alloc_addr_info[0].num_bytes, - (unsigned long int)alloc_resp->resp.result); + dev_info(memsh_child->dev, + "memshare_alloc: client_id: %d, alloc_resp.num_bytes: %d, alloc_resp.resp.result: %lx\n", + alloc_req->client_id, + alloc_resp->dhms_mem_alloc_addr_info[0].num_bytes, + (unsigned long int)alloc_resp->resp.result); rc = qmi_send_response(mem_share_svc_handle, sq, txn, MEM_ALLOC_GENERIC_RESP_MSG_V01, sizeof(struct mem_alloc_generic_resp_msg_v01), mem_alloc_generic_resp_msg_data_v01_ei, alloc_resp); if (rc < 0) - pr_err("memshare: %s, Error sending the alloc response: %d\n", - __func__, rc); + dev_err(memsh_child->dev, + "memshare_alloc: Error sending the alloc response: %d\n", + rc); kfree(alloc_resp); alloc_resp = NULL; @@ -525,22 +542,22 @@ static void handle_free_generic_req(struct qmi_handle *handle, mutex_lock(&memsh_drv->mem_free); free_req = (struct mem_free_generic_req_msg_v01 *)decoded_msg; - pr_debug("memshare: %s: Received Free Request\n", __func__); memset(&free_resp, 0, sizeof(free_resp)); free_resp.resp.error = QMI_ERR_INTERNAL_V01; free_resp.resp.result = QMI_RESULT_FAILURE_V01; - pr_debug("memshare: Client id: %d proc id: %d\n", free_req->client_id, - free_req->proc_id); + dev_info(memsh_child->dev, + "memshare_free: handling memory free request with client id: %d, proc_id: %d\n", + free_req->client_id, free_req->proc_id); client_id = check_client(free_req->client_id, free_req->proc_id, FREE); if (client_id == DHMS_MEM_CLIENT_INVALID) { - pr_err("memshare: %s, Invalid client request to free memory\n", - __func__); + dev_err(memsh_child->dev, "memshare_free: invalid client request to free memory\n"); flag = 1; } else if (!memblock[client_id].guarantee && !memblock[client_id].client_request && memblock[client_id].allotted) { - pr_debug("memshare: %s:client_id:%d - size: %d", - __func__, client_id, memblock[client_id].size); + dev_dbg(memsh_child->dev, + "memshare_free: hypervisor unmapping for client_id:%d - size: %d\n", + client_id, memblock[client_id].size); ret = hyp_assign_phys(memblock[client_id].phy_addr, memblock[client_id].size, source_vmlist, 1, dest_vmids, dest_perms, 1); @@ -549,8 +566,9 @@ static void handle_free_generic_req(struct qmi_handle *handle, * This is an error case as hyp mapping was successful * earlier but during unmap it lead to failure. */ - pr_err("memshare: %s, failed to unmap the region for client id:%d\n", - __func__, client_id); + dev_err(memsh_child->dev, + "memshare_free: failed to unmap the region for client id:%d\n", + client_id); } size = memblock[client_id].size; if (memblock[client_id].guard_band) { @@ -567,8 +585,9 @@ static void handle_free_generic_req(struct qmi_handle *handle, attrs); free_client(client_id); } else { - pr_err("memshare: %s, Request came for a guaranteed client (client_id: %d) cannot free up the memory\n", - __func__, client_id); + dev_err(memsh_child->dev, + "memshare_free: cannot free the memory for a guaranteed client (client_id: %d)\n", + client_id); } if (flag) { @@ -585,8 +604,8 @@ static void handle_free_generic_req(struct qmi_handle *handle, sizeof(struct mem_free_generic_resp_msg_v01), mem_free_generic_resp_msg_data_v01_ei, &free_resp); if (rc < 0) - pr_err("memshare: %s, Error sending the free response: %d\n", - __func__, rc); + dev_err(memsh_child->dev, + "memshare_free: error sending the free response: %d\n", rc); return; } @@ -606,15 +625,16 @@ static void handle_query_size_req(struct qmi_handle *handle, mutex_unlock(&memsh_drv->mem_share); return; } - pr_debug("memshare: query request client id: %d proc _id: %d\n", + dev_dbg(memsh_child->dev, + "memshare_query: query on availalbe memory size for client id: %d, proc_id: %d\n", query_req->client_id, query_req->proc_id); client_id = check_client(query_req->client_id, query_req->proc_id, CHECK); if (client_id >= MAX_CLIENTS) { - pr_err("memshare: %s client not found, requested client: %d, proc_id: %d\n", - __func__, query_req->client_id, - query_req->proc_id); + dev_err(memsh_child->dev, + "memshare_query: client not found, requested client: %d, proc_id: %d\n", + query_req->client_id, query_req->proc_id); kfree(query_resp); query_resp = NULL; mutex_unlock(&memsh_drv->mem_share); @@ -632,16 +652,17 @@ static void handle_query_size_req(struct qmi_handle *handle, query_resp->resp.error = QMI_ERR_NONE_V01; mutex_unlock(&memsh_drv->mem_share); - pr_debug("memshare: query_resp.size :%d, query_resp.resp.result :%lx\n", - query_resp->size, - (unsigned long int)query_resp->resp.result); + dev_info(memsh_child->dev, + "memshare_query: client_id : %d, query_resp.size :%d, query_resp.resp.result :%lx\n", + query_req->client_id, query_resp->size, + (unsigned long int)query_resp->resp.result); rc = qmi_send_response(mem_share_svc_handle, sq, txn, MEM_QUERY_SIZE_RESP_MSG_V01, MEM_QUERY_MAX_MSG_LEN_V01, mem_query_size_resp_msg_data_v01_ei, query_resp); if (rc < 0) - pr_err("memshare: %s, Error sending the query response: %d\n", - __func__, rc); + dev_err(memsh_child->dev, + "memshare_query: Error sending the query response: %d\n", rc); kfree(query_resp); query_resp = NULL; @@ -686,11 +707,12 @@ int memshare_alloc(struct device *dev, unsigned int block_size, struct mem_blocks *pblk) { - pr_debug("memshare: %s", __func__); + dev_dbg(memsh_child->dev, + "memshare: allocation request for size: %d", block_size); if (!pblk) { - pr_err("memshare: %s: Failed memory block allocation\n", - __func__); + dev_err(memsh_child->dev, + "memshare: Failed memory block allocation\n"); return -ENOMEM; } @@ -723,8 +745,8 @@ static void memshare_init_worker(struct work_struct *work) sizeof(struct qmi_elem_info), &server_ops, qmi_memshare_handlers); if (rc < 0) { - pr_err("memshare: %s: Creating mem_share_svc qmi handle failed\n", - __func__); + dev_err(memsh_child->dev, + "memshare: Creating mem_share_svc qmi handle failed\n"); kfree(mem_share_svc_handle); destroy_workqueue(mem_share_svc_workqueue); return; @@ -732,14 +754,14 @@ static void memshare_init_worker(struct work_struct *work) rc = qmi_add_server(mem_share_svc_handle, MEM_SHARE_SERVICE_SVC_ID, MEM_SHARE_SERVICE_VERS, MEM_SHARE_SERVICE_INS_ID); if (rc < 0) { - pr_err("memshare: %s: Registering mem share svc failed %d\n", - __func__, rc); + dev_err(memsh_child->dev, + "memshare: Registering mem share svc failed %d\n", rc); qmi_handle_release(mem_share_svc_handle); kfree(mem_share_svc_handle); destroy_workqueue(mem_share_svc_workqueue); return; } - pr_debug("memshare: memshare_init successful\n"); + dev_dbg(memsh_child->dev, "memshare: memshare_init successful\n"); } static int memshare_child_probe(struct platform_device *pdev) @@ -762,16 +784,16 @@ static int memshare_child_probe(struct platform_device *pdev) rc = of_property_read_u32(pdev->dev.of_node, "qcom,peripheral-size", &size); if (rc) { - pr_err("memshare: %s, Error reading size of clients, rc: %d\n", - __func__, rc); + dev_err(memsh_child->dev, "memshare: Error reading size of clients, rc: %d\n", + rc); return rc; } rc = of_property_read_u32(pdev->dev.of_node, "qcom,client-id", &client_id); if (rc) { - pr_err("memshare: %s, Error reading client id, rc: %d\n", - __func__, rc); + dev_err(memsh_child->dev, "memshare: Error reading client id, rc: %d\n", + rc); return rc; } @@ -790,8 +812,8 @@ static int memshare_child_probe(struct platform_device *pdev) rc = of_property_read_string(pdev->dev.of_node, "label", &name); if (rc) { - pr_err("memshare: %s, Error reading peripheral info for client, rc: %d\n", - __func__, rc); + dev_err(memsh_child->dev, "memshare: Error reading peripheral info for client, rc: %d\n", + rc); return rc; } @@ -815,8 +837,9 @@ static int memshare_child_probe(struct platform_device *pdev) size, &memblock[num_clients]); if (rc) { - pr_err("memshare: %s, Unable to allocate memory for guaranteed clients, rc: %d\n", - __func__, rc); + dev_err(memsh_child->dev, + "memshare_child: Unable to allocate memory for guaranteed clients, rc: %d\n", + rc); return rc; } memblock[num_clients].allotted = 1; @@ -833,9 +856,9 @@ static int memshare_child_probe(struct platform_device *pdev) if (!memblock[num_clients].file_created) { rc = mem_share_configure_ramdump(num_clients); if (rc) - pr_err("memshare: %s, cannot collect dumps for client id: %d\n", - __func__, - memblock[num_clients].client_id); + dev_err(memsh_child->dev, + "memshare_child: cannot create ramdump for client with id: %d\n", + memblock[num_clients].client_id); else memblock[num_clients].file_created = 1; } @@ -873,13 +896,13 @@ static int memshare_probe(struct platform_device *pdev) &pdev->dev); if (rc) { - pr_err("memshare: %s, error populating the devices\n", - __func__); + dev_err(memsh_child->dev, + "memshare: error populating the devices\n"); return rc; } subsys_notif_register_notifier("modem", &nb); - pr_debug("memshare: %s, Memshare inited\n", __func__); + dev_dbg(memsh_child->dev, "memshare: Memshare inited\n"); return 0; } -- GitLab From fe6101d4736b3d85b373813514cec1ad1c456a8e Mon Sep 17 00:00:00 2001 From: Abhijeet Dharmapurikar Date: Tue, 22 Jan 2019 21:36:49 -0800 Subject: [PATCH 1085/1286] sched/tune: remove disabling sched_boost per cgroup The current code support enabling/disabling sched boost per cgroup. This is not used. Remove it. This also makes it unnecessary to track the backup of enabled, remove it too. Change-Id: I1af1bc9116a21e8921742a8aac6e9b8568e4de3c Signed-off-by: Abhijeet Dharmapurikar --- kernel/sched/tune.c | 35 +---------------------------------- 1 file changed, 1 insertion(+), 34 deletions(-) diff --git a/kernel/sched/tune.c b/kernel/sched/tune.c index dc49ffb4278f..627185b31973 100644 --- a/kernel/sched/tune.c +++ b/kernel/sched/tune.c @@ -43,12 +43,6 @@ struct schedtune { */ bool sched_boost_enabled; - /* - * This tracks the default value of sched_boost_enabled and is used - * restore the value following any temporary changes to that flag. - */ - bool sched_boost_enabled_backup; - /* * Controls whether tasks of this cgroup should be colocated with each * other and tasks of other cgroups that have the same flag turned on. @@ -94,7 +88,6 @@ root_schedtune = { #ifdef CONFIG_SCHED_WALT .sched_boost_no_override = false, .sched_boost_enabled = true, - .sched_boost_enabled_backup = true, .colocate = false, .colocate_update_disabled = false, #endif @@ -153,7 +146,6 @@ static inline void init_sched_boost(struct schedtune *st) { st->sched_boost_no_override = false; st->sched_boost_enabled = true; - st->sched_boost_enabled_backup = st->sched_boost_enabled; st->colocate = false; st->colocate_update_disabled = false; } @@ -186,8 +178,7 @@ void restore_cgroup_boost_settings(void) if (!allocated_group[i]) break; - allocated_group[i]->sched_boost_enabled = - allocated_group[i]->sched_boost_enabled_backup; + allocated_group[i]->sched_boost_enabled = true; } } @@ -461,25 +452,6 @@ int schedtune_can_attach(struct cgroup_taskset *tset) } #ifdef CONFIG_SCHED_WALT -static u64 sched_boost_enabled_read(struct cgroup_subsys_state *css, - struct cftype *cft) -{ - struct schedtune *st = css_st(css); - - return st->sched_boost_enabled; -} - -static int sched_boost_enabled_write(struct cgroup_subsys_state *css, - struct cftype *cft, u64 enable) -{ - struct schedtune *st = css_st(css); - - st->sched_boost_enabled = !!enable; - st->sched_boost_enabled_backup = st->sched_boost_enabled; - - return 0; -} - static u64 sched_colocate_read(struct cgroup_subsys_state *css, struct cftype *cft) { @@ -667,11 +639,6 @@ static struct cftype files[] = { .read_u64 = sched_boost_override_read, .write_u64 = sched_boost_override_write, }, - { - .name = "sched_boost_enabled", - .read_u64 = sched_boost_enabled_read, - .write_u64 = sched_boost_enabled_write, - }, { .name = "colocate", .read_u64 = sched_colocate_read, -- GitLab From 860a87cc9d09f5c07b37b8372469b77d6cc115f1 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Thu, 24 Jan 2019 10:46:23 +0530 Subject: [PATCH 1086/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: If04d5d50971a18652a0f3dde22dca8725d20a632 Signed-off-by: Pavankumar Kondeti --- kernel/sched/boost.c | 46 +------------------------------------------- kernel/sched/core.c | 11 +---------- kernel/sched/fair.c | 3 --- kernel/sched/sched.h | 10 ---------- kernel/sched/walt.c | 3 +-- 5 files changed, 3 insertions(+), 70 deletions(-) diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index d4fe48c999ab..ae8f5f5785e2 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -29,47 +29,6 @@ static enum sched_boost_policy boost_policy_dt = SCHED_BOOST_NONE; static DEFINE_MUTEX(boost_mutex); static int boost_refcount[MAX_NUM_BOOST_TYPE]; -static inline void boost_kick(int cpu) -{ - struct rq *rq = cpu_rq(cpu); - - if (!test_and_set_bit(BOOST_KICK, &rq->walt_flags)) - smp_send_reschedule(cpu); -} - -static void boost_kick_cpus(void) -{ - int i; - struct cpumask kick_mask; - - if (boost_policy != SCHED_BOOST_ON_BIG) - return; - - cpus_read_lock(); - cpumask_andnot(&kick_mask, cpu_online_mask, cpu_isolated_mask); - - for_each_cpu(i, &kick_mask) { - if (cpu_capacity(i) != max_capacity) - boost_kick(i); - } - cpus_read_unlock(); -} - -int got_boost_kick(void) -{ - int cpu = smp_processor_id(); - struct rq *rq = cpu_rq(cpu); - - return test_bit(BOOST_KICK, &rq->walt_flags); -} - -void clear_boost_kick(int cpu) -{ - struct rq *rq = cpu_rq(cpu); - - clear_bit(BOOST_KICK, &rq->walt_flags); -} - /* * Scheduler boost type and boost policy might at first seem unrelated, * however, there exists a connection between them that will allow us @@ -135,7 +94,6 @@ static void _sched_set_boost(int type) if (boost_refcount[FULL_THROTTLE_BOOST] == 1) { core_ctl_set_boost(true); restore_cgroup_boost_settings(); - boost_kick_cpus(); if (!boost_refcount[RESTRAINED_BOOST]) walt_enable_frequency_aggregation(true); } @@ -144,10 +102,8 @@ static void _sched_set_boost(int type) case CONSERVATIVE_BOOST: boost_refcount[CONSERVATIVE_BOOST]++; if ((boost_refcount[CONSERVATIVE_BOOST] == 1) && - !boost_refcount[FULL_THROTTLE_BOOST]) { + !boost_refcount[FULL_THROTTLE_BOOST]) update_cgroup_boost_settings(); - boost_kick_cpus(); - } break; case RESTRAINED_BOOST: diff --git a/kernel/sched/core.c b/kernel/sched/core.c index b6b92ab63cbf..95e6e0f45895 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -1837,18 +1837,9 @@ void scheduler_ipi(void) */ preempt_fold_need_resched(); - if (llist_empty(&this_rq()->wake_list) && !got_nohz_idle_kick() - && !got_boost_kick()) + if (llist_empty(&this_rq()->wake_list) && !got_nohz_idle_kick()) return; - if (got_boost_kick()) { - struct rq *rq = cpu_rq(cpu); - - if (rq->curr->sched_class == &fair_sched_class) - check_for_migration(rq, rq->curr); - clear_boost_kick(cpu); - } - /* * Not all reschedule IPI handlers call irq_enter/irq_exit, since * traditionally all their work was done from the interrupt return diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index d06fdfd38309..3cc4dde46fbf 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -12847,9 +12847,6 @@ static void walt_check_for_rotation(struct rq *src_rq) if (!walt_rotation_enabled) return; - if (got_boost_kick()) - return; - if (!is_min_capacity_cpu(src_cpu)) return; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 7d395e49452d..9a0dc1642f2f 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2829,7 +2829,6 @@ static inline int same_freq_domain(int src_cpu, int dst_cpu) return cpumask_test_cpu(dst_cpu, &rq->freq_domain_cpumask); } -#define BOOST_KICK 0 #define CPU_RESERVED 1 extern int sched_boost(void); @@ -2909,8 +2908,6 @@ extern unsigned long thermal_cap(int cpu); extern void clear_walt_request(int cpu); -extern int got_boost_kick(void); -extern void clear_boost_kick(int cpu); extern enum sched_boost_policy sched_boost_policy(void); extern void sched_boost_parse_dt(void); extern void clear_ed_task(struct task_struct *p, struct rq *rq); @@ -3076,13 +3073,6 @@ static inline int is_reserved(int cpu) return 0; } -static inline int got_boost_kick(void) -{ - return 0; -} - -static inline void clear_boost_kick(int cpu) { } - static inline enum sched_boost_policy sched_boost_policy(void) { return SCHED_BOOST_NONE; diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c index 4e7ea7978ed0..0719cf32d3ff 100644 --- a/kernel/sched/walt.c +++ b/kernel/sched/walt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -421,7 +421,6 @@ void clear_walt_request(int cpu) struct rq *rq = cpu_rq(cpu); unsigned long flags; - clear_boost_kick(cpu); clear_reserved(cpu); if (rq->push_task) { struct task_struct *push_task = NULL; -- GitLab From df8edaadf95817f6c999ffe2dc7f327eba14348c Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Wed, 9 Jan 2019 20:32:29 +0530 Subject: [PATCH 1087/1286] ARM: dts: msm: add support to enable backlight through PWM on TRINKET Add changes required to enable backlight through PWM gpio for td4330 truly panel on TRINKET. Change-Id: Ic27c0e735210439bdda8ba5a54e60a02dada99fb Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 5bfefed8f4fe..50cadae17b45 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -255,9 +255,15 @@ status = "ok"; }; +&pm6125_pwm { + status = "ok"; +}; + &dsi_td4330_truly_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 90 0>; @@ -266,7 +272,9 @@ &dsi_td4330_truly_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 89 0>; -- GitLab From 7222a0a5d6580acad3cef0649856274f30ae205d Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 3 Jan 2019 15:01:41 +0530 Subject: [PATCH 1088/1286] ARM: dts: msm: enable dynamic clk switch feature for sdmmagpie Enable dynamic clock switch feature for sw4328 video mode panel on sdmmmagpie platform. Change-Id: I90fd899cb61198f98bf7a5306fc06891b21d8a2b Signed-off-by: Ritesh Kumar --- .../boot/dts/qcom/sdmmagpie-sde-display.dtsi | 17 ++++++++++++++--- arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi | 15 ++++++++++----- arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi | 12 +++++++----- arch/arm64/boot/dts/qcom/sdmmagpie.dtsi | 9 +++++++-- 4 files changed, 38 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index e7bda760eb67..4d85b6a458d5 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -104,7 +104,9 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_video>; }; @@ -294,9 +296,15 @@ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "mux_byte_clk1", "mux_pixel_clk1", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_te_active &disp_pins_default>; @@ -389,6 +397,9 @@ qcom,dsi-supported-dfps-list = <60 57 55>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <534712320 532484352 530256384 525800448 528028416>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi index f9f1bff180b0..515cb56a5b7e 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,11 +18,14 @@ #clock-cells = <1>; reg = <0xae94a00 0x1e0>, <0xae94400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; + memory-region = <&dfps_data_memory>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; @@ -45,8 +48,10 @@ #clock-cells = <1>; reg = <0xae96a00 0x1e0>, <0xae96400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi index b1c2183a4562..ca96afac6846 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -503,8 +503,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-0"; cell-index = <0>; - reg = <0xae94400 0x7c0>; - reg-names = "dsi_phy"; + reg = <0xae94400 0x7c0>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; vdda-0p9-supply = <&pm6150_l4>; qcom,platform-strength-ctrl = [55 03 55 03 @@ -535,8 +536,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-1"; cell-index = <1>; - reg = <0xae96400 0x7c0>; - reg-names = "dsi_phy"; + reg = <0xae96400 0x7c0>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; vdda-0p9-supply = <&pm6150_l4>; qcom,platform-strength-ctrl = [55 03 55 03 diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi index 88d938ad7980..0cf7ec7fc899 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -650,10 +650,15 @@ }; cont_splash_memory: cont_splash_region@9c000000 { - reg = <0x0 0x9c000000 0x0 0x02400000>; + reg = <0x0 0x9c000000 0x0 0x02300000>; label = "cont_splash_region"; }; + dfps_data_memory: dfps_data_region@9e300000 { + reg = <0x0 0x9e300000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; -- GitLab From ec554f88fded77826513f535272281ee0ab3c952 Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Wed, 23 Jan 2019 14:37:03 +0530 Subject: [PATCH 1089/1286] ion: return proper error value on allocation failure Return ENOMEM on allocation failure from ion_system_heap_allocate. The absence of this was resulting in ion_buffer_create to proceed further and thus causing a crash. Change-Id: I906b129b5fe1c74f7176116142085fbb47c3c834 Signed-off-by: Vinayak Menon --- drivers/staging/android/ion/ion_system_heap.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/android/ion/ion_system_heap.c b/drivers/staging/android/ion/ion_system_heap.c index 960fc18ba9ab..562eba5f46b2 100644 --- a/drivers/staging/android/ion/ion_system_heap.c +++ b/drivers/staging/android/ion/ion_system_heap.c @@ -2,7 +2,7 @@ * drivers/staging/android/ion/ion_system_heap.c * * Copyright (C) 2011 Google, Inc. - * Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -331,8 +331,10 @@ static int ion_system_heap_allocate(struct ion_heap *heap, goto err; table = kzalloc(sizeof(*table), GFP_KERNEL); - if (!table) + if (!table) { + ret = -ENOMEM; goto err_free_data_pages; + } ret = sg_alloc_table(table, i, GFP_KERNEL); if (ret) -- GitLab From c5080d7dd25114faa5711e4ea5df4f5ac7adcc7a Mon Sep 17 00:00:00 2001 From: Md Mansoor Ahmed Date: Tue, 13 Nov 2018 18:50:32 +0530 Subject: [PATCH 1090/1286] ARM: dts: msm: audio support with overlay disabled on sm6150 LE Include audio-overlay for non overlay targets. Change-Id: I332372deafc18381bef53229ca447459ef0d690e Signed-off-by: Md Mansoor Ahmed --- arch/arm64/boot/dts/qcom/sm6150-idp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150-idp.dts b/arch/arm64/boot/dts/qcom/sm6150-idp.dts index 66014ab30161..0b32f1756855 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-idp.dts +++ b/arch/arm64/boot/dts/qcom/sm6150-idp.dts @@ -14,6 +14,7 @@ #include "sm6150.dtsi" #include "sm6150-idp.dtsi" +#include "sm6150-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. SM6150 PM6150 IDP"; -- GitLab From c6ad6822dc385b8135ba2526ee9d1fca3e509c42 Mon Sep 17 00:00:00 2001 From: Mohammed Javid Date: Fri, 11 Jan 2019 12:36:48 +0530 Subject: [PATCH 1091/1286] ARM: dts: msm: disable ipa for sa6155 and sa6155p IPA is not required on SA platforms. Make a change to disable IPA node. Change-Id: I666279e9af26a8145845046436df545a23590bae Acked-by: Chaitanya Pratapa Signed-off-by: Mohammed Javid --- arch/arm64/boot/dts/qcom/sa6155.dtsi | 11 ++++++++++- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 8 ++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155.dtsi b/arch/arm64/boot/dts/qcom/sa6155.dtsi index 73ca4eb69ecb..9a7030834a70 100644 --- a/arch/arm64/boot/dts/qcom/sa6155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -242,8 +242,17 @@ compatible = "qcom,msm-ext-disp-audio-codec-rx"; }; }; + + qcom,rmnet-ipa { + status="disabled"; + }; }; +&ipa_hw { + status="disabled"; +}; + + &mdss_dsi_phy0 { qcom,panel-force-clock-lane-hs; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 3ce74a06c637..be2818a67d23 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -23,6 +23,14 @@ aliases { pci-domain0 = &pcie0; /* PCIe0 domain */ }; + + qcom,rmnet-ipa { + status="disabled"; + }; +}; + +&ipa_hw { + status="disabled"; }; /* Delete second instance of pm6155 definitions for APQ version */ -- GitLab From 86d48dcf2f40ade4285e7d1d7c9da8e574d3bb06 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 24 Jan 2019 16:33:00 +0530 Subject: [PATCH 1092/1286] ARM: dts: msm: Correct BCL Ibat thermal zones name for TRINKET Use correct BCL Ibat thermal zones name for Ibat cooling device binding for TRINKET. Change-Id: I1d2628f00b706c67722e0829c873bdd28cf196ad Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi index f4f823a1c115..815d349995e3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -284,7 +284,7 @@ }; }; - pm6125-ibat-lvl0 { + pmi632-ibat-lvl0 { cooling-maps { ibat_cpu0 { trip = <&pmi632_ibat_lvl0>; @@ -337,7 +337,7 @@ }; }; - pm6125-ibat-lvl1 { + pmi632-ibat-lvl1 { cooling-maps { ibat_cpu0 { trip = <&pmi632_ibat_lvl1>; -- GitLab From 95bdef6404a2c4b7b610bbe7e623b3c7bd66d832 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 24 Jan 2019 16:37:57 +0530 Subject: [PATCH 1093/1286] ARM: dts: msm: Enable backlight cooling device for TRINKET Add display backlight cooling device for TRINKET. This cooling device can be used for controlling the temperature due to backlight display. Change-Id: Ib09eb6583a6df30e1cdec3f53a5615ec6aa48eaf Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi index 815d349995e3..e9d73c24237f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -443,3 +443,7 @@ }; }; }; + +&mdss_mdp { + #cooling-cells = <2>; +}; -- GitLab From d9ac0e5b788a7728ba04efb68d263a1c0fcd13c7 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Wed, 5 Dec 2018 19:57:52 +0530 Subject: [PATCH 1094/1286] iommu: arm-smmu: clear sid in DEBUG_SID_HALT_REG during ecats Clear the SID bits in the DEBUG_SID_HALT_REG register, so it will not carry the old value. Consider a case where doing ecats with sid = 7 in first iteration and then sid = 0 in the second iteration. The existing code still trigger a transaction with sid = 7 as we are not masking off the respective bits. Change-Id: Ib646533ec7a986ef541275ef95bc089111d5e335 Signed-off-by: Charan Teja Reddy Signed-off-by: Prakash Gupta --- drivers/iommu/arm-smmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index e63faa4b9a33..d4a85539fcca 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -5317,6 +5317,7 @@ static phys_addr_t qsmmuv500_iova_to_phys( redo: /* Set address and stream-id */ val = readq_relaxed(tbu->base + DEBUG_SID_HALT_REG); + val &= ~DEBUG_SID_HALT_SID_MASK; val |= sid & DEBUG_SID_HALT_SID_MASK; writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG); writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG); @@ -5379,6 +5380,9 @@ static phys_addr_t qsmmuv500_iova_to_phys( /* Reset hardware */ writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG); writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG); + val = readl_relaxed(tbu->base + DEBUG_SID_HALT_REG); + val &= ~DEBUG_SID_HALT_SID_MASK; + writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG); /* * After a failed translation, the next successful translation will -- GitLab From 94c997120d41baa1c1393b48865e21ee997c9990 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Thu, 24 Jan 2019 17:39:01 +0530 Subject: [PATCH 1095/1286] iommu/of: return -EPROBE_DEFER when smmu driver is not registered Return -EPROBE_DEFER from of_iommu_xlate() for the smmu client devices that are on the platform bus but trying to register their drivers before SMMU driver registration happens. Without this deferral probe can result into a situation of not adding the smmu clients to any of the iommu groups thus can't use iommu_*() services. Change-Id: I7b9da4ea1bc3bdcfb17e3c81b85938d50544fb9d Signed-off-by: Charan Teja Reddy --- drivers/iommu/of_iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 50947ebb6d17..7b6b248d94a6 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -119,6 +119,14 @@ static int of_iommu_xlate(struct device *dev, int err; ops = iommu_ops_from_fwnode(fwnode); + /* + * Return -EPROBE_DEFER for the platform devices which are dependent + * on the SMMU driver registration. Deferring from here helps in adding + * the clients in proper iommu groups. + */ + if (!dev_is_pci(dev) && of_device_is_available(iommu_spec->np) && !ops) + return -EPROBE_DEFER; + if ((ops && !ops->of_xlate) || !of_device_is_available(iommu_spec->np) || (!ops && !of_iommu_driver_present(iommu_spec->np))) -- GitLab From 696ae1695661445f644c86af0a23af465988b68f Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Thu, 24 Jan 2019 18:48:38 +0530 Subject: [PATCH 1096/1286] ARM: dts: msm: Fix jeita config for qg-ascent battery profile Correct the soft jeita hysteresis thresholds for qgauge 3450mAh ascent battery data profile. Change-Id: Iaa80ba2f334922d732e311686eec4c948985a656 Signed-off-by: Umang Agrawal --- arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi b/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi index e8dff3cad2cd..8095f0cbf680 100644 --- a/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi +++ b/arch/arm64/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi @@ -32,7 +32,7 @@ qcom,ascent_3450mah { qcom,jeita-hard-thresholds = <0x4aa5 0x1bfb>; /* COOL hys = 8 DegC, WARM hys = 37 DegC */ - qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>; + qcom,jeita-soft-hys-thresholds = <0x4126 0x223e>; qcom,jeita-soft-fcc-ua = <1725000 2760000>; qcom,jeita-soft-fv-uv = <4250000 4250000>; -- GitLab From 2010354f01480404535801742fb2dcbbe0e015d6 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Thu, 24 Jan 2019 15:39:03 +0530 Subject: [PATCH 1097/1286] ARM: dts: msm: update clock names as per latest driver Update clock names as per latest driver changes for TRINKET, sm6150, sdmmagpie, sa6155, sa6155p, sa8155 and sm8150 targets. Change-Id: I678a562ac545deaeaad417e879864a80859410c1 Signed-off-by: Tharun Raj Soma Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/sa6155.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sa8155.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8150-hdk-overlay.dts | 4 ++-- arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi | 9 ++++----- 7 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155.dtsi b/arch/arm64/boot/dts/qcom/sa6155.dtsi index 73ca4eb69ecb..2459f19a4e8f 100644 --- a/arch/arm64/boot/dts/qcom/sa6155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -196,7 +196,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_ext_bridge_1080p>; }; @@ -210,7 +210,7 @@ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, <&mdss_dsi0_pll PIX0_MUX_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-display-list = diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 3ce74a06c637..22e4aaa2b4bb 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -262,7 +262,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_ext_bridge_1080p>; }; @@ -276,7 +276,7 @@ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, <&mdss_dsi0_pll PIX0_MUX_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-display-list = diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index 37cc7aafcd47..a3bcd3085432 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -527,7 +527,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_ext_bridge_1080p>; }; @@ -539,7 +539,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_ext_bridge_1080p>; }; @@ -555,8 +555,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-display-list = <&dsi_anx_7625_1>; @@ -585,8 +585,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-display-list = <&dsi_anx_7625_2>; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index e7bda760eb67..6e6c5cf43e2c 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -496,8 +496,7 @@ &dsi_rm69298_truly_amoled_video { qcom,mdss-dsi-t-clk-post = <0x0D>; qcom,mdss-dsi-t-clk-pre = <0x30>; - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 57 55>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi index d8b535a97cd3..33a0a4e69deb 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi @@ -179,7 +179,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4330_truly_video>; }; @@ -190,7 +190,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4330_truly_cmd>; }; @@ -201,7 +201,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_split_link_wuxga_video>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk-overlay.dts index 40af0120dd5a..9c77660f7ded 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -110,7 +110,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_ext_bridge_hdmi_1080p>; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi index d7e7beabde25..5e7b8d5ccd51 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde-display.dtsi @@ -94,7 +94,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4330_truly_video>; }; @@ -105,7 +105,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4330_truly_cmd>; }; @@ -118,7 +118,7 @@ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, <&mdss_dsi0_pll PIX0_MUX_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; @@ -177,8 +177,7 @@ &dsi_td4330_truly_video { qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x36>; - qcom,mdss-dsi-min-refresh-rate = <48>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 55 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; -- GitLab From 80ced834e430d275e54b018fa4c32ae901e2d014 Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Thu, 24 Jan 2019 15:53:19 +0530 Subject: [PATCH 1098/1286] ARM: dts: msm: Add support for btfm audio in trinket During bringup for trinket target, btfm support was removed. Remove the respective property reset setting to enable it back. Change-Id: Idb884383433062e0a79a582bacfe98cdb260b901 Signed-off-by: Aditya Bavanari --- arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi index 0ba63ab04d33..da5753a4ca12 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -184,7 +184,6 @@ qcom,model = "trinket-idp-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; qcom,ext-disp-audio-rx = <0>; - qcom,wcn-btfm = <0>; qcom,audio-routing = "AMIC2", "MIC BIAS2", "MIC BIAS2", "Analog Mic2", -- GitLab From 5a1f5d3d2d2bb836e0a98073a51eb9bb801cbd2f Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Thu, 24 Jan 2019 19:56:05 +0200 Subject: [PATCH 1099/1286] msm: ipa: print only accessible registers on AP crash On AP crash, only accessible IPA registers need to be printed. Change-Id: Ic642375ce00fa7e276184146acdfc656006b60ca Signed-off-by: Ghanim Fodi --- .../platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c index ff33340f960d..e9c0d7b0fe2b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -2390,8 +2390,8 @@ static void ipareg_parse_coal_qmap_cfg(enum ipahal_reg_name reg, * @parse - CB to parse register value to abstracted structure * @offset - register offset relative to base address * @n_ofst - N parameterized register sub-offset - * @n_start - starting n for n_registers - * @n_end - ending n for n_registers + * @n_start - starting n for n_registers used for printing + * @n_end - ending n for n_registers used for printing * @en_print - enable this register to be printed when the device crashes */ struct ipahal_reg_obj { @@ -2692,16 +2692,16 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { /* IPAv4.0 */ [IPA_HW_v4_0][IPA_SUSPEND_IRQ_INFO_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003030, 0x1000, 0, 1, 1}, + 0x00003030, 0x1000, 0, 0, 1}, [IPA_HW_v4_0][IPA_SUSPEND_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003034, 0x1000, 0, 1, 1}, + 0x00003034, 0x1000, 0, 0, 1}, [IPA_HW_v4_0][IPA_SUSPEND_IRQ_CLR_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x00003038, 0x1000, 0, 1, 1}, + 0x00003038, 0x1000, 0, 0, 1}, [IPA_HW_v4_0][IPA_IRQ_EN_EE_n] = { ipareg_construct_dummy, ipareg_parse_dummy, - 0x0000300c, 0x1000, 0, 1, 1}, + 0x0000300c, 0x1000, 0, 0, 1}, [IPA_HW_v4_0][IPA_TAG_TIMER] = { ipareg_construct_dummy, ipareg_parse_dummy, 0x00000060, 0, 0, 0, 1}, @@ -3177,7 +3177,7 @@ void ipahal_print_all_regs(bool print_to_dmesg) j = reg->n_start; - if (j == reg->n_end) { + if (j == reg->n_end && (reg->n_ofst == 0)) { if (print_to_dmesg) IPAHAL_DBG_REG("%s=0x%x\n", ipahal_reg_name_str(i), -- GitLab From dc5aa805f28603cc18197fcdfd1c09c3a347ec60 Mon Sep 17 00:00:00 2001 From: David Collins Date: Tue, 22 Jan 2019 17:26:40 -0800 Subject: [PATCH 1100/1286] defconfig: sdxprairie: enable fixed-regulator and gpio-regulator drivers Enable the fixed-regulator and gpio-regulator drivers so that regulator devices managed by multiple GPIOs can be used. Change-Id: Id707f654fb8414162a9aa9a6482ee2c330ca5154 Signed-off-by: David Collins --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 2 ++ arch/arm/configs/vendor/sdxprairie_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index db545d3002c0..3d14afa01755 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -243,6 +243,8 @@ CONFIG_THERMAL_TSENS=y CONFIG_QTI_ADC_TM=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_RPMH=y CONFIG_REGULATOR_STUB=y CONFIG_SOUND=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 73a39d2ffece..d63a3fbf8ca4 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -234,6 +234,8 @@ CONFIG_THERMAL_TSENS=y CONFIG_QTI_ADC_TM=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_RPMH=y CONFIG_REGULATOR_STUB=y CONFIG_FB=y -- GitLab From b358ff87e36d0f11372dd89b0320d8d1282a8bb8 Mon Sep 17 00:00:00 2001 From: David Collins Date: Tue, 22 Jan 2019 18:09:41 -0800 Subject: [PATCH 1101/1286] ARM: dts: msm: add SD card regulator devices for sdxprairie Add regulator devices for the external gpio-controlled regulators which power the SD card slot on sdxprairie boards. Change-Id: Ie8ef9bb9d6c59a90e8cdfe00409f36ca20c2609c Signed-off-by: David Collins --- .../boot/dts/qcom/sdxprairie-regulator.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi index c6077a23628a..db5c96cb5716 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -11,6 +11,7 @@ */ #include +#include &soc { /* RPMh regulators */ @@ -451,4 +452,25 @@ qcom,set = ; }; }; + + vreg_vddpx_2: vddpx2-gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpio = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, + <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + }; + + vreg_sd_vdd: sd-vdd-fixed-regulator { + compatible = "qcom,stub-regulator"; + regulator-name = "sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + parent-supply = <&vreg_vddpx_2>; + }; }; -- GitLab From bcfab5734ab3d7680e36dfda445c358d464f03e4 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 17 May 2018 15:17:33 -0700 Subject: [PATCH 1102/1286] fs/proc: simplify and clarify get_mm_cmdline() function We have some very odd semantics for reading the command line through /proc, because we allow people to rewrite their own command line pretty much at will, and things get positively funky when you extend your command line past the point that used to be the end of the command line, and is now in the environment variable area. But our weird semantics doesn't mean that we should write weird and complex code to handle them. So re-write get_mm_cmdline() to be much simpler, and much more explicit about what it is actually doing and why. And avoid the extra check for "is there a NUL character at the end of the command line where I expect one to be", by simply making the NUL character handling be part of the normal "once you hit the end of the command line, stop at the first NUL character" logic. It's quite possible that we should stop the crazy "walk into environment" entirely, but happily it's not really the usual case. NOTE! We tried to really simplify and limit our odd cmdline parsing some time ago, but people complained. See commit c2c0bb44620d ("proc: fix PAGE_SIZE limit of /proc/$PID/cmdline") for details about why we have this complexity. Change-Id: Ifacdf9f2cfb212f10292aa24eb2620330fd6cd93 Cc: Tejun Heo Cc: Alexey Dobriyan Cc: Jarod Wilson Signed-off-by: Linus Torvalds Git-commit: 5ab8271899658042fabc5ae7e6a99066a210bc0e Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [sramana@codeaurora.org: resolve trivial merge conflicts] Signed-off-by: Srinivas Ramana --- fs/proc/base.c | 186 +++++++++++++++++-------------------------------- 1 file changed, 65 insertions(+), 121 deletions(-) diff --git a/fs/proc/base.c b/fs/proc/base.c index 64501ad7b1f3..1d6dcfbac4e6 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -209,24 +209,16 @@ static int proc_root_link(struct dentry *dentry, struct path *path) } static ssize_t get_mm_cmdline(struct mm_struct *mm, char __user *buf, - size_t _count, loff_t *pos) + size_t count, loff_t *ppos) { - char *page; - unsigned long count = _count; unsigned long arg_start, arg_end, env_start, env_end; - unsigned long len1, len2, len; - unsigned long p; - char c; - ssize_t rv; + unsigned long pos, len; + char *page; /* Check if process spawned far enough to have cmdline. */ if (!mm->env_end) return 0; - page = (char *)__get_free_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - down_read(&mm->mmap_sem); arg_start = mm->arg_start; arg_end = mm->arg_end; @@ -234,126 +226,78 @@ static ssize_t get_mm_cmdline(struct mm_struct *mm, char __user *buf, env_end = mm->env_end; up_read(&mm->mmap_sem); - BUG_ON(arg_start > arg_end); - BUG_ON(env_start > env_end); - - len1 = arg_end - arg_start; - len2 = env_end - env_start; + if (arg_start >= arg_end) + return 0; - /* Empty ARGV. */ - if (len1 == 0) { - rv = 0; - goto out_free_page; - } /* - * Inherently racy -- command line shares address space - * with code and data. + * We have traditionally allowed the user to re-write + * the argument strings and overflow the end result + * into the environment section. But only do that if + * the environment area is contiguous to the arguments. */ - rv = access_remote_vm(mm, arg_end - 1, &c, 1, FOLL_ANON); - if (rv <= 0) - goto out_free_page; - - rv = 0; - - if (c == '\0') { - /* Command line (set of strings) occupies whole ARGV. */ - if (len1 <= *pos) - goto out_free_page; - - p = arg_start + *pos; - len = len1 - *pos; - while (count > 0 && len > 0) { - unsigned int _count; - int nr_read; - - _count = min3(count, len, PAGE_SIZE); - nr_read = access_remote_vm(mm, p, page, _count, FOLL_ANON); - if (nr_read < 0) - rv = nr_read; - if (nr_read <= 0) - goto out_free_page; - - if (copy_to_user(buf, page, nr_read)) { - rv = -EFAULT; - goto out_free_page; - } + if (env_start != arg_end || env_start >= env_end) + env_start = env_end = arg_end; - p += nr_read; - len -= nr_read; - buf += nr_read; - count -= nr_read; - rv += nr_read; - } - } else { - /* - * Command line (1 string) occupies ARGV and - * extends into ENVP. - */ - struct { - unsigned long p; - unsigned long len; - } cmdline[2] = { - { .p = arg_start, .len = len1 }, - { .p = env_start, .len = len2 }, - }; - loff_t pos1 = *pos; - unsigned int i; - - i = 0; - while (i < 2 && pos1 >= cmdline[i].len) { - pos1 -= cmdline[i].len; - i++; + /* We're not going to care if "*ppos" has high bits set */ + pos = arg_start + *ppos; + + /* .. but we do check the result is in the proper range */ + if (pos < arg_start || pos >= env_end) + return 0; + + /* .. and we never go past env_end */ + if (env_end - pos < count) + count = env_end - pos; + + page = (char *)__get_free_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + len = 0; + while (count) { + int got; + size_t size = min_t(size_t, PAGE_SIZE, count); + + got = access_remote_vm(mm, pos, page, size, FOLL_ANON); + if (got <= 0) + break; + + /* Don't walk past a NUL character once you hit arg_end */ + if (pos + got >= arg_end) { + int n = 0; + + /* + * If we started before 'arg_end' but ended up + * at or after it, we start the NUL character + * check at arg_end-1 (where we expect the normal + * EOF to be). + * + * NOTE! This is smaller than 'got', because + * pos + got >= arg_end + */ + if (pos < arg_end) + n = arg_end - pos - 1; + + /* Cut off at first NUL after 'n' */ + got = n + strnlen(page+n, got-n); + if (!got) + break; } - while (i < 2) { - p = cmdline[i].p + pos1; - len = cmdline[i].len - pos1; - while (count > 0 && len > 0) { - unsigned int _count, l; - int nr_read; - bool final; - - _count = min3(count, len, PAGE_SIZE); - nr_read = access_remote_vm(mm, p, page, _count, FOLL_ANON); - if (nr_read < 0) - rv = nr_read; - if (nr_read <= 0) - goto out_free_page; - - /* - * Command line can be shorter than whole ARGV - * even if last "marker" byte says it is not. - */ - final = false; - l = strnlen(page, nr_read); - if (l < nr_read) { - nr_read = l; - final = true; - } - - if (copy_to_user(buf, page, nr_read)) { - rv = -EFAULT; - goto out_free_page; - } - - p += nr_read; - len -= nr_read; - buf += nr_read; - count -= nr_read; - rv += nr_read; - - if (final) - goto out_free_page; - } - /* Only first chunk can be read partially. */ - pos1 = 0; - i++; + got -= copy_to_user(buf, page, got); + if (unlikely(!got)) { + if (!len) + len = -EFAULT; + break; } + pos += got; + buf += got; + len += got; + count -= got; } -out_free_page: free_page((unsigned long)page); - return rv; + return len; } static ssize_t get_task_cmdline(struct task_struct *tsk, char __user *buf, -- GitLab From 1022f84ec61fe728f774e8f3f5afa9959fdf7d46 Mon Sep 17 00:00:00 2001 From: Yang Shi Date: Thu, 7 Jun 2018 17:05:28 -0700 Subject: [PATCH 1103/1286] mm: introduce arg_lock to protect arg_start|end and env_start|end in mm_struct mmap_sem is on the hot path of kernel, and it very contended, but it is abused too. It is used to protect arg_start|end and evn_start|end when reading /proc/$PID/cmdline and /proc/$PID/environ, but it doesn't make sense since those proc files just expect to read 4 values atomically and not related to VM, they could be set to arbitrary values by C/R. And, the mmap_sem contention may cause unexpected issue like below: INFO: task ps:14018 blocked for more than 120 seconds. Tainted: G E 4.9.79-009.ali3000.alios7.x86_64 #1 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. ps D 0 14018 1 0x00000004 Call Trace: schedule+0x36/0x80 rwsem_down_read_failed+0xf0/0x150 call_rwsem_down_read_failed+0x18/0x30 down_read+0x20/0x40 proc_pid_cmdline_read+0xd9/0x4e0 __vfs_read+0x37/0x150 vfs_read+0x96/0x130 SyS_read+0x55/0xc0 entry_SYSCALL_64_fastpath+0x1a/0xc5 Both Alexey Dobriyan and Michal Hocko suggested to use dedicated lock for them to mitigate the abuse of mmap_sem. So, introduce a new spinlock in mm_struct to protect the concurrent access to arg_start|end, env_start|end and others, as well as replace write map_sem to read to protect the race condition between prctl and sys_brk which might break check_data_rlimit(), and makes prctl more friendly to other VM operations. This patch just eliminates the abuse of mmap_sem, but it can't resolve the above hung task warning completely since the later access_remote_vm() call needs acquire mmap_sem. The mmap_sem scalability issue will be solved in the future. Change-Id: Ifa8f001ee2fc4f0ce60c18e771cebcf8a1f0943e [yang.shi@linux.alibaba.com: add comment about mmap_sem and arg_lock] Link: http://lkml.kernel.org/r/1524077799-80690-1-git-send-email-yang.shi@linux.alibaba.com Link: http://lkml.kernel.org/r/1523730291-109696-1-git-send-email-yang.shi@linux.alibaba.com Signed-off-by: Yang Shi Reviewed-by: Cyrill Gorcunov Acked-by: Michal Hocko Cc: Alexey Dobriyan Cc: Matthew Wilcox Cc: Mateusz Guzik Cc: Kirill Tkhai Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Git-commit: 88aa7cc688d48ddd84558b41d5905a0db9535c4b Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Srinivas Ramana --- fs/proc/base.c | 8 ++++---- include/linux/mm_types.h | 2 ++ kernel/fork.c | 1 + kernel/sys.c | 10 ++++++++-- mm/init-mm.c | 1 + 5 files changed, 16 insertions(+), 6 deletions(-) diff --git a/fs/proc/base.c b/fs/proc/base.c index 1d6dcfbac4e6..498dc83f6d0f 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -219,12 +219,12 @@ static ssize_t get_mm_cmdline(struct mm_struct *mm, char __user *buf, if (!mm->env_end) return 0; - down_read(&mm->mmap_sem); + spin_lock(&mm->arg_lock); arg_start = mm->arg_start; arg_end = mm->arg_end; env_start = mm->env_start; env_end = mm->env_end; - up_read(&mm->mmap_sem); + spin_unlock(&mm->arg_lock); if (arg_start >= arg_end) return 0; @@ -902,10 +902,10 @@ static ssize_t environ_read(struct file *file, char __user *buf, if (!mmget_not_zero(mm)) goto free; - down_read(&mm->mmap_sem); + spin_lock(&mm->arg_lock); env_start = mm->env_start; env_end = mm->env_end; - up_read(&mm->mmap_sem); + spin_unlock(&mm->arg_lock); while (count > 0) { size_t this_len, max_len; diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 10bc2286b4c4..31eb56c07561 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -430,6 +430,8 @@ struct mm_struct { unsigned long exec_vm; /* VM_EXEC & ~VM_WRITE & ~VM_STACK */ unsigned long stack_vm; /* VM_STACK */ unsigned long def_flags; + + spinlock_t arg_lock; /* protect the below fields */ unsigned long start_code, end_code, start_data, end_data; unsigned long start_brk, brk, start_stack; unsigned long arg_start, arg_end, env_start, env_end; diff --git a/kernel/fork.c b/kernel/fork.c index d875b3d2f6b1..d9b3c6b93afe 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -828,6 +828,7 @@ static struct mm_struct *mm_init(struct mm_struct *mm, struct task_struct *p, mm->pinned_vm = 0; memset(&mm->rss_stat, 0, sizeof(mm->rss_stat)); spin_lock_init(&mm->page_table_lock); + spin_lock_init(&mm->arg_lock); mm_init_cpumask(mm); mm_init_aio(mm); mm_init_owner(mm, p); diff --git a/kernel/sys.c b/kernel/sys.c index 26a5cf02b094..990de67e4ec8 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -1954,7 +1954,11 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data return error; } - down_write(&mm->mmap_sem); + /* + * arg_lock protects concurent updates but we still need mmap_sem for + * read to exclude races with sys_brk. + */ + down_read(&mm->mmap_sem); /* * We don't validate if these members are pointing to @@ -1968,6 +1972,7 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data * to any problem in kernel itself */ + spin_lock(&mm->arg_lock); mm->start_code = prctl_map.start_code; mm->end_code = prctl_map.end_code; mm->start_data = prctl_map.start_data; @@ -1979,6 +1984,7 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data mm->arg_end = prctl_map.arg_end; mm->env_start = prctl_map.env_start; mm->env_end = prctl_map.env_end; + spin_unlock(&mm->arg_lock); /* * Note this update of @saved_auxv is lockless thus @@ -1991,7 +1997,7 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data if (prctl_map.auxv_size) memcpy(mm->saved_auxv, user_auxv, sizeof(user_auxv)); - up_write(&mm->mmap_sem); + up_read(&mm->mmap_sem); return 0; } #endif /* CONFIG_CHECKPOINT_RESTORE */ diff --git a/mm/init-mm.c b/mm/init-mm.c index e71ac37a98c4..228134f5a336 100644 --- a/mm/init-mm.c +++ b/mm/init-mm.c @@ -25,6 +25,7 @@ struct mm_struct init_mm = { .mm_count = ATOMIC_INIT(1), .mmap_sem = __RWSEM_INITIALIZER(init_mm.mmap_sem), .page_table_lock = __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock), + .arg_lock = __SPIN_LOCK_UNLOCKED(init_mm.arg_lock), .mmlist = LIST_HEAD_INIT(init_mm.mmlist), .user_ns = &init_user_ns, INIT_MM_CONTEXT(init_mm) -- GitLab From 4fe2e741b222dff907a31d1daaab2fba18316535 Mon Sep 17 00:00:00 2001 From: Josh Kirsch Date: Thu, 24 Jan 2019 14:11:24 -0800 Subject: [PATCH 1104/1286] defconfig: enabled CONFIG_SND_DYNAMIC_MINORS for sdxprairie target Enable defconfig to allow more than 8 sound cards registration. Change-Id: I80611675aa0ff0a01d94b463f3626cff19473a9b Signed-off-by: Josh Kirsch --- arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 73a39d2ffece..51c7ccc7a7bc 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -239,6 +239,7 @@ CONFIG_REGULATOR_STUB=y CONFIG_FB=y CONFIG_SOUND=y CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SOC=y CONFIG_UHID=y CONFIG_HID_APPLE=y -- GitLab From 65813dd071c89f78ac657bf7535e18a5ebe5f2c3 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 24 Jan 2019 14:24:13 -0800 Subject: [PATCH 1105/1286] ARM: dts: msm: Configure HW thermal mitigation on sdxprairie MTP Turn on HW-controlled mitigation of skin, die and connector temperatures. Change-Id: I3fcf310f24535a6484ae14d4d43f60734e7af203 Signed-off-by: Guru Das Srinagesh --- arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi index 82ce24e6fdb1..7ae66eda3e33 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -182,4 +182,7 @@ io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp"; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,hw-skin-temp-mitigation; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi index e989e2ddc80e..e5d7bd7388f7 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -200,6 +200,9 @@ qcom,suspend-input-on-debug-batt; qcom,hvdcp-autonomous-enable; qcom,usb-pd-disable; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,hw-skin-temp-mitigation; }; &pm8150b_fg { -- GitLab From a520a734291facee67d4c89f5f01e2466503041e Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Thu, 24 Jan 2019 14:21:03 -0800 Subject: [PATCH 1106/1286] ARM: dts: msm: Update USB QMP PHY configuration on sdxprairie Use fine tune configuration with USB QMP PHY on sdxprairie for better compliance and interoperability of USB gen1 and gen2. Change-Id: Id269975a821d01b6a03c68773d6ea829383dedba Signed-off-by: Mayank Rana --- arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi | 26 ++++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index 22a83f7c4c72..792f27832f39 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -193,6 +193,7 @@ USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0 USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0 + USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 @@ -201,14 +202,13 @@ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0 USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 - USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x8c 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xff 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x3f 0 USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xff 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xbc 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0 USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0 @@ -221,9 +221,9 @@ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0 - USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0 @@ -236,28 +236,28 @@ USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x00 0 USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 + USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0 - USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x00 0 USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x20 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x60 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x60 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x17 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0 USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0 USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0 USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 - USB3_UNI_PCS_EQ_CONFIG1 0x0d 0 + USB3_UNI_PCS_EQ_CONFIG1 0x4b 0 + USB3_UNI_PCS_EQ_CONFIG5 0x10 0 USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 - USB3_UNI_PCS_CDR_RESET_TIME 0x02 0 0xffffffff 0xffffffff 0x00>; qcom,qmp-phy-reg-offset = -- GitLab From b5de69d20853d81799a8bec88e813b9190a24392 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Thu, 24 Jan 2019 15:16:18 -0800 Subject: [PATCH 1107/1286] cnss2: Ignore triggering assert if device is already in bad state There is no need to handle firmware assert if device is already in bad state so just directly ignore it. Change-Id: I594754d8bbed3e6aefc8b2e859d4542def0b1aaf Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/pci.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index da611a6b2cf9..7b1a45267dee 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -1556,9 +1556,8 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) if (!plat_priv) return -ENODEV; - if (test_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state)) { - cnss_pr_err("RDDM already collected 0x%x, return\n", - pci_priv->mhi_state); + if (cnss_pci_is_device_down(&pci_priv->pci_dev->dev)) { + cnss_pr_info("Device is already in bad state, ignore force assert\n"); return 0; } @@ -2288,6 +2287,7 @@ static void cnss_pci_set_mhi_state_bit(struct cnss_pci_data *pci_priv, case CNSS_MHI_POWER_OFF: case CNSS_MHI_FORCE_POWER_OFF: clear_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state); + clear_bit(CNSS_MHI_TRIGGER_RDDM, &pci_priv->mhi_state); clear_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state); break; case CNSS_MHI_SUSPEND: @@ -2297,6 +2297,7 @@ static void cnss_pci_set_mhi_state_bit(struct cnss_pci_data *pci_priv, clear_bit(CNSS_MHI_SUSPEND, &pci_priv->mhi_state); break; case CNSS_MHI_TRIGGER_RDDM: + set_bit(CNSS_MHI_TRIGGER_RDDM, &pci_priv->mhi_state); break; case CNSS_MHI_RDDM_DONE: set_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state); -- GitLab From 45af158f69631792ae28695c7a7e16cf34934a17 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Thu, 24 Jan 2019 12:20:56 -0800 Subject: [PATCH 1108/1286] cnss2: Collect firmware dump after SMMU fault happens Currently, after enabling SMMU stage 1, SMMU driver will panic by default if there is a SMMU fault. Config SMMU driver not to panic for WLAN so that CNSS driver is able to collect firmware dump after SMMU fault. Fix misuse of error print API as well since they are in the same SMMU function. Change-Id: Ie457873210103eb4c4b5f4a68f0c08fe8a33fc80 Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/pci.c | 48 ++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index da611a6b2cf9..98adf67065f2 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -818,13 +818,25 @@ int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv) return 0; } +static int cnss_pci_smmu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, + int flags, void *handler_token) +{ + cnss_pr_err("SMMU fault happened with IOVA 0x%lx\n", iova); + + cnss_force_fw_assert(dev); + + /* IOMMU driver requires non-zero return value to print debug info. */ + return -EINVAL; +} + static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) { int ret = 0; struct device *dev; struct dma_iommu_mapping *mapping; int atomic_ctx = 1, s1_bypass = 1, fast = 1, cb_stall_disable = 1, - no_cfre = 1; + no_cfre = 1, non_fatal_faults = 1; cnss_pr_dbg("Initializing SMMU\n"); @@ -846,8 +858,8 @@ static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) DOMAIN_ATTR_ATOMIC, &atomic_ctx); if (ret) { - pr_err("Failed to set SMMU atomic_ctx attribute, err = %d\n", - ret); + cnss_pr_err("Failed to set SMMU atomic_ctx attribute, err = %d\n", + ret); goto release_mapping; } @@ -855,8 +867,8 @@ static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) DOMAIN_ATTR_FAST, &fast); if (ret) { - pr_err("Failed to set SMMU fast attribute, err = %d\n", - ret); + cnss_pr_err("Failed to set SMMU fast attribute, err = %d\n", + ret); goto release_mapping; } @@ -864,8 +876,8 @@ static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) DOMAIN_ATTR_CB_STALL_DISABLE, &cb_stall_disable); if (ret) { - pr_err("Failed to set SMMU cb_stall_disable attribute, err = %d\n", - ret); + cnss_pr_err("Failed to set SMMU cb_stall_disable attribute, err = %d\n", + ret); goto release_mapping; } @@ -873,24 +885,36 @@ static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) DOMAIN_ATTR_NO_CFRE, &no_cfre); if (ret) { - pr_err("Failed to set SMMU no_cfre attribute, err = %d\n", - ret); + cnss_pr_err("Failed to set SMMU no_cfre attribute, err = %d\n", + ret); goto release_mapping; } + + ret = iommu_domain_set_attr(mapping->domain, + DOMAIN_ATTR_NON_FATAL_FAULTS, + &non_fatal_faults); + if (ret) { + cnss_pr_err("Failed to set SMMU non_fatal_faults attribute, err = %d\n", + ret); + goto release_mapping; + } + + iommu_set_fault_handler(mapping->domain, + cnss_pci_smmu_fault_handler, pci_priv); } else { ret = iommu_domain_set_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, &s1_bypass); if (ret) { - pr_err("Failed to set SMMU s1_bypass attribute, err = %d\n", - ret); + cnss_pr_err("Failed to set SMMU s1_bypass attribute, err = %d\n", + ret); goto release_mapping; } } ret = arm_iommu_attach_device(dev, mapping); if (ret) { - pr_err("Failed to attach SMMU device, err = %d\n", ret); + cnss_pr_err("Failed to attach SMMU device, err = %d\n", ret); goto release_mapping; } -- GitLab From 3a1c32616162f3f608743ba5ccb8a29ad8402fe1 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Wed, 16 Jan 2019 11:31:46 +0530 Subject: [PATCH 1109/1286] icnss: Defer modem graceful shutdown until probe complete In case WLAN driver probe is in progress and modem graceful shutdown occurs and if modem shutdown request is sent just before the mode on request sent to firmware, firmware may end up in illegal memory access. To address this issue, modem notifier needs to be blocked needs for probe to complete or max 5 seconds timeout. CRs-Fixed: 2381846 Change-Id: I9e13a11c56059cb29e161c34df11de484f87ac5e Signed-off-by: Anurag Chouhan --- drivers/soc/qcom/icnss.c | 30 +++++++++++++++++++++++++++++- drivers/soc/qcom/icnss_private.h | 4 +++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c index 79d73184bf34..2bda7f1c3c99 100644 --- a/drivers/soc/qcom/icnss.c +++ b/drivers/soc/qcom/icnss.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -66,6 +66,8 @@ #define ICNSS_QUIRKS_DEFAULT BIT(FW_REJUVENATE_ENABLE) #define ICNSS_MAX_PROBE_CNT 2 +#define PROBE_TIMEOUT 5000 + static struct icnss_priv *penv; unsigned long quirks = ICNSS_QUIRKS_DEFAULT; @@ -883,6 +885,8 @@ static int icnss_call_driver_probe(struct icnss_priv *priv) icnss_hw_power_on(priv); + set_bit(ICNSS_DRIVER_LOADING, &priv->state); + reinit_completion(&penv->driver_probed); while (probe_cnt < ICNSS_MAX_PROBE_CNT) { ret = priv->ops->probe(&priv->pdev->dev); probe_cnt++; @@ -892,9 +896,13 @@ static int icnss_call_driver_probe(struct icnss_priv *priv) if (ret < 0) { icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n", ret, priv->state, probe_cnt); + complete(&penv->driver_probed); + clear_bit(ICNSS_DRIVER_LOADING, &penv->state); goto out; } + complete(&penv->driver_probed); + clear_bit(ICNSS_DRIVER_LOADING, &priv->state); set_bit(ICNSS_DRIVER_PROBED, &priv->state); return 0; @@ -1033,6 +1041,8 @@ static int icnss_driver_event_register_driver(void *data) if (ret) goto out; + set_bit(ICNSS_DRIVER_LOADING, &penv->state); + reinit_completion(&penv->driver_probed); while (probe_cnt < ICNSS_MAX_PROBE_CNT) { ret = penv->ops->probe(&penv->pdev->dev); probe_cnt++; @@ -1042,9 +1052,13 @@ static int icnss_driver_event_register_driver(void *data) if (ret) { icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n", ret, penv->state, probe_cnt); + clear_bit(ICNSS_DRIVER_LOADING, &penv->state); + complete(&penv->driver_probed); goto power_off; } + complete(&penv->driver_probed); + clear_bit(ICNSS_DRIVER_LOADING, &penv->state); set_bit(ICNSS_DRIVER_PROBED, &penv->state); return 0; @@ -1269,6 +1283,13 @@ static int icnss_modem_notifier_nb(struct notifier_block *nb, if (code != SUBSYS_BEFORE_SHUTDOWN) return NOTIFY_OK; + if (code == SUBSYS_BEFORE_SHUTDOWN && !notif->crashed && + test_bit(ICNSS_DRIVER_LOADING, &priv->state)) { + if (!wait_for_completion_timeout(&priv->driver_probed, + PROBE_TIMEOUT)) + icnss_pr_err("wlan driver probe timeout\n"); + } + if (code == SUBSYS_BEFORE_SHUTDOWN && !notif->crashed) { ret = wlfw_send_modem_shutdown_msg(priv); if (ret < 0) @@ -2579,6 +2600,9 @@ static int icnss_stats_show_state(struct seq_file *s, struct icnss_priv *priv) continue; case ICNSS_MODE_ON: seq_puts(s, "MODE ON DONE"); + continue; + case ICNSS_DRIVER_LOADING: + seq_puts(s, "WLAN DRIVER LOADING"); } seq_printf(s, "UNKNOWN-%d", i); @@ -3202,6 +3226,8 @@ static int icnss_probe(struct platform_device *pdev) penv = priv; + init_completion(&priv->driver_probed); + icnss_pr_info("Platform driver probed successfully\n"); return 0; @@ -3224,6 +3250,8 @@ static int icnss_remove(struct platform_device *pdev) icnss_debugfs_destroy(penv); + complete_all(&penv->driver_probed); + icnss_modem_ssr_unregister_notifier(penv); destroy_ramdump_device(penv->msa0_dump_dev); diff --git a/drivers/soc/qcom/icnss_private.h b/drivers/soc/qcom/icnss_private.h index 4d524e7f4197..f7c0e8327806 100644 --- a/drivers/soc/qcom/icnss_private.h +++ b/drivers/soc/qcom/icnss_private.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -156,6 +156,7 @@ enum icnss_driver_state { ICNSS_DRIVER_UNLOADING, ICNSS_REJUVENATE, ICNSS_MODE_ON, + ICNSS_DRIVER_LOADING, }; struct ce_irq_list { @@ -354,6 +355,7 @@ struct icnss_priv { bool is_hyp_disabled; uint32_t fw_error_fatal_irq; uint32_t fw_early_crash_irq; + struct completion driver_probed; char function_name[WLFW_FUNCTION_NAME_LEN + 1]; }; -- GitLab From f7b254d9da74416a41ccb88b7d7485436f40b83a Mon Sep 17 00:00:00 2001 From: xianzhu Date: Thu, 24 Jan 2019 14:31:15 +0800 Subject: [PATCH 1110/1286] defconfig: enable boot time marker driver for sa8155 target Enable this driver for start-up time measurement. Change-Id: Ia9632eb72c5c9f1ff08cabc16777e22b3d8df580 Signed-off-by: xianzhu --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 1 + arch/arm64/configs/vendor/sa8155_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index 1e84758c900f..c00a4ab31dff 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -533,6 +533,7 @@ CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y CONFIG_MSM_BOOT_STATS=y +CONFIG_MSM_BOOT_TIME_MARKER=y CONFIG_QCOM_DCC_V2=y CONFIG_QCOM_SECURE_BUFFER=y CONFIG_QCOM_EUD=y diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index ac5b78b6e571..4005e7d49b10 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -557,6 +557,7 @@ CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y CONFIG_MSM_BOOT_STATS=y +CONFIG_MSM_BOOT_TIME_MARKER=y CONFIG_MSM_CORE_HANG_DETECT=y CONFIG_QCOM_DCC_V2=y CONFIG_MSM_GLADIATOR_HANG_DETECT=y -- GitLab From e9465353bd835e981141471e2a62be1c9f91ce35 Mon Sep 17 00:00:00 2001 From: Gaurav Singhal Date: Tue, 18 Dec 2018 19:31:44 +0530 Subject: [PATCH 1111/1286] NFC: Keep VEN gpio always high from boot VEN will be toggled from NFC driver only once during boot and it will remain high on successful driver probe exit, after that MW shouldn't modify it's state as eSE is also powered using VEN gpio in SN100 NFC HW. VEN toggle will reset eSE power and cause failure if any communication is in progress. Change-Id: Id1c75a47017e53cc9d597e8d307a80a667207f74 Signed-off-by: Gaurav Singhal --- drivers/nfc/nq-nci.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/nfc/nq-nci.c b/drivers/nfc/nq-nci.c index fc4ace7584c5..47a01dff17e5 100644 --- a/drivers/nfc/nq-nci.c +++ b/drivers/nfc/nq-nci.c @@ -501,6 +501,7 @@ int nfc_ioctl_power_states(struct file *filp, unsigned long arg) gpio_set_value(nqx_dev->en_gpio, 0); usleep_range(10000, 10100); } + if (nqx_dev->pdata->clk_pin_voting) { r = nqx_clock_deselect(nqx_dev); if (r < 0) @@ -516,8 +517,14 @@ int nfc_ioctl_power_states(struct file *filp, unsigned long arg) gpio_set_value(nqx_dev->firm_gpio, 0); usleep_range(10000, 10100); } - gpio_set_value(nqx_dev->en_gpio, 1); - usleep_range(10000, 10100); + + if (gpio_get_value(nqx_dev->en_gpio)) { + dev_dbg(&nqx_dev->client->dev, "VEN gpio already high\n"); + } else { + gpio_set_value(nqx_dev->en_gpio, 1); + usleep_range(10000, 10100); + } + if (nqx_dev->pdata->clk_pin_voting) { r = nqx_clock_select(nqx_dev); if (r < 0) @@ -887,8 +894,6 @@ static int nfcc_hw_check(struct i2c_client *client, struct nqx_dev *nqx_dev) break; } - /*Disable NFC by default to save power on boot*/ - gpio_set_value(enable_gpio, 0);/* ULPM: Disable */ ret = 0; goto done; -- GitLab From c203ccdbba3b27387a54612c9b4153cf6fa691ce Mon Sep 17 00:00:00 2001 From: Bhuvan Varshney Date: Thu, 3 Jan 2019 21:17:45 +0530 Subject: [PATCH 1112/1286] NFC: Add support for SN100 eSE power management Enable support for eSE power management from secure element HAL service and make sure VEN is not HIGH after boot. Change-Id: I0740681a62cc879eaf696358592b750332afe992 Signed-off-by: Bhuvan Varshney --- drivers/nfc/nq-nci.c | 66 ++++++++++++++++++++++++++++++++++++++++++-- drivers/nfc/nq-nci.h | 4 ++- 2 files changed, 66 insertions(+), 4 deletions(-) diff --git a/drivers/nfc/nq-nci.c b/drivers/nfc/nq-nci.c index 47a01dff17e5..cfdbe5959370 100644 --- a/drivers/nfc/nq-nci.c +++ b/drivers/nfc/nq-nci.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -329,6 +329,52 @@ static int nqx_standby_write(struct nqx_dev *nqx_dev, return ret; } +/* + * Power management of the SN100 eSE + * eSE and NFCC both are powered using VEN gpio in SN100, + * VEN HIGH - eSE and NFCC both are powered on + * VEN LOW - eSE and NFCC both are power down + */ +static int sn100_ese_pwr(struct nqx_dev *nqx_dev, unsigned long int arg) +{ + int r = -1; + + if (arg == 0) { + /** + * Let's store the NFC VEN pin state + * will check stored value in case of eSE power off request, + * to find out if NFC MW also sent request to set VEN HIGH + * VEN state will remain HIGH if NFC is enabled otherwise + * it will be set as LOW + */ + nqx_dev->nfc_ven_enabled = + gpio_get_value(nqx_dev->en_gpio); + if (!nqx_dev->nfc_ven_enabled) { + dev_dbg(&nqx_dev->client->dev, "eSE HAL service setting en_gpio HIGH\n"); + gpio_set_value(nqx_dev->en_gpio, 1); + /* hardware dependent delay */ + usleep_range(1000, 1100); + } else { + dev_dbg(&nqx_dev->client->dev, "en_gpio already HIGH\n"); + } + r = 0; + } else if (arg == 1) { + if (!nqx_dev->nfc_ven_enabled) { + dev_dbg(&nqx_dev->client->dev, "NFC not enabled, disabling en_gpio\n"); + gpio_set_value(nqx_dev->en_gpio, 0); + /* hardware dependent delay */ + usleep_range(1000, 1100); + } else { + dev_dbg(&nqx_dev->client->dev, "keep en_gpio high as NFC is enabled\n"); + } + r = 0; + } else if (arg == 3) { + // eSE power state + r = gpio_get_value(nqx_dev->en_gpio); + } + return r; +} + /* * Power management of the eSE * NFC & eSE ON : NFC_EN high and eSE_pwr_req high. @@ -653,16 +699,28 @@ static long nfc_ioctl(struct file *pfile, unsigned int cmd, unsigned long arg) { int r = 0; + struct nqx_dev *nqx_dev = pfile->private_data; + + if (!nqx_dev) + return -ENODEV; switch (cmd) { case NFC_SET_PWR: r = nfc_ioctl_power_states(pfile, arg); break; case ESE_SET_PWR: - r = nqx_ese_pwr(pfile->private_data, arg); + if ((nqx_dev->nqx_info.info.chip_type == NFCC_SN100_A) || + (nqx_dev->nqx_info.info.chip_type == NFCC_SN100_B)) + r = sn100_ese_pwr(nqx_dev, arg); + else + r = nqx_ese_pwr(nqx_dev, arg); break; case ESE_GET_PWR: - r = nqx_ese_pwr(pfile->private_data, 3); + if ((nqx_dev->nqx_info.info.chip_type == NFCC_SN100_A) || + (nqx_dev->nqx_info.info.chip_type == NFCC_SN100_B)) + r = sn100_ese_pwr(nqx_dev, 3); + else + r = nqx_ese_pwr(nqx_dev, 3); break; case SET_RX_BLOCK: break; @@ -894,6 +952,8 @@ static int nfcc_hw_check(struct i2c_client *client, struct nqx_dev *nqx_dev) break; } + /*Disable NFC by default to save power on boot*/ + gpio_set_value(enable_gpio, 0);/* ULPM: Disable */ ret = 0; goto done; diff --git a/drivers/nfc/nq-nci.h b/drivers/nfc/nq-nci.h index 5cbb06c0bea3..ba8a8eba1ade 100644 --- a/drivers/nfc/nq-nci.h +++ b/drivers/nfc/nq-nci.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,6 +48,8 @@ enum nfcc_chip_variant { NFCC_NQ_220 = 0x58, /**< NFCC NQ220 */ NFCC_NQ_310 = 0x40, /**< NFCC NQ310 */ NFCC_NQ_330 = 0x51, /**< NFCC NQ330 */ + NFCC_SN100_A = 0xa3, /**< NFCC SN100_A */ + NFCC_SN100_B = 0xa4, /**< NFCC SN100_B */ NFCC_PN66T = 0x18, /**< NFCC PN66T */ NFCC_NOT_SUPPORTED = 0xFF /**< NFCC is not supported */ }; -- GitLab From 12799000e8b647c93a5c63cdfc9d8eb0315d9aee Mon Sep 17 00:00:00 2001 From: Xiaojun Sang Date: Fri, 25 Jan 2019 13:08:09 +0800 Subject: [PATCH 1113/1286] ARM: dts: msm: add sound node entry for qrd trinket add trinket-qrd-specific info in device tree. Change-Id: Id63a773cb47b2a809f008b9d9c3a3d028d4bb74d Signed-off-by: Xiaojun Sang --- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 8a01883274d1..890ea574b07f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -14,6 +14,7 @@ #include #include #include "trinket-sde-display.dtsi" +#include "trinket-audio-overlay.dtsi" #include &qupv3_se1_i2c { @@ -284,3 +285,43 @@ &pm6125_pwm { status = "ok"; }; + +&sm6150_snd { + status = "okay"; + qcom,model = "trinket-qrd-snd-card"; + qcom,audio-routing = + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "Analog Mic1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "Analog Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "TX SWR_ADC3", "ADC3_OUTPUT", + "SpkrLeft IN", "WSA_SPK1 OUT", + "WSA_SPK1 OUT", "VA_MCLK"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,codec-max-aux-devs = <1>; + qcom,codec-aux-devs = <&wcd937x_codec>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, + <&bolero>; +}; -- GitLab From 682b0d2d97acb1e94bb4fda94c234524f59b07b9 Mon Sep 17 00:00:00 2001 From: Hardik Arya Date: Fri, 18 Jan 2019 12:21:16 +0530 Subject: [PATCH 1114/1286] diag: Add protection while freeing diag mempool buffer There is possibility of double free because of protection is missing while freeing diag hdlc mempool buffer. The patch adds protection for the same by taking spinlock. Change-Id: I7d2176e05408df80c839e198994807663ce172e8 Signed-off-by: Hardik Arya --- drivers/char/diag/diag_usb.c | 6 +++--- drivers/char/diag/diagchar.h | 1 + drivers/char/diag/diagchar_core.c | 16 ++++++++++++---- drivers/char/diag/diagfwd.c | 4 +++- drivers/char/diag/diagmem.c | 4 ++-- 5 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/char/diag/diag_usb.c b/drivers/char/diag/diag_usb.c index 1e64465af72c..ea34b52ac232 100644 --- a/drivers/char/diag/diag_usb.c +++ b/drivers/char/diag/diag_usb.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -347,8 +347,8 @@ static void diag_usb_write_done(struct diag_usb_info *ch, DIAG_LOG(DIAG_DEBUG_MUX, "partial write_done ref %d\n", atomic_read(&entry->ref_count)); diag_ws_on_copy_complete(DIAG_WS_MUX); - spin_unlock_irqrestore(&ch->write_lock, flags); diagmem_free(driver, req, ch->mempool); + spin_unlock_irqrestore(&ch->write_lock, flags); return; } DIAG_LOG(DIAG_DEBUG_MUX, "full write_done, ctxt: %d\n", @@ -365,8 +365,8 @@ static void diag_usb_write_done(struct diag_usb_info *ch, buf = NULL; len = 0; ctxt = 0; - spin_unlock_irqrestore(&ch->write_lock, flags); diagmem_free(driver, req, ch->mempool); + spin_unlock_irqrestore(&ch->write_lock, flags); } static void diag_usb_notifier(void *priv, unsigned int event, diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h index d48d34632558..42e9aa748142 100644 --- a/drivers/char/diag/diagchar.h +++ b/drivers/char/diag/diagchar.h @@ -612,6 +612,7 @@ struct diagchar_dev { unsigned int poolsize_hdlc; unsigned int poolsize_dci; unsigned int poolsize_user; + spinlock_t diagmem_lock; /* Buffers for masks */ struct mutex diag_cntl_mutex; /* Members for Sending response */ diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c index f69c9f556cda..4e0c8f3fd1a7 100644 --- a/drivers/char/diag/diagchar_core.c +++ b/drivers/char/diag/diagchar_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -214,17 +214,19 @@ static void drain_timer_func(unsigned long data) static void diag_drain_apps_data(struct diag_apps_data_t *data) { int err = 0; + unsigned long flags; if (!data || !data->buf) return; err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, data->ctxt); + spin_lock_irqsave(&driver->diagmem_lock, flags); if (err) diagmem_free(driver, data->buf, POOL_TYPE_HDLC); - data->buf = NULL; data->len = 0; + spin_unlock_irqrestore(&driver->diagmem_lock, flags); } void diag_update_user_client_work_fn(struct work_struct *work) @@ -295,6 +297,8 @@ static void diag_mempool_init(void) diagmem_init(driver, POOL_TYPE_HDLC); diagmem_init(driver, POOL_TYPE_USER); diagmem_init(driver, POOL_TYPE_DCI); + + spin_lock_init(&driver->diagmem_lock); } static void diag_mempool_exit(void) @@ -2891,6 +2895,7 @@ static int diag_process_apps_data_hdlc(unsigned char *buf, int len, struct diag_apps_data_t *data = &hdlc_data; struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 }; struct diag_hdlc_dest_type enc = { NULL, NULL, 0 }; + unsigned long flags; /* * The maximum encoded size of the buffer can be atmost twice the length * of the packet. Add three bytes foe footer - 16 bit CRC (2 bytes) + @@ -2995,10 +3000,11 @@ static int diag_process_apps_data_hdlc(unsigned char *buf, int len, return PKT_ALLOC; fail_free_buf: + spin_lock_irqsave(&driver->diagmem_lock, flags); diagmem_free(driver, data->buf, POOL_TYPE_HDLC); data->buf = NULL; data->len = 0; - + spin_unlock_irqrestore(&driver->diagmem_lock, flags); fail_ret: return ret; } @@ -3010,6 +3016,7 @@ static int diag_process_apps_data_non_hdlc(unsigned char *buf, int len, int ret = PKT_DROP; struct diag_pkt_frame_t header; struct diag_apps_data_t *data = &non_hdlc_data; + unsigned long flags; /* * The maximum packet size, when the data is non hdlc encoded is equal * to the size of the packet frame header and the length. Add 1 for the @@ -3074,10 +3081,11 @@ static int diag_process_apps_data_non_hdlc(unsigned char *buf, int len, return PKT_ALLOC; fail_free_buf: + spin_lock_irqsave(&driver->diagmem_lock, flags); diagmem_free(driver, data->buf, POOL_TYPE_HDLC); data->buf = NULL; data->len = 0; - + spin_unlock_irqrestore(&driver->diagmem_lock, flags); fail_ret: return ret; } diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c index 4286bf833940..c4be1699edc1 100644 --- a/drivers/char/diag/diagfwd.c +++ b/drivers/char/diag/diagfwd.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1783,9 +1783,11 @@ static int diagfwd_mux_write_done(unsigned char *buf, int len, int buf_ctxt, diagfwd_write_done(peripheral, type, num); diag_ws_on_copy(DIAG_WS_MUX); } else if (peripheral == APPS_DATA) { + spin_lock_irqsave(&driver->diagmem_lock, flags); diagmem_free(driver, (unsigned char *)buf, POOL_TYPE_HDLC); buf = NULL; + spin_unlock_irqrestore(&driver->diagmem_lock, flags); } else { pr_err_ratelimited("diag: Invalid peripheral %d in %s, type: %d\n", peripheral, __func__, type); diff --git a/drivers/char/diag/diagmem.c b/drivers/char/diag/diagmem.c index 66d406572b75..f526eddcb6e5 100644 --- a/drivers/char/diag/diagmem.c +++ b/drivers/char/diag/diagmem.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2014, 2016-2017 The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2014, 2016-2017, 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -221,7 +221,7 @@ void diagmem_free(struct diagchar_dev *driver, void *buf, int pool_type) break; } spin_lock_irqsave(&mempool->lock, flags); - if (mempool->count > 0) { + if (mempool->count > 0 && buf) { mempool_free(buf, mempool->pool); atomic_add(-1, (atomic_t *)&mempool->count); } else { -- GitLab From 91d6e9a79fa785e74b4e5c5d32046a45b53efe06 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 24 Jan 2019 22:18:52 +0530 Subject: [PATCH 1115/1286] ARM: dts: msm: Update skin thermal zone mitigation for SDMMAGPIE Update quiet_therm skin thermal zone mitigation for SDMMAGPIE based on latest recommendation. Change-Id: Icd5c7bfa4be451a07c1311d9b12f9c357bbc86fb Signed-off-by: Manaf Meethalavalappu Pallikunhi --- .../boot/dts/qcom/sdmmagpie-thermal.dtsi | 77 +++++++++++++++---- 1 file changed, 63 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi index 6ce5f4cc73e2..bf64f31bc997 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1687,38 +1687,63 @@ thermal-governor = "step_wise"; thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM4_PU2>; trips { - modem_trip0: modem-trip0 { - temperature = <46000>; + batt_trip0: batt-trip0 { + temperature = <43000>; hysteresis = <4000>; type = "passive"; }; - gold_trip: gold-trip { - temperature = <46000>; - hysteresis = <0>; + batt_trip1: batt-trip1 { + temperature = <45000>; + hysteresis = <2000>; type = "passive"; }; - skin_gpu_trip: skin-gpu-trip { + batt_trip2: batt-trip2 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip0: modem-trip0 { temperature = <48000>; hysteresis = <4000>; type = "passive"; }; - modem_trip1: modem-trip1 { - temperature = <48000>; + batt_trip3: batt-trip3 { + temperature = <49000>; hysteresis = <2000>; type = "passive"; }; - modem_trip2: modem-trip2 { + modem_trip1_hvx_trip: modem-trip1-hvx-trip { temperature = <50000>; hysteresis = <2000>; type = "passive"; }; - silver_trip: silver-trip { + gold_trip: gold-trip { temperature = <50000>; hysteresis = <0>; type = "passive"; }; - modem_trip3: modem-trip3 { + batt_trip4: batt-trip4 { + temperature = <51000>; + hysteresis = <2000>; + type = "passive"; + }; + skin_gpu_trip: skin-gpu-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + modem_trip2: modem-trip2 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + silver_trip: silver-trip { temperature = <54000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip3: modem-trip3 { + temperature = <58000>; hysteresis = <4000>; type = "passive"; }; @@ -1772,11 +1797,11 @@ skin_gpu { trip = <&skin_gpu_trip>; /* throttle from fmax to 650000000 Hz */ - cooling-device = <&msm_gpu THERMAL_NO_LIMIT + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; modem_lvl1 { - trip = <&modem_trip1>; + trip = <&modem_trip1_hvx_trip>; cooling-device = <&modem_pa 1 1>; }; modem_lvl2 { @@ -1795,6 +1820,30 @@ trip = <&modem_trip3>; cooling-device = <&modem_proc 3 3>; }; + cdsp_cdev1 { + trip = <&modem_trip1_hvx_trip>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + battery_lvl0 { + trip = <&batt_trip0>; + cooling-device = <&pm6150_charger 1 1>; + }; + battery_lvl1 { + trip = <&batt_trip1>; + cooling-device = <&pm6150_charger 2 2>; + }; + battery_lvl2 { + trip = <&batt_trip2>; + cooling-device = <&pm6150_charger 4 4>; + }; + battery_lvl3 { + trip = <&batt_trip3>; + cooling-device = <&pm6150_charger 5 5>; + }; + battery_lvl4 { + trip = <&batt_trip4>; + cooling-device = <&pm6150_charger 6 6>; + }; }; }; }; -- GitLab From bc026abe794111fd1ba5666ff6b389b925ecb70f Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Wed, 23 Jan 2019 14:30:30 +0530 Subject: [PATCH 1116/1286] ARM: dts: msm: Fix eMMC high voltage corner wake up eMMC is waking up in turbo voltage corner due to high bus voting. Reduced vote to NOM only for 400MBps bus voting. Change-Id: I5972479ed17b0e34da671e6c149d1e644db40426 Signed-off-by: Ram Prakash Gupta --- arch/arm64/boot/dts/qcom/sdmmagpie.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi index 0cf7ec7fc899..f5cb18c3ab2e 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi @@ -2174,8 +2174,8 @@ <150 512 150000 250000>, <1 806 80000 120000>, /* 400 MB/s */ - <150 512 261438 2800000>, - <1 806 1200000 2400000>, + <150 512 261438 2718822>, + <1 806 300000 1359411>, /* Max. bandwidth */ <150 512 1338562 4096000>, <1 806 1338562 4096000>; -- GitLab From 1af1e7fa48b95423a14ad71a0d851801b6c09bc9 Mon Sep 17 00:00:00 2001 From: Amit P Choudhari Date: Fri, 25 Jan 2019 15:22:43 +0530 Subject: [PATCH 1117/1286] ARM: dts: msm: Add secure display memory regions for trinket Add Secure display heap entry for secureUI and other secure usecases. Change-Id: I9edfd0f3d33c3e918d7f75a51ea4756fc30438c7 Signed-off-by: Amit P Choudhari Signed-off-by: Rajesh Yadav --- arch/arm64/boot/dts/qcom/trinket.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index a18805c6f772..74b3e1d95162 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -510,6 +510,14 @@ size = <0 0x1000000>; }; + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; -- GitLab From 9c1ca02a97f48433e367fa525e1d146748599fb5 Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Fri, 25 Jan 2019 19:09:29 +0530 Subject: [PATCH 1118/1286] defconfig: arm64: Enable CDSP request manager for trinket CDSP request manager is required for CDSP FastRPC based applications to improve QoS. The manager also interfaces with thermal driver for CDSP/HVX thermal mitigation. Change-Id: I643e98de892484decad959acd8efc95207630bbf Acked-by: Sreekanth Gande Signed-off-by: Tharun Kumar Merugu --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index a494111ccb6a..d4939585d7c6 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -577,6 +577,7 @@ CONFIG_MEM_SHARE_QMI_SERVICE=y CONFIG_MSM_PERFORMANCE=y CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y +CONFIG_QCOM_CDSP_RM=y CONFIG_DEVFREQ_GOV_PASSIVE=y CONFIG_QCOM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index a6f31e4b4d80..db9550563642 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -605,6 +605,7 @@ CONFIG_MEM_SHARE_QMI_SERVICE=y CONFIG_MSM_PERFORMANCE=y CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_QCOM_SMP2P_SLEEPSTATE=y +CONFIG_QCOM_CDSP_RM=y CONFIG_DEVFREQ_GOV_PASSIVE=y CONFIG_QCOM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y -- GitLab From 54b2e4722042e179db3d90f047f86606c06a001c Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Fri, 25 Jan 2019 19:14:04 +0530 Subject: [PATCH 1119/1286] ARM: dts: msm: Add CDSP rpmsg entry for trinket CDSPRM communicates with CDSP based on the rpmsg driver. The device tree entry configures CDSPRM module of FastRPC based AQoS feature and enables thermal mitigation for CDSP subsystem. Change-Id: I81f7398fa6cf3f554be23f63639443d9b4f60853 Acked-by: Sreekanth Gande Signed-off-by: Tharun Kumar Merugu --- arch/arm64/boot/dts/qcom/trinket.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index a18805c6f772..1a5cdf04e58f 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1635,6 +1635,24 @@ qcom,intents = <0x64 64>; }; + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + qcom,cdsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, -- GitLab From 98171c3b9b50f0a68f154029cee3673fe1ecf221 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Sun, 20 Jan 2019 11:50:15 +0530 Subject: [PATCH 1120/1286] ARM: dts: msm: Update the min/max voltages for trinket Update the min/max voltages of the LDOs/SMPS to meet the regulator spec. Also correct the LDO8 labels. Change-Id: I10ea429c0317feaadee0cd784e3dbd4c06744670 Signed-off-by: Kiran Gunda --- .../boot/dts/qcom/trinket-regulator.dtsi | 102 +++++++++--------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi index c4562ae48bab..396751468f9a 100644 --- a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi @@ -120,9 +120,9 @@ rpm-regulator-smpa6 { status = "okay"; S6A: pm6125_s6: regulator-s6 { - regulator-min-microvolt = <1064000>; - regulator-max-microvolt = <1424000>; - qcom,init-voltage = <1064000>; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + qcom,init-voltage = <936000>; status = "okay"; }; }; @@ -130,9 +130,9 @@ rpm-regulator-ldoa1 { status = "okay"; L1A: pm6125_l1: regulator-l1 { - regulator-min-microvolt = <1178000>; - regulator-max-microvolt = <1252000>; - qcom,init-voltage = <1178000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1200000>; status = "okay"; }; }; @@ -140,9 +140,9 @@ rpm-regulator-ldoa2 { status = "okay"; L2A: pm6125_l2: regulator-l2 { - regulator-min-microvolt = <944000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1056000>; - qcom,init-voltage = <944000>; + qcom,init-voltage = <1000000>; status = "okay"; }; }; @@ -150,9 +150,9 @@ rpm-regulator-ldoa3 { status = "okay"; L3A: pm6125_l3: regulator-l3 { - regulator-min-microvolt = <968000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1064000>; - qcom,init-voltage = <968000>; + qcom,init-voltage = <1000000>; status = "okay"; }; }; @@ -161,7 +161,7 @@ status = "okay"; L4A: pm6125_l4: regulator-l4 { regulator-min-microvolt = <872000>; - regulator-max-microvolt = <1000000>; + regulator-max-microvolt = <976000>; qcom,init-voltage = <872000>; status = "okay"; }; @@ -180,9 +180,9 @@ rpm-regulator-ldoa6 { status = "okay"; L6A: pm6125_l6: regulator-l6 { - regulator-min-microvolt = <568000>; + regulator-min-microvolt = <576000>; regulator-max-microvolt = <656000>; - qcom,init-voltage = <568000>; + qcom,init-voltage = <576000>; status = "okay"; }; }; @@ -190,9 +190,9 @@ rpm-regulator-ldoa7 { status = "okay"; L7A: pm6125_l7: regulator-l7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1000000>; + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + qcom,init-voltage = <872000>; status = "okay"; }; }; @@ -200,7 +200,7 @@ /* WCSS_CX */ rpm-regulator-ldoa8 { status = "okay"; - L8A: pm6125_l8_level: regulator-l8-level { + L8A: pm6125_l8: regulator-l8 { regulator-min-microvolt = <400000>; regulator-max-microvolt = <728000>; qcom,init-voltage = <400000>; @@ -211,9 +211,9 @@ rpm-regulator-ldoa9 { status = "okay"; L9A: pm6125_l9: regulator-l9 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2000000>; - qcom,init-voltage = <1200000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -221,9 +221,9 @@ rpm-regulator-ldoa10 { status = "okay"; L10A: pm6125_l10: regulator-l10 { - regulator-min-microvolt = <1624000>; - regulator-max-microvolt = <1984000>; - qcom,init-voltage = <1624000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -231,9 +231,9 @@ rpm-regulator-ldoa11 { status = "okay"; L11A: pm6125_l11: regulator-l11 { - regulator-min-microvolt = <1624000>; - regulator-max-microvolt = <1984000>; - qcom,init-voltage = <1624000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -241,9 +241,9 @@ rpm-regulator-ldoa12 { status = "okay"; L12A: pm6125_l12: regulator-l12 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <1904000>; - qcom,init-voltage = <1648000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -251,9 +251,9 @@ rpm-regulator-ldoa13 { status = "okay"; L13A: pm6125_l13: regulator-l13 { - regulator-min-microvolt = <1720000>; - regulator-max-microvolt = <1824000>; - qcom,init-voltage = <1720000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -261,9 +261,9 @@ rpm-regulator-ldoa14 { status = "okay"; L14A: pm6125_l14: regulator-l14 { - regulator-min-microvolt = <1696000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1904000>; - qcom,init-voltage = <1696000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -272,9 +272,9 @@ status = "okay"; pm6125_l15-parent-supply = <&pm6125_l10>; L15A: pm6125_l15: regulator-l15 { - regulator-min-microvolt = <2928000>; + regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3232000>; - qcom,init-voltage = <2928000>; + qcom,init-voltage = <3104000>; status = "okay"; }; }; @@ -282,9 +282,9 @@ rpm-regulator-ldoa16 { status = "okay"; L16A: pm6125_l16: regulator-l16 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <1952000>; - qcom,init-voltage = <1648000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; status = "okay"; }; }; @@ -292,9 +292,9 @@ rpm-regulator-ldoa17 { status = "okay"; L17A: pm6125_l17: regulator-l17 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1352000>; - qcom,init-voltage = <1144000>; + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1248000>; status = "okay"; }; }; @@ -302,9 +302,9 @@ rpm-regulator-ldoa18 { status = "okay"; L18A: pm6125_l18: regulator-l18 { - regulator-min-microvolt = <1136000>; - regulator-max-microvolt = <1312000>; - qcom,init-voltage = <1136000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + qcom,init-voltage = <1200000>; status = "okay"; }; }; @@ -312,9 +312,9 @@ rpm-regulator-ldoa19 { status = "okay"; L19A: pm6125_l19: regulator-l19 { - regulator-min-microvolt = <1616000>; + regulator-min-microvolt = <1648000>; regulator-max-microvolt = <2952000>; - qcom,init-voltage = <1616000>; + qcom,init-voltage = <1648000>; status = "okay"; }; }; @@ -322,9 +322,9 @@ rpm-regulator-ldoa20 { status = "okay"; L20A: pm6125_l20: regulator-l20 { - regulator-min-microvolt = <1616000>; + regulator-min-microvolt = <1648000>; regulator-max-microvolt = <2952000>; - qcom,init-voltage = <1616000>; + qcom,init-voltage = <1648000>; status = "okay"; }; }; @@ -362,9 +362,9 @@ rpm-regulator-ldoa24 { status = "okay"; L24A: pm6125_l24: regulator-l24 { - regulator-min-microvolt = <1696000>; + regulator-min-microvolt = <2944000>; regulator-max-microvolt = <3304000>; - qcom,init-voltage = <1696000>; + qcom,init-voltage = <2944000>; status = "okay"; }; }; -- GitLab From 6fa83c1410c051580bb37e4a603d9f91570ba72a Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 25 Jan 2019 21:28:47 +0530 Subject: [PATCH 1121/1286] ARM: dts: msm: Enable CDSP thermal zone mitigation for TRINKET Enable CDSP thermal mitigation for CDSP TSENS for TRINKET. It throttles CDSP DCVS frequencies whenever preset trips are violated. Change-Id: If622105c02d1b393b317e88d03047f3b18840ce4 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 71e9099dd0fc..53b5511709f4 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -1536,22 +1536,41 @@ }; cdsp-step { - polling-delay-passive = <0>; + polling-delay-passive = <10>; polling-delay = <0>; thermal-sensors = <&tsens0 1>; thermal-governor = "step_wise"; trips { - cdsp_config: cdsp-config { + cdsp_trip0: cdsp-trip0 { temperature = <95000>; hysteresis = <20000>; type = "passive"; }; + cdsp_trip1: cdsp-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + cdsp_trip2: cdsp-trip2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { cxip-cdev { - trip = <&cdsp_config>; + trip = <&cdsp_trip0>; cooling-device = <&cxip_cdev 1 1>; }; + cdsp-cdev0 { + trip = <&cdsp_trip1>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 4>; + }; + cdsp-cdev1 { + trip = <&cdsp_trip2>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; }; }; }; -- GitLab From ec0348d95aa9cffb961bd5e7fad1eb51788e7af4 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Thu, 24 Jan 2019 16:18:01 +0530 Subject: [PATCH 1122/1286] ARM: dts: msm: add support to vote for MX to power phy for TRINKET Add changes to support voting MX to power phy for TRINKET target. Change-Id: I7c726b9eb16ec53c43b3c47bd84b3fc98439e34f Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi index f7eb8c89e73c..f5b526bb27d5 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -366,7 +366,7 @@ reg = <0x5e94400 0x588>, <0x5e01400 0x100>; reg-names = "dsi_phy", "phy_clamp_base"; - vdda-0p9-supply = <&L4A>; + vdda-0p9-supply = <&VDD_MX_LEVEL>; qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 @@ -378,15 +378,18 @@ 00 00 10 0f 00 00 10 8f]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <975000>; - qcom,supply-enable-load = <36000>; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; -- GitLab From ded6f525cba5dedc80857e34e7f7051f05edabde Mon Sep 17 00:00:00 2001 From: Steve Muckle Date: Thu, 17 Nov 2016 10:48:45 +0530 Subject: [PATCH 1123/1286] ANDROID: cpufreq/schedutil: add up/down frequency transition rate limits The rate-limit tunable in the schedutil governor applies to transitions to both lower and higher frequencies. On several platforms it is not the ideal tunable though, as it is difficult to get best power/performance figures using the same limit in both directions. It is common on mobile platforms with demanding user interfaces to want to increase frequency rapidly for example but decrease slowly. One of the example can be a case where we have short busy periods followed by similar or longer idle periods. If we keep the rate-limit high enough, we will not go to higher frequencies soon enough. On the other hand, if we keep it too low, we will have too many frequency transitions, as we will always reduce the frequency after the busy period. It would be very useful if we can set low rate-limit while increasing the frequency (so that we can respond to the short busy periods quickly) and high rate-limit while decreasing frequency (so that we don't reduce the frequency immediately after the short busy period and that may avoid frequency transitions before the next busy period). Implement separate up/down transition rate limits. Note that the governor avoids frequency recalculations for a period equal to minimum of up and down rate-limit. A global mutex is also defined to protect updates to min_rate_limit_us via two separate sysfs files. Note that this wouldn't change behavior of the schedutil governor for the platforms which wish to keep same values for both up and down rate limits. This is tested with the rt-app [1] on ARM Exynos, dual A15 processor platform. Testcase: Run a SCHED_OTHER thread on CPU0 which will emulate work-load for X ms of busy period out of the total period of Y ms, i.e. Y - X ms of idle period. The values of X/Y taken were: 20/40, 20/50, 20/70, i.e idle periods of 20, 30 and 50 ms respectively. These were tested against values of up/down rate limits as: 10/10 ms and 10/40 ms. For every test we noticed a performance increase of 5-10% with the schedutil governor, which was very much expected. [Viresh]: Simplified user interface and introduced min_rate_limit_us + mutex, rewrote commit log and included test results. [1] https://github.com/scheduler-tools/rt-app/ Change-Id: I44fc7adc155a126ea61f6956a15ca1a02fdc4692 Signed-off-by: Steve Muckle Signed-off-by: Viresh Kumar (applied from https://marc.info/?l=linux-kernel&m=147936011103832&w=2) [trivial adaptations] Signed-off-by: Juri Lelli [updated rate limiting & fixed conflicts] Signed-off-by: Chris Redpath (cherry picked from commit 50c26fdb74563ec0cb4a83373d42667f4e83a23e) [Trivial cherry-pick conflicts] Signed-off-by: Quentin Perret Git-commit: 50c26fdb74563ec0cb4a83373d42667f4e83a23e Git-repo: https://android.googlesource.com/kernel/common/ [gsantosh@codeaurora.org: refactored variable to fix compilation errors also fixed checkpatch errors] Signed-off-by: Santosh Mardi --- kernel/sched/cpufreq_schedutil.c | 112 ++++++++++++++++++++++++++----- 1 file changed, 95 insertions(+), 17 deletions(-) diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c index 1e23ffb7a099..69b1321deb63 100644 --- a/kernel/sched/cpufreq_schedutil.c +++ b/kernel/sched/cpufreq_schedutil.c @@ -23,7 +23,8 @@ struct sugov_tunables { struct gov_attr_set attr_set; - unsigned int rate_limit_us; + unsigned int up_rate_limit_us; + unsigned int down_rate_limit_us; unsigned int hispeed_load; unsigned int hispeed_freq; bool pl; @@ -37,6 +38,9 @@ struct sugov_policy { raw_spinlock_t update_lock; /* For shared policies */ u64 last_freq_update_time; + s64 min_rate_limit_ns; + s64 up_rate_delay_ns; + s64 down_rate_delay_ns; s64 freq_update_delay_ns; u64 last_ws; u64 curr_cycles; @@ -120,9 +124,32 @@ static bool sugov_should_update_freq(struct sugov_policy *sg_policy, u64 time) sg_policy->next_freq = UINT_MAX; return true; } + /* No need to recalculate next freq for min_rate_limit_us + * at least. However we might still decide to further rate + * limit once frequency change direction is decided, according + * to the separate rate limits. + */ delta_ns = time - sg_policy->last_freq_update_time; - return delta_ns >= sg_policy->freq_update_delay_ns; + return delta_ns >= sg_policy->min_rate_limit_ns; +} + +static bool sugov_up_down_rate_limit(struct sugov_policy *sg_policy, u64 time, + unsigned int next_freq) +{ + s64 delta_ns; + + delta_ns = time - sg_policy->last_freq_update_time; + + if (next_freq > sg_policy->next_freq && + delta_ns < sg_policy->up_rate_delay_ns) + return true; + + if (next_freq < sg_policy->next_freq && + delta_ns < sg_policy->down_rate_delay_ns) + return true; + + return false; } static inline bool use_pelt(void) @@ -197,6 +224,9 @@ static void sugov_update_commit(struct sugov_policy *sg_policy, u64 time, if (sg_policy->next_freq == next_freq) return; + if (sugov_up_down_rate_limit(sg_policy, time, next_freq)) + return; + sg_policy->next_freq = next_freq; sg_policy->last_freq_update_time = time; @@ -582,15 +612,32 @@ static inline struct sugov_tunables *to_sugov_tunables(struct gov_attr_set *attr return container_of(attr_set, struct sugov_tunables, attr_set); } -static ssize_t rate_limit_us_show(struct gov_attr_set *attr_set, char *buf) +static DEFINE_MUTEX(min_rate_lock); + +static void update_min_rate_limit_ns(struct sugov_policy *sg_policy) +{ + mutex_lock(&min_rate_lock); + sg_policy->min_rate_limit_ns = min(sg_policy->up_rate_delay_ns, + sg_policy->down_rate_delay_ns); + mutex_unlock(&min_rate_lock); +} + +static ssize_t up_rate_limit_us_show(struct gov_attr_set *attr_set, char *buf) { struct sugov_tunables *tunables = to_sugov_tunables(attr_set); - return sprintf(buf, "%u\n", tunables->rate_limit_us); + return sprintf(buf, "%u\n", tunables->up_rate_limit_us); } -static ssize_t rate_limit_us_store(struct gov_attr_set *attr_set, const char *buf, - size_t count) +static ssize_t down_rate_limit_us_show(struct gov_attr_set *attr_set, char *buf) +{ + struct sugov_tunables *tunables = to_sugov_tunables(attr_set); + + return sprintf(buf, "%u\n", tunables->down_rate_limit_us); +} + +static ssize_t up_rate_limit_us_store(struct gov_attr_set *attr_set, + const char *buf, size_t count) { struct sugov_tunables *tunables = to_sugov_tunables(attr_set); struct sugov_policy *sg_policy; @@ -599,10 +646,32 @@ static ssize_t rate_limit_us_store(struct gov_attr_set *attr_set, const char *bu if (kstrtouint(buf, 10, &rate_limit_us)) return -EINVAL; - tunables->rate_limit_us = rate_limit_us; + tunables->up_rate_limit_us = rate_limit_us; + + list_for_each_entry(sg_policy, &attr_set->policy_list, tunables_hook) { + sg_policy->up_rate_delay_ns = rate_limit_us * NSEC_PER_USEC; + update_min_rate_limit_ns(sg_policy); + } - list_for_each_entry(sg_policy, &attr_set->policy_list, tunables_hook) - sg_policy->freq_update_delay_ns = rate_limit_us * NSEC_PER_USEC; + return count; +} + +static ssize_t down_rate_limit_us_store(struct gov_attr_set *attr_set, + const char *buf, size_t count) +{ + struct sugov_tunables *tunables = to_sugov_tunables(attr_set); + struct sugov_policy *sg_policy; + unsigned int rate_limit_us; + + if (kstrtouint(buf, 10, &rate_limit_us)) + return -EINVAL; + + tunables->down_rate_limit_us = rate_limit_us; + + list_for_each_entry(sg_policy, &attr_set->policy_list, tunables_hook) { + sg_policy->down_rate_delay_ns = rate_limit_us * NSEC_PER_USEC; + update_min_rate_limit_ns(sg_policy); + } return count; } @@ -677,13 +746,15 @@ static ssize_t pl_store(struct gov_attr_set *attr_set, const char *buf, return count; } -static struct governor_attr rate_limit_us = __ATTR_RW(rate_limit_us); +static struct governor_attr up_rate_limit_us = __ATTR_RW(up_rate_limit_us); +static struct governor_attr down_rate_limit_us = __ATTR_RW(down_rate_limit_us); static struct governor_attr hispeed_load = __ATTR_RW(hispeed_load); static struct governor_attr hispeed_freq = __ATTR_RW(hispeed_freq); static struct governor_attr pl = __ATTR_RW(pl); static struct attribute *sugov_attributes[] = { - &rate_limit_us.attr, + &up_rate_limit_us.attr, + &down_rate_limit_us.attr, &hispeed_load.attr, &hispeed_freq.attr, &pl.attr, @@ -804,7 +875,8 @@ static void sugov_tunables_save(struct cpufreq_policy *policy, cached->pl = tunables->pl; cached->hispeed_load = tunables->hispeed_load; cached->hispeed_freq = tunables->hispeed_freq; - cached->rate_limit_us = tunables->rate_limit_us; + cached->up_rate_limit_us = tunables->up_rate_limit_us; + cached->down_rate_limit_us = tunables->down_rate_limit_us; } static void sugov_tunables_free(struct sugov_tunables *tunables) @@ -827,9 +899,9 @@ static void sugov_tunables_restore(struct cpufreq_policy *policy) tunables->pl = cached->pl; tunables->hispeed_load = cached->hispeed_load; tunables->hispeed_freq = cached->hispeed_freq; - tunables->rate_limit_us = cached->rate_limit_us; - sg_policy->freq_update_delay_ns = - tunables->rate_limit_us * NSEC_PER_USEC; + tunables->up_rate_limit_us = cached->up_rate_limit_us; + tunables->down_rate_limit_us = cached->down_rate_limit_us; + update_min_rate_limit_ns(sg_policy); } static int sugov_init(struct cpufreq_policy *policy) @@ -874,7 +946,10 @@ static int sugov_init(struct cpufreq_policy *policy) goto stop_kthread; } - tunables->rate_limit_us = cpufreq_policy_transition_delay_us(policy); + tunables->up_rate_limit_us = + cpufreq_policy_transition_delay_us(policy); + tunables->down_rate_limit_us = + cpufreq_policy_transition_delay_us(policy); tunables->hispeed_load = DEFAULT_HISPEED_LOAD; tunables->hispeed_freq = 0; @@ -940,7 +1015,10 @@ static int sugov_start(struct cpufreq_policy *policy) struct sugov_policy *sg_policy = policy->governor_data; unsigned int cpu; - sg_policy->freq_update_delay_ns = sg_policy->tunables->rate_limit_us * NSEC_PER_USEC; + sg_policy->up_rate_delay_ns = + sg_policy->tunables->up_rate_limit_us * NSEC_PER_USEC; + sg_policy->down_rate_delay_ns = + sg_policy->tunables->down_rate_limit_us * NSEC_PER_USEC; sg_policy->last_freq_update_time = 0; sg_policy->next_freq = UINT_MAX; sg_policy->work_in_progress = false; -- GitLab From b3431e57dcc76b7060946417ca4fa1760e8a852b Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Fri, 25 Jan 2019 16:24:53 +0530 Subject: [PATCH 1124/1286] clk: qcom: gcc: Add PLL type flag for gpll_out_even clk Add PLL type flag for gpll1_out_even and gpll4_out_even clk to correctly read the user ctl register offset in recalc rate ops. Change-Id: I177a31d1ffa88b6ec345c9b604410ba18452a625 Signed-off-by: Naveen Yadav --- drivers/clk/qcom/gcc-sdxprairie.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-sdxprairie.c b/drivers/clk/qcom/gcc-sdxprairie.c index 1915206ee285..a3069bd52982 100644 --- a/drivers/clk/qcom/gcc-sdxprairie.c +++ b/drivers/clk/qcom/gcc-sdxprairie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -179,6 +179,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .post_div_table = post_div_table_lucid_even, .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), .width = 4, + .type = LUCID_PLL, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", .parent_names = (const char *[]){ "gpll0" }, @@ -217,6 +218,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_even = { .post_div_table = post_div_table_lucid_even, .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), .width = 4, + .type = LUCID_PLL, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_even", .parent_names = (const char *[]){ "gpll4" }, -- GitLab From 15d3ac3d1f73f92d5b95db5576a3ce0526d346b4 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Sat, 26 Jan 2019 08:34:52 +0530 Subject: [PATCH 1125/1286] ARM: dts: msm: update cpubw with bwmon4 version on trikent target Update cpubw node on trinket target to work with bwmon4 version populate base, global base address along with mport value. Change-Id: If4b8da981fac4b4426cd1374034c42f393b79623 Signed-off-by: Santosh Mardi --- arch/arm64/boot/dts/qcom/trinket.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index a18805c6f772..0ff1eea3fc79 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2271,11 +2271,12 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; - cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@90cd000 { - compatible = "qcom,bimc-bwmon5"; - reg = <0x90cd000 0x1000>; - reg-names = "base"; + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x01b8e200 0x100>, <0x01b8e100 0x100>; + reg-names = "base", "global_base"; interrupts = ; + qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_cpu_ddr_bw>; qcom,count-unit = <0x10000>; -- GitLab From 04717e47d06af575ce0d13d7cf27023ef134d1cd Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Fri, 25 Jan 2019 10:26:06 +0530 Subject: [PATCH 1126/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: I2d3c30440ff69f87dc975b33df9d0531115375ae Signed-off-by: Pavankumar Kondeti --- kernel/sched/boost.c | 20 +++++++------------- kernel/sched/fair.c | 2 +- kernel/sched/sched.h | 20 +++++++++++++------- kernel/sched/walt.c | 2 +- 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index ae8f5f5785e2..84f7e232d665 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -23,8 +23,10 @@ * boost is responsible for disabling it as well. */ -unsigned int sysctl_sched_boost; -static enum sched_boost_policy boost_policy; +unsigned int sysctl_sched_boost; /* To/from userspace */ +unsigned int sched_boost_type; /* currently activated sched boost */ +enum sched_boost_policy boost_policy; + static enum sched_boost_policy boost_policy_dt = SCHED_BOOST_NONE; static DEFINE_MUTEX(boost_mutex); static int boost_refcount[MAX_NUM_BOOST_TYPE]; @@ -60,11 +62,6 @@ static void set_boost_policy(int type) boost_policy = SCHED_BOOST_ON_ALL; } -enum sched_boost_policy sched_boost_policy(void) -{ - return boost_policy; -} - static bool verify_boost_params(int type) { return type >= RESTRAINED_BOOST_DISABLE && type <= RESTRAINED_BOOST; @@ -159,8 +156,10 @@ static void _sched_set_boost(int type) else type = NO_BOOST; - set_boost_policy(type); + sched_boost_type = type; sysctl_sched_boost = type; + + set_boost_policy(type); trace_sched_set_boost(type); } @@ -217,8 +216,3 @@ int sched_boost_handler(struct ctl_table *table, int write, mutex_unlock(&boost_mutex); return ret; } - -int sched_boost(void) -{ - return sysctl_sched_boost; -} diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 3cc4dde46fbf..e728e591f70c 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7981,7 +7981,7 @@ static inline int wake_to_idle(struct task_struct *p) #ifdef CONFIG_SCHED_WALT static inline bool is_task_util_above_min_thresh(struct task_struct *p) { - unsigned int threshold = (sysctl_sched_boost == CONSERVATIVE_BOOST) ? + unsigned int threshold = (sched_boost() == CONSERVATIVE_BOOST) ? sysctl_sched_min_task_util_for_boost : sysctl_sched_min_task_util_for_colocation; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 9a0dc1642f2f..21282b846944 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2524,11 +2524,6 @@ enum sched_boost_policy { SCHED_BOOST_ON_ALL, }; -#define NO_BOOST 0 -#define FULL_THROTTLE_BOOST 1 -#define CONSERVATIVE_BOOST 2 -#define RESTRAINED_BOOST 3 - /* * Returns the rq capacity of any rq in a group. This does not play * well with groups where rq capacity can change independently. @@ -2831,7 +2826,18 @@ static inline int same_freq_domain(int src_cpu, int dst_cpu) #define CPU_RESERVED 1 -extern int sched_boost(void); +extern enum sched_boost_policy boost_policy; +static inline enum sched_boost_policy sched_boost_policy(void) +{ + return boost_policy; +} + +extern unsigned int sched_boost_type; +static inline int sched_boost(void) +{ + return sched_boost_type; +} + extern int preferred_cluster(struct sched_cluster *cluster, struct task_struct *p); extern struct sched_cluster *rq_cluster(struct rq *rq); @@ -2939,7 +2945,7 @@ static inline enum sched_boost_policy task_boost_policy(struct task_struct *p) * Filter out tasks less than min task util threshold * under conservative boost. */ - if (sysctl_sched_boost == CONSERVATIVE_BOOST && + if (sched_boost() == CONSERVATIVE_BOOST && task_util(p) <= sysctl_sched_min_task_util_for_boost) policy = SCHED_BOOST_NONE; diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c index 0719cf32d3ff..0bda756f5e62 100644 --- a/kernel/sched/walt.c +++ b/kernel/sched/walt.c @@ -3129,7 +3129,7 @@ static void walt_update_coloc_boost_load(void) struct sched_cluster *cluster; if (!sysctl_sched_little_cluster_coloc_fmin_khz || - sysctl_sched_boost == CONSERVATIVE_BOOST) + sched_boost() == CONSERVATIVE_BOOST) return; grp = lookup_related_thread_group(DEFAULT_CGROUP_COLOC_ID); -- GitLab From 980436fe4228a6d2d3f6efd24f8a1fff0501b8be Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Thu, 24 Jan 2019 15:22:31 +0530 Subject: [PATCH 1127/1286] sched: Improve the scheduler This change is for general scheduler improvement. Change-Id: Ifebdb171fec030347e0582e5a91d3deac8812763 Signed-off-by: Pavankumar Kondeti Signed-off-by: Abhijeet Dharmapurikar --- kernel/sched/boost.c | 243 ++++++++++++++++++++++++++++--------------- 1 file changed, 157 insertions(+), 86 deletions(-) diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c index 84f7e232d665..c3c29e1796b8 100644 --- a/kernel/sched/boost.c +++ b/kernel/sched/boost.c @@ -29,7 +29,6 @@ enum sched_boost_policy boost_policy; static enum sched_boost_policy boost_policy_dt = SCHED_BOOST_NONE; static DEFINE_MUTEX(boost_mutex); -static int boost_refcount[MAX_NUM_BOOST_TYPE]; /* * Scheduler boost type and boost policy might at first seem unrelated, @@ -67,100 +66,172 @@ static bool verify_boost_params(int type) return type >= RESTRAINED_BOOST_DISABLE && type <= RESTRAINED_BOOST; } -static void _sched_set_boost(int type) +static void sched_no_boost_nop(void) { - switch (type) { - case NO_BOOST: /* All boost clear */ - if (boost_refcount[FULL_THROTTLE_BOOST] > 0) { - core_ctl_set_boost(false); - walt_enable_frequency_aggregation(false); - boost_refcount[FULL_THROTTLE_BOOST] = 0; - } - if (boost_refcount[CONSERVATIVE_BOOST] > 0) { - restore_cgroup_boost_settings(); - boost_refcount[CONSERVATIVE_BOOST] = 0; - } - if (boost_refcount[RESTRAINED_BOOST] > 0) { - walt_enable_frequency_aggregation(false); - boost_refcount[RESTRAINED_BOOST] = 0; - } - break; - - case FULL_THROTTLE_BOOST: - boost_refcount[FULL_THROTTLE_BOOST]++; - if (boost_refcount[FULL_THROTTLE_BOOST] == 1) { - core_ctl_set_boost(true); - restore_cgroup_boost_settings(); - if (!boost_refcount[RESTRAINED_BOOST]) - walt_enable_frequency_aggregation(true); - } - break; - - case CONSERVATIVE_BOOST: - boost_refcount[CONSERVATIVE_BOOST]++; - if ((boost_refcount[CONSERVATIVE_BOOST] == 1) && - !boost_refcount[FULL_THROTTLE_BOOST]) - update_cgroup_boost_settings(); - break; - - case RESTRAINED_BOOST: - boost_refcount[RESTRAINED_BOOST]++; - if (boost_refcount[RESTRAINED_BOOST] == 1 && - !boost_refcount[FULL_THROTTLE_BOOST]) - walt_enable_frequency_aggregation(true); - break; - - case FULL_THROTTLE_BOOST_DISABLE: - if (boost_refcount[FULL_THROTTLE_BOOST] >= 1) { - boost_refcount[FULL_THROTTLE_BOOST]--; - if (!boost_refcount[FULL_THROTTLE_BOOST]) { - core_ctl_set_boost(false); - if (boost_refcount[CONSERVATIVE_BOOST] >= 1) - update_cgroup_boost_settings(); - if (!boost_refcount[RESTRAINED_BOOST]) - walt_enable_frequency_aggregation( - false); - } - } - break; +} - case CONSERVATIVE_BOOST_DISABLE: - if (boost_refcount[CONSERVATIVE_BOOST] >= 1) { - boost_refcount[CONSERVATIVE_BOOST]--; - if (!boost_refcount[CONSERVATIVE_BOOST]) - restore_cgroup_boost_settings(); - } - break; - - case RESTRAINED_BOOST_DISABLE: - if (boost_refcount[RESTRAINED_BOOST] >= 1) { - boost_refcount[RESTRAINED_BOOST]--; - if (!boost_refcount[RESTRAINED_BOOST] && - !boost_refcount[FULL_THROTTLE_BOOST]) - walt_enable_frequency_aggregation(false); - } - break; +static void sched_full_throttle_boost_enter(void) +{ + core_ctl_set_boost(true); + walt_enable_frequency_aggregation(true); +} + +static void sched_full_throttle_boost_exit(void) +{ + core_ctl_set_boost(false); + walt_enable_frequency_aggregation(false); +} + +static void sched_conservative_boost_enter(void) +{ + update_cgroup_boost_settings(); +} + +static void sched_conservative_boost_exit(void) +{ + restore_cgroup_boost_settings(); +} + +static void sched_restrained_boost_enter(void) +{ + walt_enable_frequency_aggregation(true); +} + +static void sched_restrained_boost_exit(void) +{ + walt_enable_frequency_aggregation(false); +} + +struct sched_boost_data { + int refcount; + void (*enter)(void); + void (*exit)(void); +}; + +static struct sched_boost_data sched_boosts[] = { + [NO_BOOST] = { + .refcount = 0, + .enter = sched_no_boost_nop, + .exit = sched_no_boost_nop, + }, + [FULL_THROTTLE_BOOST] = { + .refcount = 0, + .enter = sched_full_throttle_boost_enter, + .exit = sched_full_throttle_boost_exit, + }, + [CONSERVATIVE_BOOST] = { + .refcount = 0, + .enter = sched_conservative_boost_enter, + .exit = sched_conservative_boost_exit, + }, + [RESTRAINED_BOOST] = { + .refcount = 0, + .enter = sched_restrained_boost_enter, + .exit = sched_restrained_boost_exit, + }, +}; + +#define SCHED_BOOST_START FULL_THROTTLE_BOOST +#define SCHED_BOOST_END (RESTRAINED_BOOST + 1) + +static int sched_effective_boost(void) +{ + int i; + + /* + * The boosts are sorted in descending order by + * priority. + */ + for (i = SCHED_BOOST_START; i < SCHED_BOOST_END; i++) { + if (sched_boosts[i].refcount >= 1) + return i; + } + + return NO_BOOST; +} + +static void sched_boost_disable(int type) +{ + struct sched_boost_data *sb = &sched_boosts[type]; + int next_boost; + + if (sb->refcount <= 0) + return; + + sb->refcount--; + + if (sb->refcount) + return; + + /* + * This boost's refcount becomes zero, so it must + * be disabled. Disable it first and then apply + * the next boost. + */ + sb->exit(); + + next_boost = sched_effective_boost(); + sched_boosts[next_boost].enter(); +} - default: - WARN_ON(1); +static void sched_boost_enable(int type) +{ + struct sched_boost_data *sb = &sched_boosts[type]; + int next_boost, prev_boost = sched_boost_type; + + sb->refcount++; + + if (sb->refcount != 1) + return; + + /* + * This boost enable request did not come before. + * Take this new request and find the next boost + * by aggregating all the enabled boosts. If there + * is a change, disable the previous boost and enable + * the next boost. + */ + + next_boost = sched_effective_boost(); + if (next_boost == prev_boost) return; + + sched_boosts[prev_boost].exit(); + sched_boosts[next_boost].enter(); +} + +static void sched_boost_disable_all(void) +{ + int i; + + for (i = SCHED_BOOST_START; i < SCHED_BOOST_END; i++) { + if (sched_boosts[i].refcount > 0) { + sched_boosts[i].exit(); + sched_boosts[i].refcount = 0; + } } +} - /* Aggregate final boost type */ - if (boost_refcount[FULL_THROTTLE_BOOST] >= 1) - type = FULL_THROTTLE_BOOST; - else if (boost_refcount[CONSERVATIVE_BOOST] >= 1) - type = CONSERVATIVE_BOOST; - else if (boost_refcount[RESTRAINED_BOOST] >= 1) - type = RESTRAINED_BOOST; +static void _sched_set_boost(int type) +{ + if (type == 0) + sched_boost_disable_all(); + else if (type > 0) + sched_boost_enable(type); else - type = NO_BOOST; + sched_boost_disable(-type); - sched_boost_type = type; - sysctl_sched_boost = type; + /* + * sysctl_sched_boost holds the boost request from + * user space which could be different from the + * effectively enabled boost. Update the effective + * boost here. + */ - set_boost_policy(type); - trace_sched_set_boost(type); + sched_boost_type = sched_effective_boost(); + sysctl_sched_boost = sched_boost_type; + set_boost_policy(sysctl_sched_boost); + trace_sched_set_boost(sysctl_sched_boost); } void sched_boost_parse_dt(void) -- GitLab From cff38c326b9855535d56ad260dadcb1db15a7691 Mon Sep 17 00:00:00 2001 From: Konstantin Dorfman Date: Thu, 20 Dec 2018 17:55:50 +0200 Subject: [PATCH 1128/1286] soc:qcom:spcom: free not consumed packet on rx timeout Every SPU to hlos spcom data packet should be consumed by userspace read() context. When spcomlib read() system call exits on timeout, a packet arrived later will be stuck till next read() context arrives. This change fixes this by removing not used packet from channel table in following cases: - user character device is closed (no packet expected) - packet receive from SPU, by assumption, that the next read() belongs to different session There is sequence number maintained for each spcom session per channel. It is stored in a channel context and changed as follows: - initialized on channel creation and channel destroy - incremented by client side, before send new request to spcom server - no changes on spcom_device_open/spcom_device_release - incremented when timeout on spcom_rx() in order to drop later txn_id of incoming server response is used to validate that incoming packet has same sequence number as expected by client channel context. Also added logic to support detection of communication role (client/server): - for server: first packet is incoming from SPU - for client: first packet is send to SPU Change-Id: Ied52fd6fa41255db817f1aabc2f4acf2616ee75c Signed-off-by: Konstantin Dorfman --- drivers/soc/qcom/spcom.c | 61 ++++++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/spcom.c b/drivers/soc/qcom/spcom.c index 31608b66411e..0904be5c3dbc 100644 --- a/drivers/soc/qcom/spcom.c +++ b/drivers/soc/qcom/spcom.c @@ -151,6 +151,8 @@ struct spcom_channel { struct mutex lock; uint32_t txn_id; /* incrementing nonce per client request */ bool is_server; /* for txn_id and response_timeout_msec */ + bool comm_role_undefined; /* is true on channel creation, before */ + /* first tx/rx on channel */ uint32_t response_timeout_msec; /* for client only */ /* char dev */ @@ -320,6 +322,7 @@ static int spcom_init_channel(struct spcom_channel *ch, const char *name) ch->pid = 0; ch->rpmsg_abort = false; ch->rpmsg_rx_buf = NULL; + ch->comm_role_undefined = true; return 0; } @@ -381,7 +384,9 @@ static int spcom_rx(struct spcom_channel *ch, mutex_lock(&ch->lock); if (timeout_msec && timeleft == 0) { - pr_err("rx_done timeout expired %d ms\n", timeout_msec); + ch->txn_id++; /* to drop expired rx packet later */ + pr_err("rx_done timeout expired %d ms, set txn_id=%d\n", + timeout_msec, ch->txn_id); ret = -ETIMEDOUT; goto exit_err; } else if (ch->rpmsg_abort) { @@ -395,16 +400,16 @@ static int spcom_rx(struct spcom_channel *ch, ret = -ERESTARTSYS; goto exit_err; } else if (ch->actual_rx_size) { - pr_debug("actual_rx_size is [%zu]\n", - ch->actual_rx_size); + pr_debug("actual_rx_size is [%zu], txn_id %d\n", + ch->actual_rx_size, ch->txn_id); } else { pr_err("actual_rx_size is zero.\n"); ret = -EFAULT; goto exit_err; } } else { - pr_debug("pending data size [%zu], requested size [%u]\n", - ch->actual_rx_size, size); + pr_debug("pending data size [%zu], requested size [%zu], ch->txn_id %d\n", + ch->actual_rx_size, size, ch->txn_id); } if (!ch->rpmsg_rx_buf) { pr_err("invalid rpmsg_rx_buf.\n"); @@ -624,12 +629,17 @@ static int spcom_handle_send_command(struct spcom_channel *ch, hdr = tx_buf; mutex_lock(&ch->lock); - /* Header */ - hdr->txn_id = ch->txn_id; + if (ch->comm_role_undefined) { + pr_debug("ch [%s] send first -> it is client\n", ch->name); + ch->comm_role_undefined = false; + ch->is_server = false; + } + if (!ch->is_server) { ch->txn_id++; /* client sets the request txn_id */ ch->response_timeout_msec = timeout_msec; } + hdr->txn_id = ch->txn_id; /* user buf */ memcpy(hdr->buf, buf, buf_size); @@ -818,12 +828,16 @@ static int spcom_handle_send_modified_command(struct spcom_channel *ch, hdr = tx_buf; mutex_lock(&ch->lock); - /* Header */ - hdr->txn_id = ch->txn_id; + if (ch->comm_role_undefined) { + pr_debug("ch [%s] send first -> it is client\n", ch->name); + ch->comm_role_undefined = false; + ch->is_server = false; + } if (!ch->is_server) { ch->txn_id++; /* client sets the request txn_id */ ch->response_timeout_msec = timeout_msec; } + hdr->txn_id = ch->txn_id; /* user buf */ memcpy(hdr->buf, buf, buf_size); @@ -1308,7 +1322,6 @@ static int spcom_device_open(struct inode *inode, struct file *filp) ch->is_busy = true; ch->pid = pid; - ch->txn_id = INITIAL_TXN_ID; mutex_unlock(&ch->lock); filp->private_data = ch; @@ -1363,7 +1376,13 @@ static int spcom_device_release(struct inode *inode, struct file *filp) ch->is_busy = false; ch->pid = 0; - ch->txn_id = INITIAL_TXN_ID; /* use non-zero nonce for debug */ + if (ch->rpmsg_rx_buf) { + pr_debug("ch [%s] discarting unconsumed rx packet actual_rx_size=%d\n", + name, ch->actual_rx_size); + kfree(ch->rpmsg_rx_buf); + ch->rpmsg_rx_buf = NULL; + } + ch->actual_rx_size = 0; mutex_unlock(&ch->lock); filp->private_data = NULL; @@ -1844,6 +1863,7 @@ static void spcom_signal_rx_done(struct work_struct *ignored) { struct spcom_channel *ch; struct rx_buff_list *rx_item; + struct spcom_msg_hdr *hdr; unsigned long flags; spin_lock_irqsave(&spcom_dev->rx_lock, flags); @@ -1860,7 +1880,17 @@ static void spcom_signal_rx_done(struct work_struct *ignored) continue; } ch = rx_item->ch; + hdr = (struct spcom_msg_hdr *)rx_item->rpmsg_rx_buf; mutex_lock(&ch->lock); + + if (ch->comm_role_undefined) { + ch->comm_role_undefined = false; + ch->is_server = true; + ch->txn_id = hdr->txn_id; + pr_debug("ch [%s] first packet txn_id=%d, it is server\n", + ch->name, ch->txn_id); + } + if (ch->rpmsg_abort) { if (ch->rpmsg_rx_buf) { pr_debug("ch [%s] rx aborted free %d bytes\n", @@ -1873,6 +1903,13 @@ static void spcom_signal_rx_done(struct work_struct *ignored) if (ch->rpmsg_rx_buf) { pr_err("ch [%s] previous buffer not consumed %lu bytes\n", ch->name, ch->actual_rx_size); + kfree(ch->rpmsg_rx_buf); + ch->rpmsg_rx_buf = NULL; + ch->actual_rx_size = 0; + } + if (!ch->is_server && (hdr->txn_id != ch->txn_id)) { + pr_err("ch [%s] rx dropped txn_id %d, ch->txn_id %d\n", + ch->name, hdr->txn_id, ch->txn_id); goto rx_aborted; } ch->rpmsg_rx_buf = rx_item->rpmsg_rx_buf; @@ -1959,6 +1996,7 @@ static int spcom_rpdev_probe(struct rpmsg_device *rpdev) mutex_lock(&ch->lock); ch->rpdev = rpdev; ch->rpmsg_abort = false; + ch->txn_id = INITIAL_TXN_ID; complete_all(&ch->connect); mutex_unlock(&ch->lock); @@ -2005,6 +2043,7 @@ static void spcom_rpdev_remove(struct rpmsg_device *rpdev) ch->rpdev = NULL; ch->rpmsg_abort = true; + ch->txn_id = 0; complete_all(&ch->rx_done); mutex_unlock(&ch->lock); -- GitLab From 59167d0f0c67982d1aa5cdc662a9cc9e466b403c Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 24 Jan 2019 15:47:33 +0530 Subject: [PATCH 1129/1286] defconfig: Enable PM wakelock config on sdxprairie Enable PM wakelock config. Change-Id: I620ca441e43b5748d17e38e614b827655dbc8a7d Signed-off-by: Maulik Shah --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 3 +++ arch/arm/configs/vendor/sdxprairie_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 5a97981a798c..a40e99673c50 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -43,6 +43,9 @@ CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 8eb28c70f6a7..ef8bd3cce96e 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -43,6 +43,9 @@ CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -- GitLab From da9021cc2b0dbc4b5d294c12c4ef7e9726a8a46d Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 24 Jan 2019 15:50:02 +0530 Subject: [PATCH 1130/1286] ARM: dts: msm: Add QMP debugfs support for sdxprairie Add device bindings for QMP debugfs client. Change-Id: I9b88a936421d4f5c05b0a2820bf79a20a2c06224 Signed-off-by: Maulik Shah --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index e306ea838849..56645e85ecec 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -687,6 +687,12 @@ #mbox-cells = <1>; }; + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + apps_rsc: mailbox@17840000 { compatible = "qcom,tcs-drv"; label = "apps_rsc"; -- GitLab From 953c7f1c5fd589b08f3023466639fad882421a78 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 24 Jan 2019 16:00:54 +0530 Subject: [PATCH 1131/1286] defconfig: Enable QMP debugfs client on sdxprairie Enable QMP debugfs client support. Change-Id: I1681267bdaa35e7e8888ecad8f9e8c031e4b519c Signed-off-by: Maulik Shah --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index a40e99673c50..d26b9ce1e656 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -363,6 +363,7 @@ CONFIG_QCOM_GLINK_PKT=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_ARM_MEMLAT_MON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index ef8bd3cce96e..f30251297f06 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -355,6 +355,7 @@ CONFIG_QCOM_GLINK_PKT=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_ARM_MEMLAT_MON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y -- GitLab From acb7bce3e1ba37909adfebc43e3cc02f80460683 Mon Sep 17 00:00:00 2001 From: Manoj Prabhu B Date: Fri, 25 Jan 2019 14:33:15 +0530 Subject: [PATCH 1132/1286] diag: Return proper value in error case Presently for error cases return value is improperly updated. Proper handling is added in error cases to maintain proper return value. Change-Id: I771124b8a1eaa29a2eca246cd8c1457309745a85 Signed-off-by: Manoj Prabhu B --- drivers/char/diag/diagchar_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c index f69c9f556cda..7858bda636a1 100644 --- a/drivers/char/diag/diagchar_core.c +++ b/drivers/char/diag/diagchar_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2008-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -202,6 +202,7 @@ do { \ if ((count < ret+length) || (copy_to_user(buf, \ (void *)&data, length))) { \ ret = -EFAULT; \ + break; \ } \ ret += length; \ } while (0) -- GitLab From 034fee39d2c75e7d84b448af3b8aa3bfe2c4de01 Mon Sep 17 00:00:00 2001 From: Shefali Jain Date: Mon, 14 Jan 2019 16:20:20 +0530 Subject: [PATCH 1133/1286] clk: qcom: gcc-qcs405: Add support for bias pll clock Add support for misc_reset, ahb and aon clock. Change-Id: I4f105fcfaed3a83078a350897b55e41748c8f44a Signed-off-by: Shefali Jain --- drivers/clk/qcom/gcc-qcs405.c | 46 ++++++++++++++++++++- include/dt-bindings/clock/qcom,gcc-qcs405.h | 6 ++- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs405.c b/drivers/clk/qcom/gcc-qcs405.c index a6eaac1f2180..fc1ba78da814 100644 --- a/drivers/clk/qcom/gcc-qcs405.c +++ b/drivers/clk/qcom/gcc-qcs405.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1401,6 +1401,46 @@ static struct clk_rcg2 vsync_clk_src = { }, }; +static struct clk_branch gcc_bias_pll_misc_reset_clk = { + .halt_reg = 0x3c004, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x3c004, + .enable_is_inverted = true, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bias_pll_misc_reset_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bias_pll_ahb_clk = { + .halt_reg = 0x3c008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3c008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bias_pll_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bias_pll_aon_clk = { + .halt_reg = 0x3c00c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x3c00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bias_pll_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_apss_ahb_clk = { .halt_reg = 0x4601c, .halt_check = BRANCH_HALT_VOTED, @@ -2847,6 +2887,9 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, + [GCC_BIAS_PLL_MISC_RESET_CLK] = &gcc_bias_pll_misc_reset_clk.clkr, + [GCC_BIAS_PLL_AHB_CLK] = &gcc_bias_pll_ahb_clk.clkr, + [GCC_BIAS_PLL_AON_CLK] = &gcc_bias_pll_aon_clk.clkr, }; static const struct qcom_reset_map gcc_qcs405_resets[] = { @@ -2864,6 +2907,7 @@ static const struct qcom_reset_map gcc_qcs405_resets[] = { [GCC_PCIE_0_LINK_DOWN_BCR] = {0x3E038}, [GCC_PCIEPHY_0_PHY_BCR] = {0x3E03C}, [GCC_EMAC_BCR] = {0x4E000}, + [GCC_BIAS_PLL_BCR] = {0x3C000}, }; static const struct regmap_config gcc_qcs405_regmap_config = { diff --git a/include/dt-bindings/clock/qcom,gcc-qcs405.h b/include/dt-bindings/clock/qcom,gcc-qcs405.h index 67e1fcf11fc0..9a61ce8a7b35 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs405.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs405.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -153,6 +153,9 @@ #define GCC_CRYPTO_CLK 137 #define GCC_MDP_TBU_CLK 138 #define GCC_QDSS_DAP_CLK 139 +#define GCC_BIAS_PLL_MISC_RESET_CLK 142 +#define GCC_BIAS_PLL_AHB_CLK 143 +#define GCC_BIAS_PLL_AON_CLK 144 #define GCC_GENI_IR_BCR 0 #define GCC_USB_HS_BCR 1 @@ -168,5 +171,6 @@ #define GCC_PCIE_0_LINK_DOWN_BCR 11 #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 +#define GCC_BIAS_PLL_BCR 14 #endif -- GitLab From 8ee08d03390898616401bc35111f5ba6612ad04a Mon Sep 17 00:00:00 2001 From: Shaoqing Liu Date: Mon, 28 Jan 2019 14:44:00 +0800 Subject: [PATCH 1134/1286] ARM: dts: msm: Add mem_dump node for sdxprairie ADD mem_dump node for sdxprairie to support memory dump feature. Change-Id: I43b1daddaf7de60d9bbe1d49b985e6bce164a05d Signed-off-by: Shaoqing Liu --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index e306ea838849..58257bf6d38f 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -113,6 +113,12 @@ reusable; size = <0x1400000>; }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x400000>; + }; }; cpus { @@ -794,6 +800,47 @@ <&apps_smmu 0x0074 0x0013>; }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + + tmc_etf { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + qcom_tzlog: tz-log@0x1468f720 { compatible = "qcom,tz-log"; reg = <0x1468f720 0x2000>; -- GitLab From c577a71fdb2d103c5e4fd8d9002367085fc46f74 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Fri, 25 Jan 2019 20:26:55 +0530 Subject: [PATCH 1135/1286] ARM: dts: msm: Update LDO18 voltage range for trinket LDO18A is shared between UFS and display driver. This change updates max voltage range for LDO18A to allow voting from display driver. Change-Id: I12dbf298a698d54b7edfd05f9e95ebd0e512525c Signed-off-by: Sayali Lokhande --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 2 ++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 5bfefed8f4fe..891b14d22755 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -251,6 +251,8 @@ qcom,vddp-ref-clk-supply = <&pm6125_l18>; qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1232000>; status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 8a01883274d1..fd0a68147057 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -234,6 +234,8 @@ qcom,vddp-ref-clk-supply = <&pm6125_l18>; qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1232000>; status = "ok"; }; -- GitLab From f35bc36099a7c5816edee756a3705e669e3a4416 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Mon, 28 Jan 2019 13:10:46 +0530 Subject: [PATCH 1136/1286] power: qpnp-qg: Fix the return value The return value should be 0 on success, however the iio read reports 1 on success, ignore this by reporting 0 on success from qg_battery_temp. Change-Id: Ibdf0015870ebf56cb4565d1a8a342b8f998c68ba Signed-off-by: Anirudh Ghayal --- drivers/power/supply/qcom/qg-util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/qg-util.c b/drivers/power/supply/qcom/qg-util.c index 2154b318d86b..0428d8f0537e 100644 --- a/drivers/power/supply/qcom/qg-util.c +++ b/drivers/power/supply/qcom/qg-util.c @@ -368,7 +368,7 @@ int qg_get_battery_temp(struct qpnp_qg *chip, int *temp) } pr_debug("batt_temp = %d\n", *temp); - return rc; + return 0; } int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua) -- GitLab From 14ac7e5b25e7913266615d6ac14f2b06c929c768 Mon Sep 17 00:00:00 2001 From: Amir Levy Date: Mon, 28 Jan 2019 10:11:34 +0200 Subject: [PATCH 1137/1286] msm: ipa4: 11ad integration fixes Bug fixes and configurations changes requested by GSI FW. Change-Id: I5b736115213bef1feda7184ca839426b6aba0848 Signed-off-by: Amir Levy --- drivers/platform/msm/ipa/ipa_api.c | 8 +- .../platform/msm/ipa/ipa_clients/ipa_wigig.c | 37 +++- drivers/platform/msm/ipa/ipa_v3/ipa_dp.c | 13 +- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 3 +- drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c | 208 ++++++++++++++---- include/linux/ipa_wigig.h | 18 +- include/linux/msm_gsi.h | 19 +- 7 files changed, 230 insertions(+), 76 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c index 7558248ad6a0..b03509373539 100644 --- a/drivers/platform/msm/ipa/ipa_api.c +++ b/drivers/platform/msm/ipa/ipa_api.c @@ -201,13 +201,13 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = { __stringify(RESERVED_PROD_86), __stringify(IPA_CLIENT_APPS_WAN_COAL_CONS), __stringify(IPA_CLIENT_WIGIG_PROD), - __stringify(IPA_CLIENT_WIGIG_CONS1), + __stringify(IPA_CLIENT_WIGIG1_CONS), __stringify(RESERVERD_PROD_90), - __stringify(IPA_CLIENT_WIGIG_CONS2), + __stringify(IPA_CLIENT_WIGIG2_CONS), __stringify(RESERVERD_PROD_92), - __stringify(IPA_CLIENT_WIGIG_CONS3), + __stringify(IPA_CLIENT_WIGIG3_CONS), __stringify(RESERVERD_PROD_94), - __stringify(IPA_CLIENT_WIGIG_CONS4), + __stringify(IPA_CLIENT_WIGIG4_CONS), __stringify(IPA_CLIENT_AQC_ETHERNET_PROD), __stringify(IPA_CLIENT_AQC_ETHERNET_CONS), }; diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c b/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c index 7ea71c9c96a1..aa4f776547a8 100644 --- a/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c +++ b/drivers/platform/msm/ipa/ipa_clients/ipa_wigig.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -103,6 +103,14 @@ int ipa_wigig_init(struct ipa_wigig_init_in_params *in, ipa_wigig_ctx->dma_ep_misc_pa = in->dma_ep_misc_pa; ipa_wigig_ctx->periph_baddr_pa = in->periph_baddr_pa; + IPA_WIGIG_DBG( + "periph_baddr_pa 0x%pa pseudo_cause_pa 0x%pa, int_gen_tx_pa 0x%pa, int_gen_rx_pa 0x%pa, dma_ep_misc_pa 0x%pa" + , &ipa_wigig_ctx->periph_baddr_pa, + &ipa_wigig_ctx->pseudo_cause_pa, + &ipa_wigig_ctx->int_gen_tx_pa, + &ipa_wigig_ctx->int_gen_rx_pa, + &ipa_wigig_ctx->dma_ep_misc_pa); + inout.notify = in->notify; inout.priv = in->priv; if (ipa_wigig_uc_init(&inout, in->int_notify, &out->uc_db_pa)) { @@ -111,6 +119,8 @@ int ipa_wigig_init(struct ipa_wigig_init_in_params *in, return -EFAULT; } + IPA_WIGIG_DBG("uc_db_pa 0x%pa\n", &out->uc_db_pa); + out->is_uc_ready = inout.is_uC_ready; IPA_WIGIG_DBG("exit\n"); @@ -156,7 +166,7 @@ bool ipa_wigig_is_smmu_enabled(void) ipa_get_smmu_params(&in, &out); - IPA_WIGIG_DBG("exit\n"); + IPA_WIGIG_DBG("exit (%d)\n", out.smmu_enable); return out.smmu_enable; } @@ -176,6 +186,11 @@ static int ipa_wigig_commit_partial_hdr( return -EINVAL; } + IPA_WIGIG_DBG("dst_mac_addr_offset %d hdr_len %d hdr_type %d\n", + hdr_info->dst_mac_addr_offset, + hdr_info->hdr_len, + hdr_info->hdr_type); + hdr->commit = 1; hdr->num_hdrs = 2; @@ -264,8 +279,11 @@ int ipa_wigig_reg_intf( return -EPERM; } - IPA_WIGIG_DBG("register interface for netdev %s\n", - in->netdev_name); + IPA_WIGIG_DBG( + "register interface for netdev %s, MAC 0x[%X][%X][%X][%X][%X][%X]\n" + , in->netdev_name, + in->netdev_mac[0], in->netdev_mac[1], in->netdev_mac[2], + in->netdev_mac[3], in->netdev_mac[4], in->netdev_mac[5]); mutex_lock(&ipa_wigig_ctx->lock); list_for_each_entry(entry, &ipa_wigig_ctx->head_intf_list, link) @@ -396,13 +414,13 @@ int ipa_wigig_dereg_intf(const char *netdev_name) struct ipa_wigig_intf_info *entry; struct ipa_wigig_intf_info *next; - IPA_WIGIG_DBG("\n"); - if (!netdev_name) { IPA_WIGIG_ERR("no netdev name\n"); return -EINVAL; } + IPA_WIGIG_DBG("netdev %s\n", netdev_name); + if (!ipa_wigig_ctx) { IPA_WIGIG_ERR("wigig ctx is not initialized\n"); return -EPERM; @@ -1232,6 +1250,7 @@ int ipa_wigig_disconn_pipe(enum ipa_client_type client) /* RX will be disconnected last, deinit uC msi config */ if (client == IPA_CLIENT_WIGIG_PROD) { + IPA_WIGIG_DBG("Rx pipe disconnected, deIniting uc\n"); ret = ipa_wigig_uc_msi_init(false, ipa_wigig_ctx->periph_baddr_pa, ipa_wigig_ctx->pseudo_cause_pa, @@ -1242,6 +1261,12 @@ int ipa_wigig_disconn_pipe(enum ipa_client_type client) IPA_WIGIG_ERR("failed unmapping msi regs\n"); WARN_ON(1); } + + ret = ipa_pm_deregister(ipa_wigig_ctx->ipa_pm_hdl); + if (ret) { + IPA_WIGIG_ERR("failed dereg pm\n"); + WARN_ON(1); + } } if (ipa_wigig_is_smmu_enabled()) ipa_wigig_clean_smmu_info(client); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c index e5f2aee00cac..649b2f07c2fb 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -1674,6 +1674,8 @@ int ipa3_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, } if (dst_ep_idx != -1) { + int skb_idx; + /* SW data path */ data_idx = 0; if (sys->policy == IPA_POLICY_NOINTR_MODE) { @@ -1705,6 +1707,8 @@ int ipa3_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, desc[data_idx].dma_address_valid = true; desc[data_idx].dma_address = meta->dma_address; } + + skb_idx = data_idx; data_idx++; for (f = 0; f < num_frags; f++) { @@ -1715,10 +1719,11 @@ int ipa3_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, } /* don't free skb till frag mappings are released */ if (num_frags) { - desc[data_idx + f - 1].callback = desc[2].callback; - desc[data_idx + f - 1].user1 = desc[2].user1; - desc[data_idx + f - 1].user2 = desc[2].user2; - desc[data_idx - 1].callback = NULL; + desc[data_idx + f - 1].callback = + desc[skb_idx].callback; + desc[data_idx + f - 1].user1 = desc[skb_idx].user1; + desc[data_idx + f - 1].user2 = desc[skb_idx].user2; + desc[skb_idx].callback = NULL; } if (ipa3_send(sys, num_frags + data_idx, desc, true)) { diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index c4442f14e293..f957d3dc97d2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -5004,7 +5004,8 @@ int ipa3_write_qmap_id(struct ipa_ioc_write_qmapid *param_in) if (param_in->client == IPA_CLIENT_USB_PROD || param_in->client == IPA_CLIENT_HSIC1_PROD || param_in->client == IPA_CLIENT_ODU_PROD || - param_in->client == IPA_CLIENT_ETHERNET_PROD) { + param_in->client == IPA_CLIENT_ETHERNET_PROD || + param_in->client == IPA_CLIENT_WIGIG_PROD) { result = ipa3_cfg_ep_metadata(ipa_ep_idx, &meta); } else if (param_in->client == IPA_CLIENT_WLAN1_PROD || param_in->client == IPA_CLIENT_WLAN2_PROD) { diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c index c6db5f398d6d..71475b0d25a4 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_wigig_i.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -16,6 +16,7 @@ #include #define IPA_WIGIG_DESC_RING_EL_SIZE 32 +#define IPA_WIGIG_STATUS_RING_EL_SIZE 16 #define GSI_STOP_MAX_RETRY_CNT 10 @@ -25,6 +26,9 @@ #define IPA_WIGIG_LSB_MASK 0x00000000FFFFFFFF #define IPA_WIGIG_MSB(num) ((u32)((num & IPA_WIGIG_MSB_MASK) >> 32)) #define IPA_WIGIG_LSB(num) ((u32)(num & IPA_WIGIG_LSB_MASK)) +/* extract PCIE addresses [0:39] relevant msb */ +#define IPA_WIGIG_8_MSB_MASK 0xFF00000000 +#define IPA_WIGIG_8_MSB(num) ((u32)((num & IPA_WIGIG_8_MSB_MASK) >> 32)) #define W11AD_RX 0 #define W11AD_TX 1 #define W11AD_TO_GSI_DB_m 1 @@ -94,11 +98,10 @@ int ipa3_wigig_uc_init( if (result) { inout->is_uC_ready = false; ipa3_ctx->uc_wigig_ctx.uc_ready_cb = inout->notify; - ipa3_ctx->uc_wigig_ctx.priv = inout->priv; } else { inout->is_uC_ready = true; } - + ipa3_ctx->uc_wigig_ctx.priv = inout->priv; ipa3_ctx->uc_wigig_ctx.misc_notify_cb = int_notify; *uc_db_pa = ipa3_ctx->ipa_wrapper_base + @@ -400,6 +403,8 @@ static int ipa3_wigig_config_gsi(bool Rx, struct ipa_wigig_tx_pipe_data_buffer_info *tx_dbuff; struct ipa_wigig_tx_pipe_data_buffer_info_smmu *tx_dbuff_smmu; + IPADBG("%s, %s\n", Rx ? "Rx" : "Tx", smmu_en ? "smmu en" : "smmu dis"); + /* alloc event ring */ memset(&evt_props, 0, sizeof(evt_props)); evt_props.intf = GSI_EVT_CHTYPE_11AD_EV; @@ -463,7 +468,7 @@ static int ipa3_wigig_config_gsi(bool Rx, channel_props.dir = GSI_CHAN_DIR_FROM_GSI; channel_props.re_size = GSI_CHAN_RE_SIZE_16B; - channel_props.prot - GSI_CHAN_PROT_11AD; + channel_props.prot = GSI_CHAN_PROT_11AD; channel_props.ch_id = ep_gsi->ipa_gsi_chan_num; channel_props.evt_ring_hdl = ep->gsi_evt_ring_hdl; channel_props.xfer_cb = NULL; @@ -521,8 +526,21 @@ static int ipa3_wigig_config_gsi(bool Rx, gsi_scratch.rx_11ad.fixed_data_buffer_size_pow_2 = ilog2(rx_dbuff->data_buffer_size); } - IPADBG("fixed_data_buffer_size_pow_2 %d\n", + IPADBG("rx scratch: status_ring_hwtail_address_lsb 0x%X\n", + gsi_scratch.rx_11ad.status_ring_hwtail_address_lsb); + IPADBG("rx scratch: status_ring_hwtail_address_msb 0x%X\n", + gsi_scratch.rx_11ad.status_ring_hwtail_address_msb); + IPADBG("rx scratch: data_buffers_base_address_lsb 0x%X\n", + gsi_scratch.rx_11ad.data_buffers_base_address_lsb); + IPADBG("rx scratch: data_buffers_base_address_msb 0x%X\n", + gsi_scratch.rx_11ad.data_buffers_base_address_msb); + IPADBG("rx scratch: fixed_data_buffer_size_pow_2 %d\n", gsi_scratch.rx_11ad.fixed_data_buffer_size_pow_2); + IPADBG("rx scratch 0x[%X][%X][%X][%X]\n", + gsi_scratch.data.word1, + gsi_scratch.data.word2, + gsi_scratch.data.word3, + gsi_scratch.data.word4); } else { if (smmu_en) { tx_dbuff_smmu = @@ -535,12 +553,19 @@ static int ipa3_wigig_config_gsi(bool Rx, gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb = IPA_WIGIG_LSB( pipe_smmu->status_ring_HWTAIL_pa); - gsi_scratch.tx_11ad.status_ring_hwtail_address_msb = - IPA_WIGIG_MSB( - pipe_smmu->status_ring_HWTAIL_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb = + IPA_WIGIG_LSB( + pipe_smmu->status_ring_HWHEAD_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb = + IPA_WIGIG_8_MSB( + pipe_smmu->status_ring_HWHEAD_pa); gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2 = ilog2(tx_dbuff_smmu->data_buffer_size); + + gsi_scratch.tx_11ad.status_ring_num_elem = + pipe_smmu->status_ring_size / + IPA_WIGIG_STATUS_RING_EL_SIZE; } else { tx_dbuff = (struct ipa_wigig_tx_pipe_data_buffer_info *)buff; @@ -551,15 +576,35 @@ static int ipa3_wigig_config_gsi(bool Rx, gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb = IPA_WIGIG_LSB( pipe->status_ring_HWTAIL_pa); - gsi_scratch.tx_11ad.status_ring_hwtail_address_msb = - IPA_WIGIG_MSB( - pipe->status_ring_HWTAIL_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb = + IPA_WIGIG_LSB( + pipe->status_ring_HWHEAD_pa); + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb = + IPA_WIGIG_8_MSB(pipe->status_ring_HWHEAD_pa); + + gsi_scratch.tx_11ad.status_ring_num_elem = + pipe->status_ring_size / + IPA_WIGIG_STATUS_RING_EL_SIZE; gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2 = ilog2(tx_dbuff->data_buffer_size); } - IPADBG("fixed_data_buffer_size_pow_2 %d\n", + gsi_scratch.tx_11ad.update_status_hwtail_mod_threshold = 1; + IPADBG("tx scratch: status_ring_hwtail_address_lsb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwtail_address_lsb); + IPADBG("tx scratch: status_ring_hwhead_address_lsb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwhead_address_lsb); + IPADBG("tx scratch: status_ring_hwhead_hwtail_8_msb 0x%X\n", + gsi_scratch.tx_11ad.status_ring_hwhead_hwtail_8_msb); + IPADBG("tx scratch:status_ring_num_elem %d\n", + gsi_scratch.tx_11ad.status_ring_num_elem); + IPADBG("tx scratch:fixed_data_buffer_size_pow_2 %d\n", gsi_scratch.tx_11ad.fixed_data_buffer_size_pow_2); + IPADBG("tx scratch 0x[%X][%X][%X][%X]\n", + gsi_scratch.data.word1, + gsi_scratch.data.word2, + gsi_scratch.data.word3, + gsi_scratch.data.word4); } IPADBG("ch_id: %d\n", channel_props.ch_id); @@ -573,9 +618,12 @@ static int ipa3_wigig_config_gsi(bool Rx, gsi_res = gsi_alloc_channel(&channel_props, ipa3_ctx->gsi_dev_hdl, &ep->gsi_chan_hdl); - if (gsi_res != GSI_STATUS_SUCCESS) + if (gsi_res != GSI_STATUS_SUCCESS) { + IPAERR("gsi_alloc_channel failed %d\n", gsi_res); goto fail_alloc_channel; + } + IPADBG("Writing Channel scratch\n"); ep->gsi_mem_info.chan_ring_len = channel_props.ring_len; ep->gsi_mem_info.chan_ring_base_addr = channel_props.ring_base_addr; ep->gsi_mem_info.chan_ring_base_vaddr = @@ -589,6 +637,9 @@ static int ipa3_wigig_config_gsi(bool Rx, goto fail_write_channel_scratch; } + IPADBG("exit\n"); + + return 0; fail_write_channel_scratch: gsi_dealloc_channel(ep->gsi_chan_hdl); fail_alloc_channel: @@ -740,18 +791,28 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) ep->client_notify = input_smmu->notify; ep->priv = input_smmu->priv; + IPADBG( + "desc_ring_base %lld desc_ring_size %d status_ring_base %lld status_ring_size %d", + (unsigned long long)input_smmu->pipe_smmu.desc_ring_base_iova, + input_smmu->pipe_smmu.desc_ring_size, + (unsigned long long)input_smmu->pipe_smmu.status_ring_base_iova, + input_smmu->pipe_smmu.status_ring_size); + IPADBG("data_buffer_base_iova %lld data_buffer_size %d", + (unsigned long long)dbuff_smmu->data_buffer_base_iova, + input_smmu->dbuff_smmu.data_buffer_size); + if (IPA_WIGIG_MSB( dbuff_smmu->data_buffer_base_iova) & 0xFFFFFF00) { IPAERR( - "data_buffers_base_address_msb is over the 8 bit limit (0xpa)\n" - , &dbuff_smmu->data_buffer_base_iova); + "data_buffers_base_address_msb is over the 8 bit limit (%lld)\n", + (unsigned long long)dbuff_smmu->data_buffer_base_iova); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); return -EFAULT; } if (dbuff_smmu->data_buffer_size >> 16) { IPAERR( - "data_buffer_size is over the 16 bit limit (0x%X)\n" + "data_buffer_size is over the 16 bit limit (%d)\n" , dbuff_smmu->data_buffer_size); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); return -EFAULT; @@ -761,6 +822,16 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) ep->client_notify = input->notify; ep->priv = input->priv; + IPADBG( + "desc_ring_base_pa %pa desc_ring_size %d status_ring_base_pa %pa status_ring_size %d", + &input->pipe.desc_ring_base_pa, + input->pipe.desc_ring_size, + &input->pipe.status_ring_base_pa, + input->pipe.status_ring_size); + IPADBG("data_buffer_base_pa %pa data_buffer_size %d", + &input->dbuff.data_buffer_base_pa, + input->dbuff.data_buffer_size); + if ( IPA_WIGIG_MSB(input->dbuff.data_buffer_base_pa) & 0xFFFFFF00) { IPAERR( @@ -790,7 +861,7 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) ep_cfg.mode.mode = IPA_BASIC; - if (ipa3_cfg_ep(ipa_ep_idx, &ep->cfg)) { + if (ipa3_cfg_ep(ipa_ep_idx, &ep_cfg)) { IPAERR("fail to setup rx pipe cfg\n"); result = -EFAULT; goto fail; @@ -818,13 +889,6 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) input->pipe.status_ring_HWHEAD_pa; } - result = ipa3_wigig_config_uc( - true, true, 0, - ep_gsi->ipa_gsi_chan_num, - status_ring_HWHEAD_pa); - if (result) - goto fail_uc_config; - result = ipa3_wigig_config_gsi(true, is_smmu_enabled, pipe_info, @@ -833,6 +897,13 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) if (result) goto fail_gsi; + result = ipa3_wigig_config_uc( + true, true, 0, + ep_gsi->ipa_gsi_chan_num, + status_ring_HWHEAD_pa); + if (result) + goto fail_uc_config; + ipa3_install_dflt_flt_rules(ipa_ep_idx); out->client = IPA_CLIENT_WIGIG_PROD; @@ -845,12 +916,10 @@ int ipa3_conn_wigig_rx_pipe_i(void *in, struct ipa_wigig_conn_out_params *out) return 0; -fail_gsi: - ipa3_wigig_config_uc( - false, true, 0, - ep_gsi->ipa_gsi_chan_num, - status_ring_HWHEAD_pa); fail_uc_config: + /* Release channel and evt*/ + ipa3_release_gsi_channel(ipa_ep_idx); +fail_gsi: if (input_smmu) ipa3_wigig_smmu_map_channel(true, &input_smmu->pipe_smmu, &input_smmu->dbuff_smmu, false); @@ -881,11 +950,21 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) is_smmu_enabled = !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]; if (is_smmu_enabled) { input_smmu = (struct ipa_wigig_conn_tx_in_params_smmu *)in; + + IPADBG( + "desc_ring_base %lld desc_ring_size %d status_ring_base %lld status_ring_size %d", + (unsigned long long)input_smmu->pipe_smmu.desc_ring_base_iova, + input_smmu->pipe_smmu.desc_ring_size, + (unsigned long long)input_smmu->pipe_smmu.status_ring_base_iova, + input_smmu->pipe_smmu.status_ring_size); + IPADBG("num buffers %d, data buffer size %d\n", + input_smmu->dbuff_smmu.num_buffers, + input_smmu->dbuff_smmu.data_buffer_size); + if (ipa3_wigig_tx_bit_to_ep(input_smmu->int_gen_tx_bit_num, &tx_client)) { return -EINVAL; } - wifi_ch = input_smmu->int_gen_tx_bit_num; if (input_smmu->dbuff_smmu.data_buffer_size >> 16) { IPAERR( "data_buffer_size is over the 16 bit limit (0x%X)\n" @@ -893,16 +972,37 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) return -EFAULT; } + if (IPA_WIGIG_8_MSB( + input_smmu->pipe_smmu.status_ring_HWHEAD_pa) + != IPA_WIGIG_8_MSB( + input_smmu->pipe_smmu.status_ring_HWTAIL_pa)) { + IPAERR( + "status ring HWHEAD and HWTAIL differ in 8 MSbs head 0x%X tail 0x%X\n" + , input_smmu->pipe_smmu.status_ring_HWHEAD_pa, + input_smmu->pipe_smmu.status_ring_HWTAIL_pa); + return -EFAULT; + } + + wifi_ch = input_smmu->int_gen_tx_bit_num; + /* convert to kBytes */ aggr_byte_limit = IPA_ADJUST_AGGR_BYTE_HARD_LIMIT( input_smmu->dbuff_smmu.data_buffer_size); } else { input = (struct ipa_wigig_conn_tx_in_params *)in; + + IPADBG( + "desc_ring_base_pa %pa desc_ring_size %d status_ring_base_pa %pa status_ring_size %d", + &input->pipe.desc_ring_base_pa, + input->pipe.desc_ring_size, + &input->pipe.status_ring_base_pa, + input->pipe.status_ring_size); + IPADBG("data_buffer_size %d", input->dbuff.data_buffer_size); + if (ipa3_wigig_tx_bit_to_ep(input->int_gen_tx_bit_num, &tx_client)) { return -EINVAL; } - wifi_ch = input->int_gen_tx_bit_num; if (input->dbuff.data_buffer_size >> 16) { IPAERR( @@ -911,6 +1011,19 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) return -EFAULT; } + if (IPA_WIGIG_8_MSB( + input->pipe.status_ring_HWHEAD_pa) + != IPA_WIGIG_8_MSB( + input->pipe.status_ring_HWTAIL_pa)) { + IPAERR( + "status ring HWHEAD and HWTAIL differ in 8 MSbs head 0x%X tail 0x%X\n" + , input->pipe.status_ring_HWHEAD_pa, + input->pipe.status_ring_HWTAIL_pa); + return -EFAULT; + } + + wifi_ch = input->int_gen_tx_bit_num; + /* convert to kBytes */ aggr_byte_limit = IPA_ADJUST_AGGR_BYTE_HARD_LIMIT( input->dbuff.data_buffer_size); @@ -1006,13 +1119,6 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) input->pipe.desc_ring_HWHEAD_pa; } - result = ipa3_wigig_config_uc( - true, false, wifi_ch, - ep_gsi->ipa_gsi_chan_num, - desc_ring_HWHEAD_pa); - if (result) - goto fail_uc_config; - result = ipa3_wigig_config_gsi(false, is_smmu_enabled, pipe_info, @@ -1021,6 +1127,13 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) if (result) goto fail_gsi; + result = ipa3_wigig_config_uc( + true, false, wifi_ch, + ep_gsi->ipa_gsi_chan_num, + desc_ring_HWHEAD_pa); + if (result) + goto fail_uc_config; + out->client = tx_client; ep->gsi_offload_state |= IPA_WIGIG_CONNECTED; @@ -1030,12 +1143,10 @@ int ipa3_conn_wigig_client_i(void *in, struct ipa_wigig_conn_out_params *out) ipa_ep_idx); return 0; -fail_gsi: - ipa3_wigig_config_uc( - false, false, wifi_ch, - ep_gsi->ipa_gsi_chan_num, - desc_ring_HWHEAD_pa); fail_uc_config: + /* Release channel and evt*/ + ipa3_release_gsi_channel(ipa_ep_idx); +fail_gsi: if (input_smmu) ipa3_wigig_smmu_map_channel(false, &input_smmu->pipe_smmu, &input_smmu->dbuff_smmu, false); @@ -1159,7 +1270,13 @@ int ipa3_wigig_uc_msi_init(bool init, enum ipa_cpu_2_hw_offload_commands command; bool map = false; - IPADBG("\n"); + IPADBG("params: %s, %pa, %pa, %pa, %pa, %pa\n", + init ? "init" : "deInit", + &periph_baddr_pa, + &pseudo_cause_pa, + &int_gen_tx_pa, + &int_gen_rx_pa, + &dma_ep_misc_pa); /* first make sure registers are SMMU mapped if necessary*/ if ((!ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC])) { @@ -1344,6 +1461,7 @@ int ipa3_enable_wigig_pipe_i(enum ipa_client_type client) goto fail_ring_evt; } + IPADBG("start channel\n"); res = gsi_start_channel(ep->gsi_chan_hdl); if (res != GSI_STATUS_SUCCESS) { IPAERR("gsi_start_channel failed %d\n", res); @@ -1360,6 +1478,8 @@ int ipa3_enable_wigig_pipe_i(enum ipa_client_type client) ep->gsi_mem_info.chan_ring_len - IPA_WIGIG_DESC_RING_EL_SIZE; + IPADBG("ring ch doorbell (0x%llX) TX %d\n", val, + ep->gsi_chan_hdl); res = gsi_ring_ch_ring_db(ep->gsi_chan_hdl, val); if (res) { IPAERR( diff --git a/include/linux/ipa_wigig.h b/include/linux/ipa_wigig.h index f190fe862750..7866fbff83c7 100644 --- a/include/linux/ipa_wigig.h +++ b/include/linux/ipa_wigig.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -84,22 +84,22 @@ struct ipa_wigig_reg_intf_in_params { /* * struct ipa_wigig_pipe_setup_info - WIGIG TX/Rx configuration * @desc_ring_base_pa: physical address of the base of the descriptor ring - * @desc_ring_size: size of the descriptor ring + * @desc_ring_size: size of the descriptor ring in bytes * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL * @status_ring_base_pa: physical address of the base of the status ring - * @status_ring_size: status ring size + * @status_ring_size: status ring size in bytes * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL */ struct ipa_wigig_pipe_setup_info { phys_addr_t desc_ring_base_pa; - u32 desc_ring_size; + u16 desc_ring_size; phys_addr_t desc_ring_HWHEAD_pa; phys_addr_t desc_ring_HWTAIL_pa; phys_addr_t status_ring_base_pa; - u32 status_ring_size; + u16 status_ring_size; phys_addr_t status_ring_HWHEAD_pa; phys_addr_t status_ring_HWTAIL_pa; }; @@ -108,25 +108,25 @@ struct ipa_wigig_pipe_setup_info { * struct ipa_wigig_pipe_setup_info_smmu - WIGIG TX/Rx configuration smmu mode * @desc_ring_base: sg_table of the base of the descriptor ring * @desc_ring_base_iova: IO virtual address mapped to physical base address - * @desc_ring_size: size of the descriptor ring + * @desc_ring_size: size of the descriptor ring in bytes * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL * @status_ring_base: sg_table of the base of the status ring * @status_ring_base_iova: IO virtual address mapped to physical base address - * @status_ring_size: status ring size + * @status_ring_size: status ring size in bytes * @desc_ring_HWHEAD_pa: physical address of the wigig descriptor ring HWHEAD * @desc_ring_HWTAIL_pa: physical address of the wigig descriptor ring HWTAIL */ struct ipa_wigig_pipe_setup_info_smmu { struct sg_table desc_ring_base; u64 desc_ring_base_iova; - u32 desc_ring_size; + u16 desc_ring_size; phys_addr_t desc_ring_HWHEAD_pa; phys_addr_t desc_ring_HWTAIL_pa; struct sg_table status_ring_base; u64 status_ring_base_iova; - u32 status_ring_size; + u16 status_ring_size; phys_addr_t status_ring_HWHEAD_pa; phys_addr_t status_ring_HWTAIL_pa; }; diff --git a/include/linux/msm_gsi.h b/include/linux/msm_gsi.h index ad12b3fc3f4d..6069245d2955 100644 --- a/include/linux/msm_gsi.h +++ b/include/linux/msm_gsi.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -732,22 +732,25 @@ struct __packed gsi_11ad_rx_channel_scratch { * TX channel scratch * * @status_ring_hwtail_address_lsb: Low 32 bits of status ring hwtail address. - * @status_ring_hwtail_address_msb: High 32 bits of status ring hwtail address. + * @status_ring_hwhead_address_lsb: Low 32 bits of status ring hwhead address. + * @status_ring_hwhead_hwtail_8_msb: higher 8 msbs of status ring + * hwhead\hwtail addresses (should be identical). * @update_status_hwtail_mod_threshold: The threshold in (32B) elements for * updating descriptor ring 11ad HWTAIL pointer moderation. + * @status_ring_num_elem - the number of elements in the status ring. * @resv1: reserved bits. - * @resv2: reserved bit. * @fixed_data_buffer_size_pow_2: the fixed buffer size power of 2 (> MTU). - * @resv3: reserved bits. + * @resv2: reserved bits. */ struct __packed gsi_11ad_tx_channel_scratch { uint32_t status_ring_hwtail_address_lsb; - uint32_t status_ring_hwtail_address_msb; + uint32_t status_ring_hwhead_address_lsb; + uint32_t status_ring_hwhead_hwtail_8_msb:8; uint32_t update_status_hwtail_mod_threshold:8; - uint32_t resv1:24; - uint32_t resv2:8; + uint32_t status_ring_num_elem:16; + uint32_t resv1:8; uint32_t fixed_data_buffer_size_pow_2:16; - uint32_t resv3:8; + uint32_t resv2:8; }; /** -- GitLab From d712da9872c161d7d95ef5343cce711fecdba5ed Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Sun, 27 Jan 2019 22:36:16 +0530 Subject: [PATCH 1138/1286] iommu: dma-mapping-fast: Add a check for count in fast_smmu_alloc In fast_smmu_alloc size_t variable size is type casted to int variable count, this variable count can get truncated and can result in memory corruption during unmap, make count as size_t and also add a check for count as sg_alloc_table_from_pages accepts unsigned int value for count. Change-Id: I4780a554c5c062fd9dd229e5cc0ac804b1ba31d8 Signed-off-by: Vijayanand Jitta --- drivers/iommu/dma-mapping-fast.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/dma-mapping-fast.c b/drivers/iommu/dma-mapping-fast.c index 0622720c87f6..23c721b072dc 100644 --- a/drivers/iommu/dma-mapping-fast.c +++ b/drivers/iommu/dma-mapping-fast.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -542,12 +542,22 @@ static void *fast_smmu_alloc(struct device *dev, size_t size, av8l_fast_iopte *ptep; unsigned long flags; struct sg_mapping_iter miter; - unsigned int count = ALIGN(size, SZ_4K) >> PAGE_SHIFT; + size_t count = ALIGN(size, SZ_4K) >> PAGE_SHIFT; int prot = IOMMU_READ | IOMMU_WRITE; /* TODO: extract from attrs */ bool is_coherent = is_dma_coherent(dev, attrs); pgprot_t remap_prot = __get_dma_pgprot(attrs, PAGE_KERNEL, is_coherent); struct page **pages; + /* + * sg_alloc_table_from_pages accepts unsigned int value for count + * so check count doesn't exceed UINT_MAX. + */ + + if (count > UINT_MAX) { + dev_err(dev, "count: %zx exceeds UNIT_MAX\n", count); + return NULL; + } + prot = __get_iommu_pgprot(attrs, prot, is_coherent); *handle = DMA_ERROR_CODE; -- GitLab From ea4f734c81f1f3d075bbce6dbb75e835cbecf96b Mon Sep 17 00:00:00 2001 From: Srikanth Uyyala Date: Sun, 27 Jan 2019 10:50:33 +0530 Subject: [PATCH 1139/1286] msm: camera_v2: fix close sequence of isp stats stream Stats stream close is failing in dual vfe usecases, due to wrong array index is used while deleting the stream. Change-Id: I8fa4b73f257439b13bddadd1b4edd6d2a5508c69 Signed-off-by: Srikanth Uyyala --- .../media/platform/msm/camera_v2/isp/msm_isp_stats_util.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c index 072f3d46dcdc..304356a973a6 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -563,10 +563,11 @@ int msm_isp_release_stats_stream(struct vfe_device *vfe_dev, void *arg) stream_info->buffer_offset[i] = stream_info->buffer_offset[k]; } + stream_info->num_isp--; + stream_info->vfe_dev[stream_info->num_isp] = NULL; stream_info->stream_handle[stream_info->num_isp] = 0; stream_info->buffer_offset[stream_info->num_isp] = 0; - stream_info->num_isp--; stream_info->vfe_mask &= ~(1 << vfe_dev->pdev->id); if (stream_info->num_isp == 0) stream_info->state = STATS_AVAILABLE; -- GitLab From 8acde59488a8a17b8fab4541fff9ead8b3fc52dd Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Mon, 28 Jan 2019 13:53:33 +0530 Subject: [PATCH 1140/1286] usb: gadget: composite: remove duplicated code in OS desc handling When the host wants to fetch OS descriptors, it sends two requests. The first is only for the header and the second for the full amount specified by the header in the first request. The OS descriptor handling code is distinguishing the header-only requests based on the wLength of the setup packet, but the same code is executed in both cases to construct the actual header. Simplify this by always constructing the header and then filling out the rest of the request if the wLength is greater than the size of the header. Also remove the duplicate code for queueing the request to ep0 by adding a goto label. Change-Id: Ifb8ae3bdeaf269caa163ad09696de227f540918f Signed-off-by: Chris Dickens Signed-off-by: Felipe Balbi Git-commit: 636ba13aec8a0198d3fa4e2246e291a19694b50f Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [cchiluve@codeaurora.org: resolve trivial merge conflicts and checkpatch errors] Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/composite.c | 75 +++++++++++----------------------- 1 file changed, 23 insertions(+), 52 deletions(-) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index f28fdfe200e9..4bd8879e277b 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -1566,6 +1566,7 @@ static int fill_ext_compat(struct usb_configuration *c, u8 *buf) int i, count; count = 16; + buf += 16; for (i = 0; i < c->next_interface_id; ++i) { struct usb_function *f; int j; @@ -1641,6 +1642,7 @@ static int fill_ext_prop(struct usb_configuration *c, int interface, u8 *buf) f = c->interface[interface]; count = 10; /* header length */ + buf += 10; for (j = 0; j < f->os_desc_n; ++j) { if (interface != f->os_desc_table[j].if_id) continue; @@ -1980,22 +1982,14 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (w_index != 0x4 || (w_value >> 8)) break; buf[6] = w_index; - if (w_length == 0x10) { - /* Number of ext compat interfaces */ - count = count_ext_compat(os_desc_cfg); - buf[8] = count; - count *= 24; /* 24 B/ext compat desc */ - count += 16; /* header */ - put_unaligned_le32(count, buf); - value = w_length; - } else { - /* "extended compatibility ID"s */ - count = count_ext_compat(os_desc_cfg); - buf[8] = count; - count *= 24; /* 24 B/ext compat desc */ - count += 16; /* header */ - put_unaligned_le32(count, buf); - buf += 16; + /* Number of ext compat interfaces */ + count = count_ext_compat(os_desc_cfg); + buf[8] = count; + count *= 24; /* 24 B/ext compat desc */ + count += 16; /* header */ + put_unaligned_le32(count, buf); + value = w_length; + if (w_length > 0x10) { value = fill_ext_compat(os_desc_cfg, buf); value = min_t(u16, w_length, value); } @@ -2005,47 +1999,23 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) break; interface = w_value & 0xFF; buf[6] = w_index; - if (w_length == 0x0A) { - count = count_ext_prop(os_desc_cfg, - interface); - put_unaligned_le16(count, buf + 8); - count = len_ext_prop(os_desc_cfg, - interface); - put_unaligned_le32(count, buf); - - value = w_length; - } else { - count = count_ext_prop(os_desc_cfg, - interface); - put_unaligned_le16(count, buf + 8); - count = len_ext_prop(os_desc_cfg, - interface); - put_unaligned_le32(count, buf); - buf += 10; + count = count_ext_prop(os_desc_cfg, + interface); + put_unaligned_le16(count, buf + 8); + count = len_ext_prop(os_desc_cfg, + interface); + put_unaligned_le32(count, buf); + value = w_length; + if (w_length > 0x0A) { value = fill_ext_prop(os_desc_cfg, interface, buf); - if (value < 0) - return value; - value = min_t(u16, w_length, value); + if (value >= 0) + value = min_t(u16, w_length, + value); } break; } - - if (value >= 0) { - req->length = value; - req->context = cdev; - req->zero = value < w_length; - value = composite_ep0_queue(cdev, req, - GFP_ATOMIC); - if (value < 0) { - DBG(cdev, "ep_queue --> %d\n", value); - req->status = 0; - if (value != -ESHUTDOWN) - composite_setup_complete( - gadget->ep0, req); - } - } - return value; + goto check_value; } VDBG(cdev, @@ -2119,6 +2089,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) goto done; } +check_value: /* respond with data transfer before status phase? */ if (value >= 0 && value != USB_GADGET_DELAYED_STATUS) { req->length = value; -- GitLab From 675522b8d587b78d8f3b31c301830dc8a5ff76bb Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 27 Jun 2018 12:33:56 +1000 Subject: [PATCH 1141/1286] usb: gadget: Fix OS descriptors support The current code is broken as it re-defines "req" inside the if block, then goto out of it. Thus the request that ends up being sent is not the one that was populated by the code in question. This fixes RNDIS driver autodetect by Windows 10 for me. The bug was introduced by Chris rework to remove the local queuing inside the if { } block of the redefined request. Change-Id: If591ca27e7f5648e9375fc2388c6410f99e82664 Fixes: 636ba13aec8a ("usb: gadget: composite: remove duplicated code in OS desc handling") Cc: # v4.17 Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Felipe Balbi Git-commit: 50b9773c13bffbef32060e67c4483ea7b2eca7b5 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/composite.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 4bd8879e277b..247dbe75379f 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -1963,7 +1963,6 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (cdev->use_os_string && cdev->os_desc_config && (ctrl->bRequestType & USB_TYPE_VENDOR) && ctrl->bRequest == cdev->b_vendor_code) { - struct usb_request *req; struct usb_configuration *os_desc_cfg; u8 *buf; int interface; -- GitLab From 1dd2837de57bff201f6fd3dffec4298075defd3f Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 25 Jan 2019 15:22:35 +0530 Subject: [PATCH 1142/1286] usb: gadget: Stall OS descriptor request for unsupported functions Hosts which request "OS descriptors" from gadgets do so during the enumeration phase and before the configuration is set with SET_CONFIGURATION. Composite driver supports OS descriptor handling in composite_setup function. This requires to pass signature field, vendor code, compatibleID and subCompatibleID from user space. Currently gadget providing this info from usb init scripts irrespective of the functions supported for OS descriptors. In mass-storage only composition, mass storage function doesn't have os descriptor at all, but windows 10 host sending vendor specific request for os descriptors and composite driver handling this request with invalid data. With this invalid info host resetting the bus and never selecting the configuration and leading enumeration issue. Fix this by bailing out from the OS descriptor setup request handling if the functions does not have OS descriptors compatibleID. Change-Id: I4629cee9787201cbb9dbb61c958a3c2f637edb9f Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/gadget/composite.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 247dbe75379f..81be8e68f290 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -1983,6 +1983,12 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) buf[6] = w_index; /* Number of ext compat interfaces */ count = count_ext_compat(os_desc_cfg); + /* + * Bailout if device does not + * have ext_compat interfaces. + */ + if (count == 0) + break; buf[8] = count; count *= 24; /* 24 B/ext compat desc */ count += 16; /* header */ -- GitLab From e763cd84e7c33b8aa141755692991296a1ec39ad Mon Sep 17 00:00:00 2001 From: Mohit Sharma Date: Mon, 28 Jan 2019 13:02:20 +0530 Subject: [PATCH 1143/1286] defconfig: trinket: align with android config requirement Align with android-base.cfg which is android kernel config requirement for trinket defconfig and perf defconfig. Change-Id: I3db4e2d3fd9189a5fdab96db9cc74f88792d0ddf Signed-off-by: Mohit Sharma --- arch/arm64/configs/vendor/trinket-perf_defconfig | 3 +++ arch/arm64/configs/vendor/trinket_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index aff6ef3cbb95..baca22ee325e 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -1,5 +1,6 @@ CONFIG_LOCALVERSION="-perf" # CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_FHANDLE is not set CONFIG_AUDIT=y # CONFIG_AUDITSYSCALL is not set CONFIG_NO_HZ=y @@ -317,6 +318,7 @@ CONFIG_INPUT_UINPUT=y # CONFIG_SERIO_SERPORT is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y @@ -649,6 +651,7 @@ CONFIG_HARDENED_USERCOPY=y CONFIG_FORTIFY_SOURCE=y CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 8887eb0bd077..ef78baffd836 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -1,4 +1,5 @@ # CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_FHANDLE is not set CONFIG_AUDIT=y # CONFIG_AUDITSYSCALL is not set CONFIG_NO_HZ=y @@ -329,6 +330,7 @@ CONFIG_INPUT_UINPUT=y # CONFIG_SERIO_SERPORT is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y CONFIG_SERIAL_MSM_GENI_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y @@ -734,6 +736,7 @@ CONFIG_HARDENED_USERCOPY_PAGESPAN=y CONFIG_FORTIFY_SOURCE=y CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y -- GitLab From bf0ceb012bc33fc80d1f14aa0150948721fb26f6 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 11 Jan 2019 16:27:43 +0530 Subject: [PATCH 1144/1286] clk: qcom: Support for 650MHz for GPU clock for SM6150 GFX3D clock requires to support 650MHz on SM6150, so add support for the same. Change-Id: I40f684698d647b1c36c39b4882fecff5a7d8c5b5 Signed-off-by: Odelu Kukatla --- drivers/clk/qcom/gpucc-sm6150.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sm6150.c b/drivers/clk/qcom/gpucc-sm6150.c index f56e68620ffe..c6b0d0f62add 100644 --- a/drivers/clk/qcom/gpucc-sm6150.c +++ b/drivers/clk/qcom/gpucc-sm6150.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -217,8 +217,11 @@ static struct clk_fixed_factor crc_div_pll1_out_aux2 = { static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { F(290000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), + F(350000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), F(435000000, P_CRC_DIV_PLL1_OUT_AUX2, 1, 0, 0), + F(500000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), F(550000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), + F(650000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), F(700000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), F(745000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), F(845000000, P_CRC_DIV_PLL0_OUT_AUX2, 1, 0, 0), -- GitLab From 978810e14634f6e51670c4d399e1ba92a3f325a7 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 11 Jan 2019 15:59:31 +0530 Subject: [PATCH 1145/1286] clk: qcom: Support for 980MHz for GPU clock for TRINKET GFX3D clock requires to support 980MHz on TRINKET, so add support for the same. Change-Id: I5e43d09d72d0febd225b311bf91bcf86b89d1c86 Signed-off-by: Odelu Kukatla --- drivers/clk/qcom/gpucc-trinket.c | 5 ++++- drivers/clk/qcom/vdd-level-trinket.h | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-trinket.c b/drivers/clk/qcom/gpucc-trinket.c index ba20a7aab732..831724735024 100644 --- a/drivers/clk/qcom/gpucc-trinket.c +++ b/drivers/clk/qcom/gpucc-trinket.c @@ -194,6 +194,8 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), { } }; @@ -218,7 +220,8 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { [VDD_LOW_L1] = 600000000, [VDD_NOMINAL] = 745000000, [VDD_NOMINAL_L1] = 820000000, - [VDD_HIGH] = 900000000}, + [VDD_HIGH] = 900000000, + [VDD_HIGH_L1] = 980000000}, }, }; diff --git a/drivers/clk/qcom/vdd-level-trinket.h b/drivers/clk/qcom/vdd-level-trinket.h index f4a28f64a3be..b6a9e6861c0a 100644 --- a/drivers/clk/qcom/vdd-level-trinket.h +++ b/drivers/clk/qcom/vdd-level-trinket.h @@ -25,6 +25,7 @@ enum vdd_mx_levels { VDD_MX_LOW_L1, /* SVSL1 */ VDD_MX_NOMINAL, /* NOM */ VDD_MX_HIGH, /* TURBO */ + VDD_MX_HIGH_L1, /* TURBO_L1 */ VDD_MX_NUM, }; @@ -36,6 +37,7 @@ static int vdd_mx_corner[] = { RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_LOW_L1 */ RPM_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ RPM_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ + RPM_REGULATOR_LEVEL_TURBO_NO_CPR, /* VDD_HIGH_L1 */ RPM_REGULATOR_LEVEL_MAX }; @@ -48,6 +50,7 @@ enum vdd_dig_levels { VDD_NOMINAL, /* NOM */ VDD_NOMINAL_L1, /* NOM */ VDD_HIGH, /* TURBO */ + VDD_HIGH_L1, /* TURBO_L1 */ VDD_NUM, }; @@ -60,6 +63,7 @@ static int vdd_corner[] = { RPM_REGULATOR_LEVEL_NOM, /* VDD_NOMINAL */ RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_NOMINAL */ RPM_REGULATOR_LEVEL_TURBO, /* VDD_HIGH */ + RPM_REGULATOR_LEVEL_TURBO_NO_CPR, /* VDD_HIGH_L1 */ RPM_REGULATOR_LEVEL_MAX }; -- GitLab From 9fa8d7d7971cd817c205c29d0a0ae50601f4e4e3 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Mon, 28 Jan 2019 16:08:40 +0530 Subject: [PATCH 1146/1286] ARM: dts: msm: enable display in command mode on TRINKET Add support to enable display in command mode for below platforms with TRINKET SoC: 1. Trinket IDP with External Audio codec. 2. Trinket IDP with External Audio Codec over USB type C. 3. Trinket IDP with Audio over USB type C. Change-Id: I7c1b94fe40f1fe46b22f8c0ea44227f705352a87 Signed-off-by: Tharun Raj Soma --- .../arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts | 3 +++ .../boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts | 3 +++ arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts index 2a366244cfcc..ce50ac46f1b9 100644 --- a/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-external-codec-idp-overlay.dts @@ -26,3 +26,6 @@ qcom,board-id = <34 1>; }; +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts index f69f9ba4dbac..5f83b48f630f 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts @@ -24,3 +24,6 @@ qcom,board-id = <34 3>; }; +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts index 6fc501c8e333..d51449703035 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp-overlay.dts @@ -24,3 +24,6 @@ qcom,board-id = <34 2>; }; +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; -- GitLab From a5fab6331a93cf45a969261286416fa4240f7908 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Mon, 28 Jan 2019 16:42:24 +0530 Subject: [PATCH 1147/1286] ARM: dts: msm: Fix typo for vls_clamp_reg on Trinket The vls_clamp_reg is needed to needed to clamp the SS PHY lines for autonomous mode. Fix the typo so that the driver can parse the register base and clamp the PHY accordingly. Change-Id: If3bee04bac95606b2fc4467175cc107a50691cde Signed-off-by: Sriharsha Allenki --- arch/arm64/boot/dts/qcom/trinket-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index 7f0848ebb405..f543d9c9a78b 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -175,7 +175,7 @@ reg = <0x01615000 0x1000>, <0x03cb244 0x4>; reg-names = "qmp_phy_base", - "vls_clamp-reg"; + "vls_clamp_reg"; vdd-supply = <&pm6125_l7>; core-supply = <&pm6125_l10>; -- GitLab From 0239d800a595c9910cb542329b2bddbc0f26719f Mon Sep 17 00:00:00 2001 From: Avaneesh Kumar Dwivedi Date: Fri, 11 Jan 2019 15:19:16 +0530 Subject: [PATCH 1148/1286] ARM: dts: msm: V4 memory map changes for qcs405 Aligning NHLOS side memory map as per latest v4 memory map. Change-Id: I68e468704b5b727bcb6a7bdd090e297425770521 Signed-off-by: Avaneesh Kumar Dwivedi --- arch/arm64/boot/dts/qcom/qcs405.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi index e5cf516bb369..db92cc079646 100644 --- a/arch/arm64/boot/dts/qcom/qcs405.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405.dtsi @@ -59,25 +59,25 @@ wlan_fw_mem: wlan_fw_mem@86400000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x86400000 0x0 0x1100000>; + reg = <0x0 0x86400000 0x0 0xf00000>; }; adsp_fw_mem: adsp_fw_mem@87500000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x87500000 0x0 0x1a00000>; + reg = <0x0 0x87300000 0x0 0x1a00000>; }; cdsp_fw_mem: cdsp_fw_mem@88f00000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x88f00000 0x0 0x600000>; + reg = <0x0 0x88d00000 0x0 0x600000>; }; wlan_msa_mem: wlan_msa_region@89500000 { compatible = "removed-dma-pool"; no-map; - reg = <0x0 0x89500000 0x0 0x100000>; + reg = <0x0 0x89300000 0x0 0x100000>; }; secure_mem: secure_region { -- GitLab From 5c17ff7325246f55d88fcc8e13c99b95c9d711b3 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 28 Jan 2019 18:31:22 +0530 Subject: [PATCH 1149/1286] ARM: dts: msm: Update default lmh dcvsh thermal thresholds for SA6155 Update default lmh dcvsh thermal thresholds based on latest recommendation for both SA6155 and SA6155P. Change-Id: I6c68339b356635ba4566c81edb5778cb3af1b407 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/sa6155.dtsi | 22 +++++++++++++++++++++- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 20 ++++++++++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155.dtsi b/arch/arm64/boot/dts/qcom/sa6155.dtsi index 73ca4eb69ecb..26c4af032b22 100644 --- a/arch/arm64/boot/dts/qcom/sa6155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -307,3 +307,23 @@ qcom,smmu-s1-enable; }; }; + +&thermal_zones { + lmh-dcvs-00 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + lmh-dcvs-01 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 3ce74a06c637..1cb656a98674 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -339,6 +339,26 @@ vdd_mx-supply = <&VDD_CX_LEVEL>; }; +&thermal_zones { + lmh-dcvs-00 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + lmh-dcvs-01 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; +}; + /* Audio device tree */ #include "sa6155-audio.dtsi" #include "sa6155-pcie.dtsi" -- GitLab From 7d0a1bded638fb85675b58e3e49a90ea8d4ec7db Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Fri, 14 Dec 2018 15:13:18 +0530 Subject: [PATCH 1150/1286] clk: qcom: debugcc-sdxprairie: Add CPU clock measure for sdxprairie Add CPU debug mux with inputs for measuring the CPU clocks on sdxprairie. Change-Id: I9ed7eb6f1923392c934f5502c1616b61214481aa Signed-off-by: Naveen Yadav --- drivers/clk/qcom/debugcc-sdxprairie.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/debugcc-sdxprairie.c b/drivers/clk/qcom/debugcc-sdxprairie.c index bcf993264bdf..0c7c77eb2f15 100644 --- a/drivers/clk/qcom/debugcc-sdxprairie.c +++ b/drivers/clk/qcom/debugcc-sdxprairie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -91,6 +91,7 @@ static const char *const debug_mux_parent_names[] = { "measure_only_bimc_clk", "measure_only_ipa_2x_clk", "measure_only_snoc_clk", + "apcs_mux_clk", }; static struct clk_debug_mux gcc_debug_mux = { @@ -219,6 +220,8 @@ static struct clk_debug_mux gcc_debug_mux = { 0xAC, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 }, { "measure_only_snoc_clk", 0x109, 4, GCC, 0x109, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 }, + { "apcs_mux_clk", 0x7C, 4, CPU_CC, + 0x3, 0x7, 0x3, 0x0, 0, 1, 0, 0, U32_MAX, 1 }, ), .hw.init = &(struct clk_init_data){ .name = "gcc_debug_mux", @@ -273,6 +276,10 @@ static int clk_debug_sdxprairie_probe(struct platform_device *pdev) if (ret) return ret; + ret = map_debug_bases(pdev, "qcom,cpucc", CPU_CC); + if (ret) + return ret; + clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); -- GitLab From d3b4d5b5f9288bc0579f20fc84b838b9dcf1a59d Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Fri, 14 Dec 2018 15:26:02 +0530 Subject: [PATCH 1151/1286] ARM: dts: msm: Add cpu clock debug node for sdxprairie Add cpu clock debug node and clock measure support for sdxprairie. Change-Id: I95de38dd25b6709b5fc81a01403671fa3f551ce2 Signed-off-by: Naveen Yadav --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index e306ea838849..caf340c8b96e 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -322,8 +322,9 @@ clock_debugcc: qcom,cc-debug { compatible = "qcom,debugcc-sdxprairie"; - qcom,cc-count = <1>; + qcom,cc-count = <2>; qcom,gcc = <&clock_gcc>; + qcom,cpucc = <&cpucc_debug>; clock-names = "xo_clk_src"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; @@ -348,6 +349,11 @@ #clock-cells = <1>; }; + cpucc_debug: syscon@1781101c { + compatible = "syscon"; + reg = <0x1781101c 0x4>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, -- GitLab From 6b69141156429ab67dbd4b907cc3c0104a935ba9 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Sun, 20 Jan 2019 17:02:34 +0530 Subject: [PATCH 1152/1286] ARM: dts: msm: Add xo_board clock node for TRINKET Add xo_board fixed clock node as it is the parent for XO clock. Change-Id: Ie597728015066f3a65b1a4faea1e8621d2cf86dc Signed-off-by: Odelu Kukatla --- arch/arm64/boot/dts/qcom/trinket.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 20e8d7e0cba3..c87c8718db32 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -764,6 +764,13 @@ clock-output-names = "chip_sleep_clk"; #clock-cells = <1>; }; + + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; }; clock_rpmcc: qcom,rpmcc { -- GitLab From 1eb4898e22b022bcb504be3e0b1f15024638f7d5 Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Wed, 23 Jan 2019 23:36:31 +0530 Subject: [PATCH 1153/1286] ARM: dts: msm: Bringup changes for tasha codec on trinket Update cpe nodes, wsa device nodes, clocks and gpio configuration to support audio on tasha codec for trinket target. Change-Id: I266d28a97b0dd1ea044d7b38bdda722b4693326e Signed-off-by: Aditya Bavanari --- .../boot/dts/qcom/trinket-audio-overlay.dtsi | 13 ++++-- arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 8 ++-- .../trinket-tasha-codec-audio-overlay.dtsi | 40 +++++++++++++++++++ .../boot/dts/qcom/trinket-tasha-codec.dtsi | 30 ++++++++++---- 4 files changed, 75 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi index da5753a4ca12..69839502fa9d 100644 --- a/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -351,7 +351,7 @@ interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&tlmm>; - qcom,gpio-connect = <&tlmm 118 0>; + qcom,gpio-connect = <&tlmm 110 0>; pinctrl-names = "default"; pinctrl-0 = <&wcd_intr_default>; }; @@ -368,6 +368,8 @@ status = "disabled"; compatible = "qcom,audio-ref-clk"; #clock-cells = <1>; + qcom,codec-ext-clk-src = ; + clock-names = "osr_clk"; qcom,lpass-mclk-id = <0x116>; qcom,codec-mclk-clk-freq = <11289600>; qcom,audio-ref-clk-gpio = <&tlmm 112 0>; @@ -379,12 +381,15 @@ clock_audio: audio_ext_clk { status = "disabled"; compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <0>; + qcom,use-pinctrl = <1>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&tasha_mclk_default>; pinctrl-1 = <&tasha_mclk_default>; qcom,audio-ref-clk-gpio = <&pm6125_gpios 1 0>; clock-names = "osr_clk"; clocks = <&pm6125_clkdiv>; + pmic-clock-names = "pm6125_div_clk1"; qcom,node_has_rpm_clock; #clock-cells = <1>; }; @@ -411,8 +416,8 @@ qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; clock-names = "wcd_clk", "wcd_native_clk"; - clocks = <&clock_audio AUDIO_PMI_CLK>, - <&clock_audio_native AUDIO_LPASS_MCLK_1>; + clocks = <&clock_audio 0>, + <&clock_audio_native 0>; qcom,cdc-micbias1-mv = <1800>; qcom,cdc-micbias2-mv = <1800>; @@ -443,7 +448,7 @@ "cdc-buck-sido", "cdc-vdd-tx-h", "cdc-vdd-rx-h", - "cdc-vddpx-1"; + "cdc-vddio-1"; qcom,cdc-mclk-clk-rate = <9600000>; qcom,cdc-slim-ifd = "tasha-slim-ifd"; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index a694c85691d1..1992e0001fb0 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -715,12 +715,12 @@ wcd9xxx_intr { wcd_intr_default: wcd_intr_default{ mux { - pins = "gpio118"; + pins = "gpio110"; function = "gpio"; }; config { - pins = "gpio118"; + pins = "gpio110"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* pull down */ input-enable; @@ -818,7 +818,7 @@ audio_ref_clk_active: audio_ref_clk_active { mux { pins = "gpio112"; - function = "func2"; + function = "gpio"; }; config { @@ -832,7 +832,7 @@ audio_ref_clk_sleep: audio_ref_clk_sleep { mux { pins = "gpio112"; - function = "func2"; + function = "gpio"; }; config { diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi index 8e85ba88f1b1..e0a4420cf8e9 100644 --- a/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi @@ -19,6 +19,10 @@ status = "disabled"; }; +&wcd937x_rst_gpio{ + status = "disabled"; +}; + &cdc_dmic01_gpios { status = "disabled"; }; @@ -27,6 +31,42 @@ status = "disabled"; }; +&clock_audio_wsa_1 { + status = "disabled"; +}; + +&clock_audio_wsa_2 { + status = "disabled"; +}; + +&clock_audio_va { + status = "disabled"; +}; + +&clock_audio_rx_1 { + status = "disabled"; +}; + +&clock_audio_rx_2 { + status = "disabled"; +}; + +&clock_audio_tx_1 { + status = "disabled"; +}; + +&clock_audio_tx_2 { + status = "disabled"; +}; + +&wsa_spkr_en1 { + status = "disabled"; +}; + +&rx_swr_gpios { + status = "disabled"; +}; + &slim_aud { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi index 73f3c2ee6ce5..d8aaf77293f4 100644 --- a/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-tasha-codec.dtsi @@ -13,20 +13,32 @@ #include #include "trinket-wcd.dtsi" +&soc { + cpe: qcom,msm-cpe-lsm { + compatible = "qcom,msm-cpe-lsm"; + }; + + cpe3: qcom,msm-cpe-lsm@3 { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <3>; + }; +}; + &sm6150_snd { qcom,model = "trinket-tashalite-snd-card"; qcom,tasha_codec = <1>; asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, <&loopback>, <&compress>, <&hostless>, <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; + <&pcm_noirq>, <&cpe>, <&cpe3>; asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", - "msm-compr-dsp", "msm-pcm-dsp-noirq"; + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-cpe-lsm", "msm-cpe-lsm.3"; asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, @@ -108,10 +120,12 @@ asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_00211>, <&wsa881x_00212>, - <&wsa881x_00213>, <&wsa881x_00214>; + qcom,wsa-devs = <&wsa881x_70211>, <&wsa881x_70212>, + <&wsa881x_70213>, <&wsa881x_70214>; qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&wcd9335>, + <&q6core>; }; &slim_aud { @@ -127,25 +141,25 @@ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, <8 SPKR_R_VI 0x3>; qcom,swr_master_id = <1>; - wsa881x_00211: wsa881x@20170211 { + wsa881x_70211: wsa881x@70211 { compatible = "qcom,wsa881x"; reg = <0x00 0x20170211>; qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; }; - wsa881x_00212: wsa881x@20170212 { + wsa881x_70212: wsa881x@70212 { compatible = "qcom,wsa881x"; reg = <0x00 0x20170212>; qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; }; - wsa881x_00213: wsa881x@21170213 { + wsa881x_70213: wsa881x@70213 { compatible = "qcom,wsa881x"; reg = <0x00 0x21170213>; qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; }; - wsa881x_00214: wsa881x@21170214 { + wsa881x_70214: wsa881x@70214 { compatible = "qcom,wsa881x"; reg = <0x00 0x21170214>; qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; -- GitLab From 9ebfb8d16592596f854d3fc4d068de231c725262 Mon Sep 17 00:00:00 2001 From: Sean Tranchetti Date: Wed, 23 Jan 2019 17:41:34 -0700 Subject: [PATCH 1154/1286] soc: qcom: wda: Additional cleanup logic Perform cleanup of WDA and DFC structures when all rmnet VNDs are removed. This is needed in case IPA notifier callback is not invoked in for example shutdown process. Also protect the rmnet check stats function with RCU lock. Change-Id: I88f0fb7efb73465b467ef37f5dd15a389ee50d1c Acked-by: Weiyi Chen Signed-off-by: Sean Tranchetti --- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c index 7eee43d5fb75..596a365cf3ee 100644 --- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c +++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -224,6 +224,10 @@ static void rmnet_dellink(struct net_device *dev, struct list_head *head) synchronize_rcu(); kfree(ep); } + + if (!port->nr_rmnet_devs) + qmi_rmnet_qmi_exit(port->qmi_info, port); + rmnet_unregister_real_device(real_dev, port); unregister_netdevice_queue(dev, head); @@ -557,6 +561,7 @@ void rmnet_get_packets(void *port, u64 *rx, u64 *tx) *tx = 0; *rx = 0; + rcu_read_lock(); hash_for_each(((struct rmnet_port *)port)->muxed_ep, bkt, ep, hlnode) { priv = netdev_priv(ep->egress_dev); for_each_possible_cpu(cpu) { @@ -568,6 +573,7 @@ void rmnet_get_packets(void *port, u64 *rx, u64 *tx) } while (u64_stats_fetch_retry_irq(&ps->syncp, start)); } } + rcu_read_unlock(); } EXPORT_SYMBOL(rmnet_get_packets); -- GitLab From be732c5445d3b3c65b83956dd750cd8a7e75ac86 Mon Sep 17 00:00:00 2001 From: cpratapa Date: Mon, 28 Jan 2019 22:53:41 +0530 Subject: [PATCH 1155/1286] ARM: dts: msm: fix to disable ipa node for sa6155p IPA is not required on SA platforms. Make a change to disable IPA node properly. Change-Id: Ia0edd64964be4008ca1b6c198ebc0b74e8976143 Signed-off-by: Chaitanya Pratapa --- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index f0e82644c5ac..46c7bf760c9e 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -23,14 +23,6 @@ aliases { pci-domain0 = &pcie0; /* PCIe0 domain */ }; - - qcom,rmnet-ipa { - status="disabled"; - }; -}; - -&ipa_hw { - status="disabled"; }; /* Delete second instance of pm6155 definitions for APQ version */ @@ -93,6 +85,14 @@ /* Upto 800 Mbps */ <45 512 207108 1146880>, <1 512 207108 3124992>; }; + + qcom,rmnet-ipa { + status="disabled"; + }; +}; + +&ipa_hw { + status="disabled"; }; &pil_modem { -- GitLab From 700899baebfa3083038f1ec55505601c762258a3 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Wed, 9 Jan 2019 10:38:37 -0800 Subject: [PATCH 1156/1286] msm: kgsl: Adjust RBBM_HANG_INT_CNTL register value to increase cycle count GPU may sometimes falsely report a hang interrupt in case of long running payloads. Increase the number of cycles for fault detection to avoid false interrupts from the GPU. Change-Id: I7783e16948cf0af1ac3cad96b2f0149c74dc8723 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor --- drivers/gpu/msm/adreno_a6xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 9eb144438733..b2ea857a4b22 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -918,9 +918,9 @@ static void a6xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (glbl_inv << 29) | (mal << 23) | (bit << 21)); - /* Set hang detection threshold to 0x3FFFFF * 16 cycles */ + /* Set hang detection threshold to 0xCFFFFF * 16 cycles */ kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x3fffff); + (1 << 30) | 0xcfffff); kgsl_regwrite(device, A6XX_UCHE_CLIENT_PF, 1); -- GitLab From abd4df7b818cbc432c244f919f8d4bde1d93a0cf Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 26 Dec 2018 18:46:01 -0800 Subject: [PATCH 1157/1286] mhi: core: clear BHIE RX vector registers during init Power on reset values for BHIE RX vector registers are undefined, manually clear it during init. CRs-Fixed: 2373857 Change-Id: Iae386ba90cd4743e87fef8a5496d0e48d3e31a0c Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_init.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_init.c b/drivers/bus/mhi/core/mhi_init.c index daa28ceb2fef..105987f3766c 100644 --- a/drivers/bus/mhi/core/mhi_init.c +++ b/drivers/bus/mhi/core/mhi_init.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1247,6 +1247,7 @@ EXPORT_SYMBOL(mhi_alloc_controller); int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) { int ret; + u32 bhie_off; mutex_lock(&mhi_cntrl->pm_mutex); @@ -1266,16 +1267,39 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) * allocate rddm table if specified, this table is for debug purpose * so we'll ignore erros */ - if (mhi_cntrl->rddm_size) + if (mhi_cntrl->rddm_size) { mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, mhi_cntrl->rddm_size); + /* + * This controller supports rddm, we need to manually clear + * BHIE RX registers since por values are undefined. + */ + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, + &bhie_off); + if (ret) { + MHI_ERR("Error getting bhie offset\n"); + goto bhie_error; + } + + memset_io(mhi_cntrl->regs + bhie_off + BHIE_RXVECADDR_LOW_OFFS, + 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS + + 4); + } + mhi_cntrl->pre_init = true; mutex_unlock(&mhi_cntrl->pm_mutex); return 0; +bhie_error: + if (mhi_cntrl->rddm_image) { + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); + mhi_cntrl->rddm_image = NULL; + } + mhi_deinit_free_irq(mhi_cntrl); + error_setup_irq: mhi_deinit_dev_ctxt(mhi_cntrl); -- GitLab From 057520c0ed9de75f022d4d50ed95a2b4cfd24084 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Fri, 25 Jan 2019 15:41:06 -0800 Subject: [PATCH 1158/1286] ARM: dts: msm: Add modem qrtr node for sm8150-sdxprairie For certain usecases the internal modem will be brought out of reset. Set the net id to 2 so the packets coming from the internal modem are not forwarded to other Q6 or SDX. Change-Id: I439f42128bced10001197182fd58a695c782a4b9 Signed-off-by: Chris Lew --- arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index ac243fba7bef..ccefd93c160e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -100,6 +100,12 @@ }; }; +&glink_modem { + qcom,modem_qrtr { + qcom,net-id = <2>; + }; +}; + &soc { ipa_hw: qcom,ipa@1e00000 { qcom,platform-type = <2>; /* APQ platform */ -- GitLab From e8afc059f8d64db62cb4118dc13e91eadfd2cc5a Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 26 Dec 2018 19:19:04 -0800 Subject: [PATCH 1159/1286] mhi: core: force a hardware reset if device failed to enter rddm If device fail to enter ramdump mode (rddm) gracefully, trigger a hardware reset to force rddm mode. CRs-Fixed: 2373857 Change-Id: If1fd02ff6da882df6b2db858b410d76ac8b0f1a8 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_boot.c | 26 ++++++++++++++++++++++++-- drivers/bus/mhi/core/mhi_internal.h | 4 ++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_boot.c b/drivers/bus/mhi/core/mhi_boot.c index 8fa1d037c3df..d49884fe8c95 100644 --- a/drivers/bus/mhi/core/mhi_boot.c +++ b/drivers/bus/mhi/core/mhi_boot.c @@ -52,8 +52,10 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) u32 rx_status; enum mhi_ee ee; struct image_info *rddm_image = mhi_cntrl->rddm_image; - const u32 delayus = 100; + const u32 delayus = 2000; u32 retry = (mhi_cntrl->timeout_ms * 1000) / delayus; + const u32 rddm_timeout_us = 200000; + int rddm_retry = rddm_timeout_us / delayus; /* time to enter rddm */ void __iomem *base = mhi_cntrl->bhie; MHI_LOG("Entered with pm_state:%s dev_state:%s ee:%s\n", @@ -107,7 +109,27 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) MHI_LOG("Trigger device into RDDM mode\n"); mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR); - MHI_LOG("Waiting for image download completion\n"); + MHI_LOG("Waiting for device to enter RDDM\n"); + while (rddm_retry--) { + ee = mhi_get_exec_env(mhi_cntrl); + if (ee == MHI_EE_RDDM) + break; + + udelay(delayus); + } + + if (rddm_retry <= 0) { + /* This is a hardware reset, will force device to enter rddm */ + MHI_LOG( + "Did not enter RDDM triggering host req. reset to force rddm\n"); + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, + MHI_SOC_RESET_REQ_OFFSET, MHI_SOC_RESET_REQ); + udelay(delayus); + } + + ee = mhi_get_exec_env(mhi_cntrl); + MHI_LOG("Waiting for image download completion, current EE:%s\n", + TO_MHI_EXEC_STR(ee)); while (retry--) { ret = mhi_read_reg_field(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS, BHIE_RXVECSTATUS_STATUS_BMSK, diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index 8fac51e20928..03c1f9684731 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -134,6 +134,10 @@ extern struct bus_type mhi_bus_type; #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_MASK (0xFFFFFFFF) #define MHIDATALIMIT_HIGHER_MHIDATALIMIT_HIGHER_SHIFT (0) +/* Host request register */ +#define MHI_SOC_RESET_REQ_OFFSET (0xB0) +#define MHI_SOC_RESET_REQ BIT(0) + /* MHI misc capability registers */ #define MISC_OFFSET (0x24) #define MISC_CAP_MASK (0xFFFFFFFF) -- GitLab From a38b4cd8ae90569ec8b0649ec2877b20b31c4783 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 26 Dec 2018 19:34:54 -0800 Subject: [PATCH 1160/1286] mhi: core: always try forcing device into rddm when bus master requests Let bus master determine the link states. Whenever bus master request device to enter rddm always try enter rddm regardless of current software state. CRs-Fixed: 2373857 Change-Id: I9e5a993f3e7311c4367b7fd82385d4f0dcacc932 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_boot.c | 10 ++-------- drivers/bus/mhi/core/mhi_pm.c | 21 --------------------- 2 files changed, 2 insertions(+), 29 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_boot.c b/drivers/bus/mhi/core/mhi_boot.c index d49884fe8c95..291c41b2dca2 100644 --- a/drivers/bus/mhi/core/mhi_boot.c +++ b/drivers/bus/mhi/core/mhi_boot.c @@ -69,14 +69,8 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) * returning from this function, we expect device to reset. * * Normaly, we would read/write pm_state only after grabbing - * pm_lock, since we're in a panic, skipping it. - */ - - if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) - return -EIO; - - /* - * There is no gurantee this state change would take effect since + * pm_lock, since we're in a panic, skipping it. Also there is no + * gurantee this state change would take effect since * we're setting it w/o grabbing pmlock, it's best effort */ mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT; diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index cedb4b10d0b9..a8a7605ce5e4 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -1133,22 +1133,8 @@ int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl) to_mhi_pm_state_str(mhi_cntrl->pm_state), TO_MHI_EXEC_STR(mhi_cntrl->ee)); - /* before rddm mode, we need to enter M0 state */ - ret = __mhi_device_get_sync(mhi_cntrl); - if (ret) - return ret; - - mutex_lock(&mhi_cntrl->pm_mutex); - write_lock_irq(&mhi_cntrl->pm_lock); - if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) - goto no_reg_access; - MHI_LOG("Triggering SYS_ERR to force rddm state\n"); - mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR); - mhi_cntrl->wake_put(mhi_cntrl, false); - write_unlock_irq(&mhi_cntrl->pm_lock); - mutex_unlock(&mhi_cntrl->pm_mutex); /* wait for rddm event */ MHI_LOG("Waiting for device to enter RDDM state\n"); @@ -1162,12 +1148,5 @@ int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl) TO_MHI_EXEC_STR(mhi_cntrl->ee), ret); return ret; - -no_reg_access: - mhi_cntrl->wake_put(mhi_cntrl, false); - write_unlock_irq(&mhi_cntrl->pm_lock); - mutex_unlock(&mhi_cntrl->pm_mutex); - - return -EIO; } EXPORT_SYMBOL(mhi_force_rddm_mode); -- GitLab From c5a148b069b5d5274ceaa931cab8c793108801c8 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Wed, 26 Dec 2018 20:32:36 -0800 Subject: [PATCH 1161/1286] mhi: core: add support for handling MHI SYS ERROR state in low power mode It's possible for device to enter error state immediately after entering low power mode. This change add supports for it by forcing a sys error check during a fail resume. CRs-Fixed: 2373857 Change-Id: I7fcf1804dcc147397e0ff4e0e3f59749396a90e2 Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_main.c | 13 ++++++++++--- drivers/bus/mhi/core/mhi_pm.c | 6 ++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/bus/mhi/core/mhi_main.c b/drivers/bus/mhi/core/mhi_main.c index 7d52c748c22f..9762a79c0b4f 100644 --- a/drivers/bus/mhi/core/mhi_main.c +++ b/drivers/bus/mhi/core/mhi_main.c @@ -1389,12 +1389,20 @@ void mhi_ctrl_ev_task(unsigned long data) { struct mhi_event *mhi_event = (struct mhi_event *)data; struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; - enum mhi_dev_state state = MHI_STATE_MAX; + enum mhi_dev_state state; enum MHI_PM_STATE pm_state = 0; int ret; MHI_VERB("Enter for ev_index:%d\n", mhi_event->er_index); + /* + * we can check pm_state w/o a lock here because there is no way + * pm_state can change from reg access valid to no access while this + * therad being executed. + */ + if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + return; + /* process ctrl events events */ ret = mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); @@ -1404,8 +1412,7 @@ void mhi_ctrl_ev_task(unsigned long data) */ if (!ret) { write_lock_irq(&mhi_cntrl->pm_lock); - if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) - state = mhi_get_mhi_state(mhi_cntrl); + state = mhi_get_mhi_state(mhi_cntrl); if (state == MHI_STATE_SYS_ERR) { MHI_ERR("MHI system error detected\n"); pm_state = mhi_tryset_pm_state(mhi_cntrl, diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index a8a7605ce5e4..57e54c3d65c5 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -1054,6 +1054,12 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl) MHI_ERR("Did not enter M0 state, cur_state:%s pm_state:%s\n", TO_MHI_STATE_STR(mhi_cntrl->dev_state), to_mhi_pm_state_str(mhi_cntrl->pm_state)); + + /* + * It's possible device already in error state and we didn't + * process it due to low power mode, force a check + */ + mhi_intvec_threaded_handlr(0, mhi_cntrl); return -EIO; } -- GitLab From dd595272be74ddd14959665057cab0084a442a1f Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Thu, 27 Dec 2018 17:04:55 -0800 Subject: [PATCH 1162/1286] mhi: core: log device EE and device state inside intvec handler For debugging purpose, always print the current execution environment and device state whenever intvec handler is triggered. CRs-Fixed: 2373857 Change-Id: Idf961573dbcd12c0797f94095a828dd5c675c6ef Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/bus/mhi/core/mhi_main.c b/drivers/bus/mhi/core/mhi_main.c index 9762a79c0b4f..e1814923c260 100644 --- a/drivers/bus/mhi/core/mhi_main.c +++ b/drivers/bus/mhi/core/mhi_main.c @@ -1464,6 +1464,8 @@ irqreturn_t mhi_intvec_threaded_handlr(int irq_number, void *dev) if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { state = mhi_get_mhi_state(mhi_cntrl); ee = mhi_get_exec_env(mhi_cntrl); + MHI_LOG("device ee:%s dev_state:%s\n", TO_MHI_EXEC_STR(ee), + TO_MHI_STATE_STR(state)); } if (state == MHI_STATE_SYS_ERR) { -- GitLab From 5d5c991894e39783ab3cdeb3704c06d85bdf9ab5 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Mon, 21 Jan 2019 15:56:30 -0800 Subject: [PATCH 1163/1286] ARM: dts: msm: Add glink pkt channels for sdxprairie Add sdx specific smd channels for the glinkpkt driver. These nodes expose dev nodes that can be used to communicate to the modem through rpmsg glink. Change-Id: I750659d7a91eec52320c1eefa58cb4ee61f58eb9 Signed-off-by: Chris Lew --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 58257bf6d38f..8d5f502fac1f 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -654,6 +654,18 @@ qcom,glinkpkt-dev-name = "at_mdm0"; }; + qcom,glinkpkt-data5-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA5_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl0"; + }; + + qcom,glinkpkt-data6-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA6_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl1"; + }; + qcom,glinkpkt-data40-cntl { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA40_CNTL"; @@ -677,6 +689,18 @@ qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; + + qcom,glinkpkt-data21 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA21"; + qcom,glinkpkt-dev-name = "smd21"; + }; + + qcom,glinkpkt-data22 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA22"; + qcom,glinkpkt-dev-name = "smd22"; + }; }; qmp_aop: qcom,qmp-aop@c300000 { -- GitLab From 90723d93d4f1f4d09a68783a96c9829b9ab2a8c9 Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Samavedam Date: Mon, 28 Jan 2019 16:30:14 -0800 Subject: [PATCH 1164/1286] usb: f_gsi: Do not override config item name Rndis gsi driver updates the config item type and in the process also overrides config item name as empty string. This can cause confusion as symlined config item appears as empty file name. Change-Id: Ic05e50d753a79ca9aa08f393b6bab0a5789cd03a Signed-off-by: Vamsi Krishna Samavedam --- drivers/usb/gadget/function/f_gsi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 2a0f5fb81a57..a55c0c7a59b7 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -3669,8 +3669,9 @@ static int gsi_set_inst_name(struct usb_function_instance *fi, } if (prot_id == USB_PROT_RNDIS_IPA) - config_group_init_type_name(&opts->func_inst.group, "", - &gsi_func_rndis_type); + config_group_init_type_name(&opts->func_inst.group, + fi->group.cg_item.ci_name, + &gsi_func_rndis_type); gsi = opts->gsi = __gsi[prot_id]; opts->gsi->prot_id = prot_id; -- GitLab From 63f03c109a4b4cb05afca11734c5b38bf2af7272 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Thu, 17 Jan 2019 15:09:51 +0800 Subject: [PATCH 1165/1286] scsi: ufs: tune host unipro attribute PA_PEERRXHSADAPTINITIAL During power mode change, UFS host Unipro attribute PA_PEERRXHSADAPTINITIAL should be set to the value of M-PHY attribute RX_HS_ADAPT_INITIAL_CAPABILITY read from its peer UFS device. Change-Id: I67f196babe584254add7f4805c7568dd0443904e Signed-off-by: Can Guo --- drivers/scsi/ufs/ufshcd.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index cab3c29f3971..15533880402b 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -5446,6 +5446,7 @@ int ufshcd_change_power_mode(struct ufs_hba *hba, struct ufs_pa_layer_attr *pwr_mode) { int ret = 0; + u32 peer_rx_hs_adapt_initial_cap; /* if already configured to the requested pwr_mode */ if (!hba->restore_needed && @@ -5496,8 +5497,19 @@ int ufshcd_change_power_mode(struct ufs_hba *hba, pwr_mode->hs_rate); if (pwr_mode->gear_tx == UFS_HS_G4) { + ret = ufshcd_dme_peer_get(hba, + UIC_ARG_MIB_SEL(RX_HS_ADAPT_INITIAL_CAPABILITY, + UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), + &peer_rx_hs_adapt_initial_cap); + if (ret) { + dev_err(hba->dev, + "%s: RX_HS_ADAPT_INITIAL_CAP get failed %d\n", + __func__, ret); + peer_rx_hs_adapt_initial_cap = + PA_PEERRXHSADAPTINITIAL_Default; + } ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSADAPTINITIAL), - PA_PEERRXHSADAPTINITIAL_Default); + peer_rx_hs_adapt_initial_cap); /* INITIAL ADAPT */ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_INITIAL_ADAPT); -- GitLab From ee4ba7353db2e6e2fdd9d707324795838c6b1c8b Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Mon, 28 Jan 2019 17:47:36 +0530 Subject: [PATCH 1166/1286] ARM: dts: msm: fix supported DFPS range for rm69298 truly panel Fix supported DFPS range for rm69298 truly panel on sdmmagpie target. Change-Id: I62fc14584a3a951a4cc58e95ad13f467d0cbccc3 Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index 64e336c0a689..f5095ee9440d 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -507,7 +507,7 @@ &dsi_rm69298_truly_amoled_video { qcom,mdss-dsi-t-clk-post = <0x0D>; qcom,mdss-dsi-t-clk-pre = <0x30>; - qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,dsi-supported-dfps-list = <60 57 53>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; -- GitLab From 088aaee4a1e5ad4a89322f38ec6f4f354e13c14f Mon Sep 17 00:00:00 2001 From: Nidhisha Dhananjayan Date: Tue, 29 Jan 2019 10:32:52 +0530 Subject: [PATCH 1167/1286] uapi: msm: dolby: Support for TrueHD and MAT decoders Audio codec addition of MAT and TrueHD decoders for decoding in DSP. Change-Id: I049c1210d3600da723850bae1dd61b6ad4b3a78a Acked-by: Janamaddi Sravan Kumar Signed-off-by: Nidhisha Dhananjayan --- include/uapi/sound/compress_params.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/uapi/sound/compress_params.h b/include/uapi/sound/compress_params.h index a0927d3ea1e9..1bb6e0fe6d19 100644 --- a/include/uapi/sound/compress_params.h +++ b/include/uapi/sound/compress_params.h @@ -107,7 +107,9 @@ #define SND_AUDIOCODEC_DSD ((__u32) 0x00000022) #define SND_AUDIOCODEC_APTX ((__u32) 0x00000023) #define SND_AUDIOCODEC_TRUEHD ((__u32) 0x00000024) -#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_TRUEHD +#define SND_AUDIOCODEC_DLB_MAT ((__u32) 0x00000025) +#define SND_AUDIOCODEC_DLB_THD ((__u32) 0x00000026) +#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_DLB_THD /* * Profile and modes are listed with bit masks. This allows for a @@ -361,6 +363,13 @@ struct snd_dec_ddp { __u32 params_value[SND_DEC_DDP_MAX_PARAMS]; } __attribute__((packed, aligned(4))); +#define SND_DEC_THD_MAX_PARAMS 8 +struct snd_dec_thd { + __u32 params_length; + __u32 params_id[SND_DEC_THD_MAX_PARAMS]; + __u32 params_value[SND_DEC_THD_MAX_PARAMS]; +} __attribute__((packed, aligned(4))); + struct snd_dec_flac { __u16 sample_size; __u16 min_blk_size; @@ -419,6 +428,7 @@ union snd_codec_options { struct snd_dec_alac alac; struct snd_dec_ape ape; struct snd_dec_aptx aptx_dec; + struct snd_dec_thd truehd; }; /** struct snd_codec_desc - description of codec capabilities -- GitLab From 23d4a2438254a1607f72e8d233fbdf106895fb9b Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Wed, 2 Jan 2019 20:44:21 +0530 Subject: [PATCH 1168/1286] iommu: do not attempt reclaim on higher order allocs Attempting reclaim for non-zero order allocations can result in the context blocked in reclaim for unpredictable amounts of time. There are cases reported where dma_alloc_attrs gets blocked for 20+ seconds for an allocation of 200MB. Since higher order allocation is not a necessity in the presence of iommu, avoid reclaim. Change-Id: I93f57e2ea5f7c57ec84a92911e2aae36112d95e1 Signed-off-by: Vinayak Menon --- arch/arm64/mm/dma-mapping.c | 11 ++++++++--- drivers/iommu/dma-iommu.c | 5 +++-- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 7351c6f6cdce..a8669b4198b5 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -1262,9 +1262,14 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, while (count) { int j, order = __fls(count); - pages[i] = alloc_pages(gfp, order); - while (!pages[i] && order) - pages[i] = alloc_pages(gfp, --order); + pages[i] = alloc_pages(order ? (gfp | __GFP_NORETRY) & + ~__GFP_RECLAIM : gfp, order); + while (!pages[i] && order) { + order--; + pages[i] = alloc_pages(order ? (gfp | __GFP_NORETRY) & + ~__GFP_RECLAIM : gfp, order); + } + if (!pages[i]) goto error; diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 3b1d92402d37..bf7105e0e539 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -540,8 +540,9 @@ static struct page **__iommu_dma_alloc_pages(unsigned int count, unsigned int order = __fls(order_mask); order_size = 1U << order; - page = alloc_pages((order_mask - order_size) ? - gfp | __GFP_NORETRY : gfp, order); + page = alloc_pages(order ? + (gfp | __GFP_NORETRY) & + ~__GFP_RECLAIM : gfp, order); if (!page) continue; if (!order) -- GitLab From f02ed8a1fd8cbffaaf42ba1bba6f8b5b21663314 Mon Sep 17 00:00:00 2001 From: Shefali Jain Date: Thu, 17 Jan 2019 12:09:02 +0530 Subject: [PATCH 1169/1286] clk: qcom: cmn_blk: Add support for Common block PLL On target like qcs405, Common block PLL is required for USB and PCIE subsystems. Add support for common block pll so that client driver can vote and unvote it as per requirement. Change-Id: Idf6db3f4585fe73f4f9087ec0db7551c0fb6f862 Signed-off-by: Shefali Jain --- .../bindings/clock/qcom,cmn-blk-pll.txt | 26 ++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/cmn-blk-pll.c | 226 ++++++++++++++++++ include/dt-bindings/clock/qcom,cmn-blk-pll.h | 19 ++ 5 files changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,cmn-blk-pll.txt create mode 100644 drivers/clk/qcom/cmn-blk-pll.c create mode 100644 include/dt-bindings/clock/qcom,cmn-blk-pll.h diff --git a/Documentation/devicetree/bindings/clock/qcom,cmn-blk-pll.txt b/Documentation/devicetree/bindings/clock/qcom,cmn-blk-pll.txt new file mode 100644 index 000000000000..ae6ae72bad04 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,cmn-blk-pll.txt @@ -0,0 +1,26 @@ +Qualcomm Technologies, Inc. Common Block PLL Controller Binding +--------------------------------------------------------------- + +Required properties : +- compatible : shall contain only the following: + "qcom,cmn_blk_pll" + +- reg : shall contain base register location and size. +- reg-names : "cmn_blk". +- clock-names : Shall contain "misc_reset", "ahb_clk", "aon_clk". +- clocks : phandle + clock reference to misc_reset, ahb and aon clock. +- #clock-cells : shall contain 1. + +Example : + clock_cmn_blk_pll@2f780 { + compatible = "qcom,cmn_blk_pll"; + reg = <0x2f780 0x4>; + reg-names = "cmn_blk"; + clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>, + <&clock_gcc GCC_BIAS_PLL_AHB_CLK>, + <&clock_gcc GCC_BIAS_PLL_AON_CLK>; + clock-names = "misc_reset_clk", "ahb_clk", "aon_clk"; + resets = <&clock_gcc GCC_BIAS_PLL_BCR>; + reset-names = "cmn_blk_pll_reset"; + #clock-cells = <1>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 08f8e2e0b92c..49216c3f4ee2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -546,3 +546,11 @@ config SM_DEBUGCC_TRINKET Support for the debug clock controller on Qualcomm Technologies, Inc TRINKET devices. Say Y if you want to support the clock measurement functionality. + +config QCS_CMN_BLK_PLL + tristate "QCS405 CMN BLK PLL" + select MDM_GCC_QCS405 + help + Support for the CMN BLK PLL on Qualcomm Technologies, Inc QCS405 + devices. + Say Y if you want to support the Common Block PLL. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f06caae54a54..b72bfe534ee6 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o obj-$(CONFIG_MSM_VIDEOCC_SM8150) += videocc-sm8150.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_QCS_CMN_BLK_PLL) += cmn_blk_pll.o obj-$(CONFIG_SM_DEBUGCC_TRINKET) += debugcc-trinket.o obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o diff --git a/drivers/clk/qcom/cmn-blk-pll.c b/drivers/clk/qcom/cmn-blk-pll.c new file mode 100644 index 000000000000..31455f6e4ce8 --- /dev/null +++ b/drivers/clk/qcom/cmn-blk-pll.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" + +#define SW_RESET_LOGIC_MASK BIT(6) + +struct cmn_blk_pll { + struct regmap *regmap; + struct clk *misc_reset; + struct clk *ahb_clk; + struct clk *aon_clk; + struct reset_control *reset; +}; +static struct cmn_blk_pll pll; + +static unsigned long clk_cmn_blk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return to_clk_fixed_rate(hw)->fixed_rate; +} + +static int clk_cmn_blk_pll_enable(struct clk_hw *hw) +{ + u32 val, ret; + + ret = reset_control_reset(pll.reset); + if (ret) + return ret; + + ret = clk_prepare_enable(pll.misc_reset); + if (ret) + return ret; + + ret = clk_prepare_enable(pll.aon_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(pll.ahb_clk); + if (ret) + return ret; + + ret = regmap_read(pll.regmap, 0, &val); + if (ret) + return ret; + + if (val & SW_RESET_LOGIC_MASK) { + val &= ~BIT(6); + regmap_write(pll.regmap, 0, val); + } + + val |= BIT(6); + regmap_write(pll.regmap, 0, val); + + return 0; +} + +static void clk_cmn_blk_pll_disable(struct clk_hw *hw) +{ + u32 val; + + regmap_read(pll.regmap, 0, &val); + val &= ~BIT(6); + regmap_write(pll.regmap, 0, val); + + clk_disable_unprepare(pll.misc_reset); + clk_disable_unprepare(pll.aon_clk); + clk_disable_unprepare(pll.ahb_clk); +} + +const struct clk_ops clk_cmn_blk_ops = { + .enable = clk_cmn_blk_pll_enable, + .disable = clk_cmn_blk_pll_disable, + .recalc_rate = clk_cmn_blk_recalc_rate, +}; + +static struct clk_fixed_rate cmn_blk_pll = { + .fixed_rate = 100000000, + .hw.init = &(struct clk_init_data){ + .name = "cmn_blk_pll", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_cmn_blk_ops, + }, +}; + +struct clk_hw *cmn_blk_pll_hws[] = { + [CMN_BLK_PLL] = &cmn_blk_pll.hw, +}; + +static const struct regmap_config cmn_blk_pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8, + .fast_io = true, +}; + +static const struct of_device_id cmn_blk_pll_match_table[] = { + { .compatible = "qcom,cmn_blk_pll" }, + { } +}; +MODULE_DEVICE_TABLE(of, cmn_blk_pll_match_table); + +static int cmn_blk_pll_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk_hw_onecell_data *clk_data; + struct device *dev = &pdev->dev; + void __iomem *base; + int i, ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pll.regmap = devm_regmap_init_mmio(&pdev->dev, base, + &cmn_blk_pll_regmap_config); + if (IS_ERR(pll.regmap)) + return PTR_ERR(pll.regmap); + + pll.misc_reset = devm_clk_get(&pdev->dev, "misc_reset_clk"); + if (IS_ERR(pll.misc_reset)) { + if (PTR_ERR(pll.misc_reset) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get misc_reset clock\n"); + return PTR_ERR(pll.misc_reset); + } + + pll.ahb_clk = devm_clk_get(&pdev->dev, "ahb_clk"); + if (IS_ERR(pll.ahb_clk)) { + if (PTR_ERR(pll.ahb_clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get ahb_clk clock\n"); + return PTR_ERR(pll.ahb_clk); + } + + pll.aon_clk = devm_clk_get(&pdev->dev, "aon_clk"); + if (IS_ERR(pll.aon_clk)) { + if (PTR_ERR(pll.aon_clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get aon_clk clock\n"); + return PTR_ERR(pll.aon_clk); + } + + pll.reset = devm_reset_control_get(&pdev->dev, "cmn_blk_pll_reset"); + if (IS_ERR(pll.reset)) { + if (PTR_ERR(pll.reset) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get cmn_blk\n"); + return PTR_ERR(pll.reset); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cmn_blk"); + if (!res) { + dev_err(&pdev->dev, "Register base not defined\n"); + return -ENOMEM; + } + + clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = ARRAY_SIZE(cmn_blk_pll_hws); + + for (i = 0; i < clk_data->num; i++) { + ret = devm_clk_hw_register(dev, cmn_blk_pll_hws[i]); + if (ret) { + dev_err(&pdev->dev, "Failed to register cmn_blk_pll\n"); + return ret; + } + clk_data->hws[i] = cmn_blk_pll_hws[i]; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) { + dev_err(dev, "Unable to register cmn_blk_pll provider ret = %d\n" + , ret); + return ret; + } + + dev_info(&pdev->dev, "Registered CMN BLK PLL\n"); + return 0; +} + +static struct platform_driver cmn_blk_pll_driver = { + .probe = cmn_blk_pll_probe, + .driver = { + .name = "cmn_blk_pll", + .of_match_table = cmn_blk_pll_match_table, + }, +}; + +static int __init cmn_blk_pll_init(void) +{ + return platform_driver_register(&cmn_blk_pll_driver); +} +subsys_initcall(cmn_blk_pll_init); + +static void __exit cmn_blk_pll_exit(void) +{ + platform_driver_unregister(&cmn_blk_pll_driver); +} +module_exit(cmn_blk_pll_exit); diff --git a/include/dt-bindings/clock/qcom,cmn-blk-pll.h b/include/dt-bindings/clock/qcom,cmn-blk-pll.h new file mode 100644 index 000000000000..c390e09a7aa3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,cmn-blk-pll.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CMN_BLK_PLL_H +#define _DT_BINDINGS_CLK_QCOM_CMN_BLK_PLL_H + +#define CMN_BLK_PLL 0 + +#endif -- GitLab From 2e67a988acf6d4fec44a9d780b4519d72b875141 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Tue, 29 Jan 2019 11:21:58 +0530 Subject: [PATCH 1170/1286] ARM: dts: msm: Configure LDO7 as a parent to LDO4 for trinket On trinket UFS platform, LDO7 (USB 0.9V) is affecting UFS and resulting in UFS failures when USB is removed(LDO7 off). This change configures LDO7 as a parent-supply to LDO4 as per power grid scheme to make sure LDO7 is turned off only if LDO4 is off. Change-Id: Ief210254126fd269699ca23eb22800e3b4fc1000 Signed-off-by: Sayali Lokhande --- arch/arm64/boot/dts/qcom/trinket-regulator.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi index c4562ae48bab..cf6ff9284368 100644 --- a/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-regulator.dtsi @@ -159,6 +159,7 @@ rpm-regulator-ldoa4 { status = "okay"; + pm6125_l4-parent-supply = <&pm6125_l7>; L4A: pm6125_l4: regulator-l4 { regulator-min-microvolt = <872000>; regulator-max-microvolt = <1000000>; -- GitLab From 24e0e2153aa5f01c8620b792b087eab6e93aab3e Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Tue, 29 Jan 2019 11:53:25 +0530 Subject: [PATCH 1171/1286] defconfig: trinket: enable kernel crypto framework Enable configuration flag for kernel crypto framework needed for Disk Encryption. Change-Id: I26990fc9b34852298f3f1520b071bfe88548e904 Signed-off-by: Ramandeep Trehan --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index d5cc20275b3f..50e81b661e65 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -269,6 +269,7 @@ CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 0a5dd6fec494..7242fba4e772 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -280,6 +280,7 @@ CONFIG_SCSI_UFS_QCOM=y CONFIG_SCSI_UFSHCD_CMD_LOGGING=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y -- GitLab From 07f2e5c78de06dc4ea07815a7be94565ab699e7d Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Mon, 21 Jan 2019 17:34:02 +0530 Subject: [PATCH 1172/1286] clk: qcom: Keep sys_noc_compute_sf_axi as CRITICAL clock gcc_sys_noc_compute_sf_axi clock is marked as critical as it needs to be always on. Change-Id: I915f888305c9123ff11a7a69e8cc9236d00fadee Signed-off-by: Diptanshu Jamgade --- drivers/clk/qcom/gcc-trinket.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-trinket.c b/drivers/clk/qcom/gcc-trinket.c index 0ec89b65695a..ee1ad685ee98 100644 --- a/drivers/clk/qcom/gcc-trinket.c +++ b/drivers/clk/qcom/gcc-trinket.c @@ -3731,6 +3731,7 @@ static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_compute_sf_axi_clk", + .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, -- GitLab From bde10962331c312204ffe088b3258dfbba5630b8 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Fri, 25 Jan 2019 16:46:33 +0530 Subject: [PATCH 1173/1286] ARM: dts: msm: add secure display ion heap on trinket Add secure display ION heap used for the secure usecases on trinket. Change-Id: I212f50d69999fac46a19a94ef34ebb1c6b0461c5 Signed-off-by: Charan Teja Reddy --- arch/arm64/boot/dts/qcom/trinket-ion.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-ion.dtsi b/arch/arm64/boot/dts/qcom/trinket-ion.dtsi index 4adf296afb30..aa8a2f23448e 100644 --- a/arch/arm64/boot/dts/qcom/trinket-ion.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-ion.dtsi @@ -38,6 +38,12 @@ qcom,ion-heap-type = "SYSTEM_SECURE"; }; + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ reg = <14>; qcom,ion-heap-type = "SECURE_CARVEOUT"; -- GitLab From 2dda6ec008e95d0aad517bdcbbc78e1c3c340e76 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 2 Oct 2018 14:08:16 -0700 Subject: [PATCH 1174/1286] dmaengine: edma: add support for QCOM PCIe eDMA Add dmaengine framework support for QCOM PCIe eDMA controller. PCIe eDMA controller can be used for transferring data between system memory and peripherals. Change-Id: I3eae47922476ac3831eac044af6c243468803016 Signed-off-by: Tony Truong --- drivers/dma/qcom/Kconfig | 18 + drivers/dma/qcom/Makefile | 1 + drivers/dma/qcom/pci-edma.c | 1075 +++++++++++++++++++++++++++++++++++ 3 files changed, 1094 insertions(+) create mode 100644 drivers/dma/qcom/pci-edma.c diff --git a/drivers/dma/qcom/Kconfig b/drivers/dma/qcom/Kconfig index 2afceb1627a1..f6dfd44c763a 100644 --- a/drivers/dma/qcom/Kconfig +++ b/drivers/dma/qcom/Kconfig @@ -46,3 +46,21 @@ config QCOM_GPI_DMA_DEBUG help Enable detailed logging for QCOM GPI driver. Extra logging will be helpful when debugging critical issues. + +config QCOM_PCI_EDMA + tristate "Qualcomm Technologies Inc PCIe eDMA support" + select DMA_ENGINE + help + Enable support for the QCOM PCIe eDMA. This DMA is part of QCOM + PCIe controller that provides DMA capabilities for clients. + By using PCIe eDMA driver, clients can use a standardize + interface that is protocol independent to transfer data between DDR + and peripheral. + +config QCOM_PCI_EDMA_DEBUG + bool "Qualcomm Technologies Inc PCIe eDMA debug support" + depends on QCOM_PCI_EDMA + help + Enable detailed logging for QCOM PCIe eDMA driver. Should + only be enabled for debugging purpose since excessive logging + of all channels information and activity will decrease throughput. diff --git a/drivers/dma/qcom/Makefile b/drivers/dma/qcom/Makefile index 4ab8764d68e1..9ed8d07b6352 100644 --- a/drivers/dma/qcom/Makefile +++ b/drivers/dma/qcom/Makefile @@ -5,3 +5,4 @@ hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o obj-$(CONFIG_QCOM_HIDMA) += hdma.o hdma-objs := hidma_ll.o hidma.o hidma_dbg.o obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o +obj-$(CONFIG_QCOM_PCI_EDMA) += pci-edma.o diff --git a/drivers/dma/qcom/pci-edma.c b/drivers/dma/qcom/pci-edma.c new file mode 100644 index 000000000000..096d97e5adee --- /dev/null +++ b/drivers/dma/qcom/pci-edma.c @@ -0,0 +1,1075 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../dmaengine.h" + +/* global logging macros */ +#define EDMA_LOG(e_dev, fmt, ...) do { \ + if (e_dev->klog_lvl != LOG_LVL_MASK_ALL) \ + dev_dbg(e_dev->dev, "[I] %s: %s: " fmt, e_dev->label, \ + __func__, ##__VA_ARGS__); \ + if (e_dev->ipc_log && e_dev->ipc_log_lvl != LOG_LVL_MASK_ALL) \ + ipc_log_string(e_dev->ipc_log, \ + "[I] %s: %s: " fmt, e_dev->label, __func__, \ + ##__VA_ARGS__); \ + } while (0) +#define EDMA_ERR(e_dev, fmt, ...) do { \ + if (e_dev->klog_lvl <= LOG_LVL_ERROR) \ + dev_err(e_dev->dev, "[E] %s: %s: " fmt, e_dev->label, \ + __func__, ##__VA_ARGS__); \ + if (e_dev->ipc_log && e_dev->ipc_log_lvl <= LOG_LVL_ERROR) \ + ipc_log_string(e_dev->ipc_log, \ + "[E] %s: %s: " fmt, e_dev->label, __func__, \ + ##__VA_ARGS__); \ + } while (0) + +#define EDMA_ASSERT(cond, msg) do { \ + if (cond) \ + panic(msg); \ + } while (0) + +/* edmac specific logging macros */ +#define EDMAC_INFO(ec_dev, ev_ch, fmt, ...) do { \ + if (ec_dev->klog_lvl <= LOG_LVL_INFO) \ + pr_info("[I] %s: %s: %u: %u: %s: " fmt, ec_dev->label, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), ec_dev->ch_id, ev_ch, \ + __func__, ##__VA_ARGS__); \ + if (ec_dev->ipc_log && ec_dev->ipc_log_lvl <= LOG_LVL_INFO) \ + ipc_log_string(ec_dev->ipc_log, \ + "[I] %s: EC_%u: EV_%u: %s: " fmt, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), \ + ec_dev->ch_id, ev_ch, __func__, \ + ##__VA_ARGS__); \ + } while (0) +#define EDMAC_ERR(ec_dev, ev_ch, fmt, ...) do { \ + if (ec_dev->klog_lvl <= LOG_LVL_ERROR) \ + pr_err("[E] %s: %s: %u: %u: %s: " fmt, ec_dev->label, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), ec_dev->ch_id, ev_ch, \ + __func__, ##__VA_ARGS__); \ + if (ec_dev->ipc_log && ec_dev->ipc_log_lvl <= LOG_LVL_ERROR) \ + ipc_log_string(ec_dev->ipc_log, \ + "[E] %s: EC_%u: EV_%u: %s: " fmt, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), \ + ec_dev->ch_id, ev_ch, __func__, \ + ##__VA_ARGS__); \ + } while (0) + +enum debug_log_lvl { + LOG_LVL_VERBOSE, + LOG_LVL_INFO, + LOG_LVL_ERROR, + LOG_LVL_MASK_ALL, +}; + +#define EDMA_DRV_NAME "edma" +#define DEFAULT_KLOG_LVL (LOG_LVL_ERROR) + +#ifdef CONFIG_QCOM_PCI_EDMA_DEBUG +#define DEFAULT_IPC_LOG_LVL (LOG_LVL_VERBOSE) +#define IPC_LOG_PAGES (40) +#define EDMA_IRQ(e_dev, ec_ch, fmt, ...) do { \ + if (e_dev->klog_lvl != LOG_LVL_MASK_ALL) \ + dev_dbg(e_dev->dev, "[IRQ] %s: EC_%u: %s: " fmt, e_dev->label, \ + ec_ch, __func__, ##__VA_ARGS__); \ + if (e_dev->ipc_log_irq && e_dev->ipc_log_lvl != LOG_LVL_MASK_ALL) \ + ipc_log_string(e_dev->ipc_log_irq, \ + "[IRQ] %s: EC_%u: %s: " fmt, e_dev->label, ec_ch, \ + __func__, ##__VA_ARGS__); \ + } while (0) +#define EDMAC_VERB(ec_dev, ev_ch, fmt, ...) do { \ + if (ec_dev->klog_lvl <= LOG_LVL_VERBOSE) \ + pr_info("[V] %s: %s: %u: %u: %s: " fmt, ec_dev->label, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), ec_dev->ch_id, ev_ch, \ + __func__, ##__VA_ARGS__); \ + if (ec_dev->ipc_log && ec_dev->ipc_log_lvl <= LOG_LVL_VERBOSE) \ + ipc_log_string(ec_dev->ipc_log, \ + "[V] %s: EC_%u: EV_%u: %s: " fmt, \ + TO_EDMA_DIR_CH_STR(ec_dev->dir), \ + ec_dev->ch_id, ev_ch, __func__, \ + ##__VA_ARGS__); \ + } while (0) + +#else +#define IPC_LOG_PAGES (2) +#define DEFAULT_IPC_LOG_LVL (LOG_LVL_ERROR) +#define EDMA_IRQ(e_dev, ec_ch, fmt, ...) +#define EDMAC_REG(ec_dev, ev_ch, fmt, ...) +#define EDMAC_VERB(ec_dev, ev_ch, fmt, ...) +#endif + +#define WR_CH_BASE (0x200) +#define RD_CH_BASE (0x300) +#define DMA_CH_BASE(d, n) ((d == EDMA_WR_CH ? WR_CH_BASE : RD_CH_BASE) +\ + (n * 0x200)) + +#define DMA_CH_CONTROL1_REG_DIR_CH_N(d, n) (DMA_CH_BASE(d, n)) +#define DMA_LLP_LOW_OFF_DIR_CH_N(d, n) (DMA_CH_BASE(d, n) + 0x1c) +#define DMA_LLP_HIGH_OFF_DIR_CH_N(d, n) (DMA_CH_BASE(d, n) + 0x20) + +#define DMA_WRITE_ENGINE_EN_OFF (0xc) +#define DMA_WRITE_DOORBELL_OFF (0x10) +#define DMA_WRITE_INT_STATUS_OFF (0x4c) +#define DMA_WRITE_INT_MASK_OFF (0x54) +#define DMA_WRITE_INT_CLEAR_OFF (0x58) +#define DMA_WRITE_LINKED_LIST_ERR_EN_OFF (0x90) + +#define DMA_READ_ENGINE_EN_OFF (0x2c) +#define DMA_READ_DOORBELL_OFF (0x30) +#define DMA_READ_INT_STATUS_OFF (0xa0) +#define DMA_READ_INT_MASK_OFF (0xa8) +#define DMA_READ_INT_CLEAR_OFF (0xac) +#define DMA_READ_LINKED_LIST_ERR_EN_OFF (0xc4) + +#define DMA_CTRL_OFF (0x8) +#define DMA_CTRL_NUM_CH_MASK (0xf) +#define DMA_CTRL_NUM_WR_CH_SHIFT (0) +#define DMA_CTRL_NUM_RD_CH_SHIFT (16) + +#define EDMA_LABEL_SIZE (256) +#define EDMA_DESC_LIST_SIZE (256) +#define EDMA_NUM_MAX_EV_CH (32) +#define EDMA_NUM_TL_INIT (2) +#define EDMA_NUM_TL_ELE (1024) + +#define EDMA_CH_CONTROL1_LLE BIT(9) /* Linked List Enable */ +#define EDMA_CH_CONTROL1_CCS BIT(8) /* Consumer Cycle Status */ +#define EDMA_CH_CONTROL1_LIE BIT(3) /* Local Interrupt Enable */ +#define EDMA_CH_CONTROL1_LLP BIT(2) /* Load Link Pointer */ +#define EDMA_CH_CONTROL1_CB BIT(0) /* Cycle bit */ + +#define EDMA_CH_CONTROL1_INIT (EDMA_CH_CONTROL1_LLE | EDMA_CH_CONTROL1_CCS) +#define EDMA_HW_STATUS_MASK (BIT(6) | BIT(5)) +#define EDMA_HW_STATUS_SHIFT (5) +#define EDMA_INT_ERR_MASK (0xff00) + +#define REQ_OF_DMA_ARGS (2) /* # of arguments required from client */ + +/* + * EDMAV CH ID = EDMA CH ID * EDMAV_BASE_CH_ID + EDMAV index + * + * Virtual channel is assigned a channel ID based on the physical + * channel is it assigned to. + * ex: + * physical channel 0: virtual base = 0 + * physical channel 1: virtual base = 100 + * physical channel 2: virtual base = 200 + */ +#define EDMAV_BASE_CH_ID (100) +#define EDMAV_NO_CH_ID (99) /* RESERVED CH ID for no virtual channel */ + +enum edma_dir_ch { + EDMA_WR_CH, + EDMA_RD_CH, + EDMA_DIR_CH_MAX, +}; + +static const char *const edma_dir_ch_str[EDMA_DIR_CH_MAX] = { + [EDMA_WR_CH] = "WR", + [EDMA_RD_CH] = "RD", +}; + +#define TO_EDMA_DIR_CH_STR(dir) (dir < EDMA_DIR_CH_MAX ? \ + edma_dir_ch_str[dir] : "INVALID") + +enum edma_hw_state { + EDMA_HW_STATE_INIT, + EDMA_HW_STATE_ACTIVE, + EDMA_HW_STATE_HALTED, + EDMA_HW_STATE_STOPPED, + EDMA_HW_STATE_MAX, +}; + +static const char *const edma_hw_state_str[EDMA_HW_STATE_MAX] = { + [EDMA_HW_STATE_INIT] = "INIT", + [EDMA_HW_STATE_ACTIVE] = "ACTIVE", + [EDMA_HW_STATE_HALTED] = "HALTED", + [EDMA_HW_STATE_STOPPED] = "STOPPED", +}; + +#define TO_EDMA_HW_STATE_STR(state) (state < EDMA_HW_STATE_MAX ? \ + edma_hw_state_str[state] : "INVALID") + +/* transfer list element */ +struct data_element { + u32 ch_ctrl; + u32 size; + u64 sar; + u64 dar; +}; + +/* transfer list last element */ +struct link_element { + u32 ch_ctrl; + u32 reserved0; + u64 lle_ptr; /* points to new transfer list */ + u32 reserved1; + u32 reserved2; +}; + +union edma_element { + struct data_element de; + struct link_element le; +}; + +/* main structure for eDMA driver */ +struct edma_dev { + struct list_head node; + struct dma_device dma_device; + struct device_node *of_node; + struct device *dev; + struct edmac_dev *ec_wr_devs; /* array of wr channels */ + struct edmac_dev *ec_rd_devs; /* array of rd channels */ + struct edmav_dev *ev_devs; /* array of virtual channels */ + u32 n_max_ec_ch; /* max physical channels */ + u32 n_max_ev_ch; /* max virtual channels */ + u32 n_wr_ch; + u32 n_rd_ch; + u32 cur_wr_ch_idx; /* index for wr round robin allocation */ + u32 cur_rd_ch_idx; /* index for rd round robin allocation */ + u32 cur_ev_ch_idx; /* index for next available eDMA virtual chan */ + u32 n_tl_init; /* # of transfer list for each channel init */ + u32 n_tl_ele; /* (# of de + le) */ + phys_addr_t base_phys; + size_t base_size; + void __iomem *base; + int irq; + u32 edmac_mask; /* edma channel available for apps */ + char label[EDMA_LABEL_SIZE]; + void *ipc_log; + void *ipc_log_irq; + enum debug_log_lvl ipc_log_lvl; + enum debug_log_lvl klog_lvl; +}; + +/* eDMA physical channels */ +struct edmac_dev { + struct list_head ev_list; + struct edma_dev *e_dev; + u32 n_ev; + u32 ch_id; + enum edma_dir_ch dir; + dma_addr_t tl_dma_rd_p; /* address of next DE to process */ + struct data_element *tl_wr_p; /* next available DE in TL */ + struct data_element *tl_rd_p; + struct link_element *le_p; /* link element of newest TL */ + struct edma_desc **dl_wr_p; /* next available desc in DL */ + struct edma_desc **dl_rd_p; + struct edma_desc **ldl_p; /* last desc of newest desc list */ + u32 n_de_avail; /* # of available DE in current TL (excludes LE) */ + struct tasklet_struct proc_task; /* processing tasklet */ + char label[EDMA_LABEL_SIZE]; + void *ipc_log; + enum debug_log_lvl ipc_log_lvl; + enum debug_log_lvl klog_lvl; + enum edma_hw_state hw_state; + + void __iomem *engine_en_reg; + void __iomem *int_mask_reg; + void __iomem *ll_err_en_reg; + void __iomem *ch_ctrl1_reg; + void __iomem *llp_low_reg; + void __iomem *llp_high_reg; + void __iomem *db_reg; +}; + +/* eDMA virtual channels */ +struct edmav_dev { + struct list_head node; + struct edmac_dev *ec_dev; + struct list_head dl; + struct dma_chan dma_ch; + enum edma_dir_ch dir; + u32 ch_id; + u32 priority; + u32 n_de; + u32 outstanding; +}; + +/* eDMA descriptor and last descriptor */ +struct edma_desc { + struct list_head node; + struct edmav_dev *ev_dev; + struct dma_async_tx_descriptor tx; + struct data_element *de; + + /* Below are for LDESC (last desc of the list) */ + dma_addr_t tl_dma; /* start of this transfer list (physical) */ + union edma_element *tl; /* start of this transfer list (virtual) */ + struct edma_desc **dl; /* start of this desc list */ + dma_addr_t tl_dma_next; /* next transfer list (physical) */ + union edma_element *tl_next; /* next transfer list (virtual) */ + struct edma_desc **dl_next;/* next desc list */ +}; + +static void edma_set_clear(void __iomem *addr, u32 set, + u32 clear) +{ + u32 val; + + val = (readl_relaxed(addr) & ~clear) | set; + writel_relaxed(val, addr); + + /* ensure register write goes through before next register operation */ + wmb(); +} + +static enum edma_hw_state edma_get_hw_state(struct edmac_dev *ec_dev) +{ + u32 val; + + val = readl_relaxed(ec_dev->ch_ctrl1_reg); + val &= EDMA_HW_STATUS_MASK; + val >>= EDMA_HW_STATUS_SHIFT; + + return val; +} + +static struct edmav_dev *to_edmav_dev(struct dma_chan *dma_ch) +{ + return container_of(dma_ch, struct edmav_dev, dma_ch); +} + +static void edmac_process_tasklet(unsigned long data) +{ + struct edmac_dev *ec_dev = (struct edmac_dev *)data; + struct edma_dev *e_dev = ec_dev->e_dev; + dma_addr_t llp_low, llp_high, llp; + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "enter\n"); + + llp_low = readl_relaxed(ec_dev->llp_low_reg); + llp_high = readl_relaxed(ec_dev->llp_high_reg); + llp = (u64)(llp_high << 32) | llp_low; + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "DMA_LLP: %pad\n", &llp); + + while (ec_dev->tl_dma_rd_p != llp) { + struct edma_desc *desc; + + /* current element is a link element. Need to jump and free */ + if (ec_dev->tl_rd_p->ch_ctrl & EDMA_CH_CONTROL1_LLP) { + struct edma_desc *ldesc = *ec_dev->dl_rd_p; + + ec_dev->tl_dma_rd_p = ldesc->tl_dma_next; + ec_dev->tl_rd_p = (struct data_element *)ldesc->tl_next; + ec_dev->dl_rd_p = ldesc->dl_next; + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, + "free transfer list: %pad\n", &ldesc->tl_dma); + dma_free_coherent(e_dev->dev, + sizeof(*ldesc->tl) * e_dev->n_tl_ele, + ldesc->tl, ldesc->tl_dma); + kfree(ldesc->dl); + continue; + } + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "TL_DMA_RD_P: %pad\n", + &ec_dev->tl_dma_rd_p); + + desc = *ec_dev->dl_rd_p; + if (desc) { + dmaengine_desc_get_callback_invoke(&desc->tx, NULL); + kfree(desc); + } + + ec_dev->tl_dma_rd_p += sizeof(struct data_element); + ec_dev->tl_rd_p++; + ec_dev->dl_rd_p++; + } + + edma_set_clear(ec_dev->int_mask_reg, 0, BIT(ec_dev->ch_id)); + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "exit\n"); +} + +static irqreturn_t handle_edma_irq(int irq, void *data) +{ + struct edma_dev *e_dev = data; + u32 wr_int_status; + u32 rd_int_status; + int i = 0; + + wr_int_status = readl_relaxed(e_dev->base + DMA_WRITE_INT_STATUS_OFF); + rd_int_status = readl_relaxed(e_dev->base + DMA_READ_INT_STATUS_OFF); + + edma_set_clear(e_dev->base + DMA_WRITE_INT_CLEAR_OFF, wr_int_status, 0); + edma_set_clear(e_dev->base + DMA_READ_INT_CLEAR_OFF, rd_int_status, 0); + + EDMA_IRQ(e_dev, EDMAV_NO_CH_ID, + "IRQ wr status: 0x%x rd status: 0x%x\n", + wr_int_status, rd_int_status); + + EDMA_ASSERT((wr_int_status & EDMA_INT_ERR_MASK) || + (rd_int_status & EDMA_INT_ERR_MASK), + "Error reported by H/W\n"); + + while (wr_int_status) { + if (wr_int_status & 0x1) { + struct edmac_dev *ec_dev = &e_dev->ec_wr_devs[i]; + + edma_set_clear(ec_dev->int_mask_reg, + BIT(ec_dev->ch_id), 0); + tasklet_schedule(&ec_dev->proc_task); + } + wr_int_status >>= 1; + i++; + } + + i = 0; + while (rd_int_status) { + if (rd_int_status & 0x1) { + struct edmac_dev *ec_dev = &e_dev->ec_rd_devs[i]; + + edma_set_clear(ec_dev->int_mask_reg, + BIT(ec_dev->ch_id), 0); + tasklet_schedule(&ec_dev->proc_task); + } + rd_int_status >>= 1; + i++; + } + + return IRQ_HANDLED; +} + +static struct dma_chan *edma_of_dma_xlate(struct of_phandle_args *args, + struct of_dma *of_dma) +{ + struct edma_dev *e_dev = (struct edma_dev *)of_dma->of_dma_data; + struct edmac_dev *ec_dev; + struct edmav_dev *ev_dev; + u32 ch_id; + + if (args->args_count < REQ_OF_DMA_ARGS) { + EDMA_ERR(e_dev, + "EDMA requires atleast %d arguments, client passed:%d\n", + REQ_OF_DMA_ARGS, args->args_count); + return NULL; + } + + if (e_dev->cur_ev_ch_idx >= e_dev->n_max_ev_ch) { + EDMA_ERR(e_dev, "No more eDMA virtual channels available\n"); + return NULL; + } + + ev_dev = &e_dev->ev_devs[e_dev->cur_ev_ch_idx++]; + + ev_dev->dir = args->args[0] ? EDMA_RD_CH : EDMA_WR_CH; + ev_dev->priority = args->args[1]; + + /* use round robin to allocate eDMA channel */ + if (ev_dev->dir == EDMA_WR_CH) { + ch_id = e_dev->cur_wr_ch_idx++ % e_dev->n_wr_ch; + ec_dev = &e_dev->ec_wr_devs[ch_id]; + } else { + ch_id = e_dev->cur_rd_ch_idx++ % e_dev->n_rd_ch; + ec_dev = &e_dev->ec_rd_devs[ch_id]; + } + + ev_dev->ec_dev = ec_dev; + ev_dev->ch_id = EDMAV_BASE_CH_ID * ec_dev->ch_id + ec_dev->n_ev; + + list_add_tail(&ev_dev->node, &ec_dev->ev_list); + + EDMA_LOG(e_dev, "EC_ID: %u EV_ID: %u direction: %s priority: %u", + ec_dev->ch_id, ev_dev->ch_id, TO_EDMA_DIR_CH_STR(ev_dev->dir), + ev_dev->priority); + + return dma_get_slave_channel(&ev_dev->dma_ch); +} + +static int edma_alloc_transfer_list(struct edmac_dev *ec_dev) +{ + struct edma_dev *e_dev = ec_dev->e_dev; + union edma_element *tl; + struct edma_desc **dl; + struct edma_desc *ldesc; + dma_addr_t tl_dma; + u32 n_tl_ele = e_dev->n_tl_ele; + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "enter\n"); + + tl = dma_zalloc_coherent(e_dev->dev, sizeof(*tl) * n_tl_ele, + &tl_dma, GFP_ATOMIC); + if (!tl) + return -ENOMEM; + + dl = kcalloc(n_tl_ele, sizeof(*dl), GFP_ATOMIC); + if (!dl) + goto free_transfer_list; + + ldesc = kzalloc(sizeof(*ldesc), GFP_ATOMIC); + if (!ldesc) + goto free_descriptor_list; + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, + "allocated transfer list dma: %pad\n", &tl_dma); + + dl[n_tl_ele - 1] = ldesc; + + if (ec_dev->tl_wr_p) { + /* link current lists with new lists */ + ec_dev->le_p->lle_ptr = tl_dma; + (*ec_dev->ldl_p)->tl_dma_next = tl_dma; + (*ec_dev->ldl_p)->tl_next = tl; + (*ec_dev->ldl_p)->dl_next = dl; + } else { + /* init read and write ptr if these are the initial lists */ + ec_dev->tl_dma_rd_p = tl_dma; + ec_dev->tl_wr_p = ec_dev->tl_rd_p = (struct data_element *)tl; + ec_dev->dl_wr_p = ec_dev->dl_rd_p = dl; + } + + /* move ptr and compose LE and LDESC of new lists */ + ec_dev->le_p = (struct link_element *)&tl[n_tl_ele - 1]; + ec_dev->le_p->ch_ctrl = EDMA_CH_CONTROL1_LLP | EDMA_CH_CONTROL1_CB; + + /* setup ldesc */ + ec_dev->ldl_p = dl + n_tl_ele - 1; + (*ec_dev->ldl_p)->tl_dma = tl_dma; + (*ec_dev->ldl_p)->tl = tl; + (*ec_dev->ldl_p)->dl = dl; + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "exit\n"); + + return 0; + +free_descriptor_list: + kfree(dl); +free_transfer_list: + dma_free_coherent(e_dev->dev, sizeof(*tl) * n_tl_ele, tl, tl_dma); + + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "exit with error\n"); + + return -ENOMEM; +} + +static void edma_free_chan_resources(struct dma_chan *chan) +{ + struct edmav_dev *ev_dev = to_edmav_dev(chan); + struct edmac_dev *ec_dev = ev_dev->ec_dev; + struct edma_dev *e_dev = ec_dev->e_dev; + struct edma_desc **ldesc; + + if (!ec_dev->n_ev) + return; + + if (--ec_dev->n_ev) + return; + + /* get ldesc of desc */ + ldesc = ec_dev->dl_wr_p + ec_dev->n_de_avail + 1; + while (ldesc) { + struct edma_desc *ldesc_t = *ldesc; + + /* move ldesc ptr to next list ldesc and free current lists */ + if (ldesc_t->dl_next) + ldesc = ldesc_t->dl_next + e_dev->n_tl_ele - 1; + else + ldesc = NULL; + + if (ldesc_t->tl) + dma_free_coherent(e_dev->dev, + sizeof(*ldesc_t->tl) * e_dev->n_tl_ele, + ldesc_t->tl, ldesc_t->tl_dma); + kfree(ldesc_t->dl); + } + + ec_dev->dl_wr_p = ec_dev->dl_rd_p = ec_dev->ldl_p = NULL; + ec_dev->tl_wr_p = ec_dev->tl_rd_p = NULL; + ec_dev->le_p = NULL; + ec_dev->tl_dma_rd_p = 0; +} + +static int edma_alloc_chan_resources(struct dma_chan *chan) +{ + struct edmav_dev *ev_dev = to_edmav_dev(chan); + struct edmac_dev *ec_dev = ev_dev->ec_dev; + struct edma_dev *e_dev = ec_dev->e_dev; + int ret = 0; + + /* + * If this is the first client for this eDMA channel, setup the initial + * transfer and descriptor lists and configure the H/W for it. + */ + if (!ec_dev->n_ev) { + int i; + + for (i = 0; i < e_dev->n_tl_init; i++) { + ret = edma_alloc_transfer_list(ec_dev); + if (ret) + goto out; + } + + writel_relaxed(true, ec_dev->engine_en_reg); + writel_relaxed(0, ec_dev->int_mask_reg); + writel_relaxed(true, ec_dev->ll_err_en_reg); + writel_relaxed(EDMA_CH_CONTROL1_INIT, ec_dev->ch_ctrl1_reg); + writel_relaxed(lower_32_bits(ec_dev->tl_dma_rd_p), + ec_dev->llp_low_reg); + writel_relaxed(upper_32_bits(ec_dev->tl_dma_rd_p), + ec_dev->llp_high_reg); + ec_dev->n_de_avail = e_dev->n_tl_ele - 1; + } + ec_dev->n_ev++; + + return 0; +out: + edma_free_chan_resources(chan); + return ret; +} + +static inline void edma_compose_data_element(struct edmav_dev *ev_dev, + struct data_element *de, dma_addr_t dst_addr, + dma_addr_t src_addr, size_t size, + unsigned long flags) +{ + EDMAC_VERB(ev_dev->ec_dev, ev_dev->ch_id, + "dst_addr: %pad\tsrc_addr: %pad\n", + &dst_addr, &src_addr); + + de->ch_ctrl |= EDMA_CH_CONTROL1_CB; + if (flags & DMA_PREP_INTERRUPT) + de->ch_ctrl |= EDMA_CH_CONTROL1_LIE; + de->size = size; + de->sar = src_addr; + de->dar = dst_addr; +} + +static struct edma_desc *edma_alloc_descriptor(struct edmav_dev *ev_dev) +{ + struct edma_desc *desc; + + desc = kzalloc(sizeof(*desc) + sizeof(*desc->de), + GFP_ATOMIC); + if (!desc) + return NULL; + + desc->de = (struct data_element *)(&desc[1]); + desc->ev_dev = ev_dev; + ev_dev->n_de++; + + dma_async_tx_descriptor_init(&desc->tx, &ev_dev->dma_ch); + + return desc; +} + +struct dma_async_tx_descriptor *edma_prep_dma_memcpy(struct dma_chan *chan, + dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct edmav_dev *ev_dev = to_edmav_dev(chan); + struct edma_desc *desc; + + EDMAC_VERB(ev_dev->ec_dev, ev_dev->ch_id, "enter\n", chan); + + desc = edma_alloc_descriptor(ev_dev); + if (!desc) + goto err; + + edma_compose_data_element(ev_dev, desc->de, dst, src, len, flags); + + /* insert the descriptor to client descriptor list */ + list_add_tail(&desc->node, &ev_dev->dl); + + EDMAC_VERB(ev_dev->ec_dev, ev_dev->ch_id, "exit\n", chan); + + return &desc->tx; +err: + EDMAC_VERB(ev_dev->ec_dev, ev_dev->ch_id, "exit with error\n", chan); + return NULL; +} + +static void edma_issue_descriptor(struct edmac_dev *ec_dev, + struct edma_desc *desc) +{ + /* set descriptor for last Data Element */ + *ec_dev->dl_wr_p = desc; + memcpy(ec_dev->tl_wr_p, desc->de, sizeof(*desc->de)); + + ec_dev->dl_wr_p++; + ec_dev->tl_wr_p++; + ec_dev->n_de_avail--; + + /* dl_wr_p points to ldesc and tl_wr_p points link element */ + if (!ec_dev->n_de_avail) { + int ret; + + ec_dev->tl_wr_p = (struct data_element *) + (*ec_dev->dl_wr_p)->tl_next; + ec_dev->dl_wr_p = (*ec_dev->dl_wr_p)->dl_next; + ec_dev->n_de_avail = ec_dev->e_dev->n_tl_ele - 1; + + ret = edma_alloc_transfer_list(ec_dev); + EDMA_ASSERT(ret, "failed to allocate new transfer list\n"); + } +} + +static void edma_issue_pending(struct dma_chan *chan) +{ + struct edmav_dev *ev_dev = to_edmav_dev(chan); + struct edmac_dev *ec_dev = ev_dev->ec_dev; + struct edma_desc *desc; + enum edma_hw_state hw_state; + + EDMAC_VERB(ec_dev, ev_dev->ch_id, "enter\n"); + + if (unlikely(list_empty(&ev_dev->dl))) { + EDMAC_VERB(ec_dev, ev_dev->ch_id, "No descriptor to issue\n"); + return; + } + + list_for_each_entry(desc, &ev_dev->dl, node) + edma_issue_descriptor(ec_dev, desc); + + list_del_init(&ev_dev->dl); + + hw_state = edma_get_hw_state(ec_dev); + if ((hw_state == EDMA_HW_STATE_STOPPED) || + (hw_state == EDMA_HW_STATE_INIT)) { + EDMAC_VERB(ec_dev, EDMAV_NO_CH_ID, "ringing doorbell\n"); + writel_relaxed(ec_dev->ch_id, ec_dev->db_reg); + ec_dev->hw_state = EDMA_HW_STATE_ACTIVE; + } + + EDMAC_VERB(ec_dev, ev_dev->ch_id, "exit\n"); +} + +static int edma_config(struct dma_chan *chan, struct dma_slave_config *config) +{ + return -EINVAL; +} + +static int edma_terminate_all(struct dma_chan *chan) +{ + return -EINVAL; +} + +static int edma_pause(struct dma_chan *chan) +{ + return -EINVAL; +} + +static int edma_resume(struct dma_chan *chan) +{ + return -EINVAL; +} + +static int edma_init_irq(struct edma_dev *e_dev) +{ + int ret; + + ret = of_irq_get_byname(e_dev->of_node, "pci-edma-int"); + if (ret <= 0) { + EDMA_ERR(e_dev, "failed to get IRQ from DT. ret: %d\n", ret); + return ret; + } + + e_dev->irq = ret; + EDMA_LOG(e_dev, "received eDMA irq %d", e_dev->irq); + + ret = devm_request_irq(e_dev->dev, e_dev->irq, + handle_edma_irq, IRQF_TRIGGER_HIGH, + e_dev->label, e_dev); + if (ret < 0) { + EDMA_ERR(e_dev, "failed to request irq: %d ret: %d\n", + e_dev->irq, ret); + return ret; + } + + return 0; +} + +static void edma_init_log(struct edma_dev *e_dev, struct edmac_dev *ec_dev) +{ + if (!ec_dev) { + snprintf(e_dev->label, EDMA_LABEL_SIZE, "%s_%llx", + EDMA_DRV_NAME, (u64)e_dev->base_phys); + + e_dev->ipc_log_lvl = DEFAULT_IPC_LOG_LVL; + e_dev->klog_lvl = DEFAULT_KLOG_LVL; + e_dev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, + e_dev->label, 0); + e_dev->ipc_log_irq = ipc_log_context_create(IPC_LOG_PAGES, + e_dev->label, 0); + } else { + snprintf(ec_dev->label, EDMA_LABEL_SIZE, "%s_%llx_%s_ch_%u", + EDMA_DRV_NAME, (u64)e_dev->base_phys, + (ec_dev->dir == EDMA_WR_CH ? "wr" : "rd"), + ec_dev->ch_id); + + ec_dev->ipc_log_lvl = DEFAULT_IPC_LOG_LVL; + ec_dev->klog_lvl = DEFAULT_KLOG_LVL; + ec_dev->ipc_log = ipc_log_context_create(IPC_LOG_PAGES, + ec_dev->label, 0); + } +} + +static void edma_init_channels(struct edma_dev *e_dev) +{ + int i; + + /* setup physical channels */ + for (i = 0; i < e_dev->n_max_ec_ch; i++) { + struct edmac_dev *ec_dev; + enum edma_dir_ch dir; + u32 ch_id; + u32 engine_en_off, int_mask_off, ll_err_en_off; + u32 ch_ctrl1_off, llp_low_off, llp_high_off, db_off; + + if (i < e_dev->n_wr_ch) { + ch_id = i; + ec_dev = &e_dev->ec_wr_devs[ch_id]; + dir = EDMA_WR_CH; + engine_en_off = DMA_WRITE_ENGINE_EN_OFF; + int_mask_off = DMA_WRITE_INT_MASK_OFF; + ll_err_en_off = DMA_WRITE_LINKED_LIST_ERR_EN_OFF; + ch_ctrl1_off = DMA_CH_CONTROL1_REG_DIR_CH_N(dir, ch_id); + llp_low_off = DMA_LLP_LOW_OFF_DIR_CH_N(dir, ch_id); + llp_high_off = DMA_LLP_HIGH_OFF_DIR_CH_N(dir, ch_id); + db_off = DMA_WRITE_DOORBELL_OFF; + } else { + ch_id = i - e_dev->n_wr_ch; + ec_dev = &e_dev->ec_rd_devs[ch_id]; + dir = EDMA_RD_CH; + engine_en_off = DMA_READ_ENGINE_EN_OFF; + int_mask_off = DMA_READ_INT_MASK_OFF; + ll_err_en_off = DMA_READ_LINKED_LIST_ERR_EN_OFF; + ch_ctrl1_off = DMA_CH_CONTROL1_REG_DIR_CH_N(dir, ch_id); + llp_low_off = DMA_LLP_LOW_OFF_DIR_CH_N(dir, ch_id); + llp_high_off = DMA_LLP_HIGH_OFF_DIR_CH_N(dir, ch_id); + db_off = DMA_READ_DOORBELL_OFF; + } + + ec_dev->e_dev = e_dev; + ec_dev->ch_id = ch_id; + ec_dev->dir = dir; + ec_dev->hw_state = EDMA_HW_STATE_INIT; + + edma_init_log(e_dev, ec_dev); + + INIT_LIST_HEAD(&ec_dev->ev_list); + tasklet_init(&ec_dev->proc_task, edmac_process_tasklet, + (unsigned long)ec_dev); + + EDMA_LOG(e_dev, "EC_DIR: %s EC_INDEX: %d EC_ADDR: 0x%pK\n", + TO_EDMA_DIR_CH_STR(ec_dev->dir), ec_dev->ch_id, ec_dev); + + ec_dev->engine_en_reg = e_dev->base + engine_en_off; + ec_dev->int_mask_reg = e_dev->base + int_mask_off; + ec_dev->ll_err_en_reg = e_dev->base + ll_err_en_off; + ec_dev->ch_ctrl1_reg = e_dev->base + ch_ctrl1_off; + ec_dev->llp_low_reg = e_dev->base + llp_low_off; + ec_dev->llp_high_reg = e_dev->base + llp_high_off; + ec_dev->db_reg = e_dev->base + db_off; + } + + /* setup virtual channels */ + for (i = 0; i < e_dev->n_max_ev_ch; i++) { + struct edmav_dev *ev_dev = &e_dev->ev_devs[i]; + + dma_cookie_init(&ev_dev->dma_ch); + INIT_LIST_HEAD(&ev_dev->dl); + ev_dev->dma_ch.device = &e_dev->dma_device; + + list_add_tail(&ev_dev->dma_ch.device_node, + &e_dev->dma_device.channels); + + EDMA_LOG(e_dev, "EV_INDEX: %d EV_ADDR: 0x%pK\n", i, ev_dev); + } +} + +static void edma_init_dma_device(struct edma_dev *e_dev) +{ + /* clear and set capabilities */ + dma_cap_zero(e_dev->dma_device.cap_mask); + dma_cap_set(DMA_MEMCPY, e_dev->dma_device.cap_mask); + + e_dev->dma_device.dev = e_dev->dev; + e_dev->dma_device.device_config = edma_config; + e_dev->dma_device.device_pause = edma_pause; + e_dev->dma_device.device_resume = edma_resume; + e_dev->dma_device.device_terminate_all = edma_terminate_all; + e_dev->dma_device.device_alloc_chan_resources = + edma_alloc_chan_resources; + e_dev->dma_device.device_free_chan_resources = + edma_free_chan_resources; + e_dev->dma_device.device_prep_dma_memcpy = edma_prep_dma_memcpy; + e_dev->dma_device.device_issue_pending = edma_issue_pending; + e_dev->dma_device.device_tx_status = dma_cookie_status; +} + +/* + * Initializes and enables eDMA driver and H/W block for PCIe controllers. + * Only call this function if PCIe supports eDMA and has all its resources + * turned on. + */ +int qcom_edma_init(struct device *dev) +{ + int ret; + struct edma_dev *e_dev; + struct device_node *of_node; + const __be32 *prop_val; + + if (!dev || !dev->of_node) { + pr_err("EDMA: invalid %s\n", dev ? "of_node" : "dev"); + return -EINVAL; + } + + of_node = of_parse_phandle(dev->of_node, "edma-parent", 0); + if (!of_node) { + pr_info("EDMA: no phandle for eDMA found\n"); + return -ENODEV; + } + + if (!of_device_is_compatible(of_node, "qcom,pci-edma")) { + pr_info("EDMA: no compatible qcom,pci-edma found\n"); + return -ENODEV; + } + + e_dev = devm_kzalloc(dev, sizeof(*e_dev), GFP_KERNEL); + if (!e_dev) + return -ENOMEM; + + e_dev->dev = dev; + e_dev->of_node = of_node; + + prop_val = of_get_address(e_dev->of_node, 0, NULL, NULL); + if (!prop_val) { + pr_err("EDMA: missing 'reg' devicetree\n"); + return -EINVAL; + } + + e_dev->base_phys = be32_to_cpup(prop_val); + if (!e_dev->base_phys) { + pr_err("EDMA: failed to get eDMA base register address\n"); + return -EINVAL; + } + + e_dev->base_size = be32_to_cpup(&prop_val[1]); + if (!e_dev->base_size) { + pr_err("EDMA: failed to get the size of eDMA register space\n"); + return -EINVAL; + } + + e_dev->base = devm_ioremap_nocache(e_dev->dev, e_dev->base_phys, + e_dev->base_size); + if (!e_dev->base) { + pr_err("EDMA: failed to remap eDMA base register\n"); + return -EFAULT; + } + + edma_init_log(e_dev, NULL); + + e_dev->n_wr_ch = (readl_relaxed(e_dev->base + DMA_CTRL_OFF) >> + DMA_CTRL_NUM_WR_CH_SHIFT) & DMA_CTRL_NUM_CH_MASK; + EDMA_LOG(e_dev, "number of write channels: %d\n", + e_dev->n_wr_ch); + + e_dev->n_rd_ch = (readl_relaxed(e_dev->base + DMA_CTRL_OFF) >> + DMA_CTRL_NUM_RD_CH_SHIFT) & DMA_CTRL_NUM_CH_MASK; + EDMA_LOG(e_dev, "number of read channels: %d\n", + e_dev->n_rd_ch); + + e_dev->n_max_ec_ch = e_dev->n_wr_ch + e_dev->n_rd_ch; + EDMA_LOG(e_dev, "number of eDMA physical channels: %d\n", + e_dev->n_max_ec_ch); + + ret = of_property_read_u32(e_dev->of_node, "qcom,n-max-ev-ch", + &e_dev->n_max_ev_ch); + if (ret) + e_dev->n_max_ev_ch = EDMA_NUM_MAX_EV_CH; + + EDMA_LOG(e_dev, "number of eDMA virtual channels: %d\n", + e_dev->n_max_ev_ch); + + ret = of_property_read_u32(e_dev->of_node, "qcom,n-tl-init", + &e_dev->n_tl_init); + if (ret) + e_dev->n_tl_init = EDMA_NUM_TL_INIT; + + EDMA_LOG(e_dev, + "number of initial transfer and descriptor lists: %d\n", + e_dev->n_tl_init); + + ret = of_property_read_u32(e_dev->of_node, "qcom,n-tl-ele", + &e_dev->n_tl_ele); + if (ret) + e_dev->n_tl_ele = EDMA_NUM_TL_ELE; + + EDMA_LOG(e_dev, + "number of elements for transfer and descriptor list: %d\n", + e_dev->n_tl_ele); + + e_dev->ec_wr_devs = devm_kcalloc(e_dev->dev, e_dev->n_wr_ch, + sizeof(*e_dev->ec_wr_devs), GFP_KERNEL); + if (!e_dev->ec_wr_devs) + return -ENOMEM; + + e_dev->ec_rd_devs = devm_kcalloc(e_dev->dev, e_dev->n_rd_ch, + sizeof(*e_dev->ec_rd_devs), GFP_KERNEL); + if (!e_dev->ec_rd_devs) + return -ENOMEM; + + e_dev->ev_devs = devm_kcalloc(e_dev->dev, e_dev->n_max_ev_ch, + sizeof(*e_dev->ev_devs), GFP_KERNEL); + if (!e_dev->ev_devs) + return -ENOMEM; + + INIT_LIST_HEAD(&e_dev->dma_device.channels); + edma_init_channels(e_dev); + + ret = edma_init_irq(e_dev); + if (ret) + return ret; + + edma_init_dma_device(e_dev); + + ret = dma_async_device_register(&e_dev->dma_device); + if (ret) { + EDMA_ERR(e_dev, "failed to register device: %d\n", ret); + return ret; + } + + ret = of_dma_controller_register(e_dev->of_node, edma_of_dma_xlate, + e_dev); + if (ret) { + EDMA_ERR(e_dev, "failed to register controller %d\n", ret); + dma_async_device_unregister(&e_dev->dma_device); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(qcom_edma_init); + +MODULE_DESCRIPTION("QCOM PCIe eDMA driver"); +MODULE_LICENSE("GPL v2"); -- GitLab From cc2332637afb69ddfd31f7f771d4df02a4ed8cdd Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Tue, 8 Jan 2019 15:48:21 +0530 Subject: [PATCH 1175/1286] defconfig: msm: enable PCIe eDMA for sa8155 PCIe eDMA controller can be used for transferring data between system memory and peripherals. Enable PCIe eDMA for sa8155. Change-Id: I4056fd960c2ee0045179af81ecb73749eab77d4d Signed-off-by: Rama Krishna Phani A --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 1 + arch/arm64/configs/vendor/sa8155_defconfig | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index 1e84758c900f..e914641e07cc 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -470,6 +470,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y CONFIG_QCOM_GPI_DMA=y +CONFIG_QCOM_PCI_EDMA=y CONFIG_UIO=y CONFIG_UIO_MSM_SHAREDMEM=y CONFIG_STAGING=y diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index ac5b78b6e571..2cafb9a474c2 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -493,6 +493,8 @@ CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y CONFIG_QCOM_GPI_DMA=y CONFIG_QCOM_GPI_DMA_DEBUG=y +CONFIG_QCOM_PCI_EDMA=y +CONFIG_QCOM_PCI_EDMA_DEBUG=y CONFIG_UIO=y CONFIG_UIO_MSM_SHAREDMEM=y CONFIG_STAGING=y -- GitLab From f45aa3d8c18d5377614fa2c8afb028925505fd4d Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Tue, 15 Jan 2019 19:44:25 +0800 Subject: [PATCH 1176/1286] dt-bindings: cnss: update devicetree documentation Add description for qcom,cnss-qca-converged. CRs-Fixed: 2384088 Change-Id: If68d8904ad79bff5334ed8b38040522a956edd97 Signed-off-by: Yu Wang --- .../devicetree/bindings/cnss/cnss-wlan.txt | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt index 9d6351baa651..b3a41e0a8a7e 100644 --- a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt +++ b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt @@ -14,6 +14,7 @@ Required properties: - compatible: "qcom,cnss" for QCA6174 device "qcom,cnss-qca6290" for QCA6290 device "qcom,cnss-qca6390" for QCA6390 device + "qcom,cnss-qca-converged" for converged QCA devices - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications - vdd-wlan-supply: phandle to the regulator device tree node - pinctrl-names: Names corresponding to the numbered pinctrl states @@ -63,6 +64,20 @@ Optional properties: specifications, should be drived depending on products. - cnss-daemon-support: Boolean property to decide whether cnss_daemon userspace QMI client is supported. + - qcom,converged-dt: Boolean property to decide whether it supports multiple + chips. + - qcom,bus-type: U32 property to specify the bus type, is required when + 'qcom,converged-dt' being present. + - wlan_vregs: String array to decide which vregs are required, is required + when 'qcom,converged-dt' being present. + +List of chip specific sub nodes: + - chip_cfg@X: represent chip specific configurations + Each sub node has the following required properties: + - wlan_vregs: String array to decide which vregs are required, property + being present but no values means no additional vregs. + - supported-ids: U32 array to decide which device ids are supported by + sub node. Example: @@ -82,3 +97,27 @@ Example: qcom,mhi = <&mhi_wlan>; qcom,cap-tsf-gpio = <&tlmm 126 1>; }; + + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + qcom,converged-dt; + qcom,bus-type=<0>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + + chip_cfg@1 { + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + }; + }; -- GitLab From 06bda73eb5209f57b71d521051ff21fa031e6da0 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Fri, 14 Dec 2018 15:03:34 +0800 Subject: [PATCH 1177/1286] cnss2: add support for converged dt node Converge dt nodes for wlan chips those share the same PCI slot into one node. The items in this node are split into 2 parts: common and chip specific. The common part will be parsed during cnss probe, such as basic power related configuration and bus type, to power on the device and trigger pci probe; Chip specific part will be parsed during pci probe, such as chip specific power and feature related configurations. With this change, cnss2 can support different chips on one pci slot with the same image. CRs-Fixed: 2384088 Change-Id: I08c64b6dc3cc27a479ee6fd07e3c8705cc3ac43d Signed-off-by: Yu Wang --- drivers/net/wireless/cnss2/bus.c | 32 ++- drivers/net/wireless/cnss2/bus.h | 4 +- drivers/net/wireless/cnss2/main.c | 67 ++++++- drivers/net/wireless/cnss2/main.h | 25 ++- drivers/net/wireless/cnss2/pci.c | 191 +++++++++++++++--- drivers/net/wireless/cnss2/power.c | 309 +++++++++++++++++++---------- drivers/net/wireless/cnss2/qmi.c | 32 +-- 7 files changed, 490 insertions(+), 170 deletions(-) diff --git a/drivers/net/wireless/cnss2/bus.c b/drivers/net/wireless/cnss2/bus.c index 471bcfbb4527..da06a9c9e6fc 100644 --- a/drivers/net/wireless/cnss2/bus.c +++ b/drivers/net/wireless/cnss2/bus.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,17 +28,37 @@ enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev) return CNSS_BUS_NONE; } -enum cnss_dev_bus_type cnss_get_bus_type(unsigned long device_id) +enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv) { - switch (device_id) { + int ret; + struct device *dev; + u32 bus_type = CNSS_BUS_NONE; + + if (plat_priv->is_converged_dt) { + dev = &plat_priv->plat_dev->dev; + ret = of_property_read_u32(dev->of_node, "qcom,bus-type", + &bus_type); + if (!ret) + cnss_pr_dbg("Got bus type[%u] from dt\n", bus_type); + else + cnss_pr_err("No bus type for converged dt\n"); + + return bus_type; + } + + /* Get bus type according to device id if it's not converged DT */ + switch (plat_priv->device_id) { case QCA6174_DEVICE_ID: case QCA6290_DEVICE_ID: case QCA6390_DEVICE_ID: - return CNSS_BUS_PCI; + bus_type = CNSS_BUS_PCI; + break; default: - cnss_pr_err("Unknown device_id: 0x%lx\n", device_id); - return CNSS_BUS_NONE; + cnss_pr_err("Unknown device: 0x%lx\n", plat_priv->device_id); + break; } + + return bus_type; } void *cnss_bus_dev_to_bus_priv(struct device *dev) diff --git a/drivers/net/wireless/cnss2/bus.h b/drivers/net/wireless/cnss2/bus.h index 87f634f59d5a..81627bef35f8 100644 --- a/drivers/net/wireless/cnss2/bus.h +++ b/drivers/net/wireless/cnss2/bus.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -26,7 +26,7 @@ #define QCA6390_DEVICE_ID 0x1101 enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev); -enum cnss_dev_bus_type cnss_get_bus_type(unsigned long device_id); +enum cnss_dev_bus_type cnss_get_bus_type(struct cnss_plat_data *plat_priv); void *cnss_bus_dev_to_bus_priv(struct device *dev); struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev); int cnss_bus_init(struct cnss_plat_data *plat_priv); diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c index e11acf923b2c..aefe9c908de3 100644 --- a/drivers/net/wireless/cnss2/main.c +++ b/drivers/net/wireless/cnss2/main.c @@ -642,6 +642,8 @@ static int cnss_get_resources(struct cnss_plat_data *plat_priv) static void cnss_put_resources(struct cnss_plat_data *plat_priv) { + cnss_put_pinctrl(plat_priv); + cnss_put_vreg(plat_priv); } static int cnss_modem_notifier_nb(struct notifier_block *nb, @@ -759,7 +761,7 @@ static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc) } if (!plat_priv->driver_state) { - cnss_pr_dbg("Powerup is ignored\n"); + cnss_pr_dbg("subsys powerup is ignored\n"); return 0; } @@ -783,7 +785,7 @@ static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc, } if (!plat_priv->driver_state) { - cnss_pr_dbg("shutdown is ignored\n"); + cnss_pr_dbg("subsys shutdown is ignored\n"); return 0; } @@ -1293,7 +1295,8 @@ static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv) subsys_info = &plat_priv->subsys_info; ramdump_info = &plat_priv->ramdump_info; - if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic", + if (of_property_read_u32(plat_priv->dev_node, + "qcom,wlan-ramdump-dynamic", &ramdump_size) == 0) { ramdump_info->ramdump_va = dma_alloc_coherent(dev, ramdump_size, @@ -1358,14 +1361,14 @@ static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv) struct cnss_ramdump_info_v2 *info_v2; struct cnss_dump_data *dump_data; struct msm_dump_entry dump_entry; - struct device *dev = &plat_priv->plat_dev->dev; u32 ramdump_size = 0; subsys_info = &plat_priv->subsys_info; info_v2 = &plat_priv->ramdump_info_v2; dump_data = &info_v2->dump_data; - if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic", + if (of_property_read_u32(plat_priv->dev_node, + "qcom,wlan-ramdump-dynamic", &ramdump_size) == 0) info_v2->ramdump_size = ramdump_size; @@ -1625,6 +1628,7 @@ static const struct platform_device_id cnss_platform_id_table[] = { { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, }, { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, }, { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, }, + { .name = "qcaconv", .driver_data = 0}, }; static const struct of_device_id cnss_of_match_table[] = { @@ -1637,10 +1641,55 @@ static const struct of_device_id cnss_of_match_table[] = { { .compatible = "qcom,cnss-qca6390", .data = (void *)&cnss_platform_id_table[2]}, + { + .compatible = "qcom,cnss-qca-converged", + .data = (void *)&cnss_platform_id_table[3]}, { }, }; MODULE_DEVICE_TABLE(of, cnss_of_match_table); +struct cnss_fw_path { + unsigned long device_id; + const char path[CNSS_FW_PATH_MAX_LEN]; +}; + +static const struct cnss_fw_path cnss_fw_path_table[] = { + { QCA6174_DEVICE_ID, "qca6174/" }, + { QCA6290_DEVICE_ID, "qca6290/" }, + { QCA6390_DEVICE_ID, "qca6390/" }, + { 0, "" } +}; + +const char *cnss_get_fw_path(struct cnss_plat_data *plat_priv) +{ + const struct cnss_fw_path *fw_path; + const char *path; + int size = ARRAY_SIZE(cnss_fw_path_table); + + if (!plat_priv->is_converged_dt) { + path = cnss_fw_path_table[size - 1].path; + } else { + fw_path = cnss_fw_path_table; + while (fw_path->device_id && + fw_path->device_id != plat_priv->device_id) { + fw_path++; + } + + path = fw_path->path; + } + + cnss_pr_dbg("get firmware path[%s] for device[0x%lx]\n", + path, plat_priv->device_id); + return path; +} + +static inline bool +cnss_is_converged_dt(struct cnss_plat_data *plat_priv) +{ + return of_property_read_bool(plat_priv->plat_dev->dev.of_node, + "qcom,converged-dt"); +} + static int cnss_probe(struct platform_device *plat_dev) { int ret = 0; @@ -1671,10 +1720,16 @@ static int cnss_probe(struct platform_device *plat_dev) } plat_priv->plat_dev = plat_dev; + plat_priv->dev_node = NULL; plat_priv->device_id = device_id->driver_data; - plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id); + plat_priv->is_converged_dt = cnss_is_converged_dt(plat_priv); + cnss_pr_dbg("Probing platform driver from %s DT\n", + plat_priv->is_converged_dt ? "converged" : "single"); + + plat_priv->bus_type = cnss_get_bus_type(plat_priv); cnss_set_plat_priv(plat_dev, plat_priv); platform_set_drvdata(plat_dev, plat_priv); + INIT_LIST_HEAD(&plat_priv->vreg_list); cnss_init_control_params(plat_priv); diff --git a/drivers/net/wireless/cnss2/main.h b/drivers/net/wireless/cnss2/main.h index b8598f2b2a36..1fb86099a88d 100644 --- a/drivers/net/wireless/cnss2/main.h +++ b/drivers/net/wireless/cnss2/main.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,13 +34,14 @@ #define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \ CNSS_EVENT_UNINTERRUPTIBLE) +#define CNSS_FW_PATH_MAX_LEN 32 + enum cnss_dev_bus_type { CNSS_BUS_NONE = -1, CNSS_BUS_PCI, }; -struct cnss_vreg_info { - struct regulator *reg; +struct cnss_vreg_cfg { const char *name; u32 min_uv; u32 max_uv; @@ -47,11 +49,19 @@ struct cnss_vreg_info { u32 delay_us; }; +struct cnss_vreg_info { + struct list_head list; + struct regulator *reg; + struct cnss_vreg_cfg cfg; + u32 enabled; +}; + struct cnss_pinctrl_info { struct pinctrl *pinctrl; struct pinctrl_state *bootstrap_active; struct pinctrl_state *wlan_en_active; struct pinctrl_state *wlan_en_sleep; + u32 activated; }; struct cnss_subsys_info { @@ -229,7 +239,7 @@ struct cnss_plat_data { struct platform_device *plat_dev; void *bus_priv; enum cnss_dev_bus_type bus_type; - struct cnss_vreg_info *vreg_info; + struct list_head vreg_list; struct cnss_pinctrl_info pinctrl_info; struct cnss_subsys_info subsys_info; struct cnss_ramdump_info ramdump_info; @@ -267,10 +277,11 @@ struct cnss_plat_data { u32 diag_reg_read_len; u8 *diag_reg_read_buf; bool cal_done; - bool powered_on; - char firmware_name[13]; + char firmware_name[CNSS_FW_PATH_MAX_LEN]; struct completion rddm_complete; struct cnss_control_params ctrl_params; + u32 is_converged_dt; + struct device_node *dev_node; }; struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev); @@ -279,6 +290,8 @@ int cnss_driver_event_post(struct cnss_plat_data *plat_priv, u32 flags, void *data); int cnss_get_vreg(struct cnss_plat_data *plat_priv); int cnss_get_pinctrl(struct cnss_plat_data *plat_priv); +void cnss_put_vreg(struct cnss_plat_data *plat_priv); +void cnss_put_pinctrl(struct cnss_plat_data *plat_priv); int cnss_power_on_device(struct cnss_plat_data *plat_priv); void cnss_power_off_device(struct cnss_plat_data *plat_priv); int cnss_register_subsys(struct cnss_plat_data *plat_priv); @@ -286,5 +299,7 @@ void cnss_unregister_subsys(struct cnss_plat_data *plat_priv); int cnss_register_ramdump(struct cnss_plat_data *plat_priv); void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv); void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv); +const char *cnss_get_fw_path(struct cnss_plat_data *plat_priv); +int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv); #endif /* _CNSS_MAIN_H */ diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index da611a6b2cf9..c547fe944801 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -43,7 +43,6 @@ #define MHI_NODE_NAME "qcom,mhi" #define MHI_MSI_NAME "MHI" -#define MAX_M3_FILE_NAME_LENGTH 13 #define DEFAULT_M3_FILE_NAME "m3.bin" #define DEFAULT_FW_FILE_NAME "amss.bin" @@ -1495,12 +1494,14 @@ int cnss_pci_load_m3(struct cnss_pci_data *pci_priv) { struct cnss_plat_data *plat_priv = pci_priv->plat_priv; struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem; - char filename[MAX_M3_FILE_NAME_LENGTH]; + char filename[CNSS_FW_PATH_MAX_LEN]; const struct firmware *fw_entry; int ret = 0; if (!m3_mem->va && !m3_mem->size) { - snprintf(filename, sizeof(filename), DEFAULT_M3_FILE_NAME); + snprintf(filename, sizeof(filename), + "%s" DEFAULT_M3_FILE_NAME, + cnss_get_fw_path(plat_priv)); ret = request_firmware(&fw_entry, filename, &pci_priv->pci_dev->dev); @@ -2165,7 +2166,7 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv) mhi_ctrl->priv_data = pci_priv; mhi_ctrl->dev = &pci_dev->dev; - mhi_ctrl->of_node = (&plat_priv->plat_dev->dev)->of_node; + mhi_ctrl->of_node = plat_priv->dev_node; mhi_ctrl->dev_id = pci_priv->device_id; mhi_ctrl->domain = pci_domain_nr(pci_dev->bus); mhi_ctrl->bus = pci_dev->bus->number; @@ -2436,13 +2437,143 @@ void cnss_pci_stop_mhi(struct cnss_pci_data *pci_priv) cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_DEINIT); } +static int cnss_pci_get_dev_cfg_node(struct cnss_plat_data *plat_priv) +{ + struct device_node *child; + u32 id, i; + int id_n, ret; + + if (!plat_priv->is_converged_dt) { + plat_priv->dev_node = plat_priv->plat_dev->dev.of_node; + return 0; + } + + if (!plat_priv->device_id) { + cnss_pr_err("Invalid device id\n"); + return -EINVAL; + } + + for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node, + child) { + if (strcmp(child->name, "chip_cfg")) + continue; + + id_n = of_property_count_u32_elems(child, "supported-ids"); + if (id_n <= 0) { + cnss_pr_err("Device id is NOT set\n"); + return -EINVAL; + } + + for (i = 0; i < id_n; i++) { + ret = of_property_read_u32_index(child, + "supported-ids", + i, &id); + if (ret) { + cnss_pr_err("Failed to read supported ids\n"); + return -EINVAL; + } + + if (id == plat_priv->device_id) { + plat_priv->dev_node = child; + cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n", + child->name, i, id); + return 0; + } + } + } + + return -EINVAL; +} + +/* For converged dt, property 'reg' is declared in sub node, + * won't be parsed during probe. + */ +static int cnss_pci_get_smmu_cfg(struct cnss_plat_data *plat_priv) +{ + struct resource res_tmp; + struct cnss_pci_data *pci_priv; + struct resource *res; + int index; + int ret; + struct device_node *dev_node; + + dev_node = (plat_priv->dev_node ? + plat_priv->dev_node : plat_priv->plat_dev->dev.of_node); + + if (plat_priv->is_converged_dt) { + index = of_property_match_string(dev_node, "reg-names", + "smmu_iova_base"); + if (index < 0) { + ret = -ENODATA; + goto out; + } + ret = of_address_to_resource(dev_node, index, &res_tmp); + if (ret) + goto out; + + res = &res_tmp; + } else { + res = platform_get_resource_byname(plat_priv->plat_dev, + IORESOURCE_MEM, + "smmu_iova_base"); + if (!res) { + ret = -ENODATA; + goto out; + } + } + + pci_priv = plat_priv->bus_priv; + if (of_property_read_bool(dev_node, "qcom,smmu-s1-enable")) + pci_priv->smmu_s1_enable = true; + + pci_priv->smmu_iova_start = res->start; + pci_priv->smmu_iova_len = resource_size(res); + cnss_pr_dbg("smmu_iova_start: %pa, smmu_iova_len: %zu\n", + &pci_priv->smmu_iova_start, + pci_priv->smmu_iova_len); + + if (plat_priv->is_converged_dt) { + index = of_property_match_string(dev_node, "reg-names", + "smmu_iova_ipa"); + if (index < 0) { + ret = -ENODATA; + goto out; + } + + ret = of_address_to_resource(dev_node, index, &res_tmp); + if (ret) + goto out; + + res = &res_tmp; + } else { + res = platform_get_resource_byname(plat_priv->plat_dev, + IORESOURCE_MEM, + "smmu_iova_ipa"); + if (!res) { + ret = -ENODATA; + goto out; + } + } + + pci_priv->smmu_iova_ipa_start = res->start; + pci_priv->smmu_iova_ipa_len = resource_size(res); + cnss_pr_dbg("%s - smmu_iova_ipa_start: %pa, smmu_iova_ipa_len: %zu\n", + (plat_priv->is_converged_dt ? + "converged dt" : "single dt"), + &pci_priv->smmu_iova_ipa_start, + pci_priv->smmu_iova_ipa_len); + return 0; + +out: + return ret; +} + static int cnss_pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) { int ret = 0; struct cnss_pci_data *pci_priv; struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(NULL); - struct resource *res; cnss_pr_dbg("PCI is probing, vendor ID: 0x%x, device ID: 0x%x\n", id->vendor, pci_dev->device); @@ -2462,8 +2593,19 @@ static int cnss_pci_probe(struct pci_dev *pci_dev, cnss_set_pci_priv(pci_dev, pci_priv); plat_priv->device_id = pci_dev->device; plat_priv->bus_priv = pci_priv; + snprintf(plat_priv->firmware_name, sizeof(plat_priv->firmware_name), - DEFAULT_FW_FILE_NAME); + "%s" DEFAULT_FW_FILE_NAME, cnss_get_fw_path(plat_priv)); + + ret = cnss_pci_get_dev_cfg_node(plat_priv); + if (ret) { + cnss_pr_err("Failed to get device cfg node, err = %d\n", ret); + goto reset_ctx; + } + + ret = cnss_dev_specific_power_on(plat_priv); + if (ret) + goto reset_ctx; ret = cnss_register_subsys(plat_priv); if (ret) @@ -2473,30 +2615,8 @@ static int cnss_pci_probe(struct pci_dev *pci_dev, if (ret) goto unregister_subsys; - res = platform_get_resource_byname(plat_priv->plat_dev, IORESOURCE_MEM, - "smmu_iova_base"); - if (res) { - if (of_property_read_bool(plat_priv->plat_dev->dev.of_node, - "qcom,smmu-s1-enable")) - pci_priv->smmu_s1_enable = true; - - pci_priv->smmu_iova_start = res->start; - pci_priv->smmu_iova_len = resource_size(res); - cnss_pr_dbg("smmu_iova_start: %pa, smmu_iova_len: %zu\n", - &pci_priv->smmu_iova_start, - pci_priv->smmu_iova_len); - - res = platform_get_resource_byname(plat_priv->plat_dev, - IORESOURCE_MEM, - "smmu_iova_ipa"); - if (res) { - pci_priv->smmu_iova_ipa_start = res->start; - pci_priv->smmu_iova_ipa_len = resource_size(res); - cnss_pr_dbg("smmu_iova_ipa_start: %pa, smmu_iova_ipa_len: %zu\n", - &pci_priv->smmu_iova_ipa_start, - pci_priv->smmu_iova_ipa_len); - } - + ret = cnss_pci_get_smmu_cfg(plat_priv); + if (!ret) { ret = cnss_pci_init_smmu(pci_priv); if (ret) { cnss_pr_err("Failed to init SMMU, err = %d\n", ret); @@ -2658,7 +2778,16 @@ int cnss_pci_init(struct cnss_plat_data *plat_priv) goto out; } + if (!plat_priv->bus_priv) { + cnss_pr_err("Failed to probe pci driver\n"); + ret = -ENODEV; + goto deinit; + } + return 0; + +deinit: + pci_unregister_driver(&cnss_pci_driver); out: return ret; } diff --git a/drivers/net/wireless/cnss2/power.c b/drivers/net/wireless/cnss2/power.c index 71cac4e2950d..f9d590bc027c 100644 --- a/drivers/net/wireless/cnss2/power.c +++ b/drivers/net/wireless/cnss2/power.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,21 +18,21 @@ #include "main.h" #include "debug.h" -static struct cnss_vreg_info cnss_vreg_info[] = { - {NULL, "vdd-wlan-core", 1300000, 1300000, 0, 0}, - {NULL, "vdd-wlan-io", 1800000, 1800000, 0, 0}, - {NULL, "vdd-wlan-xtal-aon", 0, 0, 0, 0}, - {NULL, "vdd-wlan-xtal", 1800000, 1800000, 0, 2}, - {NULL, "vdd-wlan", 0, 0, 0, 0}, - {NULL, "vdd-wlan-ctrl1", 0, 0, 0, 0}, - {NULL, "vdd-wlan-ctrl2", 0, 0, 0, 0}, - {NULL, "vdd-wlan-sp2t", 2700000, 2700000, 0, 0}, - {NULL, "wlan-ant-switch", 2700000, 2700000, 20000, 0}, - {NULL, "wlan-soc-swreg", 1200000, 1200000, 0, 0}, - {NULL, "vdd-wlan-en", 0, 0, 0, 10}, +static struct cnss_vreg_cfg cnss_vreg_list[] = { + {"vdd-wlan-core", 1300000, 1300000, 0, 0}, + {"vdd-wlan-io", 1800000, 1800000, 0, 0}, + {"vdd-wlan-xtal-aon", 0, 0, 0, 0}, + {"vdd-wlan-xtal", 1800000, 1800000, 0, 2}, + {"vdd-wlan", 0, 0, 0, 0}, + {"vdd-wlan-ctrl1", 0, 0, 0, 0}, + {"vdd-wlan-ctrl2", 0, 0, 0, 0}, + {"vdd-wlan-sp2t", 2700000, 2700000, 0, 0}, + {"wlan-ant-switch", 2700000, 2700000, 20000, 0}, + {"wlan-soc-swreg", 1200000, 1200000, 0, 0}, + {"vdd-wlan-en", 0, 0, 0, 10}, }; -#define CNSS_VREG_INFO_SIZE ARRAY_SIZE(cnss_vreg_info) +#define CNSS_VREG_INFO_SIZE ARRAY_SIZE(cnss_vreg_list) #define MAX_PROP_SIZE 32 #define BOOTSTRAP_GPIO "qcom,enable-bootstrap-gpio" @@ -40,71 +40,114 @@ static struct cnss_vreg_info cnss_vreg_info[] = { #define WLAN_EN_GPIO "wlan-en-gpio" #define WLAN_EN_ACTIVE "wlan_en_active" #define WLAN_EN_SLEEP "wlan_en_sleep" +#define WLAN_VREGS_PROP "wlan_vregs" #define BOOTSTRAP_DELAY 1000 #define WLAN_ENABLE_DELAY 1000 +/* For converged dt node, get the required vregs from property 'wlan_vregs', + * which is string array; if the property is present but no value is set, + * means no additional wlan verg is required. + * For non-converged dt, go through all vregs in static array 'cnss_vreg_list'. + */ int cnss_get_vreg(struct cnss_plat_data *plat_priv) { int ret = 0; int i; - struct cnss_vreg_info *vreg_info; + struct cnss_vreg_info *vreg; struct device *dev; struct regulator *reg; const __be32 *prop; - char prop_name[MAX_PROP_SIZE]; - int len; + char prop_name[MAX_PROP_SIZE] = {0}; + int len, id_n; + struct device_node *dt_node; + + if (!list_empty(&plat_priv->vreg_list) && + !plat_priv->is_converged_dt) { + cnss_pr_dbg("Vregs have already been updated\n"); + return 0; + } dev = &plat_priv->plat_dev->dev; + dt_node = (plat_priv->dev_node ? plat_priv->dev_node : dev->of_node); + + if (plat_priv->is_converged_dt) { + id_n = of_property_count_strings(dt_node, WLAN_VREGS_PROP); + if (id_n <= 0) { + if (id_n == -ENODATA) { + cnss_pr_dbg("No additional vregs for: %s:%lx\n", + dt_node->name, + plat_priv->device_id); + return 0; + } - plat_priv->vreg_info = devm_kzalloc(dev, sizeof(cnss_vreg_info), - GFP_KERNEL); - if (!plat_priv->vreg_info) { - ret = -ENOMEM; - goto out; + cnss_pr_err("property %s is invalid or missed: %s:%lx\n", + WLAN_VREGS_PROP, dt_node->name, + plat_priv->device_id); + return -EINVAL; + } + } else { + id_n = CNSS_VREG_INFO_SIZE; } - memcpy(plat_priv->vreg_info, cnss_vreg_info, sizeof(cnss_vreg_info)); + for (i = 0; i < id_n; i++) { + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) { + ret = -ENOMEM; + goto out; + } + + if (plat_priv->is_converged_dt) { + ret = of_property_read_string_index(dt_node, + WLAN_VREGS_PROP, i, + &vreg->cfg.name); + if (ret) { + devm_kfree(dev, vreg); + cnss_pr_err("Failed to read vreg ids\n"); + goto out; + } + } else { + memcpy(&vreg->cfg, &cnss_vreg_list[i], + sizeof(vreg->cfg)); + } - for (i = 0; i < CNSS_VREG_INFO_SIZE; i++) { - vreg_info = &plat_priv->vreg_info[i]; - reg = devm_regulator_get_optional(dev, vreg_info->name); + reg = devm_regulator_get_optional(dev, vreg->cfg.name); if (IS_ERR(reg)) { ret = PTR_ERR(reg); - if (ret == -ENODEV) + if (ret == -ENODEV) { + devm_kfree(dev, vreg); continue; + } else if (ret == -EPROBE_DEFER) cnss_pr_info("EPROBE_DEFER for regulator: %s\n", - vreg_info->name); + vreg->cfg.name); else cnss_pr_err("Failed to get regulator %s, err = %d\n", - vreg_info->name, ret); + vreg->cfg.name, ret); + + devm_kfree(dev, vreg); goto out; } - vreg_info->reg = reg; - + vreg->reg = reg; snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-info", - vreg_info->name); - - prop = of_get_property(dev->of_node, prop_name, &len); - cnss_pr_dbg("Got regulator info, name: %s, len: %d\n", - prop_name, len); - + vreg->cfg.name); + prop = of_get_property(dt_node, prop_name, &len); if (!prop || len != (4 * sizeof(__be32))) { cnss_pr_dbg("Property %s %s, use default\n", prop_name, prop ? "invalid format" : "doesn't exist"); } else { - vreg_info->min_uv = be32_to_cpup(&prop[0]); - vreg_info->max_uv = be32_to_cpup(&prop[1]); - vreg_info->load_ua = be32_to_cpup(&prop[2]); - vreg_info->delay_us = be32_to_cpup(&prop[3]); + vreg->cfg.min_uv = be32_to_cpup(&prop[0]); + vreg->cfg.max_uv = be32_to_cpup(&prop[1]); + vreg->cfg.load_ua = be32_to_cpup(&prop[2]); + vreg->cfg.delay_us = be32_to_cpup(&prop[3]); } + list_add_tail(&vreg->list, &plat_priv->vreg_list); cnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u\n", - vreg_info->name, vreg_info->min_uv, - vreg_info->max_uv, vreg_info->load_ua, - vreg_info->delay_us); + vreg->cfg.name, vreg->cfg.min_uv, + vreg->cfg.max_uv, vreg->cfg.load_ua, + vreg->cfg.delay_us); } return 0; @@ -112,121 +155,148 @@ int cnss_get_vreg(struct cnss_plat_data *plat_priv) return ret; } +void cnss_put_vreg(struct cnss_plat_data *plat_priv) +{ + struct device *dev; + struct cnss_vreg_info *vreg; + + dev = &plat_priv->plat_dev->dev; + while (!list_empty(&plat_priv->vreg_list)) { + vreg = list_first_entry(&plat_priv->vreg_list, + struct cnss_vreg_info, list); + list_del(&vreg->list); + + if (IS_ERR_OR_NULL(vreg->reg)) + continue; + + cnss_pr_dbg("Put regulator: %s\n", vreg->cfg.name); + devm_regulator_put(vreg->reg); + devm_kfree(dev, vreg); + } +} + static int cnss_vreg_on(struct cnss_plat_data *plat_priv) { int ret = 0; - struct cnss_vreg_info *vreg_info; - int i; + struct cnss_vreg_info *vreg; if (!plat_priv) { cnss_pr_err("plat_priv is NULL!\n"); return -ENODEV; } - for (i = 0; i < CNSS_VREG_INFO_SIZE; i++) { - vreg_info = &plat_priv->vreg_info[i]; + list_for_each_entry(vreg, &plat_priv->vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg)) + continue; - if (!vreg_info->reg) + if (vreg->enabled) { + cnss_pr_dbg("Regulator %s is already enabled\n", + vreg->cfg.name); continue; + } - cnss_pr_dbg("Regulator %s is being enabled\n", vreg_info->name); + cnss_pr_dbg("Regulator %s is being enabled\n", + vreg->cfg.name); - if (vreg_info->min_uv != 0 && vreg_info->max_uv != 0) { - ret = regulator_set_voltage(vreg_info->reg, - vreg_info->min_uv, - vreg_info->max_uv); + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) { + ret = regulator_set_voltage(vreg->reg, + vreg->cfg.min_uv, + vreg->cfg.max_uv); if (ret) { cnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n", - vreg_info->name, vreg_info->min_uv, - vreg_info->max_uv, ret); + vreg->cfg.name, + vreg->cfg.min_uv, + vreg->cfg.max_uv, ret); break; } } - if (vreg_info->load_ua) { - ret = regulator_set_load(vreg_info->reg, - vreg_info->load_ua); + if (vreg->cfg.load_ua) { + ret = regulator_set_load(vreg->reg, vreg->cfg.load_ua); if (ret < 0) { cnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n", - vreg_info->name, vreg_info->load_ua, + vreg->cfg.name, vreg->cfg.load_ua, ret); break; } } - if (vreg_info->delay_us) - udelay(vreg_info->delay_us); + if (vreg->cfg.delay_us) + udelay(vreg->cfg.delay_us); - ret = regulator_enable(vreg_info->reg); + ret = regulator_enable(vreg->reg); if (ret) { cnss_pr_err("Failed to enable regulator %s, err = %d\n", - vreg_info->name, ret); + vreg->cfg.name, ret); break; } + vreg->enabled = true; } - if (ret) { - for (; i >= 0; i--) { - vreg_info = &plat_priv->vreg_info[i]; - - if (!vreg_info->reg) - continue; + if (!ret) + return 0; - regulator_disable(vreg_info->reg); - if (vreg_info->load_ua) - regulator_set_load(vreg_info->reg, 0); - if (vreg_info->min_uv != 0 && vreg_info->max_uv != 0) - regulator_set_voltage(vreg_info->reg, 0, - vreg_info->max_uv); - } + list_for_each_entry_continue_reverse(vreg, &plat_priv->vreg_list, + list) { + if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled) + continue; - return ret; + regulator_disable(vreg->reg); + if (vreg->cfg.load_ua) + regulator_set_load(vreg->reg, 0); + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) + regulator_set_voltage(vreg->reg, 0, vreg->cfg.max_uv); + vreg->enabled = false; } - return 0; + return ret; } static int cnss_vreg_off(struct cnss_plat_data *plat_priv) { int ret = 0; - struct cnss_vreg_info *vreg_info; - int i; + struct cnss_vreg_info *vreg; if (!plat_priv) { cnss_pr_err("plat_priv is NULL!\n"); return -ENODEV; } - for (i = CNSS_VREG_INFO_SIZE - 1; i >= 0; i--) { - vreg_info = &plat_priv->vreg_info[i]; + list_for_each_entry_reverse(vreg, &plat_priv->vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg)) + continue; - if (!vreg_info->reg) + if (!vreg->enabled) { + cnss_pr_dbg("Regulator %s is already disabled\n", + vreg->cfg.name); continue; + } cnss_pr_dbg("Regulator %s is being disabled\n", - vreg_info->name); + vreg->cfg.name); - ret = regulator_disable(vreg_info->reg); + ret = regulator_disable(vreg->reg); if (ret) cnss_pr_err("Failed to disable regulator %s, err = %d\n", - vreg_info->name, ret); + vreg->cfg.name, ret); - if (vreg_info->load_ua) { - ret = regulator_set_load(vreg_info->reg, 0); + if (vreg->cfg.load_ua) { + ret = regulator_set_load(vreg->reg, 0); if (ret < 0) cnss_pr_err("Failed to set load for regulator %s, err = %d\n", - vreg_info->name, ret); + vreg->cfg.name, ret); } - if (vreg_info->min_uv != 0 && vreg_info->max_uv != 0) { - ret = regulator_set_voltage(vreg_info->reg, 0, - vreg_info->max_uv); + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) { + ret = regulator_set_voltage(vreg->reg, 0, + vreg->cfg.max_uv); if (ret) cnss_pr_err("Failed to set voltage for regulator %s, err = %d\n", - vreg_info->name, ret); + vreg->cfg.name, ret); } + vreg->enabled = false; } return ret; @@ -287,6 +357,18 @@ int cnss_get_pinctrl(struct cnss_plat_data *plat_priv) return ret; } +void cnss_put_pinctrl(struct cnss_plat_data *plat_priv) +{ + struct pinctrl *pinctrl; + + pinctrl = plat_priv->pinctrl_info.pinctrl; + if (IS_ERR_OR_NULL(pinctrl)) + return; + + devm_pinctrl_put(pinctrl); + memset(&plat_priv->pinctrl_info, 0, sizeof(plat_priv->pinctrl_info)); +} + static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, bool state) { @@ -302,6 +384,11 @@ static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, pinctrl_info = &plat_priv->pinctrl_info; if (state) { + if (pinctrl_info->activated) { + cnss_pr_dbg("Pinctrl is already activated\n", ret); + goto out; + } + if (!IS_ERR_OR_NULL(pinctrl_info->bootstrap_active)) { ret = pinctrl_select_state( pinctrl_info->pinctrl, @@ -325,7 +412,13 @@ static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, } udelay(WLAN_ENABLE_DELAY); } + pinctrl_info->activated = true; } else { + if (!pinctrl_info->activated) { + cnss_pr_dbg("Pinctrl is already de-activated\n", ret); + goto out; + } + if (!IS_ERR_OR_NULL(pinctrl_info->wlan_en_sleep)) { ret = pinctrl_select_state(pinctrl_info->pinctrl, pinctrl_info->wlan_en_sleep); @@ -335,6 +428,7 @@ static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, goto out; } } + pinctrl_info->activated = false; } return 0; @@ -346,11 +440,6 @@ int cnss_power_on_device(struct cnss_plat_data *plat_priv) { int ret = 0; - if (plat_priv->powered_on) { - cnss_pr_dbg("Already powered up"); - return 0; - } - ret = cnss_vreg_on(plat_priv); if (ret) { cnss_pr_err("Failed to turn on vreg, err = %d\n", ret); @@ -362,7 +451,6 @@ int cnss_power_on_device(struct cnss_plat_data *plat_priv) cnss_pr_err("Failed to select pinctrl state, err = %d\n", ret); goto vreg_off; } - plat_priv->powered_on = true; return 0; vreg_off: @@ -373,14 +461,8 @@ int cnss_power_on_device(struct cnss_plat_data *plat_priv) void cnss_power_off_device(struct cnss_plat_data *plat_priv) { - if (!plat_priv->powered_on) { - cnss_pr_dbg("Already powered down"); - return; - } - cnss_select_pinctrl_state(plat_priv, false); cnss_vreg_off(plat_priv); - plat_priv->powered_on = false; } void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv) @@ -398,3 +480,18 @@ void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv) plat_priv->pin_result.host_pin_result = pin_status; } + +/* If it's converged dt, get device specific regulators and enable them. */ +int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv) +{ + int ret; + + if (!plat_priv->is_converged_dt) + return 0; + + ret = cnss_get_vreg(plat_priv); + if (ret) + return ret; + + return cnss_power_on_device(plat_priv); +} diff --git a/drivers/net/wireless/cnss2/qmi.c b/drivers/net/wireless/cnss2/qmi.c index 0bc3530801bb..46d6ac59382e 100644 --- a/drivers/net/wireless/cnss2/qmi.c +++ b/drivers/net/wireless/cnss2/qmi.c @@ -21,7 +21,6 @@ #define WLFW_SERVICE_INS_ID_V01 1 #define WLFW_CLIENT_ID 0x4b4e454c -#define MAX_BDF_FILE_NAME 13 #define ELF_BDF_FILE_NAME "bdwlan.elf" #define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e" #define BIN_BDF_FILE_NAME "bdwlan.bin" @@ -410,11 +409,12 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) struct wlfw_bdf_download_req_msg_v01 *req; struct wlfw_bdf_download_resp_msg_v01 *resp; struct qmi_txn txn; - char filename[MAX_BDF_FILE_NAME]; + char filename[CNSS_FW_PATH_MAX_LEN]; const struct firmware *fw_entry; const u8 *temp; unsigned int remaining; int ret = 0; + const char *fw_path; cnss_pr_dbg("Sending BDF download message, state: 0x%lx\n", plat_priv->driver_state); @@ -429,36 +429,40 @@ int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv) return -ENOMEM; } + fw_path = cnss_get_fw_path(plat_priv); switch (plat_priv->ctrl_params.bdf_type) { case CNSS_BDF_ELF: if (plat_priv->board_info.board_id == 0xFF) - snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME); + snprintf(filename, sizeof(filename), + "%s" ELF_BDF_FILE_NAME, fw_path); else if (plat_priv->board_info.board_id < 0xFF) snprintf(filename, sizeof(filename), - ELF_BDF_FILE_NAME_PREFIX "%02x", - plat_priv->board_info.board_id); + "%s" ELF_BDF_FILE_NAME_PREFIX "%02x", + fw_path, plat_priv->board_info.board_id); else snprintf(filename, sizeof(filename), - ELF_BDF_FILE_NAME_PREFIX "%04x", - plat_priv->board_info.board_id); + "%s" ELF_BDF_FILE_NAME_PREFIX "%04x", + fw_path, plat_priv->board_info.board_id); break; case CNSS_BDF_BIN: if (plat_priv->board_info.board_id == 0xFF) - snprintf(filename, sizeof(filename), BIN_BDF_FILE_NAME); + snprintf(filename, sizeof(filename), + "%s" BIN_BDF_FILE_NAME, fw_path); else if (plat_priv->board_info.board_id < 0xFF) snprintf(filename, sizeof(filename), - BIN_BDF_FILE_NAME_PREFIX "%02x", - plat_priv->board_info.board_id); + "%s" BIN_BDF_FILE_NAME_PREFIX "%02x", + fw_path, plat_priv->board_info.board_id); else snprintf(filename, sizeof(filename), - BIN_BDF_FILE_NAME_PREFIX "%04x", - plat_priv->board_info.board_id); + "%s" BIN_BDF_FILE_NAME_PREFIX "%04x", + fw_path, plat_priv->board_info.board_id); break; case CNSS_BDF_DUMMY: cnss_pr_dbg("CNSS_BDF_DUMMY is set, sending dummy BDF\n"); - snprintf(filename, sizeof(filename), DUMMY_BDF_FILE_NAME); + snprintf(filename, sizeof(filename), + "%s" DUMMY_BDF_FILE_NAME, fw_path); temp = DUMMY_BDF_FILE_NAME; - remaining = MAX_BDF_FILE_NAME; + remaining = CNSS_FW_PATH_MAX_LEN; goto bypass_bdf; default: cnss_pr_err("Invalid BDF type: %d\n", -- GitLab From 82c11482156974b8996289a6acfe8b01f906d4e5 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Tue, 25 Dec 2018 13:37:19 +0800 Subject: [PATCH 1178/1286] dts: sa8155: add converged dt node for wlan Add node 'qcom,cnss-qca-converged' and remove 'qcom,cnss'. CRs-Fixed: 2384088 Change-Id: Ie138c948e45ba4241a6a115369e04a559efb9db4 Signed-off-by: Yu Wang --- arch/arm64/boot/dts/qcom/sa8155.dtsi | 64 ++++++++++++++++++---------- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index a3bcd3085432..e01b4924fbff 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -736,35 +736,55 @@ }; }; - cnss_pcie: qcom,cnss { - compatible = "qcom,cnss"; - wlan-en-gpio = <&tlmm 169 0>; - vdd-wlan-supply = <&vreg_wlan>; + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>; + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; - reg = <0x10000000 0x10000000>, - <0x20000000 0x10000>; - reg-names = "smmu_iova_base", "smmu_iova_ipa"; - qcom,notify-modem-status; + vdd-wlan-supply = <&vreg_wlan>; + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; - qcom,wlan-rc-num = <0>; - qcom,wlan-ramdump-dynamic = <0x200000>; - qcom,msm-bus,name = "msm-cnss"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <45 512 0 0>, <1 512 0 0>, - /* Upto 200 Mbps */ - <45 512 41421 655360>, <1 512 41421 655360>, - /* Upto 400 Mbps */ - <45 512 98572 655360>, <1 512 98572 1600000>, - /* Upto 800 Mbps */ - <45 512 207108 1146880>, <1 512 207108 3124992>; - qcom,smmu-s1-enable; + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; }; + }; #include "sa8155-audio.dtsi" -- GitLab From 5c200a3b164e2fec9430dda76a12daaab41e48bb Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Wed, 23 Jan 2019 12:53:40 +0800 Subject: [PATCH 1179/1286] dt-bindings: Add regulator entry for WLAN Add regulator entry in CNSS node. They'll be used to power up WLAN chip. CRs-Fixed: 2384088 Change-Id: I6d6acaf34e5ee9b78a06f125a8622ef5f20a1276 Signed-off-by: Yu Wang --- Documentation/devicetree/bindings/cnss/cnss-wlan.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt index b3a41e0a8a7e..5b1e25f553ae 100644 --- a/Documentation/devicetree/bindings/cnss/cnss-wlan.txt +++ b/Documentation/devicetree/bindings/cnss/cnss-wlan.txt @@ -70,6 +70,10 @@ Optional properties: 'qcom,converged-dt' being present. - wlan_vregs: String array to decide which vregs are required, is required when 'qcom,converged-dt' being present. + - -supply: phandle to the regulator device tree node. + optional "supply-name" is "vdd-wlan-rfa". + - qcom,-info: Specifies configuration for supply. Should be + specified in . List of chip specific sub nodes: - chip_cfg@X: represent chip specific configurations -- GitLab From 476ff79a8e3c9941be91fbaf81880ba33ba26cc1 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Wed, 23 Jan 2019 12:55:28 +0800 Subject: [PATCH 1180/1286] cnss2: add regulators for qca6390 Add 4 fixed regulators for WLAN, they'll be used to power up qca6390. CRs-Fixed: 2384088 Change-Id: I0e81afa576d697d005976c54e86372b203d9c7a1 Signed-off-by: Yu Wang --- drivers/net/wireless/cnss2/power.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/wireless/cnss2/power.c b/drivers/net/wireless/cnss2/power.c index f9d590bc027c..d745136c4ed6 100644 --- a/drivers/net/wireless/cnss2/power.c +++ b/drivers/net/wireless/cnss2/power.c @@ -24,6 +24,10 @@ static struct cnss_vreg_cfg cnss_vreg_list[] = { {"vdd-wlan-xtal-aon", 0, 0, 0, 0}, {"vdd-wlan-xtal", 1800000, 1800000, 0, 2}, {"vdd-wlan", 0, 0, 0, 0}, + {"vdd-wlan-aon", 1055000, 1055000, 0, 0}, + {"vdd-wlan-rfa1", 1350000, 1350000, 0, 0}, + {"vdd-wlan-rfa2", 2040000, 2040000, 0, 0}, + {"vdd-wlan-rfa3", 1900000, 1900000, 0, 0}, {"vdd-wlan-ctrl1", 0, 0, 0, 0}, {"vdd-wlan-ctrl2", 0, 0, 0, 0}, {"vdd-wlan-sp2t", 2700000, 2700000, 0, 0}, -- GitLab From 590cfd18caea3fd6b93fda3ba4ef3279fc09f73c Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Tue, 22 Jan 2019 11:46:41 +0800 Subject: [PATCH 1181/1286] dts: sa8155: add qca6390 support in converged wlan dt node Add chip specific sub node(chip_cfg@1) for qca6390 in 'qcom,cnss-qca-converged'; disable 'qcom,cnss-qca6390'. CRs-Fixed: 2384088 Change-Id: I372af5cc19bad85d41a9bbd9290c19e0cf3ac907 Signed-off-by: Yu Wang --- arch/arm64/boot/dts/qcom/sa8155.dtsi | 122 ++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index e01b4924fbff..ff7866ebd8f7 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -736,6 +736,10 @@ }; }; + qcom,cnss-qca6390@a0000000 { + status = "disabled"; + }; + qcom,cnss-qca-converged { compatible = "qcom,cnss-qca-converged"; @@ -758,11 +762,18 @@ #address-cells=<1>; #size-cells=<1>; ranges = <0x10000000 0x10000000 0x10000000>, - <0x20000000 0x20000000 0x10000>; + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8150_1_s6>; + vdd-wlan-rfa1-supply = <&pm8150_2_s4>; + vdd-wlan-rfa2-supply = <&pm8150_2_s5>; + vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; @@ -783,8 +794,115 @@ qcom,smmu-s1-enable; qcom,wlan-ramdump-dynamic = <0x200000>; }; - }; + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; }; #include "sa8155-audio.dtsi" -- GitLab From c2bd32439bb14ac19ba8e427cd1ff5a022a36dee Mon Sep 17 00:00:00 2001 From: Maya Erez Date: Tue, 29 Jan 2019 10:14:43 +0200 Subject: [PATCH 1182/1286] wil6210: reset buff id in status message after completion Since DR bit and buffer id are written in different dwords of the status message, the DR bit can already be set to 1 while the buffer id is not updated yet. Resetting the buffer id in the status message will allow the driver to identify such cases and re-read the status message until the buffer id is written by HW. In case DR bit is set but buffer id is zero, need to read the status message again, until a valid id is identified. In addition to that, move the completed buffer id to the tail of the free list to prevent its immediate reuse in the upcoming refill. Change-Id: Ibdbaa1542940b975cd7669fb30548998222b359e Signed-off-by: Maya Erez --- drivers/net/wireless/ath/wil6210/debugfs.c | 2 + drivers/net/wireless/ath/wil6210/txrx_edma.c | 52 +++++++++++++++----- drivers/net/wireless/ath/wil6210/txrx_edma.h | 8 ++- drivers/net/wireless/ath/wil6210/wil6210.h | 1 + 4 files changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c index a52700a189d4..6dad1b691cb3 100644 --- a/drivers/net/wireless/ath/wil6210/debugfs.c +++ b/drivers/net/wireless/ath/wil6210/debugfs.c @@ -218,6 +218,8 @@ static void wil_print_sring(struct seq_file *s, struct wil6210_priv *wil, seq_puts(s, "???\n"); } seq_printf(s, " desc_rdy_pol = %d\n", sring->desc_rdy_pol); + seq_printf(s, " invalid_buff_id_cnt = %d\n", + sring->invalid_buff_id_cnt); if (sring->va && (sring->size <= (1 << WIL_RING_SIZE_ORDER_MAX))) { uint i; diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.c b/drivers/net/wireless/ath/wil6210/txrx_edma.c index df5b71be0a81..91d86f8e129f 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.c +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -29,6 +29,7 @@ #define WIL_EDMA_MAX_DATA_OFFSET (2) /* RX buffer size must be aligned to 4 bytes */ #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) +#define MAX_INVALID_BUFF_ID_RETRY (3) static void wil_tx_desc_unmap_edma(struct device *dev, union wil_tx_desc *desc, @@ -313,7 +314,8 @@ static int wil_init_rx_buff_arr(struct wil6210_priv *wil, struct list_head *free = &wil->rx_buff_mgmt.free; int i; - wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff), + wil->rx_buff_mgmt.buff_arr = kcalloc(size + 1, + sizeof(struct wil_rx_buff), GFP_KERNEL); if (!wil->rx_buff_mgmt.buff_arr) return -ENOMEM; @@ -322,14 +324,16 @@ static int wil_init_rx_buff_arr(struct wil6210_priv *wil, INIT_LIST_HEAD(active); INIT_LIST_HEAD(free); - /* Linkify the list */ + /* Linkify the list. + * buffer id 0 should not be used (marks invalid id). + */ buff_arr = wil->rx_buff_mgmt.buff_arr; - for (i = 0; i < size; i++) { + for (i = 1; i <= size; i++) { list_add(&buff_arr[i].list, free); buff_arr[i].id = i; } - wil->rx_buff_mgmt.size = size; + wil->rx_buff_mgmt.size = size + 1; return 0; } @@ -893,26 +897,50 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, /* Extract the buffer ID from the status message */ buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); - if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) { + + while (!buff_id) { + struct wil_rx_status_extended *s; + int invalid_buff_id_retry = 0; + + wil_dbg_txrx(wil, + "buff_id is not updated yet by HW, (swhead 0x%x)\n", + sring->swhead); + if (++invalid_buff_id_retry > MAX_INVALID_BUFF_ID_RETRY) + break; + + /* Read the status message again */ + s = (struct wil_rx_status_extended *) + (sring->va + (sring->elem_size * sring->swhead)); + *(struct wil_rx_status_extended *)msg = *s; + buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); + } + + if (unlikely(!wil_val_in_range(buff_id, 1, wil->rx_buff_mgmt.size))) { wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", buff_id, sring->swhead); + wil_rx_status_reset_buff_id(sring); wil_sring_advance_swhead(sring); + sring->invalid_buff_id_cnt++; goto again; } - wil_sring_advance_swhead(sring); - /* Extract the SKB from the rx_buff management array */ skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; if (!skb) { wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); + wil_rx_status_reset_buff_id(sring); /* Move the buffer from the active list to the free list */ - list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, - &wil->rx_buff_mgmt.free); + list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, + &wil->rx_buff_mgmt.free); + wil_sring_advance_swhead(sring); + sring->invalid_buff_id_cnt++; goto again; } + wil_rx_status_reset_buff_id(sring); + wil_sring_advance_swhead(sring); + memcpy(&pa, skb->cb, sizeof(pa)); dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); @@ -927,8 +955,8 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, sizeof(struct wil_rx_status_extended), false); /* Move the buffer from the active list to the free list */ - list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, - &wil->rx_buff_mgmt.free); + list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, + &wil->rx_buff_mgmt.free); eop = wil_rx_status_get_eop(msg); diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.h b/drivers/net/wireless/ath/wil6210/txrx_edma.h index 343516a03a1e..a055b7fb6868 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.h +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2016,2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -427,6 +427,12 @@ static inline int wil_rx_status_get_eop(void *msg) /* EoP = End of Packet */ 30, 30); } +static inline void wil_rx_status_reset_buff_id(struct wil_status_ring *s) +{ + ((struct wil_rx_status_compressed *) + (s->va + (s->elem_size * s->swhead)))->buff_id = 0; +} + static inline __le16 wil_rx_status_get_buff_id(void *msg) { return ((struct wil_rx_status_compressed *)msg)->buff_id; diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index 99a572f6a91e..2992b694c71b 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -567,6 +567,7 @@ struct wil_status_ring { bool is_rx; u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ struct wil_ring_rx_data rx_data; + u32 invalid_buff_id_cnt; /* relevant only for RX */ }; #define WIL_STA_TID_NUM (16) -- GitLab From c726e64347c3dfe2bac587e64f3ca2660123ffc6 Mon Sep 17 00:00:00 2001 From: Ghanim Fodi Date: Thu, 24 Jan 2019 21:04:20 +0200 Subject: [PATCH 1183/1286] msm: ipa: eth: enable/disable UL channel per request Besides Dl channel, UL channel need to be disabled or enabled per request. Change-Id: If0326b7c1360500e0857a3e4898f1e57f16de7da Signed-off-by: Ghanim Fodi --- drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c | 44 +++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c index 0195ad316ce2..ffe4a32c252d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_ntn.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -455,10 +455,18 @@ int ipa3_setup_uc_ntn_pipes(struct ipa_ntn_conn_in_params *in, goto fail; } + result = ipa3_enable_data_path(ipa_ep_idx_ul); + if (result) { + IPAERR("Enable data path failed res=%d pipe=%d.\n", result, + ipa_ep_idx_ul); + result = -EFAULT; + goto fail_smmu_unmap_ul; + } + if (ipa3_uc_send_ntn_setup_pipe_cmd(&in->ul, IPA_NTN_RX_DIR)) { IPAERR("fail to send cmd to uc for ul pipe\n"); result = -EFAULT; - goto fail_smmu_map_ul; + goto fail_disable_dp_ul; } ipa3_install_dflt_flt_rules(ipa_ep_idx_ul); outp->ul_uc_db_pa = IPA_UC_NTN_DB_PA_RX; @@ -477,40 +485,44 @@ int ipa3_setup_uc_ntn_pipes(struct ipa_ntn_conn_in_params *in, if (ipa3_cfg_ep(ipa_ep_idx_dl, &ep_dl->cfg)) { IPAERR("fail to setup dl pipe cfg\n"); result = -EFAULT; - goto fail_smmu_map_ul; + goto fail_disable_dp_ul; } result = ipa3_smmu_map_uc_ntn_pipes(&in->dl, true); if (result) { IPAERR("failed to map SMMU for DL %d\n", result); - goto fail_smmu_map_ul; + goto fail_disable_dp_ul; + } + + result = ipa3_enable_data_path(ipa_ep_idx_dl); + if (result) { + IPAERR("Enable data path failed res=%d pipe=%d.\n", result, + ipa_ep_idx_dl); + result = -EFAULT; + goto fail_smmu_unmap_dl; } if (ipa3_uc_send_ntn_setup_pipe_cmd(&in->dl, IPA_NTN_TX_DIR)) { IPAERR("fail to send cmd to uc for dl pipe\n"); result = -EFAULT; - goto fail_smmu_map_dl; + goto fail_disable_dp_dl; } outp->dl_uc_db_pa = IPA_UC_NTN_DB_PA_TX; ep_dl->uc_offload_state |= IPA_UC_OFFLOAD_CONNECTED; - result = ipa3_enable_data_path(ipa_ep_idx_dl); - if (result) { - IPAERR("Enable data path failed res=%d clnt=%d.\n", result, - ipa_ep_idx_dl); - result = -EFAULT; - goto fail_smmu_map_dl; - } - IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); IPADBG("client %d (ep: %d) connected\n", in->dl.client, ipa_ep_idx_dl); return 0; -fail_smmu_map_dl: +fail_disable_dp_dl: + ipa3_disable_data_path(ipa_ep_idx_dl); +fail_smmu_unmap_dl: ipa3_smmu_map_uc_ntn_pipes(&in->dl, false); -fail_smmu_map_ul: +fail_disable_dp_ul: + ipa3_disable_data_path(ipa_ep_idx_ul); +fail_smmu_unmap_ul: ipa3_smmu_map_uc_ntn_pipes(&in->ul, false); fail: IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); @@ -595,6 +607,8 @@ int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, } /* teardown the UL pipe */ + ipa3_disable_data_path(ipa_ep_idx_ul); + tear->params.ipa_pipe_number = ipa_ep_idx_ul; result = ipa3_uc_send_cmd((u32)(cmd.phys_base), IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN, -- GitLab From f95560b322e9f41af6e2b0972ef2a8a4bfea1d81 Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Tue, 29 Jan 2019 11:07:40 +0530 Subject: [PATCH 1184/1286] ARM: dts: msm: Enable hardware trigger mode for Venus GDSC for Trinket Hardware trigger mode needs to be enabled for Venus GDSC to power collapse Venus core during inter frame transition. Change-Id: I0b5d651cfbe3b1d989cbd7f4c78236180ef579f8 Signed-off-by: Diptanshu Jamgade --- arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 8d840c956e62..6e0bdbba3809 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2659,6 +2659,7 @@ }; &vcodec0_gdsc { + qcom,support-hw-trigger; status = "ok"; }; -- GitLab From 2f11926b0605ca4d66e21b1e3d824fc4cfdc7292 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 23 Jan 2019 11:54:53 +0530 Subject: [PATCH 1185/1286] clk: qcom: Add support for 24MHz and 19.2MHz for MCLK clocks for TRINKET MCLK clocks require to support 24MHz and 19.2MHz on TRINKET, so add support for the same. Change-Id: I3846276646e933c4c893b7325bf70ea2455dc890 Signed-off-by: Odelu Kukatla --- drivers/clk/qcom/gcc-trinket.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-trinket.c b/drivers/clk/qcom/gcc-trinket.c index 0ec89b65695a..fc7683a990b1 100644 --- a/drivers/clk/qcom/gcc-trinket.c +++ b/drivers/clk/qcom/gcc-trinket.c @@ -34,6 +34,10 @@ #include "vdd-level-trinket.h" #define GCC_VIDEO_MISC 0x80258 +#define GCC_CAMSS_MCLK0_CFG_RCGR 0x51004 +#define GCC_CAMSS_MCLK1_CFG_RCGR 0x51020 +#define GCC_CAMSS_MCLK2_CFG_RCGR 0x5103c +#define GCC_CAMSS_MCLK3_CFG_RCGR 0x51058 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } @@ -827,7 +831,9 @@ static struct clk_rcg2 gcc_camss_jpeg_clk_src = { }; static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { - F(64000000, P_GPLL9_OUT_MAIN, 9, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24), + F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9), { } }; @@ -4487,6 +4493,15 @@ static int gcc_trinket_probe(struct platform_device *pdev) */ regmap_update_bits(regmap, GCC_VIDEO_MISC, 0x1, 0x1); + /* + * Enable DUAL_EDGE mode for MCLK RCGs + * This is requierd to enable MND divider mode + */ + regmap_update_bits(regmap, GCC_CAMSS_MCLK0_CFG_RCGR, 0x3000, 0x2000); + regmap_update_bits(regmap, GCC_CAMSS_MCLK1_CFG_RCGR, 0x3000, 0x2000); + regmap_update_bits(regmap, GCC_CAMSS_MCLK2_CFG_RCGR, 0x3000, 0x2000); + regmap_update_bits(regmap, GCC_CAMSS_MCLK3_CFG_RCGR, 0x3000, 0x2000); + ret = qcom_cc_really_probe(pdev, &gcc_trinket_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GCC clocks\n"); -- GitLab From 2033b93b2dbb3ba8edaed8653fdd3bce4f6af792 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Tue, 29 Jan 2019 11:54:16 +0530 Subject: [PATCH 1186/1286] ARM: dts: msm: Add tpdm west for TRINKET Add tpdm west for TRINKET to support to get tpdm west hardware events. Change-Id: I1899bb56b478e6a74e5123222ad85a13a1067194 Signed-off-by: Mao Jinlong --- .../boot/dts/qcom/trinket-coresight.dtsi | 30 +++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi b/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi index 8ef7eda4f05f..712bea54a18a 100644 --- a/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -889,6 +889,15 @@ }; port@9 { + reg = <13>; + tpda_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda>; + }; + }; + + port@10 { reg = <14>; tpda_in_tpdm_pimem: endpoint { slave-mode; @@ -897,7 +906,6 @@ }; }; - }; }; @@ -919,6 +927,24 @@ }; }; + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_west_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_west>; + }; + }; + }; + tpdm_dcc: tpdm@8870000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b968>; -- GitLab From 7e128e466b641adaacfdf632ea8c99df2a679bb0 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 24 Jan 2019 14:44:18 +0530 Subject: [PATCH 1187/1286] f2fs: fix to propagate error from __get_meta_page() If caller of __get_meta_page() can handle error, let's propagate error from __get_meta_page(). Change-Id: Ie16bba4c62892a0e36d7419bcc66d740b78d3f3a Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Git-commit: 7735730d39d75e70476c1b01435b9b1f41637f0e Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git Signed-off-by: Ritesh Harjani --- fs/f2fs/checkpoint.c | 57 ++++++++++++++++++++++------- fs/f2fs/data.c | 25 +++++++++++-- fs/f2fs/f2fs.h | 8 +++- fs/f2fs/file.c | 7 +++- fs/f2fs/gc.c | 17 +++++++-- fs/f2fs/inline.c | 13 ++++++- fs/f2fs/inode.c | 13 +++++-- fs/f2fs/node.c | 87 ++++++++++++++++++++++++++++++++++---------- fs/f2fs/recovery.c | 13 ++++++- fs/f2fs/segment.c | 35 +++++++++++++----- 10 files changed, 218 insertions(+), 57 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index e086b20761f7..a4a60de30cb6 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -70,6 +70,7 @@ static struct page *__get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index, .encrypted_page = NULL, .is_meta = is_meta, }; + int err; if (unlikely(!is_meta)) fio.op_flags &= ~REQ_META; @@ -84,11 +85,10 @@ static struct page *__get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index, fio.page = page; - if (f2fs_submit_page_bio(&fio)) { - memset(page_address(page), 0, PAGE_SIZE); - f2fs_stop_checkpoint(sbi, false); - f2fs_bug_on(sbi, 1); - return page; + err = f2fs_submit_page_bio(&fio); + if (err) { + f2fs_put_page(page, 1); + return ERR_PTR(err); } lock_page(page); @@ -97,13 +97,10 @@ static struct page *__get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index, goto repeat; } - /* - * if there is any IO error when accessing device, make our filesystem - * readonly and make sure do not write checkpoint with non-uptodate - * meta page. - */ - if (unlikely(!PageUptodate(page))) - f2fs_stop_checkpoint(sbi, false); + if (unlikely(!PageUptodate(page))) { + f2fs_put_page(page, 1); + return ERR_PTR(-EIO); + } out: return page; } @@ -113,6 +110,25 @@ struct page *get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index) return __get_meta_page(sbi, index, true); } +struct page *f2fs_get_meta_page_nofail(struct f2fs_sb_info *sbi, pgoff_t index) +{ + struct page *page; + int count = 0; + +retry: + page = __get_meta_page(sbi, index, true); + if (IS_ERR(page)) { + if (PTR_ERR(page) == -EIO && + ++count <= DEFAULT_RETRY_IO_COUNT) + goto retry; + + f2fs_stop_checkpoint(sbi, false); + f2fs_bug_on(sbi, 1); + } + + return page; +} + /* for POR only */ struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index) { @@ -614,7 +630,9 @@ static int recover_orphan_inode(struct f2fs_sb_info *sbi, nid_t ino) /* truncate all the data during iput */ iput(inode); - get_node_info(sbi, ino, &ni); + err = get_node_info(sbi, ino, &ni); + if (err) + goto err_out; /* ENOMEM was fully retried in f2fs_evict_inode. */ if (ni.blk_addr != NULL_ADDR) { @@ -663,9 +681,15 @@ int recover_orphan_inodes(struct f2fs_sb_info *sbi) ra_meta_pages(sbi, start_blk, orphan_blocks, META_CP, true); for (i = 0; i < orphan_blocks; i++) { - struct page *page = get_meta_page(sbi, start_blk + i); + struct page *page; struct f2fs_orphan_block *orphan_blk; + page = get_meta_page(sbi, start_blk + i); + if (IS_ERR(page)) { + err = PTR_ERR(page); + goto out; + } + orphan_blk = (struct f2fs_orphan_block *)page_address(page); for (j = 0; j < le32_to_cpu(orphan_blk->entry_count); j++) { nid_t ino = le32_to_cpu(orphan_blk->ino[j]); @@ -756,6 +780,9 @@ static int get_checkpoint_version(struct f2fs_sb_info *sbi, block_t cp_addr, __u32 crc = 0; *cp_page = get_meta_page(sbi, cp_addr); + if (IS_ERR(*cp_page)) + return PTR_ERR(*cp_page); + *cp_block = (struct f2fs_checkpoint *)page_address(*cp_page); crc_offset = le32_to_cpu((*cp_block)->checksum_offset); @@ -881,6 +908,8 @@ int get_valid_checkpoint(struct f2fs_sb_info *sbi) unsigned char *ckpt = (unsigned char *)sbi->ckpt; cur_page = get_meta_page(sbi, cp_blk_no + i); + if (IS_ERR(cur_page)) + goto free_fail_no_cp; sit_bitmap_ptr = page_address(cur_page); memcpy(ckpt + i * blk_size, sit_bitmap_ptr, blk_size); f2fs_put_page(cur_page, 1); diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 99f0a5fb5762..7b5f0e54a1e1 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -909,6 +909,10 @@ static int __allocate_data_block(struct dnode_of_data *dn, int seg_type) if (unlikely(is_inode_flag_set(dn->inode, FI_NO_ALLOC))) return -EPERM; + err = get_node_info(sbi, dn->nid, &ni); + if (err) + return err; + dn->data_blkaddr = datablock_addr(dn->inode, dn->node_page, dn->ofs_in_node); if (dn->data_blkaddr == NEW_ADDR) @@ -918,7 +922,6 @@ static int __allocate_data_block(struct dnode_of_data *dn, int seg_type) return err; alloc: - get_node_info(sbi, dn->nid, &ni); set_summary(&sum, dn->nid, dn->ofs_in_node, ni.version); allocate_data_block(sbi, NULL, dn->data_blkaddr, &dn->data_blkaddr, @@ -1321,7 +1324,12 @@ static int f2fs_xattr_fiemap(struct inode *inode, if (!page) return -ENOMEM; - get_node_info(sbi, inode->i_ino, &ni); + err = get_node_info(sbi, inode->i_ino, &ni); + if (err) { + f2fs_put_page(page, 1); + return err; + } + phys = (__u64)blk_to_logical(inode, ni.blk_addr); offset = offsetof(struct f2fs_inode, i_addr) + @@ -1348,7 +1356,11 @@ static int f2fs_xattr_fiemap(struct inode *inode, if (!page) return -ENOMEM; - get_node_info(sbi, xnid, &ni); + err = get_node_info(sbi, xnid, &ni); + if (err) { + f2fs_put_page(page, 1); + return err; + } phys = (__u64)blk_to_logical(inode, ni.blk_addr); len = inode->i_sb->s_blocksize; @@ -1749,6 +1761,7 @@ int do_write_data_page(struct f2fs_io_info *fio) struct inode *inode = page->mapping->host; struct dnode_of_data dn; struct extent_info ei = {0,0,0}; + struct node_info ni; bool ipu_force = false; int err = 0; @@ -1817,6 +1830,12 @@ int do_write_data_page(struct f2fs_io_info *fio) fio->need_lock = LOCK_REQ; } + err = get_node_info(fio->sbi, dn.nid, &ni); + if (err) + goto out_writepage; + + fio->version = ni.version; + err = encrypt_one_page(fio); if (err) goto out_writepage; diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 99e6e07079fc..2316563e8b3b 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -510,6 +510,8 @@ enum { */ }; +#define DEFAULT_RETRY_IO_COUNT 8 /* maximum retry read IO count */ + #define F2FS_LINK_MAX 0xffffffff /* maximum link count per file */ #define MAX_DIR_RA_PAGES 4 /* maximum ra pages of dir */ @@ -1010,6 +1012,7 @@ struct f2fs_io_info { bool is_meta; /* indicate borrow meta inode mapping or not */ enum iostat_type io_type; /* io type */ struct writeback_control *io_wbc; /* writeback control */ + unsigned char version; /* version of the node */ }; #define is_read_io(rw) ((rw) == READ) @@ -2756,7 +2759,7 @@ bool available_free_memory(struct f2fs_sb_info *sbi, int type); int need_dentry_mark(struct f2fs_sb_info *sbi, nid_t nid); bool is_checkpointed_node(struct f2fs_sb_info *sbi, nid_t nid); bool need_inode_block_update(struct f2fs_sb_info *sbi, nid_t ino); -void get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni); +int get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni); pgoff_t get_next_page_offset(struct dnode_of_data *dn, pgoff_t pgofs); int get_dnode_of_data(struct dnode_of_data *dn, pgoff_t index, int mode); int truncate_inode_blocks(struct inode *inode, pgoff_t from); @@ -2781,7 +2784,7 @@ int try_to_free_nids(struct f2fs_sb_info *sbi, int nr_shrink); void recover_inline_xattr(struct inode *inode, struct page *page); int recover_xattr_data(struct inode *inode, struct page *page); int recover_inode_page(struct f2fs_sb_info *sbi, struct page *page); -void restore_node_summary(struct f2fs_sb_info *sbi, +int restore_node_summary(struct f2fs_sb_info *sbi, unsigned int segno, struct f2fs_summary_block *sum); void flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc); int build_node_manager(struct f2fs_sb_info *sbi); @@ -2855,6 +2858,7 @@ enum rw_hint io_type_to_rw_hint(struct f2fs_sb_info *sbi, enum page_type type, void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io); struct page *grab_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); +struct page *f2fs_get_meta_page_nofail(struct f2fs_sb_info *sbi, pgoff_t index); struct page *get_tmp_page(struct f2fs_sb_info *sbi, pgoff_t index); bool f2fs_is_valid_blkaddr(struct f2fs_sb_info *sbi, block_t blkaddr, int type); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index c000ea15205c..d942f3e4ac78 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -1058,7 +1058,12 @@ static int __clone_blkaddrs(struct inode *src_inode, struct inode *dst_inode, if (ret) return ret; - get_node_info(sbi, dn.nid, &ni); + ret = get_node_info(sbi, dn.nid, &ni); + if (ret) { + f2fs_put_dnode(&dn); + return ret; + } + ilen = min((pgoff_t) ADDRS_PER_PAGE(dn.node_page, dst_inode) - dn.ofs_in_node, len - i); diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index a88425815cfa..8258983cbee5 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -526,7 +526,11 @@ static int gc_node_segment(struct f2fs_sb_info *sbi, continue; } - get_node_info(sbi, nid, &ni); + if (get_node_info(sbi, nid, &ni)) { + f2fs_put_page(node_page, 1); + continue; + } + if (ni.blk_addr != start_addr + off) { f2fs_put_page(node_page, 1); continue; @@ -585,7 +589,10 @@ static bool is_alive(struct f2fs_sb_info *sbi, struct f2fs_summary *sum, if (IS_ERR(node_page)) return false; - get_node_info(sbi, nid, dni); + if (get_node_info(sbi, nid, dni)) { + f2fs_put_page(node_page, 1); + return false; + } if (sum->version != dni->version) { f2fs_msg(sbi->sb, KERN_WARNING, @@ -665,7 +672,11 @@ static int move_data_block(struct inode *inode, block_t bidx, */ f2fs_wait_on_page_writeback(page, DATA, true); - get_node_info(fio.sbi, dn.nid, &ni); + err = get_node_info(fio.sbi, dn.nid, &ni); + if (err) + goto put_out; + + set_summary(&sum, dn.nid, dn.ofs_in_node, ni.version); /* read page */ diff --git a/fs/f2fs/inline.c b/fs/f2fs/inline.c index e49f19b78f25..cc2598d2e8e0 100644 --- a/fs/f2fs/inline.c +++ b/fs/f2fs/inline.c @@ -138,6 +138,7 @@ int f2fs_convert_inline_page(struct dnode_of_data *dn, struct page *page) .encrypted_page = NULL, .io_type = FS_DATA_IO, }; + struct node_info ni; int dirty, err; if (!f2fs_exist_data(dn->inode)) @@ -146,6 +147,13 @@ int f2fs_convert_inline_page(struct dnode_of_data *dn, struct page *page) err = f2fs_reserve_block(dn, 0); if (err) return err; + err = get_node_info(fio.sbi, dn->nid, &ni); + if (err) { + f2fs_put_dnode(dn); + return err; + } + + fio.version = ni.version; if (unlikely(dn->data_blkaddr != NEW_ADDR)) { f2fs_put_dnode(dn); @@ -713,7 +721,10 @@ int f2fs_inline_data_fiemap(struct inode *inode, ilen = start + len; ilen -= start; - get_node_info(F2FS_I_SB(inode), inode->i_ino, &ni); + err = get_node_info(F2FS_I_SB(inode), inode->i_ino, &ni); + if (err) + goto out; + byteaddr = (__u64)ni.blk_addr << inode->i_sb->s_blocksize_bits; byteaddr += (char *)inline_data_addr(inode, ipage) - (char *)F2FS_INODE(ipage); diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index e436169e94c7..c297ae056b37 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -676,6 +676,7 @@ void handle_failed_inode(struct inode *inode) { struct f2fs_sb_info *sbi = F2FS_I_SB(inode); struct node_info ni; + int err; /* * clear nlink of inode in order to release resource of inode @@ -698,10 +699,16 @@ void handle_failed_inode(struct inode *inode) * so we can prevent losing this orphan when encoutering checkpoint * and following suddenly power-off. */ - get_node_info(sbi, inode->i_ino, &ni); + err = get_node_info(sbi, inode->i_ino, &ni); + if (err) { + set_sbi_flag(sbi, SBI_NEED_FSCK); + f2fs_msg(sbi->sb, KERN_WARNING, + "May loss orphan inode, run fsck to fix."); + goto out; + } if (ni.blk_addr != NULL_ADDR) { - int err = acquire_orphan_inode(sbi); + err = acquire_orphan_inode(sbi); if (err) { set_sbi_flag(sbi, SBI_NEED_FSCK); f2fs_msg(sbi->sb, KERN_WARNING, @@ -713,7 +720,7 @@ void handle_failed_inode(struct inode *inode) } else { set_inode_flag(inode, FI_FREE_NID); } - +out: f2fs_unlock_op(sbi); /* iput will drop the inode object */ diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index aeeadf4b7a8c..ae3458c8eaa7 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -121,7 +121,7 @@ static void clear_node_page_dirty(struct page *page) static struct page *get_current_nat_page(struct f2fs_sb_info *sbi, nid_t nid) { pgoff_t index = current_nat_addr(sbi, nid); - return get_meta_page(sbi, index); + return f2fs_get_meta_page_nofail(sbi, index); } static struct page *get_next_nat_page(struct f2fs_sb_info *sbi, nid_t nid) @@ -427,7 +427,7 @@ int try_to_free_nats(struct f2fs_sb_info *sbi, int nr_shrink) /* * This function always returns success */ -void get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni) +int get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni) { struct f2fs_nm_info *nm_i = NM_I(sbi); struct curseg_info *curseg = CURSEG_I(sbi, CURSEG_HOT_DATA); @@ -450,7 +450,7 @@ void get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni) ni->blk_addr = nat_get_blkaddr(e); ni->version = nat_get_version(e); up_read(&nm_i->nat_tree_lock); - return; + return 0; } memset(&ne, 0, sizeof(struct f2fs_nat_entry)); @@ -473,6 +473,9 @@ void get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni) up_read(&nm_i->nat_tree_lock); page = get_meta_page(sbi, index); + if (IS_ERR(page)) + return PTR_ERR(page); + nat_blk = (struct f2fs_nat_block *)page_address(page); ne = nat_blk->entries[nid - start_nid]; node_info_from_raw_nat(ni, &ne); @@ -480,6 +483,7 @@ void get_node_info(struct f2fs_sb_info *sbi, nid_t nid, struct node_info *ni) cache: /* cache nat entry */ cache_nat_entry(sbi, nid, &ne); + return 0; } /* @@ -729,12 +733,15 @@ int get_dnode_of_data(struct dnode_of_data *dn, pgoff_t index, int mode) return err; } -static void truncate_node(struct dnode_of_data *dn) +static int truncate_node(struct dnode_of_data *dn) { struct f2fs_sb_info *sbi = F2FS_I_SB(dn->inode); struct node_info ni; + int err; - get_node_info(sbi, dn->nid, &ni); + err = get_node_info(sbi, dn->nid, &ni); + if (err) + return err; /* Deallocate node address */ invalidate_blocks(sbi, ni.blk_addr); @@ -757,11 +764,13 @@ static void truncate_node(struct dnode_of_data *dn) dn->node_page = NULL; trace_f2fs_truncate_node(dn->inode, dn->nid, ni.blk_addr); + return 0; } static int truncate_dnode(struct dnode_of_data *dn) { struct page *page; + int err; if (dn->nid == 0) return 1; @@ -777,7 +786,9 @@ static int truncate_dnode(struct dnode_of_data *dn) dn->node_page = page; dn->ofs_in_node = 0; truncate_data_blocks(dn); - truncate_node(dn); + err = truncate_node(dn); + if (err) + return err; return 1; } @@ -842,7 +853,9 @@ static int truncate_nodes(struct dnode_of_data *dn, unsigned int nofs, if (!ofs) { /* remove current indirect node */ dn->node_page = page; - truncate_node(dn); + ret = truncate_node(dn); + if (ret) + goto out_err; freed++; } else { f2fs_put_page(page, 1); @@ -900,7 +913,9 @@ static int truncate_partial_nodes(struct dnode_of_data *dn, if (offset[idx + 1] == 0) { dn->node_page = pages[idx]; dn->nid = nid[idx]; - truncate_node(dn); + err = truncate_node(dn); + if (err) + goto fail; } else { f2fs_put_page(pages[idx], 1); } @@ -1021,6 +1036,7 @@ int truncate_xattr_node(struct inode *inode) nid_t nid = F2FS_I(inode)->i_xattr_nid; struct dnode_of_data dn; struct page *npage; + int err; if (!nid) return 0; @@ -1029,10 +1045,15 @@ int truncate_xattr_node(struct inode *inode) if (IS_ERR(npage)) return PTR_ERR(npage); + set_new_dnode(&dn, inode, NULL, npage, nid); + err = truncate_node(&dn); + if (err) { + f2fs_put_page(npage, 1); + return err; + } + f2fs_i_xnid_write(inode, 0); - set_new_dnode(&dn, inode, NULL, npage, nid); - truncate_node(&dn); return 0; } @@ -1066,7 +1087,11 @@ int remove_inode_page(struct inode *inode) inode->i_blocks != 0 && inode->i_blocks != 8); /* will put inode & node pages */ - truncate_node(&dn); + err = truncate_node(&dn); + if (err) { + f2fs_put_dnode(&dn); + return err; + } return 0; } @@ -1099,7 +1124,11 @@ struct page *new_node_page(struct dnode_of_data *dn, unsigned int ofs) goto fail; #ifdef CONFIG_F2FS_CHECK_FS - get_node_info(sbi, dn->nid, &new_ni); + err = get_node_info(sbi, dn->nid, &new_ni); + if (err) { + dec_valid_node_count(sbi, dn->inode, !ofs); + goto fail; + } f2fs_bug_on(sbi, new_ni.blk_addr != NULL_ADDR); #endif new_ni.nid = dn->nid; @@ -1147,11 +1176,14 @@ static int read_node_page(struct page *page, int op_flags) .page = page, .encrypted_page = NULL, }; + int err; if (PageUptodate(page)) return LOCKED_PAGE; - get_node_info(sbi, page->index, &ni); + err = get_node_info(sbi, page->index, &ni); + if (err) + return err; if (unlikely(ni.blk_addr == NULL_ADDR)) { ClearPageUptodate(page); @@ -1392,6 +1424,9 @@ static int __write_node_page(struct page *page, bool atomic, bool *submitted, nid = nid_of_node(page); f2fs_bug_on(sbi, page->index != nid); + if (get_node_info(sbi, nid, &ni)) + goto redirty_out; + if (wbc->for_reclaim) { if (!down_read_trylock(&sbi->node_write)) goto redirty_out; @@ -1399,8 +1434,6 @@ static int __write_node_page(struct page *page, bool atomic, bool *submitted, down_read(&sbi->node_write); } - get_node_info(sbi, nid, &ni); - /* This page is already truncated */ if (unlikely(ni.blk_addr == NULL_ADDR)) { ClearPageUptodate(page); @@ -2305,12 +2338,15 @@ int recover_xattr_data(struct inode *inode, struct page *page) struct dnode_of_data dn; struct node_info ni; struct page *xpage; + int err; if (!prev_xnid) goto recover_xnid; /* 1: invalidate the previous xattr nid */ - get_node_info(sbi, prev_xnid, &ni); + err = get_node_info(sbi, prev_xnid, &ni); + if (err) + return err; invalidate_blocks(sbi, ni.blk_addr); dec_valid_node_count(sbi, inode, false); set_node_addr(sbi, &ni, NULL_ADDR, false); @@ -2345,8 +2381,11 @@ int recover_inode_page(struct f2fs_sb_info *sbi, struct page *page) nid_t ino = ino_of_node(page); struct node_info old_ni, new_ni; struct page *ipage; + int err; - get_node_info(sbi, ino, &old_ni); + err = get_node_info(sbi, ino, &old_ni); + if (err) + return err; if (unlikely(old_ni.blk_addr != NULL_ADDR)) return -EINVAL; @@ -2400,7 +2439,7 @@ int recover_inode_page(struct f2fs_sb_info *sbi, struct page *page) return 0; } -void restore_node_summary(struct f2fs_sb_info *sbi, +int restore_node_summary(struct f2fs_sb_info *sbi, unsigned int segno, struct f2fs_summary_block *sum) { struct f2fs_node *rn; @@ -2422,6 +2461,9 @@ void restore_node_summary(struct f2fs_sb_info *sbi, for (idx = addr; idx < addr + nrpages; idx++) { struct page *page = get_tmp_page(sbi, idx); + if (IS_ERR(page)) + return PTR_ERR(page); + rn = F2FS_NODE(page); sum_entry->nid = rn->footer.nid; sum_entry->version = 0; @@ -2433,6 +2475,7 @@ void restore_node_summary(struct f2fs_sb_info *sbi, invalidate_mapping_pages(META_MAPPING(sbi), addr, addr + nrpages); } + return 0; } static void remove_nats_in_journal(struct f2fs_sb_info *sbi) @@ -2662,7 +2705,13 @@ static int __get_nat_bitmaps(struct f2fs_sb_info *sbi) nat_bits_addr = __start_cp_addr(sbi) + sbi->blocks_per_seg - nm_i->nat_bits_blocks; for (i = 0; i < nm_i->nat_bits_blocks; i++) { - struct page *page = get_meta_page(sbi, nat_bits_addr++); + struct page *page; + + page = get_meta_page(sbi, nat_bits_addr++); + if (IS_ERR(page)) { + disable_nat_bits(sbi, true); + return PTR_ERR(page); + } memcpy(nm_i->nat_bits + (i << F2FS_BLKSIZE_BITS), page_address(page), F2FS_BLKSIZE); diff --git a/fs/f2fs/recovery.c b/fs/f2fs/recovery.c index 6fc97822302e..ea2d80098452 100644 --- a/fs/f2fs/recovery.c +++ b/fs/f2fs/recovery.c @@ -259,6 +259,10 @@ static int find_fsync_dnodes(struct f2fs_sb_info *sbi, struct list_head *head, return 0; page = get_tmp_page(sbi, blkaddr); + if (IS_ERR(page)) { + err = PTR_ERR(page); + break; + } if (!is_recoverable_dnode(page)) break; @@ -473,7 +477,10 @@ static int do_recover_data(struct f2fs_sb_info *sbi, struct inode *inode, f2fs_wait_on_page_writeback(dn.node_page, NODE, true); - get_node_info(sbi, dn.nid, &ni); + err = get_node_info(sbi, dn.nid, &ni); + if (err) + goto err; + f2fs_bug_on(sbi, ni.ino != ino_of_node(page)); f2fs_bug_on(sbi, ofs_of_node(dn.node_page) != ofs_of_node(page)); @@ -576,6 +583,10 @@ static int recover_data(struct f2fs_sb_info *sbi, struct list_head *inode_list, ra_meta_pages_cond(sbi, blkaddr); page = get_tmp_page(sbi, blkaddr); + if (IS_ERR(page)) { + err = PTR_ERR(page); + break; + } if (!is_recoverable_dnode(page)) { f2fs_put_page(page, 1); diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index b5fe5fd2ddbd..a9765fa17794 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -249,7 +249,11 @@ static int __revoke_inmem_pages(struct inode *inode, err = -EAGAIN; goto next; } - get_node_info(sbi, dn.nid, &ni); + err = get_node_info(sbi, dn.nid, &ni); + if (err) { + f2fs_put_dnode(&dn); + return err; + } if (cur->old_addr == NEW_ADDR) { invalidate_blocks(sbi, dn.data_blkaddr); f2fs_update_data_blkaddr(&dn, NEW_ADDR); @@ -1966,7 +1970,7 @@ int npages_for_summary_flush(struct f2fs_sb_info *sbi, bool for_ra) */ struct page *get_sum_page(struct f2fs_sb_info *sbi, unsigned int segno) { - return get_meta_page(sbi, GET_SUM_BLOCK(sbi, segno)); + return f2fs_get_meta_page_nofail(sbi, GET_SUM_BLOCK(sbi, segno)); } void update_meta_page(struct f2fs_sb_info *sbi, void *src, block_t blk_addr) @@ -2808,11 +2812,9 @@ void write_data_page(struct dnode_of_data *dn, struct f2fs_io_info *fio) { struct f2fs_sb_info *sbi = fio->sbi; struct f2fs_summary sum; - struct node_info ni; f2fs_bug_on(sbi, dn->data_blkaddr == NULL_ADDR); - get_node_info(sbi, dn->nid, &ni); - set_summary(&sum, dn->nid, dn->ofs_in_node, ni.version); + set_summary(&sum, dn->nid, dn->ofs_in_node, fio->version); do_write_page(&sum, fio); f2fs_update_data_blkaddr(dn, fio->new_blkaddr); @@ -2978,7 +2980,7 @@ void f2fs_wait_on_block_writeback(struct inode *inode, block_t blkaddr) } } -static void read_compacted_summaries(struct f2fs_sb_info *sbi) +static int read_compacted_summaries(struct f2fs_sb_info *sbi) { struct f2fs_checkpoint *ckpt = F2FS_CKPT(sbi); struct curseg_info *seg_i; @@ -2990,6 +2992,8 @@ static void read_compacted_summaries(struct f2fs_sb_info *sbi) start = start_sum_block(sbi); page = get_meta_page(sbi, start++); + if (IS_ERR(page)) + return PTR_ERR(page); kaddr = (unsigned char *)page_address(page); /* Step 1: restore nat cache */ @@ -3030,11 +3034,14 @@ static void read_compacted_summaries(struct f2fs_sb_info *sbi) page = NULL; page = get_meta_page(sbi, start++); + if (IS_ERR(page)) + return PTR_ERR(page); kaddr = (unsigned char *)page_address(page); offset = 0; } } f2fs_put_page(page, 1); + return 0; } static int read_normal_summaries(struct f2fs_sb_info *sbi, int type) @@ -3046,6 +3053,7 @@ static int read_normal_summaries(struct f2fs_sb_info *sbi, int type) unsigned short blk_off; unsigned int segno = 0; block_t blk_addr = 0; + int err = 0; /* get segment number and block addr */ if (IS_DATASEG(type)) { @@ -3069,6 +3077,8 @@ static int read_normal_summaries(struct f2fs_sb_info *sbi, int type) } new = get_meta_page(sbi, blk_addr); + if (IS_ERR(new)) + return PTR_ERR(new); sum = (struct f2fs_summary_block *)page_address(new); if (IS_NODESEG(type)) { @@ -3080,7 +3090,9 @@ static int read_normal_summaries(struct f2fs_sb_info *sbi, int type) ns->ofs_in_node = 0; } } else { - restore_node_summary(sbi, segno, sum); + err = restore_node_summary(sbi, segno, sum); + if (err) + goto out; } } @@ -3100,8 +3112,9 @@ static int read_normal_summaries(struct f2fs_sb_info *sbi, int type) curseg->alloc_type = ckpt->alloc_type[type]; curseg->next_blkoff = blk_off; mutex_unlock(&curseg->curseg_mutex); +out: f2fs_put_page(new, 1); - return 0; + return err; } static int restore_curseg_summaries(struct f2fs_sb_info *sbi) @@ -3119,7 +3132,9 @@ static int restore_curseg_summaries(struct f2fs_sb_info *sbi) META_CP, true); /* restore for compacted data summary */ - read_compacted_summaries(sbi); + err = read_compacted_summaries(sbi); + if (err) + return err; type = CURSEG_HOT_NODE; } @@ -3248,7 +3263,7 @@ int lookup_journal_in_cursum(struct f2fs_journal *journal, int type, static struct page *get_current_sit_page(struct f2fs_sb_info *sbi, unsigned int segno) { - return get_meta_page(sbi, current_sit_addr(sbi, segno)); + return f2fs_get_meta_page_nofail(sbi, current_sit_addr(sbi, segno)); } static struct page *get_next_sit_page(struct f2fs_sb_info *sbi, -- GitLab From 35387179e28d1cb06232c92a84762eb226132996 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 24 Jan 2019 16:08:32 +0530 Subject: [PATCH 1188/1286] f2fs: fix to propagate return value of scan_nat_page() As Anatoly Trosinenko reported in bugzilla: How to reproduce: 1. Compile the 73fcb1a370c76 version of the kernel using the config attached 2. Unpack and mount the attached filesystem image as F2FS 3. The kernel will BUG() on mount (BUGs are explicitly enabled in config) [ 2.233612] F2FS-fs (sda): Found nat_bits in checkpoint [ 2.248422] ------------[ cut here ]------------ [ 2.248857] kernel BUG at fs/f2fs/node.c:1967! [ 2.249760] invalid opcode: 0000 [#1] SMP NOPTI [ 2.250219] Modules linked in: [ 2.251848] CPU: 0 PID: 944 Comm: mount Not tainted 4.17.0-rc5+ #1 [ 2.252331] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.2-1ubuntu1 04/01/2014 [ 2.253305] RIP: 0010:build_free_nids+0x337/0x3f0 [ 2.253672] RSP: 0018:ffffae7fc0857c50 EFLAGS: 00000246 [ 2.254080] RAX: 00000000ffffffff RBX: 0000000000000123 RCX: 0000000000000001 [ 2.254638] RDX: ffff9aa7063d5c00 RSI: 0000000000000122 RDI: ffff9aa705852e00 [ 2.255190] RBP: ffff9aa705852e00 R08: 0000000000000001 R09: ffff9aa7059090c0 [ 2.255719] R10: 0000000000000000 R11: 0000000000000000 R12: ffff9aa705852e00 [ 2.256242] R13: ffff9aa7063ad000 R14: ffff9aa705919000 R15: 0000000000000123 [ 2.256809] FS: 00000000023078c0(0000) GS:ffff9aa707800000(0000) knlGS:0000000000000000 [ 2.258654] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2.259153] CR2: 00000000005511ae CR3: 0000000005872000 CR4: 00000000000006f0 [ 2.259801] Call Trace: [ 2.260583] build_node_manager+0x5cd/0x600 [ 2.260963] f2fs_fill_super+0x66a/0x17c0 [ 2.261300] ? f2fs_commit_super+0xe0/0xe0 [ 2.261622] mount_bdev+0x16e/0x1a0 [ 2.261899] mount_fs+0x30/0x150 [ 2.262398] vfs_kern_mount.part.28+0x4f/0xf0 [ 2.262743] do_mount+0x5d0/0xc60 [ 2.263010] ? _copy_from_user+0x37/0x60 [ 2.263313] ? memdup_user+0x39/0x60 [ 2.263692] ksys_mount+0x7b/0xd0 [ 2.263960] __x64_sys_mount+0x1c/0x20 [ 2.264268] do_syscall_64+0x43/0xf0 [ 2.264560] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 2.265095] RIP: 0033:0x48d31a [ 2.265502] RSP: 002b:00007ffc6fe60a08 EFLAGS: 00000246 ORIG_RAX: 00000000000000a5 [ 2.266089] RAX: ffffffffffffffda RBX: 0000000000008000 RCX: 000000000048d31a [ 2.266607] RDX: 00007ffc6fe62fa5 RSI: 00007ffc6fe62f9d RDI: 00007ffc6fe62f94 [ 2.267130] RBP: 00000000023078a0 R08: 0000000000000000 R09: 0000000000000000 [ 2.267670] R10: 0000000000008000 R11: 0000000000000246 R12: 0000000000000000 [ 2.268192] R13: 0000000000000000 R14: 00007ffc6fe60c78 R15: 0000000000000000 [ 2.268767] Code: e8 5f c3 ff ff 83 c3 01 41 83 c7 01 81 fb c7 01 00 00 74 48 44 39 7d 04 76 42 48 63 c3 48 8d 04 c0 41 8b 44 06 05 83 f8 ff 75 c1 <0f> 0b 49 8b 45 50 48 8d b8 b0 00 00 00 e8 37 59 69 00 b9 01 00 [ 2.270434] RIP: build_free_nids+0x337/0x3f0 RSP: ffffae7fc0857c50 [ 2.271426] ---[ end trace ab20c06cd3c8fde4 ]--- During loading NAT entries, we will do sanity check, once the entry info is corrupted, it will cause BUG_ON directly to protect user data from being overwrited. In this case, it will be better to just return failure on mount() instead of panic, so that user can get hint from kmsg and try fsck for recovery immediately rather than after an abnormal reboot. https://bugzilla.kernel.org/show_bug.cgi?id=199769 Reported-by: Anatoly Trosinenko Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Change-Id: I05568b154fb5d02fc2f89c6a28911f45f2d4a167 Git-commit: e2374015f27fe5ee5d5c37966e2faf396cdaaa65 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git Signed-off-by: Ritesh Harjani --- fs/f2fs/f2fs.h | 2 +- fs/f2fs/node.c | 35 ++++++++++++++++++++++++----------- 2 files changed, 25 insertions(+), 12 deletions(-) diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 2316563e8b3b..61d6f14b3309 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -2776,7 +2776,7 @@ int fsync_node_pages(struct f2fs_sb_info *sbi, struct inode *inode, struct writeback_control *wbc, bool atomic); int sync_node_pages(struct f2fs_sb_info *sbi, struct writeback_control *wbc, bool do_balance, enum iostat_type io_type); -void build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount); +int build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount); bool alloc_nid(struct f2fs_sb_info *sbi, nid_t *nid); void alloc_nid_done(struct f2fs_sb_info *sbi, nid_t nid); void alloc_nid_failed(struct f2fs_sb_info *sbi, nid_t nid); diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index ae3458c8eaa7..d5377b85f481 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -2030,7 +2030,7 @@ static void remove_free_nid(struct f2fs_sb_info *sbi, nid_t nid) kmem_cache_free(free_nid_slab, i); } -static void scan_nat_page(struct f2fs_sb_info *sbi, +static int scan_nat_page(struct f2fs_sb_info *sbi, struct page *nat_page, nid_t start_nid) { struct f2fs_nm_info *nm_i = NM_I(sbi); @@ -2049,6 +2049,8 @@ static void scan_nat_page(struct f2fs_sb_info *sbi, blk_addr = le32_to_cpu(nat_blk->entries[i].block_addr); f2fs_bug_on(sbi, blk_addr == NEW_ADDR); + if (blk_addr == NEW_ADDR) + return -EINVAL; if (blk_addr == NULL_ADDR) { add_free_nid(sbi, start_nid, true, true); } else { @@ -2057,6 +2059,7 @@ static void scan_nat_page(struct f2fs_sb_info *sbi, spin_unlock(&NM_I(sbi)->nid_list_lock); } } + return 0; } static void scan_curseg_cache(struct f2fs_sb_info *sbi) @@ -2112,10 +2115,10 @@ static void scan_free_nid_bits(struct f2fs_sb_info *sbi) up_read(&nm_i->nat_tree_lock); } -static void __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) +static int __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) { struct f2fs_nm_info *nm_i = NM_I(sbi); - int i = 0; + int i = 0, ret; nid_t nid = nm_i->next_scan_nid; if (unlikely(nid >= nm_i->max_nid)) @@ -2123,17 +2126,17 @@ static void __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) /* Enough entries */ if (nm_i->nid_cnt[FREE_NID] >= NAT_ENTRY_PER_BLOCK) - return; + return 0; if (!sync && !available_free_memory(sbi, FREE_NIDS)) - return; + return 0; if (!mount) { /* try to find free nids in free_nid_bitmap */ scan_free_nid_bits(sbi); if (nm_i->nid_cnt[FREE_NID] >= NAT_ENTRY_PER_BLOCK) - return; + return 0; } /* readahead nat pages to be scanned */ @@ -2147,8 +2150,16 @@ static void __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) nm_i->nat_block_bitmap)) { struct page *page = get_current_nat_page(sbi, nid); - scan_nat_page(sbi, page, nid); + ret = scan_nat_page(sbi, page, nid); f2fs_put_page(page, 1); + + if (ret) { + up_read(&nm_i->nat_tree_lock); + f2fs_bug_on(sbi, !mount); + f2fs_msg(sbi->sb, KERN_ERR, + "NAT is corrupt, run fsck to fix it"); + return -EINVAL; + } } nid += (NAT_ENTRY_PER_BLOCK - (nid % NAT_ENTRY_PER_BLOCK)); @@ -2169,13 +2180,16 @@ static void __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) ra_meta_pages(sbi, NAT_BLOCK_OFFSET(nm_i->next_scan_nid), nm_i->ra_nid_pages, META_NAT, false); + return 0; } -void build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) +int build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) { + int ret; mutex_lock(&NM_I(sbi)->build_lock); - __build_free_nids(sbi, sync, mount); + ret = __build_free_nids(sbi, sync, mount); mutex_unlock(&NM_I(sbi)->build_lock); + return ret; } /* @@ -2874,8 +2888,7 @@ int build_node_manager(struct f2fs_sb_info *sbi) /* load free nid status from nat_bits table */ load_free_nid_bitmap(sbi); - build_free_nids(sbi, true, true); - return 0; + return build_free_nids(sbi, true, true); } void destroy_node_manager(struct f2fs_sb_info *sbi) -- GitLab From 728b4ac0b2351851bcf198b71df8e8e9f31386df Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Thu, 24 Jan 2019 16:03:14 +0530 Subject: [PATCH 1189/1286] f2fs: avoid f2fs_bug_on if f2fs_get_meta_page_nofail got EIO This patch avoids BUG_ON when f2fs_get_meta_page_nofail got EIO during xfstests/generic/475. Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Change-Id: Ie1e9ed9acb6413fec869c3f7ca8ba1f9d7e964c7 Git-commit: edc55aaf0d1712b54a3704dd58423c7e495534fe Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git Signed-off-by: Ritesh Harjani --- fs/f2fs/checkpoint.c | 10 +++++----- fs/f2fs/f2fs.h | 2 +- fs/f2fs/gc.c | 12 ++++++++++++ fs/f2fs/node.c | 31 +++++++++++++++++++++++-------- fs/f2fs/recovery.c | 2 ++ fs/f2fs/segment.c | 3 +++ 6 files changed, 46 insertions(+), 14 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index a4a60de30cb6..be87b49ec4c1 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -121,11 +121,8 @@ struct page *f2fs_get_meta_page_nofail(struct f2fs_sb_info *sbi, pgoff_t index) if (PTR_ERR(page) == -EIO && ++count <= DEFAULT_RETRY_IO_COUNT) goto retry; - f2fs_stop_checkpoint(sbi, false); - f2fs_bug_on(sbi, 1); } - return page; } @@ -1492,7 +1489,10 @@ int write_checkpoint(struct f2fs_sb_info *sbi, struct cp_control *cpc) ckpt->checkpoint_ver = cpu_to_le64(++ckpt_ver); /* write cached NAT/SIT entries to NAT/SIT area */ - flush_nat_entries(sbi, cpc); + err = flush_nat_entries(sbi, cpc); + if (err) + goto stop; + flush_sit_entries(sbi, cpc); /* unlock all the fs_lock[] in do_checkpoint() */ @@ -1501,7 +1501,7 @@ int write_checkpoint(struct f2fs_sb_info *sbi, struct cp_control *cpc) release_discard_addrs(sbi); else clear_prefree_segments(sbi, cpc); - +stop: unblock_operations(sbi); stat_inc_cp_count(sbi->stat_info); diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 61d6f14b3309..d7db68bac750 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -2786,7 +2786,7 @@ int recover_xattr_data(struct inode *inode, struct page *page); int recover_inode_page(struct f2fs_sb_info *sbi, struct page *page); int restore_node_summary(struct f2fs_sb_info *sbi, unsigned int segno, struct f2fs_summary_block *sum); -void flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc); +int flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc); int build_node_manager(struct f2fs_sb_info *sbi); void destroy_node_manager(struct f2fs_sb_info *sbi); int __init create_node_manager_caches(void); diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index 8258983cbee5..cd317c256c2a 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -998,6 +998,18 @@ static int do_garbage_collect(struct f2fs_sb_info *sbi, /* reference all summary page */ while (segno < end_segno) { sum_page = get_sum_page(sbi, segno++); + if (IS_ERR(sum_page)) { + int err = PTR_ERR(sum_page); + + end_segno = segno - 1; + for (segno = start_segno; segno < end_segno; segno++) { + sum_page = find_get_page(META_MAPPING(sbi), + GET_SUM_BLOCK(sbi, segno)); + f2fs_put_page(sum_page, 0); + f2fs_put_page(sum_page, 0); + } + return err; + } unlock_page(sum_page); } diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index d5377b85f481..42a3833092db 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -139,6 +139,8 @@ static struct page *get_next_nat_page(struct f2fs_sb_info *sbi, nid_t nid) /* get current nat block page with lock */ src_page = get_meta_page(sbi, src_off); + if (IS_ERR(src_page)) + return src_page; dst_page = grab_meta_page(sbi, dst_off); f2fs_bug_on(sbi, PageDirty(src_page)); @@ -2150,15 +2152,19 @@ static int __build_free_nids(struct f2fs_sb_info *sbi, bool sync, bool mount) nm_i->nat_block_bitmap)) { struct page *page = get_current_nat_page(sbi, nid); - ret = scan_nat_page(sbi, page, nid); - f2fs_put_page(page, 1); + if (IS_ERR(page)) { + ret = PTR_ERR(page); + } else { + ret = scan_nat_page(sbi, page, nid); + f2fs_put_page(page, 1); + } if (ret) { up_read(&nm_i->nat_tree_lock); f2fs_bug_on(sbi, !mount); f2fs_msg(sbi->sb, KERN_ERR, "NAT is corrupt, run fsck to fix it"); - return -EINVAL; + return ret; } } @@ -2582,7 +2588,7 @@ static void __update_nat_bits(struct f2fs_sb_info *sbi, nid_t start_nid, __clear_bit_le(nat_index, nm_i->full_nat_bits); } -static void __flush_nat_entry_set(struct f2fs_sb_info *sbi, +static int __flush_nat_entry_set(struct f2fs_sb_info *sbi, struct nat_entry_set *set, struct cp_control *cpc) { struct curseg_info *curseg = CURSEG_I(sbi, CURSEG_HOT_DATA); @@ -2606,6 +2612,8 @@ static void __flush_nat_entry_set(struct f2fs_sb_info *sbi, down_write(&curseg->journal_rwsem); } else { page = get_next_nat_page(sbi, start_nid); + if (IS_ERR(page)) + return PTR_ERR(page); nat_blk = page_address(page); f2fs_bug_on(sbi, !nat_blk); } @@ -2651,12 +2659,13 @@ static void __flush_nat_entry_set(struct f2fs_sb_info *sbi, radix_tree_delete(&NM_I(sbi)->nat_set_root, set->set); kmem_cache_free(nat_entry_set_slab, set); } + return 0; } /* * This function is called during the checkpointing process. */ -void flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc) +int flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc) { struct f2fs_nm_info *nm_i = NM_I(sbi); struct curseg_info *curseg = CURSEG_I(sbi, CURSEG_HOT_DATA); @@ -2666,9 +2675,10 @@ void flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc) unsigned int found; nid_t set_idx = 0; LIST_HEAD(sets); + int err = 0; if (!nm_i->dirty_nat_cnt) - return; + return 0; down_write(&nm_i->nat_tree_lock); @@ -2691,11 +2701,16 @@ void flush_nat_entries(struct f2fs_sb_info *sbi, struct cp_control *cpc) } /* flush dirty nats in nat entry set */ - list_for_each_entry_safe(set, tmp, &sets, set_list) - __flush_nat_entry_set(sbi, set, cpc); + list_for_each_entry_safe(set, tmp, &sets, set_list) { + err = __flush_nat_entry_set(sbi, set, cpc); + if (err) + break; + } up_write(&nm_i->nat_tree_lock); /* Allow dirty nats by node block allocation in write_begin */ + + return err; } static int __get_nat_bitmaps(struct f2fs_sb_info *sbi) diff --git a/fs/f2fs/recovery.c b/fs/f2fs/recovery.c index ea2d80098452..d9c1efb8a226 100644 --- a/fs/f2fs/recovery.c +++ b/fs/f2fs/recovery.c @@ -361,6 +361,8 @@ static int check_index_in_prev_nodes(struct f2fs_sb_info *sbi, } sum_page = get_sum_page(sbi, segno); + if (IS_ERR(sum_page)) + return PTR_ERR(sum_page); sum_node = (struct f2fs_summary_block *)page_address(sum_page); sum = sum_node->entries[blkoff]; f2fs_put_page(sum_page, 1); diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index a9765fa17794..f7aa25cf352b 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -2237,6 +2237,7 @@ static void change_curseg(struct f2fs_sb_info *sbi, int type) __next_free_blkoff(sbi, curseg, 0); sum_page = get_sum_page(sbi, new_segno); + f2fs_bug_on(sbi, IS_ERR(sum_page)); sum_node = (struct f2fs_summary_block *)page_address(sum_page); memcpy(curseg->sum_blk, sum_node, SUM_ENTRY_SIZE); f2fs_put_page(sum_page, 1); @@ -3663,6 +3664,8 @@ static int build_sit_entries(struct f2fs_sb_info *sbi) se = &sit_i->sentries[start]; page = get_current_sit_page(sbi, start); + if (IS_ERR(page)) + return PTR_ERR(page); sit_blk = (struct f2fs_sit_block *)page_address(page); sit = sit_blk->entries[SIT_ENTRY_OFFSET(sit_i, start)]; f2fs_put_page(page, 1); -- GitLab From b46747421d1bfe9b327e30787306923b195e64db Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 4 Oct 2018 11:15:20 +0800 Subject: [PATCH 1190/1286] f2fs: remove unneeded disable_nat_bits() Commit 7735730d39d7 ("f2fs: fix to propagate error from __get_meta_page()") added disable_nat_bits() in error path of __get_nat_bitmaps(), but it's unneeded, beause we will fail mount, we won't have chance to change nid usage status w/o nat full/empty bitmaps. Change-Id: I7c1cca1706bad8be5114d4481c4933529899034c Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Git-commit: 3b30eb19dcf1f79d1c3283da8c5f064be6175fbe Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git Signed-off-by: Ritesh Harjani --- fs/f2fs/node.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 42a3833092db..0c01b23e0d18 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -2737,10 +2737,8 @@ static int __get_nat_bitmaps(struct f2fs_sb_info *sbi) struct page *page; page = get_meta_page(sbi, nat_bits_addr++); - if (IS_ERR(page)) { - disable_nat_bits(sbi, true); + if (IS_ERR(page)) return PTR_ERR(page); - } memcpy(nm_i->nat_bits + (i << F2FS_BLKSIZE_BITS), page_address(page), F2FS_BLKSIZE); -- GitLab From 6ddd7c8ad60307217b8831a18450c17cbbb4ba9c Mon Sep 17 00:00:00 2001 From: Abhishek Choubey Date: Mon, 12 Nov 2018 11:41:50 +0530 Subject: [PATCH 1191/1286] msm: ipa3: Enable DPL for MHI pipe Add required EP config for MHI DPL and a new consumer pipe (73) and disable burst mode while starting gsi channel for the same. Change-Id: If8794639e735d0c9b1e94f9047284247ab897824 Signed-off-by: Abhishek Choubey --- .../platform/msm/ipa/ipa_clients/ipa_mhi_client.c | 2 +- drivers/platform/msm/ipa/ipa_v3/ipa_client.c | 5 +++-- drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c | 10 ++++++---- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 12 ++++++++++++ 4 files changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c index 29f0c87fdb91..3a700687059a 100644 --- a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +++ b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c @@ -64,7 +64,7 @@ #define IPA_MHI_SUSPEND_SLEEP_MAX 1100 #define IPA_MHI_MAX_UL_CHANNELS 1 -#define IPA_MHI_MAX_DL_CHANNELS 1 +#define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c index c651bc72332a..7d2e94795768 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -67,7 +67,8 @@ int ipa3_enable_data_path(u32 clnt_hdl) * if DPL client is not pulling the data * on other end from IPA hw. */ - if (ep->client == IPA_CLIENT_USB_DPL_CONS) + if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || + (ep->client == IPA_CLIENT_MHI_DPL_CONS)) holb_cfg.en = IPA_HOLB_TMR_EN; else holb_cfg.en = IPA_HOLB_TMR_DIS; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c index 3dd285ef5f88..72357d589a83 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -61,7 +61,7 @@ IPA_MHI_DBG("EXIT\n") #define IPA_MHI_MAX_UL_CHANNELS 1 -#define IPA_MHI_MAX_DL_CHANNELS 1 +#define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_HOST_ADDR_COND(addr) \ @@ -283,8 +283,10 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( params->ch_ctx_host->rbase); - if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || - params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) { + /* Burst mode is not supported on DPL pipes */ + if ((client != IPA_CLIENT_MHI_DPL_CONS) && + (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || + params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { burst_mode_enabled = true; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index c4442f14e293..442a4b4deccd 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -1657,6 +1657,18 @@ static const struct ipa_ep_configuration ipa3_ep_mapping IPA_DPS_HPS_SEQ_TYPE_INVALID, QMB_MASTER_SELECT_DDR, { 16, 5, 9, 9, IPA_EE_Q6 } }, + [IPA_4_0_MHI][IPA_CLIENT_USB_DPL_CONS] = { + true, IPA_v4_0_MHI_GROUP_DDR, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_DDR, + { 15, 7, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, + [IPA_4_0_MHI][IPA_CLIENT_MHI_DPL_CONS] = { + true, IPA_v4_0_MHI_GROUP_PCIE, + false, + IPA_DPS_HPS_SEQ_TYPE_INVALID, + QMB_MASTER_SELECT_PCIE, + { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } }, /* Only for test purpose */ [IPA_4_0_MHI][IPA_CLIENT_TEST_CONS] = { true, IPA_v4_0_GROUP_UL_DL, -- GitLab From 76dd5ee4f385a4908d96e3b1122595ea8bcb9545 Mon Sep 17 00:00:00 2001 From: Yueyi Li Date: Mon, 24 Dec 2018 07:40:07 +0000 Subject: [PATCH 1192/1286] arm64: kaslr: Reserve size of ARM64_MEMSTART_ALIGN in linear region When KASLR is enabled (CONFIG_RANDOMIZE_BASE=y), the top 4K of kernel virtual address space may be mapped to physical addresses despite being reserved for ERR_PTR values. Fix the randomization of the linear region so that we avoid mapping the last page of the virtual address space. Change-Id: I3035dbe8e64b2a31f5d56b7dc29366958adda6ce Cc: Ard Biesheuvel Signed-off-by: liyueyi [will: rewrote commit message; merged in suggestion from Ard] Signed-off-by: Will Deacon Git-commit: c8a43c18a97845e7f94ed7d181c11f41964976a2 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Vinayak Menon --- arch/arm64/mm/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index c5f095b2413c..fa8e8e160e5b 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -539,7 +539,7 @@ void __init arm64_memblock_init(void) * memory spans, randomize the linear region as well. */ if (memstart_offset_seed > 0 && range >= ARM64_MEMSTART_ALIGN) { - range = range / ARM64_MEMSTART_ALIGN + 1; + range /= ARM64_MEMSTART_ALIGN; memstart_addr -= ARM64_MEMSTART_ALIGN * ((range * memstart_offset_seed) >> 16); } -- GitLab From 939ea3572fad2bf35ba424d1ec6fa68193e2f8ed Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Tue, 29 Jan 2019 18:51:18 +0530 Subject: [PATCH 1193/1286] cpufreq: add CPUFREQ_INCOMPATIBLE event in policy notifiers Add support for CPUFREQ_INCOMPATIBLE event in policy notifiers this event is added for thermal driver to make sure thermal is the last client in applying the policy limits. Change-Id: I392e4745957829dd923f1f40201ad5c6b8ccf006 Signed-off-by: Santosh Mardi --- drivers/cpufreq/cpufreq.c | 4 ++++ include/linux/cpufreq.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 93893c3aae16..7bb10ae1a3d3 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2220,6 +2220,10 @@ static int cpufreq_set_policy(struct cpufreq_policy *policy, blocking_notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_ADJUST, new_policy); + /* adjust if necessary - hardware incompatibility */ + blocking_notifier_call_chain(&cpufreq_policy_notifier_list, + CPUFREQ_INCOMPATIBLE, new_policy); + /* * verify the cpu speed can be set within this limit, which might be * different to the first one diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 938b2a5d010c..fb519ed77374 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -437,6 +437,7 @@ static inline void cpufreq_resume(void) {} /* Policy Notifiers */ #define CPUFREQ_ADJUST (0) #define CPUFREQ_NOTIFY (1) +#define CPUFREQ_INCOMPATIBLE (6) #ifdef CONFIG_CPU_FREQ int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list); -- GitLab From 3757b946e8d38369cb6bd2b386c062bfebc2d962 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Mon, 28 Jan 2019 17:51:29 +0530 Subject: [PATCH 1194/1286] clk: qcom: cpu: Set the latch interface bypass bit for lucid PLL In lucid pll when slew is not supported the LATCH_INTERFACE_BYPASS bit of USER_CTL_U register needs to set in order to configure the PLL. Add support for the same. Change-Id: Icc3ef45367737692ba8537e1c43a3756b22fe842 Signed-off-by: Naveen Yadav --- drivers/clk/qcom/clk-cpu-sdxprairie.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-cpu-sdxprairie.c b/drivers/clk/qcom/clk-cpu-sdxprairie.c index 939605aa14ec..4c4f6e879772 100644 --- a/drivers/clk/qcom/clk-cpu-sdxprairie.c +++ b/drivers/clk/qcom/clk-cpu-sdxprairie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -750,6 +750,8 @@ static int __init cpu_clock_init(void) l_val = readl_relaxed(base + LUCID_PLL_OFF_L_VAL); } + writel_relaxed(0xC05, base + LUCID_PLL_OFF_USER_CTL_U); + cpucc_clk_init_rate = l_val * XO_RATE; regval = readl_relaxed(base); -- GitLab From ae3b6117b955172b6d6abd27bf85b1906cae5d6e Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Thu, 17 Jan 2019 18:59:50 -0800 Subject: [PATCH 1195/1286] ARM: dts: msm: Remove address from node-name for reserved-mem regions Remove address from node-names of reserved-mem regions to be able to override node properties through overlays without having to recreate a new node if the base address of the region changes. Change-Id: Ia21270ad24144be53cc22e7a65f3f693e39d3b96 Signed-off-by: Swathi Sridhar --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 40 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 22d8efd88d31..6604cefbbf00 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -595,116 +595,116 @@ #size-cells = <2>; ranges; - hyp_mem: hyp_mem@85700000 { + hyp_mem: hyp_mem { no-map; reg = <0x0 0x85700000 0x0 0x600000>; }; - xbl_aop_mem: xbl_aop_mem@85e00000 { + xbl_aop_mem: xbl_aop_mem { no-map; reg = <0x0 0x85e00000 0x0 0x140000>; }; - smem_region: smem@86000000 { + smem_region: smem { no-map; reg = <0x0 0x86000000 0x0 0x200000>; }; - removed_regions: removed_regions@86200000 { + removed_regions: removed_regions { no-map; reg = <0x0 0x86200000 0x0 0x5500000>; }; - pil_camera_mem: camera_region@8b700000 { + pil_camera_mem: camera_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8b700000 0x0 0x500000>; }; - pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 { + pil_wlan_fw_mem: pil_wlan_fw_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8bc00000 0x0 0x180000>; }; - pil_npu_mem: pil_npu_region@8bd80000 { + pil_npu_mem: pil_npu_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8bd80000 0x0 0x80000>; }; - pil_adsp_mem: pil_adsp_region@8be00000 { + pil_adsp_mem: pil_adsp_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8be00000 0x0 0x1a00000>; }; - pil_modem_mem: modem_region@8d800000 { + pil_modem_mem: modem_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8d800000 0x0 0x9600000>; }; - pil_video_mem: pil_video_region@96e00000 { + pil_video_mem: pil_video_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x96e00000 0x0 0x500000>; }; - pil_slpi_mem: pil_slpi_region@97300000 { + pil_slpi_mem: pil_slpi_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x97300000 0x0 0x1400000>; }; - pil_ipa_fw_mem: pil_ipa_fw_region@98700000 { + pil_ipa_fw_mem: pil_ipa_fw_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x98700000 0x0 0x10000>; }; - pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 { + pil_ipa_gsi_mem: pil_ipa_gsi_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x98710000 0x0 0x5000>; }; - pil_gpu_mem: pil_gpu_region@98715000 { + pil_gpu_mem: pil_gpu_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x98715000 0x0 0x2000>; }; - pil_spss_mem: pil_spss_region@98800000 { + pil_spss_mem: pil_spss_region { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x98800000 0x0 0x100000>; }; - pil_cdsp_mem: cdsp_regions@98900000 { + pil_cdsp_mem: cdsp_regions { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x98900000 0x0 0x1400000>; }; - qseecom_mem: qseecom_region@0x9e400000 { + qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; no-map; reg = <0 0x9e400000 0 0x1400000>; }; - cdsp_sec_mem: cdsp_sec_regions@0xa4c00000 { + cdsp_sec_mem: cdsp_sec_regions { compatible = "removed-dma-pool"; no-map; reg = <0x0 0xa4c00000 0x0 0x3c00000>; }; - cont_splash_memory: cont_splash_region@9c000000 { + cont_splash_memory: cont_splash_region { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "cont_splash_region"; }; - disp_rdump_memory: disp_rdump_region@9c000000 { + disp_rdump_memory: disp_rdump_region { reg = <0x0 0x9c000000 0x0 0x02400000>; label = "disp_rdump_region"; }; -- GitLab From 363838da78a00c4de8c88d679b71be9c8bc84c71 Mon Sep 17 00:00:00 2001 From: Zhen Kong Date: Tue, 29 Jan 2019 14:16:00 -0800 Subject: [PATCH 1196/1286] qseecom: check register listener syscall result If smcinvoke based register listener syscall is not supported, scm driver will return -EIO, then qseecom can change to use legacy cmd to register listener again. Change-Id: I232c900abab57e6aee735b92b4eb06d5fc66e66b Signed-off-by: Zhen Kong --- drivers/misc/qseecom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 784755659d0a..fef242ca20db 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -614,7 +614,8 @@ static int qseecom_scm_call2(uint32_t svc_id, uint32_t tz_cmd_id, qseecom.smcinvoke_support = true; smc_id = TZ_OS_REGISTER_LISTENER_SMCINVOKE_ID; ret = scm_call2(smc_id, &desc); - if (ret && ret != -EBUSY) { + if (ret == -EIO) { + /* smcinvoke is not supported */ qseecom.smcinvoke_support = false; smc_id = TZ_OS_REGISTER_LISTENER_ID; ret = scm_call2(smc_id, &desc); -- GitLab From a0bf366982d6982af213a06e2b9b3c251f06128d Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 29 Jan 2019 11:12:21 -0800 Subject: [PATCH 1197/1286] soc: qcom: pil: Extend minidump ToC logs for auxiliary entries Currently, only the main subsystem ToC is printed during SSR minidump collection, but the ToC for the auxiliary entries are not, which makes it difficult to debug issues with the ToC for the auxiliary entries. Add logging to print out the minidump ToC for a subsystem's auxiliary entries. Change-Id: Ia9eb05f8eb3b33f856f3fc999eda3697f371c456 Signed-off-by: Isaac J. Manjarres --- drivers/soc/qcom/peripheral-loader.c | 32 +++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/peripheral-loader.c b/drivers/soc/qcom/peripheral-loader.c index 594a9891f199..7611b2540b0e 100644 --- a/drivers/soc/qcom/peripheral-loader.c +++ b/drivers/soc/qcom/peripheral-loader.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -405,6 +405,33 @@ static int pil_do_minidump(struct pil_desc *desc, void *ramdump_dev) return ret; } +/** + * print_aux_minidump_tocs() - Print the ToC for an auxiliary minidump entry + * @desc: PIL descriptor for the subsystem for which minidump is collected + * + * Prints out the table of contents(ToC) for all of the auxiliary + * minidump entries for a subsystem. + */ +static void print_aux_minidump_tocs(struct pil_desc *desc) +{ + int i; + struct md_ss_toc *toc; + + for (i = 0; i < desc->num_aux_minidump_ids; i++) { + toc = desc->aux_minidump[i]; + pr_debug("Minidump : md_aux_toc->toc_init 0x%x\n", + (unsigned int)toc->md_ss_toc_init); + pr_debug("Minidump : md_aux_toc->enable_status 0x%x\n", + (unsigned int)toc->md_ss_enable_status); + pr_debug("Minidump : md_aux_toc->encryption_status 0x%x\n", + (unsigned int)toc->encryption_status); + pr_debug("Minidump : md_aux_toc->ss_region_count 0x%x\n", + (unsigned int)toc->ss_region_count); + pr_debug("Minidump : md_aux_toc->smem_regions_baseptr 0x%x\n", + (unsigned int)toc->md_ss_smem_regions_baseptr); + } +} + /** * pil_do_ramdump() - Ramdump an image * @desc: descriptor from pil_desc_init() @@ -433,6 +460,9 @@ int pil_do_ramdump(struct pil_desc *desc, pr_debug("Minidump : md_ss_toc->md_ss_smem_regions_baseptr is 0x%x\n", (unsigned int) desc->minidump_ss->md_ss_smem_regions_baseptr); + + print_aux_minidump_tocs(desc); + /** * Collect minidump if SS ToC is valid and segment table * is initialized in memory and encryption status is set. -- GitLab From 1cd2897e42855e94a675afd13775b0805a2b7d5a Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Tue, 29 Jan 2019 18:13:03 -0800 Subject: [PATCH 1198/1286] ARM: dts: msm: Add devicetree node for EUD on sdxprairie Add devicetree node to enable Embedded USB debugger (EUD) on sdxprairie target. Change-Id: I75071b3169ce80b545ae01ceea7ffb4d8a8cc52b Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 43b3cddd4b1b..554cc423b374 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -419,6 +419,20 @@ }; }; + eud: qcom,msm-eud@ff0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0xff0000 0x2000>, + <0xff2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + pil_modem: qcom,mss@4080000 { compatible = "qcom,pil-tz-generic"; reg = <0x4080000 0x100>; -- GitLab From a8334d522688458dbdf3a2bedcd40098072a7e0b Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Tue, 29 Jan 2019 18:14:50 -0800 Subject: [PATCH 1199/1286] defconfig: Enable EUD config flag on sdxprairie target Enable CONFIG_QCOM_EUD config flag to enable Embedded USB debugger (EUD) on sdxprairie target. Change-Id: I64bdb027dba49f0121f7273f64676332b6f874dc Signed-off-by: Jeevan Shriram --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 1 + arch/arm/configs/vendor/sdxprairie_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 7ba18df1ad72..572a0dfd515f 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -356,6 +356,7 @@ CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y CONFIG_QCOM_BUS_SCALING=y CONFIG_QCOM_BUS_CONFIG_RPMH=y CONFIG_QCOM_COMMAND_DB=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 1274e22471aa..362af9044679 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -349,6 +349,7 @@ CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y CONFIG_QCOM_BUS_SCALING=y CONFIG_QCOM_BUS_CONFIG_RPMH=y CONFIG_QCOM_COMMAND_DB=y -- GitLab From c9a57f9e97c9b8a25ad782785e353f957bccc9a6 Mon Sep 17 00:00:00 2001 From: Mahesh Sivasubramanian Date: Fri, 19 Jan 2018 17:12:01 -0700 Subject: [PATCH 1200/1286] clockevents: Add NULL definition for tick_broadcast on UP For uniprocessor systems, add a NULL definition of tick_broadcast to add support for tick broadcast. Change-Id: I7dc47984cb6b60c9814171888f6adbc480a1e990 Signed-off-by: Mahesh Sivasubramanian --- include/linux/clockchips.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h index 8ae9a95ebf5b..fd9e0a145843 100644 --- a/include/linux/clockchips.h +++ b/include/linux/clockchips.h @@ -199,7 +199,7 @@ extern void clockevents_suspend(void); extern void clockevents_resume(void); # ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST -# ifdef CONFIG_ARCH_HAS_TICK_BROADCAST +# if defined(CONFIG_ARCH_HAS_TICK_BROADCAST) && defined(CONFIG_SMP) extern void tick_broadcast(const struct cpumask *mask); # else # define tick_broadcast NULL -- GitLab From ccd6d0c52f9286d37521af014f9738e471da6ba4 Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Tue, 29 Jan 2019 14:09:22 -0800 Subject: [PATCH 1201/1286] Kconfig: Select GENERIC_CLOCKEVENTS_BROADCAST for sdxprairie target Enable Broadcast timer support for uniprocessor systems. When a CPU enters power collapse, the system timers are held in reset and the CPU relies on the broadcast timers to wakeup the CPU up for timer events. Change-Id: Idc3d77e5a987b0bcbee59913b23325e83a35b3e5 Signed-off-by: Jeevan Shriram --- arch/arm/mach-qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 669123485dc3..fc17977d52a2 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -91,5 +91,6 @@ config ARCH_SDXPRAIRIE select COMMON_CLK select COMMON_CLK_QCOM select QCOM_GDSC + select GENERIC_CLOCKEVENTS_BROADCAST endmenu endif -- GitLab From dfb6ffc1bd4752d84c24c0ef72437ae560500e2c Mon Sep 17 00:00:00 2001 From: Jeevan Shriram Date: Fri, 18 Jan 2019 16:41:40 -0800 Subject: [PATCH 1202/1286] ARM: dts: msm: Add support for PCIE EP devices on sdxprairie Add device tree files to support PCIE-EP devices on sdxprairie target. Change-Id: I376592de60bc55e7a68ded3fa851f61f577e1b1b Signed-off-by: Jeevan Shriram --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts | 24 +++++++++++++++++++ .../boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi | 22 +++++++++++++++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 2 +- 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index adace640973d..4fbaf45a8c36 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -220,6 +220,7 @@ endif dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ sdxprairie-cdp.dtb \ sdxprairie-mtp.dtb \ + sdxprairie-pcie-ep-mtp.dtb \ sdxprairie-cdp-256.dtb \ sdxprairie-mtp-256.dtb \ sdxprairie-mtp-aqc.dtb diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts new file mode 100644 index 000000000000..8071be5a1df1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-pcie-ep-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE PCIE-EP MTP"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x6010008 0x0>; +}; + + diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi new file mode 100644 index 000000000000..4f853cca33c7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +&qnand_1 { + status = "ok"; +}; + +&restart_pshold { + qcom,force-warm-reboot; +}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 43b3cddd4b1b..984fbd1edfce 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -243,7 +243,7 @@ clock-frequency = <32768>; }; - restart@c264000 { + restart_pshold: restart@c264000 { compatible = "qcom,pshold"; reg = <0xc264000 0x4>, <0x1fd3000 0x4>; -- GitLab From 537f6da1b66467fb50f79fce1a968e51e8da4972 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 29 Jan 2019 10:14:16 +0530 Subject: [PATCH 1203/1286] sched/fair: Fix schedtune boosted tasks placement issues The current code starts the CPU search with max capacity cluster for schedtune boosted tasks. If any of the CPU in this cluster can accommodate the task without exceeding its original capacity, the search is not extended to other clusters. This approach results in sub-optimal performance on tri-cluster systems with 1 CPU in the max capacity cluster. The max capacity CPU is packed with several tasks while the other mid capacity CPUs are idle. Fix this issue by starting the CPU search with mid capacity cluster as long as the task fits. The search is also expanded to the max capacity cluster and the best CPU is selected among the iterated CPUs. The best CPU is either an idle CPU in the shallowest c-state or CPU with maximum spare capacity when all the iterated CPUs are busy. The energy evaluation is also skipped for boosted tasks to maximize the performance. While at it, extend the sched_task_util trace point to print if the task is schedtune boosted or not. Change-Id: Iefb29e9d32f1c414bd6af31d66306f04c6f57f9c Signed-off-by: Pavankumar Kondeti --- include/trace/events/sched.h | 12 ++++++++---- kernel/sched/fair.c | 29 +++++++++++++++++++---------- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h index 5bc0cbe93260..c5032fcca561 100644 --- a/include/trace/events/sched.h +++ b/include/trace/events/sched.h @@ -1449,10 +1449,11 @@ TRACE_EVENT(sched_task_util, TP_PROTO(struct task_struct *p, int next_cpu, int backup_cpu, int target_cpu, bool sync, bool need_idle, int fastpath, - bool placement_boost, int rtg_cpu, u64 start_t), + bool placement_boost, int rtg_cpu, u64 start_t, + bool stune_boosted), TP_ARGS(p, next_cpu, backup_cpu, target_cpu, sync, need_idle, fastpath, - placement_boost, rtg_cpu, start_t), + placement_boost, rtg_cpu, start_t, stune_boosted), TP_STRUCT__entry( __field(int, pid ) @@ -1468,6 +1469,7 @@ TRACE_EVENT(sched_task_util, __field(int, placement_boost ) __field(int, rtg_cpu ) __field(u64, latency ) + __field(bool, stune_boosted ) ), TP_fast_assign( @@ -1484,13 +1486,15 @@ TRACE_EVENT(sched_task_util, __entry->placement_boost = placement_boost; __entry->rtg_cpu = rtg_cpu; __entry->latency = (sched_clock() - start_t); + __entry->stune_boosted = stune_boosted; ), - TP_printk("pid=%d comm=%s util=%lu prev_cpu=%d next_cpu=%d backup_cpu=%d target_cpu=%d sync=%d need_idle=%d fastpath=%d placement_boost=%d rtg_cpu=%d latency=%llu", + TP_printk("pid=%d comm=%s util=%lu prev_cpu=%d next_cpu=%d backup_cpu=%d target_cpu=%d sync=%d need_idle=%d fastpath=%d placement_boost=%d rtg_cpu=%d latency=%llu stune_boosted=%d", __entry->pid, __entry->comm, __entry->util, __entry->prev_cpu, __entry->next_cpu, __entry->backup_cpu, __entry->target_cpu, __entry->sync, __entry->need_idle, __entry->fastpath, - __entry->placement_boost, __entry->rtg_cpu, __entry->latency) + __entry->placement_boost, __entry->rtg_cpu, __entry->latency, + __entry->stune_boosted) ) /* diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index a6d2b21a0796..9bb21314d549 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7290,11 +7290,11 @@ struct find_best_target_env { static bool is_packing_eligible(struct task_struct *p, int target_cpu, struct find_best_target_env *fbt_env, unsigned int target_cpus_count, - int best_idle_cstate) + int best_idle_cstate, bool boosted) { unsigned long tutil, estimated_capacity; - if (task_placement_boost_enabled(p) || fbt_env->need_idle) + if (task_placement_boost_enabled(p) || fbt_env->need_idle || boosted) return false; if (best_idle_cstate == -1) @@ -7325,8 +7325,12 @@ static int start_cpu(struct task_struct *p, bool boosted, struct root_domain *rd = cpu_rq(smp_processor_id())->rd; int start_cpu = -1; - if (boosted) + if (boosted) { + if (rd->mid_cap_orig_cpu != -1 && + task_fits_max(p, rd->mid_cap_orig_cpu)) + return rd->mid_cap_orig_cpu; return rd->max_cap_orig_cpu; + } /* A task always fits on its rtg_target */ if (rtg_target) { @@ -7704,7 +7708,7 @@ static inline int find_best_target(struct task_struct *p, int *backup_cpu, * next cluster if they are higher in capacity. If we are * not in any kind of boost, we break. */ - if (!prefer_idle && + if (!prefer_idle && !boosted && (target_cpu != -1 || best_idle_cpu != -1) && (fbt_env->placement_boost == SCHED_BOOST_NONE || sched_boost() != FULL_THROTTLE_BOOST || @@ -7715,9 +7719,12 @@ static inline int find_best_target(struct task_struct *p, int *backup_cpu, /* * if we are in prefer_idle and have found an idle cpu, * break from searching more groups based on the stune.boost and - * group cpu capacity. + * group cpu capacity. For !prefer_idle && boosted case, don't + * iterate lower capacity CPUs unless the task can't be + * accommodated in the higher capacity CPUs. */ - if (prefer_idle && best_idle_cpu != -1) { + if ((prefer_idle && best_idle_cpu != -1) || + (boosted && (best_idle_cpu != -1 || target_cpu != -1))) { if (boosted) { if (!next_group_higher_cap) break; @@ -7730,7 +7737,8 @@ static inline int find_best_target(struct task_struct *p, int *backup_cpu, } while (sg = sg->next, sg != sd->groups); if (best_idle_cpu != -1 && !is_packing_eligible(p, target_cpu, fbt_env, - active_cpus_count, best_idle_cstate)) { + active_cpus_count, best_idle_cstate, + boosted)) { target_cpu = best_idle_cpu; best_idle_cpu = -1; } @@ -8036,6 +8044,7 @@ static int find_energy_efficient_cpu(struct sched_domain *sd, int placement_boost = task_boost_policy(p); u64 start_t = 0; int next_cpu = -1, backup_cpu = -1; + int boosted = (schedtune_task_boost(p) > 0); fbt_env.fastpath = 0; @@ -8090,7 +8099,6 @@ static int find_energy_efficient_cpu(struct sched_domain *sd, break; } } else { - int boosted = (schedtune_task_boost(p) > 0); int prefer_idle; /* @@ -8122,7 +8130,7 @@ static int find_energy_efficient_cpu(struct sched_domain *sd, p->state == TASK_WAKING) delta = task_util(p); #endif - if (task_placement_boost_enabled(p) || need_idle || + if (task_placement_boost_enabled(p) || need_idle || boosted || (rtg_target && (!cpumask_test_cpu(prev_cpu, rtg_target) || cpumask_test_cpu(target_cpu, rtg_target))) || __cpu_overutilized(prev_cpu, delta) || @@ -8159,7 +8167,8 @@ static int find_energy_efficient_cpu(struct sched_domain *sd, trace_sched_task_util(p, next_cpu, backup_cpu, target_cpu, sync, need_idle, fbt_env.fastpath, placement_boost, - rtg_target ? cpumask_first(rtg_target) : -1, start_t); + rtg_target ? cpumask_first(rtg_target) : -1, start_t, + boosted); return target_cpu; } -- GitLab From 75f0a9b1f1ca58d6163035dd56c1ad11b3b10d77 Mon Sep 17 00:00:00 2001 From: Rama Krishna Phani A Date: Sun, 11 Nov 2018 21:30:35 +0530 Subject: [PATCH 1204/1286] msm: ep_pcie: add eDMA support for PCIe EP driver Add support to initialize eDMA driver during EP PCIe probe for eDMA supported targets. Unmask eDMA interrupt in PCIe global IRQ. Add support to bypass SMMU for PCIe eDMA. Change-Id: I68a73a0f8c2c2f9f14e17168e2bf5e04f6de1a15 Signed-off-by: Rama Krishna Phani A Signed-off-by: Chandra Devireddy --- .../devicetree/bindings/pci/msm_ep_pcie.txt | 1 + drivers/platform/msm/ep_pcie/ep_pcie_com.h | 7 ++ drivers/platform/msm/ep_pcie/ep_pcie_core.c | 78 ++++++++++++++++++- include/linux/msm_ep_pcie.h | 3 +- 4 files changed, 86 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt index 3e265a1ea80d..be84da0301d0 100644 --- a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt @@ -53,6 +53,7 @@ Optional Properties: 1, 2 or 3. - qcom,pcie-active-config: boolean type; active configuration of PCIe addressing. + - qcom,pcie-edma: boolean type; edma usage for PCIe. - qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated. - qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq. - qcom,pcie-perst-enum: Link enumeration will be triggered by PERST diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index 9a5877e583c5..46530a900055 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -23,6 +23,7 @@ #include #include #include +#include #define PCIE20_PARF_SYS_CTRL 0x00 #define PCIE20_PARF_DB_CTRL 0x10 @@ -56,6 +57,8 @@ #define PCIE20_PARF_ATU_BASE_ADDR 0x634 #define PCIE20_PARF_ATU_BASE_ADDR_HI 0x638 #define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_EDMA_BASE_ADDR 0x64C +#define PCIE20_PARF_EDMA_BASE_ADDR_HI 0x650 #define PCIE20_ELBI_VERSION 0x00 #define PCIE20_ELBI_SYS_CTRL 0x04 @@ -229,6 +232,7 @@ enum ep_pcie_res { EP_PCIE_RES_DM_CORE, EP_PCIE_RES_ELBI, EP_PCIE_RES_IATU, + EP_PCIE_RES_EDMA, EP_PCIE_MAX_RES, }; @@ -318,6 +322,7 @@ struct ep_pcie_dev_t { void __iomem *mmio; void __iomem *msi; void __iomem *dm_core; + void __iomem *edma; void __iomem *elbi; void __iomem *iatu; @@ -327,6 +332,7 @@ struct ep_pcie_dev_t { bool active_config; bool aggregated_irq; bool mhi_a7_irq; + bool pcie_edma; u32 dbi_base_reg; u32 slv_space_reg; u32 phy_status_reg; @@ -418,5 +424,6 @@ extern bool ep_pcie_phy_is_ready(struct ep_pcie_dev_t *dev); extern void ep_pcie_reg_dump(struct ep_pcie_dev_t *dev, u32 sel, bool linkdown); extern void ep_pcie_debugfs_init(struct ep_pcie_dev_t *ep_dev); extern void ep_pcie_debugfs_exit(void); +extern int qcom_edma_init(struct device *dev); #endif diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 3a9e16816ac3..e9ec55e62950 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -35,6 +35,9 @@ #include #include "ep_pcie_com.h" +#include +#include +#include /* debug mask sys interface */ static int ep_pcie_debug_mask; @@ -92,6 +95,7 @@ static const struct ep_pcie_res_info_t ep_pcie_res_info[EP_PCIE_MAX_RES] = { {"dm_core", NULL, NULL}, {"elbi", NULL, NULL}, {"iatu", NULL, NULL}, + {"edma", NULL, NULL}, }; static const struct ep_pcie_irq_info_t ep_pcie_irq_info[EP_PCIE_MAX_IRQ] = { @@ -597,6 +601,25 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) "PCIe V%d: LSB of ATU base:0x%x\n", dev->rev, readl_relaxed(dev->parf + PCIE20_PARF_ATU_BASE_ADDR)); + if (dev->pcie_edma) { + struct resource *edma = + dev->res[EP_PCIE_RES_EDMA].resource; + u32 edma_lo = edma->start; + + ep_pcie_write_reg(dev->parf, + PCIE20_PARF_EDMA_BASE_ADDR_HI, 0x100); + EP_PCIE_DBG(dev, + "PCIe V%d: EDMA base HI :0x%x\n", + dev->rev, readl_relaxed(dev->parf + + PCIE20_PARF_EDMA_BASE_ADDR_HI)); + + ep_pcie_write_reg(dev->parf, + PCIE20_PARF_EDMA_BASE_ADDR, edma_lo); + EP_PCIE_DBG(dev, + "PCIe V%d: EDMA base:0x%x\n", dev->rev, + readl_relaxed(dev->parf + + PCIE20_PARF_EDMA_BASE_ADDR)); + } } } @@ -710,6 +733,10 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) ep_pcie_write_mask(dev->parf + PCIE20_PARF_INT_ALL_MASK, 0, BIT(EP_PCIE_INT_EVT_MHI_A7)); + if (dev->pcie_edma) + ep_pcie_write_mask(dev->parf + + PCIE20_PARF_INT_ALL_MASK, 0, + BIT(EP_PCIE_INT_EVT_EDMA)); EP_PCIE_DBG(dev, "PCIe V%d: PCIE20_PARF_INT_ALL_MASK:0x%x\n", dev->rev, @@ -806,8 +833,15 @@ static void ep_pcie_config_outbound_iatu_entry(struct ep_pcie_dev_t *dev, tgt_lower); ep_pcie_write_reg(dev->iatu, PCIE20_IATU_O_UTAR(region), tgt_upper); - ep_pcie_write_mask(dev->iatu + PCIE20_IATU_O_CTRL2(region), - 0, BIT(31)); + /* Set DMA Bypass bit for eDMA */ + if (dev->pcie_edma) + ep_pcie_write_mask(dev->iatu + + PCIE20_IATU_O_CTRL2(region), 0, + BIT(31)|BIT(27)); + else + ep_pcie_write_mask(dev->iatu + + PCIE20_IATU_O_CTRL2(region), 0, + BIT(31)); EP_PCIE_DBG(dev, "PCIe V%d: Outbound iATU configuration\n", dev->rev); @@ -1166,6 +1200,7 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev, dev->mmio = dev->res[EP_PCIE_RES_MMIO].base; dev->msi = dev->res[EP_PCIE_RES_MSI].base; dev->dm_core = dev->res[EP_PCIE_RES_DM_CORE].base; + dev->edma = dev->res[EP_PCIE_RES_EDMA].base; dev->elbi = dev->res[EP_PCIE_RES_ELBI].base; dev->iatu = dev->res[EP_PCIE_RES_IATU].base; @@ -1179,6 +1214,7 @@ static void ep_pcie_release_resources(struct ep_pcie_dev_t *dev) dev->parf = NULL; dev->elbi = NULL; dev->dm_core = NULL; + dev->edma = NULL; dev->phy = NULL; dev->mmio = NULL; dev->msi = NULL; @@ -2459,6 +2495,8 @@ struct ep_pcie_hw hw_drv = { static int ep_pcie_probe(struct platform_device *pdev) { int ret; + struct dma_iommu_mapping *mapping; + int bypass_en = 1; pr_debug("%s\n", __func__); @@ -2519,6 +2557,12 @@ static int ep_pcie_probe(struct platform_device *pdev) EP_PCIE_DBG(&ep_pcie_dev, "PCIe V%d: pcie-phy-ver:%d\n", ep_pcie_dev.rev, ep_pcie_dev.phy_rev); + ep_pcie_dev.pcie_edma = of_property_read_bool((&pdev->dev)->of_node, + "qcom,pcie-edma"); + EP_PCIE_DBG(&ep_pcie_dev, + "PCIe V%d: pcie edma is %s enabled\n", + ep_pcie_dev.rev, ep_pcie_dev.pcie_edma ? "" : "not"); + ep_pcie_dev.active_config = of_property_read_bool((&pdev->dev)->of_node, "qcom,pcie-active-config"); EP_PCIE_DBG(&ep_pcie_dev, @@ -2602,7 +2646,37 @@ static int ep_pcie_probe(struct platform_device *pdev) "PCIe V%d: %s got resources successfully; start turning on the link\n", ep_pcie_dev.rev, dev_name(&(pdev->dev))); + if (ep_pcie_dev.pcie_edma) { + mapping = arm_iommu_create_mapping + (&platform_bus_type, 0, SZ_4K); + if (IS_ERR_OR_NULL(mapping)) { + EP_PCIE_ERR(&ep_pcie_dev, + "PCIe V%d: Failed to create_mapping\n", + ep_pcie_dev.rev); + goto skip_mapping; + } + + ret = iommu_domain_set_attr(mapping->domain, + DOMAIN_ATTR_S1_BYPASS, &bypass_en); + if (ret < 0) + EP_PCIE_ERR(&ep_pcie_dev, + "PCIe V%d: Failed to set bypass\n", + ep_pcie_dev.rev); + + ret = arm_iommu_attach_device(&pdev->dev, mapping); + if (ret) + EP_PCIE_ERR(&ep_pcie_dev, + "PCIe V%d: arm_iommu_attach_device failed %d\n", + ep_pcie_dev.rev, ret); + else + EP_PCIE_ERR(&ep_pcie_dev, + "PCIe V%d: arm_iommu_attach_device successful\n", + ep_pcie_dev.rev); + } +skip_mapping: ret = ep_pcie_enumeration(&ep_pcie_dev); + if (IS_ENABLED(CONFIG_QCOM_PCI_EDMA)) + qcom_edma_init(&pdev->dev); if (!ret || ep_pcie_debug_keep_resource) return 0; diff --git a/include/linux/msm_ep_pcie.h b/include/linux/msm_ep_pcie.h index a1d2a17820e0..720a0811f85c 100644 --- a/include/linux/msm_ep_pcie.h +++ b/include/linux/msm_ep_pcie.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015, 2017, 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -47,6 +47,7 @@ enum ep_pcie_irq_event { EP_PCIE_INT_EVT_CFG_WRITE, EP_PCIE_INT_EVT_BRIDGE_FLUSH_N, EP_PCIE_INT_EVT_LINK_UP, + EP_PCIE_INT_EVT_EDMA = 22, EP_PCIE_INT_EVT_MAX = 13, }; -- GitLab From 0999d4a86c1e04dc318b8b3025a04411be41aa5c Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 2 Oct 2018 14:09:19 -0700 Subject: [PATCH 1205/1286] dt-bindings: edma: devicetree documentation for PCIe eDMA Adding devicetree documentation for PCIe eDMA driver. Change-Id: I3e8b3f6afe2595ca59fa1722991d9637d2cde045 Signed-off-by: Tony Truong Signed-off-by: Rama Krishna Phani A --- .../devicetree/bindings/dma/qcom-pci-edma.txt | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom-pci-edma.txt diff --git a/Documentation/devicetree/bindings/dma/qcom-pci-edma.txt b/Documentation/devicetree/bindings/dma/qcom-pci-edma.txt new file mode 100644 index 000000000000..4e2a43e39d07 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom-pci-edma.txt @@ -0,0 +1,79 @@ +Qualcomm Technologies Inc PCIe eDMA controller + +QCOM PCIe eDMA controller provides DMA capabilities for +peripheral connected and uses PCIe to transfer data. + +============== +Node Structure +============== + +Main node properties: + +- compatible + Usage: required + Value type: + Definition: "qcom,pci-edma" + +- #dma-cells + Usage: required + Value type: + Definition: Number of parameters client will provide. Must be set to 2. + 1st parameter: channel index, 0 for TX, 1 for RX + 2nd parameter: event processing priority, set to 0 for highest priority + +- reg + Usage: required + Value type: Array (2-cell) of + Definition: First cell is eDMA register base address. Second cell is size of + eDMA register space. + +- interrupts + Usage: required + Value type: Array of + Definition: Array of tuples which describe interrupt lines for eDMA. + +- interrupts-names + Usage: required + Value type: Array of + Definition: Array of names which map to interrupt lines for eDMA. + +- interrupt-parent + Usage: required + Value type: + Definition: phandle of the interrupt controller that services interrupts for + this device + +- qcom,n-tl-init + Usage: optional + Value type: + Definition: Number of transfer and descriptor arrays to start with. If this + entry is not presetn, default value is 2. + +- qcom,n-tl-ele + Usage: optional + Value type: + Definition: Number of elements for each transfer and descriptor array. If this + entry is not present, default value is 1024. + +- qcom,n-max-ev-ch + Usage: optional + Value type: + Definition: Total number of virtual (client) eDMA channels available. If this + entry is not present, default value is 32. + +======= +Example +======= + +pci_edma: qcom,pci-edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupts = ; + interrupt-names = "pci-edma-int"; + interrupt-parent = <&intc>; + qcom,n-max-ev-ch = <32>; + qcom,n-tl-init = <2>; + qcom,n-tl-ele = <1024>; + status = "ok"; +}; -- GitLab From 63685722c9d33142f9bb44360f5c7e03418069ce Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Wed, 30 Jan 2019 11:15:10 +0530 Subject: [PATCH 1206/1286] msm: ADSPRPC: Error handling during pd restart Bail during static pd creation if we failed to unmap memory during audiopd restart. Change-Id: Idcaf2f57c6a1e3ab3af7382c023a62bfeed1d95e Acked-by: Vishnu Karthik D Signed-off-by: Tharun Kumar Merugu --- drivers/char/adsprpc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index e470d9c21826..702e324350c2 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2133,6 +2133,8 @@ static int fastrpc_init_process(struct fastrpc_file *fl, if (!strcmp(proc_name, "audiopd")) { fl->spdname = AUDIO_PDR_SERVICE_LOCATION_CLIENT_NAME; VERIFY(err, !fastrpc_mmap_remove_pdr(fl)); + if (err) + goto bail; } if (!me->staticpd_flags && !(me->legacy_remote_heap)) { -- GitLab From 569c7edf215e7d0d03da8ba88f03491145f5bafa Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Tue, 8 Jan 2019 19:07:24 +0530 Subject: [PATCH 1207/1286] ARM: dts: msm: Add NFC device node for SM6125 Device node changes required on SM6125 describing the GPIO configuration for Nfc controller chip. Modified corresponding Nfc device node for QRD and IDP platform. Change-Id: I8e1bca110f98e030d1cd60a429dbe45aa06c2f3c Signed-off-by: Tapas Dey --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 21 +++++ arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi | 92 +++++++++++++++++++ arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 21 +++++ 3 files changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index 50cadae17b45..71805d6c7b2d 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -70,6 +70,27 @@ }; }; +&qupv3_se1_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 85 0x00>; + qcom,nq-ven = <&tlmm 83 0x00>; + qcom,nq-firm = <&tlmm 84 0x00>; + qcom,nq-clkreq = <&tlmm 95 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <85 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + &sdhc_1 { vdd-supply = <&pm6125_l24>; qcom,vdd-voltage-level = <2950000 2950000>; diff --git a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi index 1992e0001fb0..44952a8b63cb 100644 --- a/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi @@ -81,6 +81,98 @@ }; }; + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 85 NFC Read Interrupt */ + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 85 NFC Read Interrupt */ + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 83: Enable 84: Firmware */ + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 83: Enable 84: Firmware */ + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 95: NFC CLOCK REQUEST */ + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 95: NFC CLOCK REQUEST */ + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + /* SE 2 pin mappings */ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { qupv3_se2_i2c_active: qupv3_se2_i2c_active { diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index 8a01883274d1..c1d56f2f60b3 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -83,6 +83,27 @@ }; }; +&qupv3_se1_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 85 0x00>; + qcom,nq-ven = <&tlmm 83 0x00>; + qcom,nq-firm = <&tlmm 84 0x00>; + qcom,nq-clkreq = <&tlmm 95 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <85 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + &sdhc_1 { vdd-supply = <&pm6125_l24>; qcom,vdd-voltage-level = <2950000 2950000>; -- GitLab From f6bc390d2e2181c94eefac3fb81405f911b9d851 Mon Sep 17 00:00:00 2001 From: David Dai Date: Tue, 11 Dec 2018 18:52:56 -0800 Subject: [PATCH 1208/1286] clk: qcom: clk-cpu-osm: move set policy->cpu flag to end of init In order to circumvent a race condition where one CPU may access the frequency table of the policy of another CPU while it's hotplugging, move setting of the policy->cpu flag to the end of the init osm operator after it initializes its frequency table. Change-Id: I4b02caa4995387c16a6db8b8eb9de7271f23c2f6 Signed-off-by: David Dai --- drivers/clk/qcom/clk-cpu-osm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c index 874a6f07b96e..3741521baf85 100644 --- a/drivers/clk/qcom/clk-cpu-osm.c +++ b/drivers/clk/qcom/clk-cpu-osm.c @@ -79,6 +79,7 @@ struct clk_osm { u64 total_cycle_counter; u32 prev_cycle_counter; unsigned long rate; + cpumask_t related_cpus; }; static bool is_sdmshrike; @@ -560,7 +561,7 @@ static struct clk_osm *osm_configure_policy(struct cpufreq_policy *policy) if (parent != c_parent) continue; - cpumask_set_cpu(cpu, policy->cpus); + cpumask_set_cpu(cpu, &c->related_cpus); if (n->core_num == 0) first = n; } @@ -688,6 +689,9 @@ static int osm_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->dvfs_possible_from_any_cpu = true; policy->fast_switch_possible = true; policy->driver_data = c; + + cpumask_copy(policy->cpus, &c->related_cpus); + return 0; err: -- GitLab From 4443e50ca71dc3a75b02d8ae4ed3e5ca92753241 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Thu, 24 Jan 2019 17:50:21 +0530 Subject: [PATCH 1209/1286] defconfig: Enable mmc configs for sdxprairie This enables configs for sd card to function. Change-Id: Ia542332c420370a97c09c6fc230b77fae58eab05 Signed-off-by: Pradeep P V K --- arch/arm/configs/vendor/sdxprairie-perf_defconfig | 11 +++++++++++ arch/arm/configs/vendor/sdxprairie_defconfig | 12 ++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index 7ba18df1ad72..daf1db493141 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -301,6 +301,16 @@ CONFIG_USB_CONFIGFS_F_GSI=y CONFIG_USB_CONFIGFS_F_QDSS=y CONFIG_USB_PD_POLICY=y CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y @@ -366,6 +376,7 @@ CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_PM=y CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_ARM_MEMLAT_MON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 1274e22471aa..ac4bc5e7f1e3 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -294,6 +294,17 @@ CONFIG_USB_CONFIGFS_F_GSI=y CONFIG_USB_CONFIGFS_F_QDSS=y CONFIG_USB_PD_POLICY=y CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_RING_BUFFER=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y @@ -359,6 +370,7 @@ CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_PM=y CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_ARM_MEMLAT_MON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y -- GitLab From 10b9d10971c39206aa51701101c6a6c0742d42f2 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 20 Sep 2018 15:48:30 -0700 Subject: [PATCH 1210/1286] net: lan78xx: Avoid unnecessary self assignment Clang warns when a variable is assigned to itself. drivers/net/usb/lan78xx.c:940:11: warning: explicitly assigning value of variable of type 'u32' (aka 'unsigned int') to itself [-Wself-assign] offset = offset; ~~~~~~ ^ ~~~~~~ 1 warning generated. Reorder the if statement to acheive the same result and avoid a self assignment warning. Change-Id: Ia3037cdcf96bb7e720273bf2050a61d20af14e0a Link: https://github.com/ClangBuiltLinux/linux/issues/129 Signed-off-by: Nathan Chancellor Signed-off-by: David S. Miller Git-commit: 94e7c844990f0db92418586b107be135b4963b66 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Liangliang Lu --- drivers/net/usb/lan78xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index e069b310d6a6..13efaa7c1a99 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -923,11 +923,9 @@ static int lan78xx_read_otp(struct lan78xx_net *dev, u32 offset, ret = lan78xx_read_raw_otp(dev, 0, 1, &sig); if (ret == 0) { - if (sig == OTP_INDICATOR_1) - offset = offset; - else if (sig == OTP_INDICATOR_2) + if (sig == OTP_INDICATOR_2) offset += 0x100; - else + else if (sig != OTP_INDICATOR_1) ret = -EINVAL; if (!ret) ret = lan78xx_read_raw_otp(dev, offset, length, data); -- GitLab From cc74cfb32252dd45dad5d55590d43eaa3e661c50 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Sep 2018 19:29:09 +0200 Subject: [PATCH 1211/1286] net: lan78xx: Bail out if lan78xx_get_endpoints fails We need to bail out if lan78xx_get_endpoints() fails, otherwise the result is overwritten. Change-Id: I7d457042a1166c1ea34741a67cae84c41274b4df Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet") Signed-off-by: Stefan Wahren Reviewed-by: Raghuram Chary Jallipalli Signed-off-by: David S. Miller Git-commit: fa8cd98c06407b5798b927cd7fd14d30f360ed02 Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Liangliang Lu --- drivers/net/usb/lan78xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index 13efaa7c1a99..00e089ee0b4a 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -2812,6 +2812,11 @@ static int lan78xx_bind(struct lan78xx_net *dev, struct usb_interface *intf) int i; ret = lan78xx_get_endpoints(dev, intf); + if (ret) { + netdev_warn(dev->net, "lan78xx_get_endpoints failed: %d\n", + ret); + return ret; + } dev->data[0] = (unsigned long)kzalloc(sizeof(*pdata), GFP_KERNEL); -- GitLab From 7e529d1d29027ba42bdd3d5c026d828b8c0069d1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Sep 2018 19:29:10 +0200 Subject: [PATCH 1212/1286] net: lan78xx: Drop unnecessary strcpy in lan78xx_probe There is no need for this strcpy because alloc_etherdev() already does this job. Change-Id: I2cad4ea62a935a33e8e3f9e52a3812e03a5300d7 Signed-off-by: Stefan Wahren Reviewed-by: Raghuram Chary Jallipalli Signed-off-by: David S. Miller Git-commit: 7a6b022d7964a8f9fa09885a62dc5ba82127dccc Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Liangliang Lu --- drivers/net/usb/lan78xx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index 00e089ee0b4a..e2fb667c38a7 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -3601,7 +3601,6 @@ static int lan78xx_probe(struct usb_interface *intf, ret = lan78xx_bind(dev, intf); if (ret < 0) goto out2; - strcpy(netdev->name, "eth%d"); if (netdev->mtu > (dev->hard_mtu - netdev->hard_header_len)) netdev->mtu = dev->hard_mtu - netdev->hard_header_len; -- GitLab From 203f1c95c11fe47a92c58f6c76290e7ebbd7956f Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 6 Aug 2018 23:12:17 -0700 Subject: [PATCH 1213/1286] lan78xx: Do not access skb_queue_head list pointers directly. Use skb_queue_walk() instead. Adjust inner loop test to utilize and skb_queue_is_first(). Unfortunately we have to keep pkt_cnt around because it is used by a latter loop in this function. Change-Id: I63159763bfaea0d29c3f4a0a26c47ab3f5f1dc33 Signed-off-by: David S. Miller Git-commit: e42a43a5cab2e019b5ab82bedb1340854709154d Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Liangliang Lu --- drivers/net/usb/lan78xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index e2fb667c38a7..5bf19704d838 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -3188,9 +3188,9 @@ static void lan78xx_tx_bh(struct lan78xx_net *dev) count = 0; length = 0; spin_lock_irqsave(&tqp->lock, flags); - for (skb = tqp->next; pkt_cnt < tqp->qlen; skb = skb->next) { + skb_queue_walk(tqp, skb) { if (skb_is_gso(skb)) { - if (pkt_cnt) { + if (!skb_queue_is_first(tqp, skb)) { /* handle previous packets first */ break; } -- GitLab From 748b70d49c4cf43552063a693047c19a663c3ab7 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Apr 2018 17:04:03 -0700 Subject: [PATCH 1214/1286] ARM: dts: msm: add eDMA devicetree node for SM8150 Add devicetree node for PCIe eDMA for SM8150. The driver provides DMA capabilities for PCIe devices. Change-Id: I1d3bf402779dff609ca4e80bdad8d9154f62f189 Signed-off-by: Tony Truong --- arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index e1753d4cf23d..1c1b68efaca5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -597,4 +597,13 @@ , ; }; + + pcie1_edma: qcom,pcie1_edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "pci-edma-int"; + }; }; -- GitLab From 733cad6540c25522b6ede7e118f63c67966cdaf6 Mon Sep 17 00:00:00 2001 From: Jason Martinsen Date: Tue, 18 Dec 2018 05:38:22 +0000 Subject: [PATCH 1215/1286] lan78xx: Resolve issue with changing MAC address Current state for the lan78xx driver does not allow for changing the MAC address of the interface, without either removing the module (if you compiled it that way) or rebooting the machine. If you attempt to change the MAC address, ifconfig will show the new address, however, the system/interface will not respond to any traffic using that configuration. A few short-term options to work around this are to unload the module and reload it with the new MAC address, change the interface to "promisc", or reboot with the correct configuration to change the MAC. This patch enables the ability to change the MAC address via fairly normal means... ifdown modify entry in /etc/network/interfaces OR a similar method ifup Then test via any network communication, such as ICMP requests to gateway. My only test platform for this patch has been a raspberry pi model 3b+. Change-Id: Ifcec1f077e005a2c23360dc52b2d5442be290f12 Signed-off-by: Jason Martinsen Signed-off-by: David S. Miller Git-commit: 15515aaaa69659c502003926a2067ee76176148a Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git Signed-off-by: Liangliang Lu --- drivers/net/usb/lan78xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c index 5bf19704d838..e36bbebc8eb1 100644 --- a/drivers/net/usb/lan78xx.c +++ b/drivers/net/usb/lan78xx.c @@ -2210,6 +2210,10 @@ static int lan78xx_set_mac_addr(struct net_device *netdev, void *p) ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo); ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi); + /* Added to support MAC address changes */ + ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo); + ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_); + return 0; } -- GitLab From 5c9136d987b23c5cf3219139e949f2b18ddfe9be Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Fri, 23 Nov 2018 13:35:19 +0530 Subject: [PATCH 1216/1286] ARM: dts: Add sdcard support for sdxprairie Add sdcard support for sdxprairie. Change-Id: Ia03c2d111f0f6c32b0e4c9b98a48d471ac61de9c Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi | 21 +++++ arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi | 21 +++++ .../boot/dts/qcom/sdxprairie-pinctrl.dtsi | 76 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 42 ++++++++++ 4 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi index 82ce24e6fdb1..91126a2ffff9 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-cdp.dtsi @@ -183,3 +183,24 @@ "usb_in_current", "chg_temp"; }; + +&sdhc_1 { + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,devfreq,freq-table = <50000000 200000000>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi index e989e2ddc80e..4c86a8cab14b 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-mtp.dtsi @@ -215,3 +215,24 @@ qcom,fg-esr-cal-soc-thresh = <26 230>; qcom,fg-esr-cal-temp-thresh = <10 40>; }; + +&sdhc_1 { + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,devfreq,freq-table = <50000000 200000000>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index dcb1b0c538f4..1974af190601 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -1358,5 +1358,81 @@ }; }; }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cd_on: cd_on { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc1_cd_off: cd_off { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 43b3cddd4b1b..975f3f318e55 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -32,6 +32,7 @@ aliases { pci-domain0 = &pcie0; /* PCIe0 domain */ + sdhc1 = &sdhc_1; /* SDC1 eMMC/SD/SDIO slot */ }; reserved-memory { @@ -1109,6 +1110,47 @@ mhi_devices { }; }; + + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 400000 800000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0>; + qcom,pm-qos-legacy-latency-us = <70 70>; + qcom,pm-qos-irq-type = "affine_cores"; + qcom,pm-qos-irq-cpu = <0>; + qcom,pm-qos-irq-latency = <70 70>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + qcom,restore-after-cx-collapse; + + status = "disabled"; + }; }; #include "sdxprairie-pm.dtsi" -- GitLab From 5e8d634482fcb2980af000fb21a53225b13df762 Mon Sep 17 00:00:00 2001 From: Aditya Mathur Date: Tue, 22 Jan 2019 19:48:17 +0530 Subject: [PATCH 1217/1286] net: usb: Add the USB RmNet host driver Add support for RmNet networking over USB. This is based on a snapshot from kernel msm-3.10 'commit ee337c6f350c ("net: rmnet_usb: Add sleep state extended IOCTL")' with changes to remove ether mode support and some code cleanup. This driver is used for only DATA message transactions between host and device. Change-Id: I6919ddf67613b1434adb78587e3a523897c2b5c6 Signed-off-by: Ajay Agarwal --- net/Kconfig | 1 + net/Makefile | 1 + net/rmnet_usb/Kconfig | 8 + net/rmnet_usb/Makefile | 1 + net/rmnet_usb/rmnet_usb.c | 446 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 457 insertions(+) create mode 100644 net/rmnet_usb/Kconfig create mode 100644 net/rmnet_usb/Makefile create mode 100644 net/rmnet_usb/rmnet_usb.c diff --git a/net/Kconfig b/net/Kconfig index d7bc9d21bee5..a2d984839547 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -241,6 +241,7 @@ source "net/l3mdev/Kconfig" source "net/qrtr/Kconfig" source "net/ncsi/Kconfig" source "net/rmnet_data/Kconfig" +source "net/rmnet_usb/Kconfig" config RPS bool diff --git a/net/Makefile b/net/Makefile index f04d4bbf617d..9e3c324df362 100644 --- a/net/Makefile +++ b/net/Makefile @@ -87,3 +87,4 @@ endif obj-$(CONFIG_QRTR) += qrtr/ obj-$(CONFIG_NET_NCSI) += ncsi/ obj-$(CONFIG_RMNET_DATA) += rmnet_data/ +obj-$(CONFIG_RMNET_USB) += rmnet_usb/ diff --git a/net/rmnet_usb/Kconfig b/net/rmnet_usb/Kconfig new file mode 100644 index 000000000000..d90f3fd98215 --- /dev/null +++ b/net/rmnet_usb/Kconfig @@ -0,0 +1,8 @@ +config RMNET_USB + tristate "RmNet USB Driver" + depends on USB_USBNET + help + Select this if you have a QTI modem device connected via USB + supporting RmNet network interface. + To compile this driver as a module, choose M here: the module + will be called rmnet_usb. If unsure, choose N. diff --git a/net/rmnet_usb/Makefile b/net/rmnet_usb/Makefile new file mode 100644 index 000000000000..941f6b2fdb34 --- /dev/null +++ b/net/rmnet_usb/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RMNET_USB) += rmnet_usb.o diff --git a/net/rmnet_usb/rmnet_usb.c b/net/rmnet_usb/rmnet_usb.c new file mode 100644 index 000000000000..fa95ef908b5f --- /dev/null +++ b/net/rmnet_usb/rmnet_usb.c @@ -0,0 +1,446 @@ +/* Copyright (c) 2011-2014, 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RMNET_VENDOR_ID 0x05c6 +#define RMNET_USB_DEV_NAME "rmnet_usb%d" +#define RMNET_DATA_LEN 0x4000 +#define WATCHDOG_TIMEOUT (30 * HZ) + +static void rmnet_usb_disable_usb_autosuspend(struct usbnet *usbnet, + int en_autosuspend) +{ + struct usb_device *usb_dev = usbnet->udev; + + usb_get_dev(usb_dev); + if (!en_autosuspend) + usb_disable_autosuspend(usb_dev); + else + usb_enable_autosuspend(usb_dev); + + usb_put_dev(usb_dev); +} + +static int rmnet_usb_change_dtr(struct usbnet *dev, bool on) +{ + u8 intf = dev->intf->cur_altsetting->desc.bInterfaceNumber; + + return usbnet_write_cmd(dev, USB_CDC_REQ_SET_CONTROL_LINE_STATE, + USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE, + on ? 0x01 : 0x00, intf, NULL, 0); +} + +static int rmnet_usb_manage_power(struct usbnet *dev, int on) +{ + int rv; + + rv = usb_autopm_get_interface(dev->intf); + dev->intf->needs_remote_wakeup = on; + if (!rv) + usb_autopm_put_interface(dev->intf); + + return 0; +} + +static __be16 rmnet_usb_ip_type_trans(struct sk_buff *skb) +{ + __be16 protocol = 0; + + /* determine L3 protocol */ + switch (skb->data[0] & 0xf0) { + case 0x40: + protocol = htons(ETH_P_IP); + break; + case 0x60: + protocol = htons(ETH_P_IPV6); + break; + default: + /* default is QMAP */ + protocol = htons(ETH_P_MAP); + break; + } + + return protocol; +} + +static int rmnet_usb_rx_fixup(struct usbnet *dev, struct sk_buff *skb) +{ + skb->protocol = rmnet_usb_ip_type_trans(skb); + return 1; +} + +static int rmnet_change_mtu(struct net_device *dev, int new_mtu) +{ + if (new_mtu < 0 || RMNET_DATA_LEN < new_mtu) + return -EINVAL; + + dev->mtu = new_mtu; + return 0; +} + +static struct net_device_stats *rmnet_get_stats(struct net_device *dev) +{ + return &dev->stats; +} + +static int rmnet_ioctl_extended(struct net_device *dev, struct ifreq *ifr) +{ + struct rmnet_ioctl_extended_s ext_cmd; + int rc = 0; + struct usbnet *unet = netdev_priv(dev); + + rc = copy_from_user(&ext_cmd, ifr->ifr_ifru.ifru_data, + sizeof(struct rmnet_ioctl_extended_s)); + if (rc) + return rc; + + switch (ext_cmd.extended_ioctl) { + case RMNET_IOCTL_SET_MRU: + if (test_bit(EVENT_DEV_OPEN, &unet->flags)) + return -EBUSY; + /* 16K max */ + if ((size_t)ext_cmd.u.data > 0x4000) + return -EINVAL; + dev_dbg(&unet->intf->dev, "MRU change request to 0x%x\n", + ext_cmd.u.data); + unet->rx_urb_size = (size_t)ext_cmd.u.data; + break; + case RMNET_IOCTL_GET_MRU: + ext_cmd.u.data = (uint32_t)unet->rx_urb_size; + break; + case RMNET_IOCTL_GET_SUPPORTED_FEATURES: + ext_cmd.u.data = 0; + break; + case RMNET_IOCTL_GET_DRIVER_NAME: + strlcpy(ext_cmd.u.if_name, unet->driver_name, + sizeof(ext_cmd.u.if_name)); + break; + case RMNET_IOCTL_SET_SLEEP_STATE: + rmnet_usb_disable_usb_autosuspend(unet, ext_cmd.u.data); + break; + default: + rc = -EINVAL; + break; + } + + rc = copy_to_user(ifr->ifr_ifru.ifru_data, &ext_cmd, + sizeof(struct rmnet_ioctl_extended_s)); + return rc; +} + +static int rmnet_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + int rc = 0; + struct rmnet_ioctl_data_s ioctl_data; + + switch (cmd) { + case RMNET_IOCTL_SET_LLP_IP: /* set RAWIP protocol */ + break; + case RMNET_IOCTL_GET_LLP: /* get link protocol state */ + ioctl_data.u.operation_mode = RMNET_MODE_LLP_IP; + if (copy_to_user(ifr->ifr_ifru.ifru_data, &ioctl_data, + sizeof(struct rmnet_ioctl_data_s))) + rc = -EFAULT; + break; + case RMNET_IOCTL_GET_OPMODE: /* get operation mode */ + ioctl_data.u.operation_mode = RMNET_MODE_LLP_IP; + if (copy_to_user(ifr->ifr_ifru.ifru_data, &ioctl_data, + sizeof(struct rmnet_ioctl_data_s))) + rc = -EFAULT; + break; + case RMNET_IOCTL_SET_QOS_ENABLE: + rc = -EINVAL; + break; + case RMNET_IOCTL_SET_QOS_DISABLE: + rc = 0; + break; + case RMNET_IOCTL_OPEN: + rc = usbnet_open(dev); + break; + case RMNET_IOCTL_CLOSE: + rc = usbnet_stop(dev); + break; + case RMNET_IOCTL_EXTENDED: + rc = rmnet_ioctl_extended(dev, ifr); + break; + default: + /* don't fail any IOCTL right now */ + rc = 0; + break; + } + + return rc; +} + +static const struct net_device_ops rmnet_usb_ops_ip = { + .ndo_open = usbnet_open, + .ndo_stop = usbnet_stop, + .ndo_start_xmit = usbnet_start_xmit, + .ndo_get_stats = rmnet_get_stats, + .ndo_tx_timeout = usbnet_tx_timeout, + .ndo_do_ioctl = rmnet_ioctl, + .ndo_change_mtu = rmnet_change_mtu, + .ndo_set_mac_address = 0, + .ndo_validate_addr = 0, +}; + +static void rmnet_usb_setup(struct net_device *dev) +{ + dev->header_ops = NULL; /* No header */ + dev->type = ARPHRD_NONE; + dev->hard_header_len = 0; + dev->addr_len = 0; + dev->netdev_ops = &rmnet_usb_ops_ip; + dev->mtu = RMNET_DATA_LEN; + dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + dev->watchdog_timeo = WATCHDOG_TIMEOUT; +} + +static int rmnet_usb_status(struct seq_file *s, void *unused) +{ + struct usbnet *unet = s->private; + + seq_printf(s, "Net MTU: %u\n", unet->net->mtu); + seq_printf(s, "rx_urb_size: %lu\n", unet->rx_urb_size); + seq_printf(s, "rx skb q len: %u\n", unet->rxq.qlen); + seq_printf(s, "rx skb done q len: %u\n", unet->done.qlen); + seq_printf(s, "rx errors: %lu\n", unet->net->stats.rx_errors); + seq_printf(s, "rx over errors: %lu\n", + unet->net->stats.rx_over_errors); + seq_printf(s, "rx length errors: %lu\n", + unet->net->stats.rx_length_errors); + seq_printf(s, "rx packets: %lu\n", unet->net->stats.rx_packets); + seq_printf(s, "rx bytes: %lu\n", unet->net->stats.rx_bytes); + seq_printf(s, "tx skb q len: %u\n", unet->txq.qlen); + seq_printf(s, "tx errors: %lu\n", unet->net->stats.tx_errors); + seq_printf(s, "tx packets: %lu\n", unet->net->stats.tx_packets); + seq_printf(s, "tx bytes: %lu\n", unet->net->stats.tx_bytes); + seq_printf(s, "EVENT_DEV_OPEN: %d\n", + test_bit(EVENT_DEV_OPEN, &unet->flags)); + seq_printf(s, "EVENT_TX_HALT: %d\n", + test_bit(EVENT_TX_HALT, &unet->flags)); + seq_printf(s, "EVENT_RX_HALT: %d\n", + test_bit(EVENT_RX_HALT, &unet->flags)); + seq_printf(s, "EVENT_RX_MEMORY: %d\n", + test_bit(EVENT_RX_MEMORY, &unet->flags)); + seq_printf(s, "EVENT_DEV_ASLEEP: %d\n", + test_bit(EVENT_DEV_ASLEEP, &unet->flags)); + + return 0; +} + +static int rmnet_usb_status_open(struct inode *inode, struct file *file) +{ + return single_open(file, rmnet_usb_status, inode->i_private); +} + +const struct file_operations rmnet_usb_fops = { + .open = rmnet_usb_status_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rmnet_usb_debugfs_init(struct usbnet *unet) +{ + struct dentry *rmnet_usb_dbg_root; + struct dentry *rmnet_usb_dentry; + + rmnet_usb_dbg_root = debugfs_create_dir(unet->net->name, NULL); + if (!rmnet_usb_dbg_root || IS_ERR(rmnet_usb_dbg_root)) + return -ENODEV; + + rmnet_usb_dentry = debugfs_create_file("status", + 0644, + rmnet_usb_dbg_root, + unet, + &rmnet_usb_fops); + if (!rmnet_usb_dentry) { + debugfs_remove_recursive(rmnet_usb_dbg_root); + return -ENODEV; + } + + unet->data[0] = (unsigned long)rmnet_usb_dbg_root; + + return 0; +} + +static void rmnet_usb_debugfs_cleanup(struct usbnet *unet) +{ + struct dentry *root = (struct dentry *)unet->data[0]; + + debugfs_remove_recursive(root); + unet->data[0] = 0; +} + +static int rmnet_usb_bind(struct usbnet *dev, struct usb_interface *iface) +{ + struct usb_host_endpoint *endpoint = NULL; + struct usb_host_endpoint *bulk_in = NULL; + struct usb_host_endpoint *bulk_out = NULL; + struct usb_host_endpoint *int_in = NULL; + int status = 0; + int i; + int numends; + u8 intf; + + numends = iface->cur_altsetting->desc.bNumEndpoints; + for (i = 0; i < numends; i++) { + endpoint = iface->cur_altsetting->endpoint + i; + if (!endpoint) { + dev_err(&iface->dev, "%s: invalid endpoint %u\n", + __func__, i); + status = -EINVAL; + goto out; + } + if (usb_endpoint_is_bulk_in(&endpoint->desc)) + bulk_in = endpoint; + else if (usb_endpoint_is_bulk_out(&endpoint->desc)) + bulk_out = endpoint; + else if (usb_endpoint_is_int_in(&endpoint->desc)) + int_in = endpoint; + } + + if (!bulk_in || !bulk_out || !int_in) { + dev_err(&iface->dev, "%s: invalid endpoints\n", __func__); + status = -EINVAL; + goto out; + } + dev->in = usb_rcvbulkpipe(dev->udev, + bulk_in->desc.bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK); + dev->out = usb_sndbulkpipe(dev->udev, + bulk_out->desc.bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK); + dev->status = int_in; + strlcpy(dev->net->name, RMNET_USB_DEV_NAME, IFNAMSIZ); + intf = iface->cur_altsetting->desc.bInterfaceNumber; + + /* Enable remote wakeup and set DTR (data terminal ready) + * to high to enable data calls + */ + rmnet_usb_manage_power(dev, 1); + rmnet_usb_change_dtr(dev, true); + +out: + return status; +} + +static void rmnet_usb_unbind(struct usbnet *dev, struct usb_interface *iface) +{ + /* Disable remote wakeup and set DTR (data terminal ready) + * to low to disable data calls + */ + rmnet_usb_manage_power(dev, 0); + rmnet_usb_change_dtr(dev, false); +} + +static int rmnet_usb_probe(struct usb_interface *iface, + const struct usb_device_id *prod) +{ + struct usbnet *unet = NULL; + struct usb_device *udev = NULL; + int status = 0; + + udev = interface_to_usbdev(iface); + + if (iface->num_altsetting != 1) { + dev_err(&iface->dev, "%s invalid num_altsetting %u\n", + __func__, iface->num_altsetting); + return -EINVAL; + } + + status = usbnet_probe(iface, prod); + if (status < 0) { + dev_err(&iface->dev, "usbnet_probe failed %d\n", + status); + return status; + } + + unet = usb_get_intfdata(iface); + + /* update net device */ + rmnet_usb_setup(unet->net); + + status = rmnet_usb_debugfs_init(unet); + if (status) + dev_dbg(&unet->intf->dev, + "mode debugfs file is not available\n"); + + usb_enable_autosuspend(udev); + + if (udev->parent && !udev->parent->parent) { + /* allow modem and roothub to wake up suspended system */ + device_set_wakeup_enable(&udev->dev, 1); + device_set_wakeup_enable(&udev->parent->dev, 1); + } + + return 0; +} + +static void rmnet_usb_disconnect(struct usb_interface *intf) +{ + struct usbnet *unet = usb_get_intfdata(intf); + + device_set_wakeup_enable(&unet->udev->dev, 0); + rmnet_usb_debugfs_cleanup(unet); + usbnet_disconnect(intf); +} + +static const struct driver_info rmnet_usb_info = { + .description = "RmNET device", + .flags = FLAG_SEND_ZLP, + .bind = rmnet_usb_bind, + .unbind = rmnet_usb_unbind, + .manage_power = rmnet_usb_manage_power, + .rx_fixup = rmnet_usb_rx_fixup, +}; + +static const struct usb_device_id rmnet_usb_ids[] = { + { + USB_DEVICE_INTERFACE_NUMBER(RMNET_VENDOR_ID, 0x90EF, 2), + .driver_info = (unsigned long)&rmnet_usb_info, + }, + { + USB_DEVICE_INTERFACE_NUMBER(RMNET_VENDOR_ID, 0x90F0, 2), + .driver_info = (unsigned long)&rmnet_usb_info, + }, + { } /* Terminating entry */ +}; +MODULE_DEVICE_TABLE(usb, rmnet_usb_ids); + +static struct usb_driver rmnet_usb_driver = { + .name = "rmnet_usb", + .id_table = rmnet_usb_ids, + .probe = rmnet_usb_probe, + .disconnect = rmnet_usb_disconnect, + .suspend = usbnet_suspend, + .resume = usbnet_resume, + .reset_resume = usbnet_resume, + .supports_autosuspend = 1, + .disable_hub_initiated_lpm = 1, +}; + +module_usb_driver(rmnet_usb_driver); + +MODULE_DESCRIPTION("QTI RmNet USB driver"); +MODULE_LICENSE("GPL v2"); -- GitLab From a2880111e61cbae89bfd16e5ff5fd1a660909558 Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Wed, 23 Jan 2019 18:28:02 +0530 Subject: [PATCH 1218/1286] net: rmnet_usb: Add support for 90f3 PID Add 05c6 VID and 90f3 PID with interface number 1 to device ID table, so that the rmnet function can be probed by rmnet_usb driver on cable connect. Change-Id: I44e5bee85902940c590e3acb167d60b20f05c1ac Signed-off-by: Ajay Agarwal --- net/rmnet_usb/rmnet_usb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/rmnet_usb/rmnet_usb.c b/net/rmnet_usb/rmnet_usb.c index fa95ef908b5f..9e978eb9d499 100644 --- a/net/rmnet_usb/rmnet_usb.c +++ b/net/rmnet_usb/rmnet_usb.c @@ -424,6 +424,10 @@ static const struct usb_device_id rmnet_usb_ids[] = { USB_DEVICE_INTERFACE_NUMBER(RMNET_VENDOR_ID, 0x90F0, 2), .driver_info = (unsigned long)&rmnet_usb_info, }, + { + USB_DEVICE_INTERFACE_NUMBER(RMNET_VENDOR_ID, 0x90F3, 1), + .driver_info = (unsigned long)&rmnet_usb_info, + }, { } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, rmnet_usb_ids); -- GitLab From 7cfabe7c8c687245df466fca2220e40e72bf6381 Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Wed, 23 Jan 2019 18:29:51 +0530 Subject: [PATCH 1219/1286] defconfig: msm: Enable USB RMNET host driver on SA6155 Enable USB host driver which probes a connected RMNET interface on SA6155 and allows DATA message exchange with device. Change-Id: I93d7172a1dd85b5e939fe8a195a6958b7a800287 Signed-off-by: Ajay Agarwal --- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 1 + arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index dbd5b5501014..e47f106bc714 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -236,6 +236,7 @@ CONFIG_NET_ACT_SKBEDIT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_SOCKEV_NLMCAST=y CONFIG_CAN=y CONFIG_QTI_CAN=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index bec7f78e9d93..0a23826ec28b 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -244,6 +244,7 @@ CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_SOCKEV_NLMCAST=y CONFIG_CAN=y CONFIG_QTI_CAN=y -- GitLab From 123d87bc6cf1e7d58087375448a292360070ceab Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Fri, 18 Jan 2019 11:22:15 +0530 Subject: [PATCH 1220/1286] ARM: dts: msm: Add device tree file for External Buck board Add dts file for Reworked External buck board for APC. Change-Id: I0951017fc7e5c86eb9f897851ecd1497b025aa71 Signed-off-by: Archit Saxena --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs405-iot-sku11.dts | 49 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs405-iot-sku11.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index adace640973d..4a71516d0520 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_QCS405) += qcs405-rumi.dtb \ qcs405-iot-sku8.dtb \ qcs405-iot-sku9.dtb \ qcs405-iot-sku10.dtb \ + qcs405-iot-sku11.dtb \ qcs405-iot-sku12.dtb else dtb-$(CONFIG_ARCH_QCS405) += qcs403-iot-sku1.dtb \ diff --git a/arch/arm64/boot/dts/qcom/qcs405-iot-sku11.dts b/arch/arm64/boot/dts/qcom/qcs405-iot-sku11.dts new file mode 100644 index 000000000000..cb4472ae28b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs405-iot-sku11.dts @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" + +/ { + model = "sEVB/SLT with DSI display and APC external Buck"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x020020 0x2>; +}; + +&soc { + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; +}; -- GitLab From e738aab7b4df2264f0e9c9a670ec097432f8bc50 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Wed, 30 Jan 2019 15:07:20 +0530 Subject: [PATCH 1221/1286] sysctl: Limit sched_upmigrate/sched_downmigrate tunables range The sched_upmigrate/sched_downmigrate tunable values are accepted in percentage. Hence don't accept any values greater than 100. The sched_upmigrate is also used to check if a CPU is overutilized or not. Accepting a large value for this tunable makes a heavily loaded CPU not getting classified as overutilized. Since the CPUs are not overutilized, the higher capacity CPUs does not offer help to the heavily loaded lower capacity CPUs. The no-hz idle balance kicks are also not sent to the CPUs with in the same cluster. This results in starvation. Change-Id: I83c3caeeb61f05de5b74b41c22702cb895072fad Signed-off-by: Pavankumar Kondeti --- kernel/sysctl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 9d27dbad7de3..daf37833692e 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -3327,7 +3327,11 @@ static int do_proc_douintvec_capacity_conv(bool *negp, unsigned long *lvalp, int *valp, int write, void *data) { if (write) { - if (*negp || *lvalp == 0) + /* + * The sched_upmigrate/sched_downmigrate tunables are + * accepted in percentage. Limit them to 100. + */ + if (*negp || *lvalp == 0 || *lvalp > 100) return -EINVAL; *valp = SCHED_FIXEDPOINT_SCALE * 100 / *lvalp; } else { -- GitLab From 4c22730465e0cf03d6d8d994c30c8b040ffd5296 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 10 Jan 2019 14:52:56 +0530 Subject: [PATCH 1222/1286] msm: ipa3: Fix to differ ipa probe if msm bus driver register fails Because of msm bus driver initialization is delayed, msm bus driver registration was failing. Differing the ipa probe until msm bus driver registration was success. Change-Id: I55cd01fc0a6775c70bb9ef969174abadbd5d0299 Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index cbe406470451..9e4cfd49c841 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -5410,7 +5410,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, ipa3_ctx->ctrl->msm_bus_data_ptr); if (!ipa3_ctx->ipa_bus_hdl) { IPAERR("fail to register with bus mgr!\n"); - result = -ENODEV; + ipa3_ctx->ctrl->msm_bus_data_ptr = NULL; + result = -EPROBE_DEFER; goto fail_bus_reg; } } @@ -6799,6 +6800,10 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p, IPADBG("dev->of_node->name = %s\n", dev->of_node->name); if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-ap-cb")) { + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_AP); cb->dev = dev; smmu_info.present[IPA_SMMU_CB_AP] = true; @@ -6807,6 +6812,10 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p, } if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-wlan-cb")) { + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_WLAN); cb->dev = dev; smmu_info.present[IPA_SMMU_CB_WLAN] = true; @@ -6815,6 +6824,10 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p, } if (of_device_is_compatible(dev->of_node, "qcom,ipa-smmu-uc-cb")) { + if (ipa3_ctx == NULL) { + IPAERR("ipa3_ctx was not initialized\n"); + return -EPROBE_DEFER; + } cb = ipa3_get_smmu_ctx(IPA_SMMU_CB_UC); cb->dev = dev; smmu_info.present[IPA_SMMU_CB_UC] = true; -- GitLab From d896f5802e72e57cfab2583883a93780cd47a975 Mon Sep 17 00:00:00 2001 From: Channagoud Kadabi Date: Mon, 5 Nov 2018 16:22:29 -0800 Subject: [PATCH 1223/1286] drivers: of: Add API to find ddr device type Add API to find the ddr device type from memory node. Change-Id: I1cfc38d46f1ea0abc6fbe8cbb6e37cde72b9fc2e Signed-off-by: Channagoud Kadabi Signed-off-by: Kaushal Kumar --- drivers/of/fdt.c | 26 ++++++++++++++++++++++++++ include/linux/of_fdt.h | 3 +++ 2 files changed, 29 insertions(+) diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index b1103e519ef6..acf7dfb00840 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -81,6 +81,32 @@ void of_fdt_limit_memory(int limit) } } +/** + * of_fdt_get_ddrtype - Return the type of ddr (4/5) on the current device + * + * On match, returns a non-zero positive value which matches the ddr type. + * Otherwise returns -ENOENT. + */ +int of_fdt_get_ddrtype(void) +{ + int memory; + int len; + int ret; + fdt32_t *prop = NULL; + + memory = fdt_path_offset(initial_boot_params, "/memory"); + if (memory > 0) + prop = fdt_getprop_w(initial_boot_params, memory, + "ddr_device_type", &len); + + if (!prop || len != sizeof(u32)) + return -ENOENT; + + ret = fdt32_to_cpu(*prop); + + return ret; +} + /** * of_fdt_is_compatible - Return true if given node from the given blob has * compat in its compatible list diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index 064bac7a464b..b7816d6bade2 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -47,6 +47,9 @@ extern void *initial_boot_params; extern char __dtb_start[]; extern char __dtb_end[]; +/* Other Prototypes */ +extern int of_fdt_get_ddrtype(void); + /* For scanning the flat device-tree at boot time */ extern int of_scan_flat_dt(int (*it)(unsigned long node, const char *uname, int depth, void *data), -- GitLab From 90ffd4bd7b3eb80727aaeac86f7c17b268cc4b41 Mon Sep 17 00:00:00 2001 From: Arun Kumar Neelakantam Date: Wed, 30 Jan 2019 17:53:23 +0530 Subject: [PATCH 1224/1286] rpmsg: glink: spi: Use mutex lock for idr_lock Using glink structure idr_lock as spinlock and channel structure intent_lock as mutexlock cause problem when last reference to channel is put during cleanup by holding idr_lock spinlock. Convert the idr_lock to mutex lock to avoid lock hierarchy issues. CRs-Fixed: 2389162 Change-Id: I68e2e3646f80171f67f922418204052888eefa78 Signed-off-by: Arun Kumar Neelakantam --- drivers/rpmsg/qcom_glink_spi.c | 96 +++++++++++++++------------------- 1 file changed, 42 insertions(+), 54 deletions(-) diff --git a/drivers/rpmsg/qcom_glink_spi.c b/drivers/rpmsg/qcom_glink_spi.c index 3f195846e8e7..08ba504674d7 100644 --- a/drivers/rpmsg/qcom_glink_spi.c +++ b/drivers/rpmsg/qcom_glink_spi.c @@ -192,7 +192,7 @@ struct glink_spi { struct mutex tx_lock; - spinlock_t idr_lock; + struct mutex idr_lock; struct idr lcids; struct idr rcids; u32 features; @@ -783,15 +783,14 @@ static int glink_spi_send_open_req(struct glink_spi *glink, int name_len = strlen(channel->name) + 1; int req_len = ALIGN(sizeof(req.msg) + name_len, SPI_ALIGNMENT); int ret; - unsigned long flags; kref_get(&channel->refcount); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); ret = idr_alloc_cyclic(&glink->lcids, channel, SPI_GLINK_CID_MIN, SPI_GLINK_CID_MAX, GFP_ATOMIC); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (ret < 0) return ret; @@ -813,10 +812,10 @@ static int glink_spi_send_open_req(struct glink_spi *glink, remove_idr: CH_INFO(channel, "remove_idr\n"); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_remove(&glink->lcids, channel->lcid); channel->lcid = 0; - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); return ret; } @@ -837,9 +836,9 @@ static int glink_spi_rx_open_ack(struct glink_spi *glink, unsigned int lcid) { struct glink_spi_channel *channel; - spin_lock(&glink->idr_lock); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->lcids, lcid); - spin_unlock(&glink->idr_lock); + mutex_unlock(&glink->idr_lock); if (!channel) { GLINK_ERR(glink, "Invalid open ack packet %d\n", lcid); return -EINVAL; @@ -926,16 +925,15 @@ static int glink_spi_handle_intent(struct glink_spi *glink, const size_t msglen = sizeof(struct intent_pair) * count; int ret; int i; - unsigned long flags; if (avail < msglen) { dev_err(&glink->dev, "Not enough data in buf\n"); return avail; } - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, cid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_err(&glink->dev, "intents for non-existing channel\n"); return msglen; @@ -970,11 +968,10 @@ static void glink_spi_handle_intent_req_ack(struct glink_spi *glink, unsigned int cid, bool granted) { struct glink_spi_channel *channel; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, cid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_err(&glink->dev, "unable to find channel\n"); return; @@ -1099,11 +1096,10 @@ static void glink_spi_handle_intent_req(struct glink_spi *glink, { struct glink_spi_rx_intent *intent; struct glink_spi_channel *channel; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, cid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { pr_err("%s channel not found for cid %d\n", __func__, cid); @@ -1289,11 +1285,10 @@ static void glink_spi_handle_rx_done(struct glink_spi *glink, { struct glink_spi_rx_intent *intent; struct glink_spi_channel *channel; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, cid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_err(&glink->dev, "invalid channel id received\n"); return; @@ -1374,7 +1369,6 @@ static struct glink_spi_channel *glink_spi_create_local(struct glink_spi *glink, { struct glink_spi_channel *channel; int ret; - unsigned long flags; channel = glink_spi_alloc_channel(glink, name); if (IS_ERR(channel)) @@ -1401,9 +1395,9 @@ static struct glink_spi_channel *glink_spi_create_local(struct glink_spi *glink, CH_INFO(channel, "err_timeout\n"); /* glink_spi_send_open_req() did register the channel in lcids*/ - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_remove(&glink->lcids, channel->lcid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); release_channel: CH_INFO(channel, "release_channel\n"); @@ -1462,14 +1456,13 @@ glink_spi_create_ept(struct rpmsg_device *rpdev, rpmsg_rx_cb_t cb, void *priv, const char *name = chinfo.name; int cid; int ret; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_for_each_entry(&glink->rcids, channel, cid) { if (!strcmp(channel->name, name)) break; } - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { channel = glink_spi_create_local(glink, name); @@ -1548,11 +1541,10 @@ static void glink_spi_rx_close(struct glink_spi *glink, unsigned int rcid) { struct rpmsg_channel_info chinfo; struct glink_spi_channel *channel; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, rcid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (WARN(!channel, "close request on unknown channel\n")) return; CH_INFO(channel, "\n"); @@ -1567,10 +1559,10 @@ static void glink_spi_rx_close(struct glink_spi *glink, unsigned int rcid) glink_spi_send_close_ack(glink, channel->rcid); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_remove(&glink->rcids, channel->rcid); channel->rcid = 0; - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); kref_put(&channel->refcount, glink_spi_channel_release); } @@ -1578,19 +1570,18 @@ static void glink_spi_rx_close(struct glink_spi *glink, unsigned int rcid) static void glink_spi_rx_close_ack(struct glink_spi *glink, unsigned int lcid) { struct glink_spi_channel *channel; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->lcids, lcid); if (WARN(!channel, "close ack on unknown channel\n")) { - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); return; } CH_INFO(channel, "\n"); idr_remove(&glink->lcids, channel->lcid); channel->lcid = 0; - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); kref_put(&channel->refcount, glink_spi_channel_release); } @@ -1635,12 +1626,11 @@ static int glink_spi_handle_signals(struct glink_spi *glink, unsigned int rcid, unsigned int signals) { struct glink_spi_channel *channel; - unsigned long flags; u32 old; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, rcid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_err(&glink->dev, "signal for non-existing channel\n"); return -EINVAL; @@ -1733,14 +1723,13 @@ static int glink_spi_rx_open(struct glink_spi *glink, unsigned int rcid, struct device_node *node; int lcid; int ret; - unsigned long flags; - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_for_each_entry(&glink->lcids, channel, lcid) { if (!strcmp(channel->name, name)) break; } - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { channel = glink_spi_alloc_channel(glink, name); @@ -1751,15 +1740,15 @@ static int glink_spi_rx_open(struct glink_spi *glink, unsigned int rcid, create_device = true; } - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); ret = idr_alloc(&glink->rcids, channel, rcid, rcid + 1, GFP_ATOMIC); if (ret < 0) { dev_err(&glink->dev, "Unable to insert channel into rcid list\n"); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); goto free_channel; } channel->rcid = ret; - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); complete_all(&channel->open_req); @@ -1796,10 +1785,10 @@ static int glink_spi_rx_open(struct glink_spi *glink, unsigned int rcid, kfree(rpdev); rcid_remove: CH_INFO(channel, "rcid_remove\n"); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); idr_remove(&glink->rcids, channel->rcid); channel->rcid = 0; - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); free_channel: CH_INFO(channel, "free_channel\n"); /* Release the reference, iff we took it */ @@ -1838,9 +1827,9 @@ static int glink_spi_rx_data(struct glink_spi *glink, left_size = le32_to_cpu(hdr->left_size); addr = (u32)le64_to_cpu(hdr->addr); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, rcid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_dbg(&glink->dev, "Data on non-existing channel\n"); return msglen; @@ -1907,9 +1896,9 @@ static int glink_spi_rx_short_data(struct glink_spi *glink, dev_dbg(&glink->dev, "Not enough data in fifo\n"); return avail; } - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); channel = idr_find(&glink->rcids, rcid); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); if (!channel) { dev_dbg(&glink->dev, "Data on non-existing channel\n"); return msglen; @@ -2344,7 +2333,7 @@ struct glink_spi *qcom_glink_spi_register(struct device *parent, kthread_init_work(&glink->rx_work, glink_spi_work); kthread_init_worker(&glink->rx_worker); - spin_lock_init(&glink->idr_lock); + mutex_init(&glink->idr_lock); idr_init(&glink->lcids); idr_init(&glink->rcids); @@ -2399,7 +2388,6 @@ static void glink_spi_remove(struct glink_spi *glink) struct glink_spi_channel *channel; int cid; int ret; - unsigned long flags; GLINK_INFO(glink, "\n"); @@ -2411,7 +2399,7 @@ static void glink_spi_remove(struct glink_spi *glink) if (ret) dev_warn(&glink->dev, "Can't remove GLINK devices: %d\n", ret); - spin_lock_irqsave(&glink->idr_lock, flags); + mutex_lock(&glink->idr_lock); /* Release any defunct local channels, waiting for close-ack */ idr_for_each_entry(&glink->lcids, channel, cid) { kref_put(&channel->refcount, glink_spi_channel_release); @@ -2426,7 +2414,7 @@ static void glink_spi_remove(struct glink_spi *glink) idr_destroy(&glink->lcids); idr_destroy(&glink->rcids); - spin_unlock_irqrestore(&glink->idr_lock, flags); + mutex_unlock(&glink->idr_lock); tx_pipe->fifo_base = 0; tx_pipe->local_addr = 0; -- GitLab From c19879c3d3e3d52011b3041367844a6358dc9b80 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Wed, 30 Jan 2019 17:06:14 +0530 Subject: [PATCH 1225/1286] sched: Handle partial write failures in sched_updown_migrate_handler The sched_upmigrate/sched_downmigrate tunable is set by passing two values on a tri cluster system. proc_douintvec_capacity() can return an error when any of the user specified value is out of range. However it may result in partial update to sysctl data when the 1st value is within the range but the 2nd value is not. Since an error is returned to the tunable write system call, discard the partial update to the tunable. Before this patch, > cat /proc/sys/kernel/sched_upmigrate > 95 95 > echo 99 0 > /proc/sys/kernel/sched_upmigrate > 99 95 After this patch, > cat /proc/sys/kernel/sched_upmigrate > 95 95 > echo 99 0 > /proc/sys/kernel/sched_upmigrate > 95 95 This patch also refactors sched_updown_migrate_handler() to allocate the temporary buffer only for write case. Change-Id: I3c6b7eb12c4f38823022fa6420f1d9c3c8d05796 Signed-off-by: Pavankumar Kondeti --- kernel/sched/core.c | 50 ++++++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 2563de424515..27ab3ccca44f 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -6902,8 +6902,8 @@ static void sched_update_down_migrate_values(int cap_margin_levels, } } -static int sched_update_updown_migrate_values(unsigned int *data, - int cap_margin_levels, int ret) +static void sched_update_updown_migrate_values(unsigned int *data, + int cap_margin_levels) { int i, cpu; static const struct cpumask *cluster_cpus[MAX_CLUSTERS]; @@ -6915,15 +6915,10 @@ static int sched_update_updown_migrate_values(unsigned int *data, } if (data == &sysctl_sched_capacity_margin_up[0]) - sched_update_up_migrate_values(cap_margin_levels, - cluster_cpus); - else if (data == &sysctl_sched_capacity_margin_down[0]) - sched_update_down_migrate_values(cap_margin_levels, - cluster_cpus); + sched_update_up_migrate_values(cap_margin_levels, cluster_cpus); else - ret = -EINVAL; - - return ret; + sched_update_down_migrate_values(cap_margin_levels, + cluster_cpus); } int sched_updown_migrate_handler(struct ctl_table *table, int write, @@ -6949,6 +6944,16 @@ int sched_updown_migrate_handler(struct ctl_table *table, int write, goto unlock_mutex; } + if (!write) { + ret = proc_douintvec_capacity(table, write, buffer, lenp, ppos); + goto unlock_mutex; + } + + /* + * Cache the old values so that they can be restored + * if either the write fails (for example out of range values) + * or the downmigrate and upmigrate are not in sync. + */ old_val = kzalloc(table->maxlen, GFP_KERNEL); if (!old_val) { ret = -ENOMEM; @@ -6959,19 +6964,22 @@ int sched_updown_migrate_handler(struct ctl_table *table, int write, ret = proc_douintvec_capacity(table, write, buffer, lenp, ppos); - if (!ret && write) { - for (i = 0; i < cap_margin_levels; i++) { - if (sysctl_sched_capacity_margin_up[i] > - sysctl_sched_capacity_margin_down[i]) { - memcpy(data, old_val, table->maxlen); - ret = -EINVAL; - goto free_old_val; - } - } + if (ret) { + memcpy(data, old_val, table->maxlen); + goto free_old_val; + } - ret = sched_update_updown_migrate_values(data, - cap_margin_levels, ret); + for (i = 0; i < cap_margin_levels; i++) { + if (sysctl_sched_capacity_margin_up[i] > + sysctl_sched_capacity_margin_down[i]) { + memcpy(data, old_val, table->maxlen); + ret = -EINVAL; + goto free_old_val; + } } + + sched_update_updown_migrate_values(data, cap_margin_levels); + free_old_val: kfree(old_val); unlock_mutex: -- GitLab From 758bcfa243c23c3a2a038d627b9cab4cdaf69e76 Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Wed, 30 Jan 2019 19:12:47 +0530 Subject: [PATCH 1226/1286] sched/fair: Update overutilized status after migrating tasks The enqueue_task_fair updates the overutilized status only for waking tasks. Since multiple tasks may get migrated during the load balancer, update the overutilized status after migrating all tasks. Change-Id: I2163ba8dcb7eb9677f609d19e3579867e4dff1b1 Signed-off-by: Pavankumar Kondeti --- kernel/sched/fair.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index a6d2b21a0796..f11443829c23 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -9305,6 +9305,7 @@ static void attach_one_task(struct rq *rq, struct task_struct *p) rq_lock(rq, &rf); update_rq_clock(rq); attach_task(rq, p); + update_overutilized_status(rq); rq_unlock(rq, &rf); } @@ -9328,6 +9329,13 @@ static void attach_tasks(struct lb_env *env) attach_task(env->dst_rq, p); } + /* + * The enqueue_task_fair only updates the overutilized status + * for the waking tasks. Since multiple tasks may get migrated + * from load balancer, instead of doing it there, update the + * overutilized status here at the end. + */ + update_overutilized_status(env->dst_rq); rq_unlock(env->dst_rq, &rf); } -- GitLab From ffa497414be78c550768e2e3be12063630d7cec1 Mon Sep 17 00:00:00 2001 From: Mangesh Kunchamwar Date: Thu, 10 Jan 2019 17:57:16 +0530 Subject: [PATCH 1227/1286] ARM: dts: msm: set dmic sampling rate in QCS405 Set DMIC sampling rate 600KHz for circular mic array board and 2.4MHz for linear mic array board. Change-Id: Icef2970aa703fdf7998820ed9a0c5c36b1b8eee5 Signed-off-by: Mangesh Kunchamwar --- arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi index cc872d4b4ebc..6d7d46901a13 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,6 +11,10 @@ * GNU General Public License for more details. */ +&va_macro { + qcom,va-dmic-sample-rate = <2400000>; +}; + &i2c_2 { status = "ok"; qcom,clk-freq-out = <100000>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi index 7ab4b7c9db3a..73a6e12fd8a5 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,7 +19,7 @@ va-vdd-micb-supply = <&pms405_l7>; qcom,va-vdd-micb-voltage = <1800000 1800000>; qcom,va-vdd-micb-current = <11200>; - qcom,va-dmic-sample-rate = <2400000>; + qcom,va-dmic-sample-rate = <600000>; }; }; -- GitLab From f5196ed6fe0bfae000a11b9bbea2f47e85ff9c7a Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 30 Jan 2019 23:46:41 +0530 Subject: [PATCH 1228/1286] ARM: dts: msm: Update cpu frequency cooling levels for TRINKET Update cpu cooling device levels for VDD restriction and BCL thermal zones based on latest clock plan for TRINKET. Change-Id: Ia7cf20c1c3d0e22ccafa859626adcd0066426f3b Signed-off-by: Manaf Meethalavalappu Pallikunhi --- .../dts/qcom/trinket-thermal-overlay.dtsi | 152 ++++----- arch/arm64/boot/dts/qcom/trinket-thermal.dtsi | 320 +++++++++--------- 2 files changed, 236 insertions(+), 236 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi index f4f823a1c115..413ddad6c643 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -130,50 +130,50 @@ vbat_cpu0 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu1 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu2 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu3 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu4 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu5 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU5 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu6 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU6 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; vbat_cpu7 { trip = <&pmi632_vbat_lvl0>; cooling-device = - <&CPU7 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; }; }; @@ -183,38 +183,38 @@ vbat_cpu0 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu1 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu2 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu3 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu4 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu5 { trip = <&pmi632_vbat_lvl1>; cooling-device = - <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu6 { trip = <&pmi632_vbat_lvl1>; @@ -236,26 +236,26 @@ vbat_cpu0 { trip = <&pmi632_vbat_lvl2>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu1 { trip = <&pmi632_vbat_lvl2>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu2 { trip = <&pmi632_vbat_lvl2>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu3 { trip = <&pmi632_vbat_lvl2>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; vbat_cpu4 { trip = <&pmi632_vbat_lvl2>; @@ -289,50 +289,50 @@ ibat_cpu0 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu1 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu2 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu3 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu4 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu5 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU5 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu6 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU6 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; ibat_cpu7 { trip = <&pmi632_ibat_lvl0>; cooling-device = - <&CPU7 (THERMAL_MAX_LIMIT-10) - (THERMAL_MAX_LIMIT-10)>; + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; }; }; }; @@ -342,38 +342,38 @@ ibat_cpu0 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu1 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu2 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu3 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu4 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu5 { trip = <&pmi632_ibat_lvl1>; cooling-device = - <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; ibat_cpu6 { trip = <&pmi632_ibat_lvl1>; @@ -395,38 +395,38 @@ soc_cpu0 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu1 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu2 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu3 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu4 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu5 { trip = <&pmi632_low_soc>; cooling-device = - <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; soc_cpu6 { trip = <&pmi632_low_soc>; diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi index 53b5511709f4..3fae75783964 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal.dtsi @@ -781,43 +781,43 @@ cooling-maps { cpu0_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&aoss0_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&aoss0_trip>; @@ -858,43 +858,43 @@ cooling-maps { cpu0_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&cdsp_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&cdsp_trip>; @@ -935,43 +935,43 @@ cooling-maps { cpu0_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&wlan_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&wlan_trip>; @@ -1012,43 +1012,43 @@ cooling-maps { cpu0_cdev { trip = <&camera_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&camera_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&camera_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&camera_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&camera_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&camera_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&camera_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&camera_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&camera_trip>; @@ -1089,43 +1089,43 @@ cooling-maps { cpu0_cdev { trip = <&video_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&video_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&video_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&video_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&video_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&video_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&video_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&video_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&video_trip>; @@ -1166,43 +1166,43 @@ cooling-maps { cpu0_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&cpu4_lowf_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&cpu4_lowf_trip>; @@ -1243,43 +1243,43 @@ cooling-maps { cpu0_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&cpu0_lowf_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&cpu0_lowf_trip>; @@ -1320,43 +1320,43 @@ cooling-maps { cpu0_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&mdm_core_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&mdm_core_trip>; @@ -1397,43 +1397,43 @@ cooling-maps { cpu0_cdev { trip = <&display_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&display_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&display_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&display_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&display_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&display_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&display_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&display_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&display_trip>; @@ -1474,43 +1474,43 @@ cooling-maps { cpu0_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu1_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu2_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu3_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) - (THERMAL_MAX_LIMIT-6)>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu4_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu5_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu6_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cpu7_cdev { trip = <&gpu_trip>; - cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-8) - (THERMAL_MAX_LIMIT-8)>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; }; cx_vdd_cdev { trip = <&gpu_trip>; -- GitLab From 5087fc0a6315926f3c16251df7ee38227c3b9475 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Tue, 29 Jan 2019 15:27:18 -0800 Subject: [PATCH 1229/1286] cnss2: Remove debug flag for athdiag feature Athdiag feature can be used for all configs from host side. It will be up to firmware for how to handle it properly. Change-Id: I6b283e947257ad077361d3fadf10fac4e7a2f47e Signed-off-by: Yue Ma --- drivers/net/wireless/cnss2/main.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c index aefe9c908de3..29ca1cf79c88 100644 --- a/drivers/net/wireless/cnss2/main.c +++ b/drivers/net/wireless/cnss2/main.c @@ -282,7 +282,6 @@ int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode) } EXPORT_SYMBOL(cnss_wlan_disable); -#ifdef CONFIG_CNSS2_DEBUG int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type, u32 data_len, u8 *output) { @@ -340,21 +339,6 @@ int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type, return ret; } EXPORT_SYMBOL(cnss_athdiag_write); -#else -int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type, - u32 data_len, u8 *output) -{ - return -EPERM; -} -EXPORT_SYMBOL(cnss_athdiag_read); - -int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type, - u32 data_len, u8 *input) -{ - return -EPERM; -} -EXPORT_SYMBOL(cnss_athdiag_write); -#endif int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode) { -- GitLab From 195469721bd28725866ea3c311d517051620276b Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Thu, 17 Jan 2019 19:09:30 -0800 Subject: [PATCH 1230/1286] ARM: dts: msm: Include memory map overlay changes for sm8150-sdx55 Include memory map V2 overlay changes for sm8150-sdx55 Change-Id: I307429778928fd4460d8e9322bb7bf40a43a2394 Signed-off-by: Swathi Sridhar --- .../boot/dts/qcom/sm8150-sdxprairie.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index ccefd93c160e..7e508a00a70c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -126,6 +126,38 @@ }; }; +&pil_modem_mem { + reg = <0x0 0x8d800000 0x0 0x3200000>; +}; + +&pil_video_mem { + reg = <0x0 0x90a00000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x90f00000 0x0 0x1500000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x92400000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x92410000 0x0 0xa000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x9241a000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x92500000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x92600000 0x0 0x1400000>; +}; + &audio_apr { voice_mhi_audio: qcom,voice-mhi-audio { compatible = "qcom,voice-mhi-audio"; -- GitLab From 83af67e97eb05371da28b433cb4f663c41cb8e4c Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 16 Jan 2019 19:25:27 -0800 Subject: [PATCH 1231/1286] power: battery: Fix low vote issue with FCC taper stepper While in taper mode, the effective result of FCC is obtained and a reduction of 200mA is made until the taper condition goes away. if another voter cuts in and votes lower, which results in lower FCC, a 200mA will be deducted from the new low FCC. Note the result cannot be reversed even after the vote is cancelled or updated. Occasionally, it may have undesired consequences. A very low vote voting in and out in the middle can leave a low FCC for the rest of charging cycle. Solve the problem by adopting a dedicated FCC voter in taper mode and doing the reduction with reference to its last vote. CRs-Fixed: 2357939 Change-Id: I8b0c1e353659c6368ea665471b0345aa24a92eb8 Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Harry Yang --- drivers/power/supply/qcom/battery.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/power/supply/qcom/battery.c b/drivers/power/supply/qcom/battery.c index d147466eebdb..a0aada40fb18 100644 --- a/drivers/power/supply/qcom/battery.c +++ b/drivers/power/supply/qcom/battery.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -32,6 +32,7 @@ #define DRV_MAJOR_VERSION 1 #define DRV_MINOR_VERSION 0 +#define BATT_PROFILE_VOTER "BATT_PROFILE_VOTER" #define CHG_STATE_VOTER "CHG_STATE_VOTER" #define TAPER_STEPPER_VOTER "TAPER_STEPPER_VOTER" #define TAPER_END_VOTER "TAPER_END_VOTER" @@ -576,11 +577,12 @@ static void pl_taper_work(struct work_struct *work) pl_taper_work); union power_supply_propval pval = {0, }; int rc; - int eff_fcc_ua; - int total_fcc_ua, master_fcc_ua, slave_fcc_ua = 0; + int fcc_ua, total_fcc_ua, master_fcc_ua, slave_fcc_ua = 0; chip->taper_entry_fv = get_effective_result(chip->fv_votable); chip->taper_work_running = true; + fcc_ua = get_client_vote(chip->fcc_votable, BATT_PROFILE_VOTER); + vote(chip->fcc_votable, TAPER_STEPPER_VOTER, true, fcc_ua); while (true) { if (get_effective_result(chip->pl_disable_votable)) { /* @@ -629,21 +631,22 @@ static void pl_taper_work(struct work_struct *work) chip->charge_type = pval.intval; if (pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER) { - eff_fcc_ua = get_effective_result(chip->fcc_votable); - if (eff_fcc_ua < 0) { + fcc_ua = get_client_vote(chip->fcc_votable, + TAPER_STEPPER_VOTER); + if (fcc_ua < 0) { pr_err("Couldn't get fcc, exiting taper work\n"); goto done; } - eff_fcc_ua = eff_fcc_ua - TAPER_REDUCTION_UA; - if (eff_fcc_ua < 0) { + fcc_ua -= TAPER_REDUCTION_UA; + if (fcc_ua < 0) { pr_err("Can't reduce FCC any more\n"); goto done; } pl_dbg(chip, PR_PARALLEL, "master is taper charging; reducing FCC to %dua\n", - eff_fcc_ua); + fcc_ua); vote(chip->fcc_votable, TAPER_STEPPER_VOTER, - true, eff_fcc_ua); + true, fcc_ua); } else { pl_dbg(chip, PR_PARALLEL, "master is fast charging; waiting for next taper\n"); } -- GitLab From 12f57d3a012f73413526ea2e0c72554954c206c1 Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Tue, 29 Jan 2019 14:09:16 -0800 Subject: [PATCH 1232/1286] power: smb1390: Fix low vote issue with FCC taper stepper While in taper mode, the effective result of FCC is obtained and a reduction of 100mA is made until the taper condition goes away. if another voter cuts in and votes lower, which results in lower FCC, a 100mA will be deducted from the new low FCC. Note the result cannot be reversed even after the vote is cancelled or updated. Occasionally, it may have undesired consequences. A very low vote voting in and out in the middle can leave a low FCC for the rest of charging cycle. Solve the problem by adopting a dedicated FCC voter in taper mode and doing the reduction with reference to its last vote. CRs-Fixed: 2357939 Change-Id: Ib8d35b21309e7cad0d3ae3dd81b491322bc37b51 Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Harry Yang --- drivers/power/supply/qcom/smb1390-charger.c | 22 ++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/power/supply/qcom/smb1390-charger.c b/drivers/power/supply/qcom/smb1390-charger.c index e6ab66f64e63..24de2166349a 100644 --- a/drivers/power/supply/qcom/smb1390-charger.c +++ b/drivers/power/supply/qcom/smb1390-charger.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -81,6 +81,7 @@ #define ATEST1_SEL_MASK GENMASK(6, 0) #define ISNS_INT_VAL 0x09 +#define BATT_PROFILE_VOTER "BATT_PROFILE_VOTER" #define CP_VOTER "CP_VOTER" #define USER_VOTER "USER_VOTER" #define ILIM_VOTER "ILIM_VOTER" @@ -544,7 +545,7 @@ static void smb1390_status_change_work(struct work_struct *work) struct smb1390 *chip = container_of(work, struct smb1390, status_change_work); union power_supply_propval pval = {0, }; - int rc; + int max_fcc_ma, rc; if (!is_psy_voter_available(chip)) goto out; @@ -621,7 +622,10 @@ static void smb1390_status_change_work(struct work_struct *work) } } else { vote(chip->disable_votable, SRC_VOTER, true, 0); - vote(chip->fcc_votable, CP_VOTER, false, 0); + max_fcc_ma = get_client_vote(chip->fcc_votable, + BATT_PROFILE_VOTER); + vote(chip->fcc_votable, CP_VOTER, + max_fcc_ma > 0 ? true : false, max_fcc_ma); } out: @@ -639,10 +643,16 @@ static void smb1390_taper_work(struct work_struct *work) goto out; do { - fcc_uA = get_effective_result(chip->fcc_votable) - 100000; + fcc_uA = get_effective_result(chip->fcc_votable); + if (fcc_uA < 2000000) + break; + + fcc_uA = get_client_vote(chip->fcc_votable, CP_VOTER) - 100000; pr_debug("taper work reducing FCC to %duA\n", fcc_uA); vote(chip->fcc_votable, CP_VOTER, true, fcc_uA); + msleep(500); + rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_CHARGE_TYPE, &pval); if (rc < 0) { @@ -650,9 +660,7 @@ static void smb1390_taper_work(struct work_struct *work) goto out; } - msleep(500); - } while (fcc_uA >= 2000000 - && pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER); + } while (pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER); out: pr_debug("taper work exit\n"); -- GitLab From cd180699bad64aca6ab4954bb6986c6d63e7d9f4 Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Mon, 3 Dec 2018 12:37:32 -0800 Subject: [PATCH 1233/1286] iommu: iommu-debug: Fix race conditions in iommu debug With the current support, concurrent iommu debug calls to the test device/debug domain can result in multiple race conditions between attach, map, unmap and detach calls.Hence introduce a new lock in the iommu_debug_device structure to serialize iommu calls to the test device. Change-Id: I94cd36eeaba4208972fdfa49ca4446a08d53b334 Signed-off-by: Swathi Sridhar --- drivers/iommu/iommu-debug.c | 70 ++++++++++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/iommu-debug.c b/drivers/iommu/iommu-debug.c index 90c0befee18f..14c4a56deeb1 100644 --- a/drivers/iommu/iommu-debug.c +++ b/drivers/iommu/iommu-debug.c @@ -172,6 +172,7 @@ struct iommu_debug_device { struct list_head list; struct mutex clk_lock; unsigned int clk_count; + struct mutex debug_dev_lock; }; static int iommu_debug_build_phoney_sg_table(struct device *dev, @@ -435,8 +436,10 @@ static int iommu_debug_profiling_show(struct seq_file *s, void *ignored) int htw_disable = 1, atomic = 1; void *attr_values[] = { &htw_disable, &atomic }; + mutex_lock(&ddev->debug_dev_lock); iommu_debug_device_profiling(s, ddev->dev, attrs, attr_values, ARRAY_SIZE(attrs), sizes); + mutex_unlock(&ddev->debug_dev_lock); return 0; } @@ -466,9 +469,10 @@ static int iommu_debug_secure_profiling_show(struct seq_file *s, void *ignored) int one = 1, secure_vmid = VMID_CP_PIXEL; void *attr_values[] = { &one, &secure_vmid }; + mutex_lock(&ddev->debug_dev_lock); iommu_debug_device_profiling(s, ddev->dev, attrs, attr_values, ARRAY_SIZE(attrs), sizes); - + mutex_unlock(&ddev->debug_dev_lock); return 0; } @@ -497,9 +501,10 @@ static int iommu_debug_profiling_fast_show(struct seq_file *s, void *ignored) int one = 1; void *attr_values[] = { &one, &one }; + mutex_lock(&ddev->debug_dev_lock); iommu_debug_device_profiling(s, ddev->dev, attrs, attr_values, ARRAY_SIZE(attrs), sizes); - + mutex_unlock(&ddev->debug_dev_lock); return 0; } @@ -1315,6 +1320,7 @@ static ssize_t __iommu_debug_dma_attach_write(struct file *file, ssize_t retval = -EINVAL; int val; + mutex_lock(&ddev->debug_dev_lock); if (kstrtoint_from_user(ubuf, count, 0, &val)) { pr_err("Invalid format. Expected a hex or decimal integer"); retval = -EFAULT; @@ -1363,11 +1369,13 @@ static ssize_t __iommu_debug_dma_attach_write(struct file *file, pr_err("Detached\n"); } retval = count; + mutex_unlock(&ddev->debug_dev_lock); return retval; out_release_mapping: arm_iommu_release_mapping(dma_mapping); out: + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1382,6 +1390,7 @@ static ssize_t __iommu_debug_attach_write(struct file *file, ssize_t retval; int val; + mutex_lock(&ddev->debug_dev_lock); if (kstrtoint_from_user(ubuf, count, 0, &val)) { pr_err("Invalid format. Expected a hex or decimal integer"); retval = -EFAULT; @@ -1421,6 +1430,7 @@ static ssize_t __iommu_debug_attach_write(struct file *file, retval = count; out: + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1585,17 +1595,23 @@ static ssize_t iommu_debug_pte_read(struct file *file, char __user *ubuf, pr_err("kptr_restrict needs to be disabled.\n"); return -EPERM; } + + mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { pr_err("No mapping. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (!dev->archdata.mapping->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } - if (*offset) + if (*offset) { + mutex_unlock(&ddev->debug_dev_lock); return 0; + } memset(buf, 0, sizeof(buf)); @@ -1615,7 +1631,7 @@ static ssize_t iommu_debug_pte_read(struct file *file, char __user *ubuf, *offset = 1; /* non-zero means we're done */ retval = buflen; } - + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1656,13 +1672,18 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, pr_err("kptr_restrict needs to be disabled.\n"); return -EPERM; } + + mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } - if (*offset) + if (*offset) { + mutex_unlock(&ddev->debug_dev_lock); return 0; + } memset(buf, 0, 100); @@ -1685,6 +1706,7 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, retval = buflen; } + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1708,18 +1730,23 @@ static ssize_t iommu_debug_dma_atos_read(struct file *file, char __user *ubuf, pr_err("kptr_restrict needs to be disabled.\n"); return -EPERM; } + + mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { pr_err("No mapping. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (!dev->archdata.mapping->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } - if (*offset) + if (*offset) { + mutex_unlock(&ddev->debug_dev_lock); return 0; - + } memset(buf, 0, sizeof(buf)); phys = iommu_iova_to_phys_hard(dev->archdata.mapping->domain, @@ -1737,7 +1764,7 @@ static ssize_t iommu_debug_dma_atos_read(struct file *file, char __user *ubuf, *offset = 1; /* non-zero means we're done */ retval = buflen; } - + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1765,8 +1792,10 @@ static ssize_t iommu_debug_map_write(struct file *file, const char __user *ubuf, return -EINVAL; } + mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1815,10 +1844,12 @@ static ssize_t iommu_debug_map_write(struct file *file, const char __user *ubuf, pr_err("Mapped %pa to %pa (len=0x%zx, prot=0x%x)\n", &iova, &phys, size, prot); out: + mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: pr_err("Invalid format. Expected: iova,phys,len,prot where `prot' is the bitwise OR of IOMMU_READ, IOMMU_WRITE, etc.\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1856,6 +1887,7 @@ static ssize_t iommu_debug_dma_map_write(struct file *file, return -EINVAL; } + mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { pr_err("No mapping. Did you already attach?\n"); retval = -EINVAL; @@ -1924,14 +1956,17 @@ static ssize_t iommu_debug_dma_map_write(struct file *file, ddev->iova = iova; pr_err("Saved iova=%pa for future PTE commands\n", &iova); out: + mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: pr_err("Invalid format. Expected: addr,len,dma attr where 'dma attr' is\n0: normal mapping\n1: force coherent\n2: force non-cohernet\n3: use system cache\n"); + mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_addr: pr_err("Invalid addr given! Address should be within 1MB size from start addr returned by doing 'cat test_virt_addr'.\n"); + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1997,8 +2032,10 @@ static ssize_t iommu_debug_unmap_write(struct file *file, return -EINVAL; } + mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -2027,16 +2064,19 @@ static ssize_t iommu_debug_unmap_write(struct file *file, if (unmapped != size) { pr_err("iommu_unmap failed. Expected to unmap: 0x%zx, unmapped: 0x%zx", size, unmapped); + mutex_unlock(&ddev->debug_dev_lock); return -EIO; } retval = count; pr_err("Unmapped %pa (len=0x%zx)\n", &iova, size); out: + mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: pr_err("Invalid format. Expected: iova,len\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -2064,6 +2104,7 @@ static ssize_t iommu_debug_dma_unmap_write(struct file *file, return -EINVAL; } + mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { pr_err("No mapping. Did you already attach?\n"); retval = -EINVAL; @@ -2118,10 +2159,12 @@ static ssize_t iommu_debug_dma_unmap_write(struct file *file, retval = count; pr_err("Unmapped %pa (len=0x%zx)\n", &iova, size); out: + mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: pr_err("Invalid format. Expected: iova,len, dma attr\n"); + mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -2144,13 +2187,16 @@ static ssize_t iommu_debug_config_clocks_write(struct file *file, return -EINVAL; } + mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { dev_err(dev, "No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (copy_from_user(&buf, ubuf, 1)) { dev_err(dev, "Couldn't copy from user\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EFAULT; } @@ -2179,10 +2225,11 @@ static ssize_t iommu_debug_config_clocks_write(struct file *file, default: dev_err(dev, "Invalid value. Should be 0 or 1.\n"); mutex_unlock(&ddev->clk_lock); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } mutex_unlock(&ddev->clk_lock); - + mutex_unlock(&ddev->debug_dev_lock); return count; } @@ -2198,17 +2245,21 @@ static ssize_t iommu_debug_trigger_fault_write( struct iommu_debug_device *ddev = file->private_data; unsigned long flags; + mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { pr_err("No domain. Did you already attach?\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (kstrtoul_from_user(ubuf, count, 0, &flags)) { pr_err("Invalid flags format\n"); + mutex_unlock(&ddev->debug_dev_lock); return -EFAULT; } iommu_trigger_fault(ddev->domain, flags); + mutex_unlock(&ddev->debug_dev_lock); return count; } @@ -2243,6 +2294,7 @@ static int snarf_iommu_devices(struct device *dev, void *ignored) return -ENODEV; mutex_init(&ddev->clk_lock); + mutex_init(&ddev->debug_dev_lock); ddev->dev = dev; dir = debugfs_create_dir(dev_name(dev), debugfs_tests_dir); if (!dir) { -- GitLab From 313692340c61c97b3f384701a9ea92ca5d8ff9f5 Mon Sep 17 00:00:00 2001 From: Swathi Sridhar Date: Wed, 5 Dec 2018 18:28:13 -0800 Subject: [PATCH 1234/1286] iommu: iommu-debug: Use ratelimited versions of pr_err and dev_err Use ratelimited versions of pr_err and dev_err in functions which are a part of the iommu-debug framework so as to prevent issues caused by excessive logging. Change-Id: I2293198a1de4619b0b30c3f7dc4e8275abe93ab7 Signed-off-by: Swathi Sridhar --- drivers/iommu/iommu-debug.c | 228 ++++++++++++++++++------------------ 1 file changed, 115 insertions(+), 113 deletions(-) diff --git a/drivers/iommu/iommu-debug.c b/drivers/iommu/iommu-debug.c index 14c4a56deeb1..de6f71461769 100644 --- a/drivers/iommu/iommu-debug.c +++ b/drivers/iommu/iommu-debug.c @@ -664,14 +664,14 @@ static int __tlb_stress_sweep(struct device *dev, struct seq_file *s) for (iova = 0, i = 0; iova < max; iova += SZ_8K, ++i) { dma_addr = dma_map_single(dev, virt, SZ_8K, DMA_TO_DEVICE); if (dma_addr == DMA_ERROR_CODE) { - dev_err(dev, "Failed map on iter %d\n", i); + dev_err_ratelimited(dev, "Failed map on iter %d\n", i); ret = -EINVAL; goto out; } } if (dma_map_single(dev, virt, SZ_4K, DMA_TO_DEVICE) != DMA_ERROR_CODE) { - dev_err(dev, + dev_err_ratelimited(dev, "dma_map_single unexpectedly (VA should have been exhausted)\n"); ret = -EINVAL; goto out; @@ -691,7 +691,7 @@ static int __tlb_stress_sweep(struct device *dev, struct seq_file *s) if (dma_addr != SZ_8K) { dma_addr_t expected = SZ_8K; - dev_err(dev, "Unexpected dma_addr. got: %pa expected: %pa\n", + dev_err_ratelimited(dev, "Unexpected dma_addr. got: %pa expected: %pa\n", &dma_addr, &expected); ret = -EINVAL; goto out; @@ -706,14 +706,14 @@ static int __tlb_stress_sweep(struct device *dev, struct seq_file *s) if (dma_addr != 0) { dma_addr_t expected = 0; - dev_err(dev, "Unexpected dma_addr. got: %pa expected: %pa\n", + dev_err_ratelimited(dev, "Unexpected dma_addr. got: %pa expected: %pa\n", &dma_addr, &expected); ret = -EINVAL; goto out; } if (dma_map_single(dev, virt, SZ_4K, DMA_TO_DEVICE) != DMA_ERROR_CODE) { - dev_err(dev, + dev_err_ratelimited(dev, "dma_map_single unexpectedly after remaps (VA should have been exhausted)\n"); ret = -EINVAL; goto out; @@ -763,7 +763,7 @@ static int __rand_va_sweep(struct device *dev, struct seq_file *s, virt = (void *)__get_free_pages(GFP_KERNEL, get_order(size)); if (!virt) { if (size > SZ_8K) { - dev_err(dev, + dev_err_ratelimited(dev, "Failed to allocate %s of memory, which is a lot. Skipping test for this size\n", _size_to_string(size)); return 0; @@ -775,7 +775,7 @@ static int __rand_va_sweep(struct device *dev, struct seq_file *s, for (iova = 0, i = 0; iova < max; iova += size, ++i) { dma_addr = dma_map_single(dev, virt, size, DMA_TO_DEVICE); if (dma_addr == DMA_ERROR_CODE) { - dev_err(dev, "Failed map on iter %d\n", i); + dev_err_ratelimited(dev, "Failed map on iter %d\n", i); ret = -EINVAL; goto out; } @@ -808,7 +808,7 @@ static int __rand_va_sweep(struct device *dev, struct seq_file *s, } if (unmapped != remapped) { - dev_err(dev, + dev_err_ratelimited(dev, "Unexpected random remap count! Unmapped %d but remapped %d\n", unmapped, remapped); ret = -EINVAL; @@ -853,7 +853,7 @@ static int __full_va_sweep(struct device *dev, struct seq_file *s, virt = (void *)__get_free_pages(GFP_KERNEL, get_order(size)); if (!virt) { if (size > SZ_8K) { - dev_err(dev, + dev_err_ratelimited(dev, "Failed to allocate %s of memory, which is a lot. Skipping test for this size\n", _size_to_string(size)); return 0; @@ -882,7 +882,7 @@ static int __full_va_sweep(struct device *dev, struct seq_file *s, phys_addr_t expected = phys; if (__check_mapping(dev, domain, iova, expected)) { - dev_err(dev, "iter: %d\n", i); + dev_err_ratelimited(dev, "iter: %d\n", i); ret = -EINVAL; goto out; } @@ -893,7 +893,7 @@ static int __full_va_sweep(struct device *dev, struct seq_file *s, unsigned long theiova = ((SZ_1G * 4ULL) - size) - iova; if (__check_mapping(dev, domain, theiova, expected)) { - dev_err(dev, "iter: %d\n", i); + dev_err_ratelimited(dev, "iter: %d\n", i); ret = -EINVAL; goto out; } @@ -1052,7 +1052,7 @@ static int __functional_dma_api_basic_test(struct device *dev, pa = iommu_iova_to_phys(domain, iova); pa2 = iommu_iova_to_phys_hard(domain, iova); if (pa != pa2) { - dev_err(dev, + dev_err_ratelimited(dev, "iova_to_phys doesn't match iova_to_phys_hard: %pa != %pa\n", &pa, &pa2); ret = -EINVAL; @@ -1060,7 +1060,7 @@ static int __functional_dma_api_basic_test(struct device *dev, } pa2 = virt_to_phys(data); if (pa != pa2) { - dev_err(dev, + dev_err_ratelimited(dev, "iova_to_phys doesn't match virt_to_phys: %pa != %pa\n", &pa, &pa2); ret = -EINVAL; @@ -1069,7 +1069,8 @@ static int __functional_dma_api_basic_test(struct device *dev, dma_unmap_single(dev, iova, size, DMA_TO_DEVICE); for (j = 0; j < size; ++j) { if (data[j] != 0xa5) { - dev_err(dev, "data[%d] != 0xa5\n", data[j]); + dev_err_ratelimited(dev, + "data[%d] != 0xa5\n", data[j]); ret = -EINVAL; goto out; } @@ -1124,7 +1125,7 @@ static int __functional_dma_api_map_sg_test(struct device *dev, pa = iommu_iova_to_phys(domain, iova); pa2 = iommu_iova_to_phys_hard(domain, iova); if (pa != pa2) { - dev_err(dev, + dev_err_ratelimited(dev, "iova_to_phys doesn't match iova_to_phys_hard: %pa != %pa\n", &pa, &pa2); ret = -EINVAL; @@ -1135,7 +1136,7 @@ static int __functional_dma_api_map_sg_test(struct device *dev, pa = iommu_iova_to_phys(domain, iova); pa2 = iommu_iova_to_phys_hard(domain, iova); if (pa != pa2) { - dev_err(dev, + dev_err_ratelimited(dev, "iova_to_phys doesn't match iova_to_phys_hard: %pa != %pa\n", &pa, &pa2); ret = -EINVAL; @@ -1190,7 +1191,7 @@ static int __apply_to_new_mapping(struct seq_file *s, goto out_release_mapping; } - dev_err(dev, "testing with pgtables at %pa\n", &pt_phys); + dev_err_ratelimited(dev, "testing with pgtables at %pa\n", &pt_phys); if (iommu_enable_config_clocks(mapping->domain)) { ds_printf(dev, s, "Couldn't enable clocks\n"); goto out_release_mapping; @@ -1284,7 +1285,7 @@ static int iommu_debug_attach_do_attach(struct iommu_debug_device *ddev, ddev->domain = iommu_domain_alloc(&platform_bus_type); if (!ddev->domain) { - pr_err("Couldn't allocate domain\n"); + pr_err_ratelimited("Couldn't allocate domain\n"); return -ENOMEM; } @@ -1293,12 +1294,12 @@ static int iommu_debug_attach_do_attach(struct iommu_debug_device *ddev, if (is_secure && iommu_domain_set_attr(ddev->domain, DOMAIN_ATTR_SECURE_VMID, &val)) { - pr_err("Couldn't set secure vmid to %d\n", val); + pr_err_ratelimited("Couldn't set secure vmid to %d\n", val); goto out_domain_free; } if (iommu_attach_group(ddev->domain, group)) { - dev_err(ddev->dev, "Couldn't attach new domain to device\n"); + dev_err_ratelimited(ddev->dev, "Couldn't attach new domain to device\n"); goto out_domain_free; } @@ -1322,7 +1323,7 @@ static ssize_t __iommu_debug_dma_attach_write(struct file *file, mutex_lock(&ddev->debug_dev_lock); if (kstrtoint_from_user(ubuf, count, 0, &val)) { - pr_err("Invalid format. Expected a hex or decimal integer"); + pr_err_ratelimited("Invalid format. Expected a hex or decimal integer"); retval = -EFAULT; goto out; } @@ -1330,7 +1331,7 @@ static ssize_t __iommu_debug_dma_attach_write(struct file *file, if (val) { if (dev->archdata.mapping) if (dev->archdata.mapping->domain) { - pr_err("Already attached.\n"); + pr_err_ratelimited("Already attached.\n"); retval = -EINVAL; goto out; } @@ -1352,21 +1353,21 @@ static ssize_t __iommu_debug_dma_attach_write(struct file *file, goto out_release_mapping; ddev->mapping = dma_mapping; - pr_err("Attached\n"); + pr_err_ratelimited("Attached\n"); } else { if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); retval = -EINVAL; goto out; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); retval = -EINVAL; goto out; } arm_iommu_detach_device(dev); arm_iommu_release_mapping(ddev->mapping); - pr_err("Detached\n"); + pr_err_ratelimited("Detached\n"); } retval = count; mutex_unlock(&ddev->debug_dev_lock); @@ -1392,21 +1393,21 @@ static ssize_t __iommu_debug_attach_write(struct file *file, mutex_lock(&ddev->debug_dev_lock); if (kstrtoint_from_user(ubuf, count, 0, &val)) { - pr_err("Invalid format. Expected a hex or decimal integer"); + pr_err_ratelimited("Invalid format. Expected a hex or decimal integer"); retval = -EFAULT; goto out; } if (val) { if (ddev->domain) { - pr_err("Iommu-Debug is already attached?\n"); + pr_err_ratelimited("Iommu-Debug is already attached?\n"); retval = -EINVAL; goto out; } domain = iommu_get_domain_for_dev(dev); if (domain) { - pr_err("Another driver is using this device's iommu\n" + pr_err_ratelimited("Another driver is using this device's iommu\n" "Iommu-Debug cannot be used concurrently\n"); retval = -EINVAL; goto out; @@ -1415,17 +1416,17 @@ static ssize_t __iommu_debug_attach_write(struct file *file, retval = -EIO; goto out; } - pr_err("Attached\n"); + pr_err_ratelimited("Attached\n"); } else { if (!ddev->domain) { - pr_err("Iommu-Debug is not attached?\n"); + pr_err_ratelimited("Iommu-Debug is not attached?\n"); retval = -EINVAL; goto out; } iommu_detach_group(ddev->domain, dev->iommu_group); iommu_domain_free(ddev->domain); ddev->domain = NULL; - pr_err("Detached\n"); + pr_err_ratelimited("Detached\n"); } retval = count; @@ -1461,7 +1462,7 @@ static ssize_t iommu_debug_dma_attach_read(struct file *file, char __user *ubuf, c[1] = '\n'; buflen = min(count, buflen); if (copy_to_user(ubuf, &c, buflen)) { - pr_err("copy_to_user failed\n"); + pr_err_ratelimited("copy_to_user failed\n"); return -EFAULT; } *offset = 1; /* non-zero means we're done */ @@ -1496,7 +1497,7 @@ static ssize_t iommu_debug_test_virt_addr_read(struct file *file, buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { - pr_err("Couldn't copy_to_user\n"); + pr_err_ratelimited("Couldn't copy_to_user\n"); retval = -EFAULT; } else { *offset = 1; /* non-zero means we're done */ @@ -1534,7 +1535,7 @@ static ssize_t iommu_debug_attach_read(struct file *file, char __user *ubuf, c[1] = '\n'; buflen = min(count, buflen); if (copy_to_user(ubuf, &c, buflen)) { - pr_err("copy_to_user failed\n"); + pr_err_ratelimited("copy_to_user failed\n"); return -EFAULT; } *offset = 1; /* non-zero means we're done */ @@ -1570,13 +1571,13 @@ static ssize_t iommu_debug_pte_write(struct file *file, dma_addr_t iova; if (kstrtox_from_user(ubuf, count, 0, &iova)) { - pr_err("Invalid format for iova\n"); + pr_err_ratelimited("Invalid format for iova\n"); ddev->iova = 0; return -EINVAL; } ddev->iova = iova; - pr_err("Saved iova=%pa for future PTE commands\n", &iova); + pr_err_ratelimited("Saved iova=%pa for future PTE commands\n", &iova); return count; } @@ -1592,18 +1593,18 @@ static ssize_t iommu_debug_pte_read(struct file *file, char __user *ubuf, size_t buflen; if (kptr_restrict != 0) { - pr_err("kptr_restrict needs to be disabled.\n"); + pr_err_ratelimited("kptr_restrict needs to be disabled.\n"); return -EPERM; } mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1625,7 +1626,7 @@ static ssize_t iommu_debug_pte_read(struct file *file, char __user *ubuf, buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { - pr_err("Couldn't copy_to_user\n"); + pr_err_ratelimited("Couldn't copy_to_user\n"); retval = -EFAULT; } else { *offset = 1; /* non-zero means we're done */ @@ -1649,13 +1650,13 @@ static ssize_t iommu_debug_atos_write(struct file *file, dma_addr_t iova; if (kstrtox_from_user(ubuf, count, 0, &iova)) { - pr_err("Invalid format for iova\n"); + pr_err_ratelimited("Invalid format for iova\n"); ddev->iova = 0; return -EINVAL; } ddev->iova = iova; - pr_err("Saved iova=%pa for future ATOS commands\n", &iova); + pr_err_ratelimited("Saved iova=%pa for future ATOS commands\n", &iova); return count; } @@ -1669,13 +1670,13 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, size_t buflen; if (kptr_restrict != 0) { - pr_err("kptr_restrict needs to be disabled.\n"); + pr_err_ratelimited("kptr_restrict needs to be disabled.\n"); return -EPERM; } mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1691,7 +1692,7 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, if (!phys) { strlcpy(buf, "FAIL\n", 100); phys = iommu_iova_to_phys(ddev->domain, ddev->iova); - dev_err(ddev->dev, "ATOS for %pa failed. Software walk returned: %pa\n", + dev_err_ratelimited(ddev->dev, "ATOS for %pa failed. Software walk returned: %pa\n", &ddev->iova, &phys); } else { snprintf(buf, 100, "%pa\n", &phys); @@ -1699,7 +1700,7 @@ static ssize_t iommu_debug_atos_read(struct file *file, char __user *ubuf, buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { - pr_err("Couldn't copy_to_user\n"); + pr_err_ratelimited("Couldn't copy_to_user\n"); retval = -EFAULT; } else { *offset = 1; /* non-zero means we're done */ @@ -1727,18 +1728,18 @@ static ssize_t iommu_debug_dma_atos_read(struct file *file, char __user *ubuf, size_t buflen; if (kptr_restrict != 0) { - pr_err("kptr_restrict needs to be disabled.\n"); + pr_err_ratelimited("kptr_restrict needs to be disabled.\n"); return -EPERM; } mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1758,7 +1759,7 @@ static ssize_t iommu_debug_dma_atos_read(struct file *file, char __user *ubuf, buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { - pr_err("Couldn't copy_to_user\n"); + pr_err_ratelimited("Couldn't copy_to_user\n"); retval = -EFAULT; } else { *offset = 1; /* non-zero means we're done */ @@ -1788,13 +1789,13 @@ static ssize_t iommu_debug_map_write(struct file *file, const char __user *ubuf, struct iommu_debug_device *ddev = file->private_data; if (count >= 100) { - pr_err("Value too large\n"); + pr_err_ratelimited("Value too large\n"); return -EINVAL; } mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1802,7 +1803,7 @@ static ssize_t iommu_debug_map_write(struct file *file, const char __user *ubuf, memset(buf, 0, 100); if (copy_from_user(buf, ubuf, count)) { - pr_err("Couldn't copy from user\n"); + pr_err_ratelimited("Couldn't copy from user\n"); retval = -EFAULT; } @@ -1835,20 +1836,20 @@ static ssize_t iommu_debug_map_write(struct file *file, const char __user *ubuf, ret = iommu_map(ddev->domain, iova, phys, size, prot); if (ret) { - pr_err("iommu_map failed with %d\n", ret); + pr_err_ratelimited("iommu_map failed with %d\n", ret); retval = -EIO; goto out; } retval = count; - pr_err("Mapped %pa to %pa (len=0x%zx, prot=0x%x)\n", + pr_err_ratelimited("Mapped %pa to %pa (len=0x%zx, prot=0x%x)\n", &iova, &phys, size, prot); out: mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: - pr_err("Invalid format. Expected: iova,phys,len,prot where `prot' is the bitwise OR of IOMMU_READ, IOMMU_WRITE, etc.\n"); + pr_err_ratelimited("Invalid format. Expected: iova,phys,len,prot where `prot' is the bitwise OR of IOMMU_READ, IOMMU_WRITE, etc.\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -1883,18 +1884,18 @@ static ssize_t iommu_debug_dma_map_write(struct file *file, struct device *dev = ddev->dev; if (count >= sizeof(buf)) { - pr_err("Value too large\n"); + pr_err_ratelimited("Value too large\n"); return -EINVAL; } mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); retval = -EINVAL; goto out; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); retval = -EINVAL; goto out; } @@ -1902,7 +1903,7 @@ static ssize_t iommu_debug_dma_map_write(struct file *file, memset(buf, 0, sizeof(buf)); if (copy_from_user(buf, ubuf, count)) { - pr_err("Couldn't copy from user\n"); + pr_err_ratelimited("Couldn't copy from user\n"); retval = -EFAULT; goto out; } @@ -1945,27 +1946,28 @@ static ssize_t iommu_debug_dma_map_write(struct file *file, DMA_TO_DEVICE, dma_attrs); if (dma_mapping_error(dev, iova)) { - pr_err("Failed to perform dma_map_single\n"); + pr_err_ratelimited("Failed to perform dma_map_single\n"); ret = -EINVAL; goto out; } retval = count; - pr_err("Mapped 0x%p to %pa (len=0x%zx)\n", + pr_err_ratelimited("Mapped 0x%p to %pa (len=0x%zx)\n", v_addr, &iova, size); ddev->iova = iova; - pr_err("Saved iova=%pa for future PTE commands\n", &iova); + pr_err_ratelimited("Saved iova=%pa for future PTE commands\n", + &iova); out: mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: - pr_err("Invalid format. Expected: addr,len,dma attr where 'dma attr' is\n0: normal mapping\n1: force coherent\n2: force non-cohernet\n3: use system cache\n"); + pr_err_ratelimited("Invalid format. Expected: addr,len,dma attr where 'dma attr' is\n0: normal mapping\n1: force coherent\n2: force non-cohernet\n3: use system cache\n"); mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_addr: - pr_err("Invalid addr given! Address should be within 1MB size from start addr returned by doing 'cat test_virt_addr'.\n"); + pr_err_ratelimited("Invalid addr given! Address should be within 1MB size from start addr returned by doing 'cat test_virt_addr'.\n"); mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -1981,11 +1983,11 @@ static ssize_t iommu_debug_dma_map_read(struct file *file, char __user *ubuf, dma_addr_t iova; if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); return -EINVAL; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); return -EINVAL; } @@ -1999,7 +2001,7 @@ static ssize_t iommu_debug_dma_map_read(struct file *file, char __user *ubuf, buflen = min(count, strlen(buf)+1); if (copy_to_user(ubuf, buf, buflen)) { - pr_err("Couldn't copy_to_user\n"); + pr_err_ratelimited("Couldn't copy_to_user\n"); retval = -EFAULT; } else { *offset = 1; /* non-zero means we're done */ @@ -2028,13 +2030,13 @@ static ssize_t iommu_debug_unmap_write(struct file *file, struct iommu_debug_device *ddev = file->private_data; if (count >= 100) { - pr_err("Value too large\n"); + pr_err_ratelimited("Value too large\n"); return -EINVAL; } mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -2042,7 +2044,7 @@ static ssize_t iommu_debug_unmap_write(struct file *file, memset(buf, 0, 100); if (copy_from_user(buf, ubuf, count)) { - pr_err("Couldn't copy from user\n"); + pr_err_ratelimited("Couldn't copy from user\n"); retval = -EFAULT; goto out; } @@ -2062,20 +2064,20 @@ static ssize_t iommu_debug_unmap_write(struct file *file, unmapped = iommu_unmap(ddev->domain, iova, size); if (unmapped != size) { - pr_err("iommu_unmap failed. Expected to unmap: 0x%zx, unmapped: 0x%zx", + pr_err_ratelimited("iommu_unmap failed. Expected to unmap: 0x%zx, unmapped: 0x%zx", size, unmapped); mutex_unlock(&ddev->debug_dev_lock); return -EIO; } retval = count; - pr_err("Unmapped %pa (len=0x%zx)\n", &iova, size); + pr_err_ratelimited("Unmapped %pa (len=0x%zx)\n", &iova, size); out: mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: - pr_err("Invalid format. Expected: iova,len\n"); + pr_err_ratelimited("Invalid format. Expected: iova,len\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } @@ -2100,18 +2102,18 @@ static ssize_t iommu_debug_dma_unmap_write(struct file *file, struct device *dev = ddev->dev; if (count >= sizeof(buf)) { - pr_err("Value too large\n"); + pr_err_ratelimited("Value too large\n"); return -EINVAL; } mutex_lock(&ddev->debug_dev_lock); if (!dev->archdata.mapping) { - pr_err("No mapping. Did you already attach?\n"); + pr_err_ratelimited("No mapping. Did you already attach?\n"); retval = -EINVAL; goto out; } if (!dev->archdata.mapping->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); retval = -EINVAL; goto out; } @@ -2119,7 +2121,7 @@ static ssize_t iommu_debug_dma_unmap_write(struct file *file, memset(buf, 0, sizeof(buf)); if (copy_from_user(buf, ubuf, count)) { - pr_err("Couldn't copy from user\n"); + pr_err_ratelimited("Couldn't copy from user\n"); retval = -EFAULT; goto out; } @@ -2157,13 +2159,13 @@ static ssize_t iommu_debug_dma_unmap_write(struct file *file, dma_unmap_single_attrs(dev, iova, size, DMA_TO_DEVICE, dma_attrs); retval = count; - pr_err("Unmapped %pa (len=0x%zx)\n", &iova, size); + pr_err_ratelimited("Unmapped %pa (len=0x%zx)\n", &iova, size); out: mutex_unlock(&ddev->debug_dev_lock); return retval; invalid_format: - pr_err("Invalid format. Expected: iova,len, dma attr\n"); + pr_err_ratelimited("Invalid format. Expected: iova,len, dma attr\n"); mutex_unlock(&ddev->debug_dev_lock); return retval; } @@ -2183,19 +2185,19 @@ static ssize_t iommu_debug_config_clocks_write(struct file *file, /* we're expecting a single character plus (optionally) a newline */ if (count > 2) { - dev_err(dev, "Invalid value\n"); + dev_err_ratelimited(dev, "Invalid value\n"); return -EINVAL; } mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { - dev_err(dev, "No domain. Did you already attach?\n"); + dev_err_ratelimited(dev, "No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (copy_from_user(&buf, ubuf, 1)) { - dev_err(dev, "Couldn't copy from user\n"); + dev_err_ratelimited(dev, "Couldn't copy from user\n"); mutex_unlock(&ddev->debug_dev_lock); return -EFAULT; } @@ -2204,26 +2206,26 @@ static ssize_t iommu_debug_config_clocks_write(struct file *file, switch (buf) { case '0': if (ddev->clk_count == 0) { - dev_err(dev, "Config clocks already disabled\n"); + dev_err_ratelimited(dev, "Config clocks already disabled\n"); break; } if (--ddev->clk_count > 0) break; - dev_err(dev, "Disabling config clocks\n"); + dev_err_ratelimited(dev, "Disabling config clocks\n"); iommu_disable_config_clocks(ddev->domain); break; case '1': if (ddev->clk_count++ > 0) break; - dev_err(dev, "Enabling config clocks\n"); + dev_err_ratelimited(dev, "Enabling config clocks\n"); if (iommu_enable_config_clocks(ddev->domain)) - dev_err(dev, "Failed!\n"); + dev_err_ratelimited(dev, "Failed!\n"); break; default: - dev_err(dev, "Invalid value. Should be 0 or 1.\n"); + dev_err_ratelimited(dev, "Invalid value. Should be 0 or 1.\n"); mutex_unlock(&ddev->clk_lock); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; @@ -2247,13 +2249,13 @@ static ssize_t iommu_debug_trigger_fault_write( mutex_lock(&ddev->debug_dev_lock); if (!ddev->domain) { - pr_err("No domain. Did you already attach?\n"); + pr_err_ratelimited("No domain. Did you already attach?\n"); mutex_unlock(&ddev->debug_dev_lock); return -EINVAL; } if (kstrtoul_from_user(ubuf, count, 0, &flags)) { - pr_err("Invalid flags format\n"); + pr_err_ratelimited("Invalid flags format\n"); mutex_unlock(&ddev->debug_dev_lock); return -EFAULT; } @@ -2298,147 +2300,147 @@ static int snarf_iommu_devices(struct device *dev, void *ignored) ddev->dev = dev; dir = debugfs_create_dir(dev_name(dev), debugfs_tests_dir); if (!dir) { - pr_err("Couldn't create iommu/devices/%s debugfs dir\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s debugfs dir\n", dev_name(dev)); goto err; } if (!debugfs_create_file("nr_iters", 0400, dir, &iters_per_op, &iommu_debug_nr_iters_ops)) { - pr_err("Couldn't create iommu/devices/%s/nr_iters debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/nr_iters debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("test_virt_addr", 0400, dir, ddev, &iommu_debug_test_virt_addr_fops)) { - pr_err("Couldn't create iommu/devices/%s/test_virt_addr debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/test_virt_addr debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("profiling", 0400, dir, ddev, &iommu_debug_profiling_fops)) { - pr_err("Couldn't create iommu/devices/%s/profiling debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/profiling debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("secure_profiling", 0400, dir, ddev, &iommu_debug_secure_profiling_fops)) { - pr_err("Couldn't create iommu/devices/%s/secure_profiling debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/secure_profiling debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("profiling_fast", 0400, dir, ddev, &iommu_debug_profiling_fast_fops)) { - pr_err("Couldn't create iommu/devices/%s/profiling_fast debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/profiling_fast debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("profiling_fast_dma_api", 0400, dir, ddev, &iommu_debug_profiling_fast_dma_api_fops)) { - pr_err("Couldn't create iommu/devices/%s/profiling_fast_dma_api debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/profiling_fast_dma_api debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("functional_fast_dma_api", 0400, dir, ddev, &iommu_debug_functional_fast_dma_api_fops)) { - pr_err("Couldn't create iommu/devices/%s/functional_fast_dma_api debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/functional_fast_dma_api debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("functional_arm_dma_api", 0400, dir, ddev, &iommu_debug_functional_arm_dma_api_fops)) { - pr_err("Couldn't create iommu/devices/%s/functional_arm_dma_api debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/functional_arm_dma_api debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("dma_attach", 0600, dir, ddev, &iommu_debug_dma_attach_fops)) { - pr_err("Couldn't create iommu/devices/%s/dma_attach debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/dma_attach debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("attach", 0400, dir, ddev, &iommu_debug_attach_fops)) { - pr_err("Couldn't create iommu/devices/%s/attach debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/attach debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("secure_attach", 0400, dir, ddev, &iommu_debug_secure_attach_fops)) { - pr_err("Couldn't create iommu/devices/%s/secure_attach debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/secure_attach debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("atos", 0200, dir, ddev, &iommu_debug_atos_fops)) { - pr_err("Couldn't create iommu/devices/%s/atos debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/atos debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("dma_atos", 0600, dir, ddev, &iommu_debug_dma_atos_fops)) { - pr_err("Couldn't create iommu/devices/%s/dma_atos debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/dma_atos debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("map", 0200, dir, ddev, &iommu_debug_map_fops)) { - pr_err("Couldn't create iommu/devices/%s/map debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/map debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("dma_map", 0600, dir, ddev, &iommu_debug_dma_map_fops)) { - pr_err("Couldn't create iommu/devices/%s/dma_map debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/dma_map debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("unmap", 0200, dir, ddev, &iommu_debug_unmap_fops)) { - pr_err("Couldn't create iommu/devices/%s/unmap debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/unmap debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("dma_unmap", 0200, dir, ddev, &iommu_debug_dma_unmap_fops)) { - pr_err("Couldn't create iommu/devices/%s/dma_unmap debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/dma_unmap debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("pte", 0600, dir, ddev, &iommu_debug_pte_fops)) { - pr_err("Couldn't create iommu/devices/%s/pte debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/pte debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("config_clocks", 0200, dir, ddev, &iommu_debug_config_clocks_fops)) { - pr_err("Couldn't create iommu/devices/%s/config_clocks debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/config_clocks debugfs file\n", dev_name(dev)); goto err_rmdir; } if (!debugfs_create_file("trigger-fault", 0200, dir, ddev, &iommu_debug_trigger_fault_fops)) { - pr_err("Couldn't create iommu/devices/%s/trigger-fault debugfs file\n", + pr_err_ratelimited("Couldn't create iommu/devices/%s/trigger-fault debugfs file\n", dev_name(dev)); goto err_rmdir; } @@ -2458,7 +2460,7 @@ static int iommu_debug_init_tests(void) debugfs_tests_dir = debugfs_create_dir("tests", iommu_debugfs_top); if (!debugfs_tests_dir) { - pr_err("Couldn't create iommu/tests debugfs directory\n"); + pr_err_ratelimited("Couldn't create iommu/tests debugfs directory\n"); return -ENODEV; } -- GitLab From 1bc96f8b71e6573587701fb02a1ece995087c25e Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Fri, 25 Jan 2019 14:57:26 +0530 Subject: [PATCH 1235/1286] power_supply: add CHIP_VERSION property Add 'POWER_SUPPLY_PROP_CHIP_VERSION' property to expose chip version to user-space. Change-Id: Ief43130c0c206c15f95a4432ad012383a28f750e Signed-off-by: Ashay Jaiswal --- drivers/power/supply/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 9c1d306f67a8..e2b98eca048a 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -392,6 +392,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(cc_soc), POWER_SUPPLY_ATTR(batt_age_level), POWER_SUPPLY_ATTR(voltage_vph), + POWER_SUPPLY_ATTR(chip_version), /* Charge pump properties */ POWER_SUPPLY_ATTR(cp_status1), POWER_SUPPLY_ATTR(cp_status2), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 402196b35ba2..16ea77125033 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -323,6 +323,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_CC_SOC, POWER_SUPPLY_PROP_BATT_AGE_LEVEL, POWER_SUPPLY_PROP_VOLTAGE_VPH, + POWER_SUPPLY_PROP_CHIP_VERSION, /* Charge pump properties */ POWER_SUPPLY_PROP_CP_STATUS1, POWER_SUPPLY_PROP_CP_STATUS2, -- GitLab From 3d71a78d8aef8ba63c431361bddac56c6630d4bf Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Fri, 25 Jan 2019 14:59:47 +0530 Subject: [PATCH 1236/1286] power: smb1390-psy: add support to expose chip version Add support to read chip version from rev-id peripheral and expose it to userspace via power_supply property. Change-Id: Ic522ec7dd7e6849f9f599cfba07e22c59878ce84 Signed-off-by: Ashay Jaiswal --- .../power/supply/qcom/smb1390-charger-psy.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom/smb1390-charger-psy.c b/drivers/power/supply/qcom/smb1390-charger-psy.c index 7d987629433d..745b80e4c9da 100644 --- a/drivers/power/supply/qcom/smb1390-charger-psy.c +++ b/drivers/power/supply/qcom/smb1390-charger-psy.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -137,6 +138,7 @@ struct smb1390 { struct notifier_block nb; struct wakeup_source *cp_ws; struct dentry *dfs_root; + struct pmic_revid_data *pmic_rev_id; /* work structs */ struct work_struct status_change_work; @@ -694,6 +696,7 @@ static enum power_supply_property smb1390_charge_pump_props[] = { POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER, POWER_SUPPLY_PROP_CP_IRQ_STATUS, POWER_SUPPLY_PROP_CP_ILIM, + POWER_SUPPLY_PROP_CHIP_VERSION, }; static int smb1390_get_prop(struct power_supply *psy, @@ -765,6 +768,9 @@ static int smb1390_get_prop(struct power_supply *psy, val->intval = ((status & CFG_ILIM_MASK) * 100000) + 500000; break; + case POWER_SUPPLY_PROP_CHIP_VERSION: + val->intval = chip->pmic_rev_id->rev4; + break; default: smb1390_dbg(chip, PR_MISC, "charge pump power supply get prop %d not supported\n", prop); @@ -1030,8 +1036,27 @@ static void smb1390_create_debugfs(struct smb1390 *chip) static int smb1390_probe(struct platform_device *pdev) { struct smb1390 *chip; + struct device_node *revid_dev_node; + struct pmic_revid_data *pmic_rev_id; int rc; + revid_dev_node = of_parse_phandle(pdev->dev.of_node, + "qcom,pmic-revid", 0); + if (!revid_dev_node) { + pr_err("Missing qcom,pmic-revid property\n"); + return -EINVAL; + } + + pmic_rev_id = get_revid_data(revid_dev_node); + if (IS_ERR_OR_NULL(pmic_rev_id)) { + /* + * the revid peripheral must be registered, any failure + * here only indicates that the rev-id module has not + * probed yet. + */ + return -EPROBE_DEFER; + } + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; @@ -1040,6 +1065,7 @@ static int smb1390_probe(struct platform_device *pdev) spin_lock_init(&chip->status_change_lock); mutex_init(&chip->die_chan_lock); chip->die_temp = -ENODATA; + chip->pmic_rev_id = pmic_rev_id; platform_set_drvdata(pdev, chip); chip->regmap = dev_get_regmap(chip->dev->parent, NULL); @@ -1094,7 +1120,8 @@ static int smb1390_probe(struct platform_device *pdev) smb1390_create_debugfs(chip); - pr_info("smb1390 probed successfully"); + pr_info("smb1390 probed successfully chip_version=%d\n", + chip->pmic_rev_id->rev4); return 0; out_notifier: -- GitLab From 2e307337c920cb99f45b4370b57ecd7c4ebeb672 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 8 Aug 2018 18:30:38 -0700 Subject: [PATCH 1237/1286] ARM: dts: msm: add PCIe endpoint node for sm8150/sa8155 Add PCIe endpoint node to device tree of sm8150/sa8155. PCIe core is in endpoint mode and communicates with the PCIe root complex on host side. Change-Id: I229eee80e3a7d2c32ca50b4b4a7212ef1be003cd Signed-off-by: Tony Truong Signed-off-by: Rama Krishna Phani A --- arch/arm64/boot/dts/qcom/sa8155.dtsi | 5 + arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi | 192 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi | 38 ++++ arch/arm64/boot/dts/qcom/sm8150-v2.dtsi | 11 ++ 4 files changed, 246 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index ff7866ebd8f7..cc4c0541314c 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -118,6 +118,11 @@ vreg-0.9-supply = <&pm8150_2_l18>; }; +&pcie_ep { + vreg-1.8-supply = <&pm8150_2_l8>; + vreg-0.9-supply = <&pm8150_2_l18>; +}; + &mdss_dsi_phy0 { vdda-0p9-supply = <&pm8150_2_l18>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index 49d699183f16..115c6eb8eafc 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -606,4 +606,196 @@ interrupts = ; interrupt-names = "pci-edma-int"; }; + + pcie_ep: qcom,pcie@40004000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x4000>, + <0x01c0c000 0x2000>, + <0x01c0e000 0x1000>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 306 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 103 0>; + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1.8-supply = <&pm8150l_l3>; + vreg-0.9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>, + <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk"; + + resets = <&clock_gcc GCC_PCIE_1_BCR>, + <&clock_gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + qcom,msm-bus,name = "pcie-ep"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 500 800>; + + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg = <0xa14>; + + qcom,phy-init = <0x0a40 0x01 0x0 0x1 + 0x0094 0x00 0x0 0x1 + 0x000c 0x02 0x0 0x1 + 0x004c 0x07 0x0 0x1 + 0x0050 0x07 0x0 0x1 + 0x0058 0x0f 0x0 0x1 + 0x0074 0x36 0x0 0x1 + 0x0078 0x36 0x0 0x1 + 0x007c 0x12 0x0 0x1 + 0x0080 0x12 0x0 0x1 + 0x0084 0x00 0x0 0x1 + 0x0088 0x00 0x0 0x1 + 0x00a4 0x42 0x0 0x1 + 0x00ac 0xff 0x0 0x1 + 0x00b0 0x04 0x0 0x1 + 0x00b4 0xff 0x0 0x1 + 0x00b8 0x09 0x0 0x1 + 0x00bc 0x19 0x0 0x1 + 0x00c4 0x14 0x0 0x1 + 0x00ec 0xfb 0x0 0x1 + 0x00f0 0x01 0x0 0x1 + 0x00f4 0xfb 0x0 0x1 + 0x00f8 0x01 0x0 0x1 + 0x010c 0x02 0x0 0x1 + 0x0110 0x24 0x0 0x1 + 0x0118 0xb4 0x0 0x1 + 0x011c 0x03 0x0 0x1 + 0x0158 0x01 0x0 0x1 + 0x016c 0x08 0x0 0x1 + 0x01ac 0x56 0x0 0x1 + 0x01b0 0x1d 0x0 0x1 + 0x01b4 0x78 0x0 0x1 + 0x01b8 0x17 0x0 0x1 + 0x0154 0x31 0x0 0x1 + 0x01bc 0x11 0x0 0x1 + 0x0284 0x05 0x0 0x1 + 0x029c 0x12 0x0 0x1 + 0x0414 0x04 0x0 0x1 + 0x0434 0x7f 0x0 0x1 + 0x0444 0x70 0x0 0x1 + 0x04d8 0x01 0x0 0x1 + 0x04ec 0x0e 0x0 0x1 + 0x04f0 0x4a 0x0 0x1 + 0x04f4 0x0f 0x0 0x1 + 0x04f8 0xc0 0x0 0x1 + 0x04fc 0x00 0x0 0x1 + 0x0510 0x17 0x0 0x1 + 0x0518 0x1c 0x0 0x1 + 0x051c 0x03 0x0 0x1 + 0x0524 0x14 0x0 0x1 + 0x05b4 0x04 0x0 0x1 + 0x0570 0xbd 0x0 0x1 + 0x0574 0xbd 0x0 0x1 + 0x0578 0x7f 0x0 0x1 + 0x057c 0xdb 0x0 0x1 + 0x0580 0x76 0x0 0x1 + 0x0584 0x24 0x0 0x1 + 0x0588 0xe4 0x0 0x1 + 0x058c 0xec 0x0 0x1 + 0x0590 0x39 0x0 0x1 + 0x0594 0x37 0x0 0x1 + 0x0598 0xd4 0x0 0x1 + 0x059c 0x54 0x0 0x1 + 0x05a0 0xdb 0x0 0x1 + 0x05a4 0x39 0x0 0x1 + 0x05a8 0x31 0x0 0x1 + 0x0684 0x05 0x0 0x1 + 0x069c 0x12 0x0 0x1 + 0x0814 0x04 0x0 0x1 + 0x0834 0x7f 0x0 0x1 + 0x0844 0x70 0x0 0x1 + 0x08d8 0x01 0x0 0x1 + 0x08ec 0x0e 0x0 0x1 + 0x08f0 0x4a 0x0 0x1 + 0x08f4 0x0f 0x0 0x1 + 0x08f8 0xc0 0x0 0x1 + 0x08fc 0x00 0x0 0x1 + 0x0910 0x17 0x0 0x1 + 0x0918 0x1c 0x0 0x1 + 0x091c 0x03 0x0 0x1 + 0x0924 0x14 0x0 0x1 + 0x09b4 0x04 0x0 0x1 + 0x0970 0xbd 0x0 0x1 + 0x0974 0xbd 0x0 0x1 + 0x0978 0x7f 0x0 0x1 + 0x097c 0xdb 0x0 0x1 + 0x0980 0x76 0x0 0x1 + 0x0984 0x24 0x0 0x1 + 0x0988 0xe4 0x0 0x1 + 0x098c 0xec 0x0 0x1 + 0x0990 0x39 0x0 0x1 + 0x0994 0x37 0x0 0x1 + 0x0998 0xd4 0x0 0x1 + 0x099c 0x54 0x0 0x1 + 0x09a0 0xdb 0x0 0x1 + 0x09a4 0x39 0x0 0x1 + 0x09a8 0x31 0x0 0x1 + 0x0a98 0x01 0x0 0x1 + 0x0abc 0x56 0x0 0x1 + 0x0adc 0x0d 0x0 0x1 + 0x0b88 0xaa 0x0 0x1 + 0x0ba4 0x01 0x0 0x1 + 0x0e0c 0x04 0x0 0x1 + 0x0e14 0x07 0x0 0x1 + 0x0e40 0x01 0x0 0x1 + 0x0e48 0x01 0x0 0x1 + 0x0e78 0x50 0x0 0x1 + 0x0ea0 0x11 0x0 0x1 + 0x0ebc 0x00 0x0 0x1 + 0x0ee0 0x58 0x0 0x1 + 0x0a00 0x00 0x0 0x1 + 0x0a44 0x03 0x0 0x1>; + + edma-parent = <&pcie1_edma>; + iommus = <&apps_smmu 0x1e00 0x0>; + qcom,pcie-edma; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi index 93e6f4ad5d1a..856f8620528b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -446,6 +446,44 @@ }; }; + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + config { + pins = "gpio103"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + wil6210_refclk3_en_pin: wil6210_refclk3_en_pin { mux { pins = "gpio87"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi index 5a779486d300..a426f6edf264 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi @@ -351,6 +351,17 @@ 0x0a44 0x03 0x0>; }; +&pcie_ep { + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x01c0b000 0x1000>; +}; + &msm_vidc { qcom,allowed-clock-rates = <240000000 338000000 365000000 444000000 533000000>; -- GitLab From 556ffd9a98d15a02d27fa2e9e904931a3d765c87 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Thu, 24 Jan 2019 17:34:23 +0530 Subject: [PATCH 1238/1286] ARM: dts: msm: Update PM8008 regulator headroom for trinket Update headroom configuration for PM8008 LDO1 and LDO2 on trinket platform. Change-Id: I4c9984c73e26e5e7cef87030ae20a6131383de15 Signed-off-by: Ashay Jaiswal --- arch/arm64/boot/dts/qcom/pm8008.dtsi | 1 - arch/arm64/boot/dts/qcom/trinket.dtsi | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8008.dtsi b/arch/arm64/boot/dts/qcom/pm8008.dtsi index 0167a29e88c5..5a6222fab4ca 100644 --- a/arch/arm64/boot/dts/qcom/pm8008.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8008.dtsi @@ -55,7 +55,6 @@ qcom,pm8008@9 { regulator-name = "pm8008_l2"; regulator-min-microvolt = <528000>; regulator-max-microvolt = <1504000>; - qcom,init-voltage = <1500000>; qcom,min-dropout-voltage = <225000>; qcom,hpm-min-load = <10000>; }; diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2504302d2872..bd8bb52c0582 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2733,11 +2733,13 @@ &L1P { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <100000>; }; &L2P { regulator-min-microvolt = <1104000>; regulator-max-microvolt = <1104000>; + qcom,min-dropout-voltage = <100000>; }; &L3P { -- GitLab From 50d813e698af43c5e646d407359d3ba6d0b315f1 Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Sun, 20 Jan 2019 20:44:54 +0800 Subject: [PATCH 1239/1286] ARM: dts: msm: Add msm name and pmic name for trinket In order to have full Machine name showed in dmesg need to have msm name and pmic name given for trinket. Change-Id: Iba8c43793dc84f03e2199d8d395773b84a2f93ea Signed-off-by: Maria Yu --- arch/arm64/boot/dts/qcom/trinket.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2504302d2872..5a32e650ac93 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -31,6 +31,8 @@ model = "Qualcomm Technologies, Inc. TRINKET"; compatible = "qcom,trinket"; qcom,msm-id = <394 0x10000>; + qcom,msm-name = "trinket"; + qcom,pmic-name = "pm6125 + pmi632"; interrupt-parent = <&wakegic>; aliases { -- GitLab From 6d043d0f052153efc052aa2403ecd0425b76b21c Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 22 Jan 2019 18:20:35 +0530 Subject: [PATCH 1240/1286] clk: qcom: gpucc: Add support for HLOS1_VOTE_GPU_SMMU_CLK Clock GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK for clients to be able to request for the clock. Change-Id: I771c1f486da8415d303b7a24918c535128ac8de0 Signed-off-by: Taniya Das --- drivers/clk/qcom/gpucc-sm6150.c | 14 ++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm6150.h | 3 ++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sm6150.c b/drivers/clk/qcom/gpucc-sm6150.c index c6b0d0f62add..6292513f883a 100644 --- a/drivers/clk/qcom/gpucc-sm6150.c +++ b/drivers/clk/qcom/gpucc-sm6150.c @@ -437,6 +437,19 @@ static struct clk_branch gpu_cc_ahb_clk = { }, }; +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + struct clk_hw *gpu_cc_sm6150_hws[] = { [CRC_DIV_PLL0_OUT_AUX2] = &crc_div_pll0_out_aux2.hw, [CRC_DIV_PLL1_OUT_AUX2] = &crc_div_pll1_out_aux2.hw, @@ -459,6 +472,7 @@ static struct clk_regmap *gpu_cc_sm6150_clocks[] = { [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, }; static const struct regmap_config gpu_cc_sm6150_regmap_config = { diff --git a/include/dt-bindings/clock/qcom,gpucc-sm6150.h b/include/dt-bindings/clock/qcom,gpucc-sm6150.h index 9f7f7edb155b..63e317e798ef 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sm6150.h +++ b/include/dt-bindings/clock/qcom,gpucc-sm6150.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -36,5 +36,6 @@ #define GPU_CC_GX_GFX3D_CLK 16 #define GPU_CC_GX_GFX3D_CLK_SRC 17 #define GPU_CC_AHB_CLK 18 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 19 #endif -- GitLab From 0034bb4c65c7b5755bdb9d302b592e5598c90cdb Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 28 Nov 2018 15:44:31 +0530 Subject: [PATCH 1241/1286] drivers: cpu_cooling: vote thermal limit on CPUFREQ_INCOMPATIBLE event The cpu cooling device request thermal frequency limit on CPUFREQ_ADJUST event notification from cpu freq driver. But other clients also using same event to their frequency vote. There is a possible case where thermal vote its limit and later other client overrides this request. To avoid this, listen for new CPUFREQ_INCOMPATIBLE event from cpu freq policy notifier and request thermal limit on this event. It makes sure that for any policy update thermal vote will be last one and nobody can override it. Change-Id: I05b69c079da2b06d2ac61b0631ca387dcda26566 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- drivers/thermal/cpu_cooling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c index d4b5c81816c2..a40ec378e950 100644 --- a/drivers/thermal/cpu_cooling.c +++ b/drivers/thermal/cpu_cooling.c @@ -300,7 +300,7 @@ static int cpufreq_thermal_notifier(struct notifier_block *nb, unsigned long clipped_freq = ULONG_MAX, floor_freq = 0; struct cpufreq_cooling_device *cpufreq_cdev; - if (event != CPUFREQ_ADJUST) + if (event != CPUFREQ_INCOMPATIBLE) return NOTIFY_DONE; mutex_lock(&cooling_list_lock); -- GitLab From 53afa03f509e995ead8f8a09d895df8494c2f054 Mon Sep 17 00:00:00 2001 From: Liangliang Lu Date: Tue, 4 Sep 2018 16:27:20 +0800 Subject: [PATCH 1242/1286] defconfig: Enable USB to Ethernet driver lan78xx on HDK8150 HDK8150 use USB 1Gbps Ethernet solution, so enable lan78xx driver. Change-Id: I033abf49bfc22145b317c785f28a521a9a157dfe Signed-off-by: Liangliang Lu --- arch/arm64/configs/vendor/sm8150-perf_defconfig | 2 ++ arch/arm64/configs/vendor/sm8150_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index d0673727c24a..5ce6c924b3a4 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -241,6 +241,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_GACT=y CONFIG_NET_ACT_MIRRED=y CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_SWITCHDEV=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y @@ -306,6 +307,7 @@ CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index 612eec624896..10a2947c47c4 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -250,6 +250,7 @@ CONFIG_NET_ACT_GACT=y CONFIG_NET_ACT_MIRRED=y CONFIG_NET_ACT_SKBEDIT=y CONFIG_DNS_RESOLVER=y +CONFIG_NET_SWITCHDEV=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y @@ -317,6 +318,7 @@ CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y -- GitLab From ba50625c7f8f6fe16f8efce4093aa0db266429ca Mon Sep 17 00:00:00 2001 From: AnilKumar Chimata Date: Fri, 25 Jan 2019 12:43:23 +0530 Subject: [PATCH 1243/1286] qseecom: Move qseecom_ioctl from inline to normal function Marking inline for qseecom_ioctl() increases stack heavily which makes device crash at multiple places with different call stacks, hence remove inline macro from ioctl function to fix stack corruption issue. Change-Id: If1704cbfcfb925fb8f9d6f97b99cb12e30bb6ab1 Signed-off-by: AnilKumar Chimata --- drivers/misc/qseecom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 784755659d0a..3d6835152cd7 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -7121,7 +7121,7 @@ static void __qseecom_clean_data_sglistinfo(struct qseecom_dev_handle *data) } } -static inline long qseecom_ioctl(struct file *file, +static long qseecom_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int ret = 0; -- GitLab From 27aad2f57b4ad8f475ca9e055abc8791247fd179 Mon Sep 17 00:00:00 2001 From: Srikanth Uyyala Date: Fri, 25 Jan 2019 23:37:44 +0530 Subject: [PATCH 1244/1286] ARM: dts: msm: Bring up camera subsystem Add clock and voltage changes to enable camera subsystem on trinket platform. Change-Id: Ieab706e9ecffed6fe7b63a5263e71edeb0bc6892 Signed-off-by: Srikanth Uyyala --- .../dts/qcom/trinket-camera-sensor-idp.dtsi | 8 +- arch/arm64/boot/dts/qcom/trinket-camera.dtsi | 84 ++++++++++--------- 2 files changed, 48 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi index 9bea872b05e4..2772c907b3f5 100644 --- a/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi @@ -154,7 +154,7 @@ compatible = "qcom,camera"; reg = <0x1>; qcom,csiphy-sd-index = <1>; - qcom,csid-sd-index = <2>; + qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; cam_vio-supply = <&L12A>; cam_vana-supply = <&L4P>; @@ -172,7 +172,7 @@ pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear2_suspend>; gpios = <&tlmm 35 0>, - <&tlmm 45 0>; + <&tlmm 46 0>; qcom,gpio-reset = <1>; qcom,gpio-req-tbl-num = <0 1>; qcom,gpio-req-tbl-flags = <1 0>; @@ -192,8 +192,8 @@ cell-index = <2>; compatible = "qcom,camera"; reg = <0x02>; - qcom,csiphy-sd-index = <1>; - qcom,csid-sd-index = <1>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; cam_vio-supply = <&L12A>; diff --git a/arch/arm64/boot/dts/qcom/trinket-camera.dtsi b/arch/arm64/boot/dts/qcom/trinket-camera.dtsi index 59156b2b61c0..c5f2d310cc38 100644 --- a/arch/arm64/boot/dts/qcom/trinket-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-camera.dtsi @@ -122,13 +122,13 @@ reg-names = "csid"; interrupts = <0 208 0>; interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; + qcom,csi-vdd-voltage = <1232000>; qcom,mipi-csi-vdd-supply = <&L18A>; gdscr-supply = <&camss_top_gdsc>; vdd_sec-supply = <&L18A>; qcom,cam-vreg-name = "vdd_sec", "gdscr"; - qcom,cam-vreg-min-voltage = <925000 0>; - qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; qcom,cam-vreg-op-mode = <0 0>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, @@ -156,13 +156,13 @@ reg-names = "csid"; interrupts = <0 209 0>; interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; + qcom,csi-vdd-voltage = <1232000>; qcom,mipi-csi-vdd-supply = <&L18A>; gdscr-supply = <&camss_top_gdsc>; vdd_sec-supply = <&L18A>; qcom,cam-vreg-name = "vdd_sec", "gdscr"; - qcom,cam-vreg-min-voltage = <925000 0>; - qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; qcom,cam-vreg-op-mode = <0 0>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, @@ -190,13 +190,13 @@ reg-names = "csid"; interrupts = <0 210 0>; interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; + qcom,csi-vdd-voltage = <1232000>; qcom,mipi-csi-vdd-supply = <&L18A>; gdscr-supply = <&camss_top_gdsc>; vdd_sec-supply = <&L18A>; qcom,cam-vreg-name = "vdd_sec", "gdscr"; - qcom,cam-vreg-min-voltage = <925000 0>; - qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; qcom,cam-vreg-op-mode = <0 0>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, @@ -224,13 +224,13 @@ reg-names = "csid"; interrupts = <0 211 0>; interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; + qcom,csi-vdd-voltage = <1232000>; qcom,mipi-csi-vdd-supply = <&L18A>; gdscr-supply = <&camss_top_gdsc>; vdd_sec-supply = <&L18A>; qcom,cam-vreg-name = "vdd_sec", "gdscr"; - qcom,cam-vreg-min-voltage = <925000 0>; - qcom,cam-vreg-max-voltage = <925000 0>; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; qcom,cam-vreg-op-mode = <0 0>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, @@ -258,8 +258,7 @@ msm_cam_smmu_cb1 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x420 0x0000>, - <&apps_smmu 0x421 0x0002>, - <&apps_smmu 0x423 0x0002>; + <&apps_smmu 0x421 0x0002>; label = "vfe"; qcom,scratch-buf-support; }; @@ -275,12 +274,12 @@ iommus = <&apps_smmu 0x820 0x0001>; label = "jpeg_enc0"; }; - msm_cam_smmu_cb5 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x821 0x0001>; label = "jpeg_dma"; }; + }; qcom,cpp@5c04000 { @@ -303,13 +302,14 @@ <&clock_gcc GCC_CAMSS_CPP_AHB_CLK>, <&clock_gcc GCC_CAMSS_CPP_AXI_CLK>, <&clock_gcc GCC_CAMSS_MICRO_AHB_CLK>, - <&clock_gcc GCC_CAMSS_CPP_VBIF_AHB_CLK>; + <&clock_gcc GCC_CAMSS_CPP_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_NRT_AXI_CLK>; clock-names = "camss_ahb_clk", "camss_top_ahb_clk", "cpp_src_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "micro_iface_clk", - "cpp_vbif_ahb_clk"; - qcom,clock-rates = <0 0 256000000 256000000 0 0 0 0>; + "cpp_vbif_ahb_clk", "mmss_throttle_camss_nrt_axi_clk"; + qcom,clock-rates = <0 0 256000000 256000000 0 0 0 0 0>; qcom,min-clock-rate = <256000000>; qcom,bus-master = <1>; status = "ok"; @@ -436,11 +436,10 @@ interrupts = <0 214 0>, <0 258 0>; interrupt-names = "vfe", "dual-vfe-irq"; - vdd-supply = <&camss_vfe0_gdsc>; camss-vdd-supply = <&camss_top_gdsc>; - qcom,vdd-names = "vdd", "camss-vdd"; - clocks = <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, - <&clock_gcc GCC_CAMERA_AHB_CLK>, + vdd-supply = <&camss_vfe0_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE0_CLK_SRC>, <&clock_gcc GCC_CAMSS_VFE0_CLK>, @@ -448,16 +447,17 @@ <&clock_gcc GCC_CAMSS_VFE0_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, <&clock_gcc GCC_CAMSS_CSI_VFE0_CLK>; - clock-names = "mmss_throttle_camss_axi_clk", "camss_ahb_clk", + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", + "camss_vfe_vbif_axi_clk", "mmss_throttle_camss_axi_clk", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 403200000 0 0 0 0 0 0 - 0 0 0 480000000 0 0 0 0 0 0 - 0 0 0 576000000 0 0 0 0 0 0>; + qcom,clock-rates = <0 0 403200000 0 0 0 0 0 0 0 + 0 0 480000000 0 0 0 0 0 0 0 + 0 0 576000000 0 0 0 0 0 0 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 @@ -510,15 +510,14 @@ reg = <0x5c14000 0x4000>, <0x5c40000 0x3000>, <0x5C00000 0x40000>; - reg-names = "vfe", "vfe_vbif", "dual-vfe-irq"; + reg-names = "vfe", "vfe_vbif", "msm-cam"; interrupts = <0 215 0>, <0 258 0>; interrupt-names = "vfe", "dual-vfe-irq"; - vdd-supply = <&camss_vfe1_gdsc>; camss-vdd-supply = <&camss_top_gdsc>; - qcom,vdd-names = "vdd", "camss-vdd"; - clocks = <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, - <&clock_gcc GCC_CAMERA_AHB_CLK>, + vdd-supply = <&camss_vfe1_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE1_CLK_SRC>, <&clock_gcc GCC_CAMSS_VFE1_CLK>, @@ -526,16 +525,17 @@ <&clock_gcc GCC_CAMSS_VFE1_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, <&clock_gcc GCC_CAMSS_CSI_VFE1_CLK>; - clock-names = "mmss_throttle_camss_axi_clk", "camss_ahb_clk", + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", + "camss_vfe_vbif_axi_clk", "mmss_throttle_camss_axi_clk", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 403200000 0 0 0 0 0 0 - 0 0 0 480000000 0 0 0 0 0 0 - 0 0 0 576000000 0 0 0 0 0 0>; + qcom,clock-rates = <0 0 403200000 0 0 0 0 0 0 0 + 0 0 480000000 0 0 0 0 0 0 0 + 0 0 576000000 0 0 0 0 0 0 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 @@ -647,15 +647,17 @@ qcom,vdd-names = "camss-vdd"; clock-names = "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", - "core_clk", + "core_src_clk", + "core_src", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_CLK>, <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; - qcom,clock-rates = <0 0 480000000 0 0>; + qcom,clock-rates = <0 0 480000000 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>; qcom,vbif-qos-setting = <0x550 0x1111>; qcom,prefetch-reg-settings = <0x30c 0x1111>, @@ -683,15 +685,17 @@ qcom,vdd-names = "camss-vdd"; clock-names = "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", + "core_clk_src", "core_clk", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_CLK>, <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; - qcom,clock-rates = <0 0 480000000 0 0>; + qcom,clock-rates = <0 0 480000000 0 0 0>; qcom,vbif-reg-settings = <0x4 0x1>; qcom,vbif-qos-setting = <0x550 0x1111>; qcom,prefetch-reg-settings = <0x18c 0x11>, -- GitLab From 2cebfbfb2d44ac30b51bd5489a60825000926da3 Mon Sep 17 00:00:00 2001 From: Devi Sandeep Endluri V V Date: Mon, 14 Jan 2019 10:47:29 +0530 Subject: [PATCH 1245/1286] xt_hardidletiemr: Check for remaining expiry time -xt_hardidletimers are getting reset with addition/ deletion of any iptable rule in any chain of raw/mangle table. -Check and restart the timer with remaining expiry time. Change-Id: I55c6fb211b929dfe500edda8e7c01530f944b067 CRs-Fixed: 2367114 Acked-by: Manoj Basapathi Signed-off-by: Devi Sandeep Endluri V V --- net/netfilter/xt_HARDIDLETIMER.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/net/netfilter/xt_HARDIDLETIMER.c b/net/netfilter/xt_HARDIDLETIMER.c index 2176a4e0ea93..ea8b103a3f39 100644 --- a/net/netfilter/xt_HARDIDLETIMER.c +++ b/net/netfilter/xt_HARDIDLETIMER.c @@ -237,6 +237,9 @@ static int hardidletimer_tg_checkentry(const struct xt_tgchk_param *par) struct hardidletimer_tg_info *info = par->targinfo; int ret; ktime_t tout; + struct timespec ktimespec; + + memset(&ktimespec, 0, sizeof(struct timespec)); pr_debug("checkentry targinfo %s\n", info->label); @@ -257,15 +260,16 @@ static int hardidletimer_tg_checkentry(const struct xt_tgchk_param *par) info->timer = __hardidletimer_tg_find_by_label(info->label); if (info->timer) { info->timer->refcnt++; - if (!info->timer->active) { - schedule_work(&info->timer->work); - pr_debug("Starting Checkentry timer\n"); + /* calculate remaining expiry time */ + tout = alarm_expires_remaining(&info->timer->alarm); + ktimespec = ktime_to_timespec(tout); + + if (ktimespec.tv_sec > 0) { + pr_debug("time_expiry_remaining %ld\n", + ktimespec.tv_sec); + alarm_start_relative(&info->timer->alarm, tout); } - info->timer->active = true; - tout = ktime_set(info->timeout, 0); - alarm_start_relative(&info->timer->alarm, tout); - pr_debug("increased refcnt of timer %s to %u\n", info->label, info->timer->refcnt); } else { -- GitLab From fc66d21a64ccc77c6706dd2c67c3744caa24ac9a Mon Sep 17 00:00:00 2001 From: Ramandeep Trehan Date: Thu, 31 Jan 2019 13:16:50 +0530 Subject: [PATCH 1246/1286] ARM64: dts: msm: add inline crypto engine node Add inline crypto engine node to support hardware encryption. Change-Id: I9f42aab0ddcd15358e66830b35b2336fd14fcba1 Signed-off-by: Ramandeep Trehan --- arch/arm64/boot/dts/qcom/trinket.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2504302d2872..f47cf06b0afe 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -890,6 +890,29 @@ poll-delay-ms = <5000>; }; + ufs_ice: ufsice@4810000 { + compatible = "qcom,ice"; + reg = <0x4810000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + ufsphy_mem: ufsphy_mem@4807000 { reg = <0x4807000 0xdb8>; /* PHY regs */ reg-names = "phy_mem"; @@ -913,6 +936,7 @@ interrupts = <0 356 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ -- GitLab From c530a2c07bcff0b5c17693cc35a860ac5bfba360 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Thu, 31 Jan 2019 15:58:36 +0800 Subject: [PATCH 1247/1286] ARM: dts: msm: Correct connection of the tpdm modems for TRINKET Correct connection of the tpdm modems for TRINKET to make modem HW events work. Change-Id: Ie1d1242d319044179dd5546f92136bc580520571 Signed-off-by: Mao Jinlong --- .../boot/dts/qcom/trinket-coresight.dtsi | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi b/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi index 712bea54a18a..b16d2c0f42e2 100644 --- a/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-coresight.dtsi @@ -750,10 +750,10 @@ port@2 { reg = <4>; - funnel_qatb_in_funnel_monaq: endpoint { + funnel_qatb_in_funnel_monaq_1: endpoint { slave-mode; remote-endpoint = - <&funnel_monaq_out_funnel_qatb>; + <&funnel_monaq_1_out_funnel_qatb>; }; }; @@ -827,10 +827,10 @@ port@2 { reg = <3>; - tpda_in_funnel_monaq_1: endpoint { + tpda_in_funnel_monaq: endpoint { slave-mode; remote-endpoint = - <&funnel_monaq_1_out_tpda>; + <&funnel_monaq_out_tpda>; }; }; @@ -1039,18 +1039,18 @@ port@0 { reg = <0>; - funnel_monaq_1_out_tpda: endpoint { + funnel_monaq_1_out_funnel_qatb: endpoint { remote-endpoint = - <&tpda_in_funnel_monaq_1>; + <&funnel_qatb_in_funnel_monaq_1>; }; }; port@1 { - reg = <0>; - funnel_monaq_1_in_tpdm_monaq: endpoint { + reg = <6>; + funnel_monaq_1_in_modem_etm0: endpoint { slave-mode; remote-endpoint = - <&tpdm_monaq_out_funnel_monaq_1>; + <&modem_etm0_out_funnel_monaq_1>; }; }; @@ -1077,9 +1077,9 @@ clock-names = "apb_pclk"; port { - tpdm_monaq_out_funnel_monaq_1: endpoint { + tpdm_monaq_out_funnel_monaq: endpoint { remote-endpoint = - <&funnel_monaq_1_in_tpdm_monaq>; + <&funnel_monaq_in_tpdm_monaq>; }; }; }; @@ -1173,7 +1173,7 @@ coresight-name = "coresight-tpda-modem-1"; - qcom,tpda-atid = <67>; + qcom,tpda-atid = <98>; qcom,dsb-elem-size = <0 32>; qcom,cmb-elem-size = <0 64>; @@ -1258,18 +1258,18 @@ port@0 { reg = <0>; - funnel_monaq_out_funnel_qatb: endpoint { + funnel_monaq_out_tpda: endpoint { remote-endpoint = - <&funnel_qatb_in_funnel_monaq>; + <&tpda_in_funnel_monaq>; }; }; port@1 { - reg = <6>; - funnel_monaq_in_modem_etm0: endpoint { + reg = <0>; + funnel_monaq_in_tpdm_monaq: endpoint { slave-mode; remote-endpoint = - <&modem_etm0_out_funnel_monaq>; + <&tpdm_monaq_out_funnel_monaq>; }; }; }; @@ -1503,9 +1503,9 @@ qcom,inst-id = <2>; port { - modem_etm0_out_funnel_monaq: endpoint { + modem_etm0_out_funnel_monaq_1: endpoint { remote-endpoint = - <&funnel_monaq_in_modem_etm0>; + <&funnel_monaq_1_in_modem_etm0>; }; }; }; -- GitLab From f3f842b5a330c97fcf008cb230277d5c54eae901 Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Wed, 9 Jan 2019 15:50:49 +0530 Subject: [PATCH 1248/1286] defconfig: trinket: Enable dual isp sync support for trinket Changes to add variable in defconfig to enable dual isp sync support for trinket. Signed-off-by: Meera Gande Signed-off-by: Abhishek Jain Change-Id: If21eb18a6746573450642df32b0073249ef65bc4 --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + drivers/media/platform/msm/camera_v2/Kconfig | 9 +++++++++ 3 files changed, 11 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 50e81b661e65..4611643a2e72 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -392,6 +392,7 @@ CONFIG_MSM_CSIPHY=y CONFIG_MSM_CSID=y CONFIG_MSM_EEPROM=y CONFIG_MSM_ISPIF=y +CONFIG_MSM_DUAL_ISP_SYNC=y CONFIG_IMX134=y CONFIG_IMX132=y CONFIG_OV9724=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 7242fba4e772..d03a265890de 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -407,6 +407,7 @@ CONFIG_MSM_CSIPHY=y CONFIG_MSM_CSID=y CONFIG_MSM_EEPROM=y CONFIG_MSM_ISPIF=y +CONFIG_MSM_DUAL_ISP_SYNC=y CONFIG_IMX134=y CONFIG_IMX132=y CONFIG_OV9724=y diff --git a/drivers/media/platform/msm/camera_v2/Kconfig b/drivers/media/platform/msm/camera_v2/Kconfig index e5439d85357c..b3a122a3fcc1 100644 --- a/drivers/media/platform/msm/camera_v2/Kconfig +++ b/drivers/media/platform/msm/camera_v2/Kconfig @@ -131,6 +131,15 @@ config MSM_ISPIF_V2 of any CID of CSID can be routed to of pix or raw data interface in VFE. +config MSM_DUAL_ISP_SYNC + bool "QTI MSM Image Signal Processing interface support" + depends on MSMB_CAMERA + ---help--- + Enable support for Image Signal Processing interface module. + This module is used to enable the dual isp sync generator that + does the synchronization of two VFE's. There will be a single + output from the sync generator + config IMX134 bool "Sensor IMX134 (BAYER 8M)" depends on MSMB_CAMERA -- GitLab From 244de534c344097c1192698d8d9dc2401ff5e015 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Wed, 14 Mar 2018 22:31:42 +0800 Subject: [PATCH 1249/1286] soc: qcom: add support for per cluster scan dumps Add support to allocate memory for per cluster scan dumps. This memory can be used to save CPU scan dumps at the time of a dump. Change-Id: I29dffb2ffe6ae6ae59f4bc91deb996e5bf512b10 Signed-off-by: Mao Jinlong [mojha@codeaurora.org: Added logic to handle both single and per core scandump buffer] Signed-off-by: Mukesh Ojha --- drivers/soc/qcom/watchdog_v2.c | 52 ++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/watchdog_v2.c b/drivers/soc/qcom/watchdog_v2.c index ff1dd668bef0..7a48f8386f0d 100644 --- a/drivers/soc/qcom/watchdog_v2.c +++ b/drivers/soc/qcom/watchdog_v2.c @@ -100,6 +100,9 @@ struct msm_watchdog_data { unsigned long long ping_start[NR_CPUS]; unsigned long long ping_end[NR_CPUS]; unsigned int cpu_scandump_sizes[NR_CPUS]; + + /* When single buffer is used to collect Scandump */ + unsigned int scandump_size; }; /* @@ -590,6 +593,38 @@ static void configure_bark_dump(struct msm_watchdog_data *wdog_dd) return; } +static void register_scan_dump(struct msm_watchdog_data *wdog_dd) +{ + static void *dump_addr; + int ret; + struct msm_dump_entry dump_entry; + struct msm_dump_data *dump_data; + + dump_data = kzalloc(sizeof(struct msm_dump_data), GFP_KERNEL); + if (!dump_data) + return; + dump_addr = kzalloc(wdog_dd->scandump_size, GFP_KERNEL); + if (!dump_addr) + goto err0; + + dump_data->addr = virt_to_phys(dump_addr); + dump_data->len = wdog_dd->scandump_size; + strlcpy(dump_data->name, "KSCANDUMP", sizeof(dump_data->name)); + + dump_entry.id = MSM_DUMP_DATA_SCANDUMP; + dump_entry.addr = virt_to_phys(dump_data); + ret = msm_dump_data_register(MSM_DUMP_TABLE_APPS, &dump_entry); + if (ret) { + pr_err("Registering scandump region failed\n"); + goto err1; + } + return; +err1: + kfree(dump_addr); +err0: + kfree(dump_data); +} + static void configure_scandump(struct msm_watchdog_data *wdog_dd) { int ret; @@ -600,6 +635,11 @@ static void configure_scandump(struct msm_watchdog_data *wdog_dd) static void *dump_vaddr; unsigned int scandump_size; + if (wdog_dd->scandump_size) { + register_scan_dump(wdog_dd); + return; + } + for_each_cpu(cpu, cpu_present_mask) { scandump_size = wdog_dd->cpu_scandump_sizes[cpu]; cpu_data = devm_kzalloc(wdog_dd->dev, @@ -819,14 +859,22 @@ static int msm_wdog_dt_to_pdata(struct platform_device *pdev, num_scandump_sizes = of_property_count_elems_of_size(node, "qcom,scandump-sizes", sizeof(u32)); - if (num_scandump_sizes < 0 || num_scandump_sizes != NR_CPUS) + if ((num_scandump_sizes < 0) || ((num_scandump_sizes != 1) && + (num_scandump_sizes != NR_CPUS))) { dev_info(&pdev->dev, "%s scandump sizes property not correct\n", __func__); - else + } else if (num_scandump_sizes == 1) { + if (of_property_read_u32(node, "qcom,scandump-sizes", + &pdata->scandump_size)) + dev_info(&pdev->dev, + "No need to allocate memory for scandumps\n"); + } else { for_each_cpu(cpu, cpu_present_mask) of_property_read_u32_index(node, "qcom,scandump-sizes", cpu, &pdata->cpu_scandump_sizes[cpu]); + } + pdata->irq_ppi = irq_is_percpu(pdata->bark_irq); dump_pdata(pdata); return 0; -- GitLab From e9b4f49899fec188244f0f10ef10da8771b1b648 Mon Sep 17 00:00:00 2001 From: Srikanth Uyyala Date: Fri, 25 Jan 2019 22:29:05 +0530 Subject: [PATCH 1250/1286] msm: camera_v2: Enable camera on trinket Add smmu and bandwidth voting changes to enable camera subsystem. Change-Id: If798c2178c73e24666cb91a58549b7d495533eae Signed-off-by: Srikanth Uyyala --- .../msm/camera_v2/common/cam_smmu_api.c | 6 +-- .../msm/camera_v2/common/cam_soc_api.c | 52 +++++++++++++++++-- .../msm/camera_v2/common/cam_soc_api.h | 19 +++++-- .../platform/msm/camera_v2/isp/msm_isp47.c | 15 +++--- .../platform/msm/camera_v2/isp/msm_isp48.h | 4 +- .../platform/msm/camera_v2/isp/msm_isp_util.c | 2 +- .../msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.c | 4 +- .../msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.h | 5 +- .../msm/camera_v2/pproc/cpp/msm_cpp.c | 13 +++-- .../csiphy/include/msm_csiphy_3_5_hwreg.h | 4 +- 10 files changed, 88 insertions(+), 36 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c b/drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c index 2b84fc8e59a2..e43ff7dc9439 100644 --- a/drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c +++ b/drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1049,13 +1049,13 @@ static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, mapping_info->attach = attach; mapping_info->table = table; mapping_info->paddr = sg_dma_address(table->sgl); - mapping_info->len = (size_t)sg_dma_len(table->sgl); + mapping_info->len = (size_t)buf->size; mapping_info->dir = dma_dir; mapping_info->ref_count = 1; /* return paddr and len to client */ *paddr_ptr = sg_dma_address(table->sgl); - *len_ptr = (size_t)sg_dma_len(table->sgl); + *len_ptr = (size_t)buf->size; if (!*paddr_ptr || !*len_ptr) { pr_err("Error: Space Allocation failed!\n"); diff --git a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c index 7f15a8d7f3ef..1f8ca8d0b699 100644 --- a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c +++ b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -360,7 +360,6 @@ int msm_camera_clk_enable(struct device *dev, if (enable) { for (i = 0; i < num_clk; i++) { - CDBG("enable %s\n", clk_info[i].clk_name); if (clk_info[i].clk_rate > 0) { clk_rate = clk_round_rate(clk_ptr[i], clk_info[i].clk_rate); @@ -411,8 +410,6 @@ int msm_camera_clk_enable(struct device *dev, } else { for (i = num_clk - 1; i >= 0; i--) { if (clk_ptr[i] != NULL) { - CDBG("%s disable %s\n", __func__, - clk_info[i].clk_name); clk_disable_unprepare(clk_ptr[i]); } } @@ -429,6 +426,24 @@ int msm_camera_clk_enable(struct device *dev, } EXPORT_SYMBOL(msm_camera_clk_enable); + +int msm_camera_cpp_clk_disable(struct device *dev, + struct msm_cam_clk_info *clk_info, + struct clk **clk_ptr, int num_clk, int enable) +{ + int i; + int rc = 1; + + for (i = num_clk - 1; i >= 0; i--) { + if (clk_ptr[i] != NULL) { + rc = strcmp(clk_info[i].clk_name, "cpp_src_clk"); + if (rc == 0) + continue; + clk_disable_unprepare(clk_ptr[i]); + } + } + return 0; +} /* Set rate on a specific clock */ long msm_camera_clk_set_rate(struct device *dev, struct clk *clk, @@ -662,7 +677,6 @@ int msm_camera_regulator_enable(struct msm_cam_regulator *vdd_info, for (i = 0; i < cnt; i++) { if (tmp && !IS_ERR_OR_NULL(tmp->vdd)) { - CDBG("name : %s, enable : %d\n", tmp->name, enable); if (enable) { rc = regulator_enable(tmp->vdd); if (rc < 0) { @@ -691,6 +705,34 @@ int msm_camera_regulator_enable(struct msm_cam_regulator *vdd_info, } EXPORT_SYMBOL(msm_camera_regulator_enable); +/* disable/Disable regulators */ +int msm_camera_regulator_disable(struct msm_cam_regulator *vdd_info, + int cnt, int disable) +{ + int i; + int rc; + struct msm_cam_regulator *tmp = vdd_info; + + if (!tmp) { + pr_err("Invalid params"); + return -EINVAL; + } + + for (i = cnt; i > 0; i--) { + if (disable) { + rc = regulator_disable(tmp[i-1].vdd); + if (rc < 0) { + pr_debug("%s: %s failed %d\n", + __func__, tmp[i-1].name, i); + return rc; + } + } + } + return 0; +} +EXPORT_SYMBOL(msm_camera_regulator_disable); + + /* set regulator mode */ int msm_camera_regulator_set_mode(struct msm_cam_regulator *vdd_info, int cnt, bool mode) diff --git a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h index 0e0736ad94bb..caa379dbeddd 100644 --- a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h +++ b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h @@ -1,4 +1,5 @@ -/* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. + * All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -168,10 +169,15 @@ int msm_camera_put_clk_info_and_rates(struct platform_device *pdev, */ int msm_camera_clk_enable(struct device *dev, - struct msm_cam_clk_info *clk_info, - struct clk **clk_ptr, - int num_clk, - int enable); + struct msm_cam_clk_info *clk_info, + struct clk **clk_ptr, + int num_clk, + int enable); + +int msm_camera_cpp_clk_disable(struct device *dev, + struct msm_cam_clk_info *clk_info, + struct clk **clk_ptr, int num_clk, int enable); + /** * @brief : Set clock rate * @@ -247,6 +253,9 @@ int msm_camera_get_regulator_info(struct platform_device *pdev, int msm_camera_regulator_enable(struct msm_cam_regulator *vdd_info, int cnt, int enable); + +int msm_camera_regulator_disable(struct msm_cam_regulator *vdd_info, + int cnt, int disable); /** * @brief : set the regultors mode * diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c index e3ed0e3fb1a3..2488b87c286e 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -322,7 +322,7 @@ int msm_vfe47_init_hardware(struct vfe_device *vfe_dev) vfe_dev, 1); if (rc) goto enable_regulators_failed; - + msm_isp_update_bandwidth(vfe_dev->pdev->id, 0x1000, 0x1000); rc = vfe_dev->hw_info->vfe_ops.platform_ops.enable_clks( vfe_dev, 1); if (rc) @@ -2010,8 +2010,6 @@ void msm_vfe47_update_ping_pong_addr( if (buf_size < 0) buf_size = 0; - paddr32_max = (paddr + buf_size) & 0xFFFFFFE0; - msm_camera_io_w(paddr32, vfe_base + VFE47_PING_PONG_BASE(wm_idx, pingpong_bit)); msm_camera_io_w(paddr32_max, vfe_base + @@ -2517,7 +2515,7 @@ void msm_vfe47_stats_update_ping_pong_addr( int vfe_idx = msm_isp_get_vfe_idx_for_stats_stream(vfe_dev, stream_info); uint32_t paddr32 = (paddr & 0xFFFFFFFF); - uint32_t paddr32_max; + uint32_t paddr32_max = 0; int stats_idx; stats_idx = STATS_IDX(stream_info->stream_handle[vfe_idx]); @@ -2525,7 +2523,6 @@ void msm_vfe47_stats_update_ping_pong_addr( msm_camera_io_w(paddr32, vfe_base + VFE47_STATS_PING_PONG_BASE(stats_idx, pingpong_status)); - paddr32_max = (paddr + buf_size) & 0xFFFFFFE0; msm_camera_io_w(paddr32_max, vfe_base + VFE47_STATS_PING_PONG_BASE(stats_idx, pingpong_status) + 0x4); } @@ -2893,8 +2890,12 @@ int msm_vfe47_get_regulators(struct vfe_device *vfe_dev) int msm_vfe47_enable_regulators(struct vfe_device *vfe_dev, int enable) { - return msm_camera_regulator_enable(vfe_dev->regulator_info, + if (enable) + return msm_camera_regulator_enable(vfe_dev->regulator_info, vfe_dev->vfe_num_regulators, enable); + else + return msm_camera_regulator_disable(vfe_dev->regulator_info, + vfe_dev->vfe_num_regulators, true); } int msm_vfe47_get_platform_data(struct vfe_device *vfe_dev) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h index 5b90343adff2..6a2f4c2974da 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016, 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,7 +22,7 @@ enum msm_vfe_clk_rates { MSM_VFE_MAX_CLK_RATES = 3, }; -#define MSM_VFE48_HW_VERSION 0x8 +#define MSM_VFE48_HW_VERSION 0x9 #define MSM_VFE48_HW_VERSION_SHIFT 28 #define MSM_VFE48_HW_VERSION_MASK 0xF diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c index 60372f85044d..d49ed55597e4 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c @@ -1524,7 +1524,7 @@ int msm_isp_proc_cmd(struct vfe_device *vfe_dev, void *arg) goto copy_cmd_failed; } } else { - pr_err("%s: Passed cmd_len as 0\n", __func__); + pr_debug("%s: Passed cmd_len as 0\n", __func__); } for (i = 0; i < proc_cmd->num_cfg; i++) rc = msm_isp_send_hw_cmd(vfe_dev, ®_cfg_cmd[i], diff --git a/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.c b/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.c index 698281b1512c..81e0d7cd3d33 100644 --- a/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.c +++ b/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "msm_jpeg_dma_dev.h" #include "msm_jpeg_dma_hw.h" diff --git a/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.h b/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.h index 50b7941a4c49..1f7008c0902d 100644 --- a/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.h +++ b/drivers/media/platform/msm/camera_v2/jpeg_dma/msm_jpeg_dma_dev.h @@ -1,4 +1,5 @@ -/* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. + * All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -232,7 +233,7 @@ struct msm_jpegdma_buf_handle { int fd; struct msm_jpegdma_device *dma; unsigned long size; - ion_phys_addr_t addr; + dma_addr_t addr; }; /* diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c index 5b8a13abf2a0..f2b2658c1524 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c +++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1093,7 +1093,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) goto clk_failed; } } - + msm_cpp_update_bandwidth(cpp_dev, 0x1000, 0x1000); rc = msm_camera_clk_enable(&cpp_dev->pdev->dev, cpp_dev->clk_info, cpp_dev->cpp_clk, cpp_dev->num_clks, true); if (rc < 0) { @@ -1184,8 +1184,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) msm_camera_clk_enable(&cpp_dev->pdev->dev, cpp_dev->clk_info, cpp_dev->cpp_clk, cpp_dev->num_clks, false); clk_failed: - msm_camera_regulator_enable(cpp_dev->cpp_vdd, - cpp_dev->num_reg, false); + msm_camera_regulator_disable(cpp_dev->cpp_vdd, cpp_dev->num_reg, true); reg_enable_failed: return rc; } @@ -1204,9 +1203,9 @@ static void cpp_release_hardware(struct cpp_device *cpp_dev) if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CPP, CAM_AHB_SUSPEND_VOTE) < 0) pr_err("%s: failed to remove vote for AHB\n", __func__); - msm_camera_clk_enable(&cpp_dev->pdev->dev, cpp_dev->clk_info, + msm_camera_cpp_clk_disable(&cpp_dev->pdev->dev, cpp_dev->clk_info, cpp_dev->cpp_clk, cpp_dev->num_clks, false); - msm_camera_regulator_enable(cpp_dev->cpp_vdd, cpp_dev->num_reg, false); + msm_camera_regulator_disable(cpp_dev->cpp_vdd, cpp_dev->num_reg, true); if (cpp_dev->stream_cnt > 0) { pr_warn("stream count active\n"); rc = msm_cpp_update_bandwidth_setting(cpp_dev, 0, 0); @@ -4094,7 +4093,7 @@ static long msm_cpp_subdev_fops_compat_ioctl(struct file *file, status = compat_ptr(k32_frame_info.status); if (copy_to_user(status, &rc, - sizeof(void *))) + sizeof(int32_t))) pr_err("error cannot copy error\n"); if (copy_to_user((void __user *)kp_ioctl.ioctl_ptr, diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h index 90b8e1cae850..409c3e97c945 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -53,7 +53,7 @@ static struct csiphy_reg_3ph_parms_t csiphy_v3_5_3ph = { {0x154, 0x0}, {0x15C, 0x33}, {0x160, ULPM_WAKE_UP_TIMER_MODE}, - {0x164, 0x48}, + {0x164, 0x50}, {0x168, 0xA0}, {0x16C, 0x17}, {0x170, 0x41}, -- GitLab From d9ccc57e2f77ad8aafaacfc0dad9f8cb49659c02 Mon Sep 17 00:00:00 2001 From: Abhishek Jain Date: Wed, 30 Jan 2019 18:13:22 +0530 Subject: [PATCH 1251/1286] defconfig: trinket: Enable Jpeg DMA on trinket Enable Jpeg DMA required for thumbnail creation on trinket. Signed-off-by: Abhishek Jain Change-Id: Id925e7982a8033c636f8ab4f15b9afb78e32db13 --- arch/arm64/configs/vendor/trinket-perf_defconfig | 1 + arch/arm64/configs/vendor/trinket_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index d5cc20275b3f..6323f3ccfebf 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -403,6 +403,7 @@ CONFIG_OV12830=y CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y +CONFIG_MSM_JPEGDMA=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 0a5dd6fec494..f5e6de151b69 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -418,6 +418,7 @@ CONFIG_OV12830=y CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y +CONFIG_MSM_JPEGDMA=y CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y -- GitLab From 2ada70131f44badc10684c8978f67314bd9f37a5 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Tue, 22 Jan 2019 17:22:36 +0530 Subject: [PATCH 1252/1286] ARM: dts: msm: add support for throttle and div clocks on TRINKET Add support for throttle and div clocks on TRINKET target. Change-Id: I54a511af2b1f4cea73efcff45d9eb83407b4a524 Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi index f5b526bb27d5..103955b11c9c 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -25,16 +25,18 @@ clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&clock_gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", "div_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; - clock-rate = <0 0 0 256000000 19200000 192000000>; - clock-max-rate = <0 0 0 307000000 19200000 307000000>; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 307000000 19200000 307000000>; sde-vdd-supply = <&mdss_core_gdsc>; -- GitLab From 907eb8c1e17eb9461fcd6efcbf180822a3ebf402 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Thu, 24 Jan 2019 19:07:03 +0530 Subject: [PATCH 1253/1286] power: smb5: Fix usb input current reporting For PMI632, the scaling factor of USB input current channel is different from that of PM8150B and PM6150 due to which incorrect usb input current is getting reported. Add support to select the ADC channel scaling factor based on PMI type to fix this. Change-Id: I610ec44aa24cb3a83ac2bf886f3210d06d94f72a Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/smb5-lib.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index e5bb720e4a99..6c5328a7d326 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -3345,7 +3345,7 @@ int smblib_get_prop_usb_current_now(struct smb_charger *chg, union power_supply_propval *val) { union power_supply_propval pval = {0, }; - int rc = 0; + int rc = 0, buck_scale = 1, boost_scale = 1; if (chg->iio.usbin_i_chan) { rc = iio_read_channel_processed(chg->iio.usbin_i_chan, @@ -3358,10 +3358,24 @@ int smblib_get_prop_usb_current_now(struct smb_charger *chg, /* * For PM8150B, scaling factor = reciprocal of * 0.2V/A in Buck mode, 0.4V/A in Boost mode. + * For PMI632, scaling factor = reciprocal of + * 0.4V/A in Buck mode, 0.8V/A in Boost mode. */ + switch (chg->smb_version) { + case PMI632_SUBTYPE: + buck_scale = 40; + boost_scale = 80; + break; + default: + buck_scale = 20; + boost_scale = 40; + break; + } + if (chg->otg_present || smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_NONE) { - val->intval = DIV_ROUND_CLOSEST(val->intval * 100, 40); + val->intval = DIV_ROUND_CLOSEST(val->intval * 100, + boost_scale); return rc; } @@ -3376,7 +3390,8 @@ int smblib_get_prop_usb_current_now(struct smb_charger *chg, if (!pval.intval) val->intval = 0; else - val->intval *= 5; + val->intval = DIV_ROUND_CLOSEST(val->intval * 100, + buck_scale); } else { val->intval = 0; rc = -ENODATA; -- GitLab From d15d7cb87d45fdb68f714405e4fd7b67cd505b4b Mon Sep 17 00:00:00 2001 From: Dilip Kota Date: Thu, 31 Jan 2019 14:44:50 +0530 Subject: [PATCH 1254/1286] ARM: dts: msm: Configure SMR masks as per SMMU SAC SMMU team recommends specific SMR masks because of limited SMR registers. Change-Id: Ic49df334e307df6847e8c3d28713b60e1ca68cac Signed-off-by: Dilip Kota --- arch/arm64/boot/dts/qcom/sdmmagpie.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi index f5cb18c3ab2e..04ade5caac96 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie.dtsi @@ -1160,9 +1160,8 @@ iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; - iommus = <&apps_smmu 0x1be6 0x0>, - <&apps_smmu 0x1bed 0x0>, - <&apps_smmu 0x1bee 0x1>, + iommus = <&apps_smmu 0x1be6 0x8>, + <&apps_smmu 0x1bed 0x2>, <&apps_smmu 0x1bf0 0x1>; }; -- GitLab From 0b838e4e5ebbe24ff07ab5c7631be2937f21afae Mon Sep 17 00:00:00 2001 From: Samyukta Mogily Date: Tue, 29 Jan 2019 14:49:19 +0530 Subject: [PATCH 1255/1286] msm: sensor: Copy camera power down settings correctly Else condition missing in power down settings, which is leading to power down data corruption. Change-Id: Ia54464d16cfd900b6f5d09234a1c3d54c9c0d4bc Signed-off-by: Samyukta Mogily --- .../msm/camera_v2/sensor/msm_sensor_driver.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor_driver.c b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor_driver.c index b20bb7608135..7d7b5cde2f66 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor_driver.c +++ b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor_driver.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -577,15 +577,16 @@ static int32_t msm_sensor_get_power_down_settings(void *setting, kfree(pd); return -EFAULT; } - } + } else #endif - if (copy_from_user( - pd, (void __user *)slave_info->power_setting_array - .power_down_setting, sizeof(*pd) * size_down)) { - pr_err("failed: copy_from_user"); - kfree(pd); - return -EFAULT; - } + if (copy_from_user(pd, + (void __user *)slave_info->power_setting_array + .power_down_setting, + sizeof(*pd) * size_down)) { + pr_err("failed: copy_from_user"); + kfree(pd); + return -EFAULT; + } } else { rc = msm_sensor_create_pd_settings(setting, pd, size_down, -- GitLab From 454ec00275324770136ca0393382515591b8768f Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Tue, 29 Jan 2019 17:09:52 +0530 Subject: [PATCH 1256/1286] iommu: arm-smmu: improve tlbsync timeout debugging Call BUG() right after the first TLB sync timeout which will helps in getting the system state information at that point of time that further helps in debugging. Change-Id: Id2d3eb491080b12486c99966da72afe2f6deefb4 Signed-off-by: Charan Teja Reddy --- drivers/iommu/Kconfig | 10 ++++++++++ drivers/iommu/arm-smmu.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index a0320bf64804..9f0df503cd76 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -371,6 +371,16 @@ config ARM_SMMU_SELFTEST If unsure, say N here. +config IOMMU_TLBSYNC_DEBUG + bool "TLB sync timeout debug" + depends on ARM_SMMU + help + Enables to collect the SMMU system state information right + after the first TLB sync timeout failure by calling BUG(). + Note to use this only on debug builds. + + If unsure, say N here. + config QCOM_LAZY_MAPPING bool "Reference counted iommu-mapping support" depends on ION diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index d4a85539fcca..4b197aa025fb 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1120,6 +1120,8 @@ static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, dev_err_ratelimited(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked, ack 0x%x\n", sync_inv_ack); + BUG_ON(IS_ENABLED(CONFIG_IOMMU_TLBSYNC_DEBUG)); + return -EINVAL; } -- GitLab From 0165c3a8869645c151cea7bb7f45867ba4a34cda Mon Sep 17 00:00:00 2001 From: Vevek Venkatesan Date: Thu, 31 Jan 2019 16:15:27 +0530 Subject: [PATCH 1257/1286] ARM: dts: msm: remove power regulator for touch driver in trinket Remove the power regulator config for touch controller in trinket as no touch load connected with these regulators. Change-Id: I1cbb9c0dbb6d67c81de2cd9d354746f258ed00f7 Signed-off-by: Vevek Venkatesan --- arch/arm64/boot/dts/qcom/trinket-idp.dtsi | 4 ---- arch/arm64/boot/dts/qcom/trinket-qrd.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi index dd2ebc4852bf..be989987f4e7 100644 --- a/arch/arm64/boot/dts/qcom/trinket-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-idp.dtsi @@ -313,15 +313,11 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <88 0x2008>; - vdd-supply = <&pm6125_l9>; - avdd-supply = <&pm6125_l21>; pinctrl-names = "pmx_ts_active","pmx_ts_suspend", "pmx_ts_release"; pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; - synaptics,bus-reg-name = "vdd"; - synaptics,pwr-reg-name = "avdd"; synaptics,irq-gpio = <&tlmm 88 0x2008>; synaptics,irq-on-state = <0>; synaptics,reset-gpio = <&tlmm 87 0x00>; diff --git a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi index b90e75567e0b..6bc00dc538e9 100644 --- a/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-qrd.dtsi @@ -63,15 +63,11 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <88 0x2008>; - vdd-supply = <&pm6125_l9>; - avdd-supply = <&pm6125_l21>; pinctrl-names = "pmx_ts_active","pmx_ts_suspend", "pmx_ts_release"; pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; - synaptics,bus-reg-name = "vdd"; - synaptics,pwr-reg-name = "avdd"; synaptics,irq-gpio = <&tlmm 88 0x2008>; synaptics,irq-on-state = <0>; synaptics,reset-gpio = <&tlmm 87 0x00>; -- GitLab From 08af65e6d50a6fd2f31f21a747d960805965c3c1 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 30 Jan 2019 21:54:21 +0530 Subject: [PATCH 1258/1286] ARM: dts: msm: Configure hph_swh and gnd_swh for trinket USBC Trinket USBC has Normally Open switch whereas Normally Closed switch is used for other targets. Configure hph_swh and gnd_swh in trinket USBC dtsi. Change-Id: I6fe9f45583b86450b2f88e3b432c5142f39f48f4 Signed-off-by: Vatsal Bucha --- arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi index 574908e27456..de74ff642f7b 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usbc-idp.dtsi @@ -14,4 +14,6 @@ &sm6150_snd { qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; }; -- GitLab From 59b96182e4acb397e1dbd69d1acca155834f79c7 Mon Sep 17 00:00:00 2001 From: Shubhashree Dhar Date: Thu, 31 Jan 2019 16:48:12 +0530 Subject: [PATCH 1259/1286] ARM: dts: msm: add ubwc 1.0 support for TRINKET Add rotator ubwc 1.0 support for trinket target. Change-Id: Idd876cc8f01bf783e7fae8cd73170d1413bb98e4 Signed-off-by: Shubhashree Dhar --- arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi index f5b526bb27d5..7345a3de7df2 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -254,6 +254,8 @@ qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x1>; + qcom,sde-ubwc-malsize = <0x1>; + qcom,sde-ubwc_swizzle = <0x1>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; -- GitLab From 48ea38e528b1aa69d09b5eb747f546e8adb34f2d Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Thu, 31 Jan 2019 16:24:40 +0530 Subject: [PATCH 1260/1286] ARM: dts: msm: Update cpu and gpu thermal zones threshold for QCS405 Update cpu and gpu thermal zone trip thresholds for QCS405 based on latest recommendation. Change-Id: Ic85c72fc97837b406315abb7fdcd77137c22d2af Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/qcs405-thermal.dtsi | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs405-thermal.dtsi b/arch/arm64/boot/dts/qcom/qcs405-thermal.dtsi index f34652c7411b..89ea35cba095 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-thermal.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -196,7 +196,7 @@ thermal-governor = "step_wise"; trips { cpu_trip:cpu-trip { - temperature = <85000>; + temperature = <105000>; hysteresis = <0>; type = "passive"; }; @@ -236,7 +236,7 @@ thermal-governor = "step_wise"; trips { gpu_step_trip: gpu-step-trip { - temperature = <95000>; + temperature = <105000>; hysteresis = <0>; type = "passive"; }; @@ -258,8 +258,8 @@ thermal-governor = "step_wise"; trips { cpuss_0_step_trip: cpuss-0-step-trip { - temperature = <105000>; - hysteresis = <15000>; + temperature = <118000>; + hysteresis = <10000>; type = "passive"; }; }; @@ -280,8 +280,8 @@ thermal-governor = "step_wise"; trips { cpuss_1_step_trip: cpuss-1-step-trip { - temperature = <105000>; - hysteresis = <15000>; + temperature = <118000>; + hysteresis = <10000>; type = "passive"; }; }; @@ -302,8 +302,8 @@ thermal-governor = "step_wise"; trips { cpuss_2_step_trip: cpuss-2-step-trip { - temperature = <105000>; - hysteresis = <15000>; + temperature = <118000>; + hysteresis = <10000>; type = "passive"; }; }; @@ -324,8 +324,8 @@ thermal-governor = "step_wise"; trips { cpuss_3_step_trip: cpuss-3-step-trip { - temperature = <105000>; - hysteresis = <15000>; + temperature = <118000>; + hysteresis = <10000>; type = "passive"; }; }; -- GitLab From 6e33809751fcf42c3fd09c37f0e0873b43a8cb83 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Fri, 11 Jan 2019 15:10:19 +0530 Subject: [PATCH 1261/1286] ARM: dts: msm: Disable the IPA Stage 1 for SM6125 target Disabling the IPA Stage 1 for SM6125 target, because facing issue in enabling stage 1 for other dependent WLAN client. Change-Id: I1078bcfd20a7d60220035fb613c371e4aa4b0702 Signed-off-by: Praveen Kurapati --- arch/arm64/boot/dts/qcom/trinket.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2504302d2872..edc5732768fc 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -2218,6 +2218,7 @@ ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x00E0 0x0>; qcom,iova-mapping = <0x10000000 0x30000000>; /* modem tables in IMEM */ -- GitLab From 6847a928c49f615fd00e57d80d4562040c86dec0 Mon Sep 17 00:00:00 2001 From: Lee Susman Date: Tue, 8 Oct 2013 09:47:59 +0300 Subject: [PATCH 1262/1286] mm: change max readahead size to 512KB Change the VM_MAX_READAHEAD value from the default 128KB to 512KB. This will allow the readahead window to grow to a maximum size of 512KB, which greatly benefits to sequential read throughput. Change-Id: Ia0780ea4e2a4ae0b6111485b72fb25376dcb1f96 Signed-off-by: Lee Susman --- include/linux/mm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mm.h b/include/linux/mm.h index 6e72885d23d4..fad2a257e730 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2362,7 +2362,7 @@ int __must_check write_one_page(struct page *page); void task_dirty_inc(struct task_struct *tsk); /* readahead.c */ -#define VM_MAX_READAHEAD 128 /* kbytes */ +#define VM_MAX_READAHEAD 512 /* kbytes */ #define VM_MIN_READAHEAD 16 /* kbytes (includes current page) */ int force_page_cache_readahead(struct address_space *mapping, struct file *filp, -- GitLab From b9ac378eb05719651901646d12356e4aa932076c Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Thu, 31 Jan 2019 18:53:43 +0530 Subject: [PATCH 1263/1286] ARM: defconfig: Set CONFIG_MMC_TEST as module In some rare case, it is observed that mmc driver is getting registered as mmc_test instead of mmcblk and resulting in NULL pointer deference issue for sdcard. To fix this, set CONFIG_MMC_TEST as module to make sure mmcblk will get registered first. Change-Id: Ia0f31a622ba88ee81ad7061dde2a392ba30a6be6 Signed-off-by: Sayali Lokhande --- arch/arm64/configs/vendor/sa8155-perf_defconfig | 2 +- arch/arm64/configs/vendor/sa8155_defconfig | 2 +- arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig | 2 +- arch/arm64/configs/vendor/sdmsteppe-auto_defconfig | 2 +- arch/arm64/configs/vendor/sdmsteppe-perf_defconfig | 2 +- arch/arm64/configs/vendor/sdmsteppe_defconfig | 2 +- arch/arm64/configs/vendor/sm8150-perf_defconfig | 2 +- arch/arm64/configs/vendor/sm8150_defconfig | 2 +- arch/arm64/configs/vendor/trinket-perf_defconfig | 2 +- arch/arm64/configs/vendor/trinket_defconfig | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index c00a4ab31dff..2d43d0e6f35e 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -450,7 +450,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index 4005e7d49b10..a79f2bf57389 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -468,7 +468,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index dbd5b5501014..3b52afa32b23 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -471,7 +471,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index bec7f78e9d93..ebc2db509922 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -487,7 +487,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index 7f89c1ea52a3..71a1095eb917 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -471,7 +471,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index e9bab57e2c35..70afcb539fd0 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -495,7 +495,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index d0673727c24a..a01de5b70f71 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -474,7 +474,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index 612eec624896..6c5fd344b0aa 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -490,7 +490,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index d5cc20275b3f..421d357ddd80 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -474,7 +474,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 0a5dd6fec494..d5b1c1027b4a 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -490,7 +490,7 @@ CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=y +CONFIG_MMC_TEST=m CONFIG_MMC_RING_BUFFER=y CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y -- GitLab From 66d36dad22f69f85568a6f9d7e1d0016d88f0c49 Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Tue, 29 Jan 2019 17:24:30 +0530 Subject: [PATCH 1264/1286] vendor: defconfig: enable smmu debug option on trinket Enable the config option for debugging the TLB sync timeout on trinket. Change-Id: Ibbbb80b5b78bb97b49a67b9b725054d06c3c080e Signed-off-by: Charan Teja Reddy --- arch/arm64/configs/vendor/trinket_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index 0a5dd6fec494..6065c8efd988 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -547,6 +547,7 @@ CONFIG_QCOM_APCS_IPC=y CONFIG_MSM_QMP=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y +CONFIG_IOMMU_TLBSYNC_DEBUG=y CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y -- GitLab From 3407b0668ba77227b5669d9ea2887ccc967626c0 Mon Sep 17 00:00:00 2001 From: Abhinay Reddy Vanipally Date: Thu, 24 Jan 2019 21:50:34 -0800 Subject: [PATCH 1265/1286] ARM: dts: msm: Enabling NFC on sm8150-sdx50m QRD platform. Enabling NFC on sm8150-sdx50m QRD platform. Change-Id: I3f3a4de56a3141bb781b849c06753498081d67ed Signed-off-by: Abhinay Reddy Vanipally --- arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts index a93249d372a5..b4d2424cc63f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -30,6 +30,3 @@ qcom,board-id = <11 1>; }; -&qupv3_se9_i2c { - status = "disabled"; -}; -- GitLab From 7281bbf46e578f167f38f577fd45c96a3b083b7b Mon Sep 17 00:00:00 2001 From: David Dai Date: Thu, 31 Jan 2019 14:29:23 -0800 Subject: [PATCH 1266/1286] ARM: dts: msm: trim unused node for sdxprairie Let's trim the unused mss-nav node for sdxprairie since there are no known users for it. Change-Id: I8e1b189a642d9d950bc033cbc35401bdd523c9e1 Signed-off-by: David Dai --- arch/arm64/boot/dts/qcom/sdxprairie-bus.dtsi | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-bus.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-bus.dtsi index 788e01efe301..5f4308c0e216 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-bus.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-bus.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -507,21 +507,6 @@ qcom,prio = <0>; }; - mas_qxm_mss_nav_ce: mas-qxm-mss-nav-ce { - cell-id = ; - label = "mas-qxm-mss-nav-ce"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,qport = <0>; - qcom,connections = <&slv_qns_snoc_memnoc - &slv_qxs_imem &slv_xs_qdss_stm>; - qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn8>; - qcom,ap-owned; - qcom,prio = <0>; - qcom,forwarding; - }; - mas_xm_emac: mas-xm-emac { cell-id = ; label = "mas-xm-emac"; -- GitLab From b691c1f51d82c14355d4b67a6399cc8f4338cebc Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 31 Jan 2019 16:11:23 +0530 Subject: [PATCH 1267/1286] ARM: dts: msm: Configure hph_swh and gnd_swh for sdmmagpie USBC Sdmmagpie USBC has Normally Closed switch for HSDET and GND. Configure hph_swh and gnd_swh in sdmmagpie USBC dtsi. Change-Id: I5ab56103ad01a53bbad67158f6e1d37b4e996855 Signed-off-by: Vatsal Bucha --- arch/arm64/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi index a0584f5e58f0..f79404f3ddae 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,4 +14,6 @@ &sm6150_snd { qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; }; -- GitLab From 22717cf86f36d5b1bc3ee454564372f6d3282a78 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 31 Jan 2019 16:05:09 +0530 Subject: [PATCH 1268/1286] ARM: dts: msm: Configure hph_swh and gnd_swh for sm6150 USBC sm6150 USBC has Normally Closed switch for HSDET and GND. Configure hph_swh and gnd_swh in sm6150 USBC dtsi. Change-Id: I5f936435bf43e4487fa269f494a6b6eeaf3e01a1 Signed-off-by: Vatsal Bucha --- arch/arm64/boot/dts/qcom/sm6150-usbc-idp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-usbc-idp.dtsi b/arch/arm64/boot/dts/qcom/sm6150-usbc-idp.dtsi index 0437415f502f..86330a6c4cf8 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-usbc-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-usbc-idp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,4 +14,6 @@ &sm6150_snd { qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; }; -- GitLab From 486e6713154761f9d162600e99fb9148d5f25192 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 31 Jan 2019 16:14:09 +0530 Subject: [PATCH 1269/1286] ARM: dts: msm: Configure hph_swh and gnd_swh for sm8150 sdx50m USBC SDX50M USBC has Normally Closed switch for HSDET and GND. Configure hph_swh and gnd_swh in sdx50m USBC dtsi. Change-Id: I88f88639c1a624405031d77004d9458f2a5fd62b Signed-off-by: Vatsal Bucha --- arch/arm64/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi index 62c60bad3ce3..eba5354ca883 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,4 +15,6 @@ &snd_934x { qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; }; -- GitLab From 4516ab18718df39d0d4abca78b20e119ec3a9851 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Wed, 30 Jan 2019 16:21:41 +0530 Subject: [PATCH 1270/1286] net: qrtr: avoid deadlock in case of recursive lock for node list Qrtr node list lock can be taken recursively by a thread and in between other thread can contend the same lock for write, this marks the lock as write biased and results in deadlock. Changed qrtr code to avoid taking node list lock recursively and prevent possible deadlock scenario. CR-Fixed: 2384092 Change-Id: Idcdd1b3dbc8c19867c8afcde40ae4dcf08d87d66 Signed-off-by: Deepak Kumar Singh --- net/qrtr/qrtr.c | 49 +++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/net/qrtr/qrtr.c b/net/qrtr/qrtr.c index b5a01378073f..35e84bbb5bea 100644 --- a/net/qrtr/qrtr.c +++ b/net/qrtr/qrtr.c @@ -777,49 +777,44 @@ static struct sk_buff *qrtr_alloc_ctrl_packet(struct qrtr_ctrl_pkt **pkt) static struct qrtr_sock *qrtr_port_lookup(int port); static void qrtr_port_put(struct qrtr_sock *ipc); -static bool qrtr_must_forward(u32 src_nid, u32 dst_nid, u32 type) +static bool qrtr_must_forward(struct qrtr_node *src, + struct qrtr_node *dst, u32 type) { - struct qrtr_node *dst; - struct qrtr_node *src; - bool ret = false; - - if (src_nid == qrtr_local_nid) + /* Node structure is not maintained for local processor. + * Hence src is null in that case. + */ + if (!src) return true; + if (!dst) + return false; + if (type == QRTR_TYPE_HELLO || type == QRTR_TYPE_RESUME_TX) - return ret; + return false; - dst = qrtr_node_lookup(dst_nid); - src = qrtr_node_lookup(src_nid); - if (!dst || !src) - goto out; - if (dst == src) - goto out; - if (dst->nid == QRTR_EP_NID_AUTO) - goto out; + if (dst == src || dst->nid == QRTR_EP_NID_AUTO) + return false; if (abs(dst->net_id - src->net_id) > 1) - ret = true; - -out: - qrtr_node_release(dst); - qrtr_node_release(src); + return true; - return ret; + return false; } static void qrtr_fwd_ctrl_pkt(struct sk_buff *skb) { struct qrtr_node *node; + struct qrtr_node *src; struct qrtr_cb *cb = (struct qrtr_cb *)skb->cb; + src = qrtr_node_lookup(cb->src_node); down_read(&qrtr_node_lock); list_for_each_entry(node, &qrtr_all_epts, item) { struct sockaddr_qrtr from; struct sockaddr_qrtr to; struct sk_buff *skbn; - if (!qrtr_must_forward(cb->src_node, node->nid, cb->type)) + if (!qrtr_must_forward(src, node, cb->type)) continue; skbn = skb_clone(skb, GFP_KERNEL); @@ -837,6 +832,7 @@ static void qrtr_fwd_ctrl_pkt(struct sk_buff *skb) qrtr_node_enqueue(node, skbn, cb->type, &from, &to, 0); } up_read(&qrtr_node_lock); + qrtr_node_release(src); } static void qrtr_fwd_pkt(struct sk_buff *skb, struct qrtr_cb *cb) @@ -989,7 +985,7 @@ static void qrtr_fwd_del_proc(struct qrtr_node *src, unsigned int nid) struct sk_buff *skb; list_for_each_entry(dst, &qrtr_all_epts, item) { - if (!qrtr_must_forward(nid, dst->nid, QRTR_TYPE_DEL_PROC)) + if (!qrtr_must_forward(src, dst, QRTR_TYPE_DEL_PROC)) continue; skb = qrtr_alloc_ctrl_packet(&pkt); @@ -1354,6 +1350,7 @@ static int qrtr_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) struct sock *sk = sock->sk; struct qrtr_ctrl_pkt *pkt; struct qrtr_node *node; + struct qrtr_node *srv_node; struct sk_buff *skb; size_t plen; u32 type = QRTR_TYPE_DATA; @@ -1391,6 +1388,7 @@ static int qrtr_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) } node = NULL; + srv_node = NULL; if (addr->sq_node == QRTR_NODE_BCAST) { enqueue_fn = qrtr_bcast_enqueue; if (addr->sq_port != QRTR_PORT_CTRL) { @@ -1444,11 +1442,14 @@ static int qrtr_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) /* drop new server cmds that are not forwardable to dst node*/ pkt = (struct qrtr_ctrl_pkt *)skb->data; - if (!qrtr_must_forward(pkt->server.node, addr->sq_node, type)) { + srv_node = qrtr_node_lookup(pkt->server.node); + if (!qrtr_must_forward(srv_node, node, type)) { rc = 0; kfree_skb(skb); + qrtr_node_release(srv_node); goto out_node; } + qrtr_node_release(srv_node); } rc = enqueue_fn(node, skb, type, &ipc->us, addr, msg->msg_flags); -- GitLab From 7489ec26ca1bc8e29768c9d7886cc6bfe44e41af Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Tue, 22 Jan 2019 20:31:37 +0530 Subject: [PATCH 1271/1286] ARM: dts: msm: Add GPU_SMMU_CLKON for sm6150 gpu clk list Add GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK in GPU clk list to have SW vote for MMU clock ON request. This will ensure GCC based HW clock gating is disabled for graphics smmu. Change-Id: If67b713f12098fe277941afc38b15a430054f8da Signed-off-by: Hareesh Gundu --- arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi b/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi index b80d84a2f3aa..38f0e13e555e 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi @@ -65,10 +65,12 @@ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&clock_gpucc GPU_CC_CX_GMU_CLK>; clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", - "iface_clk", "mem_iface_clk", "gmu_clk"; + "iface_clk", "mem_iface_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", "gmu_clk"; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; @@ -598,9 +600,11 @@ qcom,protect = <0xa0000 0x10000>; clocks =<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, - <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; - clock-names = "mem_clk", "mem_iface_clk"; + clock-names = "mem_clk", "mem_iface_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; qcom,secure_align_mask = <0xfff>; qcom,retention; @@ -638,9 +642,12 @@ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&clock_gpucc GPU_CC_GX_GFX3D_CLK>; clock-names = "gmu", "rbbmtimer", "mem", - "iface", "mem_iface", "core"; + "iface", "mem_iface", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "core"; }; }; -- GitLab From aab10c398abd343db5f84ae6c52a1748f1e6dc7f Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 15 Dec 2017 09:55:03 +0530 Subject: [PATCH 1272/1286] leds: qpnp-flash-v2: Add support for bharger flash PMI632 flash is driven by the charger in reverse boost (bharger) mode instead of the BoB regulator. Add the necessary changes to support the same. Change-Id: I9166f470f2fdffb12f1c90b1758f606ead2f131a Signed-off-by: Kiran Gunda --- .../bindings/leds/leds-qpnp-flash-v2.txt | 2 + drivers/leds/leds-qpnp-flash-v2.c | 620 ++++++++++++++---- 2 files changed, 501 insertions(+), 121 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt index 8728a1bdbc6a..c8fa87cc8cb5 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt @@ -119,6 +119,8 @@ Optional properties: 2: Flash strobe is used for LED1; GPIO9 is used for LED2; GPIO10 is used for LED3 - switchX-supply : phandle of the regulator that needs to be used as a supply for flash switch_X device. +- qcom,bst-pwm-ovrhd-uv : Charger flash VPH overhead. Applicable for PMI632 only. + Supported values (in mV) are: 300, 400, 500, 600. Default is 300. Child node: Contains settings for each individual LED. Each LED channel needs a flash node and torch node for itself, and an individual switch node to serve as an overall switch. diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c index 04bb1dd5e683..bfbcac67ee50 100644 --- a/drivers/leds/leds-qpnp-flash-v2.c +++ b/drivers/leds/leds-qpnp-flash-v2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -34,132 +34,162 @@ #include "leds.h" #define FLASH_LED_REG_LED_STATUS1(base) (base + 0x08) + #define FLASH_LED_REG_LED_STATUS2(base) (base + 0x09) +#define FLASH_LED_VPH_DROOP_FAULT_MASK BIT(4) + #define FLASH_LED_REG_INT_RT_STS(base) (base + 0x10) + #define FLASH_LED_REG_SAFETY_TMR(base) (base + 0x40) +#define FLASH_LED_SAFETY_TMR_ENABLE BIT(7) + #define FLASH_LED_REG_TGR_CURRENT(base) (base + 0x43) + #define FLASH_LED_REG_MOD_CTRL(base) (base + 0x46) +#define FLASH_LED_MOD_CTRL_MASK BIT(7) +#define FLASH_LED_MOD_ENABLE BIT(7) + #define FLASH_LED_REG_IRES(base) (base + 0x47) + #define FLASH_LED_REG_STROBE_CFG(base) (base + 0x48) +#define FLASH_LED_STROBE_MASK GENMASK(1, 0) + #define FLASH_LED_REG_STROBE_CTRL(base) (base + 0x49) +#define FLASH_LED_HW_SW_STROBE_SEL_BIT BIT(2) +#define FLASH_HW_STROBE_MASK GENMASK(2, 0) + #define FLASH_LED_EN_LED_CTRL(base) (base + 0x4C) +#define FLASH_LED_ENABLE BIT(0) + #define FLASH_LED_REG_HDRM_PRGM(base) (base + 0x4D) +#define FLASH_LED_HDRM_VOL_MASK GENMASK(7, 4) +#define FLASH_LED_HDRM_VOL_SHIFT 4 + #define FLASH_LED_REG_HDRM_AUTO_MODE_CTRL(base) (base + 0x50) #define FLASH_LED_REG_WARMUP_DELAY(base) (base + 0x51) + #define FLASH_LED_REG_ISC_DELAY(base) (base + 0x52) +#define FLASH_LED_ISC_WARMUP_DELAY_MASK GENMASK(1, 0) +#define FLASH_LED_ISC_WARMUP_DELAY_SHIFT 6 + #define FLASH_LED_REG_THERMAL_RMP_DN_RATE(base) (base + 0x55) +#define THERMAL_OTST1_RAMP_CTRL_MASK BIT(7) +#define THERMAL_OTST1_RAMP_CTRL_SHIFT 7 +#define THERMAL_DERATE_SLOW_SHIFT 4 +#define THERMAL_DERATE_SLOW_MASK GENMASK(6, 4) +#define THERMAL_DERATE_FAST_MASK GENMASK(2, 0) + #define FLASH_LED_REG_THERMAL_THRSH1(base) (base + 0x56) +#define FLASH_LED_THERMAL_THRSH_MASK GENMASK(2, 0) + #define FLASH_LED_REG_THERMAL_THRSH2(base) (base + 0x57) #define FLASH_LED_REG_THERMAL_THRSH3(base) (base + 0x58) + #define FLASH_LED_REG_THERMAL_HYSTERESIS(base) (base + 0x59) +#define FLASH_LED_THERMAL_HYSTERESIS_MASK GENMASK(1, 0) + #define FLASH_LED_REG_THERMAL_DEBOUNCE(base) (base + 0x5A) +#define FLASH_LED_THERMAL_DEBOUNCE_MASK GENMASK(1, 0) + #define FLASH_LED_REG_VPH_DROOP_THRESHOLD(base) (base + 0x61) +#define FLASH_LED_VPH_DROOP_HYSTERESIS_MASK GENMASK(5, 4) +#define FLASH_LED_VPH_DROOP_THRESHOLD_MASK GENMASK(2, 0) +#define FLASH_LED_VPH_DROOP_HYST_SHIFT 4 + #define FLASH_LED_REG_VPH_DROOP_DEBOUNCE(base) (base + 0x62) +#define FLASH_LED_VPH_DROOP_DEBOUNCE_MASK GENMASK(1, 0) + #define FLASH_LED_REG_ILED_GRT_THRSH(base) (base + 0x67) +#define FLASH_LED_ILED_GRT_THRSH_MASK GENMASK(5, 0) + #define FLASH_LED_REG_LED1N2_ICLAMP_LOW(base) (base + 0x68) #define FLASH_LED_REG_LED1N2_ICLAMP_MID(base) (base + 0x69) #define FLASH_LED_REG_LED3_ICLAMP_LOW(base) (base + 0x6A) -#define FLASH_LED_REG_LED3_ICLAMP_MID(base) (base + 0x6B) -#define FLASH_LED_REG_MITIGATION_SEL(base) (base + 0x6E) -#define FLASH_LED_REG_MITIGATION_SW(base) (base + 0x6F) -#define FLASH_LED_REG_LMH_LEVEL(base) (base + 0x70) -#define FLASH_LED_REG_MULTI_STROBE_CTRL(base) (base + 0x71) -#define FLASH_LED_REG_LPG_INPUT_CTRL(base) (base + 0x72) -#define FLASH_LED_REG_CURRENT_DERATE_EN(base) (base + 0x76) -#define FLASH_LED_HDRM_VOL_MASK GENMASK(7, 4) +#define FLASH_LED_REG_LED3_ICLAMP_MID(base) (base + 0x6B) #define FLASH_LED_CURRENT_MASK GENMASK(6, 0) -#define FLASH_LED_STROBE_MASK GENMASK(1, 0) -#define FLASH_HW_STROBE_MASK GENMASK(2, 0) -#define FLASH_LED_ISC_WARMUP_DELAY_MASK GENMASK(1, 0) -#define FLASH_LED_CURRENT_DERATE_EN_MASK GENMASK(2, 0) -#define FLASH_LED_VPH_DROOP_DEBOUNCE_MASK GENMASK(1, 0) + +#define FLASH_LED_REG_MITIGATION_SEL(base) (base + 0x6E) #define FLASH_LED_CHGR_MITIGATION_SEL_MASK GENMASK(5, 4) #define FLASH_LED_LMH_MITIGATION_SEL_MASK GENMASK(1, 0) -#define FLASH_LED_ILED_GRT_THRSH_MASK GENMASK(5, 0) -#define FLASH_LED_LMH_LEVEL_MASK GENMASK(1, 0) -#define FLASH_LED_VPH_DROOP_HYSTERESIS_MASK GENMASK(5, 4) -#define FLASH_LED_VPH_DROOP_THRESHOLD_MASK GENMASK(2, 0) -#define FLASH_LED_THERMAL_HYSTERESIS_MASK GENMASK(1, 0) -#define FLASH_LED_THERMAL_DEBOUNCE_MASK GENMASK(1, 0) -#define FLASH_LED_THERMAL_THRSH_MASK GENMASK(2, 0) -#define FLASH_LED_MOD_CTRL_MASK BIT(7) -#define FLASH_LED_HW_SW_STROBE_SEL_BIT BIT(2) -#define FLASH_LED_VPH_DROOP_FAULT_MASK BIT(4) + +#define FLASH_LED_REG_MITIGATION_SW(base) (base + 0x6F) #define FLASH_LED_LMH_MITIGATION_EN_MASK BIT(0) #define FLASH_LED_CHGR_MITIGATION_EN_MASK BIT(4) -#define THERMAL_OTST1_RAMP_CTRL_MASK BIT(7) -#define THERMAL_OTST1_RAMP_CTRL_SHIFT 7 -#define THERMAL_DERATE_SLOW_SHIFT 4 -#define THERMAL_DERATE_SLOW_MASK GENMASK(6, 4) -#define THERMAL_DERATE_FAST_MASK GENMASK(2, 0) -#define LED1N2_FLASH_ONCE_ONLY_BIT BIT(0) +#define FLASH_LED_CHGR_MITIGATION_ENABLE BIT(4) + +#define FLASH_LED_REG_LMH_LEVEL(base) (base + 0x70) +#define FLASH_LED_LMH_LEVEL_MASK GENMASK(1, 0) + +#define FLASH_LED_REG_MULTI_STROBE_CTRL(base) (base + 0x71) #define LED3_FLASH_ONCE_ONLY_BIT BIT(1) +#define LED1N2_FLASH_ONCE_ONLY_BIT BIT(0) + +#define FLASH_LED_REG_LPG_INPUT_CTRL(base) (base + 0x72) #define LPG_INPUT_SEL_BIT BIT(0) +#define FLASH_LED_REG_CURRENT_DERATE_EN(base) (base + 0x76) +#define FLASH_LED_CURRENT_DERATE_EN_MASK GENMASK(2, 0) + #define VPH_DROOP_DEBOUNCE_US_TO_VAL(val_us) (val_us / 8) #define VPH_DROOP_HYST_MV_TO_VAL(val_mv) (val_mv / 25) #define VPH_DROOP_THRESH_VAL_TO_UV(val) ((val + 25) * 100000) #define MITIGATION_THRSH_MA_TO_VAL(val_ma) (val_ma / 100) #define THERMAL_HYST_TEMP_TO_VAL(val, divisor) (val / divisor) -#define FLASH_LED_ISC_WARMUP_DELAY_SHIFT 6 -#define FLASH_LED_WARMUP_DELAY_DEFAULT 2 -#define FLASH_LED_ISC_DELAY_DEFAULT 3 -#define FLASH_LED_VPH_DROOP_DEBOUNCE_DEFAULT 2 -#define FLASH_LED_VPH_DROOP_HYST_SHIFT 4 -#define FLASH_LED_VPH_DROOP_HYST_DEFAULT 2 -#define FLASH_LED_VPH_DROOP_THRESH_DEFAULT 5 -#define FLASH_LED_DEBOUNCE_MAX 3 -#define FLASH_LED_HYSTERESIS_MAX 3 -#define FLASH_LED_VPH_DROOP_THRESH_MAX 7 -#define THERMAL_DERATE_SLOW_MAX 314592 -#define THERMAL_DERATE_FAST_MAX 512 -#define THERMAL_DEBOUNCE_TIME_MAX 64 -#define THERMAL_DERATE_HYSTERESIS_MAX 3 -#define FLASH_LED_THERMAL_THRSH_MIN 3 -#define FLASH_LED_THERMAL_THRSH_MAX 7 -#define FLASH_LED_THERMAL_OTST_LEVELS 3 -#define FLASH_LED_VLED_MAX_DEFAULT_UV 3500000 -#define FLASH_LED_IBATT_OCP_THRESH_DEFAULT_UA 4500000 -#define FLASH_LED_RPARA_DEFAULT_UOHM 0 -#define FLASH_LED_SAFETY_TMR_ENABLE BIT(7) -#define FLASH_LED_LMH_LEVEL_DEFAULT 0 -#define FLASH_LED_LMH_MITIGATION_ENABLE 1 -#define FLASH_LED_LMH_MITIGATION_DISABLE 0 -#define FLASH_LED_CHGR_MITIGATION_ENABLE BIT(4) -#define FLASH_LED_CHGR_MITIGATION_DISABLE 0 -#define FLASH_LED_LMH_MITIGATION_SEL_DEFAULT 2 -#define FLASH_LED_MITIGATION_SEL_MAX 2 -#define FLASH_LED_CHGR_MITIGATION_SEL_SHIFT 4 -#define FLASH_LED_CHGR_MITIGATION_THRSH_DEFAULT 0xA -#define FLASH_LED_CHGR_MITIGATION_THRSH_MAX 0x1F -#define FLASH_LED_LMH_OCV_THRESH_DEFAULT_UV 3700000 -#define FLASH_LED_LMH_RBATT_THRESH_DEFAULT_UOHM 400000 -#define FLASH_LED_IRES_BASE 3 -#define FLASH_LED_IRES_DIVISOR 2500 -#define FLASH_LED_IRES_MIN_UA 5000 -#define FLASH_LED_IRES_DEFAULT_UA 12500 -#define FLASH_LED_IRES_DEFAULT_VAL 0x00 -#define FLASH_LED_HDRM_VOL_SHIFT 4 -#define FLASH_LED_HDRM_VOL_DEFAULT_MV 0x80 -#define FLASH_LED_HDRM_VOL_HI_LO_WIN_DEFAULT_MV 0x04 -#define FLASH_LED_HDRM_VOL_BASE_MV 125 -#define FLASH_LED_HDRM_VOL_STEP_MV 25 -#define FLASH_LED_STROBE_CFG_DEFAULT 0x00 -#define FLASH_LED_HW_STROBE_OPTION_1 0x00 -#define FLASH_LED_HW_STROBE_OPTION_2 0x01 -#define FLASH_LED_HW_STROBE_OPTION_3 0x02 -#define FLASH_LED_ENABLE BIT(0) -#define FLASH_LED_MOD_ENABLE BIT(7) -#define FLASH_LED_DISABLE 0x00 -#define FLASH_LED_SAFETY_TMR_DISABLED 0x13 -#define FLASH_LED_MAX_TOTAL_CURRENT_MA 3750 -#define FLASH_LED_IRES5P0_MAX_CURR_MA 640 -#define FLASH_LED_IRES7P5_MAX_CURR_MA 960 -#define FLASH_LED_IRES10P0_MAX_CURR_MA 1280 -#define FLASH_LED_IRES12P5_MAX_CURR_MA 1600 -#define MAX_IRES_LEVELS 4 +#define FLASH_LED_WARMUP_DELAY_DEFAULT 2 +#define FLASH_LED_ISC_DELAY_DEFAULT 3 +#define FLASH_LED_VPH_DROOP_DEBOUNCE_DEFAULT 2 +#define FLASH_LED_VPH_DROOP_HYST_DEFAULT 2 +#define FLASH_LED_VPH_DROOP_THRESH_DEFAULT 5 +#define BHARGER_FLASH_LED_VPH_DROOP_THRESH_DEFAULT 7 +#define FLASH_LED_DEBOUNCE_MAX 3 +#define FLASH_LED_HYSTERESIS_MAX 3 +#define FLASH_LED_VPH_DROOP_THRESH_MAX 7 +#define THERMAL_DERATE_SLOW_MAX 314592 +#define THERMAL_DERATE_FAST_MAX 512 +#define THERMAL_DEBOUNCE_TIME_MAX 64 +#define THERMAL_DERATE_HYSTERESIS_MAX 3 +#define FLASH_LED_THERMAL_THRSH_MIN 3 +#define FLASH_LED_THERMAL_THRSH_MAX 7 +#define FLASH_LED_THERMAL_OTST_LEVELS 3 +#define FLASH_LED_VLED_MAX_DEFAULT_UV 3500000 +#define FLASH_LED_IBATT_OCP_THRESH_DEFAULT_UA 4500000 +#define FLASH_LED_RPARA_DEFAULT_UOHM 0 +#define FLASH_LED_LMH_LEVEL_DEFAULT 0 +#define FLASH_LED_LMH_MITIGATION_ENABLE 1 +#define FLASH_LED_LMH_MITIGATION_DISABLE 0 +#define FLASH_LED_CHGR_MITIGATION_DISABLE 0 +#define FLASH_LED_LMH_MITIGATION_SEL_DEFAULT 2 +#define FLASH_LED_MITIGATION_SEL_MAX 2 +#define FLASH_LED_CHGR_MITIGATION_SEL_SHIFT 4 +#define FLASH_LED_CHGR_MITIGATION_THRSH_DEFAULT 0xA +#define FLASH_LED_CHGR_MITIGATION_THRSH_MAX 0x1F +#define FLASH_LED_LMH_OCV_THRESH_DEFAULT_UV 3700000 +#define FLASH_LED_LMH_RBATT_THRESH_DEFAULT_UOHM 400000 +#define FLASH_LED_IRES_BASE 3 +#define FLASH_LED_IRES_DIVISOR 2500 +#define FLASH_LED_IRES_MIN_UA 5000 +#define FLASH_LED_IRES_DEFAULT_UA 12500 +#define FLASH_LED_IRES_DEFAULT_VAL 0x00 +#define FLASH_LED_HDRM_VOL_DEFAULT_MV 0x80 +#define FLASH_LED_HDRM_VOL_HI_LO_WIN_DEFAULT_MV 0x04 +#define FLASH_LED_HDRM_VOL_BASE_MV 125 +#define FLASH_LED_HDRM_VOL_STEP_MV 25 +#define FLASH_LED_STROBE_CFG_DEFAULT 0x00 +#define FLASH_LED_HW_STROBE_OPTION_1 0x00 +#define FLASH_LED_HW_STROBE_OPTION_2 0x01 +#define FLASH_LED_HW_STROBE_OPTION_3 0x02 +#define FLASH_LED_DISABLE 0x00 +#define FLASH_LED_SAFETY_TMR_DISABLED 0x13 +#define FLASH_LED_MAX_TOTAL_CURRENT_MA 3750 +#define FLASH_LED_IRES5P0_MAX_CURR_MA 640 +#define FLASH_LED_IRES7P5_MAX_CURR_MA 960 +#define FLASH_LED_IRES10P0_MAX_CURR_MA 1280 +#define FLASH_LED_IRES12P5_MAX_CURR_MA 1600 +#define MAX_IRES_LEVELS 4 +#define FLASH_BST_PWM_OVRHD_MIN_UV 300000 +#define FLASH_BST_PWM_OVRHD_MAX_UV 600000 /* notifier call chain for flash-led irqs */ static ATOMIC_NOTIFIER_HEAD(irq_notifier_list); @@ -259,6 +289,7 @@ struct flash_led_platform_data { u32 led1n2_iclamp_mid_ma; u32 led3_iclamp_low_ma; u32 led3_iclamp_mid_ma; + u32 bst_pwm_ovrhd_uv; u8 isc_delay; u8 warmup_delay; u8 current_derate_en_cfg; @@ -284,6 +315,8 @@ struct qpnp_flash_led { struct flash_node_data *fnode; struct flash_switch_data *snode; struct power_supply *bms_psy; + struct power_supply *main_psy; + struct power_supply *usb_psy; struct notifier_block nb; spinlock_t lock; int num_fnodes; @@ -738,10 +771,13 @@ static int get_property_from_fg(struct qpnp_flash_led *led, return rc; } -#define VOLTAGE_HDRM_DEFAULT_MV 350 +#define VOLTAGE_HDRM_DEFAULT_MV 350 +#define BHARGER_VOLTAGE_HDRM_DEFAULT_MV 400 +#define BHARGER_HEADROOM_OFFSET_MV 50 static int qpnp_flash_led_get_voltage_headroom(struct qpnp_flash_led *led) { int i, voltage_hdrm_mv = 0, voltage_hdrm_max = 0; + u8 pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; for (i = 0; i < led->num_fnodes; i++) { if (led->fnode[i].led_on) { @@ -765,13 +801,18 @@ static int qpnp_flash_led_get_voltage_headroom(struct qpnp_flash_led *led) voltage_hdrm_mv = 350; } + if (pmic_subtype == PMI632_SUBTYPE) + voltage_hdrm_mv += BHARGER_HEADROOM_OFFSET_MV; + voltage_hdrm_max = max(voltage_hdrm_max, voltage_hdrm_mv); } } if (!voltage_hdrm_max) - return VOLTAGE_HDRM_DEFAULT_MV; + return (pmic_subtype == PMI632_SUBTYPE) ? + BHARGER_VOLTAGE_HDRM_DEFAULT_MV : + VOLTAGE_HDRM_DEFAULT_MV; return voltage_hdrm_max; } @@ -782,7 +823,7 @@ static int qpnp_flash_led_get_voltage_headroom(struct qpnp_flash_led *led) #define BOB_EFFICIENCY 900LL #define VIN_FLASH_MIN_UV 3300000LL static int qpnp_flash_led_calc_max_current(struct qpnp_flash_led *led, - int *max_current) + int *max_current) { int ocv_uv, ibat_now, voltage_hdrm_mv, rc; int rbatt_uohm = 0; @@ -883,8 +924,181 @@ static int qpnp_flash_led_calc_max_current(struct qpnp_flash_led *led, return 0; } +static int is_main_psy_available(struct qpnp_flash_led *led) +{ + if (!led->main_psy) { + led->main_psy = power_supply_get_by_name("main"); + if (!led->main_psy) { + pr_err_ratelimited("Couldn't get main_psy\n"); + return -ENODEV; + } + } + + return 0; +} + +static int is_usb_psy_available(struct qpnp_flash_led *led) +{ + if (!led->usb_psy) { + led->usb_psy = power_supply_get_by_name("usb"); + if (!led->usb_psy) { + pr_err_ratelimited("Couldn't get usb_psy\n"); + return -ENODEV; + } + } + + return 0; +} + +#define CHGBST_EFFICIENCY 800LL +#define CHGBST_FLASH_VDIP_MARGIN 10000 +#define VIN_FLASH_UV 5000000 +#define BHARGER_FLASH_LED_MAX_TOTAL_CURRENT_MA 1500 +#define BHARGER_FLASH_LED_WITH_OTG_MAX_TOTAL_CURRENT_MA 1100 +static int qpnp_flash_led_calc_bharger_max_current(struct qpnp_flash_led *led, + int *max_current) +{ + union power_supply_propval pval = {0, }; + int ocv_uv, ibat_now, voltage_hdrm_mv, flash_led_max_total_curr_ma, rc; + int rbatt_uohm = 0, usb_present, otg_enable; + int64_t ibat_flash_ua, avail_flash_ua, avail_flash_power_fw; + int64_t ibat_safe_ua, vin_flash_uv, vph_flash_uv, vph_flash_vdip; + int64_t bst_pwm_ovrhd_uv; + + rc = is_usb_psy_available(led); + if (rc < 0) + return rc; + + rc = power_supply_get_property(led->usb_psy, POWER_SUPPLY_PROP_SCOPE, + &pval); + if (rc < 0) { + pr_err("usb psy does not support usb present, rc=%d\n", rc); + return rc; + } + otg_enable = pval.intval; + + /* RESISTANCE = esr_uohm + rslow_uohm */ + rc = get_property_from_fg(led, POWER_SUPPLY_PROP_RESISTANCE, + &rbatt_uohm); + if (rc < 0) { + pr_err("bms psy does not support resistance, rc=%d\n", rc); + return rc; + } + + /* If no battery is connected, return max possible flash current */ + if (!rbatt_uohm) { + *max_current = (otg_enable == POWER_SUPPLY_SCOPE_SYSTEM) ? + BHARGER_FLASH_LED_WITH_OTG_MAX_TOTAL_CURRENT_MA : + BHARGER_FLASH_LED_MAX_TOTAL_CURRENT_MA; + return 0; + } + + rc = get_property_from_fg(led, POWER_SUPPLY_PROP_VOLTAGE_OCV, &ocv_uv); + if (rc < 0) { + pr_err("bms psy does not support OCV, rc=%d\n", rc); + return rc; + } + + rc = get_property_from_fg(led, POWER_SUPPLY_PROP_CURRENT_NOW, + &ibat_now); + if (rc < 0) { + pr_err("bms psy does not support current, rc=%d\n", rc); + return rc; + } + + bst_pwm_ovrhd_uv = led->pdata->bst_pwm_ovrhd_uv; + + rc = power_supply_get_property(led->usb_psy, POWER_SUPPLY_PROP_PRESENT, + &pval); + if (rc < 0) { + pr_err("usb psy does not support usb present, rc=%d\n", rc); + return rc; + } + usb_present = pval.intval; + + rbatt_uohm += led->pdata->rpara_uohm; + voltage_hdrm_mv = qpnp_flash_led_get_voltage_headroom(led); + vph_flash_vdip = + VPH_DROOP_THRESH_VAL_TO_UV(led->pdata->vph_droop_threshold) + + CHGBST_FLASH_VDIP_MARGIN; + + /* Check if LMH_MITIGATION needs to be triggered */ + if (!led->trigger_lmh && (ocv_uv < led->pdata->lmh_ocv_threshold_uv || + rbatt_uohm > led->pdata->lmh_rbatt_threshold_uohm)) { + led->trigger_lmh = true; + rc = qpnp_flash_led_masked_write(led, + FLASH_LED_REG_MITIGATION_SW(led->base), + FLASH_LED_LMH_MITIGATION_EN_MASK, + FLASH_LED_LMH_MITIGATION_ENABLE); + if (rc < 0) { + pr_err("trigger lmh mitigation failed, rc=%d\n", rc); + return rc; + } + + /* Wait for LMH mitigation to take effect */ + udelay(100); + + return qpnp_flash_led_calc_bharger_max_current(led, + max_current); + } + + /* + * Calculate the maximum current that can pulled out of the battery + * before the battery voltage dips below a safe threshold. + */ + ibat_safe_ua = div_s64((ocv_uv - vph_flash_vdip) * UCONV, + rbatt_uohm); + + if (ibat_safe_ua <= led->pdata->ibatt_ocp_threshold_ua) { + /* + * If the calculated current is below the OCP threshold, then + * use it as the possible flash current. + */ + ibat_flash_ua = ibat_safe_ua - ibat_now; + vph_flash_uv = vph_flash_vdip; + } else { + /* + * If the calculated current is above the OCP threshold, then + * use the ocp threshold instead. + * + * Any higher current will be tripping the battery OCP. + */ + ibat_flash_ua = led->pdata->ibatt_ocp_threshold_ua - ibat_now; + vph_flash_uv = ocv_uv - div64_s64((int64_t)rbatt_uohm + * led->pdata->ibatt_ocp_threshold_ua, UCONV); + } + + /* when USB is present or OTG is enabled, VIN_FLASH is always at 5V */ + if (usb_present || (otg_enable == POWER_SUPPLY_SCOPE_SYSTEM)) + vin_flash_uv = VIN_FLASH_UV; + else + /* Calculate the input voltage of the flash module. */ + vin_flash_uv = max((led->pdata->vled_max_uv + + (voltage_hdrm_mv * MCONV)), + vph_flash_uv + bst_pwm_ovrhd_uv); + + /* Calculate the available power for the flash module. */ + avail_flash_power_fw = CHGBST_EFFICIENCY * vph_flash_uv * ibat_flash_ua; + /* + * Calculate the available amount of current the flash module can draw + * before collapsing the battery. (available power/ flash input voltage) + */ + avail_flash_ua = div64_s64(avail_flash_power_fw, vin_flash_uv * MCONV); + flash_led_max_total_curr_ma = otg_enable ? + BHARGER_FLASH_LED_WITH_OTG_MAX_TOTAL_CURRENT_MA : + BHARGER_FLASH_LED_MAX_TOTAL_CURRENT_MA; + *max_current = min(flash_led_max_total_curr_ma, + (int)(div64_s64(avail_flash_ua, MCONV))); + + pr_debug("avail_iflash=%lld, ocv=%d, ibat=%d, rbatt=%d, trigger_lmh=%d max_current=%lld usb_present=%d otg_enable=%d\n", + avail_flash_ua, ocv_uv, ibat_now, rbatt_uohm, led->trigger_lmh, + (*max_current * MCONV), usb_present, otg_enable); + return 0; +} + + static int qpnp_flash_led_calc_thermal_current_lim(struct qpnp_flash_led *led, - int *thermal_current_lim) + int *thermal_current_lim) { int rc; u8 thermal_thrsh1, thermal_thrsh2, thermal_thrsh3, otst_status; @@ -974,9 +1188,16 @@ static int qpnp_flash_led_get_max_avail_current(struct qpnp_flash_led *led, int *max_avail_current) { int thermal_current_lim = 0, rc; + u8 pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; led->trigger_lmh = false; - rc = qpnp_flash_led_calc_max_current(led, max_avail_current); + + if (pmic_subtype == PMI632_SUBTYPE) + rc = qpnp_flash_led_calc_bharger_max_current(led, + max_avail_current); + else + rc = qpnp_flash_led_calc_max_current(led, max_avail_current); + if (rc < 0) { pr_err("Couldn't calculate max_avail_current, rc=%d\n", rc); return rc; @@ -1018,6 +1239,7 @@ static void qpnp_flash_led_node_set(struct flash_node_data *fnode, int value) int prgm_current_ma = value; int min_ma = fnode->ires_ua / 1000; struct qpnp_flash_led *led = dev_get_drvdata(&fnode->pdev->dev); + u8 pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; if (value <= 0) prgm_current_ma = 0; @@ -1052,7 +1274,8 @@ static void qpnp_flash_led_node_set(struct flash_node_data *fnode, int value) if (prgm_current_ma) fnode->led_on = true; - if (led->pdata->chgr_mitigation_sel == FLASH_SW_CHARGER_MITIGATION) { + if (pmic_subtype != PMI632_SUBTYPE && + led->pdata->chgr_mitigation_sel == FLASH_SW_CHARGER_MITIGATION) { qpnp_flash_led_aggregate_max_current(fnode); led->trigger_chgr = false; if (led->total_current_ma >= 1000) @@ -1082,7 +1305,7 @@ static int qpnp_flash_led_switch_disable(struct flash_switch_data *snode) } } - if (!led->trigger_chgr) { + if (led->pdata->chgr_mitigation_sel && !led->trigger_chgr) { rc = qpnp_flash_led_masked_write(led, FLASH_LED_REG_MITIGATION_SW(led->base), FLASH_LED_CHGR_MITIGATION_EN_MASK, @@ -1213,9 +1436,51 @@ static int qpnp_flash_led_symmetry_config(struct flash_switch_data *snode) return 0; } +#define FLASH_LED_MODULE_EN_TIME_MS 300 +static int qpnp_flash_poll_vreg_ok(struct qpnp_flash_led *led) +{ + int rc, i; + union power_supply_propval pval = {0, }; + + rc = is_main_psy_available(led); + if (rc < 0) + return rc; + + for (i = 0; i < 60; i++) { + /* wait for the flash vreg_ok to be set */ + mdelay(5); + + rc = power_supply_get_property(led->main_psy, + POWER_SUPPLY_PROP_FLASH_TRIGGER, &pval); + if (rc < 0) { + pr_err("main psy doesn't support reading prop %d rc = %d\n", + POWER_SUPPLY_PROP_FLASH_TRIGGER, rc); + return rc; + } + + if (pval.intval > 0) { + pr_debug("Flash trigger set\n"); + break; + } + + if (pval.intval < 0) { + pr_err("Error during flash trigger %d\n", pval.intval); + return pval.intval; + } + } + + if (!pval.intval) { + pr_err("Failed to enable the module\n"); + return -ETIMEDOUT; + } + + return 0; +} + static int qpnp_flash_led_switch_set(struct flash_switch_data *snode, bool on) { struct qpnp_flash_led *led = dev_get_drvdata(&snode->pdev->dev); + u8 pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; int rc, i, addr_offset; u8 val, mask; @@ -1310,6 +1575,19 @@ static int qpnp_flash_led_switch_set(struct flash_switch_data *snode, bool on) FLASH_LED_MOD_CTRL_MASK, FLASH_LED_MOD_ENABLE); if (rc < 0) return rc; + + if (pmic_subtype == PMI632_SUBTYPE) { + rc = qpnp_flash_poll_vreg_ok(led); + if (rc < 0) { + /* Disable the module */ + qpnp_flash_led_masked_write(led, + FLASH_LED_REG_MOD_CTRL(led->base), + FLASH_LED_MOD_CTRL_MASK, + FLASH_LED_DISABLE); + + return rc; + } + } } led->enable++; @@ -1326,7 +1604,7 @@ static int qpnp_flash_led_switch_set(struct flash_switch_data *snode, bool on) udelay(500); } - if (led->trigger_chgr) { + if (led->pdata->chgr_mitigation_sel && led->trigger_chgr) { rc = qpnp_flash_led_masked_write(led, FLASH_LED_REG_MITIGATION_SW(led->base), FLASH_LED_CHGR_MITIGATION_EN_MASK, @@ -1347,27 +1625,28 @@ static int qpnp_flash_led_switch_set(struct flash_switch_data *snode, bool on) return 0; } -int qpnp_flash_led_prepare(struct led_trigger *trig, int options, - int *max_current) +static int qpnp_flash_led_regulator_control(struct led_classdev *led_cdev, + int options, int *max_current) { - struct led_classdev *led_cdev; + int rc; + u8 pmic_subtype; struct flash_switch_data *snode; struct qpnp_flash_led *led; - int rc; - - if (!trig) { - pr_err("Invalid led_trigger provided\n"); - return -EINVAL; - } - - led_cdev = trigger_to_lcdev(trig); - if (!led_cdev) { - pr_err("Invalid led_cdev in trigger %s\n", trig->name); - return -EINVAL; - } + union power_supply_propval ret = {0, }; snode = container_of(led_cdev, struct flash_switch_data, cdev); led = dev_get_drvdata(&snode->pdev->dev); + pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; + + if (pmic_subtype == PMI632_SUBTYPE) { + rc = is_main_psy_available(led); + if (rc < 0) + return rc; + + rc = is_usb_psy_available(led); + if (rc < 0) + return rc; + } if (!(options & FLASH_LED_PREPARE_OPTIONS_MASK)) { pr_err("Invalid options %d\n", options); @@ -1375,18 +1654,44 @@ int qpnp_flash_led_prepare(struct led_trigger *trig, int options, } if (options & ENABLE_REGULATOR) { - rc = qpnp_flash_led_regulator_enable(led, snode, true); - if (rc < 0) { - pr_err("enable regulator failed, rc=%d\n", rc); - return rc; + if (pmic_subtype == PMI632_SUBTYPE) { + ret.intval = 1; + rc = power_supply_set_property(led->main_psy, + POWER_SUPPLY_PROP_FLASH_ACTIVE, + &ret); + if (rc < 0) { + pr_err("Failed to set FLASH_ACTIVE on charger rc=%d\n", + rc); + return rc; + } + pr_debug("FLASH_ACTIVE = 1\n"); + } else { + rc = qpnp_flash_led_regulator_enable(led, snode, true); + if (rc < 0) { + pr_err("enable regulator failed, rc=%d\n", rc); + return rc; + } } } if (options & DISABLE_REGULATOR) { - rc = qpnp_flash_led_regulator_enable(led, snode, false); - if (rc < 0) { - pr_err("disable regulator failed, rc=%d\n", rc); - return rc; + if (pmic_subtype == PMI632_SUBTYPE) { + ret.intval = 0; + rc = power_supply_set_property(led->main_psy, + POWER_SUPPLY_PROP_FLASH_ACTIVE, + &ret); + if (rc < 0) { + pr_err("Failed to set FLASH_ACTIVE on charger rc=%d\n", + rc); + return rc; + } + pr_debug("FLASH_ACTIVE = 0\n"); + } else { + rc = qpnp_flash_led_regulator_enable(led, snode, false); + if (rc < 0) { + pr_err("disable regulator failed, rc=%d\n", rc); + return rc; + } } } @@ -1401,6 +1706,28 @@ int qpnp_flash_led_prepare(struct led_trigger *trig, int options, return 0; } +int qpnp_flash_led_prepare(struct led_trigger *trig, int options, + int *max_current) +{ + struct led_classdev *led_cdev; + int rc; + + if (!trig) { + pr_err("Invalid led_trigger provided\n"); + return -EINVAL; + } + + led_cdev = trigger_to_lcdev(trig); + if (!led_cdev) { + pr_err("Invalid led_cdev in trigger %s\n", trig->name); + return -EINVAL; + } + + rc = qpnp_flash_led_regulator_control(led_cdev, options, max_current); + + return rc; +} + static void qpnp_flash_led_brightness_set(struct led_classdev *led_cdev, enum led_brightness value) { @@ -1440,6 +1767,29 @@ static void qpnp_flash_led_brightness_set(struct led_classdev *led_cdev, spin_unlock(&led->lock); } +static ssize_t qpnp_flash_led_prepare_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int rc, options, max_current; + u32 val; + struct led_classdev *led_cdev = dev_get_drvdata(dev); + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + if (val != 0 && val != 1) + return count; + + options = val ? ENABLE_REGULATOR : DISABLE_REGULATOR; + + rc = qpnp_flash_led_regulator_control(led_cdev, options, &max_current); + if (rc < 0) + return rc; + + return count; +} + /* sysfs show function for flash_max_current */ static ssize_t qpnp_flash_led_max_current_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -1462,6 +1812,7 @@ static ssize_t qpnp_flash_led_max_current_show(struct device *dev, /* sysfs attributes exported by flash_led */ static struct device_attribute qpnp_flash_led_attrs[] = { __ATTR(max_current, 0664, qpnp_flash_led_max_current_show, NULL), + __ATTR(enable, 0664, NULL, qpnp_flash_led_prepare_store), }; static int flash_led_psy_notifier_call(struct notifier_block *nb, @@ -1590,6 +1941,7 @@ static int qpnp_flash_led_parse_each_led_dt(struct qpnp_flash_led *led, int rc, min_ma; u32 val; bool hw_strobe = 0, edge_trigger = 0, active_high = 0; + u8 pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; fnode->pdev = led->pdev; fnode->cdev.brightness_set = qpnp_flash_led_brightness_set; @@ -1619,6 +1971,11 @@ static int qpnp_flash_led_parse_each_led_dt(struct qpnp_flash_led *led, rc = of_property_read_u32(node, "qcom,id", &val); if (!rc) { fnode->id = (u8)val; + + if (pmic_subtype == PMI632_SUBTYPE && fnode->id > LED2) { + pr_err("Flash node id = %d not supported\n", fnode->id); + return -EINVAL; + } } else { pr_err("Unable to read flash LED ID\n"); return rc; @@ -1925,6 +2282,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, struct device_node *revid_node; int rc; u32 val; + u8 pmic_subtype; bool short_circuit_det, open_circuit_det, vph_droop_det; revid_node = of_parse_phandle(node, "qcom,pmic-revid", 0); @@ -1945,6 +2303,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, return -EPROBE_DEFER; } + pmic_subtype = led->pdata->pmic_rev_id->pmic_subtype; pr_debug("PMIC subtype %d Digital major %d\n", led->pdata->pmic_rev_id->pmic_subtype, led->pdata->pmic_rev_id->rev4); @@ -2059,7 +2418,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, led->pdata->thermal_hysteresis = -EINVAL; rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val); if (!rc) { - if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) + if (pmic_subtype == PM660L_SUBTYPE) val = THERMAL_HYST_TEMP_TO_VAL(val, 20); else val = THERMAL_HYST_TEMP_TO_VAL(val, 15); @@ -2123,7 +2482,13 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, return -EINVAL; } - led->pdata->vph_droop_threshold = FLASH_LED_VPH_DROOP_THRESH_DEFAULT; + if (pmic_subtype == PMI632_SUBTYPE) + led->pdata->vph_droop_threshold = + BHARGER_FLASH_LED_VPH_DROOP_THRESH_DEFAULT; + else + led->pdata->vph_droop_threshold = + FLASH_LED_VPH_DROOP_THRESH_DEFAULT; + rc = of_property_read_u32(node, "qcom,vph-droop-threshold-mv", &val); if (!rc) { led->pdata->vph_droop_threshold = @@ -2268,7 +2633,12 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, return -EINVAL; } - led->pdata->chgr_mitigation_sel = FLASH_SW_CHARGER_MITIGATION; + if (pmic_subtype == PMI632_SUBTYPE) + led->pdata->chgr_mitigation_sel = + FLASH_DISABLE_CHARGER_MITIGATION; + else + led->pdata->chgr_mitigation_sel = FLASH_SW_CHARGER_MITIGATION; + rc = of_property_read_u32(node, "qcom,chgr-mitigation-sel", &val); if (!rc) { led->pdata->chgr_mitigation_sel = val; @@ -2296,6 +2666,14 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, return -EINVAL; } + led->pdata->bst_pwm_ovrhd_uv = FLASH_BST_PWM_OVRHD_MIN_UV; + rc = of_property_read_u32(node, "qcom,bst-pwm-ovrhd-uv", &val); + if (!rc) { + if (val >= FLASH_BST_PWM_OVRHD_MIN_UV && + val <= FLASH_BST_PWM_OVRHD_MAX_UV) + led->pdata->bst_pwm_ovrhd_uv = val; + } + led->pdata->all_ramp_up_done_irq = of_irq_get_byname(node, "all-ramp-up-done-irq"); if (led->pdata->all_ramp_up_done_irq < 0) -- GitLab From 6d1f576657cc1cc1ddb704fa33778ec84fa7272d Mon Sep 17 00:00:00 2001 From: Monika Singh Date: Fri, 25 Jan 2019 19:52:32 +0530 Subject: [PATCH 1273/1286] ARM: dts: msm: Add crypto clock support Add clock support as voting has to be done from apps to control the clocks which are needed to access HW crypto module. Change-Id: I04189cef95501a2865ebb94c73c9502237639e54 Signed-off-by: Monika Singh --- arch/arm64/boot/dts/qcom/trinket.dtsi | 41 +++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index b8095ac4b0d4..3bf03ea3fc51 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -1906,10 +1906,26 @@ qcom,qsee-ce-hw-instance = <0>; qcom,disk-encrypt-pipe-pair = <2>; qcom,support-fde; - qcom,no-clock-support; qcom,fde-key-size; qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 200000 400000>, + <55 512 300000 800000>, + <55 512 400000 1000000>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; qcom,qsee-reentrancy-support = <2>; }; @@ -1983,10 +1999,18 @@ qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 393600 393600>; + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; qcom,smmu-s1-enable; - qcom,no-clock-support; iommus = <&apps_smmu 0x01A6 0x0011>, <&apps_smmu 0x01B6 0x0011>; }; @@ -2009,6 +2033,14 @@ qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; @@ -2016,7 +2048,6 @@ qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; - qcom,no-clock-support; iommus = <&apps_smmu 0x01A4 0x0011>, <&apps_smmu 0x01B4 0x0011>; }; -- GitLab From fe533a386ba6b3d93ff09ab80618ebc376d4bc8c Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 31 Jan 2019 16:29:26 +0530 Subject: [PATCH 1274/1286] usb: phy: qmp: Do not reset phy mode in DP+USB concurrent mode QMP phy driver resets phy mode to usb in phy suspend path for cable disconnect case. When USB3 controller stops responding to stop endpoint command driver performs USB host mode recovery. During this QMP PHY set_suspend for suspend called with cable disconnected case and reset the phy mode to usb. But DP driver is not notified of this reset which results DP is doing to bad sate and causing unmapped access of registers from DP driver. Fix this issue by adding proper check to do not reset the phy mode in DP+USB concurrent mode. Change-Id: I00ec1850060c74c7c76529b4f39476e384ce1022 Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/phy/phy-msm-ssusb-qmp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/phy/phy-msm-ssusb-qmp.c b/drivers/usb/phy/phy-msm-ssusb-qmp.c index 45d926909ed8..566191ed3f85 100644 --- a/drivers/usb/phy/phy-msm-ssusb-qmp.c +++ b/drivers/usb/phy/phy-msm-ssusb-qmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -724,7 +724,9 @@ static int msm_ssphy_qmp_set_suspend(struct usb_phy *uphy, int suspend) if (phy->cable_connected) { msm_ssusb_qmp_enable_autonomous(phy, 1); } else { - if (uphy->type == USB_PHY_TYPE_USB3_AND_DP) + /* Reset phy mode to USB only if DP not connected */ + if (uphy->type == USB_PHY_TYPE_USB3_AND_DP && + !(phy->phy.flags & PHY_USB_DP_CONCURRENT_MODE)) msm_ssphy_qmp_setmode(phy, USB3_MODE); writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_POWER_DOWN_CONTROL]); -- GitLab From ef7a467d3ecd0b1003d6e9b8561af14533997315 Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Tue, 22 Jan 2019 13:27:05 +0530 Subject: [PATCH 1275/1286] Documentation: batterydata: Add avg vbat step charging support Add support to specify average battery votlage based step charging using qcom,vbat-avg-based-step-chg property. While at it, add support to define whether to change the FCC directly or in steps of pre-configured value using the property qcom,taper-fcc. Change-Id: Icdbe5dd68bc7f8e2cb89aaf91b67b8f76891ace2 Signed-off-by: Umang Agrawal --- .../devicetree/bindings/batterydata/batterydata.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/batterydata/batterydata.txt b/Documentation/devicetree/bindings/batterydata/batterydata.txt index 0cef324b40ab..8224139e7d8f 100644 --- a/Documentation/devicetree/bindings/batterydata/batterydata.txt +++ b/Documentation/devicetree/bindings/batterydata/batterydata.txt @@ -87,6 +87,11 @@ Profile data node optional properties: If yes, the low and high thresholds defined in "qcom,step-chg-ranges" tuples should be assigned as OCV values in microvolts. +- qcom,vbat-avg-based-step-chg: A bool property to indicate if the battery will + perform average VBAT (Battery Voltage) based step charging. + If yes, the low and high thresholds defined in + "qcom,step-chg-ranges" tuples should be assigned as + VBAT values in microvolts. - qcom,step-chg-ranges: Array of tuples in which a tuple describes a range data of step charging setting. A range contains following 3 integer elements: @@ -141,6 +146,9 @@ Profile data node optional properties: Element 1 - FV value for soft warm. - qcom,batt-age-level: Battery age level. This is used only when multiple profile loading is supported. +- qcom,taper-fcc: A bool property to enable gradual reduction in FCC in steps + of pre-configured value, whenever step charging + thresholds are crossed-over. Profile data node required subnodes: - qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes temperature to fcc lookup. The units for this lookup -- GitLab From 6bcc3e01d8207eaf2b449942abbde6a57b23583c Mon Sep 17 00:00:00 2001 From: Umang Agrawal Date: Tue, 22 Jan 2019 13:41:03 +0530 Subject: [PATCH 1276/1286] power: step-chg-jeita: Implement tapered down step charging Add support to gradually ramp down FCC in steps of pre-configured value for step-charging implementation in order to approximate CC1->CV1->CC2->CV2 behaviour. Change-Id: Ie7dae3a551abc0a17dcfa19c2a258dd12ce4d877 Signed-off-by: Umang Agrawal --- drivers/power/supply/qcom/step-chg-jeita.c | 114 ++++++++++++++++++++- 1 file changed, 110 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/qcom/step-chg-jeita.c b/drivers/power/supply/qcom/step-chg-jeita.c index fd85de004a1c..73b4d19f6db5 100644 --- a/drivers/power/supply/qcom/step-chg-jeita.c +++ b/drivers/power/supply/qcom/step-chg-jeita.c @@ -56,7 +56,9 @@ struct step_chg_info { bool sw_jeita_cfg_valid; bool soc_based_step_chg; bool ocv_based_step_chg; + bool vbat_avg_based_step_chg; bool batt_missing; + bool taper_fcc; int jeita_fcc_index; int jeita_fv_index; int step_index; @@ -74,6 +76,7 @@ struct step_chg_info { struct power_supply *bms_psy; struct power_supply *usb_psy; struct power_supply *main_psy; + struct power_supply *dc_psy; struct delayed_work status_change_work; struct delayed_work get_config_work; struct notifier_block nb; @@ -121,6 +124,39 @@ static bool is_usb_available(struct step_chg_info *chip) return true; } +static bool is_input_present(struct step_chg_info *chip) +{ + int rc = 0, input_present = 0; + union power_supply_propval pval = {0, }; + + if (!chip->usb_psy) + chip->usb_psy = power_supply_get_by_name("usb"); + if (chip->usb_psy) { + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + if (rc < 0) + pr_err("Couldn't read USB Present status, rc=%d\n", rc); + else + input_present |= pval.intval; + } + + if (!chip->dc_psy) + chip->dc_psy = power_supply_get_by_name("dc"); + if (chip->dc_psy) { + rc = power_supply_get_property(chip->dc_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + if (rc < 0) + pr_err("Couldn't read DC Present status, rc=%d\n", rc); + else + input_present |= pval.intval; + } + + if (input_present) + return true; + + return false; +} + int read_range_data_from_node(struct device_node *node, const char *prop_str, struct range_data *ranges, u32 max_threshold, u32 max_value) @@ -260,6 +296,8 @@ static int get_step_chg_jeita_setting_from_profile(struct step_chg_info *chip) return rc; } + chip->taper_fcc = of_property_read_bool(profile_node, "qcom,taper-fcc"); + chip->soc_based_step_chg = of_property_read_bool(profile_node, "qcom,soc-based-step-chg"); if (chip->soc_based_step_chg) { @@ -279,6 +317,17 @@ static int get_step_chg_jeita_setting_from_profile(struct step_chg_info *chip) chip->step_chg_config->param.use_bms = true; } + chip->vbat_avg_based_step_chg = + of_property_read_bool(profile_node, + "qcom,vbat-avg-based-step-chg"); + if (chip->vbat_avg_based_step_chg) { + chip->step_chg_config->param.psy_prop = + POWER_SUPPLY_PROP_VOLTAGE_AVG; + chip->step_chg_config->param.prop_name = "VBAT_AVG"; + chip->step_chg_config->param.hysteresis = 0; + chip->step_chg_config->param.use_bms = true; + } + chip->step_chg_cfg_valid = true; rc = read_range_data_from_node(profile_node, "qcom,step-chg-ranges", @@ -442,10 +491,53 @@ static int get_val(struct range_data *range, int hysteresis, int current_index, return 0; } +#define TAPERED_STEP_CHG_FCC_REDUCTION_STEP_MA 50000 /* 50 mA */ +static void taper_fcc_step_chg(struct step_chg_info *chip, int index, + int current_voltage) +{ + u32 current_fcc, target_fcc; + + if (index < 0) { + pr_err("Invalid STEP CHG index\n"); + return; + } + + current_fcc = get_effective_result(chip->fcc_votable); + target_fcc = chip->step_chg_config->fcc_cfg[index].value; + + if (index == 0) { + vote(chip->fcc_votable, STEP_CHG_VOTER, true, target_fcc); + } else if (current_voltage > + (chip->step_chg_config->fcc_cfg[index - 1].high_threshold + + chip->step_chg_config->param.hysteresis)) { + /* + * Ramp down FCC in pre-configured steps till the current index + * FCC configuration is reached, whenever the step charging + * control parameter exceeds the high threshold of previous + * step charging index configuration. + */ + vote(chip->fcc_votable, STEP_CHG_VOTER, true, max(target_fcc, + current_fcc - TAPERED_STEP_CHG_FCC_REDUCTION_STEP_MA)); + } else if ((current_fcc > + chip->step_chg_config->fcc_cfg[index - 1].value) && + (current_voltage > + chip->step_chg_config->fcc_cfg[index - 1].low_threshold + + chip->step_chg_config->param.hysteresis)) { + /* + * In case the step charging index switch to the next higher + * index without FCCs saturation for the previous index, ramp + * down FCC till previous index FCC configuration is reached. + */ + vote(chip->fcc_votable, STEP_CHG_VOTER, true, + max(chip->step_chg_config->fcc_cfg[index - 1].value, + current_fcc - TAPERED_STEP_CHG_FCC_REDUCTION_STEP_MA)); + } +} + static int handle_step_chg_config(struct step_chg_info *chip) { union power_supply_propval pval = {0, }; - int rc = 0, fcc_ua = 0; + int rc = 0, fcc_ua = 0, current_index; u64 elapsed_us; elapsed_us = ktime_us_delta(ktime_get(), chip->step_last_update_time); @@ -478,6 +570,7 @@ static int handle_step_chg_config(struct step_chg_info *chip) return rc; } + current_index = chip->step_index; rc = get_val(chip->step_chg_config->fcc_cfg, chip->step_chg_config->param.hysteresis, chip->step_index, @@ -491,15 +584,28 @@ static int handle_step_chg_config(struct step_chg_info *chip) goto update_time; } + /* Do not drop step-chg index, if input supply is present */ + if (is_input_present(chip)) { + if (chip->step_index < current_index) + chip->step_index = current_index; + } else { + chip->step_index = 0; + } + if (!chip->fcc_votable) chip->fcc_votable = find_votable("FCC"); if (!chip->fcc_votable) return -EINVAL; - vote(chip->fcc_votable, STEP_CHG_VOTER, true, fcc_ua); + if (chip->taper_fcc) + taper_fcc_step_chg(chip, chip->step_index, pval.intval); + else + vote(chip->fcc_votable, STEP_CHG_VOTER, true, fcc_ua); - pr_debug("%s = %d Step-FCC = %duA\n", - chip->step_chg_config->param.prop_name, pval.intval, fcc_ua); + pr_debug("%s = %d Step-FCC = %duA taper-fcc: %d\n", + chip->step_chg_config->param.prop_name, pval.intval, + get_client_vote(chip->fcc_votable, STEP_CHG_VOTER), + chip->taper_fcc); update_time: chip->step_last_update_time = ktime_get(); -- GitLab From 8ec085ec8c9f2068f6415152ae1dcc7d663b7ae0 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Tue, 22 Jan 2019 19:01:29 +0530 Subject: [PATCH 1277/1286] ARM: dts: msm: Add GPU_SMMU_CLK in gpu smmu clk list Add GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK in GPU SMMU clk list. Change-Id: Id542842f8161c3e7035665a0ede98723e8d9a88f Signed-off-by: Prakash Gupta --- arch/arm64/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi index 4e47fb8be2d5..5acf174d40c6 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -29,10 +29,12 @@ vdd-supply = <&gpu_cx_gdsc>; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&clock_gpucc GPU_CC_AHB_CLK>; + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", - "gpu_cc_ahb_clk"; + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; #address-cells = <1>; ranges; -- GitLab From 5ac98c4c03dde5f8af4e40537c4eedb979be1710 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 31 Jan 2019 16:56:11 +0530 Subject: [PATCH 1278/1286] regulator: qcom_pm8008: Initialize voltage selector count Initialize voltage selector count (number of selectors supported by regulator) to 1 for all the LDOs of LEICA PMIC. Change-Id: Idda52cb7b5fda8a8746e18c519600cad807f5b66 Signed-off-by: Kiran Gunda --- drivers/regulator/qcom_pm8008-regulator.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/regulator/qcom_pm8008-regulator.c b/drivers/regulator/qcom_pm8008-regulator.c index 97174a4a0723..0f9fbe2b792d 100644 --- a/drivers/regulator/qcom_pm8008-regulator.c +++ b/drivers/regulator/qcom_pm8008-regulator.c @@ -556,6 +556,7 @@ static int pm8008_register_ldo(struct pm8008_regulator *pm8008_reg, pm8008_reg->rdesc.type = REGULATOR_VOLTAGE; pm8008_reg->rdesc.ops = &pm8008_regulator_ops; pm8008_reg->rdesc.name = init_data->constraints.name; + pm8008_reg->rdesc.n_voltages = 1; pm8008_reg->rdev = devm_regulator_register(dev, &pm8008_reg->rdesc, ®_config); -- GitLab From 2698ecae2367bd717fa611b2e503b927ec46c863 Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Fri, 1 Feb 2019 16:39:22 +0530 Subject: [PATCH 1279/1286] ARM: dts: msm: Add measure support ddr clock for TRINKET Add an additional MC_CC debug base to map the mc clock period register used to calculate the frequency of the MC clock. Change-Id: Ibe3331c7265595ef98fed14760c7016bea03438a Signed-off-by: Diptanshu Jamgade --- arch/arm64/boot/dts/qcom/trinket.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/trinket.dtsi b/arch/arm64/boot/dts/qcom/trinket.dtsi index 2504302d2872..3ec11d548bbb 100644 --- a/arch/arm64/boot/dts/qcom/trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket.dtsi @@ -822,12 +822,18 @@ #clock-cells = <1>; }; + mccc_debug: syscon@447d200 { + compatible = "syscon"; + reg = <0x0447d200 0x100>; + }; + clock_debugcc: qcom,cc-debug { compatible = "qcom,debugcc-trinket"; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,dispcc = <&clock_dispcc>; qcom,gpucc = <&clock_gpucc>; + qcom,mccc = <&mccc_debug>; clock-names = "cxo"; clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; #clock-cells = <1>; -- GitLab From 7f08a782983e58e2c7badd2dd3eb41b0c8d525a6 Mon Sep 17 00:00:00 2001 From: Diptanshu Jamgade Date: Fri, 18 Jan 2019 21:49:40 +0530 Subject: [PATCH 1280/1286] clk: qcom: Add clock measure support for DDR clock for TRINKET Add measure_only_mccc_clk (memory controller clock controller) to measure DDR frequency for trinket. Change-Id: I1b9e55dcf045bf7df93c43ec51aa7bfc9df6bc2a Signed-off-by: Diptanshu Jamgade --- drivers/clk/qcom/debugcc-trinket.c | 8 + drivers/clk/qcom/gcc-trinket.c | 10 + include/dt-bindings/clock/qcom,gcc-trinket.h | 430 ++++++++++--------- 3 files changed, 234 insertions(+), 214 deletions(-) diff --git a/drivers/clk/qcom/debugcc-trinket.c b/drivers/clk/qcom/debugcc-trinket.c index 780fbb380934..90eb4e37d492 100644 --- a/drivers/clk/qcom/debugcc-trinket.c +++ b/drivers/clk/qcom/debugcc-trinket.c @@ -215,6 +215,7 @@ static const char *const debug_mux_parent_names[] = { "gpu_cc_gx_cxo_clk", "gpu_cc_gx_gfx3d_clk", "gpu_cc_sleep_clk", + "measure_only_mccc_clk", "video_cc_apb_clk", "video_cc_at_clk", "video_cc_sleep_clk", @@ -231,6 +232,7 @@ static struct clk_debug_mux gcc_debug_mux = { .debug_offset = 0x62000, .post_div_offset = 0x30000, .cbcr_offset = 0x30004, + .period_offset = 0x20, .src_sel_mask = 0x3FF, .src_sel_shift = 0, .post_div_mask = 0xF, @@ -600,6 +602,8 @@ static struct clk_debug_mux gcc_debug_mux = { 0xB, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, { "gpu_cc_sleep_clk", 0xDD, 1, GPU_CC, 0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, + { "measure_only_mccc_clk", 0x97, 1, MC_CC, + 0x97, 0x3FF, 0, 0xF, 0, 1, 0x62000, 0x30000, 0x30004 }, { "video_cc_apb_clk", 0x42, 1, VIDEO_CC, 0x8, 0x3F, 0, 0x7, 0, 5, 0xA4C, 0xA30, 0xA38 }, { "video_cc_at_clk", 0x42, 1, VIDEO_CC, @@ -687,6 +691,10 @@ static int clk_debug_trinket_probe(struct platform_device *pdev) if (ret) return ret; + ret = map_debug_bases(pdev, "qcom,mccc", MC_CC); + if (ret) + return ret; + clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); if (IS_ERR(clk)) { dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); diff --git a/drivers/clk/qcom/gcc-trinket.c b/drivers/clk/qcom/gcc-trinket.c index f5118b4b3f87..f23b523c5d25 100644 --- a/drivers/clk/qcom/gcc-trinket.c +++ b/drivers/clk/qcom/gcc-trinket.c @@ -4184,12 +4184,22 @@ static struct clk_branch gcc_wcss_vs_clk = { }, }; +/* Measure-only clock for ddrss_gcc_debug_clk. */ +static struct clk_dummy measure_only_mccc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_mccc_clk", + .ops = &clk_dummy_ops, + }, +}; + struct clk_hw *gcc_trinket_hws[] = { [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw, [GPLL0_OUT_MAIN] = &gpll0_out_main.hw, [GPLL6_OUT_MAIN] = &gpll6_out_main.hw, [GPLL8_OUT_MAIN] = &gpll8_out_main.hw, [GPLL9_OUT_MAIN] = &gpll9_out_main.hw, + [MEASURE_ONLY_MMCC_CLK] = &measure_only_mccc_clk.hw, }; static struct clk_regmap *gcc_trinket_clocks[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-trinket.h b/include/dt-bindings/clock/qcom,gcc-trinket.h index 5e5d53427c0c..4bdd4d702484 100644 --- a/include/dt-bindings/clock/qcom,gcc-trinket.h +++ b/include/dt-bindings/clock/qcom,gcc-trinket.h @@ -14,220 +14,222 @@ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H #define _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H -#define GPLL0_OUT_EARLY 0 -#define GPLL0_OUT_AUX2 1 -#define GPLL0_OUT_MAIN 2 -#define GPLL3_OUT_EARLY 3 -#define GPLL4_OUT_MAIN 4 -#define GPLL5_OUT_MAIN 5 -#define GPLL6_OUT_EARLY 6 -#define GPLL6_OUT_MAIN 7 -#define GPLL7_OUT_MAIN 8 -#define GPLL8_OUT_EARLY 9 -#define GPLL8_OUT_MAIN 10 -#define GPLL9_OUT_EARLY 11 -#define GPLL9_OUT_MAIN 12 -#define GCC_AHB2PHY_CSI_CLK 13 -#define GCC_AHB2PHY_USB_CLK 14 -#define GCC_APC_VS_CLK 15 -#define GCC_BOOT_ROM_AHB_CLK 16 -#define GCC_CAMERA_AHB_CLK 17 -#define GCC_CAMERA_XO_CLK 18 -#define GCC_CAMSS_AHB_CLK_SRC 19 -#define GCC_CAMSS_CCI_AHB_CLK 20 -#define GCC_CAMSS_CCI_CLK 21 -#define GCC_CAMSS_CCI_CLK_SRC 22 -#define GCC_CAMSS_CPHY_CSID0_CLK 23 -#define GCC_CAMSS_CPHY_CSID1_CLK 24 -#define GCC_CAMSS_CPHY_CSID2_CLK 25 -#define GCC_CAMSS_CPHY_CSID3_CLK 26 -#define GCC_CAMSS_CPP_AHB_CLK 27 -#define GCC_CAMSS_CPP_AXI_CLK 28 -#define GCC_CAMSS_CPP_CLK 29 -#define GCC_CAMSS_CPP_CLK_SRC 30 -#define GCC_CAMSS_CPP_VBIF_AHB_CLK 31 -#define GCC_CAMSS_CSI0_AHB_CLK 32 -#define GCC_CAMSS_CSI0_CLK 33 -#define GCC_CAMSS_CSI0_CLK_SRC 34 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 35 -#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 36 -#define GCC_CAMSS_CSI0PIX_CLK 37 -#define GCC_CAMSS_CSI0RDI_CLK 38 -#define GCC_CAMSS_CSI1_AHB_CLK 39 -#define GCC_CAMSS_CSI1_CLK 40 -#define GCC_CAMSS_CSI1_CLK_SRC 41 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 42 -#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 43 -#define GCC_CAMSS_CSI1PIX_CLK 44 -#define GCC_CAMSS_CSI1RDI_CLK 45 -#define GCC_CAMSS_CSI2_AHB_CLK 46 -#define GCC_CAMSS_CSI2_CLK 47 -#define GCC_CAMSS_CSI2_CLK_SRC 48 -#define GCC_CAMSS_CSI2PHYTIMER_CLK 49 -#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 50 -#define GCC_CAMSS_CSI2PIX_CLK 51 -#define GCC_CAMSS_CSI2RDI_CLK 52 -#define GCC_CAMSS_CSI3_AHB_CLK 53 -#define GCC_CAMSS_CSI3_CLK 54 -#define GCC_CAMSS_CSI3_CLK_SRC 55 -#define GCC_CAMSS_CSI3PIX_CLK 56 -#define GCC_CAMSS_CSI3RDI_CLK 57 -#define GCC_CAMSS_CSI_VFE0_CLK 58 -#define GCC_CAMSS_CSI_VFE1_CLK 59 -#define GCC_CAMSS_CSIPHY0_CLK 60 -#define GCC_CAMSS_CSIPHY1_CLK 61 -#define GCC_CAMSS_CSIPHY2_CLK 62 -#define GCC_CAMSS_CSIPHY3_CLK 63 -#define GCC_CAMSS_CSIPHY_CLK_SRC 64 -#define GCC_CAMSS_GP0_CLK 65 -#define GCC_CAMSS_GP0_CLK_SRC 66 -#define GCC_CAMSS_GP1_CLK 67 -#define GCC_CAMSS_GP1_CLK_SRC 68 -#define GCC_CAMSS_ISPIF_AHB_CLK 69 -#define GCC_CAMSS_JPEG_AHB_CLK 70 -#define GCC_CAMSS_JPEG_AXI_CLK 71 -#define GCC_CAMSS_JPEG_CLK 72 -#define GCC_CAMSS_JPEG_CLK_SRC 73 -#define GCC_CAMSS_MCLK0_CLK 74 -#define GCC_CAMSS_MCLK0_CLK_SRC 75 -#define GCC_CAMSS_MCLK1_CLK 76 -#define GCC_CAMSS_MCLK1_CLK_SRC 77 -#define GCC_CAMSS_MCLK2_CLK 78 -#define GCC_CAMSS_MCLK2_CLK_SRC 79 -#define GCC_CAMSS_MCLK3_CLK 80 -#define GCC_CAMSS_MCLK3_CLK_SRC 81 -#define GCC_CAMSS_MICRO_AHB_CLK 82 -#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83 -#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84 -#define GCC_CAMSS_TOP_AHB_CLK 85 -#define GCC_CAMSS_VFE0_AHB_CLK 86 -#define GCC_CAMSS_VFE0_CLK 87 -#define GCC_CAMSS_VFE0_CLK_SRC 88 -#define GCC_CAMSS_VFE0_STREAM_CLK 89 -#define GCC_CAMSS_VFE1_AHB_CLK 90 -#define GCC_CAMSS_VFE1_CLK 91 -#define GCC_CAMSS_VFE1_CLK_SRC 92 -#define GCC_CAMSS_VFE1_STREAM_CLK 93 -#define GCC_CAMSS_VFE_TSCTR_CLK 94 -#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95 -#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96 -#define GCC_CE1_AHB_CLK 97 -#define GCC_CE1_AXI_CLK 98 -#define GCC_CE1_CLK 99 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100 -#define GCC_CPUSS_AHB_CLK 101 -#define GCC_CPUSS_AHB_CLK_SRC 102 -#define GCC_CPUSS_GNOC_CLK 103 -#define GCC_CPUSS_THROTTLE_CORE_CLK 104 -#define GCC_CPUSS_THROTTLE_XO_CLK 105 -#define GCC_DISP_AHB_CLK 106 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 107 -#define GCC_DISP_HF_AXI_CLK 108 -#define GCC_DISP_THROTTLE_CORE_CLK 109 -#define GCC_DISP_XO_CLK 110 -#define GCC_GP1_CLK 111 -#define GCC_GP1_CLK_SRC 112 -#define GCC_GP2_CLK 113 -#define GCC_GP2_CLK_SRC 114 -#define GCC_GP3_CLK 115 -#define GCC_GP3_CLK_SRC 116 -#define GCC_GPU_CFG_AHB_CLK 117 -#define GCC_GPU_GPLL0_CLK_SRC 118 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 119 -#define GCC_GPU_MEMNOC_GFX_CLK 120 -#define GCC_GPU_SNOC_DVM_GFX_CLK 121 -#define GCC_GPU_THROTTLE_CORE_CLK 122 -#define GCC_GPU_THROTTLE_XO_CLK 123 -#define GCC_MSS_VS_CLK 124 -#define GCC_PDM2_CLK 125 -#define GCC_PDM2_CLK_SRC 126 -#define GCC_PDM_AHB_CLK 127 -#define GCC_PDM_XO4_CLK 128 -#define GCC_PRNG_AHB_CLK 129 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 130 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 131 -#define GCC_QMIP_CPUSS_CFG_AHB_CLK 132 -#define GCC_QMIP_DISP_AHB_CLK 133 -#define GCC_QMIP_GPU_CFG_AHB_CLK 134 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 135 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 136 -#define GCC_QUPV3_WRAP0_CORE_CLK 137 -#define GCC_QUPV3_WRAP0_S0_CLK 138 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 139 -#define GCC_QUPV3_WRAP0_S1_CLK 140 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 141 -#define GCC_QUPV3_WRAP0_S2_CLK 142 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 143 -#define GCC_QUPV3_WRAP0_S3_CLK 144 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 145 -#define GCC_QUPV3_WRAP0_S4_CLK 146 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 147 -#define GCC_QUPV3_WRAP0_S5_CLK 148 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 149 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 150 -#define GCC_QUPV3_WRAP1_CORE_CLK 151 -#define GCC_QUPV3_WRAP1_S0_CLK 152 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 153 -#define GCC_QUPV3_WRAP1_S1_CLK 154 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 155 -#define GCC_QUPV3_WRAP1_S2_CLK 156 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 157 -#define GCC_QUPV3_WRAP1_S3_CLK 158 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 159 -#define GCC_QUPV3_WRAP1_S4_CLK 160 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 161 -#define GCC_QUPV3_WRAP1_S5_CLK 162 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 163 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 164 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 165 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 166 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 167 -#define GCC_SDCC1_AHB_CLK 168 -#define GCC_SDCC1_APPS_CLK 169 -#define GCC_SDCC1_APPS_CLK_SRC 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 172 -#define GCC_SDCC2_AHB_CLK 173 -#define GCC_SDCC2_APPS_CLK 174 -#define GCC_SDCC2_APPS_CLK_SRC 175 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 176 -#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 177 -#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 178 -#define GCC_UFS_PHY_AHB_CLK 179 -#define GCC_UFS_PHY_AXI_CLK 180 -#define GCC_UFS_PHY_AXI_CLK_SRC 181 -#define GCC_UFS_PHY_ICE_CORE_CLK 182 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 183 -#define GCC_UFS_PHY_PHY_AUX_CLK 184 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 185 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 186 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 187 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 188 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 189 -#define GCC_USB30_PRIM_MASTER_CLK 190 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 191 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 192 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 193 -#define GCC_USB30_PRIM_SLEEP_CLK 194 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 197 -#define GCC_VDDA_VS_CLK 198 -#define GCC_VDDCX_VS_CLK 199 -#define GCC_VDDMX_VS_CLK 200 -#define GCC_VIDEO_AHB_CLK 201 -#define GCC_VIDEO_AXI0_CLK 202 -#define GCC_VIDEO_THROTTLE_CORE_CLK 203 -#define GCC_VIDEO_XO_CLK 204 -#define GCC_VS_CTRL_AHB_CLK 205 -#define GCC_VS_CTRL_CLK 206 -#define GCC_VS_CTRL_CLK_SRC 207 -#define GCC_VSENSOR_CLK_SRC 208 -#define GCC_WCSS_VS_CLK 209 -#define GCC_USB3_PRIM_CLKREF_CLK 210 -#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 211 -#define GCC_BIMC_GPU_AXI_CLK 212 -#define GCC_UFS_MEM_CLKREF_CLK 213 +#define GPLL0_OUT_AUX2 0 +#define GPLL0_OUT_MAIN 1 +#define GPLL6_OUT_MAIN 2 +#define GPLL8_OUT_MAIN 3 +#define GPLL9_OUT_MAIN 4 +#define MEASURE_ONLY_MMCC_CLK 5 +#define GPLL0_OUT_EARLY 6 +#define GPLL3_OUT_EARLY 7 +#define GPLL4_OUT_MAIN 8 +#define GPLL5_OUT_MAIN 9 +#define GPLL6_OUT_EARLY 10 +#define GPLL7_OUT_MAIN 11 +#define GPLL8_OUT_EARLY 12 +#define GPLL9_OUT_EARLY 13 +#define GCC_AHB2PHY_CSI_CLK 14 +#define GCC_AHB2PHY_USB_CLK 15 +#define GCC_APC_VS_CLK 16 +#define GCC_BOOT_ROM_AHB_CLK 17 +#define GCC_CAMERA_AHB_CLK 18 +#define GCC_CAMERA_XO_CLK 19 +#define GCC_CAMSS_AHB_CLK_SRC 20 +#define GCC_CAMSS_CCI_AHB_CLK 21 +#define GCC_CAMSS_CCI_CLK 22 +#define GCC_CAMSS_CCI_CLK_SRC 23 +#define GCC_CAMSS_CPHY_CSID0_CLK 24 +#define GCC_CAMSS_CPHY_CSID1_CLK 25 +#define GCC_CAMSS_CPHY_CSID2_CLK 26 +#define GCC_CAMSS_CPHY_CSID3_CLK 27 +#define GCC_CAMSS_CPP_AHB_CLK 28 +#define GCC_CAMSS_CPP_AXI_CLK 29 +#define GCC_CAMSS_CPP_CLK 30 +#define GCC_CAMSS_CPP_CLK_SRC 31 +#define GCC_CAMSS_CPP_VBIF_AHB_CLK 32 +#define GCC_CAMSS_CSI0_AHB_CLK 33 +#define GCC_CAMSS_CSI0_CLK 34 +#define GCC_CAMSS_CSI0_CLK_SRC 35 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 36 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37 +#define GCC_CAMSS_CSI0PIX_CLK 38 +#define GCC_CAMSS_CSI0RDI_CLK 39 +#define GCC_CAMSS_CSI1_AHB_CLK 40 +#define GCC_CAMSS_CSI1_CLK 41 +#define GCC_CAMSS_CSI1_CLK_SRC 42 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 43 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44 +#define GCC_CAMSS_CSI1PIX_CLK 45 +#define GCC_CAMSS_CSI1RDI_CLK 46 +#define GCC_CAMSS_CSI2_AHB_CLK 47 +#define GCC_CAMSS_CSI2_CLK 48 +#define GCC_CAMSS_CSI2_CLK_SRC 49 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 50 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51 +#define GCC_CAMSS_CSI2PIX_CLK 52 +#define GCC_CAMSS_CSI2RDI_CLK 53 +#define GCC_CAMSS_CSI3_AHB_CLK 54 +#define GCC_CAMSS_CSI3_CLK 55 +#define GCC_CAMSS_CSI3_CLK_SRC 56 +#define GCC_CAMSS_CSI3PIX_CLK 57 +#define GCC_CAMSS_CSI3RDI_CLK 58 +#define GCC_CAMSS_CSI_VFE0_CLK 59 +#define GCC_CAMSS_CSI_VFE1_CLK 60 +#define GCC_CAMSS_CSIPHY0_CLK 61 +#define GCC_CAMSS_CSIPHY1_CLK 62 +#define GCC_CAMSS_CSIPHY2_CLK 63 +#define GCC_CAMSS_CSIPHY3_CLK 64 +#define GCC_CAMSS_CSIPHY_CLK_SRC 65 +#define GCC_CAMSS_GP0_CLK 66 +#define GCC_CAMSS_GP0_CLK_SRC 67 +#define GCC_CAMSS_GP1_CLK 68 +#define GCC_CAMSS_GP1_CLK_SRC 69 +#define GCC_CAMSS_ISPIF_AHB_CLK 70 +#define GCC_CAMSS_JPEG_AHB_CLK 71 +#define GCC_CAMSS_JPEG_AXI_CLK 72 +#define GCC_CAMSS_JPEG_CLK 73 +#define GCC_CAMSS_JPEG_CLK_SRC 74 +#define GCC_CAMSS_MCLK0_CLK 75 +#define GCC_CAMSS_MCLK0_CLK_SRC 76 +#define GCC_CAMSS_MCLK1_CLK 77 +#define GCC_CAMSS_MCLK1_CLK_SRC 78 +#define GCC_CAMSS_MCLK2_CLK 79 +#define GCC_CAMSS_MCLK2_CLK_SRC 80 +#define GCC_CAMSS_MCLK3_CLK 81 +#define GCC_CAMSS_MCLK3_CLK_SRC 82 +#define GCC_CAMSS_MICRO_AHB_CLK 83 +#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 84 +#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 85 +#define GCC_CAMSS_TOP_AHB_CLK 86 +#define GCC_CAMSS_VFE0_AHB_CLK 87 +#define GCC_CAMSS_VFE0_CLK 88 +#define GCC_CAMSS_VFE0_CLK_SRC 89 +#define GCC_CAMSS_VFE0_STREAM_CLK 90 +#define GCC_CAMSS_VFE1_AHB_CLK 91 +#define GCC_CAMSS_VFE1_CLK 92 +#define GCC_CAMSS_VFE1_CLK_SRC 93 +#define GCC_CAMSS_VFE1_STREAM_CLK 94 +#define GCC_CAMSS_VFE_TSCTR_CLK 95 +#define GCC_CAMSS_VFE_VBIF_AHB_CLK 96 +#define GCC_CAMSS_VFE_VBIF_AXI_CLK 97 +#define GCC_CE1_AHB_CLK 98 +#define GCC_CE1_AXI_CLK 99 +#define GCC_CE1_CLK 100 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 101 +#define GCC_CPUSS_AHB_CLK 102 +#define GCC_CPUSS_AHB_CLK_SRC 103 +#define GCC_CPUSS_GNOC_CLK 104 +#define GCC_CPUSS_THROTTLE_CORE_CLK 105 +#define GCC_CPUSS_THROTTLE_XO_CLK 106 +#define GCC_DISP_AHB_CLK 107 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 108 +#define GCC_DISP_HF_AXI_CLK 109 +#define GCC_DISP_THROTTLE_CORE_CLK 110 +#define GCC_DISP_XO_CLK 111 +#define GCC_GP1_CLK 112 +#define GCC_GP1_CLK_SRC 113 +#define GCC_GP2_CLK 114 +#define GCC_GP2_CLK_SRC 115 +#define GCC_GP3_CLK 116 +#define GCC_GP3_CLK_SRC 117 +#define GCC_GPU_CFG_AHB_CLK 118 +#define GCC_GPU_GPLL0_CLK_SRC 119 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 120 +#define GCC_GPU_MEMNOC_GFX_CLK 121 +#define GCC_GPU_SNOC_DVM_GFX_CLK 122 +#define GCC_GPU_THROTTLE_CORE_CLK 123 +#define GCC_GPU_THROTTLE_XO_CLK 124 +#define GCC_MSS_VS_CLK 125 +#define GCC_PDM2_CLK 126 +#define GCC_PDM2_CLK_SRC 127 +#define GCC_PDM_AHB_CLK 128 +#define GCC_PDM_XO4_CLK 129 +#define GCC_PRNG_AHB_CLK 130 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 131 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 132 +#define GCC_QMIP_CPUSS_CFG_AHB_CLK 133 +#define GCC_QMIP_DISP_AHB_CLK 134 +#define GCC_QMIP_GPU_CFG_AHB_CLK 135 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 136 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 137 +#define GCC_QUPV3_WRAP0_CORE_CLK 138 +#define GCC_QUPV3_WRAP0_S0_CLK 139 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 140 +#define GCC_QUPV3_WRAP0_S1_CLK 141 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 142 +#define GCC_QUPV3_WRAP0_S2_CLK 143 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 144 +#define GCC_QUPV3_WRAP0_S3_CLK 145 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 146 +#define GCC_QUPV3_WRAP0_S4_CLK 147 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 148 +#define GCC_QUPV3_WRAP0_S5_CLK 149 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 150 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 151 +#define GCC_QUPV3_WRAP1_CORE_CLK 152 +#define GCC_QUPV3_WRAP1_S0_CLK 153 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 154 +#define GCC_QUPV3_WRAP1_S1_CLK 155 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 156 +#define GCC_QUPV3_WRAP1_S2_CLK 157 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 158 +#define GCC_QUPV3_WRAP1_S3_CLK 159 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 160 +#define GCC_QUPV3_WRAP1_S4_CLK 161 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 162 +#define GCC_QUPV3_WRAP1_S5_CLK 163 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 164 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 165 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 166 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 167 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 168 +#define GCC_SDCC1_AHB_CLK 169 +#define GCC_SDCC1_APPS_CLK 170 +#define GCC_SDCC1_APPS_CLK_SRC 171 +#define GCC_SDCC1_ICE_CORE_CLK 172 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 +#define GCC_SDCC2_AHB_CLK 174 +#define GCC_SDCC2_APPS_CLK 175 +#define GCC_SDCC2_APPS_CLK_SRC 176 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 177 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 178 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 179 +#define GCC_UFS_PHY_AHB_CLK 180 +#define GCC_UFS_PHY_AXI_CLK 181 +#define GCC_UFS_PHY_AXI_CLK_SRC 182 +#define GCC_UFS_PHY_ICE_CORE_CLK 183 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 184 +#define GCC_UFS_PHY_PHY_AUX_CLK 185 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 186 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 187 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 188 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 189 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 190 +#define GCC_USB30_PRIM_MASTER_CLK 191 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 192 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 193 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 194 +#define GCC_USB30_PRIM_SLEEP_CLK 195 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 196 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 197 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 198 +#define GCC_VDDA_VS_CLK 199 +#define GCC_VDDCX_VS_CLK 200 +#define GCC_VDDMX_VS_CLK 201 +#define GCC_VIDEO_AHB_CLK 202 +#define GCC_VIDEO_AXI0_CLK 203 +#define GCC_VIDEO_THROTTLE_CORE_CLK 204 +#define GCC_VIDEO_XO_CLK 205 +#define GCC_VS_CTRL_AHB_CLK 206 +#define GCC_VS_CTRL_CLK 207 +#define GCC_VS_CTRL_CLK_SRC 208 +#define GCC_VSENSOR_CLK_SRC 209 +#define GCC_WCSS_VS_CLK 210 +#define GCC_USB3_PRIM_CLKREF_CLK 211 +#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 212 +#define GCC_BIMC_GPU_AXI_CLK 213 +#define GCC_UFS_MEM_CLKREF_CLK 214 + /* GCC Resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 -- GitLab From 1684420ec1e76cc0527ff8bebdcc25153ef0ebc0 Mon Sep 17 00:00:00 2001 From: Samyukta Mogily Date: Fri, 1 Feb 2019 13:32:02 +0530 Subject: [PATCH 1281/1286] ARM: dts: msm: Change dvdd for rear camera for trinket idp Changing the dvdd as per the values supported by pmic. Change-Id: Id217e23b2df385c63bd78b78745a78f620f11f94 Signed-off-by: Samyukta Mogily --- arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi index 2772c907b3f5..430397e0ff74 100644 --- a/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi @@ -45,8 +45,8 @@ cam_vaf-supply = <&L5P>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", "cam_clk", "cam_vaf"; - qcom,cam-vreg-min-voltage = <1800000 2800000 1100000 0 2800000>; - qcom,cam-vreg-max-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -123,8 +123,8 @@ cam_vaf-supply = <&L5P>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", "cam_clk", "cam_vaf"; - qcom,cam-vreg-min-voltage = <1800000 2800000 1100000 0 2800000>; - qcom,cam-vreg-max-voltage = <1800000 2800000 1100000 0 2800000>; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; -- GitLab From 9efacb0615f451d88ffad5656328f08a9815aa61 Mon Sep 17 00:00:00 2001 From: Tharun Raj Soma Date: Fri, 1 Feb 2019 18:41:36 +0530 Subject: [PATCH 1282/1286] ARM: dts: msm: fix minimum voltage vote for MX to power phy for TRINKET Fix minimum voltage vote for MX to power phy for TRINKET. Change-Id: I38ac22e8ea2e7abe4ca31e6ad776863f37398eac Signed-off-by: Tharun Raj Soma --- arch/arm64/boot/dts/qcom/trinket-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi index 103955b11c9c..1f4163e65656 100644 --- a/arch/arm64/boot/dts/qcom/trinket-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-sde.dtsi @@ -388,7 +388,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = - ; + ; qcom,supply-max-voltage = ; qcom,supply-enable-load = <0>; -- GitLab From 952ff69a89bd9b298a9cf481b081fc95f1eac8d0 Mon Sep 17 00:00:00 2001 From: Michael Adisumarta Date: Thu, 10 Jan 2019 12:26:29 -0800 Subject: [PATCH 1283/1286] ARM: dts: msm: Add emac hw changes in sdxprairie Add emac hw node, regulators and pins. Change-Id: I51c7f49e69b8385bd34f888b595f6d69e9df386b Acked-by: Rahul Kawadgave Acked-by: Sunil Paidimarri Signed-off-by: Michael Adisumarta --- .../boot/dts/qcom/sdxprairie-pinctrl.dtsi | 28 +++++++++ .../boot/dts/qcom/sdxprairie-regulator.dtsi | 20 ++++++ arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 63 +++++++++++++++++++ 3 files changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index 1974af190601..60bdb5aec4c6 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -1434,5 +1434,33 @@ bias-disable; }; }; + + emac { + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio106"; + function = "emac_PPS0"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + emac_pin_pps_1: emac_pin_pps_1 { + mux { + pins = "gpio95"; + function = "emac_PPS1"; + }; + + config { + pins = "gpio95"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi index db5c96cb5716..2aafd0075e73 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -473,4 +473,24 @@ regulator-max-microvolt = <2950000>; parent-supply = <&vreg_vddpx_2>; }; + + vreg_emac_phy: emac_phy_regulator { + compatible = "regulator-fixed"; + regulator-name = "emac_phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <100>; + gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_rgmii_io_pads: rgmii_io_pads_regulator { + compatible = "regulator-fixed"; + regulator-name = "rgmii_io_pads"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <100>; + gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 328e038d36bc..dc4cd33c16be 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -1163,6 +1163,69 @@ status = "disabled"; }; + + emac_hw: qcom,emac@00020000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3900000 0x300000>; + reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; + interrupts-extended = <&pdc 0 62 4>, <&pdc 0 60 4>, + <&tlmm 90 2>, <&pdc 0 49 4>, + <&pdc 0 50 4>, <&pdc 0 51 4>, + <&pdc 0 52 4>, <&pdc 0 53 4>, + <&pdc 0 54 4>, <&pdc 0 55 4>, + <&pdc 0 56 4>, <&pdc 0 57 4>, + <&pdc 0 290 1>, <&pdc 0 291 1>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0", "ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_ETH_AXI_CLK>, + <&clock_gcc GCC_ETH_PTP_CLK>, + <&clock_gcc GCC_ETH_RGMII_CLK>, + <&clock_gcc GCC_ETH_SLAVE_AHB_CLK>; + clock-names = "eth_axi_clk", + "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-intr-redirect = <&tlmm 90 GPIO_ACTIVE_LOW>; + qcom,phy-reset = <&tlmm 91 GPIO_ACTIVE_LOW>; + qcom,emac-pps0-test-intr = <&tlmm 31 GPIO_ACTIVE_LOW>; + vreg_rgmii-supply = <&pmxprairie_vref_rgmii>; + vreg_emac_phy-supply = <&vreg_emac_phy>; + vreg_rgmii_io_pads-supply = <&vreg_rgmii_io_pads>; + gdsc_emac-supply = <&gdsc_emac>; + mboxes = <&qmp_aop 0>; + mbox-names = "emac_aop"; + pinctrl-names = "dev-emac_pin_pps_0", + "dev-emac_pin_pps_1"; + pinctrl-0 = <&emac_pin_pps_0>; + pinctrl-1 = <&emac_pin_pps_1>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1c0 0xf>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; }; #include "sdxprairie-pm.dtsi" -- GitLab From 2fa6098bbc1b6b34078fb0ceb888b0514be933f0 Mon Sep 17 00:00:00 2001 From: Tharun Kumar Merugu Date: Sat, 2 Feb 2019 01:22:47 +0530 Subject: [PATCH 1284/1286] msm: adsprpc: restrict user apps from sending kernel RPC messages Verify that user applications are not using the kernel RPC message handle to restrict them from directly attaching to guest OS on the remote subsystem. Change-Id: Icfa114a12f2bebbe815eb9930027fded51f717fd Acked-by: Thyagarajan Venkatanarayanan Signed-off-by: Tharun Kumar Merugu --- drivers/char/adsprpc.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 702e324350c2..8fcb78ece1c6 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -99,6 +99,7 @@ #define PERF_KEYS \ "count:flush:map:copy:rpmsg:getargs:putargs:invalidate:invoke:tid:ptr" +#define FASTRPC_STATIC_HANDLE_KERNEL (1) #define FASTRPC_STATIC_HANDLE_LISTENER (3) #define FASTRPC_STATIC_HANDLE_MAX (20) #define FASTRPC_LATENCY_CTRL_ENB (1) @@ -1854,6 +1855,14 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, if (fl->profile) getnstimeofday(&invoket); + if (!kernel) { + VERIFY(err, invoke->handle != FASTRPC_STATIC_HANDLE_KERNEL); + if (err) { + pr_err("adsprpc: ERROR: %s: user application %s trying to send a kernel RPC message to channel %d", + __func__, current->comm, cid); + goto bail; + } + } VERIFY(err, fl->sctx != NULL); if (err) @@ -1993,7 +2002,7 @@ static int fastrpc_init_process(struct fastrpc_file *fl, ra[0].buf.pv = (void *)&tgid; ra[0].buf.len = sizeof(tgid); - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; ioctl.inv.sc = REMOTE_SCALARS_MAKE(0, 1, 0); ioctl.inv.pra = ra; ioctl.fds = NULL; @@ -2090,7 +2099,7 @@ static int fastrpc_init_process(struct fastrpc_file *fl, ra[5].buf.len = sizeof(inbuf.siglen); fds[5] = 0; - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; ioctl.inv.sc = REMOTE_SCALARS_MAKE(6, 4, 0); if (uproc->attrs) ioctl.inv.sc = REMOTE_SCALARS_MAKE(7, 6, 0); @@ -2179,7 +2188,7 @@ static int fastrpc_init_process(struct fastrpc_file *fl, ra[2].buf.pv = (void *)pages; ra[2].buf.len = sizeof(*pages); fds[2] = 0; - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; ioctl.inv.sc = REMOTE_SCALARS_MAKE(8, 3, 0); ioctl.inv.pra = ra; @@ -2240,7 +2249,7 @@ static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl) tgid = fl->tgid; ra[0].buf.pv = (void *)&tgid; ra[0].buf.len = sizeof(tgid); - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; ioctl.inv.sc = REMOTE_SCALARS_MAKE(1, 1, 0); ioctl.inv.pra = ra; ioctl.fds = NULL; @@ -2289,7 +2298,7 @@ static int fastrpc_mmap_on_dsp(struct fastrpc_file *fl, uint32_t flags, ra[2].buf.pv = (void *)&routargs; ra[2].buf.len = sizeof(routargs); - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; if (fl->apps->compat) ioctl.inv.sc = REMOTE_SCALARS_MAKE(4, 2, 1); else @@ -2352,7 +2361,7 @@ static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, uint64_t phys, ra[1].buf.pv = (void *)&routargs; ra[1].buf.len = sizeof(routargs); - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; ioctl.inv.sc = REMOTE_SCALARS_MAKE(9, 1, 1); ioctl.inv.pra = ra; ioctl.fds = NULL; @@ -2404,7 +2413,7 @@ static int fastrpc_munmap_on_dsp(struct fastrpc_file *fl, uintptr_t raddr, ra[0].buf.pv = (void *)&inargs; ra[0].buf.len = sizeof(inargs); - ioctl.inv.handle = 1; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; if (fl->apps->compat) ioctl.inv.sc = REMOTE_SCALARS_MAKE(5, 1, 0); else -- GitLab From faf30255372e021416cdb3c6a77cb7a9382418ed Mon Sep 17 00:00:00 2001 From: David Dai Date: Fri, 1 Feb 2019 13:34:10 -0800 Subject: [PATCH 1285/1286] ARM: dts: msm: remove IPA keepalive voter for sdxprairie This keepalive voter was added as a workaround to maintain a persistent IPA vote while APPS is awake in order to prevent an SMMU issue whereby the TCU may hang due to an unresponding TBU under the IPA clock domain, let's remove this workaround now that we're able to keep the IPA clock on due to other means. Change-Id: I841dea979e1d6676a9d6554c2c749f6ccf08eaa8 Signed-off-by: David Dai --- arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index 9b76b40de941..28923cd2e252 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -274,15 +274,6 @@ operating-points-v2 = <&keepalive_opp_table>; }; - ipa_keepalive: qcom,ipa_keepalive { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <143 777>; - qcom,active-only; - status = "ok"; - operating-points-v2 = <&keepalive_opp_table>; - }; - clock_rpmh: qcom,rpmh { compatible = "qcom,rpmh-clk-sdxprairie"; mboxes = <&apps_rsc 0>; -- GitLab From ab20cd5e062682e814b72e53a9ed325f46779240 Mon Sep 17 00:00:00 2001 From: Srikanth Uyyala Date: Mon, 24 Dec 2018 16:15:00 +0530 Subject: [PATCH 1286/1286] msm-camera: add cx-ipeak support for vfe Add support in vfe driver to vote for cx_ipeak when moving to turbo clock and unvote when moving out of turbo. Change-Id: I6b95594adbf05c0797c2748981a6b06f042adc20 Signed-off-by: Srikanth Uyyala --- drivers/media/platform/msm/camera_v2/isp/msm_isp.c | 6 ++++++ drivers/media/platform/msm/camera_v2/isp/msm_isp.h | 1 + drivers/media/platform/msm/camera_v2/isp/msm_isp47.c | 9 +++++++-- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c index dba4b7e38977..0d0fcfe37961 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c @@ -35,6 +35,7 @@ #include "msm_isp44.h" #include "msm_isp40.h" #include "msm_isp32.h" +#include "msm_cam_cx_ipeak.h" static struct msm_sd_req_vb2_q vfe_vb2_ops; static struct msm_isp_buf_mgr vfe_buf_mgr; @@ -654,6 +655,11 @@ int vfe_hw_probe(struct platform_device *pdev) "qcom,vfe-cx-ipeak", NULL)) { vfe_dev->vfe_cx_ipeak = cx_ipeak_register( pdev->dev.of_node, "qcom,vfe-cx-ipeak"); + if (vfe_dev->vfe_cx_ipeak) + cam_cx_ipeak_register_cx_ipeak( + vfe_dev->vfe_cx_ipeak, &vfe_dev->cx_ipeak_bit); + pr_debug("%s: register cx_ipeak received bit %d\n", + __func__, vfe_dev->cx_ipeak_bit); } } else { vfe_dev->hw_info = (struct msm_vfe_hardware_info *) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h index c5038a23e90b..d044d2b84b47 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h @@ -805,6 +805,7 @@ struct vfe_device { enum cam_ahb_clk_vote ahb_vote; enum cam_ahb_clk_vote user_requested_ahb_vote; struct cx_ipeak_client *vfe_cx_ipeak; + int cx_ipeak_bit; /* Sync variables*/ struct completion reset_complete; diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c index 2488b87c286e..f8f43e881914 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c @@ -26,6 +26,7 @@ #include "cam_soc_api.h" #include "msm_isp48.h" #include "linux/iopoll.h" +#include "msm_cam_cx_ipeak.h" #undef CDBG #define CDBG(fmt, args...) pr_debug(fmt, ##args) @@ -2715,7 +2716,9 @@ int msm_vfe47_set_clk_rate(struct vfe_device *vfe_dev, long *rate) prev_clk_rate < vfe_dev->vfe_clk_rates[MSM_VFE_CLK_RATE_NOMINAL] [vfe_dev->hw_info->vfe_clk_idx]) { - ret = cx_ipeak_update(vfe_dev->vfe_cx_ipeak, true); + pr_debug("%s: clk is more than Nominal vfe %d, ipeak bit %d\n", + __func__, vfe_dev->pdev->id, vfe_dev->cx_ipeak_bit); + ret = cam_cx_ipeak_update_vote_cx_ipeak(vfe_dev->cx_ipeak_bit); if (ret) { pr_err("%s: cx_ipeak_update failed %d\n", __func__, ret); @@ -2738,7 +2741,9 @@ int msm_vfe47_set_clk_rate(struct vfe_device *vfe_dev, long *rate) prev_clk_rate >= vfe_dev->vfe_clk_rates[MSM_VFE_CLK_RATE_NOMINAL] [vfe_dev->hw_info->vfe_clk_idx]) { - ret = cx_ipeak_update(vfe_dev->vfe_cx_ipeak, false); + pr_debug("%s:clk is less than Nominal vfe %d, ipeak bit %d\n", + __func__, vfe_dev->pdev->id, vfe_dev->cx_ipeak_bit); + ret = cam_cx_ipeak_unvote_cx_ipeak(vfe_dev->cx_ipeak_bit); if (ret) { pr_err("%s: cx_ipeak_update failed %d\n", __func__, ret); -- GitLab