Loading arch/ia64/kernel/esi.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -65,7 +65,7 @@ static int __init esi_init (void) } } if (!esi) if (!esi) return -ENODEV;; return -ENODEV; systab = __va(esi); systab = __va(esi); Loading arch/ia64/kvm/process.c +3 −3 Original line number Original line Diff line number Diff line Loading @@ -130,7 +130,7 @@ static void collect_interruption(struct kvm_vcpu *vcpu) if (vdcr & IA64_DCR_PP) { if (vdcr & IA64_DCR_PP) { vpsr |= IA64_PSR_PP; vpsr |= IA64_PSR_PP; } else { } else { vpsr &= ~IA64_PSR_PP;; vpsr &= ~IA64_PSR_PP; } } vcpu_set_psr(vcpu, vpsr); vcpu_set_psr(vcpu, vpsr); Loading Loading @@ -594,11 +594,11 @@ static void set_pal_call_data(struct kvm_vcpu *vcpu) p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); break; break; case PAL_BRAND_INFO: case PAL_BRAND_INFO: p->u.pal_data.gr29 = gr29;; p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); break; break; default: default: p->u.pal_data.gr29 = gr29;; p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); } } p->u.pal_data.gr28 = gr28; p->u.pal_data.gr28 = gr28; Loading arch/ia64/kvm/vcpu.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -406,7 +406,7 @@ void getreg(unsigned long regnum, unsigned long *val, * Now look at registers in [0-31] range and init correct UNAT * Now look at registers in [0-31] range and init correct UNAT */ */ addr = (unsigned long)regs; addr = (unsigned long)regs; unat = ®s->eml_unat;; unat = ®s->eml_unat; addr += gr_info[regnum]; addr += gr_info[regnum]; Loading arch/ia64/kvm/vtlb.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -135,7 +135,7 @@ struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type) u64 rid; u64 rid; rid = vcpu_get_rr(vcpu, va); rid = vcpu_get_rr(vcpu, va); rid = rid & RR_RID_MASK;; rid = rid & RR_RID_MASK; if (type == D_TLB) { if (type == D_TLB) { if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; Loading Loading @@ -518,7 +518,7 @@ struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data) struct thash_cb *hcb = &v->arch.vtlb; struct thash_cb *hcb = &v->arch.vtlb; cch = __vtr_lookup(v, va, is_data);; cch = __vtr_lookup(v, va, is_data); if (cch) if (cch) return cch; return cch; Loading Loading
arch/ia64/kernel/esi.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -65,7 +65,7 @@ static int __init esi_init (void) } } if (!esi) if (!esi) return -ENODEV;; return -ENODEV; systab = __va(esi); systab = __va(esi); Loading
arch/ia64/kvm/process.c +3 −3 Original line number Original line Diff line number Diff line Loading @@ -130,7 +130,7 @@ static void collect_interruption(struct kvm_vcpu *vcpu) if (vdcr & IA64_DCR_PP) { if (vdcr & IA64_DCR_PP) { vpsr |= IA64_PSR_PP; vpsr |= IA64_PSR_PP; } else { } else { vpsr &= ~IA64_PSR_PP;; vpsr &= ~IA64_PSR_PP; } } vcpu_set_psr(vcpu, vpsr); vcpu_set_psr(vcpu, vpsr); Loading Loading @@ -594,11 +594,11 @@ static void set_pal_call_data(struct kvm_vcpu *vcpu) p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); break; break; case PAL_BRAND_INFO: case PAL_BRAND_INFO: p->u.pal_data.gr29 = gr29;; p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); break; break; default: default: p->u.pal_data.gr29 = gr29;; p->u.pal_data.gr29 = gr29; p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); } } p->u.pal_data.gr28 = gr28; p->u.pal_data.gr28 = gr28; Loading
arch/ia64/kvm/vcpu.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -406,7 +406,7 @@ void getreg(unsigned long regnum, unsigned long *val, * Now look at registers in [0-31] range and init correct UNAT * Now look at registers in [0-31] range and init correct UNAT */ */ addr = (unsigned long)regs; addr = (unsigned long)regs; unat = ®s->eml_unat;; unat = ®s->eml_unat; addr += gr_info[regnum]; addr += gr_info[regnum]; Loading
arch/ia64/kvm/vtlb.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -135,7 +135,7 @@ struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type) u64 rid; u64 rid; rid = vcpu_get_rr(vcpu, va); rid = vcpu_get_rr(vcpu, va); rid = rid & RR_RID_MASK;; rid = rid & RR_RID_MASK; if (type == D_TLB) { if (type == D_TLB) { if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; Loading Loading @@ -518,7 +518,7 @@ struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data) struct thash_cb *hcb = &v->arch.vtlb; struct thash_cb *hcb = &v->arch.vtlb; cch = __vtr_lookup(v, va, is_data);; cch = __vtr_lookup(v, va, is_data); if (cch) if (cch) return cch; return cch; Loading