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Commit 57d0ee07 authored by Jamie Lentin's avatar Jamie Lentin Committed by Gregory CLEMENT
Browse files

clk: mvebu: Add clk support for the orion5x SoC mv88f5181 



Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: default avatarJamie Lentin <jm@lentin.co.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 29b4817d

Documentation/devicetree/bindings/clock/mvebu-core-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ Required properties: 
	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC

	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC

	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC

	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC

	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC

drivers/clk/mvebu/orion.c

+70 −0
Original line number Diff line number Diff line
@@ -20,6 +20,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { 
	{ .id = 0, .name = "ddrclk", }

};



/*

 * Orion 5181

 */



#define SAR_MV88F5181_TCLK_FREQ      8

#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3



static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)

{

	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &

		SAR_MV88F5181_TCLK_FREQ_MASK;

	if (opt == 0)

		return 133333333;

	else if (opt == 1)

		return 150000000;

	else if (opt == 2)

		return 166666667;

	else

		return 0;

}



#define SAR_MV88F5181_CPU_FREQ       4

#define SAR_MV88F5181_CPU_FREQ_MASK  0xf



static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)

{

	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &

		SAR_MV88F5181_CPU_FREQ_MASK;

	if (opt == 0)

		return 333333333;

	else if (opt == 1 || opt == 2)

		return 400000000;

	else if (opt == 3)

		return 500000000;

	else

		return 0;

}



static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,

					   int *mult, int *div)

{

	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &

		SAR_MV88F5181_CPU_FREQ_MASK;

	if (opt == 0 || opt == 1) {

		*mult = 1;

		*div  = 2;

	} else if (opt == 2 || opt == 3) {

		*mult = 1;

		*div  = 3;

	} else {

		*mult = 0;

		*div  = 1;

	}

}



static const struct coreclk_soc_desc mv88f5181_coreclks = {

	.get_tclk_freq = mv88f5181_get_tclk_freq,

	.get_cpu_freq = mv88f5181_get_cpu_freq,

	.get_clk_ratio = mv88f5181_get_clk_ratio,

	.ratios = orion_coreclk_ratios,

	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),

};



static void __init mv88f5181_clk_init(struct device_node *np)

{

	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);

}



CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);



/*

 * Orion 5182

 */