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Commit 5791f1e9 authored by Shefali Jain's avatar Shefali Jain Committed by Gerrit - the friendly Code Review server
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clk: qcom: gcc: Keep NPU clocks always ON for LITO 



Add CRITICAL flag for NPU_BWMON clocks to keep it always on and remove
support of dpm clocks as they would not be managed from HLOS.

Change-Id: I715d53b1d6eea17b7fc52392eb64f5144a28298c
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 5b273e73

drivers/clk/qcom/gcc-lito.c

+3 −61
Original line number Diff line number Diff line
@@ -280,31 +280,6 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_dpm_clk_src[] = {

	F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),

	{ }

};



static struct clk_rcg2 gcc_dpm_clk_src = {

	.cmd_rcgr = 0x4600c,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = gcc_parent_map_0,

	.freq_tbl = ftbl_gcc_dpm_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_dpm_clk_src",

		.parent_names = gcc_parent_names_0,

		.num_parents = 4,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 100000000,

			[VDD_LOW] = 150000000,

			[VDD_LOW_L1] = 200000000},

	},

};



static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
@@ -1315,39 +1290,6 @@ static struct clk_branch gcc_disp_xo_clk = { 
	},

};



static struct clk_branch gcc_dpm_ahb_clk = {

	.halt_reg = 0x46008,

	.halt_check = BRANCH_HALT,

	.hwcg_reg = 0x46008,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x46008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_dpm_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_dpm_clk = {

	.halt_reg = 0x46004,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_dpm_clk",

			.parent_names = (const char *[]){

				"gcc_dpm_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_gp1_clk = {

	.halt_reg = 0x64000,

	.halt_check = BRANCH_HALT,
@@ -1512,6 +1454,7 @@ static struct clk_branch gcc_npu_bwmon2_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_npu_bwmon2_axi_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1525,6 +1468,7 @@ static struct clk_branch gcc_npu_bwmon_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_npu_bwmon_axi_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1538,6 +1482,7 @@ static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_npu_bwmon_cfg_ahb_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2565,9 +2510,6 @@ static struct clk_regmap *gcc_lito_clocks[] = { 
	[GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,

	[GCC_DISP_THROTTLE_SF_AXI_CLK] = &gcc_disp_throttle_sf_axi_clk.clkr,

	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,

	[GCC_DPM_AHB_CLK] = &gcc_dpm_ahb_clk.clkr,

	[GCC_DPM_CLK] = &gcc_dpm_clk.clkr,

	[GCC_DPM_CLK_SRC] = &gcc_dpm_clk_src.clkr,

	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,

	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,

	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,