Merge "msm: qpnp-power-on: configure KPDPWR_N S2 for HARD_RESET at TWM entry" (55dc2c14) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/input/misc/qpnp-power-on.c

+26 −12

Original line number	Diff line number	Diff line
		@@ -541,6 +541,19 @@ static ssize_t debounce_us_store(struct device *dev,
		}
		static DEVICE_ATTR_RW(debounce_us);

		static struct qpnp_pon_config *
		qpnp_get_cfg(struct qpnp_pon *pon, u32 pon_type)
		{
		int i;

		for (i = 0; i < pon->num_pon_config; i++) {
		if (pon_type == pon->pon_cfg[i].pon_type)
		return &pon->pon_cfg[i];
		}

		return NULL;
		}

		#define PON_TWM_ENTRY_PBS_BIT BIT(0)
		static int qpnp_pon_reset_config(struct qpnp_pon *pon,
		enum pon_power_off_type type)
		@@ -548,6 +561,7 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
		int rc;
		bool disable = false;
		u16 rst_en_reg;
		struct qpnp_pon_config *cfg;

		/* Ignore the PS_HOLD reset config if TWM ENTRY is enabled */
		if (pon->support_twm_config && pon->twm_state == PMIC_TWM_ENABLE) {
		@@ -558,6 +572,18 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
		rc);
		return rc;
		}

		cfg = qpnp_get_cfg(pon, PON_KPDPWR);
		if (cfg) {
		/* configure KPDPWR_S2 to Hard reset */
		rc = qpnp_pon_masked_write(pon, cfg->s2_cntl_addr,
		QPNP_PON_S2_CNTL_TYPE_MASK,
		PON_POWER_OFF_HARD_RESET);
		if (rc < 0)
		pr_err("Unable to config KPDPWR_N S2 for hard-reset rc=%d\n",
		rc);
		}

		pr_crit("PMIC configured for TWM entry\n");
		return 0;
		}
		@@ -917,18 +943,6 @@ static int qpnp_pon_store_and_clear_warm_reset(struct qpnp_pon *pon)
		return 0;
		}

		static struct qpnp_pon_config qpnp_get_cfg(struct qpnp_pon pon, u32 pon_type)
		{
		int i;

		for (i = 0; i < pon->num_pon_config; i++) {
		if (pon_type == pon->pon_cfg[i].pon_type)
		return &pon->pon_cfg[i];
		}

		return NULL;
		}

		static int qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
		{
		struct qpnp_pon_config *cfg = NULL;