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Commit 5569aedf authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v4.7-rockchip-clk3' of... 

Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

A spelling fix and a bunch of rk3399 clock fixes.

* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix the rk3399 cifout clock
  clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
  clk: rockchip: add some frequencies on the rk3399 PLL table
  clk: rockchip: assign more necessary rk3399 clock ids
  clk: rockchip: export some necessary rk3399 clock ids
  clk: rockchip: rename rga clock-id on rk3399
  clk: rockchip: add general gpu soft-reset on rk3399
  clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
  clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
parents 58657d18 fd8bc829

drivers/clk/rockchip/clk-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 
	/* wait for the pll to lock */

	ret = rockchip_pll_wait_lock(pll);

	if (ret) {

		pr_warn("%s: pll update unsucessful, trying to restore old params\n",

		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",

			__func__);

		rockchip_rk3036_pll_set_params(pll, &cur);

	}
@@ -475,7 +475,7 @@ static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 
	/* wait for the pll to lock */

	ret = rockchip_pll_wait_lock(pll);

	if (ret) {

		pr_warn("%s: pll update unsucessful, trying to restore old params\n",

		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",

			__func__);

		rockchip_rk3066_pll_set_params(pll, &cur);

	}

drivers/clk/rockchip/clk-rk3399.c

+177 −167

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/rk3399-cru.h

+4 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ 
#define SCLK_MACREF_OUT			106

#define SCLK_VOP0_PWM			107

#define SCLK_VOP1_PWM			108

#define SCLK_RGA			109

#define SCLK_RGA_CORE			109

#define SCLK_ISP0			110

#define SCLK_ISP1			111

#define SCLK_HDMI_CEC			112
@@ -129,6 +129,8 @@ 
#define SCLK_DPHY_TX0_CFG		163

#define SCLK_DPHY_TX1RX1_CFG		164

#define SCLK_DPHY_RX0_CFG		165

#define SCLK_RMII_SRC			166

#define SCLK_PCIEPHY_REF100M		167



#define DCLK_VOP0			180

#define DCLK_VOP1			181
@@ -671,6 +673,7 @@ 
#define SRST_P_EDP_CTRL			285



/* cru_softrst_con18 */

#define SRST_A_GPU			288

#define SRST_A_GPU_NOC			289

#define SRST_A_GPU_GRF			290

#define SRST_PVTM_GPU			291