Merge branch 'asoc-4.18' into asoc-next

Qualcomm APR (Asynchronous Packet Router) binding

This binding describes the Qualcomm APR. APR is a IPC protocol for

communication between Application processor and QDSP. APR is mainly

used for audio/voice services on the QDSP.

- compatible:

	Usage: required

	Value type: <stringlist>

	Definition: must be "qcom,apr-v<VERSION-NUMBER>", example "qcom,apr-v2"

- reg

	Usage: required

	Value type: <u32>

	Definition: Destination processor ID.

	Possible values are :

			1 - APR simulator

			2 - PC

			3 - MODEM

			4 - ADSP

			5 - APPS

			6 - MODEM2

			7 - APPS2

= APR SERVICES

Each subnode of the APR node represents service tied to this apr. The name

of the nodes are not important. The properties of these nodes are defined

by the individual bindings for the specific service

- All APR services MUST contain the following property:

- reg

	Usage: required

	Value type: <u32>

	Definition: APR Service ID

	Possible values are :

			3 - DSP Core Service

			4 - Audio Front End Service.

			5 - Voice Stream Manager Service.

			6 - Voice processing manager.

			7 - Audio Stream Manager Service.

			8 - Audio Device Manager Service.

			9 - Multimode voice manager.

			10 - Core voice stream.

			11 - Core voice processor.

			12 - Ultrasound stream manager.

			13 - Listen stream manager.

= EXAMPLE

The following example represents a QDSP based sound card on a MSM8996 device

which uses apr as communication between Apps and QDSP.

	apr@4 {

		compatible = "qcom,apr-v2";

		reg = <APR_DOMAIN_ADSP>;

		q6core@3 {

			compatible = "qcom,q6core";

			reg = <APR_SVC_ADSP_CORE>;

		};

		q6afe@4 {

			compatible = "qcom,q6afe";

			reg = <APR_SVC_AFE>;

			dais {

				#sound-dai-cells = <1>;

				hdmi@1 {

					reg = <1>;

				};

			};

		};

		q6asm@7 {

			compatible = "qcom,q6asm";

			reg = <APR_SVC_ASM>;

			...

		};

		q6adm@8 {

			compatible = "qcom,q6adm";

			reg = <APR_SVC_ADM>;

			...

		};

	};

Analog Devices SSM2305 Speaker Amplifier

========================================

Required properties:

  - compatible : "adi,ssm2305"

  - shutdown-gpios : The gpio connected to the shutdown pin.

                     The gpio signal is ACTIVE_LOW.

Example:

ssm2305: analog-amplifier {

	compatible = "adi,ssm2305";

	shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;

};

* Atmel I2S controller

Required properties:

- compatible:     Should be "atmel,sama5d2-i2s".

- reg:            Should be the physical base address of the controller and the

                  length of memory mapped region.

- interrupts:     Should contain the interrupt for the controller.

- dmas:           Should be one per channel name listed in the dma-names property,

                  as described in atmel-dma.txt and dma.txt files.

- dma-names:      Two dmas have to be defined, "tx" and "rx".

                  This IP also supports one shared channel for both rx and tx;

                  if this mode is used, one "rx-tx" name must be used.

- clocks:         Must contain an entry for each entry in clock-names.

                  Please refer to clock-bindings.txt.

- clock-names:    Should be one of each entry matching the clocks phandles list:

                  - "pclk" (peripheral clock) Required.

                  - "gclk" (generated clock) Optional (1).

                  - "aclk" (Audio PLL clock) Optional (1).

                  - "muxclk" (I2S mux clock) Optional (1).

Optional properties:

- pinctrl-0:      Should specify pin control groups used for this controller.

- princtrl-names: Should contain only one value - "default".

(1) : Only the peripheral clock is required. The generated clock, the Audio

      PLL clock adn the I2S mux clock are optional and should only be set

      together, when Master Mode is required.

Example:

	i2s@f8050000 {

		compatible = "atmel,sama5d2-i2s";

		reg = <0xf8050000 0x300>;

		interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;

		dmas = <&dma0

			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |

			 AT91_XDMAC_DT_PERID(31))>,

		       <&dma0

			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |

			 AT91_XDMAC_DT_PERID(32))>;

		dma-names = "tx", "rx";

		clocks = <&i2s0_clk>, <&i2s0_gclk>, <&audio_pll_pmc>, <&i2s0muxck>;

		clock-names = "pclk", "gclk", "aclk", "muxclk";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2s0_default>;

	};

Example:

Example:

codec: cs42888@48 {

cs42888: codec@48 {

	compatible = "cirrus,cs42888";

	compatible = "cirrus,cs42888";

	reg = <0x48>;

	reg = <0x48>;

	clocks = <&codec_mclk 0>;

	clocks = <&codec_mclk 0>;

			  it. This property is optional depending on the SoC

			  it. This property is optional depending on the SoC

			  design.

			  design.

   - big-endian		: If this property is absent, the little endian mode

			  will be in use as default. Otherwise, the big endian

			  mode will be in use for all the device registers.

   - fsl,asrc-rate	: Defines a mutual sample rate used by DPCM Back Ends.

   - fsl,asrc-rate	: Defines a mutual sample rate used by DPCM Back Ends.

   - fsl,asrc-width	: Defines a mutual sample width used by DPCM Back Ends.

   - fsl,asrc-width	: Defines a mutual sample width used by DPCM Back Ends.

Optional properties:

   - big-endian		: If this property is absent, the little endian mode

			  will be in use as default. Otherwise, the big endian

			  mode will be in use for all the device registers.

Example:

Example:

asrc: asrc@2034000 {

asrc: asrc@2034000 {