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Commit 54e85e4c authored by Alexander Beykun's avatar Alexander Beykun
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clk/qcom/mdss: add 7nm dp phy pll support 



Configure 7nm Display Port PLL. Define and register
DP PLL related clocks to clock framework.

Change-Id: Ieab078392c76ceb0d2626341c0ccba2f1e49e06c
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 6f0f0541
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