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Commit 544f874d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Fix mistaken description for pcie1&3 on sa8195p"

parents a8af212b c7e5afef

arch/arm64/boot/dts/qcom/sa8195p-pcie.dtsi

+33 −33
Original line number Diff line number Diff line
@@ -555,38 +555,38 @@ 
		msi-controller;

		reg = <0x17a00040 0x0>;

		interrupt-parent = <&pdc>;

		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;

		interrupts = <GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 922 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,

			<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>;

	};



	pcie2: qcom,pcie@1c18000 {
@@ -1294,7 +1294,7 @@ 
		};

	};



	pcie3_msi: qcom,pcie1_msi@17a00040 {

	pcie3_msi: qcom,pcie3_msi@17a00040 {

		compatible = "qcom,pci-msi";

		msi-controller;

		reg = <0x17a00040 0x0>;