Commit 54071e41 authored May 05, 2018 by Nicholas Piggin Committed by Michael Ellerman Jun 03, 2018

powerpc/64s: micro-optimise __hard_irq_enable() for mtmsrd L=1 support



Book3S minimum supported ISA version now requires mtmsrd L=1. This
instruction does not require bits other than RI and EE to be supplied,
so __hard_irq_enable() and __hard_irq_disable() does not have to read
the kernel_msr from paca.

Interrupt entry code already relies on L=1 support.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 9f4b61b2

arch/powerpc/include/asm/hw_irq.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -228,8 +228,8 @@ static inline bool arch_irqs_disabled(void)
		#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory")
		#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory")
		#else
		#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr \| MSR_EE, 1)
		#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
		#define __hard_irq_enable() __mtmsrd(MSR_EE\|MSR_RI, 1)
		#define __hard_irq_disable() __mtmsrd(MSR_RI, 1)
		#endif

		#define hard_irq_disable() do { \