Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 537340d3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: enable SiRF GNSS Driver and hsuart1"

parents 09378bb7 204086a8

arch/arm64/boot/dts/qcom/sa8155-adp-common.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -51,6 +51,10 @@ 
	status = "ok";

};



&qupv3_se4_2uart {

	status = "ok";

};



&qupv3_se10_i2c {

	#address-cells = <1>;

	#size-cells = <0>;
@@ -100,6 +104,13 @@ 
		};

	};



	ss5_pwr_ctrl0 {

		compatible = "gnss_sirf";

		pinctrl-0 = <&ss5_pwr_ctrl_rst_on>;

		ssVreset-gpio = <&tlmm 11 1>;

		ssVonoff-gpio = <&tlmm 39 1>;

	};



	qcom,turing@8300000 {

		status = "ok";

	};

arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -778,6 +778,36 @@ 
			};

		};



		ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins {

			ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on {

				mux {

					pins = "gpio11", "gpio39";

					function = "gpio";

				};



				config {

					pins = "gpio11", "gpio39";

					drive-strength = <16>; /* 16 mA */

					bias-pull-up;

					output-high;

				};

			};



			ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off {

				mux {

					pins = "gpio11", "gpio39";

					function = "gpio";

				};



				config {

					pins = "gpio11", "gpio39";

					drive-strength = <16>; /* 16 mA */

					bias-pull-up;

					output-high;

				};

			};

		};



		/* SE 4 pin mappings */

		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {

			qupv3_se4_i2c_active: qupv3_se4_i2c_active {
@@ -839,6 +869,34 @@ 
			};

		};



		qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {

			qupv3_se4_2uart_active: qupv3_se4_2uart_active {

				mux {

					pins = "gpio41", "gpio42";

					function = "qup9";

				};



				config {

					pins = "gpio41", "gpio42";

					drive-strength = <16>;

					bias-disable;

				};

			};



			qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {

				mux {

					pins = "gpio41", "gpio42";

					function = "gpio";

				};



				config {

					pins = "gpio41", "gpio42";

					drive-strength = <16>;

					bias-disable;

				};

			};

		};



		/* SE 5 pin mappings */

		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {

			qupv3_se5_i2c_active: qupv3_se5_i2c_active {

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -392,6 +392,23 @@ 
		};

	};



	/* GNSS UART Instance for CDP/MTP platform */

	qupv3_se4_2uart: qcom,qup_uart@a84000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa84000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_2uart_active>;

		pinctrl-1 = <&qupv3_se4_2uart_sleep>;

		interrupts = <GIC_SPI 354 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* 2-wire UART */



	/* Debug UART Instance for CDP/MTP platform */

arch/arm64/boot/dts/qcom/sm8150.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
	aliases {

		serial0 = &qupv3_se12_2uart;

		hsuart0 = &qupv3_se13_4uart;

		hsuart1 = &qupv3_se4_2uart;

		spi0 = &qupv3_se3_spi;

		i2c0 = &qupv3_se4_i2c;

	};