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Commit 5301f005 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

include: dtbindings: clock: Update clock ID's of Lagoon 



Update the clock ID's as per the new freq plan for
NPUCC and GCC.

Change-Id: I014156b25b34a2ec5b950656f022bcc49d9f90a2
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent f56ce403

include/dt-bindings/clock/qcom,gcc-lagoon.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAGOON_H
@@ -152,6 +152,7 @@ 
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK		142

#define GCC_RX5_PCIE_CLKREF_CLK			143

#define GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC		144

#define GCC_NPU_PLL0_MAIN_DIV_CLK_SRC		145



/* GCC resets */

#define GCC_QUSB2PHY_PRIM_BCR			0

include/dt-bindings/clock/qcom,npucc-lagoon.h

+24 −25
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_NPU_CC_LAGOON_H



/* NPU_CC clocks */

#define NPU_CC_PLL0			0

#define NPU_CC_PLL0_OUT_EVEN		1

#define NPU_CC_PLL1			2

#define NPU_CC_PLL1_OUT_EVEN		3

#define NPU_CC_BTO_CORE_CLK		5

#define NPU_CC_BWMON_CLK		6

#define NPU_CC_CAL_HM0_CDC_CLK		7

#define NPU_CC_CAL_HM0_CLK		8

#define NPU_CC_CAL_HM0_CLK_SRC		9

#define NPU_CC_CAL_HM0_PERF_CNT_CLK	10

#define NPU_CC_CORE_CLK			11

#define NPU_CC_CORE_CLK_SRC		12

#define NPU_CC_DSP_AHBM_CLK		13

#define NPU_CC_DSP_AHBS_CLK		14

#define NPU_CC_DSP_AXI_CLK		15

#define NPU_CC_NOC_AHB_CLK		16

#define NPU_CC_NOC_AXI_CLK		17

#define NPU_CC_NOC_DMA_CLK		18

#define NPU_CC_RSC_XO_CLK		19

#define NPU_CC_S2P_CLK			20

#define NPU_CC_XO_CLK			21

#define NPU_CC_XO_CLK_SRC		22

#define NPU_DSP_CORE_CLK_SRC		23

#define NPU_Q6SS_PLL			24

#define NPU_CC_ATB_CLK						0

#define NPU_CC_BTO_CORE_CLK					1

#define NPU_CC_BWMON_CLK					2

#define NPU_CC_CAL_HM0_CDC_CLK					3

#define NPU_CC_CAL_HM0_CLK					4

#define NPU_CC_CAL_HM0_CLK_SRC					5

#define NPU_CC_CAL_HM0_PERF_CNT_CLK				6

#define NPU_CC_CORE_CLK					7

#define NPU_CC_CORE_CLK_SRC					8

#define NPU_CC_DSP_AHBM_CLK					9

#define NPU_CC_DSP_AHBS_CLK					10

#define NPU_CC_DSP_AXI_CLK					11

#define NPU_CC_NOC_AHB_CLK					12

#define NPU_CC_NOC_AXI_CLK					13

#define NPU_CC_NOC_DMA_CLK					14

#define NPU_CC_PLL0						15

#define NPU_CC_PLL1						16

#define NPU_CC_RSC_XO_CLK					17

#define NPU_CC_S2P_CLK						18

#define NPU_CC_XO_CLK						19

#define NPU_CC_XO_CLK_SRC					20

#define NPU_DSP_CORE_CLK_SRC					21

#define NPU_Q6SS_PLL						22



/* NPU_CC resets */

#define NPU_CC_CAL_HM0_BCR		0