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Commit 529b662e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "power: qpnp-qg: Add a start condition to begin CL"

parents 6bebd2ce 17835267

drivers/power/supply/qcom/fg-alg.c

+6 −6
Original line number Diff line number Diff line
@@ -493,14 +493,14 @@ static int cap_learning_begin(struct cap_learning *cl, u32 batt_soc_cp) 


	batt_soc_pct = DIV_ROUND_CLOSEST(batt_soc_cp, 100);



	if (!cl->dt.cl_wt_enable) {

		if (batt_soc_pct > cl->dt.max_start_soc ||

				batt_soc_pct < cl->dt.min_start_soc) {

	if ((cl->dt.max_start_soc != -EINVAL &&

			batt_soc_pct > cl->dt.max_start_soc) ||

			(cl->dt.min_start_soc != -EINVAL &&

			batt_soc_pct < cl->dt.min_start_soc)) {

		pr_debug("Battery SOC %d is high/low, not starting\n",

					batt_soc_pct);

		return -EINVAL;

	}

	}



	cl->init_cap_uah = div64_s64(cl->learned_cap_uah * batt_soc_cp,

					CENTI_FULL_SOC);

drivers/power/supply/qcom/qpnp-fg-gen4.c

+6 −3
Original line number Diff line number Diff line
@@ -5704,9 +5704,6 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) 
	of_property_read_u32(node, "qcom,cl-min-delta-batt-soc",

					&chip->cl->dt.min_delta_batt_soc);



	chip->cl->dt.cl_wt_enable = of_property_read_bool(node,

						"qcom,cl-wt-enable");



	rc = of_property_read_u32(node, "qcom,cl-min-temp", &temp);

	if (rc < 0)

		chip->cl->dt.min_temp = DEFAULT_CL_MIN_TEMP_DECIDEGC;
@@ -5745,6 +5742,12 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) 


	of_property_read_u32(node, "qcom,cl-skew", &chip->cl->dt.skew_decipct);



	if (of_property_read_bool(node, "qcom,cl-wt-enable")) {

		chip->cl->dt.cl_wt_enable = true;

		chip->cl->dt.max_start_soc = -EINVAL;

		chip->cl->dt.min_start_soc = -EINVAL;

	}



	rc = of_property_read_u32(node, "qcom,fg-batt-temp-hot", &temp);

	if (rc < 0)

		chip->dt.batt_temp_hot_thresh = -EINVAL;

drivers/power/supply/qcom/qpnp-qg.c

+18 −2
Original line number Diff line number Diff line
@@ -2244,6 +2244,17 @@ static const struct power_supply_desc qg_psy_desc = { 
	.property_is_writeable = qg_property_is_writeable,

};



#define DEFAULT_CL_BEGIN_IBAT_UA	(-100000)

static bool qg_cl_ok_to_begin(void *data)

{

	struct qpnp_qg *chip = data;



	if (chip->last_fifo_i_ua < DEFAULT_CL_BEGIN_IBAT_UA)

		return true;



	return false;

}



#define DEFAULT_RECHARGE_SOC 95

static int qg_charge_full_update(struct qpnp_qg *chip)

{
@@ -3718,6 +3729,7 @@ static int qg_alg_init(struct qpnp_qg *chip) 
	cl->get_cc_soc = qg_get_cc_soc;

	cl->get_learned_capacity = qg_get_learned_capacity;

	cl->store_learned_capacity = qg_store_learned_capacity;

	cl->ok_to_begin = qg_cl_ok_to_begin;

	cl->data = chip;



	rc = cap_learning_init(cl);
@@ -3761,6 +3773,7 @@ static int qg_alg_init(struct qpnp_qg *chip) 
#define DEFAULT_CL_MIN_LIM_DECIPERC	500

#define DEFAULT_CL_MAX_LIM_DECIPERC	100

#define DEFAULT_CL_DELTA_BATT_SOC	10

#define DEFAULT_CL_WT_START_SOC		15

#define DEFAULT_SHUTDOWN_TEMP_DIFF	60	/* 6 degC */

#define DEFAULT_ESR_QUAL_CURRENT_UA	130000

#define DEFAULT_ESR_QUAL_VBAT_UV	7000
@@ -4139,8 +4152,11 @@ static int qg_parse_dt(struct qpnp_qg *chip) 
		of_property_read_u32(node, "qcom,cl-min-delta-batt-soc",

					&chip->cl->dt.min_delta_batt_soc);



		chip->cl->dt.cl_wt_enable = of_property_read_bool(node,

							"qcom,cl-wt-enable");

		if (of_property_read_bool(node, "qcom,cl-wt-enable")) {

			chip->cl->dt.cl_wt_enable = true;

			chip->cl->dt.min_start_soc = DEFAULT_CL_WT_START_SOC;

			chip->cl->dt.max_start_soc = -EINVAL;

		}



		qg_dbg(chip, QG_DEBUG_PON, "DT: cl_min_start_soc=%d cl_max_start_soc=%d cl_min_temp=%d cl_max_temp=%d\n",

			chip->cl->dt.min_start_soc, chip->cl->dt.max_start_soc,