Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5015ed02 authored by Perry Randise's avatar Perry Randise
Browse files

msm: ipa3: removed Q6 register retrieve and add new retrievals 



Took out unnecessary retrieval of Q6 channel and event contexts
registers. Also added two new registers into the register retrieval
list.

Change-Id: I7aece73394e7d9fb0fadfd8b11d9dacf9d4ea5eb
CRs-Fixed: 2413750
Signed-off-by: default avatarPerry Randise <prandise@codeaurora.org>
parent ba0ccb0b

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c

+6 −21
Original line number Original line Diff line number Diff line
@@ -259,6 +259,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { 
	GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY,

	GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY,

			     ipa.dbg,

			     ipa.dbg,

			     ipa_ackmngr_cmdq_status_empty),

			     ipa_ackmngr_cmdq_status_empty),

	GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_WR,

			     ipa.dbg,

			     ipa_rx_hps_cmdq_cfg_wr),

	GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CFG_RD,

			     ipa.dbg,

			     ipa_rx_hps_cmdq_cfg_rd),





	/*

	/*

	 * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below.  This is

	 * NOTE: That GEN_SRC_DST_ADDR_MAP() not used below.  This is
@@ -851,27 +857,6 @@ void ipa_save_registers(void) 
				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1);

				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1);

	}

	}





	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) {

		u32 phys_ch_idx =

			ipa_reg_save.gsi.ch_cntxt.q6[

			    i].gsi_debug_ee_n_ch_k_vp_table.phy_ch;

		u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;



		if (!ipa_reg_save.gsi.ch_cntxt.q6[

			i].gsi_debug_ee_n_ch_k_vp_table.valid)

			continue;

		ipa_reg_save.gsi.ch_cntxt.q6[

			i].mcs_channel_scratch.scratch4.shram =

			IPA_READ_1xVECTOR_REG(

				GSI_SHRAM_n,

				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 2);

		ipa_reg_save.gsi.ch_cntxt.q6[

			i].mcs_channel_scratch.scratch5.shram =

			IPA_READ_1xVECTOR_REG(

				GSI_SHRAM_n,

				n + IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM - 1);

	}



	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) {

	for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC; i++) {

		u32 phys_ch_idx =

		u32 phys_ch_idx =

			ipa_reg_save.gsi.ch_cntxt.uc[

			ipa_reg_save.gsi.ch_cntxt.uc[

drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h

+17 −35
Original line number Original line Diff line number Diff line
@@ -102,8 +102,6 @@ 
#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000

#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_BIT_MASK 0x7E000

#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT    13

#define IPA_DEBUG_TESTBUS_RSRC_TYPE_CNT_SHIFT    13





#define IPA_REG_SAVE_HWP_GSI_EE                  2



/*

/*

 * A structure used to map a source address to destination address...

 * A structure used to map a source address to destination address...

 */

 */
@@ -380,27 +378,14 @@ struct map_src_dst_addr_s { 
		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \

		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \

	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \

		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \

		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \

	{ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE), \

		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\

		(u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_UC_EE].var_name }

			var_name }





/*

/*

 * Macro to define a particular register cfg entry for all GSI EE

 * Macro to define a particular register cfg entry for all GSI EE

 * register

 * register

 */

 */

#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \

#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
@@ -431,20 +416,16 @@ struct map_src_dst_addr_s { 
		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0),	\

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 2),	\

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }





#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \

#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \
@@ -469,7 +450,7 @@ struct map_src_dst_addr_s { 
		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }





/*

/*
@@ -492,6 +473,7 @@ struct map_src_dst_addr_s { 
enum ipa_hw_ee_e {

enum ipa_hw_ee_e {

	IPA_HW_A7_EE  = 0, /* A7's execution environment */

	IPA_HW_A7_EE  = 0, /* A7's execution environment */

	IPA_HW_Q6_EE  = 1, /* Q6's execution environment */

	IPA_HW_Q6_EE  = 1, /* Q6's execution environment */

	IPA_HW_UC_EE  = 2, /* UC's execution environment */

	IPA_HW_HWP_EE = 3, /* HWP's execution environment */

	IPA_HW_HWP_EE = 3, /* HWP's execution environment */

	IPA_HW_EE_MAX,     /* Max EE to support */

	IPA_HW_EE_MAX,     /* Max EE to support */

};

};
@@ -820,6 +802,10 @@ struct ipa_reg_save_dbg_s { 
		ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1];

		ipa_hps_dps_cmdq_status_arr[IPA_TESTBUS_SEL_EP_MAX + 1];

	struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s

	struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s

		ipa_hps_dps_cmdq_status_empty;

		ipa_hps_dps_cmdq_status_empty;

	union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u

		ipa_rx_hps_cmdq_cfg_wr;

	union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u

		ipa_rx_hps_cmdq_cfg_rd;





	struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s

	struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s

	  ipa_dps_tx_cmdq_cmd;

	  ipa_dps_tx_cmdq_cmd;
@@ -1188,8 +1174,6 @@ struct ipa_reg_save_gsi_fifo_status_s { 
struct ipa_reg_save_gsi_ch_cntxt_s {

struct ipa_reg_save_gsi_ch_cntxt_s {

	struct ipa_reg_save_gsi_ch_cntxt_per_ep_s

	struct ipa_reg_save_gsi_ch_cntxt_per_ep_s

		a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7];

		a7[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7];

	struct ipa_reg_save_gsi_ch_cntxt_per_ep_s

		q6[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6];

	struct ipa_reg_save_gsi_ch_cntxt_per_ep_s

	struct ipa_reg_save_gsi_ch_cntxt_per_ep_s

		uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC];

		uc[IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC];

};

};
@@ -1198,8 +1182,6 @@ struct ipa_reg_save_gsi_ch_cntxt_s { 
struct ipa_reg_save_gsi_evt_cntxt_s {

struct ipa_reg_save_gsi_evt_cntxt_s {

	struct ipa_reg_save_gsi_evt_cntxt_per_ep_s

	struct ipa_reg_save_gsi_evt_cntxt_per_ep_s

		a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7];

		a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7];

	struct ipa_reg_save_gsi_evt_cntxt_per_ep_s

		q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6];

	struct ipa_reg_save_gsi_evt_cntxt_per_ep_s

	struct ipa_reg_save_gsi_evt_cntxt_per_ep_s

		uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC];

		uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC];

};

};

drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h

+1 −11
Original line number Original line Diff line number Diff line
@@ -384,26 +384,16 @@ enum ipa_hw_irq_srcs_e { 
 */

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          15

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          15





/*

 * Total number of channel contexts that need to be saved for Q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6          6



/*

/*

 * Total number of channel contexts that need to be saved for UC

 * Total number of channel contexts that need to be saved for UC

 */

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC          2

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC          4





/*

/*

 * Total number of event ring contexts that need to be saved for APPS

 * Total number of event ring contexts that need to be saved for APPS

 */

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         12

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         12





/*

 * Total number of event ring contexts that need to be saved for Q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6         4



/*

/*

 * Total number of event ring contexts that need to be saved for UC

 * Total number of event ring contexts that need to be saved for UC

 */

 */

drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio.h

+32 −0
Original line number Original line Diff line number Diff line
@@ -7193,11 +7193,43 @@ 
					  0x0000038c)

					  0x0000038c)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

					  0x0000038c)

					  0x0000038c)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0xf

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN \

	in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

					HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) \

	in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, m)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) \

	out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, v)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m, v) \

	out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \

						m, \

						v, \

						HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0xf

#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

					  0x00000390)

					  0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \

					  0x00000390)

					  0x00000390)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0xf

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN \

	in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

					HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) \

	in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, m)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) \

	out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, v)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m, v) \

	out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \

						m, \

						v, \

						HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN)

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0xf

#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \

					     0x00000394)

					     0x00000394)

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \

drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hwio_def.h

+16 −0
Original line number Original line Diff line number Diff line
@@ -1874,6 +1874,22 @@ union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u { 
	struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s	def;

	struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s	def;

	u32					value;

	u32					value;

};

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s {

	u32	block_wr : 4;

	u32	reserved0 : 28;

};

union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u {

	struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s	def;

	u32						value;

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s {

	u32	block_rd : 4;

	u32	reserved0 : 28;

};

union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u {

	struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s	def;

	u32						value;

};

struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s {

struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s {

	u32	cmdq_packet_len_f : 16;

	u32	cmdq_packet_len_f : 16;

	u32	cmdq_dest_len_f : 16;

	u32	cmdq_dest_len_f : 16;