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Commit 4fe946cc authored by Namratha Siddappa's avatar Namratha Siddappa
Browse files

Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14 



* quic/dev/msm-4.14-display:
  drivers: clk: qcom: enable clk enable select bit during FIFO resync
  ARM: dts: msm: Enable esd support for sm8150
  drm/msm/dp: update AUX interrupt register definitions on sm8150
  drm/msm/dsi-staging: fix backlight update and dsi off race condition
  drm/msm/sde: Restarting ESD status check after Doze mode
  drm/msm/dsi-staging: validate TE GPIO prior to registering IRQ
  drm/msm/dsi-staging: initialize esd completion early
  drm/msm: add debugfs support to change ESD check interval
  drm/msm/dsi-staging: enable panel te irq only during esd check
  drm/msm/dsi-staging: add debugfs support to switch panel esd check mode
  drm/msm/dsi-staging: add support for te based esd check
  drm/msm/sde: Update dither programming for dual-pipe merge modes
  drm/msm/dp: skip HDCP version checks for simulation mode
  drm/msm/dp: validate inputs for simulated AUX transfers
  drm/msm/sde: remove frame done wait from sde_crtc
  ARM: dts: msm: update sleep vote node for sm8150
  clk: qcom: dispcc-sm8150: disable byte0/1 clock gate
  drm/msm/sde: fix invalid loop-condition in clear dim_layer

Change-Id: If55edda584e1b191ccdb6f986c7971bdca883ec6
Signed-off-by: default avatarNamratha Siddappa <namratha@codeaurora.org>
parents d2560a26 e60d32ea

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -400,6 +400,13 @@ 


/* PHY TIMINGS REVISION P */

&dsi_dual_nt35597_truly_video {

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-on-check-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -412,6 +419,13 @@ 
};



&dsi_dual_nt35597_truly_cmd {

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-on-check-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
@@ -450,6 +464,13 @@ 
};



&dsi_sharp_4k_dsc_video {

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x7>;

	qcom,mdss-dsi-panel-on-check-value = <0x7>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
@@ -461,6 +482,13 @@ 
};



&dsi_sharp_4k_dsc_cmd {

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x7>;

	qcom,mdss-dsi-panel-on-check-value = <0x7>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,mdss-dsi-display-timings {

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08

arch/arm64/boot/dts/qcom/sm8150-sde.dtsi

+4 −24
Original line number Diff line number Diff line
@@ -262,33 +262,13 @@ 


		/* data and reg bus scale settings */

		qcom,sde-data-bus {

			qcom,msm-bus,name = "mdss_sde_mnoc";

			qcom,msm-bus,name = "mdss_sde";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <2>;

			qcom,msm-bus,vectors-KBps =

			    <22 773 0 0>, <23 773 0 0>,

			    <22 773 0 6400000>, <23 773 0 6400000>,

			    <22 773 0 6400000>, <23 773 0 6400000>;

		};



		qcom,sde-llcc-bus {

			qcom,msm-bus,name = "mdss_sde_llcc";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <132 770 0 0>,

			    <132 770 0 6400000>,

			    <132 770 0 6400000>;

		};



		qcom,sde-ebi-bus {

			qcom,msm-bus,name = "mdss_sde_ebi";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

			    <129 512 0 0>,

			    <129 512 0 6400000>,

			    <129 512 0 6400000>;

				<22 512 0 0>, <23 512 0 0>,

				<22 512 0 6400000>, <23 512 0 6400000>,

				<22 512 0 6400000>, <23 512 0 6400000>;

		};



		qcom,sde-reg-bus {

drivers/clk/qcom/dispcc-sm8150.c

+1 −1
Original line number Diff line number Diff line
@@ -1522,7 +1522,7 @@ static int disp_cc_sm8150_probe(struct platform_device *pdev) 
	clk_trion_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);



	/* Enable clock gating for DSI and MDP clocks */

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x7f0, 0x7f0);

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x670, 0x670);



	ret = qcom_cc_really_probe(pdev, &disp_cc_sm8150_desc, regmap);

	if (ret) {

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+4 −1
Original line number Diff line number Diff line
@@ -896,7 +896,10 @@ static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc) 
	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_3, 0x04);



	data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5)));



	/* Turn on clk_en_sel bit prior to resync toggle fifo */

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5) |

								BIT(4)));

}



static void dsi_pll_phy_dig_reset(struct mdss_pll_resources *rsc)

drivers/gpu/drm/msm/dp/dp_aux.c

+26 −3
Original line number Diff line number Diff line
@@ -371,8 +371,11 @@ static void dp_aux_transfer_helper(struct dp_aux_private *aux, 
	bool i2c_read = input_msg->request &

		(DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);



	if (!i2c_mot || !i2c_read || (input_msg->size == 0))

	if (!i2c_mot || !i2c_read || (input_msg->size == 0)) {

		/* reset the offset for all other transaction types */

		aux->offset = 0;

		return;

	}



	/*

	 * Sending the segment value and EDID offset will be performed
@@ -417,7 +420,6 @@ static void dp_aux_transfer_helper(struct dp_aux_private *aux, 
	dp_aux_cmd_fifo_tx(aux, &helper_msg);

end:

	aux->offset += message_size;



	if (aux->offset == 0x80 || aux->offset == 0x100)

		aux->segment = 0x0; /* reset segment at end of block */

}
@@ -485,8 +487,25 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, 


	aux->aux_error_num = DP_AUX_ERR_NONE;



	if (!aux->dpcd || !aux->edid) {

		pr_err("invalid aux/dpcd structure\n");

		goto end;

	}



	if ((msg->address + msg->size) > SZ_16K) {

		pr_err("invalid dpcd access: addr=0x%x, size=0x%x\n",

				msg->address + msg->size);

		goto address_error;

	}



	if ((msg->size + aux->offset) > SZ_256) {

		pr_err("invalid edid access: offset=0x%x, size=0x%x\n",

				aux->offset, msg->size);

		goto address_error;

	}



	if (aux->native) {

		if (aux->read && ((msg->address + msg->size) < SZ_1K)) {

		if (aux->read) {

			aux->dp_aux.reg = msg->address;



			reinit_completion(&aux->comp);
@@ -525,6 +544,10 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, 
			DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;

	}



	return msg->size;



address_error:

	memset(msg->buffer, 0, msg->size);

	ret = msg->size;

end:

	return ret;