Merge "ARM: dts: msm: Add dummy clocks and GDSC support for SDMMAGPIE" (4e780981) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sdmmagpie-gdsc.dtsi

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		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		&soc {
		/* GDSCs in Global CC */
		pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "regulator-fixed";
		regulator-name = "pcie_0_gdsc";
		reg = <0x16b004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		pcie_tbu_gdsc: qcom,gdsc@128004 {
		compatible = "regulator-fixed";
		regulator-name = "pcie_tbu_gdsc";
		reg = <0x128004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "regulator-fixed";
		regulator-name = "ufs_phy_gdsc";
		reg = <0x177004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		usb30_prim_gdsc: qcom,gdsc@10f004 {
		compatible = "regulator-fixed";
		regulator-name = "usb30_prim_gdsc";
		reg = <0x10f004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d030 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
		reg = <0x17d030 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d03c {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
		reg = <0x17d03c 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d034 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
		reg = <0x17d034 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d038 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
		reg = <0x17d038 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		reg = <0x17d040 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d048 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		reg = <0x17d048 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 {
		compatible = "regulator-fixed";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
		reg = <0x17d044 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
		};

		/* GDSCs in Camera CC */
		bps_gdsc: qcom,gdsc@ad07004 {
		compatible = "regulator-fixed";
		regulator-name = "bps_gdsc";
		reg = <0xad07004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		ife_0_gdsc: qcom,gdsc@ad0a004 {
		compatible = "regulator-fixed";
		regulator-name = "ife_0_gdsc";
		reg = <0xad0a004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		ife_1_gdsc: qcom,gdsc@ad0b004 {
		compatible = "regulator-fixed";
		regulator-name = "ife_1_gdsc";
		reg = <0xad0b004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		ipe_0_gdsc: qcom,gdsc@ad08004 {
		compatible = "regulator-fixed";
		regulator-name = "ipe_0_gdsc";
		reg = <0xad08004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		ipe_1_gdsc: qcom,gdsc@ad09004 {
		compatible = "regulator-fixed";
		regulator-name = "ipe_1_gdsc";
		reg = <0xad09004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		titan_top_gdsc: qcom,gdsc@ad0c1c4 {
		compatible = "regulator-fixed";
		regulator-name = "titan_top_gdsc";
		reg = <0xad0c1c4 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		/* GDSCs in Display CC */
		mdss_core_gdsc: qcom,gdsc@0f03000 {
		compatible = "regulator-fixed";
		regulator-name = "mdss_core_gdsc";
		reg = <0xaf03000 0x4>;
		qcom,poll-cfg-gdscr;
		qcom,support-hw-trigger;
		status = "disabled";
		proxy-supply = <&mdss_core_gdsc>;
		qcom,proxy-consumer-enable;
		};

		/* GDSCs in Graphics CC */
		gpu_cx_hw_ctrl: syscon@5091540 {
		compatible = "syscon";
		reg = <0x5091540 0x4>;
		};

		gpu_cx_gdsc: qcom,gdsc@509106c {
		compatible = "regulator-fixed";
		regulator-name = "gpu_cx_gdsc";
		reg = <0x509106c 0x4>;
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		qcom,clk-dis-wait-val = <8>;
		status = "disabled";
		};

		gpu_gx_gdsc: qcom,gdsc@509100c {
		compatible = "regulator-fixed";
		regulator-name = "gpu_gx_gdsc";
		reg = <0x509100c 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
		};

		/* GDSCs in Video CC */
		mvsc_gdsc: qcom,gdsc@0b00814 {
		compatible = "regulator-fixed";
		regulator-name = "mvsc_gdsc";
		reg = <0xab00814 0x4>;
		status = "disabled";
		};

		mvs0_gdsc: qcom,gdsc@ab00874 {
		compatible = "regulator-fixed";
		regulator-name = "mvs0_gdsc";
		reg = <0xab00874 0x4>;
		status = "disabled";
		};

		mvs1_gdsc: qcom,gdsc@ab008b4 {
		compatible = "regulator-fixed";
		regulator-name = "mvs1_gdsc";
		reg = <0xab008b4 0x4>;
		status = "disabled";
		};

		/* GDSCs in NPU CC */
		npu_core_gdsc: qcom,gdsc@9911028 {
		compatible = "regulator-fixed";
		regulator-name = "npu_core_gdsc";
		reg = <0x9911028 0x4>;
		status = "disabled";
		};
		};

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

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		@@ -12,6 +12,13 @@

		#include "skeleton64.dtsi"
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/clock/qcom,gcc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,gpucc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,camcc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,videocc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,dispcc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,npucc-sdmmagpie.h>
		#include <dt-bindings/clock/qcom,rpmh.h>

		/ {
		model = "Qualcomm Technologies, Inc. SDMMAGPIE";
		@@ -400,6 +407,54 @@
		};
		};

		clock_rpmh: qcom,rpmh {
		compatible = "qcom,dummycc";
		clock-output-names = "rpm_clocks";
		#clock-cells = <1>;
		};

		clock_gcc: qcom,gcc {
		compatible = "qcom,dummycc";
		clock-output-names = "gcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		clock_camcc: qcom,camcc {
		compatible = "qcom,dummycc";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		clock_gpucc: qcom,gpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		clock_videocc: qcom,videocc {
		compatible = "qcom,dummycc";
		clock-output-names = "videocc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		clock_dispcc: qcom,dispcc {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		clock_npucc: qcom,npucc {
		compatible = "qcom,dummycc";
		clock-output-names = "npucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		@@ -647,3 +702,100 @@
		};

		#include "sdmmagpie-pinctrl.dtsi"
		#include "sdmmagpie-gdsc.dtsi"

		&pcie_0_gdsc {
		status = "ok";
		};

		&pcie_tbu_gdsc {
		status = "ok";
		};

		&usb30_prim_gdsc {
		status = "ok";
		};

		&ufs_phy_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
		status = "ok";
		};

		&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
		status = "ok";
		};

		&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
		status = "ok";
		};

		&bps_gdsc {
		status = "ok";
		};

		&ife_0_gdsc {
		status = "ok";
		};

		&ife_1_gdsc {
		status = "ok";
		};

		&ipe_0_gdsc {
		status = "ok";
		};

		&ipe_1_gdsc {
		status = "ok";
		};

		&titan_top_gdsc {
		status = "ok";
		};

		&mdss_core_gdsc {
		status = "ok";
		};

		&gpu_cx_gdsc {
		status = "ok";
		};

		&gpu_gx_gdsc {
		status = "ok";
		};

		&mvsc_gdsc {
		status = "ok";
		};

		&mvs0_gdsc {
		status = "ok";
		};

		&mvs1_gdsc {
		status = "ok";
		};

		&npu_core_gdsc {
		status = "ok";
		};

include/dt-bindings/clock/qcom,camcc-sdmmagpie.h

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		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SDMMAGPIE_H
		#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SDMMAGPIE_H

		#define CAM_CC_BPS_AHB_CLK 0
		#define CAM_CC_BPS_AREG_CLK 1
		#define CAM_CC_BPS_AXI_CLK 2
		#define CAM_CC_BPS_CLK 3
		#define CAM_CC_BPS_CLK_SRC 4
		#define CAM_CC_CAMNOC_AXI_CLK 5
		#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
		#define CAM_CC_CAMNOC_DCD_XO_CLK 7
		#define CAM_CC_CCI_0_CLK 8
		#define CAM_CC_CCI_0_CLK_SRC 9
		#define CAM_CC_CCI_1_CLK 10
		#define CAM_CC_CCI_1_CLK_SRC 11
		#define CAM_CC_CORE_AHB_CLK 12
		#define CAM_CC_CPAS_AHB_CLK 13
		#define CAM_CC_CPHY_RX_CLK_SRC 14
		#define CAM_CC_CSI0PHYTIMER_CLK 15
		#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16
		#define CAM_CC_CSI1PHYTIMER_CLK 17
		#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18
		#define CAM_CC_CSI2PHYTIMER_CLK 19
		#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20
		#define CAM_CC_CSI3PHYTIMER_CLK 21
		#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22
		#define CAM_CC_CSIPHY0_CLK 23
		#define CAM_CC_CSIPHY1_CLK 24
		#define CAM_CC_CSIPHY2_CLK 25
		#define CAM_CC_CSIPHY3_CLK 26
		#define CAM_CC_FAST_AHB_CLK_SRC 27
		#define CAM_CC_FD_CORE_CLK 28
		#define CAM_CC_FD_CORE_CLK_SRC 29
		#define CAM_CC_FD_CORE_UAR_CLK 30
		#define CAM_CC_GDSC_CLK 31
		#define CAM_CC_ICP_AHB_CLK 32
		#define CAM_CC_ICP_CLK 33
		#define CAM_CC_ICP_CLK_SRC 34
		#define CAM_CC_IFE_0_AXI_CLK 35
		#define CAM_CC_IFE_0_CLK 36
		#define CAM_CC_IFE_0_CLK_SRC 37
		#define CAM_CC_IFE_0_CPHY_RX_CLK 38
		#define CAM_CC_IFE_0_CSID_CLK 39
		#define CAM_CC_IFE_0_CSID_CLK_SRC 40
		#define CAM_CC_IFE_0_DSP_CLK 41
		#define CAM_CC_IFE_1_AXI_CLK 42
		#define CAM_CC_IFE_1_CLK 43
		#define CAM_CC_IFE_1_CLK_SRC 44
		#define CAM_CC_IFE_1_CPHY_RX_CLK 45
		#define CAM_CC_IFE_1_CSID_CLK 46
		#define CAM_CC_IFE_1_CSID_CLK_SRC 47
		#define CAM_CC_IFE_1_DSP_CLK 48
		#define CAM_CC_IFE_LITE_CLK 49
		#define CAM_CC_IFE_LITE_CLK_SRC 50
		#define CAM_CC_IFE_LITE_CPHY_RX_CLK 51
		#define CAM_CC_IFE_LITE_CSID_CLK 52
		#define CAM_CC_IFE_LITE_CSID_CLK_SRC 53
		#define CAM_CC_IPE_0_AHB_CLK 54
		#define CAM_CC_IPE_0_AREG_CLK 55
		#define CAM_CC_IPE_0_AXI_CLK 56
		#define CAM_CC_IPE_0_CLK 57
		#define CAM_CC_IPE_0_CLK_SRC 58
		#define CAM_CC_IPE_1_AHB_CLK 59
		#define CAM_CC_IPE_1_AREG_CLK 60
		#define CAM_CC_IPE_1_AXI_CLK 61
		#define CAM_CC_IPE_1_CLK 62
		#define CAM_CC_JPEG_CLK 63
		#define CAM_CC_JPEG_CLK_SRC 64
		#define CAM_CC_LRME_CLK 65
		#define CAM_CC_LRME_CLK_SRC 66
		#define CAM_CC_MCLK0_CLK 67
		#define CAM_CC_MCLK0_CLK_SRC 68
		#define CAM_CC_MCLK1_CLK 69
		#define CAM_CC_MCLK1_CLK_SRC 70
		#define CAM_CC_MCLK2_CLK 71
		#define CAM_CC_MCLK2_CLK_SRC 72
		#define CAM_CC_MCLK3_CLK 73
		#define CAM_CC_MCLK3_CLK_SRC 74
		#define CAM_CC_PLL0 75
		#define CAM_CC_PLL0_OUT_EVEN 76
		#define CAM_CC_PLL0_OUT_ODD 77
		#define CAM_CC_PLL1 78
		#define CAM_CC_PLL1_OUT_EVEN 79
		#define CAM_CC_PLL2 80
		#define CAM_CC_PLL2_OUT_AUX 81
		#define CAM_CC_PLL2_OUT_MAIN 82
		#define CAM_CC_PLL3 83
		#define CAM_CC_PLL3_OUT_EVEN 84
		#define CAM_CC_PLL4 85
		#define CAM_CC_PLL4_OUT_EVEN 86
		#define CAM_CC_PLL_TEST_CLK 87
		#define CAM_CC_QDSS_DEBUG_CLK 88
		#define CAM_CC_QDSS_DEBUG_CLK_SRC 89
		#define CAM_CC_QDSS_DEBUG_XO_CLK 90
		#define CAM_CC_SLEEP_CLK 91
		#define CAM_CC_SLEEP_CLK_SRC 92
		#define CAM_CC_SLOW_AHB_CLK_SRC 93
		#define CAM_CC_SPDM_BPS_CLK 94
		#define CAM_CC_SPDM_IFE_0_CLK 95
		#define CAM_CC_SPDM_IFE_0_CSID_CLK 96
		#define CAM_CC_SPDM_IPE_0_CLK 97
		#define CAM_CC_SPDM_IPE_1_CLK 98
		#define CAM_CC_SPDM_JPEG_CLK 99
		#define CAM_CC_XO_CLK_SRC 100

		#define BPS_GDSC 0
		#define IFE_0_GDSC 1
		#define IFE_1_GDSC 2
		#define IPE_0_GDSC 3
		#define IPE_1_GDSC 4
		#define TITAN_TOP_GDSC 5

		#endif

include/dt-bindings/clock/qcom,dispcc-sdmmagpie.h

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		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SDMMAGPIE_H
		#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SDMMAGPIE_H

		#define DISP_CC_DEBUG_CLK 0
		#define DISP_CC_MDSS_AHB_CLK 1
		#define DISP_CC_MDSS_AHB_CLK_SRC 2
		#define DISP_CC_MDSS_BYTE0_CLK 3
		#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
		#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
		#define DISP_CC_MDSS_BYTE1_CLK 6
		#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
		#define DISP_CC_MDSS_BYTE1_INTF_CLK 8
		#define DISP_CC_MDSS_DP_AUX_CLK 9
		#define DISP_CC_MDSS_DP_AUX_CLK_SRC 10
		#define DISP_CC_MDSS_DP_CRYPTO_CLK 11
		#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 12
		#define DISP_CC_MDSS_DP_LINK_CLK 13
		#define DISP_CC_MDSS_DP_LINK_CLK_SRC 14
		#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
		#define DISP_CC_MDSS_DP_PIXEL1_CLK 16
		#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 17
		#define DISP_CC_MDSS_DP_PIXEL_CLK 18
		#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 19
		#define DISP_CC_MDSS_ESC0_CLK 20
		#define DISP_CC_MDSS_ESC0_CLK_SRC 21
		#define DISP_CC_MDSS_ESC1_CLK 22
		#define DISP_CC_MDSS_ESC1_CLK_SRC 23
		#define DISP_CC_MDSS_MDP_CLK 24
		#define DISP_CC_MDSS_MDP_CLK_SRC 25
		#define DISP_CC_MDSS_MDP_LUT_CLK 26
		#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 27
		#define DISP_CC_MDSS_PCLK0_CLK 28
		#define DISP_CC_MDSS_PCLK0_CLK_SRC 29
		#define DISP_CC_MDSS_PCLK1_CLK 30
		#define DISP_CC_MDSS_PCLK1_CLK_SRC 31
		#define DISP_CC_MDSS_ROT_CLK 32
		#define DISP_CC_MDSS_ROT_CLK_SRC 33
		#define DISP_CC_MDSS_RSCC_AHB_CLK 34
		#define DISP_CC_MDSS_RSCC_VSYNC_CLK 35
		#define DISP_CC_MDSS_VSYNC_CLK 36
		#define DISP_CC_MDSS_VSYNC_CLK_SRC 37
		#define DISP_CC_PLL0 38
		#define DISP_CC_PLL_TEST_CLK 39
		#define DISP_CC_XO_CLK 40
		#define DISP_CC_XO_CLK_SRC 41

		#define MDSS_CORE_GDSC 0

		#endif

include/dt-bindings/clock/qcom,gcc-sdmmagpie.h

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		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDMMAGPIE_H
		#define _DT_BINDINGS_CLK_QCOM_GCC_SDMMAGPIE_H

		#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
		#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
		#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2
		#define GCC_APC_VS_CLK 3
		#define GCC_BOOT_ROM_AHB_CLK 4
		#define GCC_CAMERA_AHB_CLK 5
		#define GCC_CAMERA_HF_AXI_CLK 6
		#define GCC_CAMERA_SF_AXI_CLK 7
		#define GCC_CAMERA_XO_CLK 8
		#define GCC_CE1_AHB_CLK 9
		#define GCC_CE1_AXI_CLK 10
		#define GCC_CE1_CLK 11
		#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
		#define GCC_CPUSS_AHB_CLK 13
		#define GCC_CPUSS_AHB_CLK_SRC 14
		#define GCC_CPUSS_GNOC_CLK 15
		#define GCC_CPUSS_RBCPR_CLK 16
		#define GCC_CPUSS_RBCPR_CLK_SRC 17
		#define GCC_DDRSS_GPU_AXI_CLK 18
		#define GCC_DISP_AHB_CLK 19
		#define GCC_DISP_GPLL0_CLK_SRC 20
		#define GCC_DISP_GPLL0_DIV_CLK_SRC 21
		#define GCC_DISP_HF_AXI_CLK 22
		#define GCC_DISP_SF_AXI_CLK 23
		#define GCC_DISP_XO_CLK 24
		#define GCC_GP1_CLK 25
		#define GCC_GP1_CLK_SRC 26
		#define GCC_GP2_CLK 27
		#define GCC_GP2_CLK_SRC 28
		#define GCC_GP3_CLK 29
		#define GCC_GP3_CLK_SRC 30
		#define GCC_GPU_CFG_AHB_CLK 31
		#define GCC_GPU_GPLL0_CLK_SRC 32
		#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
		#define GCC_GPU_MEMNOC_GFX_CLK 34
		#define GCC_GPU_SNOC_DVM_GFX_CLK 35
		#define GCC_GPU_VS_CLK 36
		#define GCC_MSS_AXIS2_CLK 37
		#define GCC_MSS_CFG_AHB_CLK 38
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 39
		#define GCC_MSS_MFAB_AXIS_CLK 40
		#define GCC_MSS_Q6_MEMNOC_AXI_CLK 41
		#define GCC_MSS_SNOC_AXI_CLK 42
		#define GCC_MSS_VS_CLK 43
		#define GCC_NPU_AXI_CLK 44
		#define GCC_NPU_CFG_AHB_CLK 45
		#define GCC_NPU_GPLL0_CLK_SRC 46
		#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
		#define GCC_PCIE_0_AUX_CLK 48
		#define GCC_PCIE_0_AUX_CLK_SRC 49
		#define GCC_PCIE_0_CFG_AHB_CLK 50
		#define GCC_PCIE_0_MSTR_AXI_CLK 51
		#define GCC_PCIE_0_PIPE_CLK 52
		#define GCC_PCIE_0_SLV_AXI_CLK 53
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 54
		#define GCC_PCIE_PHY_AUX_CLK 55
		#define GCC_PCIE_PHY_REFGEN_CLK 56
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 57
		#define GCC_PDM2_CLK 58
		#define GCC_PDM2_CLK_SRC 59
		#define GCC_PDM_AHB_CLK 60
		#define GCC_PDM_XO4_CLK 61
		#define GCC_PRNG_AHB_CLK 62
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 63
		#define GCC_QUPV3_WRAP0_CORE_CLK 64
		#define GCC_QUPV3_WRAP0_S0_CLK 65
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 66
		#define GCC_QUPV3_WRAP0_S1_CLK 67
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 68
		#define GCC_QUPV3_WRAP0_S2_CLK 69
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 70
		#define GCC_QUPV3_WRAP0_S3_CLK 71
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 72
		#define GCC_QUPV3_WRAP0_S4_CLK 73
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 74
		#define GCC_QUPV3_WRAP0_S5_CLK 75
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 76
		#define GCC_QUPV3_WRAP0_S6_CLK 77
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 78
		#define GCC_QUPV3_WRAP0_S7_CLK 79
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 80
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 81
		#define GCC_QUPV3_WRAP1_CORE_CLK 82
		#define GCC_QUPV3_WRAP1_S0_CLK 83
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 84
		#define GCC_QUPV3_WRAP1_S1_CLK 85
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 86
		#define GCC_QUPV3_WRAP1_S2_CLK 87
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 88
		#define GCC_QUPV3_WRAP1_S3_CLK 89
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 90
		#define GCC_QUPV3_WRAP1_S4_CLK 91
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 92
		#define GCC_QUPV3_WRAP1_S5_CLK 93
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 94
		#define GCC_QUPV3_WRAP1_S6_CLK 95
		#define GCC_QUPV3_WRAP1_S6_CLK_SRC 96
		#define GCC_QUPV3_WRAP1_S7_CLK 97
		#define GCC_QUPV3_WRAP1_S7_CLK_SRC 98
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 99
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 100
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 101
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 102
		#define GCC_SDCC1_AHB_CLK 103
		#define GCC_SDCC1_APPS_CLK 104
		#define GCC_SDCC1_APPS_CLK_SRC 105
		#define GCC_SDCC1_ICE_CORE_CLK 106
		#define GCC_SDCC1_ICE_CORE_CLK_SRC 107
		#define GCC_SDCC2_AHB_CLK 108
		#define GCC_SDCC2_APPS_CLK 109
		#define GCC_SDCC2_APPS_CLK_SRC 110
		#define GCC_SDCC4_AHB_CLK 111
		#define GCC_SDCC4_APPS_CLK 112
		#define GCC_SDCC4_APPS_CLK_SRC 113
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 114
		#define GCC_TSIF_AHB_CLK 115
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 116
		#define GCC_TSIF_REF_CLK 117
		#define GCC_TSIF_REF_CLK_SRC 118
		#define GCC_UFS_PHY_AHB_CLK 119
		#define GCC_UFS_PHY_AXI_CLK 120
		#define GCC_UFS_PHY_AXI_CLK_SRC 121
		#define GCC_UFS_PHY_ICE_CORE_CLK 122
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 123
		#define GCC_UFS_PHY_PHY_AUX_CLK 124
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 125
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 126
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 127
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 128
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 129
		#define GCC_USB30_PRIM_MASTER_CLK 130
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 131
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 132
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 133
		#define GCC_USB30_PRIM_SLEEP_CLK 134
		#define GCC_USB3_PRIM_PHY_AUX_CLK 135
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 138
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 139
		#define GCC_VDDA_VS_CLK 140
		#define GCC_VDDCX_VS_CLK 141
		#define GCC_VDDMX_VS_CLK 142
		#define GCC_VIDEO_AHB_CLK 143
		#define GCC_VIDEO_AXI_CLK 144
		#define GCC_VIDEO_XO_CLK 145
		#define GCC_VS_CTRL_AHB_CLK 146
		#define GCC_VS_CTRL_CLK 147
		#define GCC_VS_CTRL_CLK_SRC 148
		#define GCC_VSENSOR_CLK_SRC 149
		#define GPLL0 150
		#define GPLL0_OUT_EVEN 151
		#define GPLL6 152
		#define GPLL7 153
		#define GCC_USB3_PRIM_CLKREF_CLK 154

		#define PCIE_0_GDSC 0
		#define PCIE_TBU_GDSC 1
		#define UFS_PHY_GDSC 2
		#define USB30_PRIM_GDSC 3

		#define GCC_PCIE_0_BCR 1
		#define GCC_PCIE_PHY_BCR 2
		#define GCC_UFS_PHY_BCR 3
		#define GCC_USB30_PRIM_BCR 4

		#endif