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Commit 4e74ae80 authored by David S. Miller's avatar David S. Miller
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[SPARC64]: Handle unimplemented FPU square-root on Niagara.



The math-emu code only expects unfinished fpop traps when
emulating FPU sqrt instructions on pre-Niagara chips.
On Niagara we can get unimplemented fpop, so handle that.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f5deb807
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+23 −2
Original line number Original line Diff line number Diff line
@@ -206,9 +206,30 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f)
			case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
			case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
			case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
			case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
			case FQTOI: TYPE(3,1,0,3,1,0,0); break;
			case FQTOI: TYPE(3,1,0,3,1,0,0); break;

			/* We can get either unimplemented or unfinished
			 * for these cases.  Pre-Niagara systems generate
			 * unfinished fpop for SUBNORMAL cases, and Niagara
			 * always gives unimplemented fpop for fsqrt{s,d}.
			 */
			case FSQRTS: {
				unsigned long x = current_thread_info()->xfsr[0];

				x = (x >> 14) & 0xf;
				TYPE(x,1,1,1,1,0,0);
				printk("math-emu: type is %08x\n", type);
				break;
			}

			case FSQRTD: {
				unsigned long x = current_thread_info()->xfsr[0];

				x = (x >> 14) & 0xf;
				TYPE(x,2,1,2,1,0,0);
				break;
			}

			/* SUBNORMAL - ftt == 2 */
			/* SUBNORMAL - ftt == 2 */
			case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
			case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
			case FADDD:
			case FADDD:
			case FSUBD:
			case FSUBD:
			case FMULD:
			case FMULD: