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Commit 4dfc0505 authored by Marc Zyngier's avatar Marc Zyngier
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KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass 



Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to
zero, which implies that there is a way to bypass the GIC and
inject raw IRQ/FIQ by driving the CPU pins.

Of course, we don't allow that when the GIC is configured, but
we fail to indicate that to the guest. The obvious fix is to
set these bits (and never let them being changed again).

Reported-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Acked-by: default avatarChristoffer Dall <cdall@linaro.org>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 68925176

include/linux/irqchip/arm-gic-v3.h

+2 −0
Original line number Diff line number Diff line
@@ -373,6 +373,8 @@ 
#define ICC_IGRPEN0_EL1_MASK		(1 << ICC_IGRPEN0_EL1_SHIFT)

#define ICC_IGRPEN1_EL1_SHIFT		0

#define ICC_IGRPEN1_EL1_MASK		(1 << ICC_IGRPEN1_EL1_SHIFT)

#define ICC_SRE_EL1_DIB			(1U << 2)

#define ICC_SRE_EL1_DFB			(1U << 1)

#define ICC_SRE_EL1_SRE			(1U << 0)



/*

virt/kvm/arm/vgic/vgic-v3.c

+4 −1
Original line number Diff line number Diff line
@@ -229,10 +229,13 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) 
	/*

	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible

	 * way, so we force SRE to 1 to demonstrate this to the guest.

	 * Also, we don't support any form of IRQ/FIQ bypass.

	 * This goes with the spec allowing the value to be RAO/WI.

	 */

	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {

		vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;

		vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |

				     ICC_SRE_EL1_DFB |

				     ICC_SRE_EL1_SRE);

		vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;

	} else {

		vgic_v3->vgic_sre = 0;