Loading Documentation/devicetree/bindings/dma/qcom-pci-edma.txt 0 → 100644 +79 −0 Original line number Diff line number Diff line Qualcomm Technologies Inc PCIe eDMA controller QCOM PCIe eDMA controller provides DMA capabilities for peripheral connected and uses PCIe to transfer data. ============== Node Structure ============== Main node properties: - compatible Usage: required Value type: <string> Definition: "qcom,pci-edma" - #dma-cells Usage: required Value type: <u32> Definition: Number of parameters client will provide. Must be set to 2. 1st parameter: channel index, 0 for TX, 1 for RX 2nd parameter: event processing priority, set to 0 for highest priority - reg Usage: required Value type: Array (2-cell) of <u32> Definition: First cell is eDMA register base address. Second cell is size of eDMA register space. - interrupts Usage: required Value type: Array of <u32> Definition: Array of tuples which describe interrupt lines for eDMA. - interrupts-names Usage: required Value type: Array of <u32> Definition: Array of names which map to interrupt lines for eDMA. - interrupt-parent Usage: required Value type: <phandle> Definition: phandle of the interrupt controller that services interrupts for this device - qcom,n-tl-init Usage: optional Value type: <u32> Definition: Number of transfer and descriptor arrays to start with. If this entry is not presetn, default value is 2. - qcom,n-tl-ele Usage: optional Value type: <u32> Definition: Number of elements for each transfer and descriptor array. If this entry is not present, default value is 1024. - qcom,n-max-ev-ch Usage: optional Value type: <u32> Definition: Total number of virtual (client) eDMA channels available. If this entry is not present, default value is 32. ======= Example ======= pci_edma: qcom,pci-edma@40002000 { compatible = "qcom,pci-edma"; #dma-cells = <2>; reg = <0x40002000 0x2000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pci-edma-int"; interrupt-parent = <&intc>; qcom,n-max-ev-ch = <32>; qcom,n-tl-init = <2>; qcom,n-tl-ele = <1024>; status = "ok"; }; arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -597,4 +597,13 @@ <GIC_SPI 830 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 831 IRQ_TYPE_EDGE_RISING>; }; pcie1_edma: qcom,pcie1_edma@40002000 { compatible = "qcom,pci-edma"; #dma-cells = <2>; reg = <0x40002000 0x2000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pci-edma-int"; }; }; drivers/dma/qcom/Kconfig +18 −0 Original line number Diff line number Diff line Loading @@ -46,3 +46,21 @@ config QCOM_GPI_DMA_DEBUG help Enable detailed logging for QCOM GPI driver. Extra logging will be helpful when debugging critical issues. config QCOM_PCI_EDMA tristate "Qualcomm Technologies Inc PCIe eDMA support" select DMA_ENGINE help Enable support for the QCOM PCIe eDMA. This DMA is part of QCOM PCIe controller that provides DMA capabilities for clients. By using PCIe eDMA driver, clients can use a standardize interface that is protocol independent to transfer data between DDR and peripheral. config QCOM_PCI_EDMA_DEBUG bool "Qualcomm Technologies Inc PCIe eDMA debug support" depends on QCOM_PCI_EDMA help Enable detailed logging for QCOM PCIe eDMA driver. Should only be enabled for debugging purpose since excessive logging of all channels information and activity will decrease throughput. drivers/dma/qcom/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -5,3 +5,4 @@ hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o obj-$(CONFIG_QCOM_HIDMA) += hdma.o hdma-objs := hidma_ll.o hidma.o hidma_dbg.o obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o obj-$(CONFIG_QCOM_PCI_EDMA) += pci-edma.o Loading
Documentation/devicetree/bindings/dma/qcom-pci-edma.txt 0 → 100644 +79 −0 Original line number Diff line number Diff line Qualcomm Technologies Inc PCIe eDMA controller QCOM PCIe eDMA controller provides DMA capabilities for peripheral connected and uses PCIe to transfer data. ============== Node Structure ============== Main node properties: - compatible Usage: required Value type: <string> Definition: "qcom,pci-edma" - #dma-cells Usage: required Value type: <u32> Definition: Number of parameters client will provide. Must be set to 2. 1st parameter: channel index, 0 for TX, 1 for RX 2nd parameter: event processing priority, set to 0 for highest priority - reg Usage: required Value type: Array (2-cell) of <u32> Definition: First cell is eDMA register base address. Second cell is size of eDMA register space. - interrupts Usage: required Value type: Array of <u32> Definition: Array of tuples which describe interrupt lines for eDMA. - interrupts-names Usage: required Value type: Array of <u32> Definition: Array of names which map to interrupt lines for eDMA. - interrupt-parent Usage: required Value type: <phandle> Definition: phandle of the interrupt controller that services interrupts for this device - qcom,n-tl-init Usage: optional Value type: <u32> Definition: Number of transfer and descriptor arrays to start with. If this entry is not presetn, default value is 2. - qcom,n-tl-ele Usage: optional Value type: <u32> Definition: Number of elements for each transfer and descriptor array. If this entry is not present, default value is 1024. - qcom,n-max-ev-ch Usage: optional Value type: <u32> Definition: Total number of virtual (client) eDMA channels available. If this entry is not present, default value is 32. ======= Example ======= pci_edma: qcom,pci-edma@40002000 { compatible = "qcom,pci-edma"; #dma-cells = <2>; reg = <0x40002000 0x2000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pci-edma-int"; interrupt-parent = <&intc>; qcom,n-max-ev-ch = <32>; qcom,n-tl-init = <2>; qcom,n-tl-ele = <1024>; status = "ok"; };
arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -597,4 +597,13 @@ <GIC_SPI 830 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 831 IRQ_TYPE_EDGE_RISING>; }; pcie1_edma: qcom,pcie1_edma@40002000 { compatible = "qcom,pci-edma"; #dma-cells = <2>; reg = <0x40002000 0x2000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pci-edma-int"; }; };
drivers/dma/qcom/Kconfig +18 −0 Original line number Diff line number Diff line Loading @@ -46,3 +46,21 @@ config QCOM_GPI_DMA_DEBUG help Enable detailed logging for QCOM GPI driver. Extra logging will be helpful when debugging critical issues. config QCOM_PCI_EDMA tristate "Qualcomm Technologies Inc PCIe eDMA support" select DMA_ENGINE help Enable support for the QCOM PCIe eDMA. This DMA is part of QCOM PCIe controller that provides DMA capabilities for clients. By using PCIe eDMA driver, clients can use a standardize interface that is protocol independent to transfer data between DDR and peripheral. config QCOM_PCI_EDMA_DEBUG bool "Qualcomm Technologies Inc PCIe eDMA debug support" depends on QCOM_PCI_EDMA help Enable detailed logging for QCOM PCIe eDMA driver. Should only be enabled for debugging purpose since excessive logging of all channels information and activity will decrease throughput.
drivers/dma/qcom/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -5,3 +5,4 @@ hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o obj-$(CONFIG_QCOM_HIDMA) += hdma.o hdma-objs := hidma_ll.o hidma.o hidma_dbg.o obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o obj-$(CONFIG_QCOM_PCI_EDMA) += pci-edma.o
