iommu: arm-smmu: Add fault syndrome register-1 support

The context bank Fault Syndrome Register 1, FSYNR1 is implementation
defined. Add support for printing the FSYNR1 info during context fault.
For targets that has this register unimplemented, the CPU read is RAZ.
This can be interpreted as 'unimplemented' with the known knowledge that
FSYNR1 is not implemented on the current target in use.

Change-Id: Icb831a074511365af64bd3ab635fed15c2e53224
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>