Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

NVIDIA Tegra Power Management Controller (PMC)

NVIDIA Tegra Power Management Controller (PMC)

== Power Management Controller Node ==

The PMC block interacts with an external Power Management Unit. The PMC

The PMC block interacts with an external Power Management Unit. The PMC

mostly controls the entry and exit of the system from different sleep

mostly controls the entry and exit of the system from different sleep

modes. It provides power-gating controllers for SoC and CPU power-islands.

modes. It provides power-gating controllers for SoC and CPU power-islands.

Required properties:

Required properties:

- name : Should be pmc

- name : Should be pmc

- compatible : For Tegra20, must contain "nvidia,tegra20-pmc".  For Tegra30,

- compatible : Should contain one of the following:

  must contain "nvidia,tegra30-pmc".  For Tegra114, must contain

	For Tegra20 must contain "nvidia,tegra20-pmc".

  "nvidia,tegra114-pmc".  For Tegra124, must contain "nvidia,tegra124-pmc".

	For Tegra30 must contain "nvidia,tegra30-pmc".

  Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the

	For Tegra114 must contain "nvidia,tegra114-pmc"

  above, where <chip> is tegra132.

	For Tegra124 must contain "nvidia,tegra124-pmc"

	For Tegra132 must contain "nvidia,tegra124-pmc"

	For Tegra210 must contain "nvidia,tegra210-pmc"

- reg : Offset and length of the register set for the device

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

  See ../clocks/clock-bindings.txt for details.

                     Defaults to 0. Valid values are described in section 12.5.2

                     Defaults to 0. Valid values are described in section 12.5.2

                     "Pinmux Support" of the Tegra4 Technical Reference Manual.

                     "Pinmux Support" of the Tegra4 Technical Reference Manual.

Optional nodes:

- powergates : This node contains a hierarchy of power domain nodes, which

	       should match the powergates on the Tegra SoC. See "Powergate

	       Nodes" below.

Example:

Example:

/ SoC dts including file

/ SoC dts including file

	};

	};

	...

	...

};

};

== Powergate Nodes ==

Each of the powergate nodes represents a power-domain on the Tegra SoC

that can be power-gated by the Tegra PMC. The name of the powergate node

should be one of the below. Note that not every powergate is applicable

to all Tegra devices and the following list shows which powergates are

applicable to which devices. Please refer to the Tegra TRM for more

details on the various powergates.

 Name		Description			Devices Applicable

 3d		3D Graphics			Tegra20/114/124/210

 3d0		3D Graphics 0			Tegra30

 3d1		3D Graphics 1			Tegra30

 aud		Audio				Tegra210

 dfd		Debug				Tegra210

 dis		Display A			Tegra114/124/210

 disb		Display B			Tegra114/124/210

 heg		2D Graphics			Tegra30/114/124/210

 iram		Internal RAM			Tegra124/210

 mpe		MPEG Encode			All

 nvdec		NVIDIA Video Decode Engine	Tegra210

 nvjpg		NVIDIA JPEG Engine		Tegra210

 pcie		PCIE				Tegra20/30/124/210

 sata		SATA				Tegra30/124/210

 sor		Display interfaces		Tegra124/210

 ve2		Video Encode Engine 2		Tegra210

 venc		Video Encode Engine		All

 vdec		Video Decode Engine		Tegra20/30/114/124

 vic		Video Imaging Compositor	Tegra124/210

 xusba		USB Partition A			Tegra114/124/210

 xusbb		USB Partition B 		Tegra114/124/210

 xusbc		USB Partition C			Tegra114/124/210

Required properties:

  - clocks: Must contain an entry for each clock required by the PMC for

    controlling a power-gate. See ../clocks/clock-bindings.txt for details.

  - resets: Must contain an entry for each reset required by the PMC for

    controlling a power-gate. See ../reset/reset.txt for details.

  - #power-domain-cells: Must be 0.

Example:

	pmc: pmc@7000e400 {

		compatible = "nvidia,tegra210-pmc";

		reg = <0x0 0x7000e400 0x0 0x400>;

		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;

		clock-names = "pclk", "clk32k_in";

		powergates {

			pd_audio: aud {

				clocks = <&tegra_car TEGRA210_CLK_APE>,

					 <&tegra_car TEGRA210_CLK_APB2APE>;

				resets = <&tegra_car 198>;

				#power-domain-cells = <0>;

			};

		};

	};

== Powergate Clients ==

Hardware blocks belonging to a power domain should contain a "power-domains"

property that is a phandle pointing to the corresponding powergate node.

Example:

	adma: adma@702e2000 {

		...

		power-domains = <&pd_audio>;

		...

	};

SAMSUNG Exynos SoCs SROM Controller driver.

Required properties:

- compatible : Should contain "samsung,exynos4210-srom".

- reg: offset and length of the register set

Optional properties:

The SROM controller can be used to attach external peripherals. In this case

extra properties, describing the bus behind it, should be specified as below:

- #address-cells: Must be set to 2 to allow device address translation.

		  Address is specified as (bank#, offset).

- #size-cells: Must be set to 1 to allow device size passing

- ranges: Must be set up to reflect the memory layout with four integer values

	  per bank:

		<bank-number> 0 <parent address of bank> <size>

Sub-nodes:

The actual device nodes should be added as subnodes to the SROMc node. These

subnodes, in addition to regular device specification, should contain the following

properties, describing configuration of the relevant SROM bank:

Required properties:

- reg: bank number, base address (relative to start of the bank) and size of

       the memory mapped for the device. Note that base address will be

       typically 0 as this is the start of the bank.

- samsung,srom-timing : array of 6 integers, specifying bank timings in the

                        following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.

                        Each value is specified in cycles and has the following

                        meaning and valid range:

                        Tacp : Page mode access cycle at Page mode (0 - 15)

                        Tcah : Address holding time after CSn (0 - 15)

                        Tcoh : Chip selection hold on OEn (0 - 15)

                        Tacc : Access cycle (0 - 31, the actual time is N + 1)

                        Tcos : Chip selection set-up before OEn (0 - 15)

                        Tacs : Address set-up before CSn (0 - 15)

Optional properties:

- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used.

- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured,

			   else normal (1 data) page mode will be set.

Example: basic definition, no banks are configured

	memory-controller@12570000 {

		compatible = "samsung,exynos4210-srom";

		reg = <0x12570000 0x14>;

	};

Example: SROMc with SMSC911x ethernet chip on bank 3

	memory-controller@12570000 {

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x04000000 0x20000   // Bank0

			  1 0 0x05000000 0x20000   // Bank1

			  2 0 0x06000000 0x20000   // Bank2

			  3 0 0x07000000 0x20000>; // Bank3

		compatible = "samsung,exynos4210-srom";

		reg = <0x12570000 0x14>;

		ethernet@3,0 {

			compatible = "smsc,lan9115";

			reg = <3 0 0x10000>;	   // Bank 3, offset = 0

			phy-mode = "mii";

			interrupt-parent = <&gpx0>;

			interrupts = <5 8>;

			reg-io-width = <2>;

			smsc,irq-push-pull;

			smsc,force-internal-phy;

			samsung,srom-page-mode;

			samsung,srom-timing = <9 12 1 9 1 1>;

		};

	};

Flash device on ARM Versatile board

Flash device on ARM Versatile board

These flash chips are found in the ARM reference designs like Integrator,

Versatile, RealView, Versatile Express etc.

They are regular CFI compatible (Intel or AMD extended) flash chips with

some special write protect/VPP bits that can be controlled by the machine's

system controller.

Required properties:

Required properties:

- compatible : must be "arm,versatile-flash";

- compatible : must be "arm,versatile-flash", "cfi-flash";

- reg : memory address for the flash chip

- bank-width : width in bytes of flash interface.

- bank-width : width in bytes of flash interface.

For the rest of the properties, see mtd-physmap.txt.

The device tree may optionally contain sub-nodes describing partitions of the

The device tree may optionally contain sub-nodes describing partitions of the

address space. See partition.txt for more detail.

address space. See partition.txt for more detail.

Example:

flash@34000000 {

	compatible = "arm,versatile-flash", "cfi-flash";

	reg = <0x34000000 0x4000000>;

	bank-width = <4>;

};

  - afi

  - afi

  - pcie_x

  - pcie_x

Required properties on Tegra124 and later:

Required properties on Tegra124 and later (deprecated):

- phys: Must contain an entry for each entry in phy-names.

- phys: Must contain an entry for each entry in phy-names.

- phy-names: Must include the following entries:

- phy-names: Must include the following entries:

  - pcie

  - pcie

These properties are deprecated in favour of per-lane PHYs define in each of

the root ports (see below).

Power supplies for Tegra20:

Power supplies for Tegra20:

- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

  - Root port 0 uses 4 lanes, root port 1 is unused.

  - Root port 0 uses 4 lanes, root port 1 is unused.

  - Both root ports use 2 lanes.

  - Both root ports use 2 lanes.

Example:

Required properties for Tegra124 and later:

- phys: Must contain an phandle to a PHY for each entry in phy-names.

- phy-names: Must include an entry for each active lane. Note that the number

  of entries does not have to (though usually will) be equal to the specified

  number of lanes in the nvidia,num-lanes property. Entries are of the form

  "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.

Examples:

=========

Tegra20:

--------

SoC DTSI:

SoC DTSI:

	pcie-controller {

	pcie-controller@80003000 {

		compatible = "nvidia,tegra20-pcie";

		compatible = "nvidia,tegra20-pcie";

		device_type = "pci";

		device_type = "pci";

		reg = <0x80003000 0x00000800   /* PADS registers */

		reg = <0x80003000 0x00000800   /* PADS registers */

		};

		};

	};

	};

Board DTS:

Board DTS:

	pcie-controller {

	pcie-controller@80003000 {

		status = "okay";

		status = "okay";

		vdd-supply = <&pci_vdd_reg>;

		vdd-supply = <&pci_vdd_reg>;

device nodes need to be added in order to allow the bus' children to be

device nodes need to be added in order to allow the bus' children to be

instantiated at the proper location in the operating system's device tree (as

instantiated at the proper location in the operating system's device tree (as

illustrated by the optional nodes in the example above).

illustrated by the optional nodes in the example above).

Tegra30:

--------

SoC DTSI:

	pcie-controller@00003000 {

		compatible = "nvidia,tegra30-pcie";

		device_type = "pci";

		reg = <0x00003000 0x00000800   /* PADS registers */

		       0x00003800 0x00000200   /* AFI registers */

		       0x10000000 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */

			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */

			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */

			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */

			  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */

		clocks = <&tegra_car TEGRA30_CLK_PCIE>,

			 <&tegra_car TEGRA30_CLK_AFI>,

			 <&tegra_car TEGRA30_CLK_PLL_E>,

			 <&tegra_car TEGRA30_CLK_CML0>;

		clock-names = "pex", "afi", "pll_e", "cml";

		resets = <&tegra_car 70>,

			 <&tegra_car 72>,

			 <&tegra_car 74>;

		reset-names = "pex", "afi", "pcie_x";

		status = "disabled";

		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

		pci@3,0 {

			device_type = "pci";

			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;

			reg = <0x001800 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

	};

Board DTS:

	pcie-controller@00003000 {

		status = "okay";

		avdd-pexa-supply = <&ldo1_reg>;

		vdd-pexa-supply = <&ldo1_reg>;

		avdd-pexb-supply = <&ldo1_reg>;

		vdd-pexb-supply = <&ldo1_reg>;

		avdd-pex-pll-supply = <&ldo1_reg>;

		avdd-plle-supply = <&ldo1_reg>;

		vddio-pex-ctl-supply = <&sys_3v3_reg>;

		hvdd-pex-supply = <&sys_3v3_pexs_reg>;

		pci@1,0 {

			status = "okay";

		};

		pci@3,0 {

			status = "okay";

		};

	};

Tegra124:

---------

SoC DTSI:

	pcie-controller@01003000 {

		compatible = "nvidia,tegra124-pcie";

		device_type = "pci";

		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */

		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */

		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */

			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */

			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */

			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

		clocks = <&tegra_car TEGRA124_CLK_PCIE>,

			 <&tegra_car TEGRA124_CLK_AFI>,

			 <&tegra_car TEGRA124_CLK_PLL_E>,

			 <&tegra_car TEGRA124_CLK_CML0>;

		clock-names = "pex", "afi", "pll_e", "cml";

		resets = <&tegra_car 70>,

			 <&tegra_car 72>,

			 <&tegra_car 74>;

		reset-names = "pex", "afi", "pcie_x";

		status = "disabled";

		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;

		};

		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";

			#address-cells = <3>;

			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <1>;

		};

	};

Board DTS:

	pcie-controller@01003000 {

		status = "okay";

		avddio-pex-supply = <&vdd_1v05_run>;

		dvddio-pex-supply = <&vdd_1v05_run>;

		avdd-pex-pll-supply = <&vdd_1v05_run>;

		hvdd-pex-supply = <&vdd_3v3_lp0>;

		hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;

		vddio-pex-ctl-supply = <&vdd_3v3_lp0>;

		avdd-pll-erefe-supply = <&avdd_1v05_run>;

		/* Mini PCIe */

		pci@1,0 {

			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;

			phy-names = "pcie-0";

			status = "okay";

		};

		/* Gigabit Ethernet */

		pci@2,0 {

			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;

			phy-names = "pcie-0";

			status = "okay";

		};

	};