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Commit 49d9684a authored by Kleber Sacilotto de Souza's avatar Kleber Sacilotto de Souza Committed by Benjamin Herrenschmidt
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powerpc/pseries: Add Gen3 definitions for PCIE link speed 



Rev3 of the PCI Express Base Specification defines a Supported Link
Speeds Vector where the bit definitions within this field are:

Bit 0 - 2.5 GT/s
Bit 1 - 5.0 GT/s
Bit 2 - 8.0 GT/s

This vector definition is used by the platform firmware to export the
maximum and current link speeds of the PCI bus via the
"ibm,pcie-link-speed-stats" device-tree property.

This patch updates pseries_root_bridge_prepare() to detect Gen3
speed buses (defined by 0x04).

Signed-off-by: default avatarKleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent b020cc6c

arch/powerpc/platforms/pseries/pci.c

+6 −0
Original line number Diff line number Diff line
@@ -144,6 +144,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) 
	case 0x02:

		bus->max_bus_speed = PCIE_SPEED_5_0GT;

		break;

	case 0x04:

		bus->max_bus_speed = PCIE_SPEED_8_0GT;

		break;

	default:

		bus->max_bus_speed = PCI_SPEED_UNKNOWN;

		break;
@@ -156,6 +159,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) 
	case 0x02:

		bus->cur_bus_speed = PCIE_SPEED_5_0GT;

		break;

	case 0x04:

		bus->cur_bus_speed = PCIE_SPEED_8_0GT;

		break;

	default:

		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;

		break;