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Commit 478143ff authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: add support for configurable PCIe core preset 



The PCIe core preset determines how aggressive PCIe PHY Gen3
equalization is. Based on the distance between SoC and PCIe
core, this setting needs to be tuned. Add support to tune
this value.

Change-Id: I1aee056cf1a81e96c2ece2c576cf27c0767f3a97
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent eac6c82e

drivers/pci/controller/pci-msm.c

+12 −1
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define PCIE20_PARF_DBI_BASE_ADDR (0x350)

#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE (0x358)



#define PCIE_GEN3_PRESET_DEFAULT (0x55555555)

#define PCIE_GEN3_SPCIE_CAP (0x0154)

#define PCIE_GEN3_GEN2_CTRL (0x080c)

#define PCIE_GEN3_RELATED (0x0890)
@@ -715,6 +716,7 @@ struct msm_pcie_dev_t { 
	uint32_t phy_status_offset;

	uint32_t phy_status_bit;

	uint32_t phy_power_down_offset;

	uint32_t core_preset;

	uint32_t cpl_timeout;

	uint32_t current_bdf;

	uint32_t perst_delay_us_min;
@@ -1372,6 +1374,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->phy_status_bit);

	PCIE_DBG_FS(dev, "phy_power_down_offset: 0x%x\n",

		dev->phy_power_down_offset);

	PCIE_DBG_FS(dev, "core_preset: 0x%x\n",

		dev->core_preset);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",

		dev->cpl_timeout);

	PCIE_DBG_FS(dev, "current_bdf: 0x%x\n",
@@ -4088,7 +4092,7 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev) 
	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 1);

	msm_pcie_write_reg(dev->dm_core,

		PCIE_GEN3_SPCIE_CAP, 0x77777777);

		PCIE_GEN3_SPCIE_CAP, dev->core_preset);

	msm_pcie_write_reg_field(dev->dm_core,

		PCIE_GEN3_MISC_CONTROL, BIT(0), 0);
@@ -6129,6 +6133,13 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	PCIE_DBG(pcie_dev, "RC%d: phy-power-down-offset: 0x%x.\n",

		pcie_dev->rc_idx, pcie_dev->phy_power_down_offset);



	pcie_dev->core_preset = PCIE_GEN3_PRESET_DEFAULT;

	of_property_read_u32(pdev->dev.of_node,

				"qcom,core-preset",

				&pcie_dev->core_preset);

	PCIE_DBG(pcie_dev, "RC%d: core-preset: 0x%x.\n",

		pcie_dev->rc_idx, pcie_dev->core_preset);



	of_property_read_u32(of_node, "qcom,cpl-timeout",

				&pcie_dev->cpl_timeout);

	PCIE_DBG(pcie_dev, "RC%d: cpl-timeout: 0x%x.\n",