Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 472f291d authored by Mark Mason's avatar Mark Mason Committed by Ralf Baechle
Browse files

[MIPS] Fix compilation warnings in arch/mips/sibyte/bcm1480/smp.c 



Signed-off-by: default avatarMark Mason <mason@broadcom.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9b95e629

arch/mips/sibyte/bcm1480/smp.c

+3 −3
Original line number Diff line number Diff line
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); 
 * independent of board/firmware

 */



static void *mailbox_0_set_regs[] = {

static volatile void *mailbox_0_set_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

};



static void *mailbox_0_clear_regs[] = {

static volatile void *mailbox_0_clear_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

};



static void *mailbox_0_regs[] = {

static volatile void *mailbox_0_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),