Loading sound/soc/codecs/wm8994.c +2 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,8 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, WM8994_FLL1_ENA | WM8994_FLL1_FRAC, reg); msleep(5); } wm8994->fll[id].in = freq_in; Loading sound/soc/tegra/tegra_i2s.c +6 −0 Original line number Diff line number Diff line Loading @@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, if (i2sclock % (2 * srate)) reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; if (!i2s->clk_refs) clk_enable(i2s->clk_i2s); tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); if (!i2s->clk_refs) clk_disable(i2s->clk_i2s); return 0; } Loading Loading
sound/soc/codecs/wm8994.c +2 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,8 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, WM8994_FLL1_ENA | WM8994_FLL1_FRAC, reg); msleep(5); } wm8994->fll[id].in = freq_in; Loading
sound/soc/tegra/tegra_i2s.c +6 −0 Original line number Diff line number Diff line Loading @@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream, if (i2sclock % (2 * srate)) reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE; if (!i2s->clk_refs) clk_enable(i2s->clk_i2s); tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg); tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR, TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS | TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS); if (!i2s->clk_refs) clk_disable(i2s->clk_i2s); return 0; } Loading